[PULL 0/2] target-arm queue
[PULL v2 00/21] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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no changes to v1, except adding the CVE identifier to one of the commit
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we were using uninitialized data for the guarded bit when
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messages.
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit cf7ca7d5b9faca13f1f8e3ea92cfb2f741eb0c0e:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2021-02-01 16:28:00 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210203
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to fd8f71b95da86f530aae3d02a14b0ccd9e024772:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/arm: Display CPU type in machine description (2021-02-03 10:15:51 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* hw/intc/arm_gic: Allow to use QTest without crashing
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* hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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* hw/char/exynos4210_uart: Fix missing call to report ready for input
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* hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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* hw/ssi/imx_spi: Fix various minor bugs
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* hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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* hw/arm: Add missing Kconfig dependencies
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* hw/arm: Display CPU type in machine description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Bin Meng (5):
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target/arm: PTE bit GP only applies to stage1
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hw/ssi: imx_spi: Use a macro for number of chip selects supported
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()
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hw/ssi: imx_spi: Round up the burst length to be multiple of 8
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hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
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hw/ssi: imx_spi: Correct tx and rx fifo endianness
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target/arm/ptw.c | 11 ++++++-----
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Iris Johnson (2):
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled
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hw/char/exynos4210_uart: Fix missing call to report ready for input
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Philippe Mathieu-Daudé (12):
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hw/intc/arm_gic: Allow to use QTest without crashing
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hw/ssi: imx_spi: Remove pointless variable initialization
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hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
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hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
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hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
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hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register
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hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ
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hw/arm/exynos4210: Add missing dependency on OR_IRQ
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hw/arm/xlnx-versal: Versal SoC requires ZDMA
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hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals
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hw/net/can: ZynqMP CAN device requires PTIMER
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hw/arm: Display CPU type in machine description
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Xuzhou Cheng (1):
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hw/ssi: imx_spi: Disable chip selects when controller is disabled
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Zenghui Yu (1):
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hw/arm/smmuv3: Fix addr_mask for range-based invalidation
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include/hw/ssi/imx_spi.h | 5 +-
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hw/arm/digic_boards.c | 2 +-
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hw/arm/microbit.c | 2 +-
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hw/arm/netduino2.c | 2 +-
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hw/arm/netduinoplus2.c | 2 +-
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hw/arm/orangepi.c | 2 +-
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hw/arm/smmuv3.c | 4 +-
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hw/arm/stellaris.c | 4 +-
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hw/char/exynos4210_uart.c | 7 ++-
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hw/intc/arm_gic.c | 5 +-
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hw/ssi/imx_spi.c | 153 +++++++++++++++++++++++++++++-----------------
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hw/Kconfig | 1 +
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hw/arm/Kconfig | 5 ++
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hw/dma/Kconfig | 3 +
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hw/dma/meson.build | 2 +-
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15 files changed, 130 insertions(+), 69 deletions(-)
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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