[PULL 0/2] target-arm queue
[PULL v2 00/46] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2 update: fix memory leaks in pvpanic-pci test case spotted by
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we were using uninitialized data for the guarded bit when
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oss-fuzz gitlab CI run.
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combining stage 1 and stage 2 attrs.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' into staging (2021-01-28 22:43:18 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210129-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 14711b6f54708b9583796db02b12ee7bd0331502:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 15:54:44 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Implement ID_PFR2
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* Conditionalize DBGDIDR
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* rename xlnx-zcu102.canbusN properties
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* provide powerdown/reset mechanism for secure firmware on 'virt' board
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* hw/misc: Fix arith overflow in NPCM7XX PWM module
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* target/arm: Replace magic value by MMU_DATA_LOAD definition
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* configure: fix preadv errors on Catalina macOS with new XCode
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* Various configure and other cleanups in preparation for iOS support
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* hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
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* Implement pvpanic-pci device
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* Convert the CMSDK timer devices to the Clock framework
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alexander Graf (1):
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hvf: Add hypervisor entitlement to output binaries
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Hao Wu (1):
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hw/misc: Fix arith overflow in NPCM7XX PWM module
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Joelle van Dyne (7):
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configure: cross-compiling with empty cross_prefix
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osdep: build with non-working system() function
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darwin: remove redundant dependency declaration
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darwin: fix cross-compiling for Darwin
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configure: cross compile should use x86_64 cpu_family
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darwin: detect CoreAudio for build
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darwin: remove 64-bit build detection on 32-bit OS
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Maxim Uvarov (3):
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hw: gpio: implement gpio-pwr driver for qemu reset/poweroff
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arm-virt: refactor gpios creation
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arm-virt: add secure pl061 for reset/power down
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Mihai Carabas (4):
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hw/misc/pvpanic: split-out generic and bus dependent code
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hw/misc/pvpanic: add PCI interface support
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pvpanic : update pvpanic spec document
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tests/qtest: add a test case for pvpanic-pci
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Paolo Bonzini (1):
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arm: rename xlnx-zcu102.canbusN properties
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Peter Maydell (26):
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configure: Move preadv check to meson.build
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ptimer: Add new ptimer_set_period_from_clock() function
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clock: Add new clock_has_source() function
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tests: Add a simple test of the CMSDK APB timer
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tests: Add a simple test of the CMSDK APB watchdog
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tests: Add a simple test of the CMSDK APB dual timer
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hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
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hw/timer/cmsdk-apb-timer: Add Clock input
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hw/timer/cmsdk-apb-dualtimer: Add Clock input
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hw/watchdog/cmsdk-apb-watchdog: Add Clock input
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hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
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hw/arm/armsse: Wire up clocks
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hw/arm/mps2: Inline CMSDK_APB_TIMER creation
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hw/arm/mps2: Create and connect SYSCLK Clock
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hw/arm/mps2-tz: Create and connect ARMSSE Clocks
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hw/arm/musca: Create and connect ARMSSE Clocks
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hw/arm/stellaris: Convert SSYS to QOM device
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hw/arm/stellaris: Create Clock input for watchdog
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hw/timer/cmsdk-apb-timer: Convert to use Clock input
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hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
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hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
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tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
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hw/arm/armsse: Use Clock to set system_clock_scale
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arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
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arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
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hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
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Philippe Mathieu-Daudé (1):
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target/arm: Replace magic value by MMU_DATA_LOAD definition
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Richard Henderson (2):
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Richard Henderson (2):
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target/arm: PTE bit GP only applies to stage1
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target/arm: Implement ID_PFR2
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target/arm: Copy guarded bit in combine_cacheattrs
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target/arm: Conditionalize DBGDIDR
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target/arm/ptw.c | 11 ++++++-----
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docs/devel/clocks.rst | 16 +++
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1 file changed, 6 insertions(+), 5 deletions(-)
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docs/specs/pci-ids.txt | 1 +
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docs/specs/pvpanic.txt | 13 ++-
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docs/system/arm/virt.rst | 2 +
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configure | 78 ++++++++------
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meson.build | 34 ++++++-
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include/hw/arm/armsse.h | 14 ++-
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include/hw/arm/virt.h | 2 +
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include/hw/clock.h | 15 +++
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include/hw/misc/pvpanic.h | 24 ++++-
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include/hw/pci/pci.h | 1 +
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include/hw/ptimer.h | 22 ++++
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include/hw/timer/cmsdk-apb-dualtimer.h | 5 +-
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include/hw/timer/cmsdk-apb-timer.h | 34 ++-----
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include/hw/watchdog/cmsdk-apb-watchdog.h | 5 +-
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include/qemu/osdep.h | 12 +++
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include/qemu/typedefs.h | 1 +
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target/arm/cpu.h | 1 +
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hw/arm/armsse.c | 48 ++++++---
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hw/arm/mps2-tz.c | 14 ++-
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hw/arm/mps2.c | 28 ++++-
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hw/arm/musca.c | 13 ++-
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hw/arm/stellaris.c | 170 +++++++++++++++++++++++--------
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hw/arm/virt.c | 111 ++++++++++++++++----
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hw/arm/xlnx-zcu102.c | 4 +-
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hw/core/ptimer.c | 34 +++++++
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hw/gpio/gpio_pwr.c | 70 +++++++++++++
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hw/misc/npcm7xx_pwm.c | 23 ++++-
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hw/misc/pvpanic-isa.c | 94 +++++++++++++++++
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hw/misc/pvpanic-pci.c | 94 +++++++++++++++++
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hw/misc/pvpanic.c | 85 ++--------------
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hw/timer/cmsdk-apb-dualtimer.c | 53 +++++++---
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hw/timer/cmsdk-apb-timer.c | 55 +++++-----
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hw/watchdog/cmsdk-apb-watchdog.c | 29 ++++--
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target/arm/helper.c | 27 +++--
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target/arm/kvm64.c | 2 +
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tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++
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tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++
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tests/qtest/cmsdk-apb-watchdog-test.c | 131 ++++++++++++++++++++++++
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tests/qtest/npcm7xx_pwm-test.c | 4 +-
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tests/qtest/pvpanic-pci-test.c | 98 ++++++++++++++++++
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tests/qtest/xlnx-can-test.c | 30 +++---
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MAINTAINERS | 3 +
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accel/hvf/entitlements.plist | 8 ++
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hw/arm/Kconfig | 1 +
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hw/gpio/Kconfig | 3 +
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hw/gpio/meson.build | 1 +
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hw/i386/Kconfig | 2 +-
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hw/misc/Kconfig | 12 ++-
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hw/misc/meson.build | 4 +-
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scripts/entitlement.sh | 13 +++
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tests/qtest/meson.build | 6 +-
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52 files changed, 1436 insertions(+), 319 deletions(-)
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create mode 100644 hw/gpio/gpio_pwr.c
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create mode 100644 hw/misc/pvpanic-isa.c
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create mode 100644 hw/misc/pvpanic-pci.c
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create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
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create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
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create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
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create mode 100644 tests/qtest/pvpanic-pci-test.c
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create mode 100644 accel/hvf/entitlements.plist
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create mode 100755 scripts/entitlement.sh
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

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