[PULL 0/2] target-arm queue
[PULL v2 00/20] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2: drop the 'merge the manuals' patch: it breaks the gitlab job which tries
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we were using uninitialized data for the guarded bit when
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to publish the docs on gitlab, and I also realised I forgot to update the
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combining stage 1 and stage 2 attrs.
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Windows installer scripts.
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 1ff5a063d60c7737de11465516331b8ca8700865:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 21:19:02 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* arm: Support emulation of ARMv8.4-TTST extension
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* arm: Update cpu.h ID register field definitions
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* arm: Fix breakage of XScale instruction emulation
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* hw/net/lan9118: Fix RX Status FIFO PEEK value
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* npcm7xx: Add ADC and PWM emulation
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* ui/cocoa: Make "open docs" help menu entry work again when binary
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is run from the build tree
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* ui/cocoa: Fix openFile: deprecation on Big Sur
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* docs: Add qemu-storage-daemon(1) manpage to meson.build
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Hao Wu (6):
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target/arm: PTE bit GP only applies to stage1
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hw/misc: Add clock converter in NPCM7XX CLK module
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target/arm: Copy guarded bit in combine_cacheattrs
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hw/timer: Refactor NPCM7XX Timer to use CLK clock
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hw/adc: Add an ADC module for NPCM7XX
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hw/misc: Add a PWM module for NPCM7XX
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hw/misc: Add QTest for NPCM7XX PWM Module
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hw/*: Use type casting for SysBusDevice in NPCM7XX
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target/arm/ptw.c | 11 ++++++-----
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Leif Lindholm (6):
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1 file changed, 6 insertions(+), 5 deletions(-)
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target/arm: fix typo in cpu.h ID_AA64PFR1 field name
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target/arm: make ARMCPU.clidr 64-bit
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target/arm: make ARMCPU.ctr 64-bit
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target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
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target/arm: add aarch64 ID register fields to cpu.h
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target/arm: add aarch32 ID register fields to cpu.h
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Peter Maydell (4):
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docs: Add qemu-storage-daemon(1) manpage to meson.build
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target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
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hw/net/lan9118: Fix RX Status FIFO PEEK value
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hw/net/lan9118: Add symbolic constants for register offsets
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Roman Bolshakov (2):
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ui/cocoa: Update path to docs in build tree
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ui/cocoa: Fix openFile: deprecation on Big Sur
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Rémi Denis-Courmont (2):
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target/arm: ARMv8.4-TTST extension
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target/arm: enable Small Translation tables in max CPU
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docs/meson.build | 1 +
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docs/system/arm/nuvoton.rst | 4 +-
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meson.build | 1 +
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hw/adc/trace.h | 1 +
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include/hw/adc/npcm7xx_adc.h | 69 ++++
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include/hw/arm/npcm7xx.h | 4 +
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include/hw/misc/npcm7xx_clk.h | 146 ++++++-
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include/hw/misc/npcm7xx_pwm.h | 105 +++++
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include/hw/timer/npcm7xx_timer.h | 1 +
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target/arm/cpu.h | 85 ++++-
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hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
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hw/arm/npcm7xx.c | 55 ++-
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hw/arm/npcm7xx_boards.c | 2 +-
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hw/mem/npcm7xx_mc.c | 2 +-
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hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
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hw/misc/npcm7xx_gcr.c | 2 +-
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hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
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hw/misc/npcm7xx_rng.c | 2 +-
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hw/net/lan9118.c | 26 +-
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hw/nvram/npcm7xx_otp.c | 2 +-
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hw/ssi/npcm7xx_fiu.c | 2 +-
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hw/timer/npcm7xx_timer.c | 39 +-
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target/arm/cpu64.c | 1 +
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target/arm/helper.c | 15 +-
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target/arm/translate.c | 7 +
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tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
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tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
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hw/adc/meson.build | 1 +
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hw/adc/trace-events | 5 +
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hw/misc/meson.build | 1 +
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hw/misc/trace-events | 6 +
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tests/qtest/meson.build | 4 +-
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ui/cocoa.m | 7 +-
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33 files changed, 3054 insertions(+), 67 deletions(-)
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create mode 100644 hw/adc/trace.h
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create mode 100644 include/hw/adc/npcm7xx_adc.h
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create mode 100644 include/hw/misc/npcm7xx_pwm.h
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create mode 100644 hw/adc/npcm7xx_adc.c
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create mode 100644 hw/misc/npcm7xx_pwm.c
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create mode 100644 tests/qtest/npcm7xx_adc-test.c
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create mode 100644 tests/qtest/npcm7xx_pwm-test.c
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create mode 100644 hw/adc/trace-events
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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