[PULL 0/2] target-arm queue
[PULL v2 00/30] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v2:
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we were using uninitialized data for the guarded bit when
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* dropped target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]
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combining stage 1 and stage 2 attrs.
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* renamed CLOCK_SECOND to CLOCK_PERIOD_1SEC
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thanks
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into staging (2020-04-29 15:07:33 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200430-1
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 6f7b6947a6639fff15c6a0956adf0f5ec004b789:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes (2020-04-30 15:35:41 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* xlnx-zdma: Fix endianness handling of descriptor loading
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* nrf51: Fix last GPIO CNF address
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* gicv3: Use gicr_typer in arm_gicv3_icc_reset
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* msf2: Add EMAC block to SmartFusion2 SoC
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* New clock modelling framework
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* hw/arm: versal: Setup the ADMA with 128bit bus-width
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* Cadence: gem: fix wraparound in 64bit descriptors
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* cadence_gem: clear RX control descriptor
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* target/arm: Vectorize integer comparison vs zero
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* hw/arm/virt: dt: add kaslr-seed property
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* hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Cameron Esfahani (1):
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target/arm: PTE bit GP only applies to stage1
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nrf51: Fix last GPIO CNF address
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target/arm: Copy guarded bit in combine_cacheattrs
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target/arm/ptw.c | 11 ++++++-----
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Damien Hedde (7):
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1 file changed, 6 insertions(+), 5 deletions(-)
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hw/core/clock-vmstate: define a vmstate entry for clock state
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qdev: add clock input&output support to devices.
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qdev-clock: introduce an init array to ease the device construction
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hw/misc/zynq_slcr: add clock generation for uarts
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hw/char/cadence_uart: add clock support
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hw/arm/xilinx_zynq: connect uart clocks to slcr
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qdev-monitor: print the device's clock with info qtree
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Edgar E. Iglesias (7):
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dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness
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dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness
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hw/arm: versal: Setup the ADMA with 128bit bus-width
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device_tree: Allow name wildcards in qemu_fdt_node_path()
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device_tree: Constify compat in qemu_fdt_node_path()
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hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102
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hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes
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Jerome Forissier (2):
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hw/arm/virt: dt: move creation of /secure-chosen to create_fdt()
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hw/arm/virt: dt: add kaslr-seed property
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Keqian Zhu (2):
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bugfix: Use gicr_typer in arm_gicv3_icc_reset
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Typo: Correct the name of CPU hotplug memory region
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Peter Maydell (2):
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hw/core/clock: introduce clock object
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docs/clocks: add device's clock documentation
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Philippe Mathieu-Daudé (2):
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target/arm: Restrict the Address Translate write operation to TCG accel
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target/arm/cpu: Update coding style to make checkpatch.pl happy
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Ramon Fried (2):
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Cadence: gem: fix wraparound in 64bit descriptors
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net: cadence_gem: clear RX control descriptor
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Richard Henderson (1):
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target/arm: Vectorize integer comparison vs zero
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Subbaraya Sundeep (3):
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hw/net: Add Smartfusion2 emac block
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msf2: Add EMAC block to SmartFusion2 SoC
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tests/boot_linux_console: Add ethernet test to SmartFusion2
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Thomas Huth (1):
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target/arm: Make cpu_register() available for other files
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hw/core/Makefile.objs | 2 +
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hw/net/Makefile.objs | 1 +
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tests/Makefile.include | 1 +
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include/hw/arm/msf2-soc.h | 2 +
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include/hw/char/cadence_uart.h | 1 +
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include/hw/clock.h | 225 +++++++++++++
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include/hw/gpio/nrf51_gpio.h | 2 +-
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include/hw/net/msf2-emac.h | 53 +++
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include/hw/qdev-clock.h | 159 +++++++++
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include/hw/qdev-core.h | 12 +
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include/sysemu/device_tree.h | 5 +-
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target/arm/cpu-qom.h | 9 +-
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target/arm/helper.h | 27 +-
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target/arm/translate.h | 5 +
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device_tree.c | 4 +-
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hw/acpi/cpu.c | 2 +-
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hw/arm/msf2-soc.c | 26 +-
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hw/arm/virt.c | 20 +-
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hw/arm/xilinx_zynq.c | 57 +++-
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hw/arm/xlnx-versal.c | 2 +
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hw/arm/xlnx-zcu102.c | 39 ++-
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hw/char/cadence_uart.c | 73 +++-
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hw/core/clock-vmstate.c | 25 ++
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hw/core/clock.c | 130 ++++++++
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hw/core/qdev-clock.c | 185 +++++++++++
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hw/core/qdev.c | 12 +
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hw/dma/xlnx-zdma.c | 25 +-
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hw/intc/arm_gicv3_kvm.c | 4 +-
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hw/misc/zynq_slcr.c | 172 +++++++++-
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hw/net/cadence_gem.c | 16 +-
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hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++
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qdev-monitor.c | 9 +
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target/arm/cpu.c | 19 +-
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target/arm/cpu64.c | 8 +-
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target/arm/helper.c | 17 +
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target/arm/neon_helper.c | 24 --
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target/arm/translate-a64.c | 64 +---
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target/arm/translate.c | 256 ++++++++++++--
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target/arm/vec_helper.c | 25 ++
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MAINTAINERS | 2 +
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docs/devel/clocks.rst | 391 ++++++++++++++++++++++
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docs/devel/index.rst | 1 +
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hw/char/trace-events | 3 +
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hw/core/trace-events | 7 +
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tests/acceptance/boot_linux_console.py | 15 +-
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45 files changed, 2533 insertions(+), 193 deletions(-)
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create mode 100644 include/hw/clock.h
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create mode 100644 include/hw/net/msf2-emac.h
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create mode 100644 include/hw/qdev-clock.h
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create mode 100644 hw/core/clock-vmstate.c
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create mode 100644 hw/core/clock.c
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create mode 100644 hw/core/qdev-clock.c
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create mode 100644 hw/net/msf2-emac.c
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create mode 100644 docs/devel/clocks.rst
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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