[PULL 0/2] target-arm queue
[PULL v3 00/20] target-arm queue
1
This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
1
v1->v2: add system/index to docs/index.rst
2
we were using uninitialized data for the guarded bit when
2
v2->v3: fix format string issues for OSX
3
combining stage 1 and stage 2 attrs.
4
3
5
thanks
4
The following changes since commit b7c359c748a2e3ccb97a184b9739feb2cd48de2f:
6
-- PMM
7
5
8
The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
6
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-01-23 14:38:43 +0000)
9
10
Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
11
7
12
are available in the Git repository at:
8
are available in the Git repository at:
13
9
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
10
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200123-3
15
11
16
for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
12
for you to fetch changes up to 9805a6b7d03a23e16d6499d16882094db490683a:
17
13
18
target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
14
hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 (2020-01-23 15:52:34 +0000)
19
15
20
----------------------------------------------------------------
16
----------------------------------------------------------------
21
target-arm: Fix bug where we weren't initializing
17
target-arm queue:
22
guarded bit state when combining S1/S2 attrs
18
* fix bug in PAuth emulation
19
* add PMU to Cortex-R5, Cortex-R5F
20
* qemu-nbd: Convert documentation to rST
21
* qemu-block-drivers: Convert documentation to rST
22
* Fix Exynos4210 UART DMA support
23
* Various minor code cleanups
23
24
24
----------------------------------------------------------------
25
----------------------------------------------------------------
25
Richard Henderson (2):
26
Andrew Jones (1):
26
target/arm: PTE bit GP only applies to stage1
27
target/arm/arch_dump: Add SVE notes
27
target/arm: Copy guarded bit in combine_cacheattrs
28
28
29
target/arm/ptw.c | 11 ++++++-----
29
Clement Deschamps (1):
30
1 file changed, 6 insertions(+), 5 deletions(-)
30
target/arm: add PMU feature to cortex-r5 and cortex-r5f
31
32
Guenter Roeck (8):
33
dma/pl330: Convert to support tracing
34
hw/core/or-irq: Increase limit of or-lines to 48
35
hw/arm/exynos4210: Fix DMA initialization
36
hw/char/exynos4210_uart: Convert to support tracing
37
hw/char/exynos4210_uart: Implement post_load function
38
hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
39
hw/char/exynos4210_uart: Add receive DMA support
40
hw/arm/exynos4210: Connect serial port DMA busy signals with pl330
41
42
Keqian Zhu (2):
43
hw/acpi: Remove extra indent in ACPI GED hotplug cb
44
hw/arm: Use helper function to trigger hotplug handler plug
45
46
Peter Maydell (3):
47
qemu-nbd: Convert invocation documentation to rST
48
docs: Create stub system manual
49
qemu-block-drivers: Convert to rST
50
51
Philippe Mathieu-Daudé (1):
52
hw/misc/stm32f4xx_syscfg: Fix copy/paste error
53
54
Richard Henderson (3):
55
tests/tcg/aarch64: Fix compilation parameters for pauth-%
56
tests/tcg/aarch64: Add pauth-3
57
tests/tcg/aarch64: Add pauth-4
58
59
Vincent Dehors (1):
60
target/arm: Fix PAuth sbox functions
61
62
Makefile | 37 +-
63
tests/tcg/aarch64/Makefile.softmmu-target | 5 +-
64
tests/tcg/aarch64/Makefile.target | 3 +-
65
include/elf.h | 1 +
66
include/hw/arm/exynos4210.h | 4 +
67
include/hw/or-irq.h | 2 +-
68
target/arm/cpu.h | 25 +
69
hw/acpi/generic_event_device.c | 2 +-
70
hw/arm/exynos4210.c | 77 ++-
71
hw/arm/virt.c | 6 +-
72
hw/char/exynos4210_uart.c | 245 +++++---
73
hw/dma/pl330.c | 88 +--
74
hw/misc/stm32f4xx_syscfg.c | 2 +-
75
target/arm/arch_dump.c | 124 +++-
76
target/arm/cpu.c | 1 +
77
target/arm/kvm64.c | 24 -
78
target/arm/pauth_helper.c | 4 +-
79
tests/tcg/aarch64/pauth-1.c | 2 -
80
tests/tcg/aarch64/pauth-2.c | 2 -
81
tests/tcg/aarch64/pauth-4.c | 25 +
82
tests/tcg/aarch64/system/pauth-3.c | 40 ++
83
MAINTAINERS | 1 +
84
docs/index.html.in | 1 +
85
docs/index.rst | 2 +-
86
docs/interop/conf.py | 4 +-
87
docs/interop/index.rst | 1 +
88
docs/interop/qemu-nbd.rst | 263 ++++++++
89
docs/interop/qemu-option-trace.rst.inc | 30 +
90
docs/qemu-block-drivers.texi | 889 ---------------------------
91
docs/system/conf.py | 22 +
92
docs/system/index.rst | 17 +
93
docs/system/qemu-block-drivers.rst | 985 ++++++++++++++++++++++++++++++
94
hw/char/trace-events | 20 +
95
hw/dma/trace-events | 24 +
96
qemu-doc.texi | 18 -
97
qemu-nbd.texi | 214 -------
98
qemu-option-trace.texi | 4 +
99
qemu-options.hx | 2 +-
100
38 files changed, 1898 insertions(+), 1318 deletions(-)
101
create mode 100644 tests/tcg/aarch64/pauth-4.c
102
create mode 100644 tests/tcg/aarch64/system/pauth-3.c
103
create mode 100644 docs/interop/qemu-nbd.rst
104
create mode 100644 docs/interop/qemu-option-trace.rst.inc
105
delete mode 100644 docs/qemu-block-drivers.texi
106
create mode 100644 docs/system/conf.py
107
create mode 100644 docs/system/index.rst
108
create mode 100644 docs/system/qemu-block-drivers.rst
109
delete mode 100644 qemu-nbd.texi
110
diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Only perform the extract of GP during the stage1 walk.
4
5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 10 +++++-----
12
1 file changed, 5 insertions(+), 5 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
19
result->f.attrs.secure = false;
20
}
21
22
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
23
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
24
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
25
- }
26
-
27
if (regime_is_stage2(mmu_idx)) {
28
result->cacheattrs.is_s2_format = true;
29
result->cacheattrs.attrs = extract32(attrs, 2, 4);
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
31
assert(attrindx <= 7);
32
result->cacheattrs.is_s2_format = false;
33
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
34
+
35
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
36
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
37
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
38
+ }
39
}
40
41
/*
42
--
43
2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The guarded bit comes from the stage1 walk.
4
5
Fixes: Coverity CID 1507929
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
19
20
assert(!s1.is_s2_format);
21
ret.is_s2_format = false;
22
+ ret.guarded = s1.guarded;
23
24
if (s1.attrs == 0xf0) {
25
tagged = true;
26
--
27
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.