| 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: | 1 | Changes v2->v3: |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | 2 | dropped the aspeed new board patch as it fails in |
| 3 | combining stage 1 and stage 2 attrs. | 3 | tests/qom-test on OSX (intermittently). |
| 4 | 4 | ||
| 5 | thanks | 5 | thanks |
| 6 | -- PMM | 6 | -- PMM |
| 7 | 7 | ||
| 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | 8 | The following changes since commit f9bec781379dd7ccf9d01b4b6a79a9ec82c192e5: |
| 9 | 9 | ||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | 10 | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191022' into staging (2019-10-22 13:45:09 +0100) |
| 11 | 11 | ||
| 12 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 13 | 13 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191022-2 |
| 15 | 15 | ||
| 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: | 16 | for you to fetch changes up to 90600829b3355b8d27b791b893095c18f529aec3: |
| 17 | 17 | ||
| 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) | 18 | hw/arm/digic4: Inline digic4_board_setup_ram() function (2019-10-22 17:44:01 +0100) |
| 19 | 19 | ||
| 20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 21 | target-arm: Fix bug where we weren't initializing | 21 | * Fix sign-extension for SMLAL* instructions |
| 22 | guarded bit state when combining S1/S2 attrs | 22 | * Various ptimer device conversions to new transaction API |
| 23 | * Add a dummy Samsung SDHCI controller model to exynos4 boards | ||
| 24 | * Minor refactorings of RAM creation for some arm boards | ||
| 23 | 25 | ||
| 24 | ---------------------------------------------------------------- | 26 | ---------------------------------------------------------------- |
| 25 | Richard Henderson (2): | 27 | Guenter Roeck (1): |
| 26 | target/arm: PTE bit GP only applies to stage1 | 28 | hw/timer/exynos4210_mct: Initialize ptimer before starting it |
| 27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
| 28 | 29 | ||
| 29 | target/arm/ptw.c | 11 ++++++----- | 30 | Peter Maydell (7): |
| 30 | 1 file changed, 6 insertions(+), 5 deletions(-) | 31 | hw/timer/arm_mptimer.c: Undo accidental rename of arm_mptimer_init() |
| 32 | hw/timer/puv3_ost.c: Switch to transaction-based ptimer API | ||
| 33 | hw/timer/sh_timer: Switch to transaction-based ptimer API | ||
| 34 | hw/timer/lm32_timer: Switch to transaction-based ptimer API | ||
| 35 | hw/timer/altera_timer.c: Switch to transaction-based ptimer API | ||
| 36 | hw/watchdog/etraxfs_timer.c: Switch to transaction-based ptimer API | ||
| 37 | hw/m68k/mcf5208.c: Switch to transaction-based ptimer API | ||
| 38 | |||
| 39 | Philippe Mathieu-Daudé (9): | ||
| 40 | hw/sd/sdhci: Add a comment to distinct the i.MX eSDHC functions | ||
| 41 | hw/sd/sdhci: Add dummy Samsung SDHCI controller | ||
| 42 | hw/arm/exynos4210: Use the Samsung s3c SDHCI controller | ||
| 43 | hw/arm/xilinx_zynq: Use the IEC binary prefix definitions | ||
| 44 | hw/arm/mps2: Use the IEC binary prefix definitions | ||
| 45 | hw/arm/collie: Create the RAM in the board | ||
| 46 | hw/arm/omap2: Create the RAM in the board | ||
| 47 | hw/arm/omap1: Create the RAM in the board | ||
| 48 | hw/arm/digic4: Inline digic4_board_setup_ram() function | ||
| 49 | |||
| 50 | Richard Henderson (1): | ||
| 51 | target/arm: Fix sign-extension for SMLAL* | ||
| 52 | |||
| 53 | hw/arm/strongarm.h | 4 +-- | ||
| 54 | include/hw/arm/omap.h | 10 +++---- | ||
| 55 | include/hw/sd/sdhci.h | 2 ++ | ||
| 56 | hw/arm/collie.c | 8 ++++-- | ||
| 57 | hw/arm/digic_boards.c | 9 ++----- | ||
| 58 | hw/arm/exynos4210.c | 2 +- | ||
| 59 | hw/arm/mps2-tz.c | 3 ++- | ||
| 60 | hw/arm/mps2.c | 3 ++- | ||
| 61 | hw/arm/nseries.c | 10 ++++--- | ||
| 62 | hw/arm/omap1.c | 12 ++++----- | ||
| 63 | hw/arm/omap2.c | 13 ++++----- | ||
| 64 | hw/arm/omap_sx1.c | 8 ++++-- | ||
| 65 | hw/arm/palm.c | 8 ++++-- | ||
| 66 | hw/arm/strongarm.c | 7 +---- | ||
| 67 | hw/arm/xilinx_zynq.c | 3 ++- | ||
| 68 | hw/m68k/mcf5208.c | 9 ++++--- | ||
| 69 | hw/sd/sdhci.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++- | ||
| 70 | hw/timer/altera_timer.c | 13 ++++++--- | ||
| 71 | hw/timer/arm_mptimer.c | 4 +-- | ||
| 72 | hw/timer/etraxfs_timer.c | 23 +++++++++------- | ||
| 73 | hw/timer/exynos4210_mct.c | 2 +- | ||
| 74 | hw/timer/lm32_timer.c | 13 ++++++--- | ||
| 75 | hw/timer/puv3_ost.c | 9 ++++--- | ||
| 76 | hw/timer/sh_timer.c | 13 ++++++--- | ||
| 77 | target/arm/translate.c | 4 ++- | ||
| 78 | 25 files changed, 174 insertions(+), 86 deletions(-) | ||
| 79 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |