[PULL 0/2] target-arm queue
[PULL v2 00/67] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2 changes: dropped the patch adding the new ast2600
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we were using uninitialized data for the guarded bit when
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board, as it doesn't pass "make check" on 32-bit hosts or
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combining stage 1 and stage 2 attrs.
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low-memory hosts.
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 3af78db68176a049e2570822f64604e0692c1447:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-10-15 13:25:05 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191015
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 19845504da1bdee4be7d0fba33da5be9efa4c11b:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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hw/misc/bcm2835_mbox: Add trace events (2019-10-15 18:09:05 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* Add Aspeed AST2600 SoC support (but no new board model yet)
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* aspeed/wdt: Check correct register for clock source
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* bcm2835: code cleanups, better logging, trace events
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* implement v2.0 of the Arm semihosting specification
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* provide new 'transaction-based' ptimer API and use it
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for the Arm devices that use ptimers
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* ARM: KVM: support more than 256 CPUs
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Amithash Prasad (1):
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target/arm: PTE bit GP only applies to stage1
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aspeed/wdt: Check correct register for clock source
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target/arm: Copy guarded bit in combine_cacheattrs
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Cédric Le Goater (14):
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target/arm/ptw.c | 11 ++++++-----
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aspeed/timer: Introduce an object class per SoC
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1 file changed, 6 insertions(+), 5 deletions(-)
36
aspeed/timer: Add support for control register 3
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aspeed/timer: Add AST2600 support
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aspeed/timer: Add support for IRQ status register on the AST2600
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aspeed/sdmc: Introduce an object class per SoC
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watchdog/aspeed: Introduce an object class per SoC
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aspeed/smc: Introduce segment operations
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aspeed/smc: Add AST2600 support
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aspeed/i2c: Introduce an object class per SoC
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aspeed/i2c: Add AST2600 support
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aspeed: Introduce an object class per SoC
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aspeed/soc: Add AST2600 support
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m25p80: Add support for w25q512jv
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aspeed: add support for the Aspeed MII controller of the AST2600
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Eddie James (1):
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hw/sd/aspeed_sdhci: New device
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Eric Auger (3):
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linux headers: update against v5.4-rc1
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intc/arm_gic: Support IRQ injection for more than 256 vpus
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ARM: KVM: Check KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 for smp_cpus > 256
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Joel Stanley (5):
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hw: aspeed_scu: Add AST2600 support
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aspeed/sdmc: Add AST2600 support
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hw: wdt_aspeed: Add AST2600 support
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aspeed: Parameterise number of MACs
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aspeed/soc: Add ASPEED Video stub
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Peter Maydell (36):
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ptimer: Rename ptimer_init() to ptimer_init_with_bh()
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ptimer: Provide new transaction-based API
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tests/ptimer-test: Switch to transaction-based ptimer API
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hw/timer/arm_timer.c: Switch to transaction-based ptimer API
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hw/arm/musicpal.c: Switch to transaction-based ptimer API
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hw/timer/allwinner-a10-pit.c: Switch to transaction-based ptimer API
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hw/timer/arm_mptimer.c: Switch to transaction-based ptimer API
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hw/timer/cmsdk-apb-dualtimer.c: Switch to transaction-based ptimer API
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hw/timer/cmsdk-apb-timer.c: Switch to transaction-based ptimer API
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hw/timer/digic-timer.c: Switch to transaction-based ptimer API
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hw/timer/exynos4210_mct.c: Switch GFRC to transaction-based ptimer API
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hw/timer/exynos4210_mct.c: Switch LFRC to transaction-based ptimer API
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hw/timer/exynos4210_mct.c: Switch ltick to transaction-based ptimer API
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hw/timer/exynos4210_pwm.c: Switch to transaction-based ptimer API
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hw/timer/exynos4210_rtc.c: Switch 1Hz ptimer to transaction-based API
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hw/timer/exynos4210_rtc.c: Switch main ptimer to transaction-based API
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hw/timer/imx_epit.c: Switch to transaction-based ptimer API
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hw/timer/imx_gpt.c: Switch to transaction-based ptimer API
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hw/timer/mss-timerc: Switch to transaction-based ptimer API
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hw/watchdog/cmsdk-apb-watchdog.c: Switch to transaction-based ptimer API
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hw/net/lan9118.c: Switch to transaction-based ptimer API
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target/arm/arm-semi: Capture errno in softmmu version of set_swi_errno()
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target/arm/arm-semi: Always set some kind of errno for failed calls
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target/arm/arm-semi: Correct comment about gdb syscall races
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target/arm/arm-semi: Make semihosting code hand out its own file descriptors
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target/arm/arm-semi: Restrict use of TaskState*
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target/arm/arm-semi: Use set_swi_errno() in gdbstub callback functions
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target/arm/arm-semi: Factor out implementation of SYS_CLOSE
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target/arm/arm-semi: Factor out implementation of SYS_WRITE
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target/arm/arm-semi: Factor out implementation of SYS_READ
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target/arm/arm-semi: Factor out implementation of SYS_ISTTY
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target/arm/arm-semi: Factor out implementation of SYS_SEEK
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target/arm/arm-semi: Factor out implementation of SYS_FLEN
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target/arm/arm-semi: Implement support for semihosting feature detection
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target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension
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target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension
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Philippe Mathieu-Daudé (6):
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hw/arm/raspi: Use the IEC binary prefix definitions
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hw/arm/bcm2835_peripherals: Improve logging
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hw/arm/bcm2835_peripherals: Name various address spaces
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hw/arm/bcm2835: Rename some definitions
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hw/arm/bcm2835: Add various unimplemented peripherals
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hw/misc/bcm2835_mbox: Add trace events
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Rashmica Gupta (1):
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hw/gpio: Add in AST2600 specific implementation
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hw/arm/Makefile.objs | 2 +-
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hw/sd/Makefile.objs | 1 +
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include/hw/arm/aspeed_soc.h | 29 +-
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include/hw/arm/bcm2835_peripherals.h | 15 +
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include/hw/arm/raspi_platform.h | 24 +-
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include/hw/i2c/aspeed_i2c.h | 20 +-
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include/hw/misc/aspeed_scu.h | 7 +-
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include/hw/misc/aspeed_sdmc.h | 20 +-
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include/hw/net/ftgmac100.h | 17 +
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include/hw/ptimer.h | 83 ++-
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include/hw/sd/aspeed_sdhci.h | 34 ++
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include/hw/ssi/aspeed_smc.h | 4 +
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include/hw/timer/aspeed_timer.h | 18 +
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include/hw/timer/mss-timer.h | 1 -
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include/hw/watchdog/wdt_aspeed.h | 19 +-
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include/standard-headers/asm-x86/bootparam.h | 2 +
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include/standard-headers/asm-x86/kvm_para.h | 1 +
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include/standard-headers/linux/ethtool.h | 24 +
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include/standard-headers/linux/pci_regs.h | 19 +-
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include/standard-headers/linux/virtio_fs.h | 19 +
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include/standard-headers/linux/virtio_ids.h | 2 +
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include/standard-headers/linux/virtio_iommu.h | 165 ++++++
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include/standard-headers/linux/virtio_pmem.h | 6 +-
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linux-headers/asm-arm/kvm.h | 16 +-
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linux-headers/asm-arm/unistd-common.h | 2 +
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linux-headers/asm-arm64/kvm.h | 21 +-
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linux-headers/asm-generic/mman-common.h | 18 +-
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linux-headers/asm-generic/mman.h | 10 +-
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linux-headers/asm-generic/unistd.h | 10 +-
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linux-headers/asm-mips/mman.h | 3 +
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linux-headers/asm-mips/unistd_n32.h | 1 +
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linux-headers/asm-mips/unistd_n64.h | 1 +
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linux-headers/asm-mips/unistd_o32.h | 1 +
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linux-headers/asm-powerpc/mman.h | 6 +-
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linux-headers/asm-powerpc/unistd_32.h | 2 +
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linux-headers/asm-powerpc/unistd_64.h | 2 +
150
linux-headers/asm-s390/kvm.h | 6 +
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linux-headers/asm-s390/unistd_32.h | 2 +
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linux-headers/asm-s390/unistd_64.h | 2 +
153
linux-headers/asm-x86/kvm.h | 28 +-
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linux-headers/asm-x86/unistd.h | 2 +-
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linux-headers/asm-x86/unistd_32.h | 2 +
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linux-headers/asm-x86/unistd_64.h | 2 +
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linux-headers/asm-x86/unistd_x32.h | 2 +
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linux-headers/linux/kvm.h | 12 +-
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linux-headers/linux/psp-sev.h | 5 +-
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linux-headers/linux/vfio.h | 71 ++-
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target/arm/kvm_arm.h | 1 +
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hw/arm/aspeed.c | 19 +-
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hw/arm/aspeed_ast2600.c | 523 +++++++++++++++++++
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hw/arm/aspeed_soc.c | 199 +++++---
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hw/arm/bcm2835_peripherals.c | 38 +-
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hw/arm/bcm2836.c | 2 +-
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hw/arm/musicpal.c | 16 +-
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hw/arm/raspi.c | 4 +-
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hw/block/m25p80.c | 1 +
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hw/char/bcm2835_aux.c | 5 +-
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hw/core/ptimer.c | 154 +++++-
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hw/display/bcm2835_fb.c | 2 +-
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hw/dma/bcm2835_dma.c | 10 +-
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hw/dma/xilinx_axidma.c | 2 +-
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hw/gpio/aspeed_gpio.c | 142 +++++-
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hw/i2c/aspeed_i2c.c | 106 +++-
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hw/intc/arm_gic_kvm.c | 7 +-
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hw/intc/bcm2836_control.c | 7 +-
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hw/m68k/mcf5206.c | 2 +-
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hw/m68k/mcf5208.c | 2 +-
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hw/misc/aspeed_scu.c | 194 ++++++-
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hw/misc/aspeed_sdmc.c | 250 ++++++---
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hw/misc/bcm2835_mbox.c | 14 +-
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hw/misc/bcm2835_property.c | 20 +-
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hw/net/fsl_etsec/etsec.c | 2 +-
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hw/net/ftgmac100.c | 162 ++++++
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hw/net/lan9118.c | 11 +-
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hw/sd/aspeed_sdhci.c | 198 ++++++++
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hw/ssi/aspeed_smc.c | 177 ++++++-
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hw/timer/allwinner-a10-pit.c | 12 +-
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hw/timer/altera_timer.c | 2 +-
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hw/timer/arm_mptimer.c | 18 +-
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hw/timer/arm_timer.c | 16 +-
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hw/timer/aspeed_timer.c | 213 +++++++-
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hw/timer/cmsdk-apb-dualtimer.c | 14 +-
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hw/timer/cmsdk-apb-timer.c | 15 +-
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hw/timer/digic-timer.c | 16 +-
198
hw/timer/etraxfs_timer.c | 6 +-
199
hw/timer/exynos4210_mct.c | 107 +++-
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hw/timer/exynos4210_pwm.c | 17 +-
201
hw/timer/exynos4210_rtc.c | 22 +-
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hw/timer/grlib_gptimer.c | 2 +-
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hw/timer/imx_epit.c | 32 +-
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hw/timer/imx_gpt.c | 21 +-
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hw/timer/lm32_timer.c | 2 +-
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hw/timer/milkymist-sysctl.c | 4 +-
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hw/timer/mss-timer.c | 11 +-
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hw/timer/puv3_ost.c | 2 +-
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hw/timer/sh_timer.c | 2 +-
210
hw/timer/slavio_timer.c | 2 +-
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hw/timer/xilinx_timer.c | 2 +-
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hw/watchdog/cmsdk-apb-watchdog.c | 13 +-
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hw/watchdog/wdt_aspeed.c | 153 +++---
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target/arm/arm-semi.c | 707 +++++++++++++++++++++-----
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target/arm/cpu.c | 10 +-
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target/arm/kvm.c | 22 +-
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tests/ptimer-test.c | 106 +++-
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hw/misc/trace-events | 6 +
219
105 files changed, 3934 insertions(+), 650 deletions(-)
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create mode 100644 include/hw/sd/aspeed_sdhci.h
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create mode 100644 include/standard-headers/linux/virtio_fs.h
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create mode 100644 include/standard-headers/linux/virtio_iommu.h
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create mode 100644 hw/arm/aspeed_ast2600.c
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create mode 100644 hw/sd/aspeed_sdhci.c
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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Only perform the extract of GP during the stage1 walk.
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5
Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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1
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The guarded bit comes from the stage1 walk.
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5
Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

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