[PULL 0/2] target-arm queue
[Qemu-devel] [PULL v2 00/44] target-arm queue
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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v1->v2 changes: drop the "convert FEATURE_THUMB2EE" patch as
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we were using uninitialized data for the guarded bit when
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it broke compilation on arm hosts (conversion of KVM related
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combining stage 1 and stage 2 attrs.
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code had been forgotten)
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into staging (2018-10-23 17:20:23 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181024
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb:
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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target/arm: Only flush tlb if ASID changes (2018-10-24 07:51:37 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm: Fix bug where we weren't initializing
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target-arm queue:
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guarded bit state when combining S1/S2 attrs
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* ssi-sd: Make devices picking up backends unavailable with -device
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* Add support for VCPU event states
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* Move towards making ID registers the source of truth for
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whether a guest CPU implements a feature, rather than having
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parallel ID registers and feature bit flags
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* Implement various HCR hypervisor trap/config bits
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* Get IL bit correct for v7 syndrome values
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* Report correct syndrome for FP/SIMD traps to Hyp mode
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* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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* Refactor A32 Neon to use generic vector infrastructure
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* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
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* net: cadence_gem: Report features correctly in ID register
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* Avoid some unnecessary TLB flushes on TTBR register writes
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----------------------------------------------------------------
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----------------------------------------------------------------
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Richard Henderson (2):
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Dongjiu Geng (1):
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target/arm: PTE bit GP only applies to stage1
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target/arm: Add support for VCPU event states
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target/arm: Copy guarded bit in combine_cacheattrs
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target/arm/ptw.c | 11 ++++++-----
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Edgar E. Iglesias (2):
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1 file changed, 6 insertions(+), 5 deletions(-)
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net: cadence_gem: Announce availability of priority queues
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net: cadence_gem: Announce 64bit addressing support
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Markus Armbruster (1):
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ssi-sd: Make devices picking up backends unavailable with -device
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Peter Maydell (10):
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target/arm: Improve debug logging of AArch32 exception return
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target/arm: Make switch_mode() file-local
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target/arm: Implement HCR.FB
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target/arm: Implement HCR.DC
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target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
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target/arm: Implement HCR.VI and VF
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target/arm: Implement HCR.PTW
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target/arm: New utility function to extract EC from syndrome
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target/arm: Get IL bit correct for v7 syndrome values
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target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
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Richard Henderson (29):
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target/arm: Move some system registers into a substructure
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target/arm: V8M should not imply V7VE
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target/arm: Convert v8 extensions from feature bits to isar tests
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target/arm: Convert division from feature bits to isar0 tests
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target/arm: Convert jazelle from feature bit to isar1 test
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target/arm: Convert sve from feature bit to aa64pfr0 test
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target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
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target/arm: Hoist address increment for vector memory ops
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target/arm: Don't call tcg_clear_temp_count
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target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
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target/arm: Promote consecutive memory ops for aa64
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target/arm: Mark some arrays const
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target/arm: Use gvec for NEON VDUP
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target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
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target/arm: Use gvec for NEON_3R_LOGIC insns
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target/arm: Use gvec for NEON_3R_VADD_VSUB insns
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target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
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target/arm: Use gvec for NEON_3R_VMUL
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target/arm: Use gvec for VSHR, VSHL
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target/arm: Use gvec for VSRA
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target/arm: Use gvec for VSRI, VSLI
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target/arm: Use gvec for NEON_3R_VML
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target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
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target/arm: Use gvec for NEON VLD all lanes
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target/arm: Reorg NEON VLD/VST all elements
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target/arm: Promote consecutive memory ops for aa32
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target/arm: Reorg NEON VLD/VST single element to one lane
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target/arm: Remove writefn from TTBR0_EL3
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target/arm: Only flush tlb if ASID changes
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Stewart Hildebrand (1):
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hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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target/arm/cpu.h | 221 ++++++-
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target/arm/internals.h | 45 +-
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target/arm/kvm_arm.h | 24 +
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target/arm/translate.h | 21 +
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hw/arm/boot.c | 18 +
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hw/intc/armv7m_nvic.c | 12 +-
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hw/net/cadence_gem.c | 9 +-
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hw/sd/ssi-sd.c | 2 +
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linux-user/aarch64/signal.c | 4 +-
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linux-user/elfload.c | 58 +-
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linux-user/syscall.c | 10 +-
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target/arm/cpu.c | 238 +++----
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target/arm/cpu64.c | 148 +++--
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target/arm/helper.c | 395 ++++++++----
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target/arm/kvm.c | 60 ++
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target/arm/kvm32.c | 13 +
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target/arm/kvm64.c | 15 +-
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target/arm/machine.c | 25 +-
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target/arm/op_helper.c | 2 +-
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target/arm/translate-a64.c | 715 ++++-----------------
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target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
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21 files changed, 2013 insertions(+), 1473 deletions(-)
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diff view generated by jsdifflib
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Deleted patch
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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