Series comparison

-[PULL 0/2] target-arm queue
+[Qemu-devel] [PULL v2 00/52] target-arm queue
-This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
+target-arm queue: this clears out a bunch of patches I'd sent over
-we were using uninitialized data for the guarded bit when
+the last coupled of weeks that have now got reviewed. Mostly
-combining stage 1 and stage 2 attrs.
+this is MPS2 device support improvements, put there is also
 more of the incremental work towards supporting AArch32 Hyp mode,
 a floating point bugfix, and the raspi framebuffer viewport support.
 v2 fixes a "variable used uninitialized" error in a15mpcore.c.
 thanks
 -- PMM
-The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
-  Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
+The following changes since commit 6b699ae1be9f257478d5eca7ef65dcea270a2796:
   tests/vm: Increase timeout waiting for VM to boot to 5 minutes (2018-08-24 11:31:28 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180824-1
-for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
+for you to fetch changes up to 239cb6feb298a31faa40b7e97ced107bf9c2f2bf:
-  target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
+  hw/arm/mps2: Fix ID register errors on AN511 and AN385 (2018-08-24 13:17:50 +0100)
 ----------------------------------------------------------------
-target-arm: Fix bug where we weren't initializing
+target-arm queue:
-            guarded bit state when combining S1/S2 attrs
+ * Fix rounding errors in scaling float-to-int and int-to-float operations
  * Connect virtualization-related IRQs and memory regions of GICv2
    in boards that use Cortex-A7 or Cortex-A15
  * Support taking exceptions to AArch32 Hyp mode
  * Clear CPSR.IL and CPSR.J on 32-bit exception entry
    (a minor bug fix that won't affect non-buggy guest code)
  * mps2-an505: Implement various missing devices:
    dual timer, watchdogs, counters in the FPGAIO registers,
    some missing ID/control registers, TrustZone Master Security
    Controllers, PL081 DMA controllers, PL022 SPI controllers
  * correct ID register values for mps2-an385, -an511, -an505
  * fix some hardcoded tabs in untouched backwaters of the
    target/arm codebase
  * raspi: Refactor framebuffer property handling code and implement
    support for the virtual framebuffer/viewport
 ----------------------------------------------------------------
-Richard Henderson (2):
+Peter Maydell (48):
-      target/arm: PTE bit GP only applies to stage1
+      hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large
-      target/arm: Copy guarded bit in combine_cacheattrs
+      hw/arm/vexpress: Connect VIRQ and VFIQ
       hw/arm/highbank: Connect VIRQ and VFIQ
       hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
       hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
       hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up
       hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3
       hw/arm/vexpress: Add "virtualization" property controlling presence of EL2
       target/arm: Implement RAZ/WI HACTLR2
       target/arm: Implement AArch32 HCR and HCR2
       target/arm: Factor out code for taking an AArch32 exception
       target/arm: Implement support for taking exceptions to Hyp mode
       target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry
       hw/arm/boot: AArch32 kernels should be started in Hyp mode if available
       hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters
       hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER
       hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module
       hw/arm/iotkit: Wire up the dualtimer
       hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511
       hw/arm/iotkit: Wire up the watchdogs
       hw/arm/iotkit: Wire up the S32KTIMER
       hw/misc/iotkit-sysctl: Implement IoTKit system control element
       hw/misc/iotkit-sysinfo: Implement IoTKit system information block
       hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks
       hw/misc/tz-msc: Model TrustZone Master Security Controller
       hw/misc/iotkit-secctl: Wire up registers for controlling MSCs
       hw/arm/iotkit: Wire up the lines for MSCs
       hw/arm/mps2-tz: Create PL081s and MSCs
       hw/ssi/pl022: Allow use as embedded-struct device
       hw/ssi/pl022: Set up reset function in class init
       hw/ssi/pl022: Don't directly call vmstate_register()
       hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init
       hw/ssi/pl022: Correct wrong value for PL022_INT_RT
       hw/ssi/pl022: Correct wrong DMACR and ICR handling
       hw/arm/mps2-tz: Instantiate SPI controllers
       hw/arm/mps2-tz: Fix MPS2 SCC config register values
       target/arm: Untabify translate.c
       target/arm: Untabify iwmmxt_helper.c
       target/arm: Remove a handful of stray tabs
       hw/misc/bcm2835_fb: Move config fields to their own struct
       hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig
       hw/display/bcm2835_fb: Drop unused size and pitch fields
       hw/display/bcm2835_fb: Reset resolution, etc correctly
       hw/display/bcm2835_fb: Abstract out calculation of pitch, size
       hw/display/bcm2835_fb: Fix handling of virtual framebuffer
       hw/display/bcm2835_fb: Validate config settings
       hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config
       hw/arm/mps2: Fix ID register errors on AN511 and AN385
- target/arm/ptw.c | 11 ++++++-----
+Richard Henderson (4):
-file changed, 6 insertions(+), 5 deletions(-)
+      softfloat: Add scaling int-to-float routines
       softfloat: Add scaling float-to-int routines
       target/arm: Use the int-to-float-scale softfloat routines
       target/arm: Use the float-to-int-scale softfloat routines
  hw/misc/Makefile.objs                  |   3 +
  hw/timer/Makefile.objs                 |   1 +
  include/fpu/softfloat.h                | 169 +++++++---
  include/hw/arm/iotkit.h                |  25 +-
  include/hw/display/bcm2835_fb.h        |  59 +++-
  include/hw/misc/iotkit-secctl.h        |  14 +
  include/hw/misc/iotkit-sysctl.h        |  49 +++
  include/hw/misc/iotkit-sysinfo.h       |  37 +++
  include/hw/misc/mps2-fpgaio.h          |  10 +
  include/hw/misc/tz-msc.h               |  79 +++++
  include/hw/ssi/pl022.h                 |  51 +++
  include/hw/timer/cmsdk-apb-dualtimer.h |  72 ++++
  target/arm/cpu.h                       |  16 +-
  fpu/softfloat.c                        | 579 ++++++++++++++++++++++++++-------
  hw/arm/boot.c                          |  11 +
  hw/arm/fsl-imx6ul.c                    |   4 +
  hw/arm/fsl-imx7.c                      |   4 +
  hw/arm/highbank.c                      |   6 +
  hw/arm/iotkit.c                        | 114 ++++++-
  hw/arm/mps2-tz.c                       | 142 +++++++-
  hw/arm/mps2.c                          |  17 +-
  hw/arm/vexpress.c                      |  64 +++-
  hw/cpu/a15mpcore.c                     |  31 +-
  hw/display/bcm2835_fb.c                | 218 ++++++++-----
  hw/intc/arm_gic.c                      |   2 +-
  hw/misc/bcm2835_property.c             | 123 ++++---
  hw/misc/iotkit-secctl.c                |  73 ++++-
  hw/misc/iotkit-sysctl.c                | 261 +++++++++++++++
  hw/misc/iotkit-sysinfo.c               | 128 ++++++++
  hw/misc/mps2-fpgaio.c                  | 146 ++++++++-
  hw/misc/tz-msc.c                       | 308 ++++++++++++++++++
  hw/ssi/pl022.c                         |  57 ++--
  hw/timer/cmsdk-apb-dualtimer.c         | 515 +++++++++++++++++++++++++++++
  target/arm/arm-semi.c                  |   2 +-
  target/arm/helper.c                    | 342 +++++++++++++------
  target/arm/iwmmxt_helper.c             | 234 ++++++-------
  target/arm/translate.c                 | 122 +++----
  MAINTAINERS                            |  10 +
  default-configs/arm-softmmu.mak        |   4 +
  hw/misc/trace-events                   |  16 +
  hw/timer/trace-events                  |   5 +
 files changed, 3405 insertions(+), 718 deletions(-)
  create mode 100644 include/hw/misc/iotkit-sysctl.h
  create mode 100644 include/hw/misc/iotkit-sysinfo.h
  create mode 100644 include/hw/misc/tz-msc.h
  create mode 100644 include/hw/ssi/pl022.h
  create mode 100644 include/hw/timer/cmsdk-apb-dualtimer.h
  create mode 100644 hw/misc/iotkit-sysctl.c
  create mode 100644 hw/misc/iotkit-sysinfo.c
  create mode 100644 hw/misc/tz-msc.c
  create mode 100644 hw/timer/cmsdk-apb-dualtimer.c

-[PULL 1/2] target/arm: PTE bit GP only applies to stage1
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Only perform the extract of GP during the stage1 walk.
-Reported-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 10 +++++-----
-file changed, 5 insertions(+), 5 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
-         result->f.attrs.secure = false;
-     }
--    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
--    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
--        result->f.guarded = extract64(attrs, 50, 1); /* GP */
--    }
--
-     if (regime_is_stage2(mmu_idx)) {
-         result->cacheattrs.is_s2_format = true;
-         result->cacheattrs.attrs = extract32(attrs, 2, 4);
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
-         assert(attrindx <= 7);
-         result->cacheattrs.is_s2_format = false;
-         result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
-+
-+        /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
-+        if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
-+            result->f.guarded = extract64(attrs, 50, 1); /* GP */
-+        }
-     }
-     /*
---
-.34.1

-[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The guarded bit comes from the stage1 walk.
-Fixes: Coverity CID 1507929
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/ptw.c | 1 +
-file changed, 1 insertion(+)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
-+++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
-     assert(!s1.is_s2_format);
-     ret.is_s2_format = false;
-+    ret.guarded = s1.guarded;
-     if (s1.attrs == 0xf0) {
-         tagged = true;
---
-.34.1

This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
we were using uninitialized data for the guarded bit when
combining stage 1 and stage 2 attrs.

thanks
-- PMM

The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:

Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410

for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:

target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)

----------------------------------------------------------------
target-arm: Fix bug where we weren't initializing
            guarded bit state when combining S1/S2 attrs

----------------------------------------------------------------
Richard Henderson (2):
      target/arm: PTE bit GP only applies to stage1
      target/arm: Copy guarded bit in combine_cacheattrs

target/arm/ptw.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Only perform the extract of GP during the stage1 walk.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
         result->f.attrs.secure = false;
     }
 
-    /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB.  */
-    if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
-        result->f.guarded = extract64(attrs, 50, 1); /* GP */
-    }
-
     if (regime_is_stage2(mmu_idx)) {
         result->cacheattrs.is_s2_format = true;
         result->cacheattrs.attrs = extract32(attrs, 2, 4);
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
         assert(attrindx <= 7);
         result->cacheattrs.is_s2_format = false;
         result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
+
+        /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
+        if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+            result->f.guarded = extract64(attrs, 50, 1); /* GP */
+        }
     }
 
     /*
-- 
2.34.1

target-arm queue: this clears out a bunch of patches I'd sent over
the last coupled of weeks that have now got reviewed. Mostly
this is MPS2 device support improvements, put there is also
more of the incremental work towards supporting AArch32 Hyp mode,
a floating point bugfix, and the raspi framebuffer viewport support.

v2 fixes a "variable used uninitialized" error in a15mpcore.c.

thanks
-- PMM

The following changes since commit 6b699ae1be9f257478d5eca7ef65dcea270a2796:

tests/vm: Increase timeout waiting for VM to boot to 5 minutes (2018-08-24 11:31:28 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180824-1

for you to fetch changes up to 239cb6feb298a31faa40b7e97ced107bf9c2f2bf:

hw/arm/mps2: Fix ID register errors on AN511 and AN385 (2018-08-24 13:17:50 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix rounding errors in scaling float-to-int and int-to-float operations
 * Connect virtualization-related IRQs and memory regions of GICv2
   in boards that use Cortex-A7 or Cortex-A15
 * Support taking exceptions to AArch32 Hyp mode
 * Clear CPSR.IL and CPSR.J on 32-bit exception entry
   (a minor bug fix that won't affect non-buggy guest code)
 * mps2-an505: Implement various missing devices:
   dual timer, watchdogs, counters in the FPGAIO registers,
   some missing ID/control registers, TrustZone Master Security
   Controllers, PL081 DMA controllers, PL022 SPI controllers
 * correct ID register values for mps2-an385, -an511, -an505
 * fix some hardcoded tabs in untouched backwaters of the
   target/arm codebase
 * raspi: Refactor framebuffer property handling code and implement
   support for the virtual framebuffer/viewport

----------------------------------------------------------------
Peter Maydell (48):
      hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large
      hw/arm/vexpress: Connect VIRQ and VFIQ
      hw/arm/highbank: Connect VIRQ and VFIQ
      hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
      hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
      hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up
      hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3
      hw/arm/vexpress: Add "virtualization" property controlling presence of EL2
      target/arm: Implement RAZ/WI HACTLR2
      target/arm: Implement AArch32 HCR and HCR2
      target/arm: Factor out code for taking an AArch32 exception
      target/arm: Implement support for taking exceptions to Hyp mode
      target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry
      hw/arm/boot: AArch32 kernels should be started in Hyp mode if available
      hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters
      hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER
      hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module
      hw/arm/iotkit: Wire up the dualtimer
      hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511
      hw/arm/iotkit: Wire up the watchdogs
      hw/arm/iotkit: Wire up the S32KTIMER
      hw/misc/iotkit-sysctl: Implement IoTKit system control element
      hw/misc/iotkit-sysinfo: Implement IoTKit system information block
      hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks
      hw/misc/tz-msc: Model TrustZone Master Security Controller
      hw/misc/iotkit-secctl: Wire up registers for controlling MSCs
      hw/arm/iotkit: Wire up the lines for MSCs
      hw/arm/mps2-tz: Create PL081s and MSCs
      hw/ssi/pl022: Allow use as embedded-struct device
      hw/ssi/pl022: Set up reset function in class init
      hw/ssi/pl022: Don't directly call vmstate_register()
      hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init
      hw/ssi/pl022: Correct wrong value for PL022_INT_RT
      hw/ssi/pl022: Correct wrong DMACR and ICR handling
      hw/arm/mps2-tz: Instantiate SPI controllers
      hw/arm/mps2-tz: Fix MPS2 SCC config register values
      target/arm: Untabify translate.c
      target/arm: Untabify iwmmxt_helper.c
      target/arm: Remove a handful of stray tabs
      hw/misc/bcm2835_fb: Move config fields to their own struct
      hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig
      hw/display/bcm2835_fb: Drop unused size and pitch fields
      hw/display/bcm2835_fb: Reset resolution, etc correctly
      hw/display/bcm2835_fb: Abstract out calculation of pitch, size
      hw/display/bcm2835_fb: Fix handling of virtual framebuffer
      hw/display/bcm2835_fb: Validate config settings
      hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config
      hw/arm/mps2: Fix ID register errors on AN511 and AN385

Richard Henderson (4):
      softfloat: Add scaling int-to-float routines
      softfloat: Add scaling float-to-int routines
      target/arm: Use the int-to-float-scale softfloat routines
      target/arm: Use the float-to-int-scale softfloat routines

hw/misc/Makefile.objs                  |   3 +
 hw/timer/Makefile.objs                 |   1 +
 include/fpu/softfloat.h                | 169 +++++++---
 include/hw/arm/iotkit.h                |  25 +-
 include/hw/display/bcm2835_fb.h        |  59 +++-
 include/hw/misc/iotkit-secctl.h        |  14 +
 include/hw/misc/iotkit-sysctl.h        |  49 +++
 include/hw/misc/iotkit-sysinfo.h       |  37 +++
 include/hw/misc/mps2-fpgaio.h          |  10 +
 include/hw/misc/tz-msc.h               |  79 +++++
 include/hw/ssi/pl022.h                 |  51 +++
 include/hw/timer/cmsdk-apb-dualtimer.h |  72 ++++
 target/arm/cpu.h                       |  16 +-
 fpu/softfloat.c                        | 579 ++++++++++++++++++++++++++-------
 hw/arm/boot.c                          |  11 +
 hw/arm/fsl-imx6ul.c                    |   4 +
 hw/arm/fsl-imx7.c                      |   4 +
 hw/arm/highbank.c                      |   6 +
 hw/arm/iotkit.c                        | 114 ++++++-
 hw/arm/mps2-tz.c                       | 142 +++++++-
 hw/arm/mps2.c                          |  17 +-
 hw/arm/vexpress.c                      |  64 +++-
 hw/cpu/a15mpcore.c                     |  31 +-
 hw/display/bcm2835_fb.c                | 218 ++++++++-----
 hw/intc/arm_gic.c                      |   2 +-
 hw/misc/bcm2835_property.c             | 123 ++++---
 hw/misc/iotkit-secctl.c                |  73 ++++-
 hw/misc/iotkit-sysctl.c                | 261 +++++++++++++++
 hw/misc/iotkit-sysinfo.c               | 128 ++++++++
 hw/misc/mps2-fpgaio.c                  | 146 ++++++++-
 hw/misc/tz-msc.c                       | 308 ++++++++++++++++++
 hw/ssi/pl022.c                         |  57 ++--
 hw/timer/cmsdk-apb-dualtimer.c         | 515 +++++++++++++++++++++++++++++
 target/arm/arm-semi.c                  |   2 +-
 target/arm/helper.c                    | 342 +++++++++++++------
 target/arm/iwmmxt_helper.c             | 234 ++++++-------
 target/arm/translate.c                 | 122 +++----
 MAINTAINERS                            |  10 +
 default-configs/arm-softmmu.mak        |   4 +
 hw/misc/trace-events                   |  16 +
 hw/timer/trace-events                  |   5 +
 41 files changed, 3405 insertions(+), 718 deletions(-)
 create mode 100644 include/hw/misc/iotkit-sysctl.h
 create mode 100644 include/hw/misc/iotkit-sysinfo.h
 create mode 100644 include/hw/misc/tz-msc.h
 create mode 100644 include/hw/ssi/pl022.h
 create mode 100644 include/hw/timer/cmsdk-apb-dualtimer.h
 create mode 100644 hw/misc/iotkit-sysctl.c
 create mode 100644 hw/misc/iotkit-sysinfo.c
 create mode 100644 hw/misc/tz-msc.c
 create mode 100644 hw/timer/cmsdk-apb-dualtimer.c