| 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: | 1 | A random mix of items here, nothing very major. v2 is just |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | 2 | squashing in the fix for the clang unused-function error. |
| 3 | combining stage 1 and stage 2 attrs. | ||
| 4 | 3 | ||
| 5 | thanks | 4 | thanks |
| 6 | -- PMM | 5 | -- PMM |
| 7 | 6 | ||
| 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | ||
| 9 | 7 | ||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | 8 | The following changes since commit d0dff238a87fa81393ed72754d4dc8b09e50b08b: |
| 11 | 9 | ||
| 12 | are available in the Git repository at: | 10 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20170206' into staging (2017-02-07 15:29:26 +0000) |
| 13 | 11 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 | 12 | are available in the git repository at: |
| 15 | 13 | ||
| 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: | 14 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170207-1 |
| 17 | 15 | ||
| 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) | 16 | for you to fetch changes up to aecfbbc97a2e52bbee34a53c32f961a182046a95: |
| 17 | |||
| 18 | stellaris: Use the 'unimplemented' device for parts we don't implement (2017-02-07 18:55:15 +0000) | ||
| 19 | 19 | ||
| 20 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 21 | target-arm: Fix bug where we weren't initializing | 21 | target-arm: |
| 22 | guarded bit state when combining S1/S2 attrs | 22 | * new "unimplemented" device for stubbing out devices in a |
| 23 | system model so accesses can be logged | ||
| 24 | * stellaris: document the SoC memory map | ||
| 25 | * arm: create instruction syndromes for AArch32 data aborts | ||
| 26 | * arm: Correctly handle watchpoints for BE32 CPUs | ||
| 27 | * Fix Thumb-1 BE32 execution and disassembly | ||
| 28 | * arm: Add cfgend parameter for ARM CPU selection | ||
| 29 | * sd: sdhci: check data length during dma_memory_read | ||
| 30 | * aspeed: add a watchdog controller | ||
| 31 | * integratorcp: adding vmstate for save/restore | ||
| 23 | 32 | ||
| 24 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
| 25 | Richard Henderson (2): | 34 | Cédric Le Goater (2): |
| 26 | target/arm: PTE bit GP only applies to stage1 | 35 | wdt: Add Aspeed watchdog device model |
| 27 | target/arm: Copy guarded bit in combine_cacheattrs | 36 | aspeed: add a watchdog controller |
| 28 | 37 | ||
| 29 | target/arm/ptw.c | 11 ++++++----- | 38 | Julian Brown (4): |
| 30 | 1 file changed, 6 insertions(+), 5 deletions(-) | 39 | hw/arm/integratorcp: Support specifying features via -cpu |
| 40 | target/arm: Add cfgend parameter for ARM CPU selection. | ||
| 41 | Fix Thumb-1 BE32 execution and disassembly. | ||
| 42 | arm: Correctly handle watchpoints for BE32 CPUs | ||
| 43 | |||
| 44 | Pavel Dovgalyuk (1): | ||
| 45 | integratorcp: adding vmstate for save/restore | ||
| 46 | |||
| 47 | Peter Maydell (5): | ||
| 48 | target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode | ||
| 49 | target/arm: A32, T32: Create Instruction Syndromes for Data Aborts | ||
| 50 | stellaris: Document memory map and which SoC devices are unimplemented | ||
| 51 | hw/misc: New "unimplemented" sysbus device | ||
| 52 | stellaris: Use the 'unimplemented' device for parts we don't implement | ||
| 53 | |||
| 54 | Prasad J Pandit (1): | ||
| 55 | sd: sdhci: check data length during dma_memory_read | ||
| 56 | |||
| 57 | hw/misc/Makefile.objs | 2 + | ||
| 58 | hw/watchdog/Makefile.objs | 1 + | ||
| 59 | include/disas/bfd.h | 7 ++ | ||
| 60 | include/hw/arm/aspeed_soc.h | 2 + | ||
| 61 | include/hw/misc/unimp.h | 39 +++++++ | ||
| 62 | include/hw/watchdog/wdt_aspeed.h | 32 ++++++ | ||
| 63 | include/qom/cpu.h | 3 + | ||
| 64 | target/arm/arm_ldst.h | 10 +- | ||
| 65 | target/arm/cpu.h | 7 ++ | ||
| 66 | target/arm/internals.h | 5 + | ||
| 67 | target/arm/translate.h | 14 +++ | ||
| 68 | disas.c | 1 + | ||
| 69 | exec.c | 1 + | ||
| 70 | hw/arm/aspeed_soc.c | 13 +++ | ||
| 71 | hw/arm/integratorcp.c | 78 +++++++++++++- | ||
| 72 | hw/arm/stellaris.c | 48 +++++++++ | ||
| 73 | hw/misc/unimp.c | 107 +++++++++++++++++++ | ||
| 74 | hw/sd/sdhci.c | 2 +- | ||
| 75 | hw/watchdog/wdt_aspeed.c | 225 +++++++++++++++++++++++++++++++++++++++ | ||
| 76 | qom/cpu.c | 6 ++ | ||
| 77 | target/arm/cpu.c | 39 +++++++ | ||
| 78 | target/arm/op_helper.c | 22 ++++ | ||
| 79 | target/arm/translate-a64.c | 14 --- | ||
| 80 | target/arm/translate.c | 193 ++++++++++++++++++++++++--------- | ||
| 81 | 24 files changed, 801 insertions(+), 70 deletions(-) | ||
| 82 | create mode 100644 include/hw/misc/unimp.h | ||
| 83 | create mode 100644 include/hw/watchdog/wdt_aspeed.h | ||
| 84 | create mode 100644 hw/misc/unimp.c | ||
| 85 | create mode 100644 hw/watchdog/wdt_aspeed.c | ||
| 86 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The guarded bit comes from the stage1 walk. | ||
| 4 | |||
| 5 | Fixes: Coverity CID 1507929 | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 1 + | ||
| 12 | 1 file changed, 1 insertion(+) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, | ||
| 19 | |||
| 20 | assert(!s1.is_s2_format); | ||
| 21 | ret.is_s2_format = false; | ||
| 22 | + ret.guarded = s1.guarded; | ||
| 23 | |||
| 24 | if (s1.attrs == 0xf0) { | ||
| 25 | tagged = true; | ||
| 26 | -- | ||
| 27 | 2.34.1 | diff view generated by jsdifflib |