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[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

Weiwei Li posted 1 patch 2 years, 10 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230330034636.44585-1-liweiwei@iscas.ac.cn
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
1 file changed, 2 insertions(+)
[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Posted by Weiwei Li 2 years, 10 months ago 
decode_save_opc() will not work for generate_exception(), since 0 is passed
to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
not be restored in this case.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index 9248b48c36..4b730cd492 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -20,6 +20,8 @@
 static bool check_access(DisasContext *ctx)
 {
     if (!ctx->hlsx) {
+        tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
+                       offsetof(CPURISCVState, bins));
         if (ctx->virt_enabled) {
             generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
         } else {
-- 
2.25.1
Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Posted by Alistair Francis 2 years, 10 months ago 
On Thu, Mar 30, 2023 at 1:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
>  static bool check_access(DisasContext *ctx)
>  {
>      if (!ctx->hlsx) {
> +        tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> +                       offsetof(CPURISCVState, bins));
>          if (ctx->virt_enabled) {
>              generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
>          } else {
> --
> 2.25.1
>
>
Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Posted by Alistair Francis 2 years, 10 months ago 
On Thu, Mar 30, 2023 at 1:47 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
>  static bool check_access(DisasContext *ctx)
>  {
>      if (!ctx->hlsx) {
> +        tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> +                       offsetof(CPURISCVState, bins));
>          if (ctx->virt_enabled) {
>              generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
>          } else {
> --
> 2.25.1
>
>
Re: [PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Posted by Daniel Henrique Barboza 2 years, 10 months ago 

On 3/30/23 00:46, Weiwei Li wrote:
> decode_save_opc() will not work for generate_exception(), since 0 is passed
> to riscv_raise_exception() as pc in helper_raise_exception(), and bins will
> not be restored in this case.
> 
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>


>   target/riscv/insn_trans/trans_rvh.c.inc | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
> index 9248b48c36..4b730cd492 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -20,6 +20,8 @@
>   static bool check_access(DisasContext *ctx)
>   {
>       if (!ctx->hlsx) {
> +        tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
> +                       offsetof(CPURISCVState, bins));
>           if (ctx->virt_enabled) {
>               generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
>           } else {

Patchew 2.1-devel-b67e4c2

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