remove MISA ext_N flags from cpu->cfg,

[PATCH v3 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()

Posted by Daniel Henrique Barboza 2 years, 10 months ago

This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.

riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
 target/riscv/cpu.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3eb3b7dc59..036d6191ca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -396,11 +396,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     RISCVCPU *cpu = RISCV_CPU(obj);
 
-    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV64, RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_11_0);
 
     cpu->cfg.ext_g = true;
-    cpu->cfg.ext_icsr = true;
     cpu->cfg.ext_zfh = true;
     cpu->cfg.mmu = true;
     cpu->cfg.ext_xtheadba = true;
-- 
2.39.2

Re: [PATCH v3 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()

Posted by Alistair Francis 2 years, 10 months ago

On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> This CPU is enabling G via cfg.ext_g and, at the same time, setting
> IMAFD in set_misa() and cfg.ext_icsr.
>
> riscv_cpu_validate_set_extensions() is already doing that, so there's no
> need for cpu_init() setups to worry about setting G and its extensions.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3eb3b7dc59..036d6191ca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -396,11 +396,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      RISCVCPU *cpu = RISCV_CPU(obj);
>
> -    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +    set_misa(env, MXL_RV64, RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_11_0);
>
>      cpu->cfg.ext_g = true;
> -    cpu->cfg.ext_icsr = true;
>      cpu->cfg.ext_zfh = true;
>      cpu->cfg.mmu = true;
>      cpu->cfg.ext_xtheadba = true;
> --
> 2.39.2
>
>