| 1 | The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a: | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
|---|---|---|---|
| 2 | we were using uninitialized data for the guarded bit when | ||
| 3 | combining stage 1 and stage 2 attrs. | ||
| 2 | 4 | ||
| 3 | Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000) | 5 | thanks |
| 6 | -- PMM | ||
| 7 | |||
| 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: | ||
| 9 | |||
| 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) | ||
| 4 | 11 | ||
| 5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 6 | 13 | ||
| 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
| 8 | 15 | ||
| 9 | for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
| 10 | 17 | ||
| 11 | target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
| 12 | 19 | ||
| 13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 14 | target-arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
| 15 | * fix part of the "TCG-disabled builds are broken" issue | 22 | guarded bit state when combining S1/S2 attrs |
| 16 | 23 | ||
| 17 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 18 | Philippe Mathieu-Daudé (1): | 25 | Richard Henderson (2): |
| 19 | target/arm/gdbstub: Only advertise M-profile features if TCG available | 26 | target/arm: PTE bit GP only applies to stage1 |
| 27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
| 20 | 28 | ||
| 21 | target/arm/gdbstub.c | 5 +++-- | 29 | target/arm/ptw.c | 11 ++++++----- |
| 22 | 1 file changed, 3 insertions(+), 2 deletions(-) | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
| 23 | diff view generated by jsdifflib |
New patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 1 | 2 | ||
| 3 | Only perform the extract of GP during the stage1 walk. | ||
| 4 | |||
| 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/ptw.c | 10 +++++----- | ||
| 12 | 1 file changed, 5 insertions(+), 5 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/ptw.c | ||
| 17 | +++ b/target/arm/ptw.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 19 | result->f.attrs.secure = false; | ||
| 20 | } | ||
| 21 | |||
| 22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (regime_is_stage2(mmu_idx)) { | ||
| 28 | result->cacheattrs.is_s2_format = true; | ||
| 29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 31 | assert(attrindx <= 7); | ||
| 32 | result->cacheattrs.is_s2_format = false; | ||
| 33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
| 34 | + | ||
| 35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
| 36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
| 37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
| 38 | + } | ||
| 39 | } | ||
| 40 | |||
| 41 | /* | ||
| 42 | -- | ||
| 43 | 2.34.1 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Cortex-M profile is only emulable from TCG accelerator. Restrict | 3 | The guarded bit comes from the stage1 walk. |
| 4 | the GDBstub features to its availability in order to avoid a link | ||
| 5 | error when TCG is not enabled: | ||
| 6 | 4 | ||
| 7 | Undefined symbols for architecture arm64: | 5 | Fixes: Coverity CID 1507929 |
| 8 | "_arm_v7m_get_sp_ptr", referenced from: | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | _m_sysreg_get in target_arm_gdbstub.c.o | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | "_arm_v7m_mrs_control", referenced from: | 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org |
| 11 | _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o | ||
| 12 | ld: symbol(s) not found for architecture arm64 | ||
| 13 | clang: error: linker command failed with exit code 1 (use -v to see invocation) | ||
| 14 | |||
| 15 | Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext") | ||
| 16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 19 | Message-id: 20230322142902.69511-3-philmd@linaro.org | ||
| 20 | [PMM: add #include since I cherry-picked this patch from the series] | ||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 22 | --- | 10 | --- |
| 23 | target/arm/gdbstub.c | 5 +++-- | 11 | target/arm/ptw.c | 1 + |
| 24 | 1 file changed, 3 insertions(+), 2 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
| 25 | 13 | ||
| 26 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
| 27 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 28 | --- a/target/arm/gdbstub.c | 16 | --- a/target/arm/ptw.c |
| 29 | +++ b/target/arm/gdbstub.c | 17 | +++ b/target/arm/ptw.c |
| 30 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, |
| 31 | #include "cpu.h" | 19 | |
| 32 | #include "exec/gdbstub.h" | 20 | assert(!s1.is_s2_format); |
| 33 | #include "gdbstub/helpers.h" | 21 | ret.is_s2_format = false; |
| 34 | +#include "sysemu/tcg.h" | 22 | + ret.guarded = s1.guarded; |
| 35 | #include "internals.h" | 23 | |
| 36 | #include "cpregs.h" | 24 | if (s1.attrs == 0xf0) { |
| 37 | 25 | tagged = true; | |
| 38 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
| 39 | 2, "arm-vfp-sysregs.xml", 0); | ||
| 40 | } | ||
| 41 | } | ||
| 42 | - if (cpu_isar_feature(aa32_mve, cpu)) { | ||
| 43 | + if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { | ||
| 44 | gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, | ||
| 45 | 1, "arm-m-profile-mve.xml", 0); | ||
| 46 | } | ||
| 47 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
| 48 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
| 49 | "system-registers.xml", 0); | ||
| 50 | |||
| 51 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
| 52 | + if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { | ||
| 53 | gdb_register_coprocessor(cs, | ||
| 54 | arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
| 55 | arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
| 56 | -- | 26 | -- |
| 57 | 2.34.1 | 27 | 2.34.1 |
| 58 | |||
| 59 | diff view generated by jsdifflib |