[PULL 0/1] target-arm queue
[PULL v2 00/31] target-arm queue
1
The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
1
v2: fixes two build failures, and adds the mips/malta RNG reset patch.
2
2
3
Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
3
thanks
4
-- PMM
5
6
The following changes since commit 344744e148e6e865f5a57e745b02a87e5ea534ad:
7
8
Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2022-10-26 10:53:49 -0400)
4
9
5
are available in the Git repository at:
10
are available in the Git repository at:
6
11
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221027
8
13
9
for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
14
for you to fetch changes up to 6233a138599bea89ad683b883dca38388f12fd2d:
10
15
11
target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
16
mips/malta: pass RNG seed via env var and re-randomize on reboot (2022-10-27 11:47:45 +0100)
12
17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
target-arm queue:
19
target-arm queue:
15
* fix part of the "TCG-disabled builds are broken" issue
20
* Implement FEAT_E0PD
21
* Implement FEAT_HAFDBS
22
* honor HCR_E2H and HCR_TGE in arm_excp_unmasked()
23
* hw/arm/virt: Fix devicetree warnings about the virtio-iommu node
24
* hw/core/resettable: fix reset level counting
25
* hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset()
26
* imx: reload cmp timer outside of the reload ptimer transaction
27
* x86: do not re-randomize RNG seed on snapshot load
28
* m68k/virt: do not re-randomize RNG seed on snapshot load
29
* m68k/q800: do not re-randomize RNG seed on snapshot load
30
* arm: re-randomize rng-seed on reboot
31
* riscv: re-randomize rng-seed on reboot
32
* mips/boston: re-randomize rng-seed on reboot
33
* openrisc: re-randomize rng-seed on reboot
34
* rx: re-randomize rng-seed on reboot
16
35
17
----------------------------------------------------------------
36
----------------------------------------------------------------
18
Philippe Mathieu-Daudé (1):
37
Ake Koomsin (1):
19
target/arm/gdbstub: Only advertise M-profile features if TCG available
38
target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked()
20
39
21
target/arm/gdbstub.c | 5 +++--
40
Axel Heider (1):
22
1 file changed, 3 insertions(+), 2 deletions(-)
41
target/imx: reload cmp timer outside of the reload ptimer transaction
23
42
43
Damien Hedde (1):
44
hw/core/resettable: fix reset level counting
45
46
Jason A. Donenfeld (11):
47
reset: allow registering handlers that aren't called by snapshot loading
48
device-tree: add re-randomization helper function
49
x86: do not re-randomize RNG seed on snapshot load
50
arm: re-randomize rng-seed on reboot
51
riscv: re-randomize rng-seed on reboot
52
m68k/virt: do not re-randomize RNG seed on snapshot load
53
m68k/q800: do not re-randomize RNG seed on snapshot load
54
mips/boston: re-randomize rng-seed on reboot
55
openrisc: re-randomize rng-seed on reboot
56
rx: re-randomize rng-seed on reboot
57
mips/malta: pass RNG seed via env var and re-randomize on reboot
58
59
Jean-Philippe Brucker (1):
60
hw/arm/virt: Fix devicetree warnings about the virtio-iommu node
61
62
Peter Maydell (2):
63
target/arm: Implement FEAT_E0PD
64
hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset()
65
66
Richard Henderson (14):
67
target/arm: Introduce regime_is_stage2
68
target/arm: Add ptw_idx to S1Translate
69
target/arm: Add isar predicates for FEAT_HAFDBS
70
target/arm: Extract HA and HD in aa64_va_parameters
71
target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw
72
target/arm: Add ARMFault_UnsuppAtomicUpdate
73
target/arm: Remove loop from get_phys_addr_lpae
74
target/arm: Fix fault reporting in get_phys_addr_lpae
75
target/arm: Don't shift attrs in get_phys_addr_lpae
76
target/arm: Consider GP an attribute in get_phys_addr_lpae
77
target/arm: Tidy merging of attributes from descriptor and table
78
target/arm: Implement FEAT_HAFDBS, access flag portion
79
target/arm: Implement FEAT_HAFDBS, dirty bit portion
80
target/arm: Use the max page size in a 2-stage ptw
81
82
docs/devel/reset.rst | 8 +-
83
docs/system/arm/emulation.rst | 2 +
84
qapi/run-state.json | 6 +-
85
include/hw/boards.h | 2 +-
86
include/sysemu/device_tree.h | 9 +
87
include/sysemu/reset.h | 5 +-
88
target/arm/cpu.h | 15 ++
89
target/arm/internals.h | 30 +++
90
hw/arm/aspeed.c | 4 +-
91
hw/arm/boot.c | 2 +
92
hw/arm/mps2-tz.c | 4 +-
93
hw/arm/virt.c | 5 +-
94
hw/core/reset.c | 17 +-
95
hw/core/resettable.c | 3 +-
96
hw/hppa/machine.c | 4 +-
97
hw/hyperv/hyperv.c | 2 +-
98
hw/i386/microvm.c | 4 +-
99
hw/i386/pc.c | 6 +-
100
hw/i386/x86.c | 2 +-
101
hw/m68k/q800.c | 33 ++-
102
hw/m68k/virt.c | 20 +-
103
hw/mips/boston.c | 3 +
104
hw/mips/malta.c | 27 +++
105
hw/openrisc/boot.c | 3 +
106
hw/ppc/pegasos2.c | 4 +-
107
hw/ppc/pnv.c | 4 +-
108
hw/ppc/spapr.c | 4 +-
109
hw/riscv/boot.c | 3 +
110
hw/rx/rx-gdbsim.c | 3 +
111
hw/s390x/s390-virtio-ccw.c | 4 +-
112
hw/timer/imx_epit.c | 9 +-
113
migration/savevm.c | 2 +-
114
softmmu/device_tree.c | 21 ++
115
softmmu/runstate.c | 11 +-
116
target/arm/cpu.c | 24 +-
117
target/arm/cpu64.c | 2 +
118
target/arm/helper.c | 31 ++-
119
target/arm/ptw.c | 525 ++++++++++++++++++++++++++++--------------
120
38 files changed, 600 insertions(+), 263 deletions(-)
diff view generated by jsdifflib
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Cortex-M profile is only emulable from TCG accelerator. Restrict
4
the GDBstub features to its availability in order to avoid a link
5
error when TCG is not enabled:
6
7
Undefined symbols for architecture arm64:
8
"_arm_v7m_get_sp_ptr", referenced from:
9
_m_sysreg_get in target_arm_gdbstub.c.o
10
"_arm_v7m_mrs_control", referenced from:
11
_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
12
ld: symbol(s) not found for architecture arm64
13
clang: error: linker command failed with exit code 1 (use -v to see invocation)
14
15
Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
19
Message-id: 20230322142902.69511-3-philmd@linaro.org
20
[PMM: add #include since I cherry-picked this patch from the series]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
target/arm/gdbstub.c | 5 +++--
24
1 file changed, 3 insertions(+), 2 deletions(-)
25
26
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/gdbstub.c
29
+++ b/target/arm/gdbstub.c
30
@@ -XXX,XX +XXX,XX @@
31
#include "cpu.h"
32
#include "exec/gdbstub.h"
33
#include "gdbstub/helpers.h"
34
+#include "sysemu/tcg.h"
35
#include "internals.h"
36
#include "cpregs.h"
37
38
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
39
2, "arm-vfp-sysregs.xml", 0);
40
}
41
}
42
- if (cpu_isar_feature(aa32_mve, cpu)) {
43
+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
44
gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
45
1, "arm-m-profile-mve.xml", 0);
46
}
47
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
48
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
49
"system-registers.xml", 0);
50
51
- if (arm_feature(env, ARM_FEATURE_M)) {
52
+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
53
gdb_register_coprocessor(cs,
54
arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
55
arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
56
--
57
2.34.1
58
59
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.