[PULL 0/1] target-arm queue
[PULL v3 00/20] target-arm queue
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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v1->v2: add system/index to docs/index.rst
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v2->v3: fix format string issues for OSX
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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The following changes since commit b7c359c748a2e3ccb97a184b9739feb2cd48de2f:
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Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.0-pull-request' into staging (2020-01-23 14:38:43 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200123-3
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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for you to fetch changes up to 9805a6b7d03a23e16d6499d16882094db490683a:
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330 (2020-01-23 15:52:34 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* fix part of the "TCG-disabled builds are broken" issue
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* fix bug in PAuth emulation
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* add PMU to Cortex-R5, Cortex-R5F
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* qemu-nbd: Convert documentation to rST
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* qemu-block-drivers: Convert documentation to rST
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* Fix Exynos4210 UART DMA support
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* Various minor code cleanups
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----------------------------------------------------------------
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----------------------------------------------------------------
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Andrew Jones (1):
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target/arm/arch_dump: Add SVE notes
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Clement Deschamps (1):
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target/arm: add PMU feature to cortex-r5 and cortex-r5f
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Guenter Roeck (8):
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dma/pl330: Convert to support tracing
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hw/core/or-irq: Increase limit of or-lines to 48
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hw/arm/exynos4210: Fix DMA initialization
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hw/char/exynos4210_uart: Convert to support tracing
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hw/char/exynos4210_uart: Implement post_load function
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hw/char/exynos4210_uart: Implement Rx FIFO level triggers and timeouts
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hw/char/exynos4210_uart: Add receive DMA support
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hw/arm/exynos4210: Connect serial port DMA busy signals with pl330
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Keqian Zhu (2):
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hw/acpi: Remove extra indent in ACPI GED hotplug cb
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hw/arm: Use helper function to trigger hotplug handler plug
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Peter Maydell (3):
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qemu-nbd: Convert invocation documentation to rST
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docs: Create stub system manual
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qemu-block-drivers: Convert to rST
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Philippe Mathieu-Daudé (1):
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Philippe Mathieu-Daudé (1):
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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hw/misc/stm32f4xx_syscfg: Fix copy/paste error
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target/arm/gdbstub.c | 5 +++--
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Richard Henderson (3):
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1 file changed, 3 insertions(+), 2 deletions(-)
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tests/tcg/aarch64: Fix compilation parameters for pauth-%
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tests/tcg/aarch64: Add pauth-3
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tests/tcg/aarch64: Add pauth-4
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Vincent Dehors (1):
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target/arm: Fix PAuth sbox functions
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Makefile | 37 +-
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tests/tcg/aarch64/Makefile.softmmu-target | 5 +-
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tests/tcg/aarch64/Makefile.target | 3 +-
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include/elf.h | 1 +
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include/hw/arm/exynos4210.h | 4 +
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include/hw/or-irq.h | 2 +-
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target/arm/cpu.h | 25 +
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hw/acpi/generic_event_device.c | 2 +-
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hw/arm/exynos4210.c | 77 ++-
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hw/arm/virt.c | 6 +-
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hw/char/exynos4210_uart.c | 245 +++++---
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hw/dma/pl330.c | 88 +--
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hw/misc/stm32f4xx_syscfg.c | 2 +-
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target/arm/arch_dump.c | 124 +++-
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target/arm/cpu.c | 1 +
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target/arm/kvm64.c | 24 -
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target/arm/pauth_helper.c | 4 +-
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tests/tcg/aarch64/pauth-1.c | 2 -
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tests/tcg/aarch64/pauth-2.c | 2 -
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tests/tcg/aarch64/pauth-4.c | 25 +
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tests/tcg/aarch64/system/pauth-3.c | 40 ++
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MAINTAINERS | 1 +
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docs/index.html.in | 1 +
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docs/index.rst | 2 +-
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docs/interop/conf.py | 4 +-
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docs/interop/index.rst | 1 +
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docs/interop/qemu-nbd.rst | 263 ++++++++
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docs/interop/qemu-option-trace.rst.inc | 30 +
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docs/qemu-block-drivers.texi | 889 ---------------------------
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docs/system/conf.py | 22 +
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docs/system/index.rst | 17 +
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docs/system/qemu-block-drivers.rst | 985 ++++++++++++++++++++++++++++++
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hw/char/trace-events | 20 +
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hw/dma/trace-events | 24 +
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qemu-doc.texi | 18 -
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qemu-nbd.texi | 214 -------
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qemu-option-trace.texi | 4 +
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qemu-options.hx | 2 +-
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38 files changed, 1898 insertions(+), 1318 deletions(-)
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create mode 100644 tests/tcg/aarch64/pauth-4.c
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create mode 100644 tests/tcg/aarch64/system/pauth-3.c
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create mode 100644 docs/interop/qemu-nbd.rst
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create mode 100644 docs/interop/qemu-option-trace.rst.inc
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delete mode 100644 docs/qemu-block-drivers.texi
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create mode 100644 docs/system/conf.py
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create mode 100644 docs/system/index.rst
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create mode 100644 docs/system/qemu-block-drivers.rst
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delete mode 100644 qemu-nbd.texi
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diff view generated by jsdifflib
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
Deleted patch
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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