[PULL 0/1] target-arm queue
[Qemu-devel] [PULL v2 00/25] target-arm queue
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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v2: drop a couple of RTH's patches that he wants to rework.
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4:
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842:
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* fix part of the "TCG-disabled builds are broken" issue
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* gdbstub: Send a reply to the vKill packet
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* Improve codegen for neon min/max and saturating arithmetic
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* Fix a bug in clearing FPSCR exception status bits
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* hw/arm/armsse: Fix miswiring of expansion IRQs
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* hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
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* MAINTAINERS: Remove Peter Crosthwaite from various entries
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* arm: Allow system registers for KVM guests to be changed by QEMU code
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* linux-user: support HWCAP_CPUID which exposes ID registers to user code
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* Fix bug in 128-bit cmpxchg for BE Arm guests
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* Implement (no-op) HACR_EL2
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* Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
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----------------------------------------------------------------
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----------------------------------------------------------------
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Philippe Mathieu-Daudé (1):
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Aaron Lindsay OS (1):
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
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target/arm/gdbstub.c | 5 +++--
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Alex Bennée (5):
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1 file changed, 3 insertions(+), 2 deletions(-)
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target/arm: relax permission checks for HWCAP_CPUID registers
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target/arm: expose CPUID registers to userspace
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target/arm: expose MPIDR_EL1 to userspace
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target/arm: expose remaining CPUID registers as RAZ
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linux-user/elfload: enable HWCAP_CPUID for AArch64
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Catherine Ho (1):
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target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
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Peter Maydell (5):
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target/arm: Implement HACR_EL2
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arm: Allow system registers for KVM guests to be changed by QEMU code
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MAINTAINERS: Remove Peter Crosthwaite from various entries
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hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
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hw/arm/armsse: Fix miswiring of expansion IRQs
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Richard Henderson (12):
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target/arm: Rely on optimization within tcg_gen_gvec_or
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target/arm: Use vector minmax expanders for aarch64
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target/arm: Use vector minmax expanders for aarch32
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target/arm: Use tcg integer min/max primitives for neon
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target/arm: Remove neon min/max helpers
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target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
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target/arm: Fix arm_cpu_dump_state vs FPSCR
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target/arm: Split out flags setting from vfp compares
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target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
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target/arm: Split out FPSCR.QC to a vector field
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target/arm: Use vector operations for saturation
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target/arm: Add missing clear_tail calls
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Sandra Loosemore (1):
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gdbstub: Send a reply to the vKill packet.
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target/arm/cpu.h | 50 +++++++++-
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target/arm/helper.h | 45 ++++++---
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target/arm/translate.h | 4 +
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gdbstub.c | 1 +
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hw/arm/armsse.c | 2 +-
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hw/intc/armv7m_nvic.c | 4 +-
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linux-user/elfload.c | 1 +
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target/arm/helper-a64.c | 4 +-
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target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++++++---------
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target/arm/kvm32.c | 20 +---
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target/arm/kvm64.c | 2 +
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target/arm/machine.c | 2 +-
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target/arm/neon_helper.c | 14 +--
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target/arm/translate-a64.c | 77 ++++++---------
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target/arm/translate-sve.c | 6 +-
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target/arm/translate.c | 219 ++++++++++++++++++++++++++++++++++---------
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target/arm/vec_helper.c | 134 +++++++++++++++++++++++++-
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MAINTAINERS | 4 -
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18 files changed, 622 insertions(+), 195 deletions(-)
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diff view generated by jsdifflib
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
Deleted patch
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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