[PULL 0/1] target-arm queue
[Qemu-devel] [PULL v2 00/44] target-arm queue
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The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
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v1->v2 changes: drop the "convert FEATURE_THUMB2EE" patch as
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it broke compilation on arm hosts (conversion of KVM related
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code had been forgotten)
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Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
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thanks
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-- PMM
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The following changes since commit 13399aad4fa87b2878c49d02a5d3bafa6c966ba3:
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Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-10-22' into staging (2018-10-23 17:20:23 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181024
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for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
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for you to fetch changes up to 93f379b0c43617b1361f742f261479eaed4959cb:
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target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
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target/arm: Only flush tlb if ASID changes (2018-10-24 07:51:37 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* fix part of the "TCG-disabled builds are broken" issue
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* ssi-sd: Make devices picking up backends unavailable with -device
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* Add support for VCPU event states
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* Move towards making ID registers the source of truth for
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whether a guest CPU implements a feature, rather than having
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parallel ID registers and feature bit flags
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* Implement various HCR hypervisor trap/config bits
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* Get IL bit correct for v7 syndrome values
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* Report correct syndrome for FP/SIMD traps to Hyp mode
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* hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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* Refactor A32 Neon to use generic vector infrastructure
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* Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
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* net: cadence_gem: Report features correctly in ID register
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* Avoid some unnecessary TLB flushes on TTBR register writes
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----------------------------------------------------------------
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----------------------------------------------------------------
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Philippe Mathieu-Daudé (1):
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Dongjiu Geng (1):
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target/arm/gdbstub: Only advertise M-profile features if TCG available
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target/arm: Add support for VCPU event states
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target/arm/gdbstub.c | 5 +++--
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Edgar E. Iglesias (2):
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1 file changed, 3 insertions(+), 2 deletions(-)
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net: cadence_gem: Announce availability of priority queues
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net: cadence_gem: Announce 64bit addressing support
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Markus Armbruster (1):
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ssi-sd: Make devices picking up backends unavailable with -device
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Peter Maydell (10):
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target/arm: Improve debug logging of AArch32 exception return
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target/arm: Make switch_mode() file-local
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target/arm: Implement HCR.FB
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target/arm: Implement HCR.DC
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target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set
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target/arm: Implement HCR.VI and VF
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target/arm: Implement HCR.PTW
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target/arm: New utility function to extract EC from syndrome
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target/arm: Get IL bit correct for v7 syndrome values
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target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode
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Richard Henderson (29):
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target/arm: Move some system registers into a substructure
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target/arm: V8M should not imply V7VE
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target/arm: Convert v8 extensions from feature bits to isar tests
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target/arm: Convert division from feature bits to isar0 tests
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target/arm: Convert jazelle from feature bit to isar1 test
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target/arm: Convert sve from feature bit to aa64pfr0 test
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target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test
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target/arm: Hoist address increment for vector memory ops
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target/arm: Don't call tcg_clear_temp_count
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target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R
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target/arm: Promote consecutive memory ops for aa64
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target/arm: Mark some arrays const
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target/arm: Use gvec for NEON VDUP
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target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
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target/arm: Use gvec for NEON_3R_LOGIC insns
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target/arm: Use gvec for NEON_3R_VADD_VSUB insns
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target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
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target/arm: Use gvec for NEON_3R_VMUL
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target/arm: Use gvec for VSHR, VSHL
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target/arm: Use gvec for VSRA
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target/arm: Use gvec for VSRI, VSLI
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target/arm: Use gvec for NEON_3R_VML
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target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
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target/arm: Use gvec for NEON VLD all lanes
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target/arm: Reorg NEON VLD/VST all elements
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target/arm: Promote consecutive memory ops for aa32
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target/arm: Reorg NEON VLD/VST single element to one lane
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target/arm: Remove writefn from TTBR0_EL3
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target/arm: Only flush tlb if ASID changes
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Stewart Hildebrand (1):
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hw/arm/boot: Increase compliance with kernel arm64 boot protocol
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target/arm/cpu.h | 221 ++++++-
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target/arm/internals.h | 45 +-
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target/arm/kvm_arm.h | 24 +
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target/arm/translate.h | 21 +
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hw/arm/boot.c | 18 +
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hw/intc/armv7m_nvic.c | 12 +-
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hw/net/cadence_gem.c | 9 +-
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hw/sd/ssi-sd.c | 2 +
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linux-user/aarch64/signal.c | 4 +-
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linux-user/elfload.c | 58 +-
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linux-user/syscall.c | 10 +-
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target/arm/cpu.c | 238 +++----
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target/arm/cpu64.c | 148 +++--
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target/arm/helper.c | 395 ++++++++----
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target/arm/kvm.c | 60 ++
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target/arm/kvm32.c | 13 +
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target/arm/kvm64.c | 15 +-
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target/arm/machine.c | 25 +-
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target/arm/op_helper.c | 2 +-
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target/arm/translate-a64.c | 715 ++++-----------------
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target/arm/translate.c | 1451 ++++++++++++++++++++++++++++---------------
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21 files changed, 2013 insertions(+), 1473 deletions(-)
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diff view generated by jsdifflib
[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
Deleted patch
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From: Philippe Mathieu-Daudé <philmd@linaro.org>
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Cortex-M profile is only emulable from TCG accelerator. Restrict
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the GDBstub features to its availability in order to avoid a link
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error when TCG is not enabled:
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Undefined symbols for architecture arm64:
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"_arm_v7m_get_sp_ptr", referenced from:
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_m_sysreg_get in target_arm_gdbstub.c.o
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"_arm_v7m_mrs_control", referenced from:
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_arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
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ld: symbol(s) not found for architecture arm64
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clang: error: linker command failed with exit code 1 (use -v to see invocation)
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Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
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Message-id: 20230322142902.69511-3-philmd@linaro.org
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[PMM: add #include since I cherry-picked this patch from the series]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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+#include "sysemu/tcg.h"
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#include "internals.h"
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#include "cpregs.h"
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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2, "arm-vfp-sysregs.xml", 0);
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}
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}
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- if (cpu_isar_feature(aa32_mve, cpu)) {
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+ if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
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gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
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1, "arm-m-profile-mve.xml", 0);
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}
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
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"system-registers.xml", 0);
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- if (arm_feature(env, ARM_FEATURE_M)) {
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+ if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
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gdb_register_coprocessor(cs,
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arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
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arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
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--
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2.34.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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