[v1] target/riscv: Fix pointer mask related support

[PATCH 0/5] target/riscv: Fix pointer mask related support

Weiwei Li posted 5 patches 1 year ago

Diff against v2 v3 v3 v4 v5 v6 v7
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230327100027.61160-1-liweiwei@iscas.ac.cn

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.h           |  1 +
target/riscv/cpu_helper.c    | 25 +++++++++++++++++++++++--
target/riscv/csr.c           |  2 --
target/riscv/translate.c     | 16 ++++++++++++----
target/riscv/vector_helper.c |  5 ++++-
5 files changed, 40 insertions(+), 9 deletions(-)

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[PATCH 0/5] target/riscv: Fix pointer mask related support

Posted by Weiwei Li 1 year ago

This patchset tries to fix some problems in current implementation for pointer
mask extension, and add support for pointer mask of instruction fetch.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix

Weiwei Li (5):
  target/riscv: Fix effective address for pointer mask
  target/riscv: Use sign-extended data address when xl = 32
  target/riscv: Fix pointer mask transformation for vector address
  target/riscv: take xl into consideration for vector address
  target/riscv: Add pointer mask support for instruction fetch

 target/riscv/cpu.h           |  1 +
 target/riscv/cpu_helper.c    | 25 +++++++++++++++++++++++--
 target/riscv/csr.c           |  2 --
 target/riscv/translate.c     | 16 ++++++++++++----
 target/riscv/vector_helper.c |  5 ++++-
 5 files changed, 40 insertions(+), 9 deletions(-)

-- 
2.25.1