[v6] target/riscv: MSTATUS_SUM + cleanups

[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop

Posted by Richard Henderson 2 years, 10 months ago

These values are constant for every level of pte lookup.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/cpu_helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 833ea6d3fa..00f70a3dd5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -870,6 +870,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         return TRANSLATE_FAIL;
     }
 
+    bool pbmte = env->menvcfg & MENVCFG_PBMTE;
+    bool hade = env->menvcfg & MENVCFG_HADE;
+
+    if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
+        pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
+        hade = hade && (env->henvcfg & HENVCFG_HADE);
+    }
+
     int ptshift = (levels - 1) * ptidxbits;
     int i;
 
@@ -930,14 +938,6 @@ restart:
             return TRANSLATE_FAIL;
         }
 
-        bool pbmte = env->menvcfg & MENVCFG_PBMTE;
-        bool hade = env->menvcfg & MENVCFG_HADE;
-
-        if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
-            pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
-            hade = hade && (env->henvcfg & HENVCFG_HADE);
-        }
-
         if (riscv_cpu_sxl(env) == MXL_RV32) {
             ppn = pte >> PTE_PPN_SHIFT;
         } else if (pbmte || cpu->cfg.ext_svnapot) {
-- 
2.34.1

Re: [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop

Posted by Alistair Francis 2 years, 10 months ago

On Sat, Mar 25, 2023 at 9:56 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These values are constant for every level of pte lookup.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_helper.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 833ea6d3fa..00f70a3dd5 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -870,6 +870,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>          return TRANSLATE_FAIL;
>      }
>
> +    bool pbmte = env->menvcfg & MENVCFG_PBMTE;
> +    bool hade = env->menvcfg & MENVCFG_HADE;
> +
> +    if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
> +        pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> +        hade = hade && (env->henvcfg & HENVCFG_HADE);
> +    }
> +
>      int ptshift = (levels - 1) * ptidxbits;
>      int i;
>
> @@ -930,14 +938,6 @@ restart:
>              return TRANSLATE_FAIL;
>          }
>
> -        bool pbmte = env->menvcfg & MENVCFG_PBMTE;
> -        bool hade = env->menvcfg & MENVCFG_HADE;
> -
> -        if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) {
> -            pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
> -            hade = hade && (env->henvcfg & HENVCFG_HADE);
> -        }
> -
>          if (riscv_cpu_sxl(env) == MXL_RV32) {
>              ppn = pte >> PTE_PPN_SHIFT;
>          } else if (pbmte || cpu->cfg.ext_svnapot) {
> --
> 2.34.1
>
>