[PULL 0/8] target-arm queue
[PULL v2 00/57] target-arm queue
1
The following changes since commit aa9e7fa4689d1becb2faf67f65aafcbcf664f1ce:
1
Squashed in a trivial fix for 32-bit hosts:
2
2
3
Merge tag 'edk2-stable202302-20230320-pull-request' of https://gitlab.com/kraxel/qemu into staging (2023-03-20 13:43:35 +0000)
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
15
-- PMM
16
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
18
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
4
20
5
are available in the Git repository at:
21
are available in the Git repository at:
6
22
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230321
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
8
24
9
for you to fetch changes up to 5787d17a42f7af4bd117e5d6bfa54b1fdf93c255:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
10
26
11
target/arm: Don't advertise aarch64-pauth.xml to gdb (2023-03-21 13:19:08 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
12
28
13
----------------------------------------------------------------
29
----------------------------------------------------------------
14
target-arm queue:
30
target-arm queue:
15
* contrib/elf2dmp: Support Windows Server 2022
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
16
* hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings
32
* docs: Document which architecture extensions we emulate
17
* target/arm: Add Neoverse-N1 IMPDEF registers
33
* Fix bugs in M-profile FPCXT_NS accesses
18
* hw/usb/imx: Fix out of bounds access in imx_usbphy_read()
34
* First slice of MVE patches
19
* docs/system/arm/cpu-features.rst: Fix formatting
35
* Implement MTE3
20
* target/arm: Don't advertise aarch64-pauth.xml to gdb
36
* docs/system: arm: Add nRF boards description
21
37
22
----------------------------------------------------------------
38
----------------------------------------------------------------
23
Chen Baozi (1):
39
Alexandre Iooss (1):
24
target/arm: Add Neoverse-N1 registers
40
docs/system: arm: Add nRF boards description
25
41
26
Guenter Roeck (1):
42
Peter Collingbourne (1):
27
hw/usb/imx: Fix out of bounds access in imx_usbphy_read()
43
target/arm: Implement MTE3
28
44
29
Peter Maydell (3):
45
Peter Maydell (55):
30
hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
31
docs/system/arm/cpu-features.rst: Fix formatting
47
hw/acpi: Provide function acpi_ghes_present()
32
target/arm: Don't advertise aarch64-pauth.xml to gdb
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
33
101
34
Viktor Prutyanov (3):
102
docs/system/arm/emulation.rst | 103 ++++
35
contrib/elf2dmp: fix code style
103
docs/system/arm/nrf.rst | 51 ++
36
contrib/elf2dmp: move PE dir search to pe_get_data_dir_entry
104
docs/system/target-arm.rst | 7 +
37
contrib/elf2dmp: add PE name check and Windows Server 2022 support
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
38
135
39
docs/system/arm/cpu-features.rst | 68 ++++++++++-------------
40
contrib/elf2dmp/pe.h | 115 ++++++++++++++++++++++-----------------
41
contrib/elf2dmp/addrspace.c | 1 +
42
contrib/elf2dmp/main.c | 108 ++++++++++++++++++++++++------------
43
hw/char/cadence_uart.c | 6 +-
44
hw/usb/imx-usb-phy.c | 19 ++++++-
45
target/arm/cpu64.c | 69 +++++++++++++++++++++++
46
target/arm/gdbstub.c | 7 +++
47
8 files changed, 267 insertions(+), 126 deletions(-)
diff view generated by jsdifflib
[PULL 1/8] target/arm: Add Neoverse-N1 registers
Deleted patch
1
From: Chen Baozi <chenbaozi@phytium.com.cn>
2
1
3
Add implementation defined registers for neoverse-n1 which
4
would be accessed by TF-A. Since there is no DSU in Qemu,
5
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
6
7
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
10
Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++
14
1 file changed, 69 insertions(+)
15
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
19
+++ b/target/arm/cpu64.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "qemu/osdep.h"
22
#include "qapi/error.h"
23
#include "cpu.h"
24
+#include "cpregs.h"
25
#include "qemu/module.h"
26
#include "sysemu/kvm.h"
27
#include "sysemu/hvf.h"
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
29
/* TODO: Add A64FX specific HPC extension registers */
30
}
31
32
+static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
33
+ { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
34
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
35
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
36
+ { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
37
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
38
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
39
+ { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
40
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
41
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
+ { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
43
+ .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
44
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
45
+ { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
46
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
47
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
48
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
49
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
50
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
51
+ { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
52
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
53
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
54
+ { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
55
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
56
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
57
+ /*
58
+ * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
59
+ * (and in particular its system registers).
60
+ */
61
+ { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
62
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
63
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
64
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
65
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
66
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
67
+ { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
68
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
69
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
+ { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
71
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
72
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
+ { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
74
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
75
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
+ { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
77
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
78
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
+ { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
80
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
81
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
82
+ { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
83
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
84
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
+ { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
86
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
87
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
88
+ { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
89
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
90
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
+};
92
+
93
+static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
94
+{
95
+ define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
96
+}
97
+
98
static void aarch64_neoverse_n1_initfn(Object *obj)
99
{
100
ARMCPU *cpu = ARM_CPU(obj);
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
102
103
/* From D5.1 AArch64 PMU register summary */
104
cpu->isar.reset_pmcr_el0 = 0x410c3000;
105
+
106
+ define_neoverse_n1_cp_reginfo(cpu);
107
}
108
109
static void aarch64_host_initfn(Object *obj)
110
--
111
2.34.1
diff view generated by jsdifflib
[PULL 2/8] hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings
Deleted patch
1
The cadence UART attempts to avoid allowing the guest to set invalid
2
baud rate register values in the uart_write() function. However it
3
does the "mask to the size of the register field" and "check for
4
invalid values" in the wrong order, which means that a malicious
5
guest can get a bogus value into the register by setting also some
6
high bits in the value, and cause QEMU to crash by division-by-zero.
7
1
8
Do the mask before the bounds check instead of afterwards.
9
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1493
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
14
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
Tested-by: Qiang Liu <cyruscyliu@gmail.com>
18
Message-id: 20230314170804.1196232-1-peter.maydell@linaro.org
19
---
20
hw/char/cadence_uart.c | 6 ++++--
21
1 file changed, 4 insertions(+), 2 deletions(-)
22
23
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/char/cadence_uart.c
26
+++ b/hw/char/cadence_uart.c
27
@@ -XXX,XX +XXX,XX @@ static MemTxResult uart_write(void *opaque, hwaddr offset,
28
}
29
break;
30
case R_BRGR: /* Baud rate generator */
31
+ value &= 0xffff;
32
if (value >= 0x01) {
33
- s->r[offset] = value & 0xFFFF;
34
+ s->r[offset] = value;
35
}
36
break;
37
case R_BDIV: /* Baud rate divider */
38
+ value &= 0xff;
39
if (value >= 0x04) {
40
- s->r[offset] = value & 0xFF;
41
+ s->r[offset] = value;
42
}
43
break;
44
default:
45
--
46
2.34.1
47
48
diff view generated by jsdifflib
[PULL 3/8] contrib/elf2dmp: fix code style
Deleted patch
1
From: Viktor Prutyanov <viktor@daynix.com>
2
1
3
Originally elf2dmp were added with some code style issues,
4
especially in pe.h header, and some were introduced by
5
2d0fc797faaa73fbc1d30f5f9e90407bf3dd93f0. Fix them now.
6
7
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
8
Reviewed-by: Annie Li <annie.li@oracle.com>
9
Message-id: 20230222211246.883679-2-viktor@daynix.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
contrib/elf2dmp/pe.h | 100 ++++++++++++++++++------------------
13
contrib/elf2dmp/addrspace.c | 1 +
14
contrib/elf2dmp/main.c | 9 ++--
15
3 files changed, 57 insertions(+), 53 deletions(-)
16
17
diff --git a/contrib/elf2dmp/pe.h b/contrib/elf2dmp/pe.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/contrib/elf2dmp/pe.h
20
+++ b/contrib/elf2dmp/pe.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_DOS_HEADER {
22
} __attribute__ ((packed)) IMAGE_DOS_HEADER;
23
24
typedef struct IMAGE_FILE_HEADER {
25
- uint16_t Machine;
26
- uint16_t NumberOfSections;
27
- uint32_t TimeDateStamp;
28
- uint32_t PointerToSymbolTable;
29
- uint32_t NumberOfSymbols;
30
- uint16_t SizeOfOptionalHeader;
31
- uint16_t Characteristics;
32
+ uint16_t Machine;
33
+ uint16_t NumberOfSections;
34
+ uint32_t TimeDateStamp;
35
+ uint32_t PointerToSymbolTable;
36
+ uint32_t NumberOfSymbols;
37
+ uint16_t SizeOfOptionalHeader;
38
+ uint16_t Characteristics;
39
} __attribute__ ((packed)) IMAGE_FILE_HEADER;
40
41
typedef struct IMAGE_DATA_DIRECTORY {
42
- uint32_t VirtualAddress;
43
- uint32_t Size;
44
+ uint32_t VirtualAddress;
45
+ uint32_t Size;
46
} __attribute__ ((packed)) IMAGE_DATA_DIRECTORY;
47
48
#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16
49
50
typedef struct IMAGE_OPTIONAL_HEADER64 {
51
- uint16_t Magic; /* 0x20b */
52
- uint8_t MajorLinkerVersion;
53
- uint8_t MinorLinkerVersion;
54
- uint32_t SizeOfCode;
55
- uint32_t SizeOfInitializedData;
56
- uint32_t SizeOfUninitializedData;
57
- uint32_t AddressOfEntryPoint;
58
- uint32_t BaseOfCode;
59
- uint64_t ImageBase;
60
- uint32_t SectionAlignment;
61
- uint32_t FileAlignment;
62
- uint16_t MajorOperatingSystemVersion;
63
- uint16_t MinorOperatingSystemVersion;
64
- uint16_t MajorImageVersion;
65
- uint16_t MinorImageVersion;
66
- uint16_t MajorSubsystemVersion;
67
- uint16_t MinorSubsystemVersion;
68
- uint32_t Win32VersionValue;
69
- uint32_t SizeOfImage;
70
- uint32_t SizeOfHeaders;
71
- uint32_t CheckSum;
72
- uint16_t Subsystem;
73
- uint16_t DllCharacteristics;
74
- uint64_t SizeOfStackReserve;
75
- uint64_t SizeOfStackCommit;
76
- uint64_t SizeOfHeapReserve;
77
- uint64_t SizeOfHeapCommit;
78
- uint32_t LoaderFlags;
79
- uint32_t NumberOfRvaAndSizes;
80
- IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];
81
+ uint16_t Magic; /* 0x20b */
82
+ uint8_t MajorLinkerVersion;
83
+ uint8_t MinorLinkerVersion;
84
+ uint32_t SizeOfCode;
85
+ uint32_t SizeOfInitializedData;
86
+ uint32_t SizeOfUninitializedData;
87
+ uint32_t AddressOfEntryPoint;
88
+ uint32_t BaseOfCode;
89
+ uint64_t ImageBase;
90
+ uint32_t SectionAlignment;
91
+ uint32_t FileAlignment;
92
+ uint16_t MajorOperatingSystemVersion;
93
+ uint16_t MinorOperatingSystemVersion;
94
+ uint16_t MajorImageVersion;
95
+ uint16_t MinorImageVersion;
96
+ uint16_t MajorSubsystemVersion;
97
+ uint16_t MinorSubsystemVersion;
98
+ uint32_t Win32VersionValue;
99
+ uint32_t SizeOfImage;
100
+ uint32_t SizeOfHeaders;
101
+ uint32_t CheckSum;
102
+ uint16_t Subsystem;
103
+ uint16_t DllCharacteristics;
104
+ uint64_t SizeOfStackReserve;
105
+ uint64_t SizeOfStackCommit;
106
+ uint64_t SizeOfHeapReserve;
107
+ uint64_t SizeOfHeapCommit;
108
+ uint32_t LoaderFlags;
109
+ uint32_t NumberOfRvaAndSizes;
110
+ IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];
111
} __attribute__ ((packed)) IMAGE_OPTIONAL_HEADER64;
112
113
typedef struct IMAGE_NT_HEADERS64 {
114
- uint32_t Signature;
115
- IMAGE_FILE_HEADER FileHeader;
116
- IMAGE_OPTIONAL_HEADER64 OptionalHeader;
117
+ uint32_t Signature;
118
+ IMAGE_FILE_HEADER FileHeader;
119
+ IMAGE_OPTIONAL_HEADER64 OptionalHeader;
120
} __attribute__ ((packed)) IMAGE_NT_HEADERS64;
121
122
typedef struct IMAGE_DEBUG_DIRECTORY {
123
- uint32_t Characteristics;
124
- uint32_t TimeDateStamp;
125
- uint16_t MajorVersion;
126
- uint16_t MinorVersion;
127
- uint32_t Type;
128
- uint32_t SizeOfData;
129
- uint32_t AddressOfRawData;
130
- uint32_t PointerToRawData;
131
+ uint32_t Characteristics;
132
+ uint32_t TimeDateStamp;
133
+ uint16_t MajorVersion;
134
+ uint16_t MinorVersion;
135
+ uint32_t Type;
136
+ uint32_t SizeOfData;
137
+ uint32_t AddressOfRawData;
138
+ uint32_t PointerToRawData;
139
} __attribute__ ((packed)) IMAGE_DEBUG_DIRECTORY;
140
141
#define IMAGE_DEBUG_TYPE_CODEVIEW 2
142
diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c
143
index XXXXXXX..XXXXXXX 100644
144
--- a/contrib/elf2dmp/addrspace.c
145
+++ b/contrib/elf2dmp/addrspace.c
146
@@ -XXX,XX +XXX,XX @@
147
static struct pa_block *pa_space_find_block(struct pa_space *ps, uint64_t pa)
148
{
149
size_t i;
150
+
151
for (i = 0; i < ps->block_nr; i++) {
152
if (ps->block[i].paddr <= pa &&
153
pa <= ps->block[i].paddr + ps->block[i].size) {
154
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/contrib/elf2dmp/main.c
157
+++ b/contrib/elf2dmp/main.c
158
@@ -XXX,XX +XXX,XX @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps,
159
};
160
161
for (i = 0; i < ps->block_nr; i++) {
162
- h.PhysicalMemoryBlock.NumberOfPages += ps->block[i].size / ELF2DMP_PAGE_SIZE;
163
+ h.PhysicalMemoryBlock.NumberOfPages +=
164
+ ps->block[i].size / ELF2DMP_PAGE_SIZE;
165
h.PhysicalMemoryBlock.Run[i] = (WinDumpPhyMemRun64) {
166
.BasePage = ps->block[i].paddr / ELF2DMP_PAGE_SIZE,
167
.PageCount = ps->block[i].size / ELF2DMP_PAGE_SIZE,
168
};
169
}
170
171
- h.RequiredDumpSpace += h.PhysicalMemoryBlock.NumberOfPages << ELF2DMP_PAGE_BITS;
172
+ h.RequiredDumpSpace +=
173
+ h.PhysicalMemoryBlock.NumberOfPages << ELF2DMP_PAGE_BITS;
174
175
*hdr = h;
176
177
@@ -XXX,XX +XXX,XX @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps,
178
static int fill_context(KDDEBUGGER_DATA64 *kdbg,
179
struct va_space *vs, QEMU_Elf *qe)
180
{
181
- int i;
182
+ int i;
183
+
184
for (i = 0; i < qe->state_nr; i++) {
185
uint64_t Prcb;
186
uint64_t Context;
187
--
188
2.34.1
diff view generated by jsdifflib
[PULL 4/8] contrib/elf2dmp: move PE dir search to pe_get_data_dir_entry
Deleted patch
1
From: Viktor Prutyanov <viktor@daynix.com>
2
1
3
Move out PE directory search functionality to be reused not only
4
for Debug Directory processing but for arbitrary PE directory.
5
6
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
7
Reviewed-by: Annie Li <annie.li@oracle.com>
8
Message-id: 20230222211246.883679-3-viktor@daynix.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
contrib/elf2dmp/main.c | 71 +++++++++++++++++++++++++-----------------
12
1 file changed, 42 insertions(+), 29 deletions(-)
13
14
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/contrib/elf2dmp/main.c
17
+++ b/contrib/elf2dmp/main.c
18
@@ -XXX,XX +XXX,XX @@ static int fill_context(KDDEBUGGER_DATA64 *kdbg,
19
return 0;
20
}
21
22
+static int pe_get_data_dir_entry(uint64_t base, void *start_addr, int idx,
23
+ void *entry, size_t size, struct va_space *vs)
24
+{
25
+ const char e_magic[2] = "MZ";
26
+ const char Signature[4] = "PE\0\0";
27
+ IMAGE_DOS_HEADER *dos_hdr = start_addr;
28
+ IMAGE_NT_HEADERS64 nt_hdrs;
29
+ IMAGE_FILE_HEADER *file_hdr = &nt_hdrs.FileHeader;
30
+ IMAGE_OPTIONAL_HEADER64 *opt_hdr = &nt_hdrs.OptionalHeader;
31
+ IMAGE_DATA_DIRECTORY *data_dir = nt_hdrs.OptionalHeader.DataDirectory;
32
+
33
+ QEMU_BUILD_BUG_ON(sizeof(*dos_hdr) >= ELF2DMP_PAGE_SIZE);
34
+
35
+ if (memcmp(&dos_hdr->e_magic, e_magic, sizeof(e_magic))) {
36
+ return 1;
37
+ }
38
+
39
+ if (va_space_rw(vs, base + dos_hdr->e_lfanew,
40
+ &nt_hdrs, sizeof(nt_hdrs), 0)) {
41
+ return 1;
42
+ }
43
+
44
+ if (memcmp(&nt_hdrs.Signature, Signature, sizeof(Signature)) ||
45
+ file_hdr->Machine != 0x8664 || opt_hdr->Magic != 0x020b) {
46
+ return 1;
47
+ }
48
+
49
+ if (va_space_rw(vs,
50
+ base + data_dir[idx].VirtualAddress,
51
+ entry, size, 0)) {
52
+ return 1;
53
+ }
54
+
55
+ printf("Data directory entry #%d: RVA = 0x%08"PRIx32"\n", idx,
56
+ (uint32_t)data_dir[idx].VirtualAddress);
57
+
58
+ return 0;
59
+}
60
+
61
static int write_dump(struct pa_space *ps,
62
WinDumpHeader64 *hdr, const char *name)
63
{
64
@@ -XXX,XX +XXX,XX @@ static int write_dump(struct pa_space *ps,
65
static int pe_get_pdb_symstore_hash(uint64_t base, void *start_addr,
66
char *hash, struct va_space *vs)
67
{
68
- const char e_magic[2] = "MZ";
69
- const char Signature[4] = "PE\0\0";
70
const char sign_rsds[4] = "RSDS";
71
- IMAGE_DOS_HEADER *dos_hdr = start_addr;
72
- IMAGE_NT_HEADERS64 nt_hdrs;
73
- IMAGE_FILE_HEADER *file_hdr = &nt_hdrs.FileHeader;
74
- IMAGE_OPTIONAL_HEADER64 *opt_hdr = &nt_hdrs.OptionalHeader;
75
- IMAGE_DATA_DIRECTORY *data_dir = nt_hdrs.OptionalHeader.DataDirectory;
76
IMAGE_DEBUG_DIRECTORY debug_dir;
77
OMFSignatureRSDS rsds;
78
char *pdb_name;
79
size_t pdb_name_sz;
80
size_t i;
81
82
- QEMU_BUILD_BUG_ON(sizeof(*dos_hdr) >= ELF2DMP_PAGE_SIZE);
83
-
84
- if (memcmp(&dos_hdr->e_magic, e_magic, sizeof(e_magic))) {
85
- return 1;
86
- }
87
-
88
- if (va_space_rw(vs, base + dos_hdr->e_lfanew,
89
- &nt_hdrs, sizeof(nt_hdrs), 0)) {
90
- return 1;
91
- }
92
-
93
- if (memcmp(&nt_hdrs.Signature, Signature, sizeof(Signature)) ||
94
- file_hdr->Machine != 0x8664 || opt_hdr->Magic != 0x020b) {
95
- return 1;
96
- }
97
-
98
- printf("Debug Directory RVA = 0x%08"PRIx32"\n",
99
- (uint32_t)data_dir[IMAGE_FILE_DEBUG_DIRECTORY].VirtualAddress);
100
-
101
- if (va_space_rw(vs,
102
- base + data_dir[IMAGE_FILE_DEBUG_DIRECTORY].VirtualAddress,
103
- &debug_dir, sizeof(debug_dir), 0)) {
104
+ if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_DEBUG_DIRECTORY,
105
+ &debug_dir, sizeof(debug_dir), vs)) {
106
+ eprintf("Failed to get Debug Directory\n");
107
return 1;
108
}
109
110
--
111
2.34.1
diff view generated by jsdifflib
[PULL 5/8] contrib/elf2dmp: add PE name check and Windows Server 2022 support
Deleted patch
1
From: Viktor Prutyanov <viktor@daynix.com>
2
1
3
Since its inception elf2dmp has checked MZ signatures within an
4
address space above IDT[0] interrupt vector and took first PE image
5
found as Windows Kernel.
6
But in Windows Server 2022 memory dump this address space range is
7
full of invalid PE fragments and the tool must check that PE image
8
is 'ntoskrnl.exe' actually.
9
So, introduce additional validation by checking image name from
10
Export Directory against 'ntoskrnl.exe'.
11
12
Signed-off-by: Viktor Prutyanov <viktor@daynix.com>
13
Tested-by: Yuri Benditovich <yuri.benditovich@daynix.com>
14
Reviewed-by: Annie Li <annie.li@oracle.com>
15
Message-id: 20230222211246.883679-4-viktor@daynix.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
contrib/elf2dmp/pe.h | 15 +++++++++++++++
19
contrib/elf2dmp/main.c | 28 ++++++++++++++++++++++++++--
20
2 files changed, 41 insertions(+), 2 deletions(-)
21
22
diff --git a/contrib/elf2dmp/pe.h b/contrib/elf2dmp/pe.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/contrib/elf2dmp/pe.h
25
+++ b/contrib/elf2dmp/pe.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_NT_HEADERS64 {
27
IMAGE_OPTIONAL_HEADER64 OptionalHeader;
28
} __attribute__ ((packed)) IMAGE_NT_HEADERS64;
29
30
+typedef struct IMAGE_EXPORT_DIRECTORY {
31
+ uint32_t Characteristics;
32
+ uint32_t TimeDateStamp;
33
+ uint16_t MajorVersion;
34
+ uint16_t MinorVersion;
35
+ uint32_t Name;
36
+ uint32_t Base;
37
+ uint32_t NumberOfFunctions;
38
+ uint32_t NumberOfNames;
39
+ uint32_t AddressOfFunctions;
40
+ uint32_t AddressOfNames;
41
+ uint32_t AddressOfNameOrdinals;
42
+} __attribute__ ((packed)) IMAGE_EXPORT_DIRECTORY;
43
+
44
typedef struct IMAGE_DEBUG_DIRECTORY {
45
uint32_t Characteristics;
46
uint32_t TimeDateStamp;
47
@@ -XXX,XX +XXX,XX @@ typedef struct IMAGE_DEBUG_DIRECTORY {
48
#define IMAGE_DEBUG_TYPE_CODEVIEW 2
49
#endif
50
51
+#define IMAGE_FILE_EXPORT_DIRECTORY 0
52
#define IMAGE_FILE_DEBUG_DIRECTORY 6
53
54
typedef struct guid_t {
55
diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/contrib/elf2dmp/main.c
58
+++ b/contrib/elf2dmp/main.c
59
@@ -XXX,XX +XXX,XX @@
60
61
#define SYM_URL_BASE "https://msdl.microsoft.com/download/symbols/"
62
#define PDB_NAME "ntkrnlmp.pdb"
63
+#define PE_NAME "ntoskrnl.exe"
64
65
#define INITIAL_MXCSR 0x1f80
66
67
@@ -XXX,XX +XXX,XX @@ static int write_dump(struct pa_space *ps,
68
return fclose(dmp_file);
69
}
70
71
+static bool pe_check_export_name(uint64_t base, void *start_addr,
72
+ struct va_space *vs)
73
+{
74
+ IMAGE_EXPORT_DIRECTORY export_dir;
75
+ const char *pe_name;
76
+
77
+ if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_EXPORT_DIRECTORY,
78
+ &export_dir, sizeof(export_dir), vs)) {
79
+ return false;
80
+ }
81
+
82
+ pe_name = va_space_resolve(vs, base + export_dir.Name);
83
+ if (!pe_name) {
84
+ return false;
85
+ }
86
+
87
+ return !strcmp(pe_name, PE_NAME);
88
+}
89
+
90
static int pe_get_pdb_symstore_hash(uint64_t base, void *start_addr,
91
char *hash, struct va_space *vs)
92
{
93
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
94
uint64_t KdDebuggerDataBlock;
95
KDDEBUGGER_DATA64 *kdbg;
96
uint64_t KdVersionBlock;
97
+ bool kernel_found = false;
98
99
if (argc != 3) {
100
eprintf("usage:\n\t%s elf_file dmp_file\n", argv[0]);
101
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
102
}
103
104
if (*(uint16_t *)nt_start_addr == 0x5a4d) { /* MZ */
105
- break;
106
+ if (pe_check_export_name(KernBase, nt_start_addr, &vs)) {
107
+ kernel_found = true;
108
+ break;
109
+ }
110
}
111
}
112
113
- if (!nt_start_addr) {
114
+ if (!kernel_found) {
115
eprintf("Failed to find NT kernel image\n");
116
err = 1;
117
goto out_ps;
118
--
119
2.34.1
diff view generated by jsdifflib
[PULL 6/8] hw/usb/imx: Fix out of bounds access in imx_usbphy_read()
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
The i.MX USB Phy driver does not check register ranges, resulting in out of
4
bounds accesses if an attempt is made to access non-existing PHY registers.
5
Add range check and conditionally report bad accesses to fix the problem.
6
7
While at it, also conditionally log attempted writes to non-existing or
8
read-only registers.
9
10
Reported-by: Qiang Liu <cyruscyliu@gmail.com>
11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
12
Tested-by: Qiang Liu <cyruscyliu@gmail.com>
13
Message-id: 20230316234926.208874-1-linux@roeck-us.net
14
Link: https://gitlab.com/qemu-project/qemu/-/issues/1408
15
Fixes: 0701a5efa015 ("hw/usb: Add basic i.MX USB Phy support")
16
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/usb/imx-usb-phy.c | 19 +++++++++++++++++--
21
1 file changed, 17 insertions(+), 2 deletions(-)
22
23
diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/usb/imx-usb-phy.c
26
+++ b/hw/usb/imx-usb-phy.c
27
@@ -XXX,XX +XXX,XX @@
28
#include "qemu/osdep.h"
29
#include "hw/usb/imx-usb-phy.h"
30
#include "migration/vmstate.h"
31
+#include "qemu/log.h"
32
#include "qemu/module.h"
33
34
static const VMStateDescription vmstate_imx_usbphy = {
35
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
36
value = s->usbphy[index - 3];
37
break;
38
default:
39
- value = s->usbphy[index];
40
+ if (index < USBPHY_MAX) {
41
+ value = s->usbphy[index];
42
+ } else {
43
+ qemu_log_mask(LOG_GUEST_ERROR,
44
+ "%s: Read from non-existing USB PHY register 0x%"
45
+ HWADDR_PRIx "\n",
46
+ __func__, offset);
47
+ value = 0;
48
+ }
49
break;
50
}
51
return (uint64_t)value;
52
@@ -XXX,XX +XXX,XX @@ static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
53
s->usbphy[index - 3] ^= value;
54
break;
55
default:
56
- /* Other registers are read-only */
57
+ /* Other registers are read-only or do not exist */
58
+ qemu_log_mask(LOG_GUEST_ERROR,
59
+ "%s: Write to %s USB PHY register 0x%"
60
+ HWADDR_PRIx "\n",
61
+ __func__,
62
+ index >= USBPHY_MAX ? "non-existing" : "read-only",
63
+ offset);
64
break;
65
}
66
}
67
--
68
2.34.1
diff view generated by jsdifflib
[PULL 7/8] docs/system/arm/cpu-features.rst: Fix formatting
Deleted patch
1
The markup for the Arm CPU feature documentation is incorrect,
2
and results in the HTML not rendering correctly -- the first
3
line of each description is rendered in boldface as if it
4
were part of the option name.
5
1
6
Reformat to match the styling used in cpu-models-x86.rst.inc.
7
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1479
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20230316105808.1414003-1-peter.maydell@linaro.org
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
---
13
docs/system/arm/cpu-features.rst | 68 ++++++++++++++------------------
14
1 file changed, 30 insertions(+), 38 deletions(-)
15
16
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/cpu-features.rst
19
+++ b/docs/system/arm/cpu-features.rst
20
@@ -XXX,XX +XXX,XX @@ are named with the prefix "kvm-". KVM VCPU features may be probed,
21
enabled, and disabled in the same way as other CPU features. Below is
22
the list of KVM VCPU features and their descriptions.
23
24
- kvm-no-adjvtime By default kvm-no-adjvtime is disabled. This
25
- means that by default the virtual time
26
- adjustment is enabled (vtime is not *not*
27
- adjusted).
28
+``kvm-no-adjvtime``
29
+ By default kvm-no-adjvtime is disabled. This means that by default
30
+ the virtual time adjustment is enabled (vtime is not *not* adjusted).
31
32
- When virtual time adjustment is enabled each
33
- time the VM transitions back to running state
34
- the VCPU's virtual counter is updated to ensure
35
- stopped time is not counted. This avoids time
36
- jumps surprising guest OSes and applications,
37
- as long as they use the virtual counter for
38
- timekeeping. However it has the side effect of
39
- the virtual and physical counters diverging.
40
- All timekeeping based on the virtual counter
41
- will appear to lag behind any timekeeping that
42
- does not subtract VM stopped time. The guest
43
- may resynchronize its virtual counter with
44
- other time sources as needed.
45
+ When virtual time adjustment is enabled each time the VM transitions
46
+ back to running state the VCPU's virtual counter is updated to
47
+ ensure stopped time is not counted. This avoids time jumps
48
+ surprising guest OSes and applications, as long as they use the
49
+ virtual counter for timekeeping. However it has the side effect of
50
+ the virtual and physical counters diverging. All timekeeping based
51
+ on the virtual counter will appear to lag behind any timekeeping
52
+ that does not subtract VM stopped time. The guest may resynchronize
53
+ its virtual counter with other time sources as needed.
54
55
- Enable kvm-no-adjvtime to disable virtual time
56
- adjustment, also restoring the legacy (pre-5.0)
57
- behavior.
58
+ Enable kvm-no-adjvtime to disable virtual time adjustment, also
59
+ restoring the legacy (pre-5.0) behavior.
60
61
- kvm-steal-time Since v5.2, kvm-steal-time is enabled by
62
- default when KVM is enabled, the feature is
63
- supported, and the guest is 64-bit.
64
+``kvm-steal-time``
65
+ Since v5.2, kvm-steal-time is enabled by default when KVM is
66
+ enabled, the feature is supported, and the guest is 64-bit.
67
68
- When kvm-steal-time is enabled a 64-bit guest
69
- can account for time its CPUs were not running
70
- due to the host not scheduling the corresponding
71
- VCPU threads. The accounting statistics may
72
- influence the guest scheduler behavior and/or be
73
- exposed to the guest userspace.
74
+ When kvm-steal-time is enabled a 64-bit guest can account for time
75
+ its CPUs were not running due to the host not scheduling the
76
+ corresponding VCPU threads. The accounting statistics may influence
77
+ the guest scheduler behavior and/or be exposed to the guest
78
+ userspace.
79
80
TCG VCPU Features
81
=================
82
@@ -XXX,XX +XXX,XX @@ TCG VCPU Features
83
TCG VCPU features are CPU features that are specific to TCG.
84
Below is the list of TCG VCPU features and their descriptions.
85
86
- pauth-impdef When ``FEAT_Pauth`` is enabled, either the
87
- *impdef* (Implementation Defined) algorithm
88
- is enabled or the *architected* QARMA algorithm
89
- is enabled. By default the impdef algorithm
90
- is disabled, and QARMA is enabled.
91
+``pauth-impdef``
92
+ When ``FEAT_Pauth`` is enabled, either the *impdef* (Implementation
93
+ Defined) algorithm is enabled or the *architected* QARMA algorithm
94
+ is enabled. By default the impdef algorithm is disabled, and QARMA
95
+ is enabled.
96
97
- The architected QARMA algorithm has good
98
- cryptographic properties, but can be quite slow
99
- to emulate. The impdef algorithm used by QEMU
100
- is non-cryptographic but significantly faster.
101
+ The architected QARMA algorithm has good cryptographic properties,
102
+ but can be quite slow to emulate. The impdef algorithm used by QEMU
103
+ is non-cryptographic but significantly faster.
104
105
SVE CPU Properties
106
==================
107
--
108
2.34.1
diff view generated by jsdifflib
[PULL 8/8] target/arm: Don't advertise aarch64-pauth.xml to gdb
Deleted patch
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Unfortunately a bug in older versions of gdb means that they will
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crash if QEMU sends them the aarch64-pauth.xml. This bug is fixed in
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gdb commit 1ba3a3222039eb25, and there are plans to backport that to
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affected gdb release branches, but since the bug affects gdb 9
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through 12 it is very widely deployed (for instance by distros).
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1
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It is not currently clear what the best way to deal with this is; it
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has been proposed to define a new XML feature name that old gdb will
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ignore but newer gdb can handle. Since QEMU's 8.0 release is
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imminent and at least one of our CI runners is now falling over this,
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disable the pauth XML for the moment. We can follow up with a more
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considered fix either in time for 8.0 or else for the 8.1 release.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/gdbstub.c | 7 +++++++
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1 file changed, 7 insertions(+)
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diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/gdbstub.c
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+++ b/target/arm/gdbstub.c
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@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
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aarch64_gdb_set_fpu_reg,
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34, "aarch64-fpu.xml", 0);
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}
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+#if 0
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+ /*
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+ * GDB versions 9 through 12 have a bug which means they will
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+ * crash if they see this XML from QEMU; disable it for the 8.0
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+ * release, pending a better solution.
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+ */
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if (isar_feature_aa64_pauth(&cpu->isar)) {
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gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
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aarch64_gdb_set_pauth_reg,
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4, "aarch64-pauth.xml", 0);
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}
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+#endif
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#endif
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} else {
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if (arm_feature(env, ARM_FEATURE_NEON)) {
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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