[PATCH for-8.1 v3 00/26] target/riscv: rework CPU extensions validation

Daniel Henrique Barboza posted 26 patches 1 week, 2 days ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230318200436.299464-1-dbarboza@ventanamicro.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
There is a newer version of this series
target/riscv/cpu.c | 691 +++++++++++++++++++++++++++++----------------
target/riscv/cpu.h |  17 +-
target/riscv/csr.c |  85 ++++--
3 files changed, 522 insertions(+), 271 deletions(-)
[PATCH for-8.1 v3 00/26] target/riscv: rework CPU extensions validation
Posted by Daniel Henrique Barboza 1 week, 2 days ago

This new version contains changes suggested by Weiwei Li. I've also
reworked write_misa() to cover more cases. write_misa() is now able to
properly enable RVG, RVV and RVE.

A more in-depth description of what was attempted here can be found in
[1]. Note that the current validation flow already prevents certain misa
bits from being disabled (e.g. RVF) due to the presence of Z extensions
that are already enabled in the hart, so I decided not to add extra
logic to handle these cases.

Patches are rebased on top of Alistair's riscv-to-apply.next.

Changes from v2:
- patches removed:
  - patch 15 ('do not allow RVG in write_misa()')
  - patch 19 ('add misa_ext V-> D & F dependency')
- patch 15:
  - add zfinx dependency to enable RVG
- patch 19 (former patch 17):
  -  remove misa_ext* assignment from validate_set_extensions()
- patch 23 (former 25):
  - enable RVE in write_misa()
- new patch 25:
  - enable RVG in write_misa()
- new patch 26:
  - enable RVV in write_misa()
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg04424.html

[1] https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg04674.html

Daniel Henrique Barboza (26):
  target/riscv/cpu.c: add riscv_cpu_validate_v()
  target/riscv/cpu.c: remove set_vext_version()
  target/riscv/cpu.c: remove set_priv_version()
  target/riscv: add PRIV_VERSION_LATEST
  target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
  target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
  target/riscv: move pmp and epmp validations to
  target/riscv/cpu.c: validate extensions before riscv_timer_init()
  target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
  target/riscv/cpu.c: avoid set_misa() in validate_set_extensions()
  target/riscv/cpu.c: set cpu config in set_misa()
  target/riscv/cpu.c: redesign register_cpu_props()
  target/riscv: put env->misa_ext <-> cpu->cfg code into helpers
  target/riscv: add RVG
  target/riscv/cpu.c: split RVG code from validate_set_extensions()
  target/riscv/cpu.c: add riscv_cpu_validate_misa_ext()
  target/riscv: move riscv_cpu_validate_v() to validate_misa_ext()
  target/riscv: error out on priv failure for RVH
  target/riscv: write env->misa_ext* in register_generic_cpu_props()
  target/riscv: make validate_misa_ext() use a misa_ext val
  target/riscv: split riscv_cpu_validate_set_extensions()
  target/riscv: use misa_ext val in riscv_cpu_validate_extensions()
  target/riscv: rework write_misa()
  target/riscv: update cpu->cfg misa bits in commit_cpu_cfg()
  target/riscv: allow write_misa() to enable RVG
  target/riscv: allow write_misa() to enable RVV

 target/riscv/cpu.c | 691 +++++++++++++++++++++++++++++----------------
 target/riscv/cpu.h |  17 +-
 target/riscv/csr.c |  85 ++++--
 3 files changed, 522 insertions(+), 271 deletions(-)