The following changes since commit 262312d7ba6e2966acedb4f9c134fd19176b4083:

Merge tag 'pull-testing-next-010323-1' of https://gitlab.com/stsquad/qemu into staging (2023-03-02 13:02:53 +0000)

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230303

for you to fetch changes up to 0d588c4f999699a430b32c563fe9ccc1710b8fd7:

hw/loongarch/virt: add system_powerdown hmp command support (2023-03-03 09:37:30 +0800)

pull-loongarch-20230303

Bibo Mao (1):

hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE

Song Gao (4):

loongarch: Add smbios command line option.

docs/system/loongarch: update loongson3.rst and rename it to virt.rst

target/loongarch: Implement Chip Configuraiton Version Register(0x0000)

hw/loongarch/virt: add system_powerdown hmp command support

docs/system/loongarch/{loongson3.rst => virt.rst} | 97 +++++++++--------------

hw/loongarch/acpi-build.c | 3 +-

hw/loongarch/virt.c | 20 ++++-

include/hw/loongarch/virt.h | 1 +

include/hw/pci-host/ls7a.h | 17 ++--

qemu-options.hx | 2 +-

target/loongarch/cpu.c | 2 +

target/loongarch/cpu.h | 1 +

8 files changed, 70 insertions(+), 73 deletions(-)

rename docs/system/loongarch/{loongson3.rst => virt.rst} (51%)

For loongarch virt machine, add powerdown notification callback

and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add

acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this

patch.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230303010548.295580-1-gaosong@loongson.cn>

hw/loongarch/acpi-build.c | 1 +

hw/loongarch/virt.c | 12 ++++++++++++

include/hw/loongarch/virt.h | 1 +

3 files changed, 14 insertions(+)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c

--- a/hw/loongarch/acpi-build.c

+++ b/hw/loongarch/acpi-build.c

@@ -XXX,XX +XXX,XX @@ build_la_ged_aml(Aml *dsdt, MachineState *machine)

AML_SYSTEM_MEMORY,

VIRT_GED_MEM_ADDR);

}

+ acpi_dsdt_add_power_button(dsdt);

static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/loongarch/virt.c

+++ b/hw/loongarch/virt.c

@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)

loongarch_acpi_setup(lams);

+static void virt_powerdown_req(Notifier *notifier, void *opaque)

+ LoongArchMachineState *s = container_of(notifier,

+ LoongArchMachineState, powerdown_notifier);

+ acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS);

struct memmap_entry {

uint64_t address;

uint64_t length;

@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)

VIRT_PLATFORM_BUS_IRQ);

lams->machine_done.notify = virt_machine_done;

qemu_add_machine_init_done_notifier(&lams->machine_done);

+ /* connect powerdown request */

+ lams->powerdown_notifier.notify = virt_powerdown_req;

+ qemu_register_powerdown_notifier(&lams->powerdown_notifier);

fdt_add_pcie_node(lams);

/*

* Since lowmem region starts from 0 and Linux kernel legacy start address

diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/loongarch/virt.h

+++ b/include/hw/loongarch/virt.h

@@ -XXX,XX +XXX,XX @@ struct LoongArchMachineState {

/* State for other subsystems/APIs: */

FWCfgState *fw_cfg;

Notifier machine_done;

+ Notifier powerdown_notifier;

OnOffAuto acpi;

char *oem_id;

char *oem_table_id;

2.31.1

From: Bibo Mao <maobibo@loongson.cn>

In theory gsi base can start from 0 on loongarch virt machine,

however gsi base is hard-coded in linux kernel loongarch system,

else system fails to boot.

This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE,

keeps value unchanged. GSI base is common concept in acpi spec

and easy to understand.

hw/loongarch/acpi-build.c | 2 +-

hw/loongarch/virt.c | 8 ++++----

include/hw/pci-host/ls7a.h | 17 +++++++++--------

3 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c

--- a/hw/loongarch/acpi-build.c

+++ b/hw/loongarch/acpi-build.c

@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)

.pio.size = VIRT_PCI_IO_SIZE,

.ecam.base = VIRT_PCI_CFG_BASE,

.ecam.size = VIRT_PCI_CFG_SIZE,

- .irq = PCH_PIC_IRQ_OFFSET + VIRT_DEVICE_IRQS,

+ .irq = VIRT_GSI_BASE + VIRT_DEVICE_IRQS,

.bus = lams->pci_bus,

};

@@ -XXX,XX +XXX,XX @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState

sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);

sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,

- qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET));

+ qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE));

sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

return dev;

}

@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)

sysbus = SYS_BUS_DEVICE(dev);

for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {

- irq = VIRT_PLATFORM_BUS_IRQ - PCH_PIC_IRQ_OFFSET + i;

+ irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i;

sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq));

}

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,

qdev_get_gpio_in(pch_pic,

- VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),

+ VIRT_UART_IRQ - VIRT_GSI_BASE),

115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);

fdt_add_uart_node(lams);

@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *

create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);

sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,

qdev_get_gpio_in(pch_pic,

- VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));

+ VIRT_RTC_IRQ - VIRT_GSI_BASE));

fdt_add_rtc_node(lams);

pm_mem = g_new(MemoryRegion, 1);

diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h

--- a/include/hw/pci-host/ls7a.h

+++ b/include/hw/pci-host/ls7a.h

@@ -XXX,XX +XXX,XX @@

#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL

/*

- * According to the kernel pch irq start from 64 offset

- * 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs

- * used for pci device.

+ * GSI_BASE is hard-coded with 64 in linux kernel, else kernel fails to boot

+ * 0 - 15 GSI for ISA devices even if there is no ISA devices

+ * 16 - 63 GSI for CPU devices such as timers/perf monitor etc

+ * 64 - GSI for external devices

*/

#define VIRT_PCH_PIC_IRQ_NUM 32

-#define PCH_PIC_IRQ_OFFSET 64

+#define VIRT_GSI_BASE 64

#define VIRT_DEVICE_IRQS 16

-#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)

+#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)

#define VIRT_UART_BASE 0x1fe001e0

#define VIRT_UART_SIZE 0X100

-#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)

+#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 3)

#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)

#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)

#define VIRT_RTC_LEN 0x100

-#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)

+#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 4)

#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000

#define VIRT_PLATFORM_BUS_SIZE 0x2000000

#define VIRT_PLATFORM_BUS_NUM_IRQS 2

-#define VIRT_PLATFORM_BUS_IRQ 69

+#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 5)

#endif

2.31.1

According to the 3A5000 manual 4.1 implement Chip Configuration

Version Register(0x0000).

Signed-off-by: Song Gao <gaosong@loongson.cn>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>

target/loongarch/cpu.c | 2 ++

target/loongarch/cpu.h | 1 +

2 files changed, 3 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c

--- a/target/loongarch/cpu.c

+++ b/target/loongarch/cpu.c

@@ -XXX,XX +XXX,XX @@ static void loongarch_qemu_write(void *opaque, hwaddr addr,

static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)

{

switch (addr) {

+ case VERSION_REG:

+ return 0x11ULL;

case FEATURE_REG:

return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |

1ULL << IOCSRF_CSRIPI;

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h

--- a/target/loongarch/cpu.h

+++ b/target/loongarch/cpu.h

#define IOCSRF_GMOD 9

#define IOCSRF_VM 11

+#define VERSION_REG 0x0

#define FEATURE_REG 0x8

#define VENDOR_REG 0x10

#define CPUNAME_REG 0x20

2.31.1

Since the EDK2 had already support LoongArch, update build bios,

and update cpu type, cross-tools.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Song Gao <gaosong@loongson.cn>

Message-Id: <20230227035905.1290953-1-gaosong@loongson.cn>

.../loongarch/{loongson3.rst => virt.rst} | 97 ++++++++-----------

1 file changed, 38 insertions(+), 59 deletions(-)

rename docs/system/loongarch/{loongson3.rst => virt.rst} (51%)

diff --git a/docs/system/loongarch/loongson3.rst b/docs/system/loongarch/virt.rst

similarity index 51%

rename from docs/system/loongarch/loongson3.rst

rename to docs/system/loongarch/virt.rst

--- a/docs/system/loongarch/loongson3.rst

+++ b/docs/system/loongarch/virt.rst

@@ -XXX,XX +XXX,XX @@ The ``virt`` machine supports:

- Fw_cfg device

- PCI/PCIe devices

- Memory device

-- CPU device. Type: la464-loongarch-cpu.

+- CPU device. Type: la464.

CPU and machine Type

--------------------

The ``qemu-system-loongarch64`` provides emulation for virt

machine. You can specify the machine type ``virt`` and

-cpu type ``la464-loongarch-cpu``.

+cpu type ``la464``.

Boot options

------------

@@ -XXX,XX +XXX,XX @@ We can boot the LoongArch virt machine by specifying the uefi bios,

initrd, and linux kernel. And those source codes and binary files

can be accessed by following steps.

-(1) booting command:

+(1) Build qemu-system-loongarch64: