[PULL 00/25] target-arm queue
[PULL 00/14] target-arm queue
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The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c:
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The following changes since commit 8f6330a807f2642dc2a3cdf33347aa28a4c00a87:
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Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000)
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Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-06 16:56:20 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240308
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for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677:
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for you to fetch changes up to bbf6c6dbead82292a20951eb1204442a6b838de9:
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hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000)
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target/arm: Move v7m-related code from cpu32.c into a separate file (2024-03-08 14:45:03 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* Various code cleanups
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* Implement FEAT_ECV
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* More refactoring working towards allowing a build
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* STM32L4x5: Implement GPIO device
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without CONFIG_TCG
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* Fix 32-bit SMOPA
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* Refactor v7m related code from cpu32.c into its own file
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* hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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----------------------------------------------------------------
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----------------------------------------------------------------
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Claudio Fontana (2):
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Inès Varhol (3):
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target/arm: move helpers to tcg/
23
hw/gpio: Implement STM32L4x5 GPIO
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target/arm: Move psci.c into the tcg directory
24
hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
25
tests/qtest: Add STM32L4x5 GPIO QTest testcase
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Fabiano Rosas (9):
27
Peter Maydell (9):
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target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
28
target/arm: Move some register related defines to internals.h
26
target/arm: Wrap TCG-only code in debug_helper.c
29
target/arm: Timer _EL02 registers UNDEF for E2H == 0
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target/arm: move translate modules to tcg/
30
target/arm: use FIELD macro for CNTHCTL bit definitions
28
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
31
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
29
target/arm: Move hflags code into the tcg directory
32
target/arm: Implement new FEAT_ECV trap bits
30
target/arm: Move regime_using_lpae_format into internal.h
33
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
31
target/arm: Don't access TCG code when debugging with KVM
34
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
32
cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
35
target/arm: Enable FEAT_ECV for 'max' CPU
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tests/avocado: add machine:none tag to version.py
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hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
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Philippe Mathieu-Daudé (13):
38
Richard Henderson (1):
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hw/gpio/max7310: Simplify max7310_realize()
39
target/arm: Fix 32-bit SMOPA
37
hw/char/pl011: Un-inline pl011_create()
38
hw/char/pl011: Open-code pl011_luminary_create()
39
hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
40
hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
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hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
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hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
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hw/intc/armv7m_nvic: Use QOM cast CPU() macro
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hw/arm/musicpal: Remove unused dummy MemoryRegion
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iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
46
hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
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hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
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hw: Replace qemu_or_irq typedef by OrIRQState
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Thomas Huth (1):
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Thomas Huth (1):
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include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header
42
target/arm: Move v7m-related code from cpu32.c into a separate file
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MAINTAINERS | 1 +
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MAINTAINERS | 1 +
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include/exec/cpu-defs.h | 6 +
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docs/system/arm/b-l475e-iot01a.rst | 2 +-
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include/hw/arm/allwinner-a10.h | 2 -
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docs/system/arm/emulation.rst | 1 +
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include/hw/arm/armsse.h | 6 +-
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include/hw/arm/stm32l4x5_soc.h | 2 +
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include/hw/arm/bcm2835_peripherals.h | 2 +-
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include/hw/gpio/stm32l4x5_gpio.h | 71 +++++
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include/hw/arm/exynos4210.h | 4 +-
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include/hw/misc/stm32l4x5_syscfg.h | 3 +-
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include/hw/arm/stm32f205_soc.h | 2 +-
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include/hw/rtc/sun4v-rtc.h | 2 +-
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include/hw/arm/stm32f405_soc.h | 2 +-
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target/arm/cpu-features.h | 10 +
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include/hw/arm/xlnx-versal.h | 6 +-
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target/arm/cpu.h | 129 +--------
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include/hw/arm/xlnx-zynqmp.h | 2 +-
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target/arm/internals.h | 151 ++++++++++
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include/hw/char/cmsdk-apb-uart.h | 34 ---
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hw/arm/stm32l4x5_soc.c | 71 ++++-
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include/hw/char/pl011.h | 36 +--
55
hw/gpio/stm32l4x5_gpio.c | 477 ++++++++++++++++++++++++++++++++
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include/hw/char/xilinx_uartlite.h | 22 +-
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hw/misc/stm32l4x5_syscfg.c | 1 +
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include/hw/or-irq.h | 5 +-
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hw/rtc/sun4v-rtc.c | 2 +-
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include/hw/timer/cmsdk-apb-timer.h | 1 -
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target/arm/helper.c | 189 ++++++++++++-
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target/arm/internals.h | 23 +-
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target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++
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target/arm/{ => tcg}/translate-a64.h | 0
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target/arm/tcg/cpu32.c | 261 ------------------
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target/arm/{ => tcg}/translate.h | 0
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target/arm/tcg/cpu64.c | 1 +
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target/arm/{ => tcg}/vec_internal.h | 0
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target/arm/tcg/sme_helper.c | 77 +++---
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target/arm/{ => tcg}/a32-uncond.decode | 0
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tests/qtest/stm32l4x5_gpio-test.c | 551 +++++++++++++++++++++++++++++++++++++
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target/arm/{ => tcg}/a32.decode | 0
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tests/tcg/aarch64/sme-smopa-1.c | 47 ++++
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target/arm/{ => tcg}/m-nocp.decode | 0
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tests/tcg/aarch64/sme-smopa-2.c | 54 ++++
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target/arm/{ => tcg}/mve.decode | 0
66
hw/arm/Kconfig | 3 +-
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target/arm/{ => tcg}/neon-dp.decode | 0
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hw/gpio/Kconfig | 3 +
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target/arm/{ => tcg}/neon-ls.decode | 0
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hw/gpio/meson.build | 1 +
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target/arm/{ => tcg}/neon-shared.decode | 0
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hw/gpio/trace-events | 6 +
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target/arm/{ => tcg}/sme-fa64.decode | 0
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target/arm/meson.build | 3 +
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target/arm/{ => tcg}/sme.decode | 0
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target/arm/tcg/meson.build | 3 +
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target/arm/{ => tcg}/sve.decode | 0
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target/arm/trace-events | 1 +
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target/arm/{ => tcg}/t16.decode | 0
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tests/qtest/meson.build | 3 +-
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target/arm/{ => tcg}/t32.decode | 0
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tests/tcg/aarch64/Makefile.target | 2 +-
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target/arm/{ => tcg}/vfp-uncond.decode | 0
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31 files changed, 1962 insertions(+), 456 deletions(-)
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target/arm/{ => tcg}/vfp.decode | 0
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create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
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hw/arm/allwinner-a10.c | 1 +
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create mode 100644 hw/gpio/stm32l4x5_gpio.c
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hw/arm/boot.c | 6 +-
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create mode 100644 target/arm/tcg/cpu-v7m.c
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hw/arm/exynos4210.c | 4 +-
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create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
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hw/arm/mps2-tz.c | 2 +-
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create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
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hw/arm/mps2.c | 41 ++-
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create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
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hw/arm/musicpal.c | 4 -
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hw/arm/stellaris.c | 11 +-
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hw/char/pl011.c | 17 ++
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hw/char/xilinx_uartlite.c | 4 +-
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hw/core/irq.c | 9 +-
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hw/core/or-irq.c | 18 +-
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hw/gpio/max7310.c | 5 +-
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hw/intc/armv7m_nvic.c | 26 +-
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hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +-
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hw/pci-host/raven.c | 2 +-
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iothread.c | 4 -
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target/arm/arm-powerctl.c | 7 +-
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target/arm/cpu.c | 9 +-
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target/arm/debug_helper.c | 490 ++++++++++++++++---------------
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target/arm/helper.c | 411 +-------------------------
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target/arm/machine.c | 12 +-
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target/arm/ptw.c | 4 +
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target/arm/tcg-stubs.c | 27 ++
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target/arm/{ => tcg}/crypto_helper.c | 0
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target/arm/{ => tcg}/helper-a64.c | 0
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target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++
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target/arm/{ => tcg}/iwmmxt_helper.c | 0
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target/arm/{ => tcg}/m_helper.c | 0
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target/arm/{ => tcg}/mte_helper.c | 0
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target/arm/{ => tcg}/mve_helper.c | 0
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target/arm/{ => tcg}/neon_helper.c | 0
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target/arm/{ => tcg}/op_helper.c | 0
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target/arm/{ => tcg}/pauth_helper.c | 0
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target/arm/{ => tcg}/psci.c | 0
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target/arm/{ => tcg}/sme_helper.c | 0
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target/arm/{ => tcg}/sve_helper.c | 0
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target/arm/{ => tcg}/tlb_helper.c | 18 --
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target/arm/{ => tcg}/translate-a64.c | 0
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target/arm/{ => tcg}/translate-m-nocp.c | 0
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target/arm/{ => tcg}/translate-mve.c | 0
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target/arm/{ => tcg}/translate-neon.c | 0
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target/arm/{ => tcg}/translate-sme.c | 0
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target/arm/{ => tcg}/translate-sve.c | 0
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target/arm/{ => tcg}/translate-vfp.c | 0
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target/arm/{ => tcg}/translate.c | 0
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target/arm/{ => tcg}/vec_helper.c | 0
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target/arm/meson.build | 46 +--
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target/arm/tcg/meson.build | 50 ++++
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tests/avocado/version.py | 1 +
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82 files changed, 918 insertions(+), 875 deletions(-)
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rename target/arm/{ => tcg}/translate-a64.h (100%)
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rename target/arm/{ => tcg}/translate.h (100%)
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rename target/arm/{ => tcg}/vec_internal.h (100%)
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rename target/arm/{ => tcg}/a32-uncond.decode (100%)
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rename target/arm/{ => tcg}/a32.decode (100%)
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rename target/arm/{ => tcg}/m-nocp.decode (100%)
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rename target/arm/{ => tcg}/mve.decode (100%)
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rename target/arm/{ => tcg}/neon-dp.decode (100%)
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rename target/arm/{ => tcg}/neon-ls.decode (100%)
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rename target/arm/{ => tcg}/neon-shared.decode (100%)
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rename target/arm/{ => tcg}/sme-fa64.decode (100%)
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rename target/arm/{ => tcg}/sme.decode (100%)
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rename target/arm/{ => tcg}/sve.decode (100%)
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rename target/arm/{ => tcg}/t16.decode (100%)
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rename target/arm/{ => tcg}/t32.decode (100%)
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rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
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rename target/arm/{ => tcg}/vfp.decode (100%)
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create mode 100644 target/arm/tcg-stubs.c
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rename target/arm/{ => tcg}/crypto_helper.c (100%)
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rename target/arm/{ => tcg}/helper-a64.c (100%)
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create mode 100644 target/arm/tcg/hflags.c
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rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
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rename target/arm/{ => tcg}/m_helper.c (100%)
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rename target/arm/{ => tcg}/mte_helper.c (100%)
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rename target/arm/{ => tcg}/mve_helper.c (100%)
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rename target/arm/{ => tcg}/neon_helper.c (100%)
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rename target/arm/{ => tcg}/op_helper.c (100%)
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rename target/arm/{ => tcg}/pauth_helper.c (100%)
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rename target/arm/{ => tcg}/psci.c (100%)
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rename target/arm/{ => tcg}/sme_helper.c (100%)
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rename target/arm/{ => tcg}/sve_helper.c (100%)
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rename target/arm/{ => tcg}/tlb_helper.c (94%)
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rename target/arm/{ => tcg}/translate-a64.c (100%)
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rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
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rename target/arm/{ => tcg}/translate-mve.c (100%)
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rename target/arm/{ => tcg}/translate-neon.c (100%)
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rename target/arm/{ => tcg}/translate-sme.c (100%)
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rename target/arm/{ => tcg}/translate-sve.c (100%)
174
rename target/arm/{ => tcg}/translate-vfp.c (100%)
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rename target/arm/{ => tcg}/translate.c (100%)
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rename target/arm/{ => tcg}/vec_helper.c (100%)
177
create mode 100644 target/arm/tcg/meson.build
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diff view generated by jsdifflib
[PULL 01/25] include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
pci_device.h is not needed at all in allwinner-a10.h, and serial.h
4
is only needed by the corresponding .c file.
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6
Signed-off-by: Thomas Huth <thuth@redhat.com>
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Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230215152233.210024-1-thuth@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/allwinner-a10.h | 2 --
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hw/arm/allwinner-a10.c | 1 +
13
2 files changed, 1 insertion(+), 2 deletions(-)
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diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
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index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/allwinner-a10.h
18
+++ b/include/hw/arm/allwinner-a10.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef HW_ARM_ALLWINNER_A10_H
21
#define HW_ARM_ALLWINNER_A10_H
22
23
-#include "hw/char/serial.h"
24
#include "hw/arm/boot.h"
25
-#include "hw/pci/pci_device.h"
26
#include "hw/timer/allwinner-a10-pit.h"
27
#include "hw/intc/allwinner-a10-pic.h"
28
#include "hw/net/allwinner_emac.h"
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diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
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index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/allwinner-a10.c
32
+++ b/hw/arm/allwinner-a10.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/osdep.h"
35
#include "qapi/error.h"
36
#include "qemu/module.h"
37
+#include "hw/char/serial.h"
38
#include "hw/sysbus.h"
39
#include "hw/arm/allwinner-a10.h"
40
#include "hw/misc/unimp.h"
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--
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2.34.1
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diff view generated by jsdifflib
[PULL 09/25] target/arm: Move regime_using_lpae_format into internal.h
[PULL 01/14] target/arm: Move some register related defines to internals.h
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From: Fabiano Rosas <farosas@suse.de>
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cpu.h has a lot of #defines relating to CPU register fields.
2
Most of these aren't actually used outside target/arm code,
3
so there's no point in cluttering up the cpu.h file with them.
4
Move some easy ones to internals.h.
2
5
3
This function is needed by common code (ptw.c), so move it along with
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
the other regime_* functions in internal.h. When we enable the build
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
without TCG, the tlb_helper.c file will not be present.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20240301183219.2424889-2-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 128 -----------------------------------------
12
target/arm/internals.h | 128 +++++++++++++++++++++++++++++++++++++++++
13
2 files changed, 128 insertions(+), 128 deletions(-)
6
14
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
index XXXXXXX..XXXXXXX 100644
9
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
17
--- a/target/arm/cpu.h
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
+++ b/target/arm/cpu.h
11
---
19
@@ -XXX,XX +XXX,XX @@ typedef struct ARMGenericTimer {
12
target/arm/internals.h | 21 ++++++++++++++++++---
20
uint64_t ctl; /* Timer Control register */
13
target/arm/tcg/tlb_helper.c | 18 ------------------
21
} ARMGenericTimer;
14
2 files changed, 18 insertions(+), 21 deletions(-)
22
15
23
-#define VTCR_NSW (1u << 29)
24
-#define VTCR_NSA (1u << 30)
25
-#define VSTCR_SW VTCR_NSW
26
-#define VSTCR_SA VTCR_NSA
27
-
28
/* Define a maximum sized vector register.
29
* For 32-bit, this is a 128-bit NEON/AdvSIMD register.
30
* For 64-bit, this is a 2048-bit SVE register.
31
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
32
#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
33
#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
34
35
-/* Bit definitions for CPACR (AArch32 only) */
36
-FIELD(CPACR, CP10, 20, 2)
37
-FIELD(CPACR, CP11, 22, 2)
38
-FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
39
-FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
40
-FIELD(CPACR, ASEDIS, 31, 1)
41
-
42
-/* Bit definitions for CPACR_EL1 (AArch64 only) */
43
-FIELD(CPACR_EL1, ZEN, 16, 2)
44
-FIELD(CPACR_EL1, FPEN, 20, 2)
45
-FIELD(CPACR_EL1, SMEN, 24, 2)
46
-FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
47
-
48
-/* Bit definitions for HCPTR (AArch32 only) */
49
-FIELD(HCPTR, TCP10, 10, 1)
50
-FIELD(HCPTR, TCP11, 11, 1)
51
-FIELD(HCPTR, TASE, 15, 1)
52
-FIELD(HCPTR, TTA, 20, 1)
53
-FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
54
-FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
55
-
56
-/* Bit definitions for CPTR_EL2 (AArch64 only) */
57
-FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
58
-FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
59
-FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
60
-FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
61
-FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
62
-FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
63
-FIELD(CPTR_EL2, TTA, 28, 1)
64
-FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
65
-FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
66
-
67
-/* Bit definitions for CPTR_EL3 (AArch64 only) */
68
-FIELD(CPTR_EL3, EZ, 8, 1)
69
-FIELD(CPTR_EL3, TFP, 10, 1)
70
-FIELD(CPTR_EL3, ESM, 12, 1)
71
-FIELD(CPTR_EL3, TTA, 20, 1)
72
-FIELD(CPTR_EL3, TAM, 30, 1)
73
-FIELD(CPTR_EL3, TCPAC, 31, 1)
74
-
75
-#define MDCR_MTPME (1U << 28)
76
-#define MDCR_TDCC (1U << 27)
77
-#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
78
-#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
79
-#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
80
-#define MDCR_EPMAD (1U << 21)
81
-#define MDCR_EDAD (1U << 20)
82
-#define MDCR_TTRF (1U << 19)
83
-#define MDCR_STE (1U << 18) /* MDCR_EL3 */
84
-#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
85
-#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
86
-#define MDCR_SDD (1U << 16)
87
-#define MDCR_SPD (3U << 14)
88
-#define MDCR_TDRA (1U << 11)
89
-#define MDCR_TDOSA (1U << 10)
90
-#define MDCR_TDA (1U << 9)
91
-#define MDCR_TDE (1U << 8)
92
-#define MDCR_HPME (1U << 7)
93
-#define MDCR_TPM (1U << 6)
94
-#define MDCR_TPMCR (1U << 5)
95
-#define MDCR_HPMN (0x1fU)
96
-
97
-/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
98
-#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
99
- MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
100
- MDCR_STE | MDCR_SPME | MDCR_SPD)
101
-
102
#define CPSR_M (0x1fU)
103
#define CPSR_T (1U << 5)
104
#define CPSR_F (1U << 6)
105
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
106
#define XPSR_NZCV CPSR_NZCV
107
#define XPSR_IT CPSR_IT
108
109
-#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
110
-#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
111
-#define TTBCR_PD0 (1U << 4)
112
-#define TTBCR_PD1 (1U << 5)
113
-#define TTBCR_EPD0 (1U << 7)
114
-#define TTBCR_IRGN0 (3U << 8)
115
-#define TTBCR_ORGN0 (3U << 10)
116
-#define TTBCR_SH0 (3U << 12)
117
-#define TTBCR_T1SZ (3U << 16)
118
-#define TTBCR_A1 (1U << 22)
119
-#define TTBCR_EPD1 (1U << 23)
120
-#define TTBCR_IRGN1 (3U << 24)
121
-#define TTBCR_ORGN1 (3U << 26)
122
-#define TTBCR_SH1 (1U << 28)
123
-#define TTBCR_EAE (1U << 31)
124
-
125
-FIELD(VTCR, T0SZ, 0, 6)
126
-FIELD(VTCR, SL0, 6, 2)
127
-FIELD(VTCR, IRGN0, 8, 2)
128
-FIELD(VTCR, ORGN0, 10, 2)
129
-FIELD(VTCR, SH0, 12, 2)
130
-FIELD(VTCR, TG0, 14, 2)
131
-FIELD(VTCR, PS, 16, 3)
132
-FIELD(VTCR, VS, 19, 1)
133
-FIELD(VTCR, HA, 21, 1)
134
-FIELD(VTCR, HD, 22, 1)
135
-FIELD(VTCR, HWU59, 25, 1)
136
-FIELD(VTCR, HWU60, 26, 1)
137
-FIELD(VTCR, HWU61, 27, 1)
138
-FIELD(VTCR, HWU62, 28, 1)
139
-FIELD(VTCR, NSW, 29, 1)
140
-FIELD(VTCR, NSA, 30, 1)
141
-FIELD(VTCR, DS, 32, 1)
142
-FIELD(VTCR, SL2, 33, 1)
143
-
144
/* Bit definitions for ARMv8 SPSR (PSTATE) format.
145
* Only these are valid when in AArch64 mode; in
146
* AArch32 mode SPSRs are basically CPSR-format.
147
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
148
#define HCR_TWEDEN (1ULL << 59)
149
#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
150
151
-#define HCRX_ENAS0 (1ULL << 0)
152
-#define HCRX_ENALS (1ULL << 1)
153
-#define HCRX_ENASR (1ULL << 2)
154
-#define HCRX_FNXS (1ULL << 3)
155
-#define HCRX_FGTNXS (1ULL << 4)
156
-#define HCRX_SMPME (1ULL << 5)
157
-#define HCRX_TALLINT (1ULL << 6)
158
-#define HCRX_VINMI (1ULL << 7)
159
-#define HCRX_VFNMI (1ULL << 8)
160
-#define HCRX_CMOW (1ULL << 9)
161
-#define HCRX_MCE2 (1ULL << 10)
162
-#define HCRX_MSCEN (1ULL << 11)
163
-
164
-#define HPFAR_NS (1ULL << 63)
165
-
166
#define SCR_NS (1ULL << 0)
167
#define SCR_IRQ (1ULL << 1)
168
#define SCR_FIQ (1ULL << 2)
169
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
170
#define SCR_GPF (1ULL << 48)
171
#define SCR_NSE (1ULL << 62)
172
173
-#define HSTR_TTEE (1 << 16)
174
-#define HSTR_TJDBX (1 << 17)
175
-
176
-#define CNTHCTL_CNTVMASK (1 << 18)
177
-#define CNTHCTL_CNTPMASK (1 << 19)
178
-
179
/* Return the current FPSCR value. */
180
uint32_t vfp_get_fpscr(CPUARMState *env);
181
void vfp_set_fpscr(CPUARMState *env, uint32_t val);
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
182
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
184
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
185
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
186
@@ -XXX,XX +XXX,XX @@ FIELD(DBGWCR, WT, 20, 1)
21
/* Return the MMU index for a v7M CPU in the specified security state */
187
FIELD(DBGWCR, MASK, 24, 5)
22
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
188
FIELD(DBGWCR, SSCE, 29, 1)
23
189
24
-/* Return true if the translation regime is using LPAE format page tables */
190
+#define VTCR_NSW (1u << 29)
25
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
191
+#define VTCR_NSA (1u << 30)
26
-
192
+#define VSTCR_SW VTCR_NSW
27
/*
193
+#define VSTCR_SA VTCR_NSA
28
* Return true if the stage 1 translation regime is using LPAE
194
+
29
* format page tables
195
+/* Bit definitions for CPACR (AArch32 only) */
30
@@ -XXX,XX +XXX,XX @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
196
+FIELD(CPACR, CP10, 20, 2)
31
return env->cp15.tcr_el[regime_el(env, mmu_idx)];
197
+FIELD(CPACR, CP11, 22, 2)
32
}
198
+FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
33
199
+FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
34
+/* Return true if the translation regime is using LPAE format page tables */
200
+FIELD(CPACR, ASEDIS, 31, 1)
35
+static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
201
+
36
+{
202
+/* Bit definitions for CPACR_EL1 (AArch64 only) */
37
+ int el = regime_el(env, mmu_idx);
203
+FIELD(CPACR_EL1, ZEN, 16, 2)
38
+ if (el == 2 || arm_el_is_aa64(env, el)) {
204
+FIELD(CPACR_EL1, FPEN, 20, 2)
39
+ return true;
205
+FIELD(CPACR_EL1, SMEN, 24, 2)
40
+ }
206
+FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
41
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
207
+
42
+ arm_feature(env, ARM_FEATURE_V8)) {
208
+/* Bit definitions for HCPTR (AArch32 only) */
43
+ return true;
209
+FIELD(HCPTR, TCP10, 10, 1)
44
+ }
210
+FIELD(HCPTR, TCP11, 11, 1)
45
+ if (arm_feature(env, ARM_FEATURE_LPAE)
211
+FIELD(HCPTR, TASE, 15, 1)
46
+ && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
212
+FIELD(HCPTR, TTA, 20, 1)
47
+ return true;
213
+FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
48
+ }
214
+FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
49
+ return false;
215
+
50
+}
216
+/* Bit definitions for CPTR_EL2 (AArch64 only) */
51
+
217
+FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
52
/**
218
+FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
53
* arm_num_brps: Return number of implemented breakpoints.
219
+FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
54
* Note that the ID register BRPS field is "number of bps - 1",
220
+FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
55
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
221
+FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
56
index XXXXXXX..XXXXXXX 100644
222
+FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
57
--- a/target/arm/tcg/tlb_helper.c
223
+FIELD(CPTR_EL2, TTA, 28, 1)
58
+++ b/target/arm/tcg/tlb_helper.c
224
+FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
59
@@ -XXX,XX +XXX,XX @@
225
+FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
60
#include "exec/helper-proto.h"
226
+
61
227
+/* Bit definitions for CPTR_EL3 (AArch64 only) */
62
228
+FIELD(CPTR_EL3, EZ, 8, 1)
63
-/* Return true if the translation regime is using LPAE format page tables */
229
+FIELD(CPTR_EL3, TFP, 10, 1)
64
-bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
230
+FIELD(CPTR_EL3, ESM, 12, 1)
65
-{
231
+FIELD(CPTR_EL3, TTA, 20, 1)
66
- int el = regime_el(env, mmu_idx);
232
+FIELD(CPTR_EL3, TAM, 30, 1)
67
- if (el == 2 || arm_el_is_aa64(env, el)) {
233
+FIELD(CPTR_EL3, TCPAC, 31, 1)
68
- return true;
234
+
69
- }
235
+#define MDCR_MTPME (1U << 28)
70
- if (arm_feature(env, ARM_FEATURE_PMSA) &&
236
+#define MDCR_TDCC (1U << 27)
71
- arm_feature(env, ARM_FEATURE_V8)) {
237
+#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
72
- return true;
238
+#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
73
- }
239
+#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
74
- if (arm_feature(env, ARM_FEATURE_LPAE)
240
+#define MDCR_EPMAD (1U << 21)
75
- && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
241
+#define MDCR_EDAD (1U << 20)
76
- return true;
242
+#define MDCR_TTRF (1U << 19)
77
- }
243
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
78
- return false;
244
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
79
-}
245
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
80
-
246
+#define MDCR_SDD (1U << 16)
81
/*
247
+#define MDCR_SPD (3U << 14)
82
* Returns true if the stage 1 translation regime is using LPAE format page
248
+#define MDCR_TDRA (1U << 11)
83
* tables. Used when raising alignment exceptions, whose FSR changes depending
249
+#define MDCR_TDOSA (1U << 10)
250
+#define MDCR_TDA (1U << 9)
251
+#define MDCR_TDE (1U << 8)
252
+#define MDCR_HPME (1U << 7)
253
+#define MDCR_TPM (1U << 6)
254
+#define MDCR_TPMCR (1U << 5)
255
+#define MDCR_HPMN (0x1fU)
256
+
257
+/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
258
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
259
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
260
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
261
+
262
+#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
263
+#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
264
+#define TTBCR_PD0 (1U << 4)
265
+#define TTBCR_PD1 (1U << 5)
266
+#define TTBCR_EPD0 (1U << 7)
267
+#define TTBCR_IRGN0 (3U << 8)
268
+#define TTBCR_ORGN0 (3U << 10)
269
+#define TTBCR_SH0 (3U << 12)
270
+#define TTBCR_T1SZ (3U << 16)
271
+#define TTBCR_A1 (1U << 22)
272
+#define TTBCR_EPD1 (1U << 23)
273
+#define TTBCR_IRGN1 (3U << 24)
274
+#define TTBCR_ORGN1 (3U << 26)
275
+#define TTBCR_SH1 (1U << 28)
276
+#define TTBCR_EAE (1U << 31)
277
+
278
+FIELD(VTCR, T0SZ, 0, 6)
279
+FIELD(VTCR, SL0, 6, 2)
280
+FIELD(VTCR, IRGN0, 8, 2)
281
+FIELD(VTCR, ORGN0, 10, 2)
282
+FIELD(VTCR, SH0, 12, 2)
283
+FIELD(VTCR, TG0, 14, 2)
284
+FIELD(VTCR, PS, 16, 3)
285
+FIELD(VTCR, VS, 19, 1)
286
+FIELD(VTCR, HA, 21, 1)
287
+FIELD(VTCR, HD, 22, 1)
288
+FIELD(VTCR, HWU59, 25, 1)
289
+FIELD(VTCR, HWU60, 26, 1)
290
+FIELD(VTCR, HWU61, 27, 1)
291
+FIELD(VTCR, HWU62, 28, 1)
292
+FIELD(VTCR, NSW, 29, 1)
293
+FIELD(VTCR, NSA, 30, 1)
294
+FIELD(VTCR, DS, 32, 1)
295
+FIELD(VTCR, SL2, 33, 1)
296
+
297
+#define HCRX_ENAS0 (1ULL << 0)
298
+#define HCRX_ENALS (1ULL << 1)
299
+#define HCRX_ENASR (1ULL << 2)
300
+#define HCRX_FNXS (1ULL << 3)
301
+#define HCRX_FGTNXS (1ULL << 4)
302
+#define HCRX_SMPME (1ULL << 5)
303
+#define HCRX_TALLINT (1ULL << 6)
304
+#define HCRX_VINMI (1ULL << 7)
305
+#define HCRX_VFNMI (1ULL << 8)
306
+#define HCRX_CMOW (1ULL << 9)
307
+#define HCRX_MCE2 (1ULL << 10)
308
+#define HCRX_MSCEN (1ULL << 11)
309
+
310
+#define HPFAR_NS (1ULL << 63)
311
+
312
+#define HSTR_TTEE (1 << 16)
313
+#define HSTR_TJDBX (1 << 17)
314
+
315
+#define CNTHCTL_CNTVMASK (1 << 18)
316
+#define CNTHCTL_CNTPMASK (1 << 19)
317
+
318
/* We use a few fake FSR values for internal purposes in M profile.
319
* M profile cores don't have A/R format FSRs, but currently our
320
* get_phys_addr() code assumes A/R profile and reports failures via
84
--
321
--
85
2.34.1
322
2.34.1
86
323
87
324
diff view generated by jsdifflib
[PULL 07/25] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
[PULL 02/14] target/arm: Timer _EL02 registers UNDEF for E2H == 0
1
From: Fabiano Rosas <farosas@suse.de>
1
The timer _EL02 registers should UNDEF for invalid accesses from EL2
2
or EL3 when HCR_EL2.E2H == 0, not take a cp access trap. We were
3
delivering the exception to EL2 with the wrong syndrome.
2
4
3
This is in preparation to moving the hflags code into its own file
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
under the tcg/ directory.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20240301183219.2424889-3-peter.maydell@linaro.org
8
---
9
target/arm/helper.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
5
11
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/boot.c | 6 +++++-
12
hw/intc/armv7m_nvic.c | 20 +++++++++++++-------
13
target/arm/arm-powerctl.c | 7 +++++--
14
target/arm/cpu.c | 3 ++-
15
target/arm/helper.c | 18 +++++++++++++-----
16
target/arm/machine.c | 5 ++++-
17
6 files changed, 42 insertions(+), 17 deletions(-)
18
19
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/boot.c
22
+++ b/hw/arm/boot.c
23
@@ -XXX,XX +XXX,XX @@
24
#include "hw/arm/boot.h"
25
#include "hw/arm/linux-boot-if.h"
26
#include "sysemu/kvm.h"
27
+#include "sysemu/tcg.h"
28
#include "sysemu/sysemu.h"
29
#include "sysemu/numa.h"
30
#include "hw/boards.h"
31
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
32
info->secondary_cpu_reset_hook(cpu, info);
33
}
34
}
35
- arm_rebuild_hflags(env);
36
+
37
+ if (tcg_enabled()) {
38
+ arm_rebuild_hflags(env);
39
+ }
40
}
41
}
42
43
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/armv7m_nvic.c
46
+++ b/hw/intc/armv7m_nvic.c
47
@@ -XXX,XX +XXX,XX @@
48
#include "hw/intc/armv7m_nvic.h"
49
#include "hw/irq.h"
50
#include "hw/qdev-properties.h"
51
+#include "sysemu/tcg.h"
52
#include "sysemu/runstate.h"
53
#include "target/arm/cpu.h"
54
#include "exec/exec-all.h"
55
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
56
/* This is UNPREDICTABLE; treat as RAZ/WI */
57
58
exit_ok:
59
- /* Ensure any changes made are reflected in the cached hflags. */
60
- arm_rebuild_hflags(&s->cpu->env);
61
+ if (tcg_enabled()) {
62
+ /* Ensure any changes made are reflected in the cached hflags. */
63
+ arm_rebuild_hflags(&s->cpu->env);
64
+ }
65
return MEMTX_OK;
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
69
}
70
}
71
72
- /*
73
- * We updated state that affects the CPU's MMUidx and thus its hflags;
74
- * and we can't guarantee that we run before the CPU reset function.
75
- */
76
- arm_rebuild_hflags(&s->cpu->env);
77
+ if (tcg_enabled()) {
78
+ /*
79
+ * We updated state that affects the CPU's MMUidx and thus its
80
+ * hflags; and we can't guarantee that we run before the CPU
81
+ * reset function.
82
+ */
83
+ arm_rebuild_hflags(&s->cpu->env);
84
+ }
85
}
86
87
static void nvic_systick_trigger(void *opaque, int n, int level)
88
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/arm-powerctl.c
91
+++ b/target/arm/arm-powerctl.c
92
@@ -XXX,XX +XXX,XX @@
93
#include "arm-powerctl.h"
94
#include "qemu/log.h"
95
#include "qemu/main-loop.h"
96
+#include "sysemu/tcg.h"
97
98
#ifndef DEBUG_ARM_POWERCTL
99
#define DEBUG_ARM_POWERCTL 0
100
@@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state,
101
target_cpu->env.regs[0] = info->context_id;
102
}
103
104
- /* CP15 update requires rebuilding hflags */
105
- arm_rebuild_hflags(&target_cpu->env);
106
+ if (tcg_enabled()) {
107
+ /* CP15 update requires rebuilding hflags */
108
+ arm_rebuild_hflags(&target_cpu->env);
109
+ }
110
111
/* Start the new CPU at the requested address */
112
cpu_set_pc(target_cpu_state, info->entry);
113
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/cpu.c
116
+++ b/target/arm/cpu.c
117
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
118
if (tcg_enabled()) {
119
hw_breakpoint_update_all(cpu);
120
hw_watchpoint_update_all(cpu);
121
+
122
+ arm_rebuild_hflags(env);
123
}
124
- arm_rebuild_hflags(env);
125
}
126
127
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
128
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
129
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
131
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
132
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
16
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
133
/* This may enable/disable the MMU, so do a TLB flush. */
17
return CP_ACCESS_OK;
134
tlb_flush(CPU(cpu));
135
136
- if (ri->type & ARM_CP_SUPPRESS_TB_END) {
137
+ if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
138
/*
139
* Normally we would always end the TB on an SCTLR write; see the
140
* comment in ARMCPRegInfo sctlr initialization below for why Xscale
141
@@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask)
142
memset(env->zarray, 0, sizeof(env->zarray));
143
}
18
}
144
19
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
145
- arm_rebuild_hflags(env);
20
- return CP_ACCESS_TRAP;
146
+ if (tcg_enabled()) {
21
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
147
+ arm_rebuild_hflags(env);
148
+ }
149
}
150
151
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
152
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
153
}
22
}
154
mask &= ~CACHED_CPSR_BITS;
23
return CP_ACCESS_OK;
155
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
156
- if (rebuild_hflags) {
157
+ if (tcg_enabled() && rebuild_hflags) {
158
arm_rebuild_hflags(env);
159
}
160
}
161
@@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
162
env->regs[14] = env->regs[15] + offset;
163
}
164
env->regs[15] = newpc;
165
- arm_rebuild_hflags(env);
166
+
167
+ if (tcg_enabled()) {
168
+ arm_rebuild_hflags(env);
169
+ }
170
}
171
172
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
173
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
174
pstate_write(env, PSTATE_DAIF | new_mode);
175
env->aarch64 = true;
176
aarch64_restore_sp(env, new_el);
177
- helper_rebuild_hflags_a64(env, new_el);
178
+
179
+ if (tcg_enabled()) {
180
+ helper_rebuild_hflags_a64(env, new_el);
181
+ }
182
183
env->pc = addr;
184
185
diff --git a/target/arm/machine.c b/target/arm/machine.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/target/arm/machine.c
188
+++ b/target/arm/machine.c
189
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
190
if (!kvm_enabled()) {
191
pmu_op_finish(&cpu->env);
192
}
193
- arm_rebuild_hflags(&cpu->env);
194
+
195
+ if (tcg_enabled()) {
196
+ arm_rebuild_hflags(&cpu->env);
197
+ }
198
199
return 0;
200
}
24
}
201
--
25
--
202
2.34.1
26
2.34.1
203
204
diff view generated by jsdifflib
[PULL 08/25] target/arm: Move hflags code into the tcg directory
[PULL 03/14] target/arm: use FIELD macro for CNTHCTL bit definitions
1
From: Fabiano Rosas <farosas@suse.de>
1
We prefer the FIELD macro over ad-hoc #defines for register bits;
2
switch CNTHCTL to that style before we add any more bits.
2
3
3
The hflags are used only for TCG code, so introduce a new file
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
hflags.c to keep that code.
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240301183219.2424889-4-peter.maydell@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
target/arm/internals.h | 2 +
9
target/arm/internals.h | 27 +++++++++++++++++++++++++--
12
target/arm/helper.c | 393 +-----------------------------------
10
target/arm/helper.c | 9 ++++-----
13
target/arm/tcg-stubs.c | 4 +
11
2 files changed, 29 insertions(+), 7 deletions(-)
14
target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++++++++++++++
15
target/arm/tcg/meson.build | 1 +
16
5 files changed, 411 insertions(+), 392 deletions(-)
17
create mode 100644 target/arm/tcg/hflags.c
18
12
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
15
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
16
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
17
@@ -XXX,XX +XXX,XX @@ FIELD(VTCR, SL2, 33, 1)
24
18
#define HSTR_TTEE (1 << 16)
25
int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
19
#define HSTR_TJDBX (1 << 17)
26
int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
20
27
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx);
21
-#define CNTHCTL_CNTVMASK (1 << 18)
28
22
-#define CNTHCTL_CNTPMASK (1 << 19)
29
/* Determine if allocation tags are available. */
23
+/*
30
static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
24
+ * Depending on the value of HCR_EL2.E2H, bits 0 and 1
31
@@ -XXX,XX +XXX,XX @@ static inline bool arm_fgt_active(CPUARMState *env, int el)
25
+ * have different bit definitions, and EL1PCTEN might be
32
(!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
26
+ * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
33
}
27
+ * disambiguate if necessary.
34
28
+ */
35
+void assert_hflags_rebuild_correctly(CPUARMState *env);
29
+FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
36
#endif
30
+FIELD(CNTHCTL, EL0VCTEN_E2H1, 1, 1)
31
+FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
32
+FIELD(CNTHCTL, EL1PCEN_E2H0, 1, 1)
33
+FIELD(CNTHCTL, EVNTEN, 2, 1)
34
+FIELD(CNTHCTL, EVNTDIR, 3, 1)
35
+FIELD(CNTHCTL, EVNTI, 4, 4)
36
+FIELD(CNTHCTL, EL0VTEN, 8, 1)
37
+FIELD(CNTHCTL, EL0PTEN, 9, 1)
38
+FIELD(CNTHCTL, EL1PCTEN_E2H1, 10, 1)
39
+FIELD(CNTHCTL, EL1PTEN, 11, 1)
40
+FIELD(CNTHCTL, ECV, 12, 1)
41
+FIELD(CNTHCTL, EL1TVT, 13, 1)
42
+FIELD(CNTHCTL, EL1TVCT, 14, 1)
43
+FIELD(CNTHCTL, EL1NVPCT, 15, 1)
44
+FIELD(CNTHCTL, EL1NVVCT, 16, 1)
45
+FIELD(CNTHCTL, EVNTIS, 17, 1)
46
+FIELD(CNTHCTL, CNTVMASK, 18, 1)
47
+FIELD(CNTHCTL, CNTPMASK, 19, 1)
48
49
/* We use a few fake FSR values for internal purposes in M profile.
50
* M profile cores don't have A/R format FSRs, but currently our
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
51
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
53
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
54
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el)
55
@@ -XXX,XX +XXX,XX @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
42
return 0;
56
* It is RES0 in Secure and NonSecure state.
43
}
57
*/
44
58
if ((ss == ARMSS_Root || ss == ARMSS_Realm) &&
45
-/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
59
- ((timeridx == GTIMER_VIRT && (cnthctl & CNTHCTL_CNTVMASK)) ||
46
-static bool sme_fa64(CPUARMState *env, int el)
60
- (timeridx == GTIMER_PHYS && (cnthctl & CNTHCTL_CNTPMASK)))) {
47
-{
61
+ ((timeridx == GTIMER_VIRT && (cnthctl & R_CNTHCTL_CNTVMASK_MASK)) ||
48
- if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
62
+ (timeridx == GTIMER_PHYS && (cnthctl & R_CNTHCTL_CNTPMASK_MASK)))) {
49
- return false;
63
irqstate = 0;
50
- }
64
}
65
66
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
67
{
68
ARMCPU *cpu = env_archcpu(env);
69
uint32_t oldval = env->cp15.cnthctl_el2;
51
-
70
-
52
- if (el <= 1 && !el_is_in_host(env, el)) {
71
raw_write(env, ri, value);
53
- if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
72
54
- return false;
73
- if ((oldval ^ value) & CNTHCTL_CNTVMASK) {
55
- }
74
+ if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
56
- }
75
gt_update_irq(cpu, GTIMER_VIRT);
57
- if (el <= 2 && arm_is_el2_enabled(env)) {
76
- } else if ((oldval ^ value) & CNTHCTL_CNTPMASK) {
58
- if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
77
+ } else if ((oldval ^ value) & R_CNTHCTL_CNTPMASK_MASK) {
59
- return false;
78
gt_update_irq(cpu, GTIMER_PHYS);
60
- }
61
- }
62
- if (arm_feature(env, ARM_FEATURE_EL3)) {
63
- if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
64
- return false;
65
- }
66
- }
67
-
68
- return true;
69
-}
70
-
71
/*
72
* Given that SVE is enabled, return the vector length for EL.
73
*/
74
@@ -XXX,XX +XXX,XX @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
75
}
79
}
76
}
80
}
77
78
-static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
79
+int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
80
{
81
if (regime_has_2_ranges(mmu_idx)) {
82
return extract64(tcr, 57, 2);
83
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
84
return arm_mmu_idx_el(env, arm_current_el(env));
85
}
86
87
-static inline bool fgt_svc(CPUARMState *env, int el)
88
-{
89
- /*
90
- * Assuming fine-grained-traps are active, return true if we
91
- * should be trapping on SVC instructions. Only AArch64 can
92
- * trap on an SVC at EL1, but we don't need to special-case this
93
- * because if this is AArch32 EL1 then arm_fgt_active() is false.
94
- * We also know el is 0 or 1.
95
- */
96
- return el == 0 ?
97
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
98
- FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
99
-}
100
-
101
-static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
102
- ARMMMUIdx mmu_idx,
103
- CPUARMTBFlags flags)
104
-{
105
- DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
106
- DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
107
-
108
- if (arm_singlestep_active(env)) {
109
- DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
110
- }
111
-
112
- return flags;
113
-}
114
-
115
-static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
116
- ARMMMUIdx mmu_idx,
117
- CPUARMTBFlags flags)
118
-{
119
- bool sctlr_b = arm_sctlr_b(env);
120
-
121
- if (sctlr_b) {
122
- DP_TBFLAG_A32(flags, SCTLR__B, 1);
123
- }
124
- if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
125
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
126
- }
127
- DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
128
-
129
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
130
-}
131
-
132
-static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
133
- ARMMMUIdx mmu_idx)
134
-{
135
- CPUARMTBFlags flags = {};
136
- uint32_t ccr = env->v7m.ccr[env->v7m.secure];
137
-
138
- /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
139
- if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
140
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
141
- }
142
-
143
- if (arm_v7m_is_handler_mode(env)) {
144
- DP_TBFLAG_M32(flags, HANDLER, 1);
145
- }
146
-
147
- /*
148
- * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
149
- * is suppressing them because the requested execution priority
150
- * is less than 0.
151
- */
152
- if (arm_feature(env, ARM_FEATURE_V8) &&
153
- !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
154
- (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
155
- DP_TBFLAG_M32(flags, STACKCHECK, 1);
156
- }
157
-
158
- if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
159
- DP_TBFLAG_M32(flags, SECURE, 1);
160
- }
161
-
162
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
163
-}
164
-
165
-static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
166
- ARMMMUIdx mmu_idx)
167
-{
168
- CPUARMTBFlags flags = {};
169
- int el = arm_current_el(env);
170
-
171
- if (arm_sctlr(env, el) & SCTLR_A) {
172
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
173
- }
174
-
175
- if (arm_el_is_aa64(env, 1)) {
176
- DP_TBFLAG_A32(flags, VFPEN, 1);
177
- }
178
-
179
- if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
180
- (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
181
- DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
182
- }
183
-
184
- if (arm_fgt_active(env, el)) {
185
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
186
- if (fgt_svc(env, el)) {
187
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
188
- }
189
- }
190
-
191
- if (env->uncached_cpsr & CPSR_IL) {
192
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
193
- }
194
-
195
- /*
196
- * The SME exception we are testing for is raised via
197
- * AArch64.CheckFPAdvSIMDEnabled(), as called from
198
- * AArch32.CheckAdvSIMDOrFPEnabled().
199
- */
200
- if (el == 0
201
- && FIELD_EX64(env->svcr, SVCR, SM)
202
- && (!arm_is_el2_enabled(env)
203
- || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
204
- && arm_el_is_aa64(env, 1)
205
- && !sme_fa64(env, el)) {
206
- DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
207
- }
208
-
209
- return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
210
-}
211
-
212
-static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
213
- ARMMMUIdx mmu_idx)
214
-{
215
- CPUARMTBFlags flags = {};
216
- ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
217
- uint64_t tcr = regime_tcr(env, mmu_idx);
218
- uint64_t sctlr;
219
- int tbii, tbid;
220
-
221
- DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
222
-
223
- /* Get control bits for tagged addresses. */
224
- tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
225
- tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
226
-
227
- DP_TBFLAG_A64(flags, TBII, tbii);
228
- DP_TBFLAG_A64(flags, TBID, tbid);
229
-
230
- if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
231
- int sve_el = sve_exception_el(env, el);
232
-
233
- /*
234
- * If either FP or SVE are disabled, translator does not need len.
235
- * If SVE EL > FP EL, FP exception has precedence, and translator
236
- * does not need SVE EL. Save potential re-translations by forcing
237
- * the unneeded data to zero.
238
- */
239
- if (fp_el != 0) {
240
- if (sve_el > fp_el) {
241
- sve_el = 0;
242
- }
243
- } else if (sve_el == 0) {
244
- DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
245
- }
246
- DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
247
- }
248
- if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
249
- int sme_el = sme_exception_el(env, el);
250
- bool sm = FIELD_EX64(env->svcr, SVCR, SM);
251
-
252
- DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
253
- if (sme_el == 0) {
254
- /* Similarly, do not compute SVL if SME is disabled. */
255
- int svl = sve_vqm1_for_el_sm(env, el, true);
256
- DP_TBFLAG_A64(flags, SVL, svl);
257
- if (sm) {
258
- /* If SVE is disabled, we will not have set VL above. */
259
- DP_TBFLAG_A64(flags, VL, svl);
260
- }
261
- }
262
- if (sm) {
263
- DP_TBFLAG_A64(flags, PSTATE_SM, 1);
264
- DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
265
- }
266
- DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
267
- }
268
-
269
- sctlr = regime_sctlr(env, stage1);
270
-
271
- if (sctlr & SCTLR_A) {
272
- DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
273
- }
274
-
275
- if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
276
- DP_TBFLAG_ANY(flags, BE_DATA, 1);
277
- }
278
-
279
- if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
280
- /*
281
- * In order to save space in flags, we record only whether
282
- * pauth is "inactive", meaning all insns are implemented as
283
- * a nop, or "active" when some action must be performed.
284
- * The decision of which action to take is left to a helper.
285
- */
286
- if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
287
- DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
288
- }
289
- }
290
-
291
- if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
292
- /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
293
- if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
294
- DP_TBFLAG_A64(flags, BT, 1);
295
- }
296
- }
297
-
298
- /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
299
- if (!(env->pstate & PSTATE_UAO)) {
300
- switch (mmu_idx) {
301
- case ARMMMUIdx_E10_1:
302
- case ARMMMUIdx_E10_1_PAN:
303
- /* TODO: ARMv8.3-NV */
304
- DP_TBFLAG_A64(flags, UNPRIV, 1);
305
- break;
306
- case ARMMMUIdx_E20_2:
307
- case ARMMMUIdx_E20_2_PAN:
308
- /*
309
- * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
310
- * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
311
- */
312
- if (env->cp15.hcr_el2 & HCR_TGE) {
313
- DP_TBFLAG_A64(flags, UNPRIV, 1);
314
- }
315
- break;
316
- default:
317
- break;
318
- }
319
- }
320
-
321
- if (env->pstate & PSTATE_IL) {
322
- DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
323
- }
324
-
325
- if (arm_fgt_active(env, el)) {
326
- DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
327
- if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
328
- DP_TBFLAG_A64(flags, FGT_ERET, 1);
329
- }
330
- if (fgt_svc(env, el)) {
331
- DP_TBFLAG_ANY(flags, FGT_SVC, 1);
332
- }
333
- }
334
-
335
- if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
336
- /*
337
- * Set MTE_ACTIVE if any access may be Checked, and leave clear
338
- * if all accesses must be Unchecked:
339
- * 1) If no TBI, then there are no tags in the address to check,
340
- * 2) If Tag Check Override, then all accesses are Unchecked,
341
- * 3) If Tag Check Fail == 0, then Checked access have no effect,
342
- * 4) If no Allocation Tag Access, then all accesses are Unchecked.
343
- */
344
- if (allocation_tag_access_enabled(env, el, sctlr)) {
345
- DP_TBFLAG_A64(flags, ATA, 1);
346
- if (tbid
347
- && !(env->pstate & PSTATE_TCO)
348
- && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
349
- DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
350
- }
351
- }
352
- /* And again for unprivileged accesses, if required. */
353
- if (EX_TBFLAG_A64(flags, UNPRIV)
354
- && tbid
355
- && !(env->pstate & PSTATE_TCO)
356
- && (sctlr & SCTLR_TCF0)
357
- && allocation_tag_access_enabled(env, 0, sctlr)) {
358
- DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
359
- }
360
- /* Cache TCMA as well as TBI. */
361
- DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
362
- }
363
-
364
- return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
365
-}
366
-
367
-static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
368
-{
369
- int el = arm_current_el(env);
370
- int fp_el = fp_exception_el(env, el);
371
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
372
-
373
- if (is_a64(env)) {
374
- return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
375
- } else if (arm_feature(env, ARM_FEATURE_M)) {
376
- return rebuild_hflags_m32(env, fp_el, mmu_idx);
377
- } else {
378
- return rebuild_hflags_a32(env, fp_el, mmu_idx);
379
- }
380
-}
381
-
382
-void arm_rebuild_hflags(CPUARMState *env)
383
-{
384
- env->hflags = rebuild_hflags_internal(env);
385
-}
386
-
387
-/*
388
- * If we have triggered a EL state change we can't rely on the
389
- * translator having passed it to us, we need to recompute.
390
- */
391
-void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
392
-{
393
- int el = arm_current_el(env);
394
- int fp_el = fp_exception_el(env, el);
395
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
396
-
397
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
398
-}
399
-
400
-void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
401
-{
402
- int fp_el = fp_exception_el(env, el);
403
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
404
-
405
- env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
406
-}
407
-
408
-/*
409
- * If we have triggered a EL state change we can't rely on the
410
- * translator having passed it to us, we need to recompute.
411
- */
412
-void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
413
-{
414
- int el = arm_current_el(env);
415
- int fp_el = fp_exception_el(env, el);
416
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
417
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
418
-}
419
-
420
-void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
421
-{
422
- int fp_el = fp_exception_el(env, el);
423
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
424
-
425
- env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
426
-}
427
-
428
-void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
429
-{
430
- int fp_el = fp_exception_el(env, el);
431
- ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
432
-
433
- env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
434
-}
435
-
436
-static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
437
-{
438
-#ifdef CONFIG_DEBUG_TCG
439
- CPUARMTBFlags c = env->hflags;
440
- CPUARMTBFlags r = rebuild_hflags_internal(env);
441
-
442
- if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
443
- fprintf(stderr, "TCG hflags mismatch "
444
- "(current:(0x%08x,0x" TARGET_FMT_lx ")"
445
- " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
446
- c.flags, c.flags2, r.flags, r.flags2);
447
- abort();
448
- }
449
-#endif
450
-}
451
-
452
static bool mve_no_pred(CPUARMState *env)
453
{
454
/*
455
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
456
index XXXXXXX..XXXXXXX 100644
457
--- a/target/arm/tcg-stubs.c
458
+++ b/target/arm/tcg-stubs.c
459
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
460
{
461
g_assert_not_reached();
462
}
463
+/* Temporarily while cpu_get_tb_cpu_state() is still in common code */
464
+void assert_hflags_rebuild_correctly(CPUARMState *env)
465
+{
466
+}
467
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
468
new file mode 100644
469
index XXXXXXX..XXXXXXX
470
--- /dev/null
471
+++ b/target/arm/tcg/hflags.c
472
@@ -XXX,XX +XXX,XX @@
473
+/*
474
+ * ARM hflags
475
+ *
476
+ * This code is licensed under the GNU GPL v2 or later.
477
+ *
478
+ * SPDX-License-Identifier: GPL-2.0-or-later
479
+ */
480
+#include "qemu/osdep.h"
481
+#include "cpu.h"
482
+#include "internals.h"
483
+#include "exec/helper-proto.h"
484
+#include "cpregs.h"
485
+
486
+static inline bool fgt_svc(CPUARMState *env, int el)
487
+{
488
+ /*
489
+ * Assuming fine-grained-traps are active, return true if we
490
+ * should be trapping on SVC instructions. Only AArch64 can
491
+ * trap on an SVC at EL1, but we don't need to special-case this
492
+ * because if this is AArch32 EL1 then arm_fgt_active() is false.
493
+ * We also know el is 0 or 1.
494
+ */
495
+ return el == 0 ?
496
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
497
+ FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
498
+}
499
+
500
+static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
501
+ ARMMMUIdx mmu_idx,
502
+ CPUARMTBFlags flags)
503
+{
504
+ DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
505
+ DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
506
+
507
+ if (arm_singlestep_active(env)) {
508
+ DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
509
+ }
510
+
511
+ return flags;
512
+}
513
+
514
+static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
515
+ ARMMMUIdx mmu_idx,
516
+ CPUARMTBFlags flags)
517
+{
518
+ bool sctlr_b = arm_sctlr_b(env);
519
+
520
+ if (sctlr_b) {
521
+ DP_TBFLAG_A32(flags, SCTLR__B, 1);
522
+ }
523
+ if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
524
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
525
+ }
526
+ DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
527
+
528
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
529
+}
530
+
531
+static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
532
+ ARMMMUIdx mmu_idx)
533
+{
534
+ CPUARMTBFlags flags = {};
535
+ uint32_t ccr = env->v7m.ccr[env->v7m.secure];
536
+
537
+ /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
538
+ if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
539
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
540
+ }
541
+
542
+ if (arm_v7m_is_handler_mode(env)) {
543
+ DP_TBFLAG_M32(flags, HANDLER, 1);
544
+ }
545
+
546
+ /*
547
+ * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN
548
+ * is suppressing them because the requested execution priority
549
+ * is less than 0.
550
+ */
551
+ if (arm_feature(env, ARM_FEATURE_V8) &&
552
+ !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
553
+ (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
554
+ DP_TBFLAG_M32(flags, STACKCHECK, 1);
555
+ }
556
+
557
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
558
+ DP_TBFLAG_M32(flags, SECURE, 1);
559
+ }
560
+
561
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
562
+}
563
+
564
+/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */
565
+static bool sme_fa64(CPUARMState *env, int el)
566
+{
567
+ if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) {
568
+ return false;
569
+ }
570
+
571
+ if (el <= 1 && !el_is_in_host(env, el)) {
572
+ if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) {
573
+ return false;
574
+ }
575
+ }
576
+ if (el <= 2 && arm_is_el2_enabled(env)) {
577
+ if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) {
578
+ return false;
579
+ }
580
+ }
581
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
582
+ if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) {
583
+ return false;
584
+ }
585
+ }
586
+
587
+ return true;
588
+}
589
+
590
+static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
591
+ ARMMMUIdx mmu_idx)
592
+{
593
+ CPUARMTBFlags flags = {};
594
+ int el = arm_current_el(env);
595
+
596
+ if (arm_sctlr(env, el) & SCTLR_A) {
597
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
598
+ }
599
+
600
+ if (arm_el_is_aa64(env, 1)) {
601
+ DP_TBFLAG_A32(flags, VFPEN, 1);
602
+ }
603
+
604
+ if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
605
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
606
+ DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
607
+ }
608
+
609
+ if (arm_fgt_active(env, el)) {
610
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
611
+ if (fgt_svc(env, el)) {
612
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
613
+ }
614
+ }
615
+
616
+ if (env->uncached_cpsr & CPSR_IL) {
617
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
618
+ }
619
+
620
+ /*
621
+ * The SME exception we are testing for is raised via
622
+ * AArch64.CheckFPAdvSIMDEnabled(), as called from
623
+ * AArch32.CheckAdvSIMDOrFPEnabled().
624
+ */
625
+ if (el == 0
626
+ && FIELD_EX64(env->svcr, SVCR, SM)
627
+ && (!arm_is_el2_enabled(env)
628
+ || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE)))
629
+ && arm_el_is_aa64(env, 1)
630
+ && !sme_fa64(env, el)) {
631
+ DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1);
632
+ }
633
+
634
+ return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
635
+}
636
+
637
+static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
638
+ ARMMMUIdx mmu_idx)
639
+{
640
+ CPUARMTBFlags flags = {};
641
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
642
+ uint64_t tcr = regime_tcr(env, mmu_idx);
643
+ uint64_t sctlr;
644
+ int tbii, tbid;
645
+
646
+ DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
647
+
648
+ /* Get control bits for tagged addresses. */
649
+ tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
650
+ tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
651
+
652
+ DP_TBFLAG_A64(flags, TBII, tbii);
653
+ DP_TBFLAG_A64(flags, TBID, tbid);
654
+
655
+ if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
656
+ int sve_el = sve_exception_el(env, el);
657
+
658
+ /*
659
+ * If either FP or SVE are disabled, translator does not need len.
660
+ * If SVE EL > FP EL, FP exception has precedence, and translator
661
+ * does not need SVE EL. Save potential re-translations by forcing
662
+ * the unneeded data to zero.
663
+ */
664
+ if (fp_el != 0) {
665
+ if (sve_el > fp_el) {
666
+ sve_el = 0;
667
+ }
668
+ } else if (sve_el == 0) {
669
+ DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el));
670
+ }
671
+ DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
672
+ }
673
+ if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
674
+ int sme_el = sme_exception_el(env, el);
675
+ bool sm = FIELD_EX64(env->svcr, SVCR, SM);
676
+
677
+ DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el);
678
+ if (sme_el == 0) {
679
+ /* Similarly, do not compute SVL if SME is disabled. */
680
+ int svl = sve_vqm1_for_el_sm(env, el, true);
681
+ DP_TBFLAG_A64(flags, SVL, svl);
682
+ if (sm) {
683
+ /* If SVE is disabled, we will not have set VL above. */
684
+ DP_TBFLAG_A64(flags, VL, svl);
685
+ }
686
+ }
687
+ if (sm) {
688
+ DP_TBFLAG_A64(flags, PSTATE_SM, 1);
689
+ DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el));
690
+ }
691
+ DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA));
692
+ }
693
+
694
+ sctlr = regime_sctlr(env, stage1);
695
+
696
+ if (sctlr & SCTLR_A) {
697
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
698
+ }
699
+
700
+ if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
701
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
702
+ }
703
+
704
+ if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
705
+ /*
706
+ * In order to save space in flags, we record only whether
707
+ * pauth is "inactive", meaning all insns are implemented as
708
+ * a nop, or "active" when some action must be performed.
709
+ * The decision of which action to take is left to a helper.
710
+ */
711
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
712
+ DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
713
+ }
714
+ }
715
+
716
+ if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
717
+ /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
718
+ if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
719
+ DP_TBFLAG_A64(flags, BT, 1);
720
+ }
721
+ }
722
+
723
+ /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
724
+ if (!(env->pstate & PSTATE_UAO)) {
725
+ switch (mmu_idx) {
726
+ case ARMMMUIdx_E10_1:
727
+ case ARMMMUIdx_E10_1_PAN:
728
+ /* TODO: ARMv8.3-NV */
729
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
730
+ break;
731
+ case ARMMMUIdx_E20_2:
732
+ case ARMMMUIdx_E20_2_PAN:
733
+ /*
734
+ * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
735
+ * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
736
+ */
737
+ if (env->cp15.hcr_el2 & HCR_TGE) {
738
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
739
+ }
740
+ break;
741
+ default:
742
+ break;
743
+ }
744
+ }
745
+
746
+ if (env->pstate & PSTATE_IL) {
747
+ DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
748
+ }
749
+
750
+ if (arm_fgt_active(env, el)) {
751
+ DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
752
+ if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
753
+ DP_TBFLAG_A64(flags, FGT_ERET, 1);
754
+ }
755
+ if (fgt_svc(env, el)) {
756
+ DP_TBFLAG_ANY(flags, FGT_SVC, 1);
757
+ }
758
+ }
759
+
760
+ if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
761
+ /*
762
+ * Set MTE_ACTIVE if any access may be Checked, and leave clear
763
+ * if all accesses must be Unchecked:
764
+ * 1) If no TBI, then there are no tags in the address to check,
765
+ * 2) If Tag Check Override, then all accesses are Unchecked,
766
+ * 3) If Tag Check Fail == 0, then Checked access have no effect,
767
+ * 4) If no Allocation Tag Access, then all accesses are Unchecked.
768
+ */
769
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
770
+ DP_TBFLAG_A64(flags, ATA, 1);
771
+ if (tbid
772
+ && !(env->pstate & PSTATE_TCO)
773
+ && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
774
+ DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
775
+ }
776
+ }
777
+ /* And again for unprivileged accesses, if required. */
778
+ if (EX_TBFLAG_A64(flags, UNPRIV)
779
+ && tbid
780
+ && !(env->pstate & PSTATE_TCO)
781
+ && (sctlr & SCTLR_TCF0)
782
+ && allocation_tag_access_enabled(env, 0, sctlr)) {
783
+ DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
784
+ }
785
+ /* Cache TCMA as well as TBI. */
786
+ DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
787
+ }
788
+
789
+ return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
790
+}
791
+
792
+static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
793
+{
794
+ int el = arm_current_el(env);
795
+ int fp_el = fp_exception_el(env, el);
796
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
797
+
798
+ if (is_a64(env)) {
799
+ return rebuild_hflags_a64(env, el, fp_el, mmu_idx);
800
+ } else if (arm_feature(env, ARM_FEATURE_M)) {
801
+ return rebuild_hflags_m32(env, fp_el, mmu_idx);
802
+ } else {
803
+ return rebuild_hflags_a32(env, fp_el, mmu_idx);
804
+ }
805
+}
806
+
807
+void arm_rebuild_hflags(CPUARMState *env)
808
+{
809
+ env->hflags = rebuild_hflags_internal(env);
810
+}
811
+
812
+/*
813
+ * If we have triggered a EL state change we can't rely on the
814
+ * translator having passed it to us, we need to recompute.
815
+ */
816
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
817
+{
818
+ int el = arm_current_el(env);
819
+ int fp_el = fp_exception_el(env, el);
820
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
821
+
822
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
823
+}
824
+
825
+void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
826
+{
827
+ int fp_el = fp_exception_el(env, el);
828
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
829
+
830
+ env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
831
+}
832
+
833
+/*
834
+ * If we have triggered a EL state change we can't rely on the
835
+ * translator having passed it to us, we need to recompute.
836
+ */
837
+void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
838
+{
839
+ int el = arm_current_el(env);
840
+ int fp_el = fp_exception_el(env, el);
841
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
842
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
843
+}
844
+
845
+void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el)
846
+{
847
+ int fp_el = fp_exception_el(env, el);
848
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
849
+
850
+ env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx);
851
+}
852
+
853
+void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
854
+{
855
+ int fp_el = fp_exception_el(env, el);
856
+ ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
857
+
858
+ env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx);
859
+}
860
+
861
+void assert_hflags_rebuild_correctly(CPUARMState *env)
862
+{
863
+#ifdef CONFIG_DEBUG_TCG
864
+ CPUARMTBFlags c = env->hflags;
865
+ CPUARMTBFlags r = rebuild_hflags_internal(env);
866
+
867
+ if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
868
+ fprintf(stderr, "TCG hflags mismatch "
869
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
870
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
871
+ c.flags, c.flags2, r.flags, r.flags2);
872
+ abort();
873
+ }
874
+#endif
875
+}
876
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
877
index XXXXXXX..XXXXXXX 100644
878
--- a/target/arm/tcg/meson.build
879
+++ b/target/arm/tcg/meson.build
880
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
881
'translate-neon.c',
882
'translate-vfp.c',
883
'crypto_helper.c',
884
+ 'hflags.c',
885
'iwmmxt_helper.c',
886
'm_helper.c',
887
'mve_helper.c',
888
--
81
--
889
2.34.1
82
2.34.1
890
83
891
84
diff view generated by jsdifflib
[PULL 02/25] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
[PULL 04/14] target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
1
From: Fabiano Rosas <farosas@suse.de>
1
Don't allow the guest to write CNTHCTL_EL2 bits which don't exist.
2
This is not strictly architecturally required, but it is how we've
3
tended to implement registers more recently.
2
4
3
This is in preparation for restricting compilation of some parts of
5
In particular, bits [19:18] are only present with FEAT_RME,
4
debug_helper.c to TCG only.
6
and bits [17:12] will only be present with FEAT_ECV.
5
7
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240301183219.2424889-5-peter.maydell@linaro.org
9
---
11
---
10
target/arm/cpu.c | 6 ++++--
12
target/arm/helper.c | 18 ++++++++++++++++++
11
target/arm/debug_helper.c | 16 ++++++++++++----
13
1 file changed, 18 insertions(+)
12
target/arm/machine.c | 7 +++++--
13
3 files changed, 21 insertions(+), 8 deletions(-)
14
14
15
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.c
17
--- a/target/arm/helper.c
18
+++ b/target/arm/cpu.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
}
20
{
21
#endif
21
ARMCPU *cpu = env_archcpu(env);
22
22
uint32_t oldval = env->cp15.cnthctl_el2;
23
- hw_breakpoint_update_all(cpu);
23
+ uint32_t valid_mask =
24
- hw_watchpoint_update_all(cpu);
24
+ R_CNTHCTL_EL0PCTEN_E2H1_MASK |
25
+ if (tcg_enabled()) {
25
+ R_CNTHCTL_EL0VCTEN_E2H1_MASK |
26
+ hw_breakpoint_update_all(cpu);
26
+ R_CNTHCTL_EVNTEN_MASK |
27
+ hw_watchpoint_update_all(cpu);
27
+ R_CNTHCTL_EVNTDIR_MASK |
28
+ R_CNTHCTL_EVNTI_MASK |
29
+ R_CNTHCTL_EL0VTEN_MASK |
30
+ R_CNTHCTL_EL0PTEN_MASK |
31
+ R_CNTHCTL_EL1PCTEN_E2H1_MASK |
32
+ R_CNTHCTL_EL1PTEN_MASK;
33
+
34
+ if (cpu_isar_feature(aa64_rme, cpu)) {
35
+ valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
28
+ }
36
+ }
29
arm_rebuild_hflags(env);
37
+
30
}
38
+ /* Clear RES0 bits */
31
39
+ value &= valid_mask;
32
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
40
+
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/debug_helper.c
35
+++ b/target/arm/debug_helper.c
36
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
37
value &= ~3ULL;
38
39
raw_write(env, ri, value);
41
raw_write(env, ri, value);
40
- hw_watchpoint_update(cpu, i);
42
41
+ if (tcg_enabled()) {
43
if ((oldval ^ value) & R_CNTHCTL_CNTVMASK_MASK) {
42
+ hw_watchpoint_update(cpu, i);
43
+ }
44
}
45
46
static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
48
int i = ri->crm;
49
50
raw_write(env, ri, value);
51
- hw_watchpoint_update(cpu, i);
52
+ if (tcg_enabled()) {
53
+ hw_watchpoint_update(cpu, i);
54
+ }
55
}
56
57
void hw_breakpoint_update(ARMCPU *cpu, int n)
58
@@ -XXX,XX +XXX,XX @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
59
int i = ri->crm;
60
61
raw_write(env, ri, value);
62
- hw_breakpoint_update(cpu, i);
63
+ if (tcg_enabled()) {
64
+ hw_breakpoint_update(cpu, i);
65
+ }
66
}
67
68
static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
69
@@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
70
value = deposit64(value, 8, 1, extract64(value, 7, 1));
71
72
raw_write(env, ri, value);
73
- hw_breakpoint_update(cpu, i);
74
+ if (tcg_enabled()) {
75
+ hw_breakpoint_update(cpu, i);
76
+ }
77
}
78
79
void define_debug_regs(ARMCPU *cpu)
80
diff --git a/target/arm/machine.c b/target/arm/machine.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/machine.c
83
+++ b/target/arm/machine.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "cpu.h"
86
#include "qemu/error-report.h"
87
#include "sysemu/kvm.h"
88
+#include "sysemu/tcg.h"
89
#include "kvm_arm.h"
90
#include "internals.h"
91
#include "migration/cpu.h"
92
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
93
return -1;
94
}
95
96
- hw_breakpoint_update_all(cpu);
97
- hw_watchpoint_update_all(cpu);
98
+ if (tcg_enabled()) {
99
+ hw_breakpoint_update_all(cpu);
100
+ hw_watchpoint_update_all(cpu);
101
+ }
102
103
/*
104
* TCG gen_update_fp_context() relies on the invariant that
105
--
44
--
106
2.34.1
45
2.34.1
diff view generated by jsdifflib
[PULL 18/25] hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create()
[PULL 05/14] target/arm: Implement new FEAT_ECV trap bits
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
The functionality defined by ID_AA64MMFR0_EL1.ECV == 1 is:
2
* four new trap bits for various counter and timer registers
3
* the CNTHCTL_EL2.EVNTIS and CNTKCTL_EL1.EVNTIS bits which control
4
scaling of the event stream. This is a no-op for us, because we don't
5
implement the event stream (our WFE is a NOP): all we need to do is
6
allow CNTHCTL_EL2.ENVTIS to be read and written.
7
* extensions to PMSCR_EL1.PCT, PMSCR_EL2.PCT, TRFCR_EL1.TS and
8
TRFCR_EL2.TS: these are all no-ops for us, because we don't implement
9
FEAT_SPE or FEAT_TRF.
10
* new registers CNTPCTSS_EL0 and NCTVCTSS_EL0 which are
11
"self-sychronizing" views of the CNTPCT_EL0 and CNTVCT_EL0, meaning
12
that no barriers are needed around their accesses. For us these
13
are just the same as the normal views, because all our sysregs are
14
inherently self-sychronizing.
2
15
3
cmsdk_apb_uart_create() is only used twice in the same
16
In this commit we implement the trap handling and permit the new
4
file. Open-code it.
17
CNTHCTL_EL2 bits to be written.
5
18
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230220115114.25237-7-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20240301183219.2424889-6-peter.maydell@linaro.org
10
---
22
---
11
include/hw/char/cmsdk-apb-uart.h | 34 --------------------------
23
target/arm/cpu-features.h | 5 ++++
12
hw/arm/mps2.c | 41 +++++++++++++++++++++-----------
24
target/arm/helper.c | 51 +++++++++++++++++++++++++++++++++++----
13
2 files changed, 27 insertions(+), 48 deletions(-)
25
2 files changed, 51 insertions(+), 5 deletions(-)
14
26
15
diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-uart.h
27
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
16
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/cmsdk-apb-uart.h
29
--- a/target/arm/cpu-features.h
18
+++ b/include/hw/char/cmsdk-apb-uart.h
30
+++ b/target/arm/cpu-features.h
19
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
20
#ifndef CMSDK_APB_UART_H
32
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
21
#define CMSDK_APB_UART_H
33
}
22
34
23
-#include "hw/qdev-properties.h"
35
+static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
24
#include "hw/sysbus.h"
36
+{
25
#include "chardev/char-fe.h"
37
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
26
-#include "qapi/error.h"
38
+}
27
#include "qom/object.h"
39
+
28
40
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
29
#define TYPE_CMSDK_APB_UART "cmsdk-apb-uart"
41
{
30
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBUART {
42
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
31
uint8_t rxbuf;
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
};
33
34
-/**
35
- * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART
36
- * @addr: location in system memory to map registers
37
- * @chr: Chardev backend to connect UART to, or NULL if no backend
38
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
39
- */
40
-static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr,
41
- qemu_irq txint,
42
- qemu_irq rxint,
43
- qemu_irq txovrint,
44
- qemu_irq rxovrint,
45
- qemu_irq uartint,
46
- Chardev *chr,
47
- uint32_t pclk_frq)
48
-{
49
- DeviceState *dev;
50
- SysBusDevice *s;
51
-
52
- dev = qdev_new(TYPE_CMSDK_APB_UART);
53
- s = SYS_BUS_DEVICE(dev);
54
- qdev_prop_set_chr(dev, "chardev", chr);
55
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
56
- sysbus_realize_and_unref(s, &error_fatal);
57
- sysbus_mmio_map(s, 0, addr);
58
- sysbus_connect_irq(s, 0, txint);
59
- sysbus_connect_irq(s, 1, rxint);
60
- sysbus_connect_irq(s, 2, txovrint);
61
- sysbus_connect_irq(s, 3, rxovrint);
62
- sysbus_connect_irq(s, 4, uartint);
63
- return dev;
64
-}
65
-
66
#endif
67
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
68
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/arm/mps2.c
45
--- a/target/arm/helper.c
70
+++ b/hw/arm/mps2.c
46
+++ b/target/arm/helper.c
71
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
72
#include "hw/boards.h"
48
: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
73
#include "exec/address-spaces.h"
49
return CP_ACCESS_TRAP_EL2;
74
#include "sysemu/sysemu.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/misc/unimp.h"
77
#include "hw/char/cmsdk-apb-uart.h"
78
#include "hw/timer/cmsdk-apb-timer.h"
79
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
80
qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12));
81
82
for (i = 0; i < 5; i++) {
83
+ DeviceState *dev;
84
+ SysBusDevice *s;
85
+
86
static const hwaddr uartbase[] = {0x40004000, 0x40005000,
87
0x40006000, 0x40007000,
88
0x40009000};
89
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
90
rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1);
91
}
92
93
- cmsdk_apb_uart_create(uartbase[i],
94
- qdev_get_gpio_in(armv7m, uartirq[i] + 1),
95
- qdev_get_gpio_in(armv7m, uartirq[i]),
96
- txovrint, rxovrint,
97
- NULL,
98
- serial_hd(i), SYSCLK_FRQ);
99
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
100
+ s = SYS_BUS_DEVICE(dev);
101
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
102
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
103
+ sysbus_realize_and_unref(s, &error_fatal);
104
+ sysbus_mmio_map(s, 0, uartbase[i]);
105
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1));
106
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i]));
107
+ sysbus_connect_irq(s, 2, txovrint);
108
+ sysbus_connect_irq(s, 3, rxovrint);
109
}
50
}
51
+ if (has_el2 && timeridx == GTIMER_VIRT) {
52
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVCT)) {
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
55
+ }
110
break;
56
break;
111
}
57
}
112
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
58
return CP_ACCESS_OK;
113
0x4002c000, 0x4002d000,
59
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
114
0x4002e000};
60
}
115
Object *txrx_orgate;
61
}
116
- DeviceState *txrx_orgate_dev;
117
+ DeviceState *txrx_orgate_dev, *dev;
118
+ SysBusDevice *s;
119
120
txrx_orgate = object_new(TYPE_OR_IRQ);
121
object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal);
122
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
123
txrx_orgate_dev = DEVICE(txrx_orgate);
124
qdev_connect_gpio_out(txrx_orgate_dev, 0,
125
qdev_get_gpio_in(armv7m, uart_txrx_irqno[i]));
126
- cmsdk_apb_uart_create(uartbase[i],
127
- qdev_get_gpio_in(txrx_orgate_dev, 0),
128
- qdev_get_gpio_in(txrx_orgate_dev, 1),
129
- qdev_get_gpio_in(orgate_dev, i * 2),
130
- qdev_get_gpio_in(orgate_dev, i * 2 + 1),
131
- NULL,
132
- serial_hd(i), SYSCLK_FRQ);
133
+
134
+ dev = qdev_new(TYPE_CMSDK_APB_UART);
135
+ s = SYS_BUS_DEVICE(dev);
136
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
137
+ qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ);
138
+ sysbus_realize_and_unref(s, &error_fatal);
139
+ sysbus_mmio_map(s, 0, uartbase[i]);
140
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0));
141
+ sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1));
142
+ sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2));
143
+ sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1));
144
}
62
}
63
+ if (has_el2 && timeridx == GTIMER_VIRT) {
64
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1TVT)) {
65
+ return CP_ACCESS_TRAP_EL2;
66
+ }
67
+ }
145
break;
68
break;
146
}
69
}
70
return CP_ACCESS_OK;
71
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
72
if (cpu_isar_feature(aa64_rme, cpu)) {
73
valid_mask |= R_CNTHCTL_CNTVMASK_MASK | R_CNTHCTL_CNTPMASK_MASK;
74
}
75
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
76
+ valid_mask |=
77
+ R_CNTHCTL_EL1TVT_MASK |
78
+ R_CNTHCTL_EL1TVCT_MASK |
79
+ R_CNTHCTL_EL1NVPCT_MASK |
80
+ R_CNTHCTL_EL1NVVCT_MASK |
81
+ R_CNTHCTL_EVNTIS_MASK;
82
+ }
83
84
/* Clear RES0 bits */
85
value &= valid_mask;
86
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
87
{
88
if (arm_current_el(env) == 1) {
89
/* This must be a FEAT_NV access */
90
- /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
91
return CP_ACCESS_OK;
92
}
93
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
94
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
95
return CP_ACCESS_OK;
96
}
97
98
+static CPAccessResult access_el1nvpct(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
100
+{
101
+ if (arm_current_el(env) == 1) {
102
+ /* This must be a FEAT_NV access with NVx == 101 */
103
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVPCT)) {
104
+ return CP_ACCESS_TRAP_EL2;
105
+ }
106
+ }
107
+ return e2h_access(env, ri, isread);
108
+}
109
+
110
+static CPAccessResult access_el1nvvct(CPUARMState *env, const ARMCPRegInfo *ri,
111
+ bool isread)
112
+{
113
+ if (arm_current_el(env) == 1) {
114
+ /* This must be a FEAT_NV access with NVx == 101 */
115
+ if (FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, EL1NVVCT)) {
116
+ return CP_ACCESS_TRAP_EL2;
117
+ }
118
+ }
119
+ return e2h_access(env, ri, isread);
120
+}
121
+
122
/* Test if system register redirection is to occur in the current state. */
123
static bool redirect_for_e2h(CPUARMState *env)
124
{
125
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
126
{ .name = "CNTP_CTL_EL02", .state = ARM_CP_STATE_AA64,
127
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 2, .opc2 = 1,
128
.type = ARM_CP_IO | ARM_CP_ALIAS,
129
- .access = PL2_RW, .accessfn = e2h_access,
130
+ .access = PL2_RW, .accessfn = access_el1nvpct,
131
.nv2_redirect_offset = 0x180 | NV2_REDIR_NO_NV1,
132
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
133
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write },
134
{ .name = "CNTV_CTL_EL02", .state = ARM_CP_STATE_AA64,
135
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 1,
136
.type = ARM_CP_IO | ARM_CP_ALIAS,
137
- .access = PL2_RW, .accessfn = e2h_access,
138
+ .access = PL2_RW, .accessfn = access_el1nvvct,
139
.nv2_redirect_offset = 0x170 | NV2_REDIR_NO_NV1,
140
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
141
.writefn = gt_virt_ctl_write, .raw_writefn = raw_write },
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
143
.type = ARM_CP_IO | ARM_CP_ALIAS,
144
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
145
.nv2_redirect_offset = 0x178 | NV2_REDIR_NO_NV1,
146
- .access = PL2_RW, .accessfn = e2h_access,
147
+ .access = PL2_RW, .accessfn = access_el1nvpct,
148
.writefn = gt_phys_cval_write, .raw_writefn = raw_write },
149
{ .name = "CNTV_CVAL_EL02", .state = ARM_CP_STATE_AA64,
150
.opc0 = 3, .opc1 = 5, .crn = 14, .crm = 3, .opc2 = 2,
151
.type = ARM_CP_IO | ARM_CP_ALIAS,
152
.nv2_redirect_offset = 0x168 | NV2_REDIR_NO_NV1,
153
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
154
- .access = PL2_RW, .accessfn = e2h_access,
155
+ .access = PL2_RW, .accessfn = access_el1nvvct,
156
.writefn = gt_virt_cval_write, .raw_writefn = raw_write },
157
#endif
158
};
147
--
159
--
148
2.34.1
160
2.34.1
149
150
diff view generated by jsdifflib
[PULL 25/25] hw: Replace qemu_or_irq typedef by OrIRQState
[PULL 06/14] target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
For FEAT_ECV, new registers CNTPCTSS_EL0 and CNTVCTSS_EL0 are
2
defined, which are "self-synchronized" views of the physical and
3
virtual counts as seen in the CNTPCT_EL0 and CNTVCT_EL0 registers
4
(meaning that no barriers are needed around accesses to them to
5
ensure that reads of them do not occur speculatively and out-of-order
6
with other instructions).
2
7
3
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState
8
For QEMU, all our system registers are self-synchronized, so we can
4
declaration for free. Besides, the QOM code style is to use
9
simply copy the existing implementation of CNTPCT_EL0 and CNTVCT_EL0
5
the structure name as typedef, and QEMU style is to use Camel
10
to the new register encodings.
6
Case, so rename qemu_or_irq as OrIRQState.
7
11
8
Mechanical change using:
12
This means we now implement all the functionality required for
13
ID_AA64MMFR0_EL1.ECV == 0b0001.
9
14
10
$ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq)
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20240301183219.2424889-7-peter.maydell@linaro.org
18
---
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
20
1 file changed, 43 insertions(+)
11
21
12
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Message-id: 20230113200138.52869-5-philmd@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
include/hw/arm/armsse.h | 6 +++---
19
include/hw/arm/bcm2835_peripherals.h | 2 +-
20
include/hw/arm/exynos4210.h | 4 ++--
21
include/hw/arm/stm32f205_soc.h | 2 +-
22
include/hw/arm/stm32f405_soc.h | 2 +-
23
include/hw/arm/xlnx-versal.h | 6 +++---
24
include/hw/arm/xlnx-zynqmp.h | 2 +-
25
include/hw/or-irq.h | 2 --
26
hw/arm/exynos4210.c | 4 ++--
27
hw/arm/mps2-tz.c | 2 +-
28
hw/core/or-irq.c | 18 +++++++++---------
29
hw/pci-host/raven.c | 2 +-
30
12 files changed, 25 insertions(+), 27 deletions(-)
31
32
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
33
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/armsse.h
24
--- a/target/arm/helper.c
35
+++ b/include/hw/arm/armsse.h
25
+++ b/target/arm/helper.c
36
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
26
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
37
TZPPC apb_ppc[NUM_INTERNAL_PPCS];
38
TZMPC mpc[IOTS_NUM_MPC];
39
CMSDKAPBTimer timer[3];
40
- qemu_or_irq ppc_irq_orgate;
41
+ OrIRQState ppc_irq_orgate;
42
SplitIRQ sec_resp_splitter;
43
SplitIRQ ppc_irq_splitter[NUM_PPCS];
44
SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
45
- qemu_or_irq mpc_irq_orgate;
46
- qemu_or_irq nmi_orgate;
47
+ OrIRQState mpc_irq_orgate;
48
+ OrIRQState nmi_orgate;
49
50
SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS];
51
52
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/include/hw/arm/bcm2835_peripherals.h
55
+++ b/include/hw/arm/bcm2835_peripherals.h
56
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
57
BCM2835AuxState aux;
58
BCM2835FBState fb;
59
BCM2835DMAState dma;
60
- qemu_or_irq orgated_dma_irq;
61
+ OrIRQState orgated_dma_irq;
62
BCM2835ICState ic;
63
BCM2835PropertyState property;
64
BCM2835RngState rng;
65
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/hw/arm/exynos4210.h
68
+++ b/include/hw/arm/exynos4210.h
69
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
70
MemoryRegion boot_secondary;
71
MemoryRegion bootreg_mem;
72
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
73
- qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
74
- qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
75
+ OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA];
76
+ OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS];
77
A9MPPrivState a9mpcore;
78
Exynos4210GicState ext_gic;
79
Exynos4210CombinerState int_combiner;
80
diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h
81
index XXXXXXX..XXXXXXX 100644
82
--- a/include/hw/arm/stm32f205_soc.h
83
+++ b/include/hw/arm/stm32f205_soc.h
84
@@ -XXX,XX +XXX,XX @@ struct STM32F205State {
85
STM32F2XXADCState adc[STM_NUM_ADCS];
86
STM32F2XXSPIState spi[STM_NUM_SPIS];
87
88
- qemu_or_irq *adc_irqs;
89
+ OrIRQState *adc_irqs;
90
91
MemoryRegion sram;
92
MemoryRegion flash;
93
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
94
index XXXXXXX..XXXXXXX 100644
95
--- a/include/hw/arm/stm32f405_soc.h
96
+++ b/include/hw/arm/stm32f405_soc.h
97
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
98
STM32F4xxExtiState exti;
99
STM32F2XXUsartState usart[STM_NUM_USARTS];
100
STM32F2XXTimerState timer[STM_NUM_TIMERS];
101
- qemu_or_irq adc_irqs;
102
+ OrIRQState adc_irqs;
103
STM32F2XXADCState adc[STM_NUM_ADCS];
104
STM32F2XXSPIState spi[STM_NUM_SPIS];
105
106
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
107
index XXXXXXX..XXXXXXX 100644
108
--- a/include/hw/arm/xlnx-versal.h
109
+++ b/include/hw/arm/xlnx-versal.h
110
@@ -XXX,XX +XXX,XX @@ struct Versal {
111
} rpu;
112
113
struct {
114
- qemu_or_irq irq_orgate;
115
+ OrIRQState irq_orgate;
116
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
117
} xram;
118
119
@@ -XXX,XX +XXX,XX @@ struct Versal {
120
XlnxCSUDMA dma_src;
121
XlnxCSUDMA dma_dst;
122
MemoryRegion linear_mr;
123
- qemu_or_irq irq_orgate;
124
+ OrIRQState irq_orgate;
125
} ospi;
126
} iou;
127
128
@@ -XXX,XX +XXX,XX @@ struct Versal {
129
XlnxVersalEFuseCtrl efuse_ctrl;
130
XlnxVersalEFuseCache efuse_cache;
131
132
- qemu_or_irq apb_irq_orgate;
133
+ OrIRQState apb_irq_orgate;
134
} pmc;
135
136
struct {
137
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/xlnx-zynqmp.h
140
+++ b/include/hw/arm/xlnx-zynqmp.h
141
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
142
XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
143
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
144
XlnxCSUDMA qspi_dma;
145
- qemu_or_irq qspi_irq_orgate;
146
+ OrIRQState qspi_irq_orgate;
147
XlnxZynqMPAPUCtrl apu_ctrl;
148
XlnxZynqMPCRF crf;
149
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
150
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/or-irq.h
153
+++ b/include/hw/or-irq.h
154
@@ -XXX,XX +XXX,XX @@
155
*/
156
#define MAX_OR_LINES 48
157
158
-typedef struct OrIRQState qemu_or_irq;
159
-
160
OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
161
162
struct OrIRQState {
163
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/arm/exynos4210.c
166
+++ b/hw/arm/exynos4210.c
167
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
168
return (0x9 << ARM_AFF1_SHIFT) | cpu;
169
}
170
171
-static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate,
172
+static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate,
173
qemu_irq irq, int nreq, int nevents, int width)
174
{
175
SysBusDevice *busdev;
176
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
177
178
for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) {
179
char *name = g_strdup_printf("pl330-irq-orgate%d", i);
180
- qemu_or_irq *orgate = &s->pl330_irq_orgate[i];
181
+ OrIRQState *orgate = &s->pl330_irq_orgate[i];
182
183
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
184
g_free(name);
185
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/mps2-tz.c
188
+++ b/hw/arm/mps2-tz.c
189
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
190
TZMSC msc[4];
191
CMSDKAPBUART uart[6];
192
SplitIRQ sec_resp_splitter;
193
- qemu_or_irq uart_irq_orgate;
194
+ OrIRQState uart_irq_orgate;
195
DeviceState *lan9118;
196
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX];
197
Clock *sysclk;
198
diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c
199
index XXXXXXX..XXXXXXX 100644
200
--- a/hw/core/or-irq.c
201
+++ b/hw/core/or-irq.c
202
@@ -XXX,XX +XXX,XX @@
203
204
static void or_irq_handler(void *opaque, int n, int level)
205
{
206
- qemu_or_irq *s = OR_IRQ(opaque);
207
+ OrIRQState *s = OR_IRQ(opaque);
208
int or_level = 0;
209
int i;
210
211
@@ -XXX,XX +XXX,XX @@ static void or_irq_handler(void *opaque, int n, int level)
212
213
static void or_irq_reset(DeviceState *dev)
214
{
215
- qemu_or_irq *s = OR_IRQ(dev);
216
+ OrIRQState *s = OR_IRQ(dev);
217
int i;
218
219
for (i = 0; i < MAX_OR_LINES; i++) {
220
@@ -XXX,XX +XXX,XX @@ static void or_irq_reset(DeviceState *dev)
221
222
static void or_irq_realize(DeviceState *dev, Error **errp)
223
{
224
- qemu_or_irq *s = OR_IRQ(dev);
225
+ OrIRQState *s = OR_IRQ(dev);
226
227
assert(s->num_lines <= MAX_OR_LINES);
228
229
@@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp)
230
231
static void or_irq_init(Object *obj)
232
{
233
- qemu_or_irq *s = OR_IRQ(obj);
234
+ OrIRQState *s = OR_IRQ(obj);
235
236
qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
237
}
238
@@ -XXX,XX +XXX,XX @@ static void or_irq_init(Object *obj)
239
240
static bool vmstate_extras_needed(void *opaque)
241
{
242
- qemu_or_irq *s = OR_IRQ(opaque);
243
+ OrIRQState *s = OR_IRQ(opaque);
244
245
return s->num_lines >= OLD_MAX_OR_LINES;
246
}
247
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq_extras = {
248
.minimum_version_id = 1,
249
.needed = vmstate_extras_needed,
250
.fields = (VMStateField[]) {
251
- VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0,
252
+ VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0,
253
vmstate_info_bool, bool),
254
VMSTATE_END_OF_LIST(),
255
},
27
},
256
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
28
};
257
.version_id = 1,
29
258
.minimum_version_id = 1,
30
+/*
259
.fields = (VMStateField[]) {
31
+ * FEAT_ECV adds extra views of CNTVCT_EL0 and CNTPCT_EL0 which
260
- VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES),
32
+ * are "self-synchronizing". For QEMU all sysregs are self-synchronizing,
261
+ VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES),
33
+ * so our implementations here are identical to the normal registers.
262
VMSTATE_END_OF_LIST(),
34
+ */
35
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
36
+ { .name = "CNTVCTSS", .cp = 15, .crm = 14, .opc1 = 9,
37
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
38
+ .accessfn = gt_vct_access,
39
+ .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
40
+ },
41
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
42
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
43
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
44
+ .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
45
+ },
46
+ { .name = "CNTPCTSS", .cp = 15, .crm = 14, .opc1 = 8,
47
+ .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
48
+ .accessfn = gt_pct_access,
49
+ .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
50
+ },
51
+ { .name = "CNTPCTSS_EL0", .state = ARM_CP_STATE_AA64,
52
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 5,
53
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
54
+ .accessfn = gt_pct_access, .readfn = gt_cnt_read,
55
+ },
56
+};
57
+
58
#else
59
60
/*
61
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
263
},
62
},
264
.subsections = (const VMStateDescription*[]) {
265
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = {
266
};
63
};
267
64
268
static Property or_irq_properties[] = {
65
+/*
269
- DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1),
66
+ * CNTVCTSS_EL0 has the same trap conditions as CNTVCT_EL0, so it also
270
+ DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1),
67
+ * is exposed to userspace by Linux.
271
DEFINE_PROP_END_OF_LIST(),
68
+ */
272
};
69
+static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
273
70
+ { .name = "CNTVCTSS_EL0", .state = ARM_CP_STATE_AA64,
274
@@ -XXX,XX +XXX,XX @@ static void or_irq_class_init(ObjectClass *klass, void *data)
71
+ .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 6,
275
static const TypeInfo or_irq_type_info = {
72
+ .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
276
.name = TYPE_OR_IRQ,
73
+ .readfn = gt_virt_cnt_read,
277
.parent = TYPE_DEVICE,
74
+ },
278
- .instance_size = sizeof(qemu_or_irq),
75
+};
279
+ .instance_size = sizeof(OrIRQState),
76
+
280
.instance_init = or_irq_init,
77
#endif
281
.class_init = or_irq_class_init,
78
282
};
79
static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
283
diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
80
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
284
index XXXXXXX..XXXXXXX 100644
81
if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
285
--- a/hw/pci-host/raven.c
82
define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
286
+++ b/hw/pci-host/raven.c
83
}
287
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
84
+ if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
288
struct PRePPCIState {
85
+ define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
289
PCIHostState parent_obj;
86
+ }
290
87
if (arm_feature(env, ARM_FEATURE_VAPA)) {
291
- qemu_or_irq *or_irq;
88
ARMCPRegInfo vapa_cp_reginfo[] = {
292
+ OrIRQState *or_irq;
89
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
293
qemu_irq pci_irqs[PCI_NUM_PINS];
294
PCIBus pci_bus;
295
AddressSpace pci_io_as;
296
--
90
--
297
2.34.1
91
2.34.1
298
299
diff view generated by jsdifflib
[PULL 03/25] target/arm: Wrap TCG-only code in debug_helper.c
[PULL 07/14] target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
1
From: Fabiano Rosas <farosas@suse.de>
1
When ID_AA64MMFR0_EL1.ECV is 0b0010, a new register CNTPOFF_EL2 is
2
implemented. This is similar to the existing CNTVOFF_EL2, except
3
that it controls a hypervisor-adjustable offset made to the physical
4
counter and timer.
2
5
3
The next few patches will move helpers under CONFIG_TCG. We'd prefer
6
Implement the handling for this register, which includes control/trap
4
to keep the debug helpers and debug registers close together, so
7
bits in SCR_EL3 and CNTHCTL_EL2.
5
rearrange the file a bit to be able to wrap the helpers with a TCG
6
ifdef.
7
8
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240301183219.2424889-8-peter.maydell@linaro.org
11
---
12
---
12
target/arm/debug_helper.c | 476 +++++++++++++++++++-------------------
13
target/arm/cpu-features.h | 5 +++
13
1 file changed, 239 insertions(+), 237 deletions(-)
14
target/arm/cpu.h | 1 +
15
target/arm/helper.c | 68 +++++++++++++++++++++++++++++++++++++--
16
target/arm/trace-events | 1 +
17
4 files changed, 73 insertions(+), 2 deletions(-)
14
18
15
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
19
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/debug_helper.c
21
--- a/target/arm/cpu-features.h
18
+++ b/target/arm/debug_helper.c
22
+++ b/target/arm/cpu-features.h
19
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
20
#include "cpregs.h"
24
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
21
#include "exec/exec-all.h"
22
#include "exec/helper-proto.h"
23
+#include "sysemu/tcg.h"
24
25
-
26
+#ifdef CONFIG_TCG
27
/* Return the Exception Level targeted by debug exceptions. */
28
static int arm_debug_target_el(CPUARMState *env)
29
{
30
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
31
raise_exception_debug(env, EXCP_UDEF, syndrome);
32
}
25
}
33
26
34
+void hw_watchpoint_update(ARMCPU *cpu, int n)
27
+static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
35
+{
28
+{
36
+ CPUARMState *env = &cpu->env;
29
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
37
+ vaddr len = 0;
38
+ vaddr wvr = env->cp15.dbgwvr[n];
39
+ uint64_t wcr = env->cp15.dbgwcr[n];
40
+ int mask;
41
+ int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
42
+
43
+ if (env->cpu_watchpoint[n]) {
44
+ cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
45
+ env->cpu_watchpoint[n] = NULL;
46
+ }
47
+
48
+ if (!FIELD_EX64(wcr, DBGWCR, E)) {
49
+ /* E bit clear : watchpoint disabled */
50
+ return;
51
+ }
52
+
53
+ switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
54
+ case 0:
55
+ /* LSC 00 is reserved and must behave as if the wp is disabled */
56
+ return;
57
+ case 1:
58
+ flags |= BP_MEM_READ;
59
+ break;
60
+ case 2:
61
+ flags |= BP_MEM_WRITE;
62
+ break;
63
+ case 3:
64
+ flags |= BP_MEM_ACCESS;
65
+ break;
66
+ }
67
+
68
+ /*
69
+ * Attempts to use both MASK and BAS fields simultaneously are
70
+ * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
71
+ * thus generating a watchpoint for every byte in the masked region.
72
+ */
73
+ mask = FIELD_EX64(wcr, DBGWCR, MASK);
74
+ if (mask == 1 || mask == 2) {
75
+ /*
76
+ * Reserved values of MASK; we must act as if the mask value was
77
+ * some non-reserved value, or as if the watchpoint were disabled.
78
+ * We choose the latter.
79
+ */
80
+ return;
81
+ } else if (mask) {
82
+ /* Watchpoint covers an aligned area up to 2GB in size */
83
+ len = 1ULL << mask;
84
+ /*
85
+ * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
86
+ * whether the watchpoint fires when the unmasked bits match; we opt
87
+ * to generate the exceptions.
88
+ */
89
+ wvr &= ~(len - 1);
90
+ } else {
91
+ /* Watchpoint covers bytes defined by the byte address select bits */
92
+ int bas = FIELD_EX64(wcr, DBGWCR, BAS);
93
+ int basstart;
94
+
95
+ if (extract64(wvr, 2, 1)) {
96
+ /*
97
+ * Deprecated case of an only 4-aligned address. BAS[7:4] are
98
+ * ignored, and BAS[3:0] define which bytes to watch.
99
+ */
100
+ bas &= 0xf;
101
+ }
102
+
103
+ if (bas == 0) {
104
+ /* This must act as if the watchpoint is disabled */
105
+ return;
106
+ }
107
+
108
+ /*
109
+ * The BAS bits are supposed to be programmed to indicate a contiguous
110
+ * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
111
+ * we fire for each byte in the word/doubleword addressed by the WVR.
112
+ * We choose to ignore any non-zero bits after the first range of 1s.
113
+ */
114
+ basstart = ctz32(bas);
115
+ len = cto32(bas >> basstart);
116
+ wvr += basstart;
117
+ }
118
+
119
+ cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
120
+ &env->cpu_watchpoint[n]);
121
+}
30
+}
122
+
31
+
123
+void hw_watchpoint_update_all(ARMCPU *cpu)
32
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
33
{
34
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
35
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu.h
38
+++ b/target/arm/cpu.h
39
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
40
uint64_t c14_cntkctl; /* Timer Control register */
41
uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
42
uint64_t cntvoff_el2; /* Counter Virtual Offset register */
43
+ uint64_t cntpoff_el2; /* Counter Physical Offset register */
44
ARMGenericTimer c14_timer[NUM_GTIMERS];
45
uint32_t c15_cpar; /* XScale Coprocessor Access Register */
46
uint32_t c15_ticonfig; /* TI925T configuration byte. */
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
52
if (cpu_isar_feature(aa64_rme, cpu)) {
53
valid_mask |= SCR_NSE | SCR_GPF;
54
}
55
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
56
+ valid_mask |= SCR_ECVEN;
57
+ }
58
} else {
59
valid_mask &= ~(SCR_RW | SCR_ST);
60
if (cpu_isar_feature(aa32_ras, cpu)) {
61
@@ -XXX,XX +XXX,XX @@ void gt_rme_post_el_change(ARMCPU *cpu, void *ignored)
62
gt_update_irq(cpu, GTIMER_PHYS);
63
}
64
65
+static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
124
+{
66
+{
125
+ int i;
67
+ if ((env->cp15.scr_el3 & SCR_ECVEN) &&
126
+ CPUARMState *env = &cpu->env;
68
+ FIELD_EX64(env->cp15.cnthctl_el2, CNTHCTL, ECV) &&
127
+
69
+ arm_is_el2_enabled(env) &&
128
+ /*
70
+ (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
129
+ * Completely clear out existing QEMU watchpoints and our array, to
71
+ return env->cp15.cntpoff_el2;
130
+ * avoid possible stale entries following migration load.
131
+ */
132
+ cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
133
+ memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
134
+
135
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
136
+ hw_watchpoint_update(cpu, i);
137
+ }
72
+ }
73
+ return 0;
138
+}
74
+}
139
+
75
+
140
+void hw_breakpoint_update(ARMCPU *cpu, int n)
76
+static uint64_t gt_phys_cnt_offset(CPUARMState *env)
141
+{
77
+{
142
+ CPUARMState *env = &cpu->env;
78
+ if (arm_current_el(env) >= 2) {
143
+ uint64_t bvr = env->cp15.dbgbvr[n];
79
+ return 0;
144
+ uint64_t bcr = env->cp15.dbgbcr[n];
145
+ vaddr addr;
146
+ int bt;
147
+ int flags = BP_CPU;
148
+
149
+ if (env->cpu_breakpoint[n]) {
150
+ cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
151
+ env->cpu_breakpoint[n] = NULL;
152
+ }
80
+ }
153
+
81
+ return gt_phys_raw_cnt_offset(env);
154
+ if (!extract64(bcr, 0, 1)) {
155
+ /* E bit clear : watchpoint disabled */
156
+ return;
157
+ }
158
+
159
+ bt = extract64(bcr, 20, 4);
160
+
161
+ switch (bt) {
162
+ case 4: /* unlinked address mismatch (reserved if AArch64) */
163
+ case 5: /* linked address mismatch (reserved if AArch64) */
164
+ qemu_log_mask(LOG_UNIMP,
165
+ "arm: address mismatch breakpoint types not implemented\n");
166
+ return;
167
+ case 0: /* unlinked address match */
168
+ case 1: /* linked address match */
169
+ {
170
+ /*
171
+ * Bits [1:0] are RES0.
172
+ *
173
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
174
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
175
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
176
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
177
+ * whether the RESS bits are ignored when comparing an address.
178
+ * Therefore we are allowed to compare the entire register, which
179
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
180
+ *
181
+ * The BAS field is used to allow setting breakpoints on 16-bit
182
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
183
+ * a bp will fire if the addresses covered by the bp and the addresses
184
+ * covered by the insn overlap but the insn doesn't start at the
185
+ * start of the bp address range. We choose to require the insn and
186
+ * the bp to have the same address. The constraints on writing to
187
+ * BAS enforced in dbgbcr_write mean we have only four cases:
188
+ * 0b0000 => no breakpoint
189
+ * 0b0011 => breakpoint on addr
190
+ * 0b1100 => breakpoint on addr + 2
191
+ * 0b1111 => breakpoint on addr
192
+ * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
193
+ */
194
+ int bas = extract64(bcr, 5, 4);
195
+ addr = bvr & ~3ULL;
196
+ if (bas == 0) {
197
+ return;
198
+ }
199
+ if (bas == 0xc) {
200
+ addr += 2;
201
+ }
202
+ break;
203
+ }
204
+ case 2: /* unlinked context ID match */
205
+ case 8: /* unlinked VMID match (reserved if no EL2) */
206
+ case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
207
+ qemu_log_mask(LOG_UNIMP,
208
+ "arm: unlinked context breakpoint types not implemented\n");
209
+ return;
210
+ case 9: /* linked VMID match (reserved if no EL2) */
211
+ case 11: /* linked context ID and VMID match (reserved if no EL2) */
212
+ case 3: /* linked context ID match */
213
+ default:
214
+ /*
215
+ * We must generate no events for Linked context matches (unless
216
+ * they are linked to by some other bp/wp, which is handled in
217
+ * updates for the linking bp/wp). We choose to also generate no events
218
+ * for reserved values.
219
+ */
220
+ return;
221
+ }
222
+
223
+ cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
224
+}
82
+}
225
+
83
+
226
+void hw_breakpoint_update_all(ARMCPU *cpu)
84
static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
85
{
86
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
87
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
88
* reset timer to when ISTATUS next has to change
89
*/
90
uint64_t offset = timeridx == GTIMER_VIRT ?
91
- cpu->env.cp15.cntvoff_el2 : 0;
92
+ cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
93
uint64_t count = gt_get_countervalue(&cpu->env);
94
/* Note that this must be unsigned 64 bit arithmetic: */
95
int istatus = count - offset >= gt->cval;
96
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
97
98
static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
99
{
100
- return gt_get_countervalue(env);
101
+ return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
102
}
103
104
static uint64_t gt_virt_cnt_offset(CPUARMState *env)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
106
case GTIMER_HYPVIRT:
107
offset = gt_virt_cnt_offset(env);
108
break;
109
+ case GTIMER_PHYS:
110
+ offset = gt_phys_cnt_offset(env);
111
+ break;
112
}
113
114
return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
115
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
case GTIMER_HYPVIRT:
117
offset = gt_virt_cnt_offset(env);
118
break;
119
+ case GTIMER_PHYS:
120
+ offset = gt_phys_cnt_offset(env);
121
+ break;
122
}
123
124
trace_arm_gt_tval_write(timeridx, value);
125
@@ -XXX,XX +XXX,XX @@ static void gt_cnthctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
126
R_CNTHCTL_EL1NVVCT_MASK |
127
R_CNTHCTL_EVNTIS_MASK;
128
}
129
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
130
+ valid_mask |= R_CNTHCTL_ECV_MASK;
131
+ }
132
133
/* Clear RES0 bits */
134
value &= valid_mask;
135
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gen_timer_ecv_cp_reginfo[] = {
136
},
137
};
138
139
+static CPAccessResult gt_cntpoff_access(CPUARMState *env,
140
+ const ARMCPRegInfo *ri,
141
+ bool isread)
227
+{
142
+{
228
+ int i;
143
+ if (arm_current_el(env) == 2 && !(env->cp15.scr_el3 & SCR_ECVEN)) {
229
+ CPUARMState *env = &cpu->env;
144
+ return CP_ACCESS_TRAP_EL3;
230
+
231
+ /*
232
+ * Completely clear out existing QEMU breakpoints and our array, to
233
+ * avoid possible stale entries following migration load.
234
+ */
235
+ cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
236
+ memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
237
+
238
+ for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
239
+ hw_breakpoint_update(cpu, i);
240
+ }
145
+ }
146
+ return CP_ACCESS_OK;
241
+}
147
+}
242
+
148
+
243
+#if !defined(CONFIG_USER_ONLY)
149
+static void gt_cntpoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
150
+ uint64_t value)
151
+{
152
+ ARMCPU *cpu = env_archcpu(env);
244
+
153
+
245
+vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
154
+ trace_arm_gt_cntpoff_write(value);
246
+{
155
+ raw_write(env, ri, value);
247
+ ARMCPU *cpu = ARM_CPU(cs);
156
+ gt_recalc_timer(cpu, GTIMER_PHYS);
248
+ CPUARMState *env = &cpu->env;
249
+
250
+ /*
251
+ * In BE32 system mode, target memory is stored byteswapped (on a
252
+ * little-endian host system), and by the time we reach here (via an
253
+ * opcode helper) the addresses of subword accesses have been adjusted
254
+ * to account for that, which means that watchpoints will not match.
255
+ * Undo the adjustment here.
256
+ */
257
+ if (arm_sctlr_b(env)) {
258
+ if (len == 1) {
259
+ addr ^= 3;
260
+ } else if (len == 2) {
261
+ addr ^= 2;
262
+ }
263
+ }
264
+
265
+ return addr;
266
+}
157
+}
267
+
158
+
268
+#endif /* !CONFIG_USER_ONLY */
159
+static const ARMCPRegInfo gen_timer_cntpoff_reginfo = {
269
+#endif /* CONFIG_TCG */
160
+ .name = "CNTPOFF_EL2", .state = ARM_CP_STATE_AA64,
270
+
161
+ .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 6,
162
+ .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
163
+ .accessfn = gt_cntpoff_access, .writefn = gt_cntpoff_write,
164
+ .nv2_redirect_offset = 0x1a8,
165
+ .fieldoffset = offsetof(CPUARMState, cp15.cntpoff_el2),
166
+};
167
#else
168
271
/*
169
/*
272
* Check for traps to "powerdown debug" registers, which are controlled
170
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
273
* by MDCR.TDOSA
171
if (cpu_isar_feature(aa64_ecv_traps, cpu)) {
274
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
172
define_arm_cp_regs(cpu, gen_timer_ecv_cp_reginfo);
275
.access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
276
};
277
278
-void hw_watchpoint_update(ARMCPU *cpu, int n)
279
-{
280
- CPUARMState *env = &cpu->env;
281
- vaddr len = 0;
282
- vaddr wvr = env->cp15.dbgwvr[n];
283
- uint64_t wcr = env->cp15.dbgwcr[n];
284
- int mask;
285
- int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
286
-
287
- if (env->cpu_watchpoint[n]) {
288
- cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
289
- env->cpu_watchpoint[n] = NULL;
290
- }
291
-
292
- if (!FIELD_EX64(wcr, DBGWCR, E)) {
293
- /* E bit clear : watchpoint disabled */
294
- return;
295
- }
296
-
297
- switch (FIELD_EX64(wcr, DBGWCR, LSC)) {
298
- case 0:
299
- /* LSC 00 is reserved and must behave as if the wp is disabled */
300
- return;
301
- case 1:
302
- flags |= BP_MEM_READ;
303
- break;
304
- case 2:
305
- flags |= BP_MEM_WRITE;
306
- break;
307
- case 3:
308
- flags |= BP_MEM_ACCESS;
309
- break;
310
- }
311
-
312
- /*
313
- * Attempts to use both MASK and BAS fields simultaneously are
314
- * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
315
- * thus generating a watchpoint for every byte in the masked region.
316
- */
317
- mask = FIELD_EX64(wcr, DBGWCR, MASK);
318
- if (mask == 1 || mask == 2) {
319
- /*
320
- * Reserved values of MASK; we must act as if the mask value was
321
- * some non-reserved value, or as if the watchpoint were disabled.
322
- * We choose the latter.
323
- */
324
- return;
325
- } else if (mask) {
326
- /* Watchpoint covers an aligned area up to 2GB in size */
327
- len = 1ULL << mask;
328
- /*
329
- * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
330
- * whether the watchpoint fires when the unmasked bits match; we opt
331
- * to generate the exceptions.
332
- */
333
- wvr &= ~(len - 1);
334
- } else {
335
- /* Watchpoint covers bytes defined by the byte address select bits */
336
- int bas = FIELD_EX64(wcr, DBGWCR, BAS);
337
- int basstart;
338
-
339
- if (extract64(wvr, 2, 1)) {
340
- /*
341
- * Deprecated case of an only 4-aligned address. BAS[7:4] are
342
- * ignored, and BAS[3:0] define which bytes to watch.
343
- */
344
- bas &= 0xf;
345
- }
346
-
347
- if (bas == 0) {
348
- /* This must act as if the watchpoint is disabled */
349
- return;
350
- }
351
-
352
- /*
353
- * The BAS bits are supposed to be programmed to indicate a contiguous
354
- * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
355
- * we fire for each byte in the word/doubleword addressed by the WVR.
356
- * We choose to ignore any non-zero bits after the first range of 1s.
357
- */
358
- basstart = ctz32(bas);
359
- len = cto32(bas >> basstart);
360
- wvr += basstart;
361
- }
362
-
363
- cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
364
- &env->cpu_watchpoint[n]);
365
-}
366
-
367
-void hw_watchpoint_update_all(ARMCPU *cpu)
368
-{
369
- int i;
370
- CPUARMState *env = &cpu->env;
371
-
372
- /*
373
- * Completely clear out existing QEMU watchpoints and our array, to
374
- * avoid possible stale entries following migration load.
375
- */
376
- cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
377
- memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
378
-
379
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
380
- hw_watchpoint_update(cpu, i);
381
- }
382
-}
383
-
384
static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
385
uint64_t value)
386
{
387
@@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
388
}
173
}
389
}
174
+#ifndef CONFIG_USER_ONLY
390
175
+ if (cpu_isar_feature(aa64_ecv, cpu)) {
391
-void hw_breakpoint_update(ARMCPU *cpu, int n)
176
+ define_one_arm_cp_reg(cpu, &gen_timer_cntpoff_reginfo);
392
-{
177
+ }
393
- CPUARMState *env = &cpu->env;
178
+#endif
394
- uint64_t bvr = env->cp15.dbgbvr[n];
179
if (arm_feature(env, ARM_FEATURE_VAPA)) {
395
- uint64_t bcr = env->cp15.dbgbcr[n];
180
ARMCPRegInfo vapa_cp_reginfo[] = {
396
- vaddr addr;
181
{ .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
397
- int bt;
182
diff --git a/target/arm/trace-events b/target/arm/trace-events
398
- int flags = BP_CPU;
183
index XXXXXXX..XXXXXXX 100644
399
-
184
--- a/target/arm/trace-events
400
- if (env->cpu_breakpoint[n]) {
185
+++ b/target/arm/trace-events
401
- cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
186
@@ -XXX,XX +XXX,XX @@ arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%"
402
- env->cpu_breakpoint[n] = NULL;
187
arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
403
- }
188
arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
404
-
189
arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64
405
- if (!extract64(bcr, 0, 1)) {
190
+arm_gt_cntpoff_write(uint64_t value) "gt_cntpoff_write: value 0x%" PRIx64
406
- /* E bit clear : watchpoint disabled */
191
arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
407
- return;
192
408
- }
193
# kvm.c
409
-
410
- bt = extract64(bcr, 20, 4);
411
-
412
- switch (bt) {
413
- case 4: /* unlinked address mismatch (reserved if AArch64) */
414
- case 5: /* linked address mismatch (reserved if AArch64) */
415
- qemu_log_mask(LOG_UNIMP,
416
- "arm: address mismatch breakpoint types not implemented\n");
417
- return;
418
- case 0: /* unlinked address match */
419
- case 1: /* linked address match */
420
- {
421
- /*
422
- * Bits [1:0] are RES0.
423
- *
424
- * It is IMPLEMENTATION DEFINED whether bits [63:49]
425
- * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
426
- * of the VA field ([48] or [52] for FEAT_LVA), or whether the
427
- * value is read as written. It is CONSTRAINED UNPREDICTABLE
428
- * whether the RESS bits are ignored when comparing an address.
429
- * Therefore we are allowed to compare the entire register, which
430
- * lets us avoid considering whether FEAT_LVA is actually enabled.
431
- *
432
- * The BAS field is used to allow setting breakpoints on 16-bit
433
- * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
434
- * a bp will fire if the addresses covered by the bp and the addresses
435
- * covered by the insn overlap but the insn doesn't start at the
436
- * start of the bp address range. We choose to require the insn and
437
- * the bp to have the same address. The constraints on writing to
438
- * BAS enforced in dbgbcr_write mean we have only four cases:
439
- * 0b0000 => no breakpoint
440
- * 0b0011 => breakpoint on addr
441
- * 0b1100 => breakpoint on addr + 2
442
- * 0b1111 => breakpoint on addr
443
- * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
444
- */
445
- int bas = extract64(bcr, 5, 4);
446
- addr = bvr & ~3ULL;
447
- if (bas == 0) {
448
- return;
449
- }
450
- if (bas == 0xc) {
451
- addr += 2;
452
- }
453
- break;
454
- }
455
- case 2: /* unlinked context ID match */
456
- case 8: /* unlinked VMID match (reserved if no EL2) */
457
- case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
458
- qemu_log_mask(LOG_UNIMP,
459
- "arm: unlinked context breakpoint types not implemented\n");
460
- return;
461
- case 9: /* linked VMID match (reserved if no EL2) */
462
- case 11: /* linked context ID and VMID match (reserved if no EL2) */
463
- case 3: /* linked context ID match */
464
- default:
465
- /*
466
- * We must generate no events for Linked context matches (unless
467
- * they are linked to by some other bp/wp, which is handled in
468
- * updates for the linking bp/wp). We choose to also generate no events
469
- * for reserved values.
470
- */
471
- return;
472
- }
473
-
474
- cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
475
-}
476
-
477
-void hw_breakpoint_update_all(ARMCPU *cpu)
478
-{
479
- int i;
480
- CPUARMState *env = &cpu->env;
481
-
482
- /*
483
- * Completely clear out existing QEMU breakpoints and our array, to
484
- * avoid possible stale entries following migration load.
485
- */
486
- cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
487
- memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
488
-
489
- for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
490
- hw_breakpoint_update(cpu, i);
491
- }
492
-}
493
-
494
static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
495
uint64_t value)
496
{
497
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
498
g_free(dbgwcr_el1_name);
499
}
500
}
501
-
502
-#if !defined(CONFIG_USER_ONLY)
503
-
504
-vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
505
-{
506
- ARMCPU *cpu = ARM_CPU(cs);
507
- CPUARMState *env = &cpu->env;
508
-
509
- /*
510
- * In BE32 system mode, target memory is stored byteswapped (on a
511
- * little-endian host system), and by the time we reach here (via an
512
- * opcode helper) the addresses of subword accesses have been adjusted
513
- * to account for that, which means that watchpoints will not match.
514
- * Undo the adjustment here.
515
- */
516
- if (arm_sctlr_b(env)) {
517
- if (len == 1) {
518
- addr ^= 3;
519
- } else if (len == 2) {
520
- addr ^= 2;
521
- }
522
- }
523
-
524
- return addr;
525
-}
526
-
527
-#endif
528
--
194
--
529
2.34.1
195
2.34.1
diff view generated by jsdifflib
[PULL 24/25] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
[PULL 08/14] target/arm: Enable FEAT_ECV for 'max' CPU
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
Enable all FEAT_ECV features on the 'max' CPU.
2
2
3
Missed during automatic conversion from commit 8063396bf3
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20240301183219.2424889-9-peter.maydell@linaro.org
7
---
8
docs/system/arm/emulation.rst | 1 +
9
target/arm/tcg/cpu64.c | 1 +
10
2 files changed, 2 insertions(+)
5
11
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
7
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20230113200138.52869-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/or-irq.h | 3 +--
13
1 file changed, 1 insertion(+), 2 deletions(-)
14
15
diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/or-irq.h
14
--- a/docs/system/arm/emulation.rst
18
+++ b/include/hw/or-irq.h
15
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
17
- FEAT_DotProd (Advanced SIMD dot product instructions)
21
typedef struct OrIRQState qemu_or_irq;
18
- FEAT_DoubleFault (Double Fault Extension)
22
19
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
23
-DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ,
20
+- FEAT_ECV (Enhanced Counter Virtualization)
24
- TYPE_OR_IRQ)
21
- FEAT_EPAC (Enhanced pointer authentication)
25
+OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ)
22
- FEAT_ETS (Enhanced Translation Synchronization)
26
23
- FEAT_EVT (Enhanced Virtualization Traps)
27
struct OrIRQState {
24
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
28
DeviceState parent_obj;
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/tcg/cpu64.c
27
+++ b/target/arm/tcg/cpu64.c
28
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
29
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
30
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
31
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
32
+ t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
33
cpu->isar.id_aa64mmfr0 = t;
34
35
t = cpu->isar.id_aa64mmfr1;
29
--
36
--
30
2.34.1
37
2.34.1
31
38
32
39
diff view generated by jsdifflib
[PULL 04/25] target/arm: move translate modules to tcg/
[PULL 09/14] hw/gpio: Implement STM32L4x5 GPIO
1
From: Fabiano Rosas <farosas@suse.de>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
3
Features supported :
4
code that is selected by CONFIG_TCG.
4
- the 8 STM32L4x5 GPIOs are initialized with their reset values
5
(except IDR, see below)
6
- input mode : setting a pin in input mode "externally" (using input
7
irqs) results in an out irq (transmitted to SYSCFG)
8
- output mode : setting a bit in ODR sets the corresponding out irq
9
(if this line is configured in output mode)
10
- pull-up, pull-down
11
- push-pull, open-drain
5
12
6
Signed-off-by: Claudio Fontana <cfontana@suse.de>
13
Difference with the real GPIOs :
7
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
- Alternate Function and Analog mode aren't implemented :
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
pins in AF/Analog behave like pins in input mode
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
- floating pins stay at their last value
17
- register IDR reset values differ from the real one :
18
values are coherent with the other registers reset values
19
and the fact that AF/Analog modes aren't implemented
20
- setting I/O output speed isn't supported
21
- locking port bits isn't supported
22
- ADC function isn't supported
23
- GPIOH has 16 pins instead of 2 pins
24
- writing to registers LCKR, AFRL, AFRH and ASCR is ineffective
25
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Acked-by: Alistair Francis <alistair.francis@wdc.com>
30
Message-id: 20240305210444.310665-2-ines.varhol@telecom-paris.fr
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
32
---
14
MAINTAINERS | 1 +
33
MAINTAINERS | 1 +
15
target/arm/{ => tcg}/translate-a64.h | 0
34
docs/system/arm/b-l475e-iot01a.rst | 2 +-
16
target/arm/{ => tcg}/translate.h | 0
35
include/hw/gpio/stm32l4x5_gpio.h | 70 +++++
17
target/arm/{ => tcg}/a32-uncond.decode | 0
36
hw/gpio/stm32l4x5_gpio.c | 477 +++++++++++++++++++++++++++++
18
target/arm/{ => tcg}/a32.decode | 0
37
hw/gpio/Kconfig | 3 +
19
target/arm/{ => tcg}/m-nocp.decode | 0
38
hw/gpio/meson.build | 1 +
20
target/arm/{ => tcg}/mve.decode | 0
39
hw/gpio/trace-events | 6 +
21
target/arm/{ => tcg}/neon-dp.decode | 0
40
7 files changed, 559 insertions(+), 1 deletion(-)
22
target/arm/{ => tcg}/neon-ls.decode | 0
41
create mode 100644 include/hw/gpio/stm32l4x5_gpio.h
23
target/arm/{ => tcg}/neon-shared.decode | 0
42
create mode 100644 hw/gpio/stm32l4x5_gpio.c
24
target/arm/{ => tcg}/sme-fa64.decode | 0
25
target/arm/{ => tcg}/sme.decode | 0
26
target/arm/{ => tcg}/sve.decode | 0
27
target/arm/{ => tcg}/t16.decode | 0
28
target/arm/{ => tcg}/t32.decode | 0
29
target/arm/{ => tcg}/vfp-uncond.decode | 0
30
target/arm/{ => tcg}/vfp.decode | 0
31
target/arm/{ => tcg}/translate-a64.c | 0
32
target/arm/{ => tcg}/translate-m-nocp.c | 0
33
target/arm/{ => tcg}/translate-mve.c | 0
34
target/arm/{ => tcg}/translate-neon.c | 0
35
target/arm/{ => tcg}/translate-sme.c | 0
36
target/arm/{ => tcg}/translate-sve.c | 0
37
target/arm/{ => tcg}/translate-vfp.c | 0
38
target/arm/{ => tcg}/translate.c | 0
39
target/arm/meson.build | 30 +++---------------
40
target/arm/{ => tcg}/meson.build | 41 +------------------------
41
27 files changed, 6 insertions(+), 66 deletions(-)
42
rename target/arm/{ => tcg}/translate-a64.h (100%)
43
rename target/arm/{ => tcg}/translate.h (100%)
44
rename target/arm/{ => tcg}/a32-uncond.decode (100%)
45
rename target/arm/{ => tcg}/a32.decode (100%)
46
rename target/arm/{ => tcg}/m-nocp.decode (100%)
47
rename target/arm/{ => tcg}/mve.decode (100%)
48
rename target/arm/{ => tcg}/neon-dp.decode (100%)
49
rename target/arm/{ => tcg}/neon-ls.decode (100%)
50
rename target/arm/{ => tcg}/neon-shared.decode (100%)
51
rename target/arm/{ => tcg}/sme-fa64.decode (100%)
52
rename target/arm/{ => tcg}/sme.decode (100%)
53
rename target/arm/{ => tcg}/sve.decode (100%)
54
rename target/arm/{ => tcg}/t16.decode (100%)
55
rename target/arm/{ => tcg}/t32.decode (100%)
56
rename target/arm/{ => tcg}/vfp-uncond.decode (100%)
57
rename target/arm/{ => tcg}/vfp.decode (100%)
58
rename target/arm/{ => tcg}/translate-a64.c (100%)
59
rename target/arm/{ => tcg}/translate-m-nocp.c (100%)
60
rename target/arm/{ => tcg}/translate-mve.c (100%)
61
rename target/arm/{ => tcg}/translate-neon.c (100%)
62
rename target/arm/{ => tcg}/translate-sme.c (100%)
63
rename target/arm/{ => tcg}/translate-sve.c (100%)
64
rename target/arm/{ => tcg}/translate-vfp.c (100%)
65
rename target/arm/{ => tcg}/translate.c (100%)
66
copy target/arm/{ => tcg}/meson.build (64%)
67
43
68
diff --git a/MAINTAINERS b/MAINTAINERS
44
diff --git a/MAINTAINERS b/MAINTAINERS
69
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
70
--- a/MAINTAINERS
46
--- a/MAINTAINERS
71
+++ b/MAINTAINERS
47
+++ b/MAINTAINERS
72
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
48
@@ -XXX,XX +XXX,XX @@ F: hw/arm/stm32l4x5_soc.c
73
L: qemu-arm@nongnu.org
49
F: hw/misc/stm32l4x5_exti.c
74
S: Maintained
50
F: hw/misc/stm32l4x5_syscfg.c
75
F: target/arm/
51
F: hw/misc/stm32l4x5_rcc.c
76
+F: target/arm/tcg/
52
+F: hw/gpio/stm32l4x5_gpio.c
77
F: tests/tcg/arm/
53
F: include/hw/*/stm32l4x5_*.h
78
F: tests/tcg/aarch64/
54
79
F: tests/qtest/arm-cpu-features.c
55
B-L475E-IOT01A IoT Node
80
diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h
56
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
81
similarity index 100%
82
rename from target/arm/translate-a64.h
83
rename to target/arm/tcg/translate-a64.h
84
diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h
85
similarity index 100%
86
rename from target/arm/translate.h
87
rename to target/arm/tcg/translate.h
88
diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode
89
similarity index 100%
90
rename from target/arm/a32-uncond.decode
91
rename to target/arm/tcg/a32-uncond.decode
92
diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode
93
similarity index 100%
94
rename from target/arm/a32.decode
95
rename to target/arm/tcg/a32.decode
96
diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode
97
similarity index 100%
98
rename from target/arm/m-nocp.decode
99
rename to target/arm/tcg/m-nocp.decode
100
diff --git a/target/arm/mve.decode b/target/arm/tcg/mve.decode
101
similarity index 100%
102
rename from target/arm/mve.decode
103
rename to target/arm/tcg/mve.decode
104
diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode
105
similarity index 100%
106
rename from target/arm/neon-dp.decode
107
rename to target/arm/tcg/neon-dp.decode
108
diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode
109
similarity index 100%
110
rename from target/arm/neon-ls.decode
111
rename to target/arm/tcg/neon-ls.decode
112
diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.decode
113
similarity index 100%
114
rename from target/arm/neon-shared.decode
115
rename to target/arm/tcg/neon-shared.decode
116
diff --git a/target/arm/sme-fa64.decode b/target/arm/tcg/sme-fa64.decode
117
similarity index 100%
118
rename from target/arm/sme-fa64.decode
119
rename to target/arm/tcg/sme-fa64.decode
120
diff --git a/target/arm/sme.decode b/target/arm/tcg/sme.decode
121
similarity index 100%
122
rename from target/arm/sme.decode
123
rename to target/arm/tcg/sme.decode
124
diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode
125
similarity index 100%
126
rename from target/arm/sve.decode
127
rename to target/arm/tcg/sve.decode
128
diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode
129
similarity index 100%
130
rename from target/arm/t16.decode
131
rename to target/arm/tcg/t16.decode
132
diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode
133
similarity index 100%
134
rename from target/arm/t32.decode
135
rename to target/arm/tcg/t32.decode
136
diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode
137
similarity index 100%
138
rename from target/arm/vfp-uncond.decode
139
rename to target/arm/tcg/vfp-uncond.decode
140
diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode
141
similarity index 100%
142
rename from target/arm/vfp.decode
143
rename to target/arm/tcg/vfp.decode
144
diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c
145
similarity index 100%
146
rename from target/arm/translate-a64.c
147
rename to target/arm/tcg/translate-a64.c
148
diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c
149
similarity index 100%
150
rename from target/arm/translate-m-nocp.c
151
rename to target/arm/tcg/translate-m-nocp.c
152
diff --git a/target/arm/translate-mve.c b/target/arm/tcg/translate-mve.c
153
similarity index 100%
154
rename from target/arm/translate-mve.c
155
rename to target/arm/tcg/translate-mve.c
156
diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c
157
similarity index 100%
158
rename from target/arm/translate-neon.c
159
rename to target/arm/tcg/translate-neon.c
160
diff --git a/target/arm/translate-sme.c b/target/arm/tcg/translate-sme.c
161
similarity index 100%
162
rename from target/arm/translate-sme.c
163
rename to target/arm/tcg/translate-sme.c
164
diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c
165
similarity index 100%
166
rename from target/arm/translate-sve.c
167
rename to target/arm/tcg/translate-sve.c
168
diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c
169
similarity index 100%
170
rename from target/arm/translate-vfp.c
171
rename to target/arm/tcg/translate-vfp.c
172
diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c
173
similarity index 100%
174
rename from target/arm/translate.c
175
rename to target/arm/tcg/translate.c
176
diff --git a/target/arm/meson.build b/target/arm/meson.build
177
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
178
--- a/target/arm/meson.build
58
--- a/docs/system/arm/b-l475e-iot01a.rst
179
+++ b/target/arm/meson.build
59
+++ b/docs/system/arm/b-l475e-iot01a.rst
60
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
61
- STM32L4x5 EXTI (Extended interrupts and events controller)
62
- STM32L4x5 SYSCFG (System configuration controller)
63
- STM32L4x5 RCC (Reset and clock control)
64
+- STM32L4x5 GPIOs (General-purpose I/Os)
65
66
Missing devices
67
"""""""""""""""
68
@@ -XXX,XX +XXX,XX @@ Missing devices
69
The B-L475E-IOT01A does *not* support the following devices:
70
71
- Serial ports (UART)
72
-- General-purpose I/Os (GPIO)
73
- Analog to Digital Converter (ADC)
74
- SPI controller
75
- Timer controller (TIMER)
76
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
77
new file mode 100644
78
index XXXXXXX..XXXXXXX
79
--- /dev/null
80
+++ b/include/hw/gpio/stm32l4x5_gpio.h
180
@@ -XXX,XX +XXX,XX @@
81
@@ -XXX,XX +XXX,XX @@
181
-gen = [
82
+/*
182
- decodetree.process('sve.decode', extra_args: '--decode=disas_sve'),
83
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
183
- decodetree.process('sme.decode', extra_args: '--decode=disas_sme'),
84
+ *
184
- decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'),
85
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
185
- decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'),
86
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
186
- decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'),
87
+ *
187
- decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'),
88
+ * SPDX-License-Identifier: GPL-2.0-or-later
188
- decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'),
89
+ *
189
- decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'),
90
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
190
- decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'),
91
+ * See the COPYING file in the top-level directory.
191
- decodetree.process('mve.decode', extra_args: '--decode=disas_mve'),
92
+ */
192
- decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
93
+
193
- decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
94
+/*
194
- decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'),
95
+ * The reference used is the STMicroElectronics RM0351 Reference manual
195
- decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
96
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
196
-]
97
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
197
-
98
+ */
198
arm_ss = ss.source_set()
99
+
199
-arm_ss.add(gen)
100
+#ifndef HW_STM32L4X5_GPIO_H
200
arm_ss.add(files(
101
+#define HW_STM32L4X5_GPIO_H
201
'cpu.c',
102
+
202
'crypto_helper.c',
103
+#include "hw/sysbus.h"
203
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
104
+#include "qom/object.h"
204
'neon_helper.c',
105
+
205
'op_helper.c',
106
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
206
'tlb_helper.c',
107
+OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
207
- 'translate.c',
108
+
208
- 'translate-m-nocp.c',
109
+#define GPIO_NUM_PINS 16
209
- 'translate-mve.c',
110
+
210
- 'translate-neon.c',
111
+struct Stm32l4x5GpioState {
211
- 'translate-vfp.c',
112
+ SysBusDevice parent_obj;
212
'vec_helper.c',
113
+
213
'vfp_helper.c',
114
+ MemoryRegion mmio;
214
'cpu_tcg.c',
115
+
215
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
116
+ /* GPIO registers */
216
'pauth_helper.c',
117
+ uint32_t moder;
217
'sve_helper.c',
118
+ uint32_t otyper;
218
'sme_helper.c',
119
+ uint32_t ospeedr;
219
- 'translate-a64.c',
120
+ uint32_t pupdr;
220
- 'translate-sve.c',
121
+ uint32_t idr;
221
- 'translate-sme.c',
122
+ uint32_t odr;
123
+ uint32_t lckr;
124
+ uint32_t afrl;
125
+ uint32_t afrh;
126
+ uint32_t ascr;
127
+
128
+ /* GPIO registers reset values */
129
+ uint32_t moder_reset;
130
+ uint32_t ospeedr_reset;
131
+ uint32_t pupdr_reset;
132
+
133
+ /*
134
+ * External driving of pins.
135
+ * The pins can be set externally through the device
136
+ * anonymous input GPIOs lines under certain conditions.
137
+ * The pin must not be in push-pull output mode,
138
+ * and can't be set high in open-drain mode.
139
+ * Pins driven externally and configured to
140
+ * output mode will in general be "disconnected"
141
+ * (see `get_gpio_pinmask_to_disconnect()`)
142
+ */
143
+ uint16_t disconnected_pins;
144
+ uint16_t pins_connected_high;
145
+
146
+ char *name;
147
+ Clock *clk;
148
+ qemu_irq pin[GPIO_NUM_PINS];
149
+};
150
+
151
+#endif
152
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
153
new file mode 100644
154
index XXXXXXX..XXXXXXX
155
--- /dev/null
156
+++ b/hw/gpio/stm32l4x5_gpio.c
157
@@ -XXX,XX +XXX,XX @@
158
+/*
159
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
160
+ *
161
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
162
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
163
+ *
164
+ * SPDX-License-Identifier: GPL-2.0-or-later
165
+ *
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
167
+ * See the COPYING file in the top-level directory.
168
+ */
169
+
170
+/*
171
+ * The reference used is the STMicroElectronics RM0351 Reference manual
172
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
173
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
174
+ */
175
+
176
+#include "qemu/osdep.h"
177
+#include "qemu/log.h"
178
+#include "hw/gpio/stm32l4x5_gpio.h"
179
+#include "hw/irq.h"
180
+#include "hw/qdev-clock.h"
181
+#include "hw/qdev-properties.h"
182
+#include "qapi/visitor.h"
183
+#include "qapi/error.h"
184
+#include "migration/vmstate.h"
185
+#include "trace.h"
186
+
187
+#define GPIO_MODER 0x00
188
+#define GPIO_OTYPER 0x04
189
+#define GPIO_OSPEEDR 0x08
190
+#define GPIO_PUPDR 0x0C
191
+#define GPIO_IDR 0x10
192
+#define GPIO_ODR 0x14
193
+#define GPIO_BSRR 0x18
194
+#define GPIO_LCKR 0x1C
195
+#define GPIO_AFRL 0x20
196
+#define GPIO_AFRH 0x24
197
+#define GPIO_BRR 0x28
198
+#define GPIO_ASCR 0x2C
199
+
200
+/* 0b11111111_11111111_00000000_00000000 */
201
+#define RESERVED_BITS_MASK 0xFFFF0000
202
+
203
+static void update_gpio_idr(Stm32l4x5GpioState *s);
204
+
205
+static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
206
+{
207
+ return extract32(s->pupdr, 2 * pin, 2) == 1;
208
+}
209
+
210
+static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
211
+{
212
+ return extract32(s->pupdr, 2 * pin, 2) == 2;
213
+}
214
+
215
+static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
216
+{
217
+ return extract32(s->moder, 2 * pin, 2) == 1;
218
+}
219
+
220
+static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
221
+{
222
+ return extract32(s->otyper, pin, 1) == 1;
223
+}
224
+
225
+static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
226
+{
227
+ return extract32(s->otyper, pin, 1) == 0;
228
+}
229
+
230
+static void stm32l4x5_gpio_reset_hold(Object *obj)
231
+{
232
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
233
+
234
+ s->moder = s->moder_reset;
235
+ s->otyper = 0x00000000;
236
+ s->ospeedr = s->ospeedr_reset;
237
+ s->pupdr = s->pupdr_reset;
238
+ s->idr = 0x00000000;
239
+ s->odr = 0x00000000;
240
+ s->lckr = 0x00000000;
241
+ s->afrl = 0x00000000;
242
+ s->afrh = 0x00000000;
243
+ s->ascr = 0x00000000;
244
+
245
+ s->disconnected_pins = 0xFFFF;
246
+ s->pins_connected_high = 0x0000;
247
+ update_gpio_idr(s);
248
+}
249
+
250
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
251
+{
252
+ Stm32l4x5GpioState *s = opaque;
253
+ /*
254
+ * The pin isn't set if line is configured in output mode
255
+ * except if level is 0 and the output is open-drain.
256
+ * This way there will be no short-circuit prone situations.
257
+ */
258
+ if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
259
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
260
+ line);
261
+ return;
262
+ }
263
+
264
+ s->disconnected_pins &= ~(1 << line);
265
+ if (level) {
266
+ s->pins_connected_high |= (1 << line);
267
+ } else {
268
+ s->pins_connected_high &= ~(1 << line);
269
+ }
270
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
271
+ s->pins_connected_high);
272
+ update_gpio_idr(s);
273
+}
274
+
275
+
276
+static void update_gpio_idr(Stm32l4x5GpioState *s)
277
+{
278
+ uint32_t new_idr_mask = 0;
279
+ uint32_t new_idr = s->odr;
280
+ uint32_t old_idr = s->idr;
281
+ int new_pin_state, old_pin_state;
282
+
283
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
284
+ if (is_output(s, i)) {
285
+ if (is_push_pull(s, i)) {
286
+ new_idr_mask |= (1 << i);
287
+ } else if (!(s->odr & (1 << i))) {
288
+ /* open-drain ODR 0 */
289
+ new_idr_mask |= (1 << i);
290
+ /* open-drain ODR 1 */
291
+ } else if (!(s->disconnected_pins & (1 << i)) &&
292
+ !(s->pins_connected_high & (1 << i))) {
293
+ /* open-drain ODR 1 with pin connected low */
294
+ new_idr_mask |= (1 << i);
295
+ new_idr &= ~(1 << i);
296
+ /* open-drain ODR 1 with unactive pin */
297
+ } else if (is_pull_up(s, i)) {
298
+ new_idr_mask |= (1 << i);
299
+ } else if (is_pull_down(s, i)) {
300
+ new_idr_mask |= (1 << i);
301
+ new_idr &= ~(1 << i);
302
+ }
303
+ /*
304
+ * The only case left is for open-drain ODR 1
305
+ * with unactive pin without pull-up or pull-down :
306
+ * the value is floating.
307
+ */
308
+ /* input or analog mode with connected pin */
309
+ } else if (!(s->disconnected_pins & (1 << i))) {
310
+ if (s->pins_connected_high & (1 << i)) {
311
+ /* pin high */
312
+ new_idr_mask |= (1 << i);
313
+ new_idr |= (1 << i);
314
+ } else {
315
+ /* pin low */
316
+ new_idr_mask |= (1 << i);
317
+ new_idr &= ~(1 << i);
318
+ }
319
+ /* input or analog mode with disconnected pin */
320
+ } else {
321
+ if (is_pull_up(s, i)) {
322
+ /* pull-up */
323
+ new_idr_mask |= (1 << i);
324
+ new_idr |= (1 << i);
325
+ } else if (is_pull_down(s, i)) {
326
+ /* pull-down */
327
+ new_idr_mask |= (1 << i);
328
+ new_idr &= ~(1 << i);
329
+ }
330
+ /*
331
+ * The only case left is for a disconnected pin
332
+ * without pull-up or pull-down :
333
+ * the value is floating.
334
+ */
335
+ }
336
+ }
337
+
338
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
339
+ trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
340
+
341
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
342
+ if (new_idr_mask & (1 << i)) {
343
+ new_pin_state = (new_idr & (1 << i)) > 0;
344
+ old_pin_state = (old_idr & (1 << i)) > 0;
345
+ if (new_pin_state > old_pin_state) {
346
+ qemu_irq_raise(s->pin[i]);
347
+ } else if (new_pin_state < old_pin_state) {
348
+ qemu_irq_lower(s->pin[i]);
349
+ }
350
+ }
351
+ }
352
+}
353
+
354
+/*
355
+ * Return mask of pins that are both configured in output
356
+ * mode and externally driven (except pins in open-drain
357
+ * mode externally set to 0).
358
+ */
359
+static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
360
+{
361
+ uint32_t pins_to_disconnect = 0;
362
+ for (int i = 0; i < GPIO_NUM_PINS; i++) {
363
+ /* for each connected pin in output mode */
364
+ if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
365
+ /* if either push-pull or high level */
366
+ if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
367
+ pins_to_disconnect |= (1 << i);
368
+ qemu_log_mask(LOG_GUEST_ERROR,
369
+ "Line %d can't be driven externally\n",
370
+ i);
371
+ }
372
+ }
373
+ }
374
+ return pins_to_disconnect;
375
+}
376
+
377
+/*
378
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
379
+ */
380
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
381
+{
382
+ s->disconnected_pins |= lines;
383
+ trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
384
+ s->pins_connected_high);
385
+ update_gpio_idr(s);
386
+}
387
+
388
+static void disconnected_pins_set(Object *obj, Visitor *v,
389
+ const char *name, void *opaque, Error **errp)
390
+{
391
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
392
+ uint16_t value;
393
+ if (!visit_type_uint16(v, name, &value, errp)) {
394
+ return;
395
+ }
396
+ disconnect_gpio_pins(s, value);
397
+}
398
+
399
+static void disconnected_pins_get(Object *obj, Visitor *v,
400
+ const char *name, void *opaque, Error **errp)
401
+{
402
+ visit_type_uint16(v, name, (uint16_t *)opaque, errp);
403
+}
404
+
405
+static void clock_freq_get(Object *obj, Visitor *v,
406
+ const char *name, void *opaque, Error **errp)
407
+{
408
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
409
+ uint32_t clock_freq_hz = clock_get_hz(s->clk);
410
+ visit_type_uint32(v, name, &clock_freq_hz, errp);
411
+}
412
+
413
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
414
+ uint64_t val64, unsigned int size)
415
+{
416
+ Stm32l4x5GpioState *s = opaque;
417
+
418
+ uint32_t value = val64;
419
+ trace_stm32l4x5_gpio_write(s->name, addr, val64);
420
+
421
+ switch (addr) {
422
+ case GPIO_MODER:
423
+ s->moder = value;
424
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
425
+ qemu_log_mask(LOG_UNIMP,
426
+ "%s: Analog and AF modes aren't supported\n\
427
+ Analog and AF mode behave like input mode\n",
428
+ __func__);
429
+ return;
430
+ case GPIO_OTYPER:
431
+ s->otyper = value & ~RESERVED_BITS_MASK;
432
+ disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
433
+ return;
434
+ case GPIO_OSPEEDR:
435
+ qemu_log_mask(LOG_UNIMP,
436
+ "%s: Changing I/O output speed isn't supported\n\
437
+ I/O speed is already maximal\n",
438
+ __func__);
439
+ s->ospeedr = value;
440
+ return;
441
+ case GPIO_PUPDR:
442
+ s->pupdr = value;
443
+ update_gpio_idr(s);
444
+ return;
445
+ case GPIO_IDR:
446
+ qemu_log_mask(LOG_UNIMP,
447
+ "%s: GPIO->IDR is read-only\n",
448
+ __func__);
449
+ return;
450
+ case GPIO_ODR:
451
+ s->odr = value & ~RESERVED_BITS_MASK;
452
+ update_gpio_idr(s);
453
+ return;
454
+ case GPIO_BSRR: {
455
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
456
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
457
+ /* If both BSx and BRx are set, BSx has priority.*/
458
+ s->odr &= ~bits_to_reset;
459
+ s->odr |= bits_to_set;
460
+ update_gpio_idr(s);
461
+ return;
462
+ }
463
+ case GPIO_LCKR:
464
+ qemu_log_mask(LOG_UNIMP,
465
+ "%s: Locking port bits configuration isn't supported\n",
466
+ __func__);
467
+ s->lckr = value & ~RESERVED_BITS_MASK;
468
+ return;
469
+ case GPIO_AFRL:
470
+ qemu_log_mask(LOG_UNIMP,
471
+ "%s: Alternate functions aren't supported\n",
472
+ __func__);
473
+ s->afrl = value;
474
+ return;
475
+ case GPIO_AFRH:
476
+ qemu_log_mask(LOG_UNIMP,
477
+ "%s: Alternate functions aren't supported\n",
478
+ __func__);
479
+ s->afrh = value;
480
+ return;
481
+ case GPIO_BRR: {
482
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
483
+ s->odr &= ~bits_to_reset;
484
+ update_gpio_idr(s);
485
+ return;
486
+ }
487
+ case GPIO_ASCR:
488
+ qemu_log_mask(LOG_UNIMP,
489
+ "%s: ADC function isn't supported\n",
490
+ __func__);
491
+ s->ascr = value & ~RESERVED_BITS_MASK;
492
+ return;
493
+ default:
494
+ qemu_log_mask(LOG_GUEST_ERROR,
495
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
496
+ }
497
+}
498
+
499
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
500
+ unsigned int size)
501
+{
502
+ Stm32l4x5GpioState *s = opaque;
503
+
504
+ trace_stm32l4x5_gpio_read(s->name, addr);
505
+
506
+ switch (addr) {
507
+ case GPIO_MODER:
508
+ return s->moder;
509
+ case GPIO_OTYPER:
510
+ return s->otyper;
511
+ case GPIO_OSPEEDR:
512
+ return s->ospeedr;
513
+ case GPIO_PUPDR:
514
+ return s->pupdr;
515
+ case GPIO_IDR:
516
+ return s->idr;
517
+ case GPIO_ODR:
518
+ return s->odr;
519
+ case GPIO_BSRR:
520
+ return 0;
521
+ case GPIO_LCKR:
522
+ return s->lckr;
523
+ case GPIO_AFRL:
524
+ return s->afrl;
525
+ case GPIO_AFRH:
526
+ return s->afrh;
527
+ case GPIO_BRR:
528
+ return 0;
529
+ case GPIO_ASCR:
530
+ return s->ascr;
531
+ default:
532
+ qemu_log_mask(LOG_GUEST_ERROR,
533
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
534
+ return 0;
535
+ }
536
+}
537
+
538
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
539
+ .read = stm32l4x5_gpio_read,
540
+ .write = stm32l4x5_gpio_write,
541
+ .endianness = DEVICE_NATIVE_ENDIAN,
542
+ .impl = {
543
+ .min_access_size = 4,
544
+ .max_access_size = 4,
545
+ .unaligned = false,
546
+ },
547
+ .valid = {
548
+ .min_access_size = 4,
549
+ .max_access_size = 4,
550
+ .unaligned = false,
551
+ },
552
+};
553
+
554
+static void stm32l4x5_gpio_init(Object *obj)
555
+{
556
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
557
+
558
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
559
+ TYPE_STM32L4X5_GPIO, 0x400);
560
+
561
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
562
+
563
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
564
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
565
+
566
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
567
+
568
+ object_property_add(obj, "disconnected-pins", "uint16",
569
+ disconnected_pins_get, disconnected_pins_set,
570
+ NULL, &s->disconnected_pins);
571
+ object_property_add(obj, "clock-freq-hz", "uint32",
572
+ clock_freq_get, NULL, NULL, NULL);
573
+}
574
+
575
+static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
576
+{
577
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
578
+ if (!clock_has_source(s->clk)) {
579
+ error_setg(errp, "GPIO: clk input must be connected");
580
+ return;
581
+ }
582
+}
583
+
584
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
585
+ .name = TYPE_STM32L4X5_GPIO,
586
+ .version_id = 1,
587
+ .minimum_version_id = 1,
588
+ .fields = (VMStateField[]){
589
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
590
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
591
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
592
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
593
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
594
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
595
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
596
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
597
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
598
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
599
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
600
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
601
+ VMSTATE_END_OF_LIST()
602
+ }
603
+};
604
+
605
+static Property stm32l4x5_gpio_properties[] = {
606
+ DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
607
+ DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
608
+ DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
609
+ DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
610
+ DEFINE_PROP_END_OF_LIST(),
611
+};
612
+
613
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
614
+{
615
+ DeviceClass *dc = DEVICE_CLASS(klass);
616
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
617
+
618
+ device_class_set_props(dc, stm32l4x5_gpio_properties);
619
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
620
+ dc->realize = stm32l4x5_gpio_realize;
621
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
622
+}
623
+
624
+static const TypeInfo stm32l4x5_gpio_types[] = {
625
+ {
626
+ .name = TYPE_STM32L4X5_GPIO,
627
+ .parent = TYPE_SYS_BUS_DEVICE,
628
+ .instance_size = sizeof(Stm32l4x5GpioState),
629
+ .instance_init = stm32l4x5_gpio_init,
630
+ .class_init = stm32l4x5_gpio_class_init,
631
+ },
632
+};
633
+
634
+DEFINE_TYPES(stm32l4x5_gpio_types)
635
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
636
index XXXXXXX..XXXXXXX 100644
637
--- a/hw/gpio/Kconfig
638
+++ b/hw/gpio/Kconfig
639
@@ -XXX,XX +XXX,XX @@ config GPIO_PWR
640
641
config SIFIVE_GPIO
642
bool
643
+
644
+config STM32L4X5_GPIO
645
+ bool
646
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
647
index XXXXXXX..XXXXXXX 100644
648
--- a/hw/gpio/meson.build
649
+++ b/hw/gpio/meson.build
650
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
651
'bcm2835_gpio.c',
652
'bcm2838_gpio.c'
222
))
653
))
223
654
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
224
arm_softmmu_ss = ss.source_set()
655
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
225
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
656
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
226
657
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
227
subdir('hvf')
228
229
+if 'CONFIG_TCG' in config_all
230
+ subdir('tcg')
231
+endif
232
+
233
target_arch += {'arm': arm_ss}
234
target_softmmu_arch += {'arm': arm_softmmu_ss}
235
diff --git a/target/arm/meson.build b/target/arm/tcg/meson.build
236
similarity index 64%
237
copy from target/arm/meson.build
238
copy to target/arm/tcg/meson.build
239
index XXXXXXX..XXXXXXX 100644
658
index XXXXXXX..XXXXXXX 100644
240
--- a/target/arm/meson.build
659
--- a/hw/gpio/trace-events
241
+++ b/target/arm/tcg/meson.build
660
+++ b/hw/gpio/trace-events
242
@@ -XXX,XX +XXX,XX @@ gen = [
661
@@ -XXX,XX +XXX,XX @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
243
decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']),
662
# aspeed_gpio.c
244
]
663
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
245
664
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
246
-arm_ss = ss.source_set()
665
+
247
arm_ss.add(gen)
666
+# stm32l4x5_gpio.c
248
+
667
+stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
249
arm_ss.add(files(
668
+stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
250
- 'cpu.c',
669
+stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x%x"
251
- 'crypto_helper.c',
670
+stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x%x levels: 0x%x"
252
- 'debug_helper.c',
253
- 'gdbstub.c',
254
- 'helper.c',
255
- 'iwmmxt_helper.c',
256
- 'm_helper.c',
257
- 'mve_helper.c',
258
- 'neon_helper.c',
259
- 'op_helper.c',
260
- 'tlb_helper.c',
261
'translate.c',
262
'translate-m-nocp.c',
263
'translate-mve.c',
264
'translate-neon.c',
265
'translate-vfp.c',
266
- 'vec_helper.c',
267
- 'vfp_helper.c',
268
- 'cpu_tcg.c',
269
))
270
-arm_ss.add(zlib)
271
-
272
-arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
273
274
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
275
- 'cpu64.c',
276
- 'gdbstub64.c',
277
- 'helper-a64.c',
278
- 'mte_helper.c',
279
- 'pauth_helper.c',
280
- 'sve_helper.c',
281
- 'sme_helper.c',
282
'translate-a64.c',
283
'translate-sve.c',
284
'translate-sme.c',
285
))
286
-
287
-arm_softmmu_ss = ss.source_set()
288
-arm_softmmu_ss.add(files(
289
- 'arch_dump.c',
290
- 'arm-powerctl.c',
291
- 'machine.c',
292
- 'monitor.c',
293
- 'psci.c',
294
- 'ptw.c',
295
-))
296
-
297
-subdir('hvf')
298
-
299
-target_arch += {'arm': arm_ss}
300
-target_softmmu_arch += {'arm': arm_softmmu_ss}
301
--
671
--
302
2.34.1
672
2.34.1
303
673
304
674
diff view generated by jsdifflib
[PULL 23/25] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
[PULL 10/14] hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
QOM *DECLARE* macros expect a typedef as first argument,
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
not a structure. Replace 'struct IRQState' by 'IRQState'
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
to avoid when modifying the macros:
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition
7
Message-id: 20240305210444.310665-3-ines.varhol@telecom-paris.fr
8
DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
9
^
10
11
Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER.
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20230113200138.52869-3-philmd@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
9
---
19
hw/core/irq.c | 9 ++++-----
10
include/hw/arm/stm32l4x5_soc.h | 2 +
20
1 file changed, 4 insertions(+), 5 deletions(-)
11
include/hw/gpio/stm32l4x5_gpio.h | 1 +
21
12
include/hw/misc/stm32l4x5_syscfg.h | 3 +-
22
diff --git a/hw/core/irq.c b/hw/core/irq.c
13
hw/arm/stm32l4x5_soc.c | 71 +++++++++++++++++++++++-------
23
index XXXXXXX..XXXXXXX 100644
14
hw/misc/stm32l4x5_syscfg.c | 1 +
24
--- a/hw/core/irq.c
15
hw/arm/Kconfig | 3 +-
25
+++ b/hw/core/irq.c
16
6 files changed, 63 insertions(+), 18 deletions(-)
17
18
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/stm32l4x5_soc.h
21
+++ b/include/hw/arm/stm32l4x5_soc.h
22
@@ -XXX,XX +XXX,XX @@
23
#include "hw/misc/stm32l4x5_syscfg.h"
24
#include "hw/misc/stm32l4x5_exti.h"
25
#include "hw/misc/stm32l4x5_rcc.h"
26
+#include "hw/gpio/stm32l4x5_gpio.h"
27
#include "qom/object.h"
28
29
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
30
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
31
OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
32
Stm32l4x5SyscfgState syscfg;
33
Stm32l4x5RccState rcc;
34
+ Stm32l4x5GpioState gpio[NUM_GPIOS];
35
36
MemoryRegion sram1;
37
MemoryRegion sram2;
38
diff --git a/include/hw/gpio/stm32l4x5_gpio.h b/include/hw/gpio/stm32l4x5_gpio.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/gpio/stm32l4x5_gpio.h
41
+++ b/include/hw/gpio/stm32l4x5_gpio.h
42
@@ -XXX,XX +XXX,XX @@
43
#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
44
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
45
46
+#define NUM_GPIOS 8
47
#define GPIO_NUM_PINS 16
48
49
struct Stm32l4x5GpioState {
50
diff --git a/include/hw/misc/stm32l4x5_syscfg.h b/include/hw/misc/stm32l4x5_syscfg.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/include/hw/misc/stm32l4x5_syscfg.h
53
+++ b/include/hw/misc/stm32l4x5_syscfg.h
54
@@ -XXX,XX +XXX,XX @@
55
56
#include "hw/sysbus.h"
57
#include "qom/object.h"
58
+#include "hw/gpio/stm32l4x5_gpio.h"
59
60
#define TYPE_STM32L4X5_SYSCFG "stm32l4x5-syscfg"
61
OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5SyscfgState, STM32L4X5_SYSCFG)
62
63
-#define NUM_GPIOS 8
64
-#define GPIO_NUM_PINS 16
65
#define SYSCFG_NUM_EXTICR 4
66
67
struct Stm32l4x5SyscfgState {
68
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/stm32l4x5_soc.c
71
+++ b/hw/arm/stm32l4x5_soc.c
72
@@ -XXX,XX +XXX,XX @@
73
#include "sysemu/sysemu.h"
74
#include "hw/or-irq.h"
75
#include "hw/arm/stm32l4x5_soc.h"
76
+#include "hw/gpio/stm32l4x5_gpio.h"
77
#include "hw/qdev-clock.h"
78
#include "hw/misc/unimp.h"
79
80
@@ -XXX,XX +XXX,XX @@ static const int exti_or_gate1_lines_in[EXTI_OR_GATE1_NUM_LINES_IN] = {
81
16, 35, 36, 37, 38,
82
};
83
84
+static const struct {
85
+ uint32_t addr;
86
+ uint32_t moder_reset;
87
+ uint32_t ospeedr_reset;
88
+ uint32_t pupdr_reset;
89
+} stm32l4x5_gpio_cfg[NUM_GPIOS] = {
90
+ { 0x48000000, 0xABFFFFFF, 0x0C000000, 0x64000000 },
91
+ { 0x48000400, 0xFFFFFEBF, 0x00000000, 0x00000100 },
92
+ { 0x48000800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
93
+ { 0x48000C00, 0xFFFFFFFF, 0x00000000, 0x00000000 },
94
+ { 0x48001000, 0xFFFFFFFF, 0x00000000, 0x00000000 },
95
+ { 0x48001400, 0xFFFFFFFF, 0x00000000, 0x00000000 },
96
+ { 0x48001800, 0xFFFFFFFF, 0x00000000, 0x00000000 },
97
+ { 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
98
+};
99
+
100
static void stm32l4x5_soc_initfn(Object *obj)
101
{
102
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
103
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
104
}
105
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG);
106
object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32L4X5_RCC);
107
+
108
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
109
+ g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
110
+ object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
111
+ }
112
}
113
114
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
115
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
116
Stm32l4x5SocState *s = STM32L4X5_SOC(dev_soc);
117
const Stm32l4x5SocClass *sc = STM32L4X5_SOC_GET_CLASS(dev_soc);
118
MemoryRegion *system_memory = get_system_memory();
119
- DeviceState *armv7m;
120
+ DeviceState *armv7m, *dev;
121
SysBusDevice *busdev;
122
+ uint32_t pin_index;
123
124
if (!memory_region_init_rom(&s->flash, OBJECT(dev_soc), "flash",
125
sc->flash_size, errp)) {
126
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
127
return;
128
}
129
130
+ /* GPIOs */
131
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
132
+ g_autofree char *name = g_strdup_printf("%c", 'A' + i);
133
+ dev = DEVICE(&s->gpio[i]);
134
+ qdev_prop_set_string(dev, "name", name);
135
+ qdev_prop_set_uint32(dev, "mode-reset",
136
+ stm32l4x5_gpio_cfg[i].moder_reset);
137
+ qdev_prop_set_uint32(dev, "ospeed-reset",
138
+ stm32l4x5_gpio_cfg[i].ospeedr_reset);
139
+ qdev_prop_set_uint32(dev, "pupd-reset",
140
+ stm32l4x5_gpio_cfg[i].pupdr_reset);
141
+ busdev = SYS_BUS_DEVICE(&s->gpio[i]);
142
+ g_free(name);
143
+ name = g_strdup_printf("gpio%c-out", 'a' + i);
144
+ qdev_connect_clock_in(DEVICE(&s->gpio[i]), "clk",
145
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
146
+ if (!sysbus_realize(busdev, errp)) {
147
+ return;
148
+ }
149
+ sysbus_mmio_map(busdev, 0, stm32l4x5_gpio_cfg[i].addr);
150
+ }
151
+
152
/* System configuration controller */
153
busdev = SYS_BUS_DEVICE(&s->syscfg);
154
if (!sysbus_realize(busdev, errp)) {
155
return;
156
}
157
sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
158
- /*
159
- * TODO: when the GPIO device is implemented, connect it
160
- * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and
161
- * GPIO_NUM_PINS.
162
- */
163
+
164
+ for (unsigned i = 0; i < NUM_GPIOS; i++) {
165
+ for (unsigned j = 0; j < GPIO_NUM_PINS; j++) {
166
+ pin_index = GPIO_NUM_PINS * i + j;
167
+ qdev_connect_gpio_out(DEVICE(&s->gpio[i]), j,
168
+ qdev_get_gpio_in(DEVICE(&s->syscfg),
169
+ pin_index));
170
+ }
171
+ }
172
173
/* EXTI device */
174
busdev = SYS_BUS_DEVICE(&s->exti);
175
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
176
}
177
}
178
179
- for (unsigned i = 0; i < 16; i++) {
180
+ for (unsigned i = 0; i < GPIO_NUM_PINS; i++) {
181
qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
182
qdev_get_gpio_in(DEVICE(&s->exti), i));
183
}
184
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
185
/* RESERVED: 0x40024400, 0x7FDBC00 */
186
187
/* AHB2 BUS */
188
- create_unimplemented_device("GPIOA", 0x48000000, 0x400);
189
- create_unimplemented_device("GPIOB", 0x48000400, 0x400);
190
- create_unimplemented_device("GPIOC", 0x48000800, 0x400);
191
- create_unimplemented_device("GPIOD", 0x48000C00, 0x400);
192
- create_unimplemented_device("GPIOE", 0x48001000, 0x400);
193
- create_unimplemented_device("GPIOF", 0x48001400, 0x400);
194
- create_unimplemented_device("GPIOG", 0x48001800, 0x400);
195
- create_unimplemented_device("GPIOH", 0x48001C00, 0x400);
196
/* RESERVED: 0x48002000, 0x7FDBC00 */
197
create_unimplemented_device("OTG_FS", 0x50000000, 0x40000);
198
create_unimplemented_device("ADC", 0x50040000, 0x400);
199
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/misc/stm32l4x5_syscfg.c
202
+++ b/hw/misc/stm32l4x5_syscfg.c
26
@@ -XXX,XX +XXX,XX @@
203
@@ -XXX,XX +XXX,XX @@
27
#include "hw/irq.h"
204
#include "hw/irq.h"
28
#include "qom/object.h"
205
#include "migration/vmstate.h"
29
206
#include "hw/misc/stm32l4x5_syscfg.h"
30
-DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ,
207
+#include "hw/gpio/stm32l4x5_gpio.h"
31
- TYPE_IRQ)
208
32
+OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ)
209
#define SYSCFG_MEMRMP 0x00
33
210
#define SYSCFG_CFGR1 0x04
34
struct IRQState {
211
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
35
Object parent_obj;
212
index XXXXXXX..XXXXXXX 100644
36
@@ -XXX,XX +XXX,XX @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
213
--- a/hw/arm/Kconfig
37
214
+++ b/hw/arm/Kconfig
38
qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
215
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
39
{
216
bool
40
- struct IRQState *irq;
217
select ARM_V7M
41
+ IRQState *irq;
218
select OR_IRQ
42
219
- select STM32L4X5_SYSCFG
43
irq = IRQ(object_new(TYPE_IRQ));
220
select STM32L4X5_EXTI
44
irq->handler = handler;
221
+ select STM32L4X5_SYSCFG
45
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq)
222
select STM32L4X5_RCC
46
223
+ select STM32L4X5_GPIO
47
static void qemu_notirq(void *opaque, int line, int level)
224
48
{
225
config XLNX_ZYNQMP_ARM
49
- struct IRQState *irq = opaque;
226
bool
50
+ IRQState *irq = opaque;
51
52
irq->handler(irq->opaque, irq->n, !level);
53
}
54
@@ -XXX,XX +XXX,XX @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
55
static const TypeInfo irq_type_info = {
56
.name = TYPE_IRQ,
57
.parent = TYPE_OBJECT,
58
- .instance_size = sizeof(struct IRQState),
59
+ .instance_size = sizeof(IRQState),
60
};
61
62
static void irq_register_types(void)
63
--
227
--
64
2.34.1
228
2.34.1
65
229
66
230
diff view generated by jsdifflib
[PULL 05/25] target/arm: move helpers to tcg/
[PULL 11/14] tests/qtest: Add STM32L4x5 GPIO QTest testcase
1
From: Claudio Fontana <cfontana@suse.de>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
3
The testcase contains :
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
- `test_idr_reset_value()` :
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
- `test_gpio_output_mode()` :
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Checks that writing a bit in register ODR results in the corresponding
8
pin rising or lowering, if this pin is configured in output mode.
9
- `test_gpio_input_mode()` :
10
Checks that a input pin set high or low externally results
11
in the pin rising and lowering.
12
- `test_pull_up_pull_down()` :
13
Checks that a floating pin in pull-up/down mode is actually high/down.
14
- `test_push_pull()` :
15
Checks that a pin set externally is disconnected when configured in
16
push-pull output mode, and can't be set externally while in this mode.
17
- `test_open_drain()` :
18
Checks that a pin set externally high is disconnected when configured
19
in open-drain output mode, and can't be set high while in this mode.
20
- `test_bsrr_brr()` :
21
Checks that writing to BSRR and BRR has the desired result in ODR.
22
- `test_clock_enable()` :
23
Checks that GPIO clock is at the right frequency after enabling it.
24
25
Acked-by: Thomas Huth <thuth@redhat.com>
26
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
27
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
28
Message-id: 20240305210444.310665-4-ines.varhol@telecom-paris.fr
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
30
---
10
target/arm/{ => tcg}/vec_internal.h | 0
31
tests/qtest/stm32l4x5_gpio-test.c | 551 ++++++++++++++++++++++++++++++
11
target/arm/tcg-stubs.c | 23 +++++++++++++++++++++++
32
tests/qtest/meson.build | 3 +-
12
target/arm/{ => tcg}/crypto_helper.c | 0
33
2 files changed, 553 insertions(+), 1 deletion(-)
13
target/arm/{ => tcg}/helper-a64.c | 0
34
create mode 100644 tests/qtest/stm32l4x5_gpio-test.c
14
target/arm/{ => tcg}/iwmmxt_helper.c | 0
15
target/arm/{ => tcg}/m_helper.c | 0
16
target/arm/{ => tcg}/mte_helper.c | 0
17
target/arm/{ => tcg}/mve_helper.c | 0
18
target/arm/{ => tcg}/neon_helper.c | 0
19
target/arm/{ => tcg}/op_helper.c | 0
20
target/arm/{ => tcg}/pauth_helper.c | 0
21
target/arm/{ => tcg}/sme_helper.c | 0
22
target/arm/{ => tcg}/sve_helper.c | 0
23
target/arm/{ => tcg}/tlb_helper.c | 0
24
target/arm/{ => tcg}/vec_helper.c | 0
25
target/arm/meson.build | 15 ++-------------
26
target/arm/tcg/meson.build | 13 +++++++++++++
27
17 files changed, 38 insertions(+), 13 deletions(-)
28
rename target/arm/{ => tcg}/vec_internal.h (100%)
29
create mode 100644 target/arm/tcg-stubs.c
30
rename target/arm/{ => tcg}/crypto_helper.c (100%)
31
rename target/arm/{ => tcg}/helper-a64.c (100%)
32
rename target/arm/{ => tcg}/iwmmxt_helper.c (100%)
33
rename target/arm/{ => tcg}/m_helper.c (100%)
34
rename target/arm/{ => tcg}/mte_helper.c (100%)
35
rename target/arm/{ => tcg}/mve_helper.c (100%)
36
rename target/arm/{ => tcg}/neon_helper.c (100%)
37
rename target/arm/{ => tcg}/op_helper.c (100%)
38
rename target/arm/{ => tcg}/pauth_helper.c (100%)
39
rename target/arm/{ => tcg}/sme_helper.c (100%)
40
rename target/arm/{ => tcg}/sve_helper.c (100%)
41
rename target/arm/{ => tcg}/tlb_helper.c (100%)
42
rename target/arm/{ => tcg}/vec_helper.c (100%)
43
35
44
diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h
36
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
45
similarity index 100%
46
rename from target/arm/vec_internal.h
47
rename to target/arm/tcg/vec_internal.h
48
diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c
49
new file mode 100644
37
new file mode 100644
50
index XXXXXXX..XXXXXXX
38
index XXXXXXX..XXXXXXX
51
--- /dev/null
39
--- /dev/null
52
+++ b/target/arm/tcg-stubs.c
40
+++ b/tests/qtest/stm32l4x5_gpio-test.c
53
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
54
+/*
42
+/*
55
+ * QEMU ARM stubs for some TCG helper functions
43
+ * QTest testcase for STM32L4x5_GPIO
56
+ *
44
+ *
57
+ * Copyright 2021 SUSE LLC
45
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
46
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
58
+ *
47
+ *
59
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
48
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
60
+ * See the COPYING file in the top-level directory.
49
+ * See the COPYING file in the top-level directory.
61
+ */
50
+ */
62
+
51
+
63
+#include "qemu/osdep.h"
52
+#include "qemu/osdep.h"
64
+#include "cpu.h"
53
+#include "libqtest-single.h"
65
+#include "internals.h"
54
+
66
+
55
+#define GPIO_BASE_ADDR 0x48000000
67
+void write_v7m_exception(CPUARMState *env, uint32_t new_exc)
56
+#define GPIO_SIZE 0x400
68
+{
57
+#define NUM_GPIOS 8
69
+ g_assert_not_reached();
58
+#define NUM_GPIO_PINS 16
70
+}
59
+
71
+
60
+#define GPIO_A 0x48000000
72
+void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
61
+#define GPIO_B 0x48000400
73
+ uint32_t target_el, uintptr_t ra)
62
+#define GPIO_C 0x48000800
74
+{
63
+#define GPIO_D 0x48000C00
75
+ g_assert_not_reached();
64
+#define GPIO_E 0x48001000
76
+}
65
+#define GPIO_F 0x48001400
77
diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c
66
+#define GPIO_G 0x48001800
78
similarity index 100%
67
+#define GPIO_H 0x48001C00
79
rename from target/arm/crypto_helper.c
68
+
80
rename to target/arm/tcg/crypto_helper.c
69
+#define MODER 0x00
81
diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c
70
+#define OTYPER 0x04
82
similarity index 100%
71
+#define PUPDR 0x0C
83
rename from target/arm/helper-a64.c
72
+#define IDR 0x10
84
rename to target/arm/tcg/helper-a64.c
73
+#define ODR 0x14
85
diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c
74
+#define BSRR 0x18
86
similarity index 100%
75
+#define BRR 0x28
87
rename from target/arm/iwmmxt_helper.c
76
+
88
rename to target/arm/tcg/iwmmxt_helper.c
77
+#define MODER_INPUT 0
89
diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c
78
+#define MODER_OUTPUT 1
90
similarity index 100%
79
+
91
rename from target/arm/m_helper.c
80
+#define PUPDR_NONE 0
92
rename to target/arm/tcg/m_helper.c
81
+#define PUPDR_PULLUP 1
93
diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c
82
+#define PUPDR_PULLDOWN 2
94
similarity index 100%
83
+
95
rename from target/arm/mte_helper.c
84
+#define OTYPER_PUSH_PULL 0
96
rename to target/arm/tcg/mte_helper.c
85
+#define OTYPER_OPEN_DRAIN 1
97
diff --git a/target/arm/mve_helper.c b/target/arm/tcg/mve_helper.c
86
+
98
similarity index 100%
87
+const uint32_t moder_reset[NUM_GPIOS] = {
99
rename from target/arm/mve_helper.c
88
+ 0xABFFFFFF,
100
rename to target/arm/tcg/mve_helper.c
89
+ 0xFFFFFEBF,
101
diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c
90
+ 0xFFFFFFFF,
102
similarity index 100%
91
+ 0xFFFFFFFF,
103
rename from target/arm/neon_helper.c
92
+ 0xFFFFFFFF,
104
rename to target/arm/tcg/neon_helper.c
93
+ 0xFFFFFFFF,
105
diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c
94
+ 0xFFFFFFFF,
106
similarity index 100%
95
+ 0x0000000F
107
rename from target/arm/op_helper.c
96
+};
108
rename to target/arm/tcg/op_helper.c
97
+
109
diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c
98
+const uint32_t pupdr_reset[NUM_GPIOS] = {
110
similarity index 100%
99
+ 0x64000000,
111
rename from target/arm/pauth_helper.c
100
+ 0x00000100,
112
rename to target/arm/tcg/pauth_helper.c
101
+ 0x00000000,
113
diff --git a/target/arm/sme_helper.c b/target/arm/tcg/sme_helper.c
102
+ 0x00000000,
114
similarity index 100%
103
+ 0x00000000,
115
rename from target/arm/sme_helper.c
104
+ 0x00000000,
116
rename to target/arm/tcg/sme_helper.c
105
+ 0x00000000,
117
diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c
106
+ 0x00000000
118
similarity index 100%
107
+};
119
rename from target/arm/sve_helper.c
108
+
120
rename to target/arm/tcg/sve_helper.c
109
+const uint32_t idr_reset[NUM_GPIOS] = {
121
diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c
110
+ 0x0000A000,
122
similarity index 100%
111
+ 0x00000010,
123
rename from target/arm/tlb_helper.c
112
+ 0x00000000,
124
rename to target/arm/tcg/tlb_helper.c
113
+ 0x00000000,
125
diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c
114
+ 0x00000000,
126
similarity index 100%
115
+ 0x00000000,
127
rename from target/arm/vec_helper.c
116
+ 0x00000000,
128
rename to target/arm/tcg/vec_helper.c
117
+ 0x00000000
129
diff --git a/target/arm/meson.build b/target/arm/meson.build
118
+};
119
+
120
+static uint32_t gpio_readl(unsigned int gpio, unsigned int offset)
121
+{
122
+ return readl(gpio + offset);
123
+}
124
+
125
+static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value)
126
+{
127
+ writel(gpio + offset, value);
128
+}
129
+
130
+static void gpio_set_bit(unsigned int gpio, unsigned int reg,
131
+ unsigned int pin, uint32_t value)
132
+{
133
+ uint32_t mask = 0xFFFFFFFF & ~(0x1 << pin);
134
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin);
135
+}
136
+
137
+static void gpio_set_2bits(unsigned int gpio, unsigned int reg,
138
+ unsigned int pin, uint32_t value)
139
+{
140
+ uint32_t offset = 2 * pin;
141
+ uint32_t mask = 0xFFFFFFFF & ~(0x3 << offset);
142
+ gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset);
143
+}
144
+
145
+static unsigned int get_gpio_id(uint32_t gpio_addr)
146
+{
147
+ return (gpio_addr - GPIO_BASE_ADDR) / GPIO_SIZE;
148
+}
149
+
150
+static void gpio_set_irq(unsigned int gpio, int num, int level)
151
+{
152
+ g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c",
153
+ get_gpio_id(gpio) + 'a');
154
+ qtest_set_irq_in(global_qtest, name, NULL, num, level);
155
+}
156
+
157
+static void disconnect_all_pins(unsigned int gpio)
158
+{
159
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
160
+ get_gpio_id(gpio) + 'a');
161
+ QDict *r;
162
+
163
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-set', 'arguments': "
164
+ "{ 'path': %s, 'property': 'disconnected-pins', 'value': %d } }",
165
+ path, 0xFFFF);
166
+ g_assert_false(qdict_haskey(r, "error"));
167
+ qobject_unref(r);
168
+}
169
+
170
+static uint32_t get_disconnected_pins(unsigned int gpio)
171
+{
172
+ g_autofree char *path = g_strdup_printf("/machine/soc/gpio%c",
173
+ get_gpio_id(gpio) + 'a');
174
+ uint32_t disconnected_pins = 0;
175
+ QDict *r;
176
+
177
+ r = qtest_qmp(global_qtest, "{ 'execute': 'qom-get', 'arguments':"
178
+ " { 'path': %s, 'property': 'disconnected-pins'} }", path);
179
+ g_assert_false(qdict_haskey(r, "error"));
180
+ disconnected_pins = qdict_get_int(r, "return");
181
+ qobject_unref(r);
182
+ return disconnected_pins;
183
+}
184
+
185
+static uint32_t reset(uint32_t gpio, unsigned int offset)
186
+{
187
+ switch (offset) {
188
+ case MODER:
189
+ return moder_reset[get_gpio_id(gpio)];
190
+ case PUPDR:
191
+ return pupdr_reset[get_gpio_id(gpio)];
192
+ case IDR:
193
+ return idr_reset[get_gpio_id(gpio)];
194
+ }
195
+ return 0x0;
196
+}
197
+
198
+static void system_reset(void)
199
+{
200
+ QDict *r;
201
+ r = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
202
+ g_assert_false(qdict_haskey(r, "error"));
203
+ qobject_unref(r);
204
+}
205
+
206
+static void test_idr_reset_value(void)
207
+{
208
+ /*
209
+ * Checks that the values in MODER, OTYPER, PUPDR and ODR
210
+ * after reset are correct, and that the value in IDR is
211
+ * coherent.
212
+ * Since AF and analog modes aren't implemented, IDR reset
213
+ * values aren't the same as with a real board.
214
+ *
215
+ * Register IDR contains the actual values of all GPIO pins.
216
+ * Its value depends on the pins' configuration
217
+ * (intput/output/analog : register MODER, push-pull/open-drain :
218
+ * register OTYPER, pull-up/pull-down/none : register PUPDR)
219
+ * and on the values stored in register ODR
220
+ * (in case the pin is in output mode).
221
+ */
222
+
223
+ gpio_writel(GPIO_A, MODER, 0xDEADBEEF);
224
+ gpio_writel(GPIO_A, ODR, 0xDEADBEEF);
225
+ gpio_writel(GPIO_A, OTYPER, 0xDEADBEEF);
226
+ gpio_writel(GPIO_A, PUPDR, 0xDEADBEEF);
227
+
228
+ gpio_writel(GPIO_B, MODER, 0xDEADBEEF);
229
+ gpio_writel(GPIO_B, ODR, 0xDEADBEEF);
230
+ gpio_writel(GPIO_B, OTYPER, 0xDEADBEEF);
231
+ gpio_writel(GPIO_B, PUPDR, 0xDEADBEEF);
232
+
233
+ gpio_writel(GPIO_C, MODER, 0xDEADBEEF);
234
+ gpio_writel(GPIO_C, ODR, 0xDEADBEEF);
235
+ gpio_writel(GPIO_C, OTYPER, 0xDEADBEEF);
236
+ gpio_writel(GPIO_C, PUPDR, 0xDEADBEEF);
237
+
238
+ gpio_writel(GPIO_H, MODER, 0xDEADBEEF);
239
+ gpio_writel(GPIO_H, ODR, 0xDEADBEEF);
240
+ gpio_writel(GPIO_H, OTYPER, 0xDEADBEEF);
241
+ gpio_writel(GPIO_H, PUPDR, 0xDEADBEEF);
242
+
243
+ system_reset();
244
+
245
+ uint32_t moder = gpio_readl(GPIO_A, MODER);
246
+ uint32_t odr = gpio_readl(GPIO_A, ODR);
247
+ uint32_t otyper = gpio_readl(GPIO_A, OTYPER);
248
+ uint32_t pupdr = gpio_readl(GPIO_A, PUPDR);
249
+ uint32_t idr = gpio_readl(GPIO_A, IDR);
250
+ /* 15: AF, 14: AF, 13: AF, 12: Analog ... */
251
+ /* here AF is the same as Analog and Input mode */
252
+ g_assert_cmphex(moder, ==, reset(GPIO_A, MODER));
253
+ g_assert_cmphex(odr, ==, reset(GPIO_A, ODR));
254
+ g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER));
255
+ /* 15: pull-up, 14: pull-down, 13: pull-up, 12: neither ... */
256
+ g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR));
257
+ /* 15 : 1, 14: 0, 13: 1, 12 : reset value ... */
258
+ g_assert_cmphex(idr, ==, reset(GPIO_A, IDR));
259
+
260
+ moder = gpio_readl(GPIO_B, MODER);
261
+ odr = gpio_readl(GPIO_B, ODR);
262
+ otyper = gpio_readl(GPIO_B, OTYPER);
263
+ pupdr = gpio_readl(GPIO_B, PUPDR);
264
+ idr = gpio_readl(GPIO_B, IDR);
265
+ /* ... 5: Analog, 4: AF, 3: AF, 2: Analog ... */
266
+ /* here AF is the same as Analog and Input mode */
267
+ g_assert_cmphex(moder, ==, reset(GPIO_B, MODER));
268
+ g_assert_cmphex(odr, ==, reset(GPIO_B, ODR));
269
+ g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER));
270
+ /* ... 5: neither, 4: pull-up, 3: neither ... */
271
+ g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR));
272
+ /* ... 5 : reset value, 4 : 1, 3 : reset value ... */
273
+ g_assert_cmphex(idr, ==, reset(GPIO_B, IDR));
274
+
275
+ moder = gpio_readl(GPIO_C, MODER);
276
+ odr = gpio_readl(GPIO_C, ODR);
277
+ otyper = gpio_readl(GPIO_C, OTYPER);
278
+ pupdr = gpio_readl(GPIO_C, PUPDR);
279
+ idr = gpio_readl(GPIO_C, IDR);
280
+ /* Analog, same as Input mode*/
281
+ g_assert_cmphex(moder, ==, reset(GPIO_C, MODER));
282
+ g_assert_cmphex(odr, ==, reset(GPIO_C, ODR));
283
+ g_assert_cmphex(otyper, ==, reset(GPIO_C, OTYPER));
284
+ /* no pull-up or pull-down */
285
+ g_assert_cmphex(pupdr, ==, reset(GPIO_C, PUPDR));
286
+ /* reset value */
287
+ g_assert_cmphex(idr, ==, reset(GPIO_C, IDR));
288
+
289
+ moder = gpio_readl(GPIO_H, MODER);
290
+ odr = gpio_readl(GPIO_H, ODR);
291
+ otyper = gpio_readl(GPIO_H, OTYPER);
292
+ pupdr = gpio_readl(GPIO_H, PUPDR);
293
+ idr = gpio_readl(GPIO_H, IDR);
294
+ /* Analog, same as Input mode */
295
+ g_assert_cmphex(moder, ==, reset(GPIO_H, MODER));
296
+ g_assert_cmphex(odr, ==, reset(GPIO_H, ODR));
297
+ g_assert_cmphex(otyper, ==, reset(GPIO_H, OTYPER));
298
+ /* no pull-up or pull-down */
299
+ g_assert_cmphex(pupdr, ==, reset(GPIO_H, PUPDR));
300
+ /* reset value */
301
+ g_assert_cmphex(idr, ==, reset(GPIO_H, IDR));
302
+}
303
+
304
+static void test_gpio_output_mode(const void *data)
305
+{
306
+ /*
307
+ * Checks that setting a bit in ODR sets the corresponding
308
+ * GPIO line high : it should set the right bit in IDR
309
+ * and send an irq to syscfg.
310
+ * Additionally, it checks that values written to ODR
311
+ * when not in output mode are stored and not discarded.
312
+ */
313
+ unsigned int pin = ((uint64_t)data) & 0xF;
314
+ uint32_t gpio = ((uint64_t)data) >> 32;
315
+ unsigned int gpio_id = get_gpio_id(gpio);
316
+
317
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
318
+
319
+ /* Set a bit in ODR and check nothing happens */
320
+ gpio_set_bit(gpio, ODR, pin, 1);
321
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
322
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
323
+
324
+ /* Configure the relevant line as output and check the pin is high */
325
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
326
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
327
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
328
+
329
+ /* Reset the bit in ODR and check the pin is low */
330
+ gpio_set_bit(gpio, ODR, pin, 0);
331
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
332
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
333
+
334
+ /* Clean the test */
335
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
336
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
337
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
338
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
339
+}
340
+
341
+static void test_gpio_input_mode(const void *data)
342
+{
343
+ /*
344
+ * Test that setting a line high/low externally sets the
345
+ * corresponding GPIO line high/low : it should set the
346
+ * right bit in IDR and send an irq to syscfg.
347
+ */
348
+ unsigned int pin = ((uint64_t)data) & 0xF;
349
+ uint32_t gpio = ((uint64_t)data) >> 32;
350
+ unsigned int gpio_id = get_gpio_id(gpio);
351
+
352
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
353
+
354
+ /* Configure a line as input, raise it, and check that the pin is high */
355
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
356
+ gpio_set_irq(gpio, pin, 1);
357
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
358
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
359
+
360
+ /* Lower the line and check that the pin is low */
361
+ gpio_set_irq(gpio, pin, 0);
362
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
363
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
364
+
365
+ /* Clean the test */
366
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
367
+ disconnect_all_pins(gpio);
368
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
369
+}
370
+
371
+static void test_pull_up_pull_down(const void *data)
372
+{
373
+ /*
374
+ * Test that a floating pin with pull-up sets the pin
375
+ * high and vice-versa.
376
+ */
377
+ unsigned int pin = ((uint64_t)data) & 0xF;
378
+ uint32_t gpio = ((uint64_t)data) >> 32;
379
+ unsigned int gpio_id = get_gpio_id(gpio);
380
+
381
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
382
+
383
+ /* Configure a line as input with pull-up, check the line is set high */
384
+ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
385
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLUP);
386
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) | (1 << pin));
387
+ g_assert_true(get_irq(gpio_id * NUM_GPIO_PINS + pin));
388
+
389
+ /* Configure the line with pull-down, check the line is low */
390
+ gpio_set_2bits(gpio, PUPDR, pin, PUPDR_PULLDOWN);
391
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
392
+ g_assert_false(get_irq(gpio_id * NUM_GPIO_PINS + pin));
393
+
394
+ /* Clean the test */
395
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
396
+ gpio_writel(gpio, PUPDR, reset(gpio, PUPDR));
397
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
398
+}
399
+
400
+static void test_push_pull(const void *data)
401
+{
402
+ /*
403
+ * Test that configuring a line in push-pull output mode
404
+ * disconnects the pin, that the pin can't be set or reset
405
+ * externally afterwards.
406
+ */
407
+ unsigned int pin = ((uint64_t)data) & 0xF;
408
+ uint32_t gpio = ((uint64_t)data) >> 32;
409
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
410
+
411
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
412
+
413
+ /* Setting a line high externally, configuring it in push-pull output */
414
+ /* And checking the pin was disconnected */
415
+ gpio_set_irq(gpio, pin, 1);
416
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
417
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
418
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
419
+
420
+ /* Setting a line low externally, configuring it in push-pull output */
421
+ /* And checking the pin was disconnected */
422
+ gpio_set_irq(gpio2, pin, 0);
423
+ gpio_set_bit(gpio2, ODR, pin, 1);
424
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
425
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
426
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
427
+
428
+ /* Trying to set a push-pull output pin, checking it doesn't work */
429
+ gpio_set_irq(gpio, pin, 1);
430
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
431
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
432
+
433
+ /* Trying to reset a push-pull output pin, checking it doesn't work */
434
+ gpio_set_irq(gpio2, pin, 0);
435
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF);
436
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR) | (1 << pin));
437
+
438
+ /* Clean the test */
439
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
440
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
441
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
442
+}
443
+
444
+static void test_open_drain(const void *data)
445
+{
446
+ /*
447
+ * Test that configuring a line in open-drain output mode
448
+ * disconnects a pin set high externally and that the pin
449
+ * can't be set high externally while configured in open-drain.
450
+ *
451
+ * However a pin set low externally shouldn't be disconnected,
452
+ * and it can be set low externally when in open-drain mode.
453
+ */
454
+ unsigned int pin = ((uint64_t)data) & 0xF;
455
+ uint32_t gpio = ((uint64_t)data) >> 32;
456
+ uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
457
+
458
+ qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
459
+
460
+ /* Setting a line high externally, configuring it in open-drain output */
461
+ /* And checking the pin was disconnected */
462
+ gpio_set_irq(gpio, pin, 1);
463
+ gpio_set_bit(gpio, OTYPER, pin, OTYPER_OPEN_DRAIN);
464
+ gpio_set_2bits(gpio, MODER, pin, MODER_OUTPUT);
465
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
466
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
467
+
468
+ /* Setting a line low externally, configuring it in open-drain output */
469
+ /* And checking the pin wasn't disconnected */
470
+ gpio_set_irq(gpio2, pin, 0);
471
+ gpio_set_bit(gpio2, ODR, pin, 1);
472
+ gpio_set_bit(gpio2, OTYPER, pin, OTYPER_OPEN_DRAIN);
473
+ gpio_set_2bits(gpio2, MODER, pin, MODER_OUTPUT);
474
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
475
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
476
+ reset(gpio2, IDR) & ~(1 << pin));
477
+
478
+ /* Trying to set a open-drain output pin, checking it doesn't work */
479
+ gpio_set_irq(gpio, pin, 1);
480
+ g_assert_cmphex(get_disconnected_pins(gpio), ==, 0xFFFF);
481
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR) & ~(1 << pin));
482
+
483
+ /* Trying to reset a open-drain output pin, checking it works */
484
+ gpio_set_bit(gpio, ODR, pin, 1);
485
+ gpio_set_irq(gpio, pin, 0);
486
+ g_assert_cmphex(get_disconnected_pins(gpio2), ==, 0xFFFF & ~(1 << pin));
487
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==,
488
+ reset(gpio2, IDR) & ~(1 << pin));
489
+
490
+ /* Clean the test */
491
+ disconnect_all_pins(gpio2);
492
+ gpio_writel(gpio2, OTYPER, reset(gpio2, OTYPER));
493
+ gpio_writel(gpio2, ODR, reset(gpio2, ODR));
494
+ gpio_writel(gpio2, MODER, reset(gpio2, MODER));
495
+ g_assert_cmphex(gpio_readl(gpio2, IDR), ==, reset(gpio2, IDR));
496
+ disconnect_all_pins(gpio);
497
+ gpio_writel(gpio, OTYPER, reset(gpio, OTYPER));
498
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
499
+ gpio_writel(gpio, MODER, reset(gpio, MODER));
500
+ g_assert_cmphex(gpio_readl(gpio, IDR), ==, reset(gpio, IDR));
501
+}
502
+
503
+static void test_bsrr_brr(const void *data)
504
+{
505
+ /*
506
+ * Test that writing a '1' in BSS and BSRR
507
+ * has the desired effect on ODR.
508
+ * In BSRR, BSx has priority over BRx.
509
+ */
510
+ unsigned int pin = ((uint64_t)data) & 0xF;
511
+ uint32_t gpio = ((uint64_t)data) >> 32;
512
+
513
+ gpio_writel(gpio, BSRR, (1 << pin));
514
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
515
+
516
+ gpio_writel(gpio, BSRR, (1 << (pin + NUM_GPIO_PINS)));
517
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
518
+
519
+ gpio_writel(gpio, BSRR, (1 << pin));
520
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
521
+
522
+ gpio_writel(gpio, BRR, (1 << pin));
523
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
524
+
525
+ /* BSx should have priority over BRx */
526
+ gpio_writel(gpio, BSRR, (1 << pin) | (1 << (pin + NUM_GPIO_PINS)));
527
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin));
528
+
529
+ gpio_writel(gpio, BRR, (1 << pin));
530
+ g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR));
531
+
532
+ gpio_writel(gpio, ODR, reset(gpio, ODR));
533
+}
534
+
535
+int main(int argc, char **argv)
536
+{
537
+ int ret;
538
+
539
+ g_test_init(&argc, &argv, NULL);
540
+ g_test_set_nonfatal_assertions();
541
+ qtest_add_func("stm32l4x5/gpio/test_idr_reset_value",
542
+ test_idr_reset_value);
543
+ /*
544
+ * The inputs for the tests (gpio and pin) can be changed,
545
+ * but the tests don't work for pins that are high at reset
546
+ * (GPIOA15, GPIO13 and GPIOB5).
547
+ * Specifically, rising the pin then checking `get_irq()`
548
+ * is problematic since the pin was already high.
549
+ */
550
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode",
551
+ (void *)((uint64_t)GPIO_C << 32 | 5),
552
+ test_gpio_output_mode);
553
+ qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode",
554
+ (void *)((uint64_t)GPIO_H << 32 | 3),
555
+ test_gpio_output_mode);
556
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1",
557
+ (void *)((uint64_t)GPIO_D << 32 | 6),
558
+ test_gpio_input_mode);
559
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2",
560
+ (void *)((uint64_t)GPIO_C << 32 | 10),
561
+ test_gpio_input_mode);
562
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1",
563
+ (void *)((uint64_t)GPIO_B << 32 | 5),
564
+ test_pull_up_pull_down);
565
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2",
566
+ (void *)((uint64_t)GPIO_F << 32 | 1),
567
+ test_pull_up_pull_down);
568
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1",
569
+ (void *)((uint64_t)GPIO_G << 32 | 6),
570
+ test_push_pull);
571
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2",
572
+ (void *)((uint64_t)GPIO_H << 32 | 3),
573
+ test_push_pull);
574
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1",
575
+ (void *)((uint64_t)GPIO_C << 32 | 4),
576
+ test_open_drain);
577
+ qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2",
578
+ (void *)((uint64_t)GPIO_E << 32 | 11),
579
+ test_open_drain);
580
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1",
581
+ (void *)((uint64_t)GPIO_A << 32 | 12),
582
+ test_bsrr_brr);
583
+ qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2",
584
+ (void *)((uint64_t)GPIO_D << 32 | 0),
585
+ test_bsrr_brr);
586
+
587
+ qtest_start("-machine b-l475e-iot01a");
588
+ ret = g_test_run();
589
+ qtest_end();
590
+
591
+ return ret;
592
+}
593
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
130
index XXXXXXX..XXXXXXX 100644
594
index XXXXXXX..XXXXXXX 100644
131
--- a/target/arm/meson.build
595
--- a/tests/qtest/meson.build
132
+++ b/target/arm/meson.build
596
+++ b/tests/qtest/meson.build
133
@@ -XXX,XX +XXX,XX @@
597
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
134
arm_ss = ss.source_set()
598
qtests_stm32l4x5 = \
135
arm_ss.add(files(
599
['stm32l4x5_exti-test',
136
'cpu.c',
600
'stm32l4x5_syscfg-test',
137
- 'crypto_helper.c',
601
- 'stm32l4x5_rcc-test']
138
'debug_helper.c',
602
+ 'stm32l4x5_rcc-test',
139
'gdbstub.c',
603
+ 'stm32l4x5_gpio-test']
140
'helper.c',
604
141
- 'iwmmxt_helper.c',
605
qtests_arm = \
142
- 'm_helper.c',
606
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
143
- 'mve_helper.c',
144
- 'neon_helper.c',
145
- 'op_helper.c',
146
- 'tlb_helper.c',
147
- 'vec_helper.c',
148
'vfp_helper.c',
149
'cpu_tcg.c',
150
))
151
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: fil
152
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
153
'cpu64.c',
154
'gdbstub64.c',
155
- 'helper-a64.c',
156
- 'mte_helper.c',
157
- 'pauth_helper.c',
158
- 'sve_helper.c',
159
- 'sme_helper.c',
160
))
161
162
arm_softmmu_ss = ss.source_set()
163
@@ -XXX,XX +XXX,XX @@ subdir('hvf')
164
165
if 'CONFIG_TCG' in config_all
166
subdir('tcg')
167
+else
168
+ arm_ss.add(files('tcg-stubs.c'))
169
endif
170
171
target_arch += {'arm': arm_ss}
172
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/arm/tcg/meson.build
175
+++ b/target/arm/tcg/meson.build
176
@@ -XXX,XX +XXX,XX @@ arm_ss.add(files(
177
'translate-mve.c',
178
'translate-neon.c',
179
'translate-vfp.c',
180
+ 'crypto_helper.c',
181
+ 'iwmmxt_helper.c',
182
+ 'm_helper.c',
183
+ 'mve_helper.c',
184
+ 'neon_helper.c',
185
+ 'op_helper.c',
186
+ 'tlb_helper.c',
187
+ 'vec_helper.c',
188
))
189
190
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
191
'translate-a64.c',
192
'translate-sve.c',
193
'translate-sme.c',
194
+ 'helper-a64.c',
195
+ 'mte_helper.c',
196
+ 'pauth_helper.c',
197
+ 'sme_helper.c',
198
+ 'sve_helper.c',
199
))
200
--
607
--
201
2.34.1
608
2.34.1
202
609
203
610
diff view generated by jsdifflib
[PULL 13/25] hw/gpio/max7310: Simplify max7310_realize()
[PULL 12/14] target/arm: Fix 32-bit SMOPA
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since &I2C_SLAVE(dev)->qdev == dev, no need to go back and
3
While the 8-bit input elements are sequential in the input vector,
4
forth with QOM type casting. Directly use 'dev'.
4
the 32-bit output elements are not sequential in the output matrix.
5
5
Do not attempt to compute 2 32-bit outputs at the same time.
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Cc: qemu-stable@nongnu.org
8
Message-id: 20230220115114.25237-2-philmd@linaro.org
8
Fixes: 23a5e3859f5 ("target/arm: Implement SME integer outer product")
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2083
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240305163931.242795-1-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
hw/gpio/max7310.c | 5 ++---
15
target/arm/tcg/sme_helper.c | 77 ++++++++++++++++++-------------
12
1 file changed, 2 insertions(+), 3 deletions(-)
16
tests/tcg/aarch64/sme-smopa-1.c | 47 +++++++++++++++++++
13
17
tests/tcg/aarch64/sme-smopa-2.c | 54 ++++++++++++++++++++++
14
diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c
18
tests/tcg/aarch64/Makefile.target | 2 +-
19
4 files changed, 147 insertions(+), 33 deletions(-)
20
create mode 100644 tests/tcg/aarch64/sme-smopa-1.c
21
create mode 100644 tests/tcg/aarch64/sme-smopa-2.c
22
23
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
15
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/gpio/max7310.c
25
--- a/target/arm/tcg/sme_helper.c
17
+++ b/hw/gpio/max7310.c
26
+++ b/target/arm/tcg/sme_helper.c
18
@@ -XXX,XX +XXX,XX @@ static void max7310_gpio_set(void *opaque, int line, int level)
27
@@ -XXX,XX +XXX,XX @@ void HELPER(sme_bfmopa)(void *vza, void *vzn, void *vzm, void *vpn,
19
* but also accepts sequences that are not SMBus so return an I2C device. */
28
}
20
static void max7310_realize(DeviceState *dev, Error **errp)
29
}
30
31
-typedef uint64_t IMOPFn(uint64_t, uint64_t, uint64_t, uint8_t, bool);
32
+typedef uint32_t IMOPFn32(uint32_t, uint32_t, uint32_t, uint8_t, bool);
33
+static inline void do_imopa_s(uint32_t *za, uint32_t *zn, uint32_t *zm,
34
+ uint8_t *pn, uint8_t *pm,
35
+ uint32_t desc, IMOPFn32 *fn)
36
+{
37
+ intptr_t row, col, oprsz = simd_oprsz(desc) / 4;
38
+ bool neg = simd_data(desc);
39
40
-static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
41
- uint8_t *pn, uint8_t *pm,
42
- uint32_t desc, IMOPFn *fn)
43
+ for (row = 0; row < oprsz; ++row) {
44
+ uint8_t pa = (pn[H1(row >> 1)] >> ((row & 1) * 4)) & 0xf;
45
+ uint32_t *za_row = &za[tile_vslice_index(row)];
46
+ uint32_t n = zn[H4(row)];
47
+
48
+ for (col = 0; col < oprsz; ++col) {
49
+ uint8_t pb = pm[H1(col >> 1)] >> ((col & 1) * 4);
50
+ uint32_t *a = &za_row[H4(col)];
51
+
52
+ *a = fn(n, zm[H4(col)], *a, pa & pb, neg);
53
+ }
54
+ }
55
+}
56
+
57
+typedef uint64_t IMOPFn64(uint64_t, uint64_t, uint64_t, uint8_t, bool);
58
+static inline void do_imopa_d(uint64_t *za, uint64_t *zn, uint64_t *zm,
59
+ uint8_t *pn, uint8_t *pm,
60
+ uint32_t desc, IMOPFn64 *fn)
21
{
61
{
22
- I2CSlave *i2c = I2C_SLAVE(dev);
62
intptr_t row, col, oprsz = simd_oprsz(desc) / 8;
23
MAX7310State *s = MAX7310(dev);
63
bool neg = simd_data(desc);
24
64
@@ -XXX,XX +XXX,XX @@ static inline void do_imopa(uint64_t *za, uint64_t *zn, uint64_t *zm,
25
- qdev_init_gpio_in(&i2c->qdev, max7310_gpio_set, 8);
26
- qdev_init_gpio_out(&i2c->qdev, s->handler, 8);
27
+ qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler));
28
+ qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler));
29
}
65
}
30
66
31
static void max7310_class_init(ObjectClass *klass, void *data)
67
#define DEF_IMOP_32(NAME, NTYPE, MTYPE) \
68
-static uint64_t NAME(uint64_t n, uint64_t m, uint64_t a, uint8_t p, bool neg) \
69
+static uint32_t NAME(uint32_t n, uint32_t m, uint32_t a, uint8_t p, bool neg) \
70
{ \
71
- uint32_t sum0 = 0, sum1 = 0; \
72
+ uint32_t sum = 0; \
73
/* Apply P to N as a mask, making the inactive elements 0. */ \
74
n &= expand_pred_b(p); \
75
- sum0 += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
76
- sum0 += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
77
- sum0 += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
78
- sum0 += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
79
- sum1 += (NTYPE)(n >> 32) * (MTYPE)(m >> 32); \
80
- sum1 += (NTYPE)(n >> 40) * (MTYPE)(m >> 40); \
81
- sum1 += (NTYPE)(n >> 48) * (MTYPE)(m >> 48); \
82
- sum1 += (NTYPE)(n >> 56) * (MTYPE)(m >> 56); \
83
- if (neg) { \
84
- sum0 = (uint32_t)a - sum0, sum1 = (uint32_t)(a >> 32) - sum1; \
85
- } else { \
86
- sum0 = (uint32_t)a + sum0, sum1 = (uint32_t)(a >> 32) + sum1; \
87
- } \
88
- return ((uint64_t)sum1 << 32) | sum0; \
89
+ sum += (NTYPE)(n >> 0) * (MTYPE)(m >> 0); \
90
+ sum += (NTYPE)(n >> 8) * (MTYPE)(m >> 8); \
91
+ sum += (NTYPE)(n >> 16) * (MTYPE)(m >> 16); \
92
+ sum += (NTYPE)(n >> 24) * (MTYPE)(m >> 24); \
93
+ return neg ? a - sum : a + sum; \
94
}
95
96
#define DEF_IMOP_64(NAME, NTYPE, MTYPE) \
97
@@ -XXX,XX +XXX,XX @@ DEF_IMOP_64(umopa_d, uint16_t, uint16_t)
98
DEF_IMOP_64(sumopa_d, int16_t, uint16_t)
99
DEF_IMOP_64(usmopa_d, uint16_t, int16_t)
100
101
-#define DEF_IMOPH(NAME) \
102
- void HELPER(sme_##NAME)(void *vza, void *vzn, void *vzm, void *vpn, \
103
- void *vpm, uint32_t desc) \
104
- { do_imopa(vza, vzn, vzm, vpn, vpm, desc, NAME); }
105
+#define DEF_IMOPH(NAME, S) \
106
+ void HELPER(sme_##NAME##_##S)(void *vza, void *vzn, void *vzm, \
107
+ void *vpn, void *vpm, uint32_t desc) \
108
+ { do_imopa_##S(vza, vzn, vzm, vpn, vpm, desc, NAME##_##S); }
109
110
-DEF_IMOPH(smopa_s)
111
-DEF_IMOPH(umopa_s)
112
-DEF_IMOPH(sumopa_s)
113
-DEF_IMOPH(usmopa_s)
114
-DEF_IMOPH(smopa_d)
115
-DEF_IMOPH(umopa_d)
116
-DEF_IMOPH(sumopa_d)
117
-DEF_IMOPH(usmopa_d)
118
+DEF_IMOPH(smopa, s)
119
+DEF_IMOPH(umopa, s)
120
+DEF_IMOPH(sumopa, s)
121
+DEF_IMOPH(usmopa, s)
122
+
123
+DEF_IMOPH(smopa, d)
124
+DEF_IMOPH(umopa, d)
125
+DEF_IMOPH(sumopa, d)
126
+DEF_IMOPH(usmopa, d)
127
diff --git a/tests/tcg/aarch64/sme-smopa-1.c b/tests/tcg/aarch64/sme-smopa-1.c
128
new file mode 100644
129
index XXXXXXX..XXXXXXX
130
--- /dev/null
131
+++ b/tests/tcg/aarch64/sme-smopa-1.c
132
@@ -XXX,XX +XXX,XX @@
133
+#include <stdio.h>
134
+#include <string.h>
135
+
136
+int main()
137
+{
138
+ static const int cmp[4][4] = {
139
+ { 110, 134, 158, 182 },
140
+ { 390, 478, 566, 654 },
141
+ { 670, 822, 974, 1126 },
142
+ { 950, 1166, 1382, 1598 }
143
+ };
144
+ int dst[4][4];
145
+ int *tmp = &dst[0][0];
146
+
147
+ asm volatile(
148
+ ".arch armv8-r+sme\n\t"
149
+ "smstart\n\t"
150
+ "index z0.b, #0, #1\n\t"
151
+ "movprfx z1, z0\n\t"
152
+ "add z1.b, z1.b, #16\n\t"
153
+ "ptrue p0.b\n\t"
154
+ "smopa za0.s, p0/m, p0/m, z0.b, z1.b\n\t"
155
+ "ptrue p0.s, vl4\n\t"
156
+ "mov w12, #0\n\t"
157
+ "st1w { za0h.s[w12, #0] }, p0, [%0]\n\t"
158
+ "add %0, %0, #16\n\t"
159
+ "st1w { za0h.s[w12, #1] }, p0, [%0]\n\t"
160
+ "add %0, %0, #16\n\t"
161
+ "st1w { za0h.s[w12, #2] }, p0, [%0]\n\t"
162
+ "add %0, %0, #16\n\t"
163
+ "st1w { za0h.s[w12, #3] }, p0, [%0]\n\t"
164
+ "smstop"
165
+ : "+r"(tmp) : : "memory");
166
+
167
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
168
+ return 0;
169
+ }
170
+
171
+ /* See above for correct results. */
172
+ for (int i = 0; i < 4; ++i) {
173
+ for (int j = 0; j < 4; ++j) {
174
+ printf("%6d", dst[i][j]);
175
+ }
176
+ printf("\n");
177
+ }
178
+ return 1;
179
+}
180
diff --git a/tests/tcg/aarch64/sme-smopa-2.c b/tests/tcg/aarch64/sme-smopa-2.c
181
new file mode 100644
182
index XXXXXXX..XXXXXXX
183
--- /dev/null
184
+++ b/tests/tcg/aarch64/sme-smopa-2.c
185
@@ -XXX,XX +XXX,XX @@
186
+#include <stdio.h>
187
+#include <string.h>
188
+
189
+int main()
190
+{
191
+ static const long cmp[4][4] = {
192
+ { 110, 134, 158, 182 },
193
+ { 390, 478, 566, 654 },
194
+ { 670, 822, 974, 1126 },
195
+ { 950, 1166, 1382, 1598 }
196
+ };
197
+ long dst[4][4];
198
+ long *tmp = &dst[0][0];
199
+ long svl;
200
+
201
+ /* Validate that we have a wide enough vector for 4 elements. */
202
+ asm(".arch armv8-r+sme-i64\n\trdsvl %0, #1" : "=r"(svl));
203
+ if (svl < 32) {
204
+ return 0;
205
+ }
206
+
207
+ asm volatile(
208
+ "smstart\n\t"
209
+ "index z0.h, #0, #1\n\t"
210
+ "movprfx z1, z0\n\t"
211
+ "add z1.h, z1.h, #16\n\t"
212
+ "ptrue p0.b\n\t"
213
+ "smopa za0.d, p0/m, p0/m, z0.h, z1.h\n\t"
214
+ "ptrue p0.d, vl4\n\t"
215
+ "mov w12, #0\n\t"
216
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
217
+ "add %0, %0, #32\n\t"
218
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
219
+ "mov w12, #2\n\t"
220
+ "add %0, %0, #32\n\t"
221
+ "st1d { za0h.d[w12, #0] }, p0, [%0]\n\t"
222
+ "add %0, %0, #32\n\t"
223
+ "st1d { za0h.d[w12, #1] }, p0, [%0]\n\t"
224
+ "smstop"
225
+ : "+r"(tmp) : : "memory");
226
+
227
+ if (memcmp(cmp, dst, sizeof(dst)) == 0) {
228
+ return 0;
229
+ }
230
+
231
+ /* See above for correct results. */
232
+ for (int i = 0; i < 4; ++i) {
233
+ for (int j = 0; j < 4; ++j) {
234
+ printf("%6ld", dst[i][j]);
235
+ }
236
+ printf("\n");
237
+ }
238
+ return 1;
239
+}
240
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
241
index XXXXXXX..XXXXXXX 100644
242
--- a/tests/tcg/aarch64/Makefile.target
243
+++ b/tests/tcg/aarch64/Makefile.target
244
@@ -XXX,XX +XXX,XX @@ endif
245
246
# SME Tests
247
ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
248
-AARCH64_TESTS += sme-outprod1
249
+AARCH64_TESTS += sme-outprod1 sme-smopa-1 sme-smopa-2
250
endif
251
252
# System Registers Tests
32
--
253
--
33
2.34.1
254
2.34.1
34
255
35
256
diff view generated by jsdifflib
[PULL 21/25] hw/arm/musicpal: Remove unused dummy MemoryRegion
[PULL 13/14] hw/rtc/sun4v-rtc: Relicense to GPLv2-or-later
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
2
was unfortunately added with a license of GPL-v3-or-later, which is
3
not compatible with other QEMU code which has a GPL-v2-only license.
2
4
5
Relicense the code in the .c and the .h file to GPL-v2-or-later,
6
to make it compatible with the rest of QEMU.
7
8
Cc: qemu-stable@nongnu.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Paolo Bonzini (for Red Hat) <pbonzini@redhat.com>
11
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
12
Signed-off-by: Markus Armbruster <armbru@redhat.com>
13
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
16
Acked-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20240223161300.938542-1-peter.maydell@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
19
---
7
hw/arm/musicpal.c | 4 ----
20
include/hw/rtc/sun4v-rtc.h | 2 +-
8
1 file changed, 4 deletions(-)
21
hw/rtc/sun4v-rtc.c | 2 +-
22
2 files changed, 2 insertions(+), 2 deletions(-)
9
23
10
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
24
diff --git a/include/hw/rtc/sun4v-rtc.h b/include/hw/rtc/sun4v-rtc.h
11
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
12
--- a/hw/arm/musicpal.c
26
--- a/include/hw/rtc/sun4v-rtc.h
13
+++ b/hw/arm/musicpal.c
27
+++ b/include/hw/rtc/sun4v-rtc.h
14
@@ -XXX,XX +XXX,XX @@ struct musicpal_key_state {
28
@@ -XXX,XX +XXX,XX @@
15
SysBusDevice parent_obj;
29
*
16
/*< public >*/
30
* Copyright (c) 2016 Artyom Tarasenko
17
31
*
18
- MemoryRegion iomem;
32
- * This code is licensed under the GNU GPL v3 or (at your option) any later
19
uint32_t kbd_extended;
33
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
20
uint32_t pressed_keys;
34
* version.
21
qemu_irq out[8];
35
*/
22
@@ -XXX,XX +XXX,XX @@ static void musicpal_key_init(Object *obj)
36
23
DeviceState *dev = DEVICE(sbd);
37
diff --git a/hw/rtc/sun4v-rtc.c b/hw/rtc/sun4v-rtc.c
24
musicpal_key_state *s = MUSICPAL_KEY(dev);
38
index XXXXXXX..XXXXXXX 100644
25
39
--- a/hw/rtc/sun4v-rtc.c
26
- memory_region_init(&s->iomem, obj, "dummy", 0);
40
+++ b/hw/rtc/sun4v-rtc.c
27
- sysbus_init_mmio(sbd, &s->iomem);
41
@@ -XXX,XX +XXX,XX @@
28
-
42
*
29
s->kbd_extended = 0;
43
* Copyright (c) 2016 Artyom Tarasenko
30
s->pressed_keys = 0;
44
*
45
- * This code is licensed under the GNU GPL v3 or (at your option) any later
46
+ * This code is licensed under the GNU GPL v2 or (at your option) any later
47
* version.
48
*/
31
49
32
--
50
--
33
2.34.1
51
2.34.1
34
52
35
53
diff view generated by jsdifflib
[PULL 06/25] target/arm: Move psci.c into the tcg directory
[PULL 14/14] target/arm: Move v7m-related code from cpu32.c into a separate file
1
From: Claudio Fontana <cfontana@suse.de>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
3
Move the code to a separate file so that we do not have to compile
4
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
it anymore if CONFIG_ARM_V7M is not set.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20240308141051.536599-2-thuth@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/{ => tcg}/psci.c | 0
11
target/arm/tcg/cpu-v7m.c | 290 +++++++++++++++++++++++++++++++++++++
11
target/arm/meson.build | 1 -
12
target/arm/tcg/cpu32.c | 261 ---------------------------------
12
target/arm/tcg/meson.build | 4 ++++
13
target/arm/meson.build | 3 +
13
3 files changed, 4 insertions(+), 1 deletion(-)
14
target/arm/tcg/meson.build | 3 +
14
rename target/arm/{ => tcg}/psci.c (100%)
15
4 files changed, 296 insertions(+), 261 deletions(-)
16
create mode 100644 target/arm/tcg/cpu-v7m.c
15
17
16
diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c
18
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
17
similarity index 100%
19
new file mode 100644
18
rename from target/arm/psci.c
20
index XXXXXXX..XXXXXXX
19
rename to target/arm/tcg/psci.c
21
--- /dev/null
22
+++ b/target/arm/tcg/cpu-v7m.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QEMU ARMv7-M TCG-only CPUs.
26
+ *
27
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
28
+ *
29
+ * This code is licensed under the GNU GPL v2 or later.
30
+ *
31
+ * SPDX-License-Identifier: GPL-2.0-or-later
32
+ */
33
+
34
+#include "qemu/osdep.h"
35
+#include "cpu.h"
36
+#include "hw/core/tcg-cpu-ops.h"
37
+#include "internals.h"
38
+
39
+#if !defined(CONFIG_USER_ONLY)
40
+
41
+#include "hw/intc/armv7m_nvic.h"
42
+
43
+static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
44
+{
45
+ CPUClass *cc = CPU_GET_CLASS(cs);
46
+ ARMCPU *cpu = ARM_CPU(cs);
47
+ CPUARMState *env = &cpu->env;
48
+ bool ret = false;
49
+
50
+ /*
51
+ * ARMv7-M interrupt masking works differently than -A or -R.
52
+ * There is no FIQ/IRQ distinction. Instead of I and F bits
53
+ * masking FIQ and IRQ interrupts, an exception is taken only
54
+ * if it is higher priority than the current execution priority
55
+ * (which depends on state like BASEPRI, FAULTMASK and the
56
+ * currently active exception).
57
+ */
58
+ if (interrupt_request & CPU_INTERRUPT_HARD
59
+ && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
60
+ cs->exception_index = EXCP_IRQ;
61
+ cc->tcg_ops->do_interrupt(cs);
62
+ ret = true;
63
+ }
64
+ return ret;
65
+}
66
+
67
+#endif /* !CONFIG_USER_ONLY */
68
+
69
+static void cortex_m0_initfn(Object *obj)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
72
+ set_feature(&cpu->env, ARM_FEATURE_V6);
73
+ set_feature(&cpu->env, ARM_FEATURE_M);
74
+
75
+ cpu->midr = 0x410cc200;
76
+
77
+ /*
78
+ * These ID register values are not guest visible, because
79
+ * we do not implement the Main Extension. They must be set
80
+ * to values corresponding to the Cortex-M0's implemented
81
+ * features, because QEMU generally controls its emulation
82
+ * by looking at ID register fields. We use the same values as
83
+ * for the M3.
84
+ */
85
+ cpu->isar.id_pfr0 = 0x00000030;
86
+ cpu->isar.id_pfr1 = 0x00000200;
87
+ cpu->isar.id_dfr0 = 0x00100000;
88
+ cpu->id_afr0 = 0x00000000;
89
+ cpu->isar.id_mmfr0 = 0x00000030;
90
+ cpu->isar.id_mmfr1 = 0x00000000;
91
+ cpu->isar.id_mmfr2 = 0x00000000;
92
+ cpu->isar.id_mmfr3 = 0x00000000;
93
+ cpu->isar.id_isar0 = 0x01141110;
94
+ cpu->isar.id_isar1 = 0x02111000;
95
+ cpu->isar.id_isar2 = 0x21112231;
96
+ cpu->isar.id_isar3 = 0x01111110;
97
+ cpu->isar.id_isar4 = 0x01310102;
98
+ cpu->isar.id_isar5 = 0x00000000;
99
+ cpu->isar.id_isar6 = 0x00000000;
100
+}
101
+
102
+static void cortex_m3_initfn(Object *obj)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ set_feature(&cpu->env, ARM_FEATURE_V7);
106
+ set_feature(&cpu->env, ARM_FEATURE_M);
107
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
108
+ cpu->midr = 0x410fc231;
109
+ cpu->pmsav7_dregion = 8;
110
+ cpu->isar.id_pfr0 = 0x00000030;
111
+ cpu->isar.id_pfr1 = 0x00000200;
112
+ cpu->isar.id_dfr0 = 0x00100000;
113
+ cpu->id_afr0 = 0x00000000;
114
+ cpu->isar.id_mmfr0 = 0x00000030;
115
+ cpu->isar.id_mmfr1 = 0x00000000;
116
+ cpu->isar.id_mmfr2 = 0x00000000;
117
+ cpu->isar.id_mmfr3 = 0x00000000;
118
+ cpu->isar.id_isar0 = 0x01141110;
119
+ cpu->isar.id_isar1 = 0x02111000;
120
+ cpu->isar.id_isar2 = 0x21112231;
121
+ cpu->isar.id_isar3 = 0x01111110;
122
+ cpu->isar.id_isar4 = 0x01310102;
123
+ cpu->isar.id_isar5 = 0x00000000;
124
+ cpu->isar.id_isar6 = 0x00000000;
125
+}
126
+
127
+static void cortex_m4_initfn(Object *obj)
128
+{
129
+ ARMCPU *cpu = ARM_CPU(obj);
130
+
131
+ set_feature(&cpu->env, ARM_FEATURE_V7);
132
+ set_feature(&cpu->env, ARM_FEATURE_M);
133
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
134
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
135
+ cpu->midr = 0x410fc240; /* r0p0 */
136
+ cpu->pmsav7_dregion = 8;
137
+ cpu->isar.mvfr0 = 0x10110021;
138
+ cpu->isar.mvfr1 = 0x11000011;
139
+ cpu->isar.mvfr2 = 0x00000000;
140
+ cpu->isar.id_pfr0 = 0x00000030;
141
+ cpu->isar.id_pfr1 = 0x00000200;
142
+ cpu->isar.id_dfr0 = 0x00100000;
143
+ cpu->id_afr0 = 0x00000000;
144
+ cpu->isar.id_mmfr0 = 0x00000030;
145
+ cpu->isar.id_mmfr1 = 0x00000000;
146
+ cpu->isar.id_mmfr2 = 0x00000000;
147
+ cpu->isar.id_mmfr3 = 0x00000000;
148
+ cpu->isar.id_isar0 = 0x01141110;
149
+ cpu->isar.id_isar1 = 0x02111000;
150
+ cpu->isar.id_isar2 = 0x21112231;
151
+ cpu->isar.id_isar3 = 0x01111110;
152
+ cpu->isar.id_isar4 = 0x01310102;
153
+ cpu->isar.id_isar5 = 0x00000000;
154
+ cpu->isar.id_isar6 = 0x00000000;
155
+}
156
+
157
+static void cortex_m7_initfn(Object *obj)
158
+{
159
+ ARMCPU *cpu = ARM_CPU(obj);
160
+
161
+ set_feature(&cpu->env, ARM_FEATURE_V7);
162
+ set_feature(&cpu->env, ARM_FEATURE_M);
163
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
164
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
165
+ cpu->midr = 0x411fc272; /* r1p2 */
166
+ cpu->pmsav7_dregion = 8;
167
+ cpu->isar.mvfr0 = 0x10110221;
168
+ cpu->isar.mvfr1 = 0x12000011;
169
+ cpu->isar.mvfr2 = 0x00000040;
170
+ cpu->isar.id_pfr0 = 0x00000030;
171
+ cpu->isar.id_pfr1 = 0x00000200;
172
+ cpu->isar.id_dfr0 = 0x00100000;
173
+ cpu->id_afr0 = 0x00000000;
174
+ cpu->isar.id_mmfr0 = 0x00100030;
175
+ cpu->isar.id_mmfr1 = 0x00000000;
176
+ cpu->isar.id_mmfr2 = 0x01000000;
177
+ cpu->isar.id_mmfr3 = 0x00000000;
178
+ cpu->isar.id_isar0 = 0x01101110;
179
+ cpu->isar.id_isar1 = 0x02112000;
180
+ cpu->isar.id_isar2 = 0x20232231;
181
+ cpu->isar.id_isar3 = 0x01111131;
182
+ cpu->isar.id_isar4 = 0x01310132;
183
+ cpu->isar.id_isar5 = 0x00000000;
184
+ cpu->isar.id_isar6 = 0x00000000;
185
+}
186
+
187
+static void cortex_m33_initfn(Object *obj)
188
+{
189
+ ARMCPU *cpu = ARM_CPU(obj);
190
+
191
+ set_feature(&cpu->env, ARM_FEATURE_V8);
192
+ set_feature(&cpu->env, ARM_FEATURE_M);
193
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
194
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
195
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
196
+ cpu->midr = 0x410fd213; /* r0p3 */
197
+ cpu->pmsav7_dregion = 16;
198
+ cpu->sau_sregion = 8;
199
+ cpu->isar.mvfr0 = 0x10110021;
200
+ cpu->isar.mvfr1 = 0x11000011;
201
+ cpu->isar.mvfr2 = 0x00000040;
202
+ cpu->isar.id_pfr0 = 0x00000030;
203
+ cpu->isar.id_pfr1 = 0x00000210;
204
+ cpu->isar.id_dfr0 = 0x00200000;
205
+ cpu->id_afr0 = 0x00000000;
206
+ cpu->isar.id_mmfr0 = 0x00101F40;
207
+ cpu->isar.id_mmfr1 = 0x00000000;
208
+ cpu->isar.id_mmfr2 = 0x01000000;
209
+ cpu->isar.id_mmfr3 = 0x00000000;
210
+ cpu->isar.id_isar0 = 0x01101110;
211
+ cpu->isar.id_isar1 = 0x02212000;
212
+ cpu->isar.id_isar2 = 0x20232232;
213
+ cpu->isar.id_isar3 = 0x01111131;
214
+ cpu->isar.id_isar4 = 0x01310132;
215
+ cpu->isar.id_isar5 = 0x00000000;
216
+ cpu->isar.id_isar6 = 0x00000000;
217
+ cpu->clidr = 0x00000000;
218
+ cpu->ctr = 0x8000c000;
219
+}
220
+
221
+static void cortex_m55_initfn(Object *obj)
222
+{
223
+ ARMCPU *cpu = ARM_CPU(obj);
224
+
225
+ set_feature(&cpu->env, ARM_FEATURE_V8);
226
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
227
+ set_feature(&cpu->env, ARM_FEATURE_M);
228
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
229
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
230
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
231
+ cpu->midr = 0x410fd221; /* r0p1 */
232
+ cpu->revidr = 0;
233
+ cpu->pmsav7_dregion = 16;
234
+ cpu->sau_sregion = 8;
235
+ /* These are the MVFR* values for the FPU + full MVE configuration */
236
+ cpu->isar.mvfr0 = 0x10110221;
237
+ cpu->isar.mvfr1 = 0x12100211;
238
+ cpu->isar.mvfr2 = 0x00000040;
239
+ cpu->isar.id_pfr0 = 0x20000030;
240
+ cpu->isar.id_pfr1 = 0x00000230;
241
+ cpu->isar.id_dfr0 = 0x10200000;
242
+ cpu->id_afr0 = 0x00000000;
243
+ cpu->isar.id_mmfr0 = 0x00111040;
244
+ cpu->isar.id_mmfr1 = 0x00000000;
245
+ cpu->isar.id_mmfr2 = 0x01000000;
246
+ cpu->isar.id_mmfr3 = 0x00000011;
247
+ cpu->isar.id_isar0 = 0x01103110;
248
+ cpu->isar.id_isar1 = 0x02212000;
249
+ cpu->isar.id_isar2 = 0x20232232;
250
+ cpu->isar.id_isar3 = 0x01111131;
251
+ cpu->isar.id_isar4 = 0x01310132;
252
+ cpu->isar.id_isar5 = 0x00000000;
253
+ cpu->isar.id_isar6 = 0x00000000;
254
+ cpu->clidr = 0x00000000; /* caches not implemented */
255
+ cpu->ctr = 0x8303c003;
256
+}
257
+
258
+static const TCGCPUOps arm_v7m_tcg_ops = {
259
+ .initialize = arm_translate_init,
260
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
261
+ .debug_excp_handler = arm_debug_excp_handler,
262
+ .restore_state_to_opc = arm_restore_state_to_opc,
263
+
264
+#ifdef CONFIG_USER_ONLY
265
+ .record_sigsegv = arm_cpu_record_sigsegv,
266
+ .record_sigbus = arm_cpu_record_sigbus,
267
+#else
268
+ .tlb_fill = arm_cpu_tlb_fill,
269
+ .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
270
+ .do_interrupt = arm_v7m_cpu_do_interrupt,
271
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
272
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
273
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
274
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
275
+ .debug_check_breakpoint = arm_debug_check_breakpoint,
276
+#endif /* !CONFIG_USER_ONLY */
277
+};
278
+
279
+static void arm_v7m_class_init(ObjectClass *oc, void *data)
280
+{
281
+ ARMCPUClass *acc = ARM_CPU_CLASS(oc);
282
+ CPUClass *cc = CPU_CLASS(oc);
283
+
284
+ acc->info = data;
285
+ cc->tcg_ops = &arm_v7m_tcg_ops;
286
+ cc->gdb_core_xml_file = "arm-m-profile.xml";
287
+}
288
+
289
+static const ARMCPUInfo arm_v7m_cpus[] = {
290
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
291
+ .class_init = arm_v7m_class_init },
292
+ { .name = "cortex-m3", .initfn = cortex_m3_initfn,
293
+ .class_init = arm_v7m_class_init },
294
+ { .name = "cortex-m4", .initfn = cortex_m4_initfn,
295
+ .class_init = arm_v7m_class_init },
296
+ { .name = "cortex-m7", .initfn = cortex_m7_initfn,
297
+ .class_init = arm_v7m_class_init },
298
+ { .name = "cortex-m33", .initfn = cortex_m33_initfn,
299
+ .class_init = arm_v7m_class_init },
300
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
301
+ .class_init = arm_v7m_class_init },
302
+};
303
+
304
+static void arm_v7m_cpu_register_types(void)
305
+{
306
+ size_t i;
307
+
308
+ for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
309
+ arm_cpu_register(&arm_v7m_cpus[i]);
310
+ }
311
+}
312
+
313
+type_init(arm_v7m_cpu_register_types)
314
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
315
index XXXXXXX..XXXXXXX 100644
316
--- a/target/arm/tcg/cpu32.c
317
+++ b/target/arm/tcg/cpu32.c
318
@@ -XXX,XX +XXX,XX @@
319
#include "hw/boards.h"
320
#endif
321
#include "cpregs.h"
322
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
323
-#include "hw/intc/armv7m_nvic.h"
324
-#endif
325
326
327
/* Share AArch32 -cpu max features with AArch64. */
328
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
329
/* CPU models. These are not needed for the AArch64 linux-user build. */
330
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
331
332
-#if !defined(CONFIG_USER_ONLY)
333
-static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
334
-{
335
- CPUClass *cc = CPU_GET_CLASS(cs);
336
- ARMCPU *cpu = ARM_CPU(cs);
337
- CPUARMState *env = &cpu->env;
338
- bool ret = false;
339
-
340
- /*
341
- * ARMv7-M interrupt masking works differently than -A or -R.
342
- * There is no FIQ/IRQ distinction. Instead of I and F bits
343
- * masking FIQ and IRQ interrupts, an exception is taken only
344
- * if it is higher priority than the current execution priority
345
- * (which depends on state like BASEPRI, FAULTMASK and the
346
- * currently active exception).
347
- */
348
- if (interrupt_request & CPU_INTERRUPT_HARD
349
- && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
350
- cs->exception_index = EXCP_IRQ;
351
- cc->tcg_ops->do_interrupt(cs);
352
- ret = true;
353
- }
354
- return ret;
355
-}
356
-#endif /* !CONFIG_USER_ONLY */
357
-
358
static void arm926_initfn(Object *obj)
359
{
360
ARMCPU *cpu = ARM_CPU(obj);
361
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
362
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
363
}
364
365
-static void cortex_m0_initfn(Object *obj)
366
-{
367
- ARMCPU *cpu = ARM_CPU(obj);
368
- set_feature(&cpu->env, ARM_FEATURE_V6);
369
- set_feature(&cpu->env, ARM_FEATURE_M);
370
-
371
- cpu->midr = 0x410cc200;
372
-
373
- /*
374
- * These ID register values are not guest visible, because
375
- * we do not implement the Main Extension. They must be set
376
- * to values corresponding to the Cortex-M0's implemented
377
- * features, because QEMU generally controls its emulation
378
- * by looking at ID register fields. We use the same values as
379
- * for the M3.
380
- */
381
- cpu->isar.id_pfr0 = 0x00000030;
382
- cpu->isar.id_pfr1 = 0x00000200;
383
- cpu->isar.id_dfr0 = 0x00100000;
384
- cpu->id_afr0 = 0x00000000;
385
- cpu->isar.id_mmfr0 = 0x00000030;
386
- cpu->isar.id_mmfr1 = 0x00000000;
387
- cpu->isar.id_mmfr2 = 0x00000000;
388
- cpu->isar.id_mmfr3 = 0x00000000;
389
- cpu->isar.id_isar0 = 0x01141110;
390
- cpu->isar.id_isar1 = 0x02111000;
391
- cpu->isar.id_isar2 = 0x21112231;
392
- cpu->isar.id_isar3 = 0x01111110;
393
- cpu->isar.id_isar4 = 0x01310102;
394
- cpu->isar.id_isar5 = 0x00000000;
395
- cpu->isar.id_isar6 = 0x00000000;
396
-}
397
-
398
-static void cortex_m3_initfn(Object *obj)
399
-{
400
- ARMCPU *cpu = ARM_CPU(obj);
401
- set_feature(&cpu->env, ARM_FEATURE_V7);
402
- set_feature(&cpu->env, ARM_FEATURE_M);
403
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
404
- cpu->midr = 0x410fc231;
405
- cpu->pmsav7_dregion = 8;
406
- cpu->isar.id_pfr0 = 0x00000030;
407
- cpu->isar.id_pfr1 = 0x00000200;
408
- cpu->isar.id_dfr0 = 0x00100000;
409
- cpu->id_afr0 = 0x00000000;
410
- cpu->isar.id_mmfr0 = 0x00000030;
411
- cpu->isar.id_mmfr1 = 0x00000000;
412
- cpu->isar.id_mmfr2 = 0x00000000;
413
- cpu->isar.id_mmfr3 = 0x00000000;
414
- cpu->isar.id_isar0 = 0x01141110;
415
- cpu->isar.id_isar1 = 0x02111000;
416
- cpu->isar.id_isar2 = 0x21112231;
417
- cpu->isar.id_isar3 = 0x01111110;
418
- cpu->isar.id_isar4 = 0x01310102;
419
- cpu->isar.id_isar5 = 0x00000000;
420
- cpu->isar.id_isar6 = 0x00000000;
421
-}
422
-
423
-static void cortex_m4_initfn(Object *obj)
424
-{
425
- ARMCPU *cpu = ARM_CPU(obj);
426
-
427
- set_feature(&cpu->env, ARM_FEATURE_V7);
428
- set_feature(&cpu->env, ARM_FEATURE_M);
429
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
430
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
431
- cpu->midr = 0x410fc240; /* r0p0 */
432
- cpu->pmsav7_dregion = 8;
433
- cpu->isar.mvfr0 = 0x10110021;
434
- cpu->isar.mvfr1 = 0x11000011;
435
- cpu->isar.mvfr2 = 0x00000000;
436
- cpu->isar.id_pfr0 = 0x00000030;
437
- cpu->isar.id_pfr1 = 0x00000200;
438
- cpu->isar.id_dfr0 = 0x00100000;
439
- cpu->id_afr0 = 0x00000000;
440
- cpu->isar.id_mmfr0 = 0x00000030;
441
- cpu->isar.id_mmfr1 = 0x00000000;
442
- cpu->isar.id_mmfr2 = 0x00000000;
443
- cpu->isar.id_mmfr3 = 0x00000000;
444
- cpu->isar.id_isar0 = 0x01141110;
445
- cpu->isar.id_isar1 = 0x02111000;
446
- cpu->isar.id_isar2 = 0x21112231;
447
- cpu->isar.id_isar3 = 0x01111110;
448
- cpu->isar.id_isar4 = 0x01310102;
449
- cpu->isar.id_isar5 = 0x00000000;
450
- cpu->isar.id_isar6 = 0x00000000;
451
-}
452
-
453
-static void cortex_m7_initfn(Object *obj)
454
-{
455
- ARMCPU *cpu = ARM_CPU(obj);
456
-
457
- set_feature(&cpu->env, ARM_FEATURE_V7);
458
- set_feature(&cpu->env, ARM_FEATURE_M);
459
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
460
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
461
- cpu->midr = 0x411fc272; /* r1p2 */
462
- cpu->pmsav7_dregion = 8;
463
- cpu->isar.mvfr0 = 0x10110221;
464
- cpu->isar.mvfr1 = 0x12000011;
465
- cpu->isar.mvfr2 = 0x00000040;
466
- cpu->isar.id_pfr0 = 0x00000030;
467
- cpu->isar.id_pfr1 = 0x00000200;
468
- cpu->isar.id_dfr0 = 0x00100000;
469
- cpu->id_afr0 = 0x00000000;
470
- cpu->isar.id_mmfr0 = 0x00100030;
471
- cpu->isar.id_mmfr1 = 0x00000000;
472
- cpu->isar.id_mmfr2 = 0x01000000;
473
- cpu->isar.id_mmfr3 = 0x00000000;
474
- cpu->isar.id_isar0 = 0x01101110;
475
- cpu->isar.id_isar1 = 0x02112000;
476
- cpu->isar.id_isar2 = 0x20232231;
477
- cpu->isar.id_isar3 = 0x01111131;
478
- cpu->isar.id_isar4 = 0x01310132;
479
- cpu->isar.id_isar5 = 0x00000000;
480
- cpu->isar.id_isar6 = 0x00000000;
481
-}
482
-
483
-static void cortex_m33_initfn(Object *obj)
484
-{
485
- ARMCPU *cpu = ARM_CPU(obj);
486
-
487
- set_feature(&cpu->env, ARM_FEATURE_V8);
488
- set_feature(&cpu->env, ARM_FEATURE_M);
489
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
490
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
491
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
492
- cpu->midr = 0x410fd213; /* r0p3 */
493
- cpu->pmsav7_dregion = 16;
494
- cpu->sau_sregion = 8;
495
- cpu->isar.mvfr0 = 0x10110021;
496
- cpu->isar.mvfr1 = 0x11000011;
497
- cpu->isar.mvfr2 = 0x00000040;
498
- cpu->isar.id_pfr0 = 0x00000030;
499
- cpu->isar.id_pfr1 = 0x00000210;
500
- cpu->isar.id_dfr0 = 0x00200000;
501
- cpu->id_afr0 = 0x00000000;
502
- cpu->isar.id_mmfr0 = 0x00101F40;
503
- cpu->isar.id_mmfr1 = 0x00000000;
504
- cpu->isar.id_mmfr2 = 0x01000000;
505
- cpu->isar.id_mmfr3 = 0x00000000;
506
- cpu->isar.id_isar0 = 0x01101110;
507
- cpu->isar.id_isar1 = 0x02212000;
508
- cpu->isar.id_isar2 = 0x20232232;
509
- cpu->isar.id_isar3 = 0x01111131;
510
- cpu->isar.id_isar4 = 0x01310132;
511
- cpu->isar.id_isar5 = 0x00000000;
512
- cpu->isar.id_isar6 = 0x00000000;
513
- cpu->clidr = 0x00000000;
514
- cpu->ctr = 0x8000c000;
515
-}
516
-
517
-static void cortex_m55_initfn(Object *obj)
518
-{
519
- ARMCPU *cpu = ARM_CPU(obj);
520
-
521
- set_feature(&cpu->env, ARM_FEATURE_V8);
522
- set_feature(&cpu->env, ARM_FEATURE_V8_1M);
523
- set_feature(&cpu->env, ARM_FEATURE_M);
524
- set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
525
- set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
526
- set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
527
- cpu->midr = 0x410fd221; /* r0p1 */
528
- cpu->revidr = 0;
529
- cpu->pmsav7_dregion = 16;
530
- cpu->sau_sregion = 8;
531
- /* These are the MVFR* values for the FPU + full MVE configuration */
532
- cpu->isar.mvfr0 = 0x10110221;
533
- cpu->isar.mvfr1 = 0x12100211;
534
- cpu->isar.mvfr2 = 0x00000040;
535
- cpu->isar.id_pfr0 = 0x20000030;
536
- cpu->isar.id_pfr1 = 0x00000230;
537
- cpu->isar.id_dfr0 = 0x10200000;
538
- cpu->id_afr0 = 0x00000000;
539
- cpu->isar.id_mmfr0 = 0x00111040;
540
- cpu->isar.id_mmfr1 = 0x00000000;
541
- cpu->isar.id_mmfr2 = 0x01000000;
542
- cpu->isar.id_mmfr3 = 0x00000011;
543
- cpu->isar.id_isar0 = 0x01103110;
544
- cpu->isar.id_isar1 = 0x02212000;
545
- cpu->isar.id_isar2 = 0x20232232;
546
- cpu->isar.id_isar3 = 0x01111131;
547
- cpu->isar.id_isar4 = 0x01310132;
548
- cpu->isar.id_isar5 = 0x00000000;
549
- cpu->isar.id_isar6 = 0x00000000;
550
- cpu->clidr = 0x00000000; /* caches not implemented */
551
- cpu->ctr = 0x8303c003;
552
-}
553
-
554
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
555
/* Dummy the TCM region regs for the moment */
556
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
557
@@ -XXX,XX +XXX,XX @@ static void pxa270c5_initfn(Object *obj)
558
cpu->reset_sctlr = 0x00000078;
559
}
560
561
-static const TCGCPUOps arm_v7m_tcg_ops = {
562
- .initialize = arm_translate_init,
563
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
564
- .debug_excp_handler = arm_debug_excp_handler,
565
- .restore_state_to_opc = arm_restore_state_to_opc,
566
-
567
-#ifdef CONFIG_USER_ONLY
568
- .record_sigsegv = arm_cpu_record_sigsegv,
569
- .record_sigbus = arm_cpu_record_sigbus,
570
-#else
571
- .tlb_fill = arm_cpu_tlb_fill,
572
- .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
573
- .do_interrupt = arm_v7m_cpu_do_interrupt,
574
- .do_transaction_failed = arm_cpu_do_transaction_failed,
575
- .do_unaligned_access = arm_cpu_do_unaligned_access,
576
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
577
- .debug_check_watchpoint = arm_debug_check_watchpoint,
578
- .debug_check_breakpoint = arm_debug_check_breakpoint,
579
-#endif /* !CONFIG_USER_ONLY */
580
-};
581
-
582
-static void arm_v7m_class_init(ObjectClass *oc, void *data)
583
-{
584
- ARMCPUClass *acc = ARM_CPU_CLASS(oc);
585
- CPUClass *cc = CPU_CLASS(oc);
586
-
587
- acc->info = data;
588
- cc->tcg_ops = &arm_v7m_tcg_ops;
589
- cc->gdb_core_xml_file = "arm-m-profile.xml";
590
-}
591
-
592
#ifndef TARGET_AARCH64
593
/*
594
* -cpu max: a CPU with as many features enabled as our emulation supports.
595
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
596
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
597
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
598
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
599
- { .name = "cortex-m0", .initfn = cortex_m0_initfn,
600
- .class_init = arm_v7m_class_init },
601
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
602
- .class_init = arm_v7m_class_init },
603
- { .name = "cortex-m4", .initfn = cortex_m4_initfn,
604
- .class_init = arm_v7m_class_init },
605
- { .name = "cortex-m7", .initfn = cortex_m7_initfn,
606
- .class_init = arm_v7m_class_init },
607
- { .name = "cortex-m33", .initfn = cortex_m33_initfn,
608
- .class_init = arm_v7m_class_init },
609
- { .name = "cortex-m55", .initfn = cortex_m55_initfn,
610
- .class_init = arm_v7m_class_init },
611
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
612
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
613
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
20
diff --git a/target/arm/meson.build b/target/arm/meson.build
614
diff --git a/target/arm/meson.build b/target/arm/meson.build
21
index XXXXXXX..XXXXXXX 100644
615
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/meson.build
616
--- a/target/arm/meson.build
23
+++ b/target/arm/meson.build
617
+++ b/target/arm/meson.build
24
@@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files(
618
@@ -XXX,XX +XXX,XX @@ arm_system_ss.add(files(
25
'arm-powerctl.c',
26
'machine.c',
27
'monitor.c',
28
- 'psci.c',
29
'ptw.c',
619
'ptw.c',
30
))
620
))
31
621
622
+arm_user_ss = ss.source_set()
623
+
624
subdir('hvf')
625
626
if 'CONFIG_TCG' in config_all_accel
627
@@ -XXX,XX +XXX,XX @@ endif
628
629
target_arch += {'arm': arm_ss}
630
target_system_arch += {'arm': arm_system_ss}
631
+target_user_arch += {'arm': arm_user_ss}
32
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
632
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
33
index XXXXXXX..XXXXXXX 100644
633
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/meson.build
634
--- a/target/arm/tcg/meson.build
35
+++ b/target/arm/tcg/meson.build
635
+++ b/target/arm/tcg/meson.build
36
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
636
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
37
'sme_helper.c',
637
arm_system_ss.add(files(
38
'sve_helper.c',
638
'psci.c',
39
))
639
))
40
+
640
+
41
+arm_softmmu_ss.add(files(
641
+arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
42
+ 'psci.c',
642
+arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
43
+))
44
--
643
--
45
2.34.1
644
2.34.1
46
47
diff view generated by jsdifflib
[PULL 10/25] target/arm: Don't access TCG code when debugging with KVM
Deleted patch
1
From: Fabiano Rosas <farosas@suse.de>
2
1
3
When TCG is disabled this part of the code should not be reachable, so
4
wrap it with an ifdef for now.
5
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
19
ptw->out_host = NULL;
20
ptw->out_rw = false;
21
} else {
22
+#ifdef CONFIG_TCG
23
CPUTLBEntryFull *full;
24
int flags;
25
26
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
27
ptw->out_rw = full->prot & PAGE_WRITE;
28
pte_attrs = full->pte_attrs;
29
pte_secure = full->attrs.secure;
30
+#else
31
+ g_assert_not_reached();
32
+#endif
33
}
34
35
if (regime_is_stage2(s2_mmu_idx)) {
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
[PULL 11/25] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code
Deleted patch
1
From: Fabiano Rosas <farosas@suse.de>
2
1
3
This struct has no dependencies on TCG code and it is being used in
4
target/arm/ptw.c to simplify the passing around of page table walk
5
results. Those routines can be reached by KVM code via the gdbstub
6
breakpoint code, so take the structure out of CONFIG_TCG to make it
7
visible when building with --disable-tcg.
8
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/exec/cpu-defs.h | 6 ++++++
16
1 file changed, 6 insertions(+)
17
18
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/exec/cpu-defs.h
21
+++ b/include/exec/cpu-defs.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
23
24
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
25
26
+
27
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
28
+
29
+#if !defined(CONFIG_USER_ONLY)
30
/*
31
* The full TLB entry, which is not accessed by generated TCG code,
32
* so the layout is not as critical as that of CPUTLBEntry. This is
33
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
34
TARGET_PAGE_ENTRY_EXTRA
35
#endif
36
} CPUTLBEntryFull;
37
+#endif /* !CONFIG_USER_ONLY */
38
39
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
40
/*
41
* Data elements that are per MMU mode, minus the bits accessed by
42
* the TCG fast path.
43
--
44
2.34.1
45
46
diff view generated by jsdifflib
[PULL 12/25] tests/avocado: add machine:none tag to version.py
Deleted patch
1
From: Fabiano Rosas <farosas@suse.de>
2
1
3
This test currently fails when run on a host for which the QEMU target
4
has no default machine set:
5
6
ERROR| Output: qemu-system-aarch64: No machine specified, and there is
7
no default
8
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
tests/avocado/version.py | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/tests/avocado/version.py b/tests/avocado/version.py
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/avocado/version.py
19
+++ b/tests/avocado/version.py
20
@@ -XXX,XX +XXX,XX @@
21
class Version(QemuSystemTest):
22
"""
23
:avocado: tags=quick
24
+ :avocado: tags=machine:none
25
"""
26
def test_qmp_human_info_version(self):
27
self.vm.add_args('-nodefaults')
28
--
29
2.34.1
30
31
diff view generated by jsdifflib
[PULL 14/25] hw/char/pl011: Un-inline pl011_create()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
pl011_create() is only used in DeviceRealize handlers,
4
not a hot-path. Inlining is not justified.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230220115114.25237-3-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/char/pl011.h | 19 +------------------
13
hw/char/pl011.c | 17 +++++++++++++++++
14
2 files changed, 18 insertions(+), 18 deletions(-)
15
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/pl011.h
19
+++ b/include/hw/char/pl011.h
20
@@ -XXX,XX +XXX,XX @@
21
#ifndef HW_PL011_H
22
#define HW_PL011_H
23
24
-#include "hw/qdev-properties.h"
25
#include "hw/sysbus.h"
26
#include "chardev/char-fe.h"
27
-#include "qapi/error.h"
28
#include "qom/object.h"
29
30
#define TYPE_PL011 "pl011"
31
@@ -XXX,XX +XXX,XX @@ struct PL011State {
32
const unsigned char *id;
33
};
34
35
-static inline DeviceState *pl011_create(hwaddr addr,
36
- qemu_irq irq,
37
- Chardev *chr)
38
-{
39
- DeviceState *dev;
40
- SysBusDevice *s;
41
-
42
- dev = qdev_new("pl011");
43
- s = SYS_BUS_DEVICE(dev);
44
- qdev_prop_set_chr(dev, "chardev", chr);
45
- sysbus_realize_and_unref(s, &error_fatal);
46
- sysbus_mmio_map(s, 0, addr);
47
- sysbus_connect_irq(s, 0, irq);
48
-
49
- return dev;
50
-}
51
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
52
53
static inline DeviceState *pl011_luminary_create(hwaddr addr,
54
qemu_irq irq,
55
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/char/pl011.c
58
+++ b/hw/char/pl011.c
59
@@ -XXX,XX +XXX,XX @@
60
*/
61
62
#include "qemu/osdep.h"
63
+#include "qapi/error.h"
64
#include "hw/char/pl011.h"
65
#include "hw/irq.h"
66
#include "hw/sysbus.h"
67
#include "hw/qdev-clock.h"
68
+#include "hw/qdev-properties.h"
69
#include "hw/qdev-properties-system.h"
70
#include "migration/vmstate.h"
71
#include "chardev/char-fe.h"
72
@@ -XXX,XX +XXX,XX @@
73
#include "qemu/module.h"
74
#include "trace.h"
75
76
+DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
77
+{
78
+ DeviceState *dev;
79
+ SysBusDevice *s;
80
+
81
+ dev = qdev_new("pl011");
82
+ s = SYS_BUS_DEVICE(dev);
83
+ qdev_prop_set_chr(dev, "chardev", chr);
84
+ sysbus_realize_and_unref(s, &error_fatal);
85
+ sysbus_mmio_map(s, 0, addr);
86
+ sysbus_connect_irq(s, 0, irq);
87
+
88
+ return dev;
89
+}
90
+
91
#define PL011_INT_TX 0x20
92
#define PL011_INT_RX 0x10
93
94
--
95
2.34.1
96
97
diff view generated by jsdifflib
[PULL 15/25] hw/char/pl011: Open-code pl011_luminary_create()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
pl011_luminary_create() is only used for the Stellaris board,
4
open-code it.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230220115114.25237-4-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/char/pl011.h | 17 -----------------
13
hw/arm/stellaris.c | 11 ++++++++---
14
2 files changed, 8 insertions(+), 20 deletions(-)
15
16
diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/char/pl011.h
19
+++ b/include/hw/char/pl011.h
20
@@ -XXX,XX +XXX,XX @@ struct PL011State {
21
22
DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr);
23
24
-static inline DeviceState *pl011_luminary_create(hwaddr addr,
25
- qemu_irq irq,
26
- Chardev *chr)
27
-{
28
- DeviceState *dev;
29
- SysBusDevice *s;
30
-
31
- dev = qdev_new("pl011_luminary");
32
- s = SYS_BUS_DEVICE(dev);
33
- qdev_prop_set_chr(dev, "chardev", chr);
34
- sysbus_realize_and_unref(s, &error_fatal);
35
- sysbus_mmio_map(s, 0, addr);
36
- sysbus_connect_irq(s, 0, irq);
37
-
38
- return dev;
39
-}
40
-
41
#endif
42
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/stellaris.c
45
+++ b/hw/arm/stellaris.c
46
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
47
48
for (i = 0; i < 4; i++) {
49
if (board->dc2 & (1 << i)) {
50
- pl011_luminary_create(0x4000c000 + i * 0x1000,
51
- qdev_get_gpio_in(nvic, uart_irq[i]),
52
- serial_hd(i));
53
+ SysBusDevice *sbd;
54
+
55
+ dev = qdev_new("pl011_luminary");
56
+ sbd = SYS_BUS_DEVICE(dev);
57
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
58
+ sysbus_realize_and_unref(sbd, &error_fatal);
59
+ sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000);
60
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i]));
61
}
62
}
63
if (board->dc2 & (1 << 4)) {
64
--
65
2.34.1
66
67
diff view generated by jsdifflib
[PULL 16/25] hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230220115114.25237-5-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
include/hw/char/xilinx_uartlite.h | 6 +++++-
10
hw/char/xilinx_uartlite.c | 4 +---
11
2 files changed, 6 insertions(+), 4 deletions(-)
12
13
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/char/xilinx_uartlite.h
16
+++ b/include/hw/char/xilinx_uartlite.h
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/qdev-properties.h"
19
#include "hw/sysbus.h"
20
#include "qapi/error.h"
21
+#include "qom/object.h"
22
+
23
+#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
24
+OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
25
26
static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
27
qemu_irq irq,
28
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
29
DeviceState *dev;
30
SysBusDevice *s;
31
32
- dev = qdev_new("xlnx.xps-uartlite");
33
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
34
s = SYS_BUS_DEVICE(dev);
35
qdev_prop_set_chr(dev, "chardev", chr);
36
sysbus_realize_and_unref(s, &error_fatal);
37
diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/char/xilinx_uartlite.c
40
+++ b/hw/char/xilinx_uartlite.c
41
@@ -XXX,XX +XXX,XX @@
42
43
#include "qemu/osdep.h"
44
#include "qemu/log.h"
45
+#include "hw/char/xilinx_uartlite.h"
46
#include "hw/irq.h"
47
#include "hw/qdev-properties.h"
48
#include "hw/qdev-properties-system.h"
49
@@ -XXX,XX +XXX,XX @@
50
#define CONTROL_RST_RX 0x02
51
#define CONTROL_IE 0x10
52
53
-#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
54
-OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
55
-
56
struct XilinxUARTLite {
57
SysBusDevice parent_obj;
58
59
--
60
2.34.1
61
62
diff view generated by jsdifflib
[PULL 17/25] hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Open-code the single use of xilinx_uartlite_create().
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230220115114.25237-6-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/char/xilinx_uartlite.h | 20 --------------------
12
hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +++++--
13
2 files changed, 5 insertions(+), 22 deletions(-)
14
15
diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/xilinx_uartlite.h
18
+++ b/include/hw/char/xilinx_uartlite.h
19
@@ -XXX,XX +XXX,XX @@
20
#ifndef XILINX_UARTLITE_H
21
#define XILINX_UARTLITE_H
22
23
-#include "hw/qdev-properties.h"
24
-#include "hw/sysbus.h"
25
-#include "qapi/error.h"
26
#include "qom/object.h"
27
28
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
29
OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE)
30
31
-static inline DeviceState *xilinx_uartlite_create(hwaddr addr,
32
- qemu_irq irq,
33
- Chardev *chr)
34
-{
35
- DeviceState *dev;
36
- SysBusDevice *s;
37
-
38
- dev = qdev_new(TYPE_XILINX_UARTLITE);
39
- s = SYS_BUS_DEVICE(dev);
40
- qdev_prop_set_chr(dev, "chardev", chr);
41
- sysbus_realize_and_unref(s, &error_fatal);
42
- sysbus_mmio_map(s, 0, addr);
43
- sysbus_connect_irq(s, 0, irq);
44
-
45
- return dev;
46
-}
47
-
48
#endif
49
diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
52
+++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
53
@@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine)
54
irq[i] = qdev_get_gpio_in(dev, i);
55
}
56
57
- xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ],
58
- serial_hd(0));
59
+ dev = qdev_new(TYPE_XILINX_UARTLITE);
60
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
61
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
62
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
64
65
/* 2 timers at irq 2 @ 62 Mhz. */
66
dev = qdev_new("xlnx.xps-timer");
67
--
68
2.34.1
69
70
diff view generated by jsdifflib
[PULL 19/25] hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20230220115114.25237-8-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/timer/cmsdk-apb-timer.h | 1 -
9
1 file changed, 1 deletion(-)
10
11
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/timer/cmsdk-apb-timer.h
14
+++ b/include/hw/timer/cmsdk-apb-timer.h
15
@@ -XXX,XX +XXX,XX @@
16
#ifndef CMSDK_APB_TIMER_H
17
#define CMSDK_APB_TIMER_H
18
19
-#include "hw/qdev-properties.h"
20
#include "hw/sysbus.h"
21
#include "hw/ptimer.h"
22
#include "hw/clock.h"
23
--
24
2.34.1
25
26
diff view generated by jsdifflib
[PULL 20/25] hw/intc/armv7m_nvic: Use QOM cast CPU() macro
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Avoid accessing 'parent_obj' directly.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20230220115114.25237-9-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/intc/armv7m_nvic.c | 6 +++---
11
1 file changed, 3 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/intc/armv7m_nvic.c
16
+++ b/hw/intc/armv7m_nvic.c
17
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
18
* which saves having to have an extra argument is_terminal
19
* that we'd only use in one place.
20
*/
21
- cpu_abort(&s->cpu->parent_obj,
22
+ cpu_abort(CPU(s->cpu),
23
"Lockup: can't take terminal derived exception "
24
"(original exception priority %d)\n",
25
s->vectpending_prio);
26
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
27
* Lockup condition due to a guest bug. We don't model
28
* Lockup, so report via cpu_abort() instead.
29
*/
30
- cpu_abort(&s->cpu->parent_obj,
31
+ cpu_abort(CPU(s->cpu),
32
"Lockup: can't escalate %d to HardFault "
33
"(current priority %d)\n", irq, running);
34
}
35
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
36
* We want to escalate to HardFault but the context the
37
* FP state belongs to prevents the exception pre-empting.
38
*/
39
- cpu_abort(&s->cpu->parent_obj,
40
+ cpu_abort(CPU(s->cpu),
41
"Lockup: can't escalate to HardFault during "
42
"lazy FP register stacking\n");
43
}
44
--
45
2.34.1
46
47
diff view generated by jsdifflib
[PULL 22/25] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Since commit be8d853766 ("iothread: add I/O thread object") we
4
never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(),
5
remove these definitions.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20230113200138.52869-2-philmd@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
iothread.c | 4 ----
14
1 file changed, 4 deletions(-)
15
16
diff --git a/iothread.c b/iothread.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/iothread.c
19
+++ b/iothread.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "qemu/rcu.h"
22
#include "qemu/main-loop.h"
23
24
-typedef ObjectClass IOThreadClass;
25
-
26
-DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD,
27
- TYPE_IOTHREAD)
28
29
#ifdef CONFIG_POSIX
30
/* Benchmark results from 2016 on NVMe SSD drives show max polling times around
31
--
32
2.34.1
33
34
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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