[v3] Replace TARGET_TB_PCREL with CF_PCREL

[PATCH v3 17/27] target/riscv: Replace `tb_pc()` with `tb->pc`

Anton Johansson via posted 27 patches 2 years, 11 months ago

Diff against v1 v2
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Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, Michael Rolnik <mrolnik@gmail.com>, Taylor Simpson <tsimpson@quicinc.com>, Eduardo Habkost <eduardo@habkost.net>, Song Gao <gaosong@loongson.cn>, Xiaojuan Yang <yangxiaojuan@loongson.cn>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Stafford Horne <shorne@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Yoshinori Sato <ysato@users.sourceforge.jp>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Artyom Tarasenko <atar4qemu@gmail.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

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[PATCH v3 17/27] target/riscv: Replace `tb_pc()` with `tb->pc`

Posted by Anton Johansson via 2 years, 11 months ago

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/cpu.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..9eb748a283 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,7 @@
 #include "fpu/softfloat-helpers.h"
 #include "sysemu/kvm.h"
 #include "kvm_riscv.h"
+#include "tcg/tcg.h"
 
 /* RISC-V CPU definitions */
 
@@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
     CPURISCVState *env = &cpu->env;
     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
 
+    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
     if (xl == MXL_RV32) {
-        env->pc = (int32_t)tb_pc(tb);
+        env->pc = (int32_t) tb->pc;
     } else {
-        env->pc = tb_pc(tb);
+        env->pc = tb->pc;
     }
 }
 
-- 
2.39.1

Re: [PATCH v3 17/27] target/riscv: Replace `tb_pc()` with `tb->pc`

Posted by Palmer Dabbelt 2 years, 11 months ago

On Mon, 27 Feb 2023 05:51:52 PST (-0800), anjo@rev.ng wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/riscv/cpu.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 93b52b826c..9eb748a283 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,7 @@
>  #include "fpu/softfloat-helpers.h"
>  #include "sysemu/kvm.h"
>  #include "kvm_riscv.h"
> +#include "tcg/tcg.h"
>
>  /* RISC-V CPU definitions */
>
> @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>      CPURISCVState *env = &cpu->env;
>      RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
>
> +    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
> +
>      if (xl == MXL_RV32) {
> -        env->pc = (int32_t)tb_pc(tb);
> +        env->pc = (int32_t) tb->pc;
>      } else {
> -        env->pc = tb_pc(tb);
> +        env->pc = tb->pc;
>      }
>  }

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

Thanks!  I'm going to assume you want these to stay together, but LMK if 
you were looking to aim this at the RISC-V tree.

Re: [PATCH v3 17/27] target/riscv: Replace `tb_pc()` with `tb->pc`

Posted by Richard Henderson 2 years, 11 months ago

On 2/27/23 13:05, Palmer Dabbelt wrote:
> On Mon, 27 Feb 2023 05:51:52 PST (-0800), anjo@rev.ng wrote:
>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>  target/riscv/cpu.c | 7 +++++--
>>  1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 93b52b826c..9eb748a283 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -34,6 +34,7 @@
>>  #include "fpu/softfloat-helpers.h"
>>  #include "sysemu/kvm.h"
>>  #include "kvm_riscv.h"
>> +#include "tcg/tcg.h"
>>
>>  /* RISC-V CPU definitions */
>>
>> @@ -533,10 +534,12 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
>>      CPURISCVState *env = &cpu->env;
>>      RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
>>
>> +    tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
>> +
>>      if (xl == MXL_RV32) {
>> -        env->pc = (int32_t)tb_pc(tb);
>> +        env->pc = (int32_t) tb->pc;
>>      } else {
>> -        env->pc = tb_pc(tb);
>> +        env->pc = tb->pc;
>>      }
>>  }
> 
> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> Thanks!  I'm going to assume you want these to stay together, but LMK if you were looking 
> to aim this at the RISC-V tree.

I've queued to tcg-next, so they'll stay together.
I've now added your r-b.


r~