1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: | 1 | Here's another arm pullreq; nothing too exciting in here I think. |
---|---|---|---|
2 | 2 | ||
3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) | 3 | thanks |
4 | -- PMM | ||
5 | |||
6 | The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976: | ||
7 | |||
8 | Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700) | ||
4 | 9 | ||
5 | are available in the Git repository at: | 10 | are available in the Git repository at: |
6 | 11 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430 |
8 | 13 | ||
9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: | 14 | for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e: |
10 | 15 | ||
11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) | 16 | tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100) |
12 | 17 | ||
13 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
14 | target-arm queue: | 19 | target-arm queue: |
15 | * Some mostly M-profile-related code cleanups | 20 | * hw/core/clock: allow clock_propagate on child clocks |
16 | * avocado: Retire the boot_linux.py AArch64 TCG tests | 21 | * hvf: arm: Remove unused PL1_WRITE_MASK define |
17 | * hw/arm/smmuv3: Add GBPA register | 22 | * target/arm: Restrict translation disabled alignment check to VMSA |
18 | * arm/virt: don't try to spell out the accelerator | 23 | * docs/system/arm/emulation.rst: Add missing implemented features |
19 | * hw/arm: Attach PSPI module to NPCM7XX SoC | 24 | * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max' |
20 | * Some cleanup/refactoring patches aiming towards | 25 | * tests/avocado: update sunxi kernel from armbian to 6.6.16 |
21 | allowing building Arm targets without CONFIG_TCG | 26 | * target/arm: Make new CPUs default to 1GHz generic timer |
27 | * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields | ||
28 | * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size | ||
29 | * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian | ||
30 | * hw/arm: Add DM163 display to B-L475E-IOT01A board | ||
22 | 31 | ||
23 | ---------------------------------------------------------------- | 32 | ---------------------------------------------------------------- |
24 | Alex Bennée (1): | 33 | Alexandra Diupina (1): |
25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py | 34 | hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields |
26 | 35 | ||
27 | Claudio Fontana (3): | 36 | Inès Varhol (5): |
28 | target/arm: rename handle_semihosting to tcg_handle_semihosting | 37 | hw/display : Add device DM163 |
29 | target/arm: wrap psci call with tcg_enabled | 38 | hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC |
30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() | 39 | hw/arm : Create Bl475eMachineState |
40 | hw/arm : Connect DM163 to B-L475E-IOT01A | ||
41 | tests/qtest : Add testcase for DM163 | ||
31 | 42 | ||
32 | Cornelia Huck (1): | 43 | Peter Maydell (10): |
33 | arm/virt: don't try to spell out the accelerator | 44 | docs/system/arm/emulation.rst: Add missing implemented features |
45 | target/arm: Enable FEAT_CSV2_3 for -cpu max | ||
46 | target/arm: Enable FEAT_ETS2 for -cpu max | ||
47 | target/arm: Implement ID_AA64MMFR3_EL1 | ||
48 | target/arm: Enable FEAT_Spec_FPACC for -cpu max | ||
49 | tests/avocado: update sunxi kernel from armbian to 6.6.16 | ||
50 | target/arm: Refactor default generic timer frequency handling | ||
51 | hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz | ||
52 | hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property | ||
53 | target/arm: Default to 1GHz cntfrq for 'max' and new CPUs | ||
34 | 54 | ||
35 | Fabiano Rosas (7): | 55 | Philippe Mathieu-Daudé (1): |
36 | target/arm: Move PC alignment check | 56 | hw/arm/npcm7xx: Store derivative OTP fuse key in little endian |
37 | target/arm: Move cpregs code out of cpu.h | ||
38 | tests/avocado: Skip tests that require a missing accelerator | ||
39 | tests/avocado: Tag TCG tests with accel:tcg | ||
40 | target/arm: Use "max" as default cpu for the virt machine with KVM | ||
41 | tests/qtest: arm-cpu-features: Match tests to required accelerators | ||
42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG | ||
43 | 57 | ||
44 | Hao Wu (3): | 58 | Raphael Poggi (1): |
45 | MAINTAINERS: Add myself to maintainers and remove Havard | 59 | hw/core/clock: allow clock_propagate on child clocks |
46 | hw/ssi: Add Nuvoton PSPI Module | ||
47 | hw/arm: Attach PSPI module to NPCM7XX SoC | ||
48 | 60 | ||
49 | Jean-Philippe Brucker (2): | 61 | Richard Henderson (1): |
50 | hw/arm/smmu-common: Support 64-bit addresses | 62 | target/arm: Restrict translation disabled alignment check to VMSA |
51 | hw/arm/smmu-common: Fix TTB1 handling | ||
52 | 63 | ||
53 | Mostafa Saleh (1): | 64 | Thomas Huth (1): |
54 | hw/arm/smmuv3: Add GBPA register | 65 | hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size |
55 | 66 | ||
56 | Philippe Mathieu-Daudé (12): | 67 | Zenghui Yu (1): |
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | 68 | hvf: arm: Remove PL1_WRITE_MASK |
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | ||
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | ||
60 | target/arm: Constify ID_PFR1 on user emulation | ||
61 | target/arm: Convert CPUARMState::eabi to boolean | ||
62 | target/arm: Avoid resetting CPUARMState::eabi field | ||
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | ||
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | ||
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | 69 | ||
70 | MAINTAINERS | 8 +- | 70 | docs/system/arm/b-l475e-iot01a.rst | 3 +- |
71 | docs/system/arm/nuvoton.rst | 2 +- | 71 | docs/system/arm/emulation.rst | 42 ++++- |
72 | hw/arm/smmuv3-internal.h | 7 + | 72 | include/hw/display/dm163.h | 59 ++++++ |
73 | include/hw/arm/npcm7xx.h | 2 + | 73 | include/hw/watchdog/sbsa_gwdt.h | 3 +- |
74 | include/hw/arm/smmu-common.h | 2 - | 74 | target/arm/cpu.h | 28 +++ |
75 | include/hw/arm/smmuv3.h | 1 + | 75 | target/arm/internals.h | 15 +- |
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | 76 | hw/arm/b-l475e-iot01a.c | 105 +++++++++-- |
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | 77 | hw/arm/npcm7xx.c | 3 +- |
78 | linux-user/user-internals.h | 2 +- | 78 | hw/arm/sbsa-ref.c | 16 ++ |
79 | target/arm/cpregs.h | 98 ++++++++++++++ | 79 | hw/arm/stm32l4x5_soc.c | 6 +- |
80 | target/arm/cpu.h | 228 ++------------------------------- | 80 | hw/char/stm32l4x5_usart.c | 1 + |
81 | target/arm/internals.h | 14 -- | 81 | hw/core/clock.c | 1 - |
82 | hw/arm/npcm7xx.c | 25 +++- | 82 | hw/core/machine.c | 4 +- |
83 | hw/arm/smmu-common.c | 4 +- | 83 | hw/display/dm163.c | 349 ++++++++++++++++++++++++++++++++++++ |
84 | hw/arm/smmuv3.c | 43 ++++++- | 84 | hw/dma/xlnx_dpdma.c | 20 +-- |
85 | hw/arm/virt.c | 10 +- | 85 | hw/watchdog/sbsa_gwdt.c | 15 +- |
86 | hw/intc/armv7m_nvic.c | 38 ++---- | 86 | target/arm/cpu.c | 42 +++-- |
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | 87 | target/arm/cpu64.c | 2 + |
88 | linux-user/arm/cpu_loop.c | 4 +- | 88 | target/arm/helper.c | 22 +-- |
89 | target/arm/cpu.c | 5 +- | 89 | target/arm/hvf/hvf.c | 3 +- |
90 | target/arm/cpu_tcg.c | 3 + | 90 | target/arm/kvm.c | 2 + |
91 | target/arm/helper.c | 31 +++-- | 91 | target/arm/tcg/cpu32.c | 6 +- |
92 | target/arm/m_helper.c | 86 +++++++------ | 92 | target/arm/tcg/cpu64.c | 28 ++- |
93 | target/arm/machine.c | 18 +-- | 93 | target/arm/tcg/hflags.c | 12 +- |
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | 94 | tests/qtest/dm163-test.c | 194 ++++++++++++++++++++ |
95 | hw/arm/Kconfig | 1 + | 95 | tests/qtest/stm32l4x5_gpio-test.c | 13 +- |
96 | hw/ssi/meson.build | 2 +- | 96 | tests/qtest/stm32l4x5_syscfg-test.c | 17 +- |
97 | hw/ssi/trace-events | 5 + | 97 | hw/arm/Kconfig | 1 + |
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | 98 | hw/display/Kconfig | 3 + |
99 | tests/avocado/boot_linux.py | 48 ++----- | 99 | hw/display/meson.build | 1 + |
100 | tests/avocado/boot_linux_console.py | 1 + | 100 | hw/display/trace-events | 14 ++ |
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | 101 | tests/avocado/boot_linux_console.py | 70 ++++---- |
102 | tests/avocado/reverse_debugging.py | 8 ++ | 102 | tests/avocado/replay_kernel.py | 8 +- |
103 | tests/qtest/meson.build | 4 +- | 103 | tests/qtest/meson.build | 2 + |
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | 104 | 34 files changed, 987 insertions(+), 123 deletions(-) |
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | 105 | create mode 100644 include/hw/display/dm163.h |
106 | create mode 100644 hw/ssi/npcm_pspi.c | 106 | create mode 100644 hw/display/dm163.c |
107 | create mode 100644 tests/qtest/dm163-test.c | ||
107 | 108 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, | ||
4 | similarly to automatic conversion from commit 8063396bf3 | ||
5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/armv7m_nvic.h | 5 +---- | ||
13 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/intc/armv7m_nvic.h | ||
18 | +++ b/include/hw/intc/armv7m_nvic.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "qom/object.h" | ||
21 | |||
22 | #define TYPE_NVIC "armv7m_nvic" | ||
23 | - | ||
24 | -typedef struct NVICState NVICState; | ||
25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, | ||
26 | - TYPE_NVIC) | ||
27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) | ||
28 | |||
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Raphael Poggi <raphael.poggi@lynxleap.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 3 | clock_propagate() has an assert that clk->source is NULL, i.e. that |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | you are calling it on a clock which has no source clock. This made |
5 | Acked-by: Thomas Huth <thuth@redhat.com> | 5 | sense in the original design where the only way for a clock's |
6 | frequency to change if it had a source clock was when that source | ||
7 | clock changed. However, we subsequently added multiplier/divider | ||
8 | support, but didn't look at what that meant for propagation. | ||
9 | |||
10 | If a clock-management device changes the multiplier or divider value | ||
11 | on a clock, it needs to propagate that change down to child clocks, | ||
12 | even if the clock has a source clock set. So the assertion is now | ||
13 | incorrect. | ||
14 | |||
15 | Remove the assertion. | ||
16 | |||
17 | Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk> | ||
18 | Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | [PMM: Rewrote the commit message] | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 22 | --- |
8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- | 23 | hw/core/clock.c | 1 - |
9 | 1 file changed, 18 insertions(+), 10 deletions(-) | 24 | 1 file changed, 1 deletion(-) |
10 | 25 | ||
11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | 26 | diff --git a/hw/core/clock.c b/hw/core/clock.c |
12 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/tests/qtest/arm-cpu-features.c | 28 | --- a/hw/core/clock.c |
14 | +++ b/tests/qtest/arm-cpu-features.c | 29 | +++ b/hw/core/clock.c |
15 | @@ -XXX,XX +XXX,XX @@ | 30 | @@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks) |
16 | #define SVE_MAX_VQ 16 | 31 | |
17 | 32 | void clock_propagate(Clock *clk) | |
18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " | ||
19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " | ||
20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " | ||
21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ | ||
22 | " 'arguments': { 'type': 'full', " | ||
23 | #define QUERY_TAIL "}}" | ||
24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
25 | { | 33 | { |
26 | g_test_init(&argc, &argv, NULL); | 34 | - assert(clk->source == NULL); |
27 | 35 | trace_clock_propagate(CLOCK_PATH(clk)); | |
28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", | 36 | clock_propagate_period(clk, true); |
29 | - NULL, test_query_cpu_model_expansion); | ||
30 | + if (qtest_has_accel("tcg")) { | ||
31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", | ||
32 | + NULL, test_query_cpu_model_expansion); | ||
33 | + } | ||
34 | + | ||
35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { | ||
36 | + goto out; | ||
37 | + } | ||
38 | |||
39 | /* | ||
40 | * For now we only run KVM specific tests with AArch64 QEMU in | ||
41 | * order avoid attempting to run an AArch32 QEMU with KVM on | ||
42 | * AArch64 hosts. That won't work and isn't easy to detect. | ||
43 | */ | ||
44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { | ||
45 | + if (qtest_has_accel("kvm")) { | ||
46 | /* | ||
47 | * This tests target the 'host' CPU type, so register it only if | ||
48 | * KVM is available. | ||
49 | */ | ||
50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", | ||
51 | NULL, test_query_cpu_model_expansion_kvm); | ||
52 | - } | ||
53 | |||
54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
56 | - NULL, sve_tests_sve_max_vq_8); | ||
57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
58 | - NULL, sve_tests_sve_off); | ||
59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", | ||
60 | NULL, sve_tests_sve_off_kvm); | ||
61 | } | ||
62 | |||
63 | + if (qtest_has_accel("tcg")) { | ||
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
69 | + | ||
70 | +out: | ||
71 | return g_test_run(); | ||
72 | } | 37 | } |
73 | -- | 38 | -- |
74 | 2.34.1 | 39 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Zenghui Yu <zenghui.yu@linux.dev> |
---|---|---|---|
2 | 2 | ||
3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a | 3 | As it had never been used since the first commit a1477da3ddeb ("hvf: Add |
4 | KVM-only build the 'max' cpu. | 4 | Apple Silicon support"). |
5 | 5 | ||
6 | Note that we cannot use 'host' here because the qtests can run without | 6 | Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> |
7 | any other accelerator (than qtest) and 'host' depends on KVM being | 7 | Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev |
8 | enabled. | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 10 | --- |
15 | hw/arm/virt.c | 4 ++++ | 11 | target/arm/hvf/hvf.c | 1 - |
16 | 1 file changed, 4 insertions(+) | 12 | 1 file changed, 1 deletion(-) |
17 | 13 | ||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 14 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c |
19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/virt.c | 16 | --- a/target/arm/hvf/hvf.c |
21 | +++ b/hw/arm/virt.c | 17 | +++ b/target/arm/hvf/hvf.c |
22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 18 | @@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void) |
23 | mc->minimum_page_bits = 12; | 19 | |
24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; | 20 | #define HVF_SYSREG(crn, crm, op0, op1, op2) \ |
25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | 21 | ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) |
26 | +#ifdef CONFIG_TCG | 22 | -#define PL1_WRITE_MASK 0x4 |
27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | 23 | |
28 | +#else | 24 | #define SYSREG_OP0_SHIFT 20 |
29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); | 25 | #define SYSREG_OP0_MASK 0x3 |
30 | +#endif | ||
31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | ||
32 | mc->kvm_type = virt_kvm_type; | ||
33 | assert(!mc->get_hotplug_handler); | ||
34 | -- | 26 | -- |
35 | 2.34.1 | 27 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Claudio Fontana <cfontana@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | for "all" builds (tcg + kvm), we want to avoid doing | 3 | For cpus using PMSA, when the MPU is disabled, the default memory |
4 | the psci check if tcg is built-in, but not enabled. | 4 | type is Normal, Non-cachable. This means that it should not |
5 | have alignment restrictions enforced. | ||
5 | 6 | ||
6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | 7 | Cc: qemu-stable@nongnu.org |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") |
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 9 | Reported-by: Clément Chigot <chigot@adacore.com> |
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Tested-by: Clément Chigot <chigot@adacore.com> | ||
13 | Message-id: 20240422170722.117409-1-richard.henderson@linaro.org | ||
14 | [PMM: trivial comment, commit message tweaks] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 16 | --- |
12 | target/arm/helper.c | 3 ++- | 17 | target/arm/tcg/hflags.c | 12 ++++++++++-- |
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | 18 | 1 file changed, 10 insertions(+), 2 deletions(-) |
14 | 19 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 20 | diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c |
16 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 22 | --- a/target/arm/tcg/hflags.c |
18 | +++ b/target/arm/helper.c | 23 | +++ b/target/arm/tcg/hflags.c |
19 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) |
20 | #include "hw/irq.h" | ||
21 | #include "sysemu/cpu-timers.h" | ||
22 | #include "sysemu/kvm.h" | ||
23 | +#include "sysemu/tcg.h" | ||
24 | #include "qapi/qapi-commands-machine-target.h" | ||
25 | #include "qapi/error.h" | ||
26 | #include "qemu/guest-random.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
28 | env->exception.syndrome); | ||
29 | } | 25 | } |
30 | 26 | ||
31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { | 27 | /* |
32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { | 28 | - * If translation is disabled, then the default memory type is |
33 | arm_handle_psci_call(cpu); | 29 | - * Device(-nGnRnE) instead of Normal, which requires that alignment |
34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | 30 | + * With PMSA, when the MPU is disabled, all memory types in the |
35 | return; | 31 | + * default map are Normal, so don't need aligment enforcing. |
32 | + */ | ||
33 | + if (arm_feature(env, ARM_FEATURE_PMSA)) { | ||
34 | + return false; | ||
35 | + } | ||
36 | + | ||
37 | + /* | ||
38 | + * With VMSA, if translation is disabled, then the default memory type | ||
39 | + * is Device(-nGnRnE) instead of Normal, which requires that alignment | ||
40 | * be enforced. Since this affects all ram, it is most efficient | ||
41 | * to handle this during translation. | ||
42 | */ | ||
36 | -- | 43 | -- |
37 | 2.34.1 | 44 | 2.34.1 |
38 | 45 | ||
39 | 46 | diff view generated by jsdifflib |
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | 1 | As of version DDI0487K.a of the Arm ARM, some architectural features |
---|---|---|---|
2 | which previously didn't have official names have been named. Add | ||
3 | these to the list of features which QEMU's TCG emulation supports. | ||
4 | Mostly these are features which we thought of as part of baseline 8.0 | ||
5 | support. For SVE and SVE2, the names have been brought into line | ||
6 | with the FEAT_* naming convention of other extensions, and some | ||
7 | sub-components split into separate FEAT_ items. In a few cases (eg | ||
8 | FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight. | ||
2 | 9 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | the TTB1 check. | 12 | Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org |
13 | --- | ||
14 | docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++-- | ||
15 | 1 file changed, 36 insertions(+), 2 deletions(-) | ||
6 | 16 | ||
7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> | 17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/smmu-common.c | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/smmu-common.c | 19 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/hw/arm/smmu-common.c | 20 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | 21 | @@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for |
22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | 22 | the following architecture extensions: |
23 | return &cfg->tt[0]; | 23 | |
24 | } else if (cfg->tt[1].tsz && | 24 | - FEAT_AA32BF16 (AArch32 BFloat16 instructions) |
25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { | 25 | +- FEAT_AA32EL0 (Support for AArch32 at EL0) |
26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { | 26 | +- FEAT_AA32EL1 (Support for AArch32 at EL1) |
27 | /* there is a ttbr1 region and we are in it (high bits all one) */ | 27 | +- FEAT_AA32EL2 (Support for AArch32 at EL2) |
28 | return &cfg->tt[1]; | 28 | +- FEAT_AA32EL3 (Support for AArch32 at EL3) |
29 | } else if (!cfg->tt[0].tsz) { | 29 | - FEAT_AA32HPD (AArch32 hierarchical permission disables) |
30 | - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) | ||
31 | +- FEAT_AA64EL0 (Support for AArch64 at EL0) | ||
32 | +- FEAT_AA64EL1 (Support for AArch64 at EL1) | ||
33 | +- FEAT_AA64EL2 (Support for AArch64 at EL2) | ||
34 | +- FEAT_AA64EL3 (Support for AArch64 at EL3) | ||
35 | +- FEAT_AdvSIMD (Advanced SIMD Extension) | ||
36 | - FEAT_AES (AESD and AESE instructions) | ||
37 | +- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) | ||
38 | +- FEAT_ASID16 (16 bit ASID) | ||
39 | - FEAT_BBM at level 2 (Translation table break-before-make levels) | ||
40 | - FEAT_BF16 (AArch64 BFloat16 instructions) | ||
41 | - FEAT_BTI (Branch Target Identification) | ||
42 | +- FEAT_CCIDX (Extended cache index) | ||
43 | - FEAT_CRC32 (CRC32 instructions) | ||
44 | +- FEAT_Crypto (Cryptographic Extension) | ||
45 | - FEAT_CSV2 (Cache speculation variant 2) | ||
46 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | ||
47 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) | ||
48 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
49 | - FEAT_DGH (Data gathering hint) | ||
50 | - FEAT_DIT (Data Independent Timing instructions) | ||
51 | - FEAT_DPB (DC CVAP instruction) | ||
52 | +- FEAT_DPB2 (DC CVADP instruction) | ||
53 | +- FEAT_Debugv8p1 (Debug with VHE) | ||
54 | - FEAT_Debugv8p2 (Debug changes for v8.2) | ||
55 | - FEAT_Debugv8p4 (Debug changes for v8.4) | ||
56 | - FEAT_DotProd (Advanced SIMD dot product instructions) | ||
57 | - FEAT_DoubleFault (Double Fault Extension) | ||
58 | - FEAT_E0PD (Preventing EL0 access to halves of address maps) | ||
59 | - FEAT_ECV (Enhanced Counter Virtualization) | ||
60 | +- FEAT_EL0 (Support for execution at EL0) | ||
61 | +- FEAT_EL1 (Support for execution at EL1) | ||
62 | +- FEAT_EL2 (Support for execution at EL2) | ||
63 | +- FEAT_EL3 (Support for execution at EL3) | ||
64 | - FEAT_EPAC (Enhanced pointer authentication) | ||
65 | - FEAT_ETS (Enhanced Translation Synchronization) | ||
66 | - FEAT_EVT (Enhanced Virtualization Traps) | ||
67 | +- FEAT_F32MM (Single-precision Matrix Multiplication) | ||
68 | +- FEAT_F64MM (Double-precision Matrix Multiplication) | ||
69 | - FEAT_FCMA (Floating-point complex number instructions) | ||
70 | - FEAT_FGT (Fine-Grained Traps) | ||
71 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
72 | +- FEAT_FP (Floating Point extensions) | ||
73 | - FEAT_FP16 (Half-precision floating-point data processing) | ||
74 | - FEAT_FPAC (Faulting on AUT* instructions) | ||
75 | - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) | ||
76 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
77 | - FEAT_LSE (Large System Extensions) | ||
78 | - FEAT_LSE2 (Large System Extensions v2) | ||
79 | - FEAT_LVA (Large Virtual Address space) | ||
80 | +- FEAT_MixedEnd (Mixed-endian support) | ||
81 | +- FEAT_MixdEndEL0 (Mixed-endian support at EL0) | ||
82 | - FEAT_MOPS (Standardization of memory operations) | ||
83 | - FEAT_MTE (Memory Tagging Extension) | ||
84 | - FEAT_MTE2 (Memory Tagging Extension) | ||
85 | - FEAT_MTE3 (MTE Asymmetric Fault Handling) | ||
86 | +- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults) | ||
87 | - FEAT_NMI (Non-maskable Interrupt) | ||
88 | - FEAT_NV (Nested Virtualization) | ||
89 | - FEAT_NV2 (Enhanced nested virtualization support) | ||
90 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
91 | - FEAT_PAuth (Pointer authentication) | ||
92 | - FEAT_PAuth2 (Enhancements to pointer authentication) | ||
93 | - FEAT_PMULL (PMULL, PMULL2 instructions) | ||
94 | +- FEAT_PMUv3 (PMU extension version 3) | ||
95 | - FEAT_PMUv3p1 (PMU Extensions v3.1) | ||
96 | - FEAT_PMUv3p4 (PMU Extensions v3.4) | ||
97 | - FEAT_PMUv3p5 (PMU Extensions v3.5) | ||
98 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
99 | - FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode) | ||
100 | - FEAT_SME_F64F64 (Double-precision floating-point outer product instructions) | ||
101 | - FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions) | ||
102 | +- FEAT_SVE (Scalable Vector Extension) | ||
103 | +- FEAT_SVE_AES (Scalable Vector AES instructions) | ||
104 | +- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions) | ||
105 | +- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions) | ||
106 | +- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions) | ||
107 | +- FEAT_SVE_SM4 (Scalable Vector SM4 instructions) | ||
108 | +- FEAT_SVE2 (Scalable Vector Extension version 2) | ||
109 | - FEAT_SPECRES (Speculation restriction instructions) | ||
110 | - FEAT_SSBS (Speculative Store Bypass Safe) | ||
111 | +- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1) | ||
112 | +- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) | ||
113 | +- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1) | ||
114 | - FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality) | ||
115 | - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) | ||
116 | - FEAT_TLBIRANGE (TLB invalidate range instructions) | ||
117 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
118 | - FEAT_VHE (Virtualization Host Extensions) | ||
119 | - FEAT_VMID16 (16-bit VMID) | ||
120 | - FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) | ||
121 | -- SVE (The Scalable Vector Extension) | ||
122 | -- SVE2 (The Scalable Vector Extension v2) | ||
123 | |||
124 | For information on the specifics of these extensions, please refer | ||
125 | to the `Armv8-A Arm Architecture Reference Manual | ||
30 | -- | 126 | -- |
31 | 2.34.1 | 127 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose |
---|---|---|---|
2 | information about whether branch targets and branch history trained | ||
3 | in one hardware described context can control speculative execution | ||
4 | in a different hardware context. | ||
2 | 5 | ||
3 | If a test was tagged with the "accel" tag and the specified | 6 | There is no branch prediction in TCG, so we don't need to do anything |
4 | accelerator it not present in the qemu binary, cancel the test. | 7 | to be compliant with this. Upadte the '-cpu max' ID registers to |
8 | advertise the feature. | ||
5 | 9 | ||
6 | We can now write tests without explicit calls to require_accelerator, | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | just the tag is enough. | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org | ||
14 | --- | ||
15 | docs/system/arm/emulation.rst | 1 + | ||
16 | target/arm/tcg/cpu64.c | 4 ++-- | ||
17 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
8 | 18 | ||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ | ||
15 | 1 file changed, 4 insertions(+) | ||
16 | |||
17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py | ||
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/tests/avocado/avocado_qemu/__init__.py | 21 | --- a/docs/system/arm/emulation.rst |
20 | +++ b/tests/avocado/avocado_qemu/__init__.py | 22 | +++ b/docs/system/arm/emulation.rst |
21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
22 | 24 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) | |
23 | super().setUp('qemu-system-') | 25 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
24 | 26 | - FEAT_CSV2_2 (Cache speculation variant 2, version 2) | |
25 | + accel_required = self._get_unique_tag_val('accel') | 27 | +- FEAT_CSV2_3 (Cache speculation variant 2, version 3) |
26 | + if accel_required: | 28 | - FEAT_CSV3 (Cache speculation variant 3) |
27 | + self.require_accelerator(accel_required) | 29 | - FEAT_DGH (Data gathering hint) |
28 | + | 30 | - FEAT_DIT (Data Independent Timing instructions) |
29 | self.machine = self.params.get('machine', | 31 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
30 | default=self._get_unique_tag_val('machine')) | 32 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/target/arm/tcg/cpu64.c | ||
34 | +++ b/target/arm/tcg/cpu64.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
36 | t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); | ||
37 | t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ | ||
38 | t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ | ||
39 | - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ | ||
40 | + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */ | ||
41 | t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ | ||
42 | cpu->isar.id_aa64pfr0 = t; | ||
43 | |||
44 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
45 | t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ | ||
46 | t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */ | ||
47 | t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */ | ||
48 | - t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ | ||
49 | + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ | ||
50 | t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ | ||
51 | cpu->isar.id_aa64pfr1 = t; | ||
31 | 52 | ||
32 | -- | 53 | -- |
33 | 2.34.1 | 54 | 2.34.1 |
34 | 55 | ||
35 | 56 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | FEAT_ETS2 is a tighter set of guarantees about memory ordering |
---|---|---|---|
2 | involving translation table walks than the old FEAT_ETS; FEAT_ETS has | ||
3 | been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1 | ||
4 | now gives no greater guarantees than ETS == 0. | ||
2 | 5 | ||
3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have | 6 | FEAT_ETS2 requires: |
4 | a cpregs.h header which is more suitable for this code. | 7 | * the virtual address of a load or store that appears in program |
8 | order after a DSB cannot be translated until after the DSB | ||
9 | completes (section B2.10.9) | ||
10 | * TLB maintenance operations that only affect translations without | ||
11 | execute permission are guaranteed complete after a DSB | ||
12 | (R_BLDZX) | ||
13 | * if a memory access RW2 is ordered-before memory access RW2, | ||
14 | then RW1 is also ordered-before any translation table walk | ||
15 | generated by RW2 that generates a Translation, Address size | ||
16 | or Access flag fault (R_NNFPF, I_CLGHP) | ||
5 | 17 | ||
6 | Code moved verbatim. | 18 | As with FEAT_ETS, QEMU is already compliant, because we do not |
19 | reorder translation table walk memory accesses relative to other | ||
20 | memory accesses, and we always guarantee to have finished TLB | ||
21 | maintenance as soon as the TLB op is done. | ||
7 | 22 | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 23 | Update the documentation to list FEAT_ETS2 instead of the |
24 | no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers. | ||
25 | |||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 28 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 29 | Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | 30 | --- |
14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ | 31 | docs/system/arm/emulation.rst | 2 +- |
15 | target/arm/cpu.h | 91 ----------------------------------------- | 32 | target/arm/tcg/cpu32.c | 2 +- |
16 | 2 files changed, 98 insertions(+), 91 deletions(-) | 33 | target/arm/tcg/cpu64.c | 2 +- |
34 | 3 files changed, 3 insertions(+), 3 deletions(-) | ||
17 | 35 | ||
18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 36 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
19 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpregs.h | 38 | --- a/docs/system/arm/emulation.rst |
21 | +++ b/target/arm/cpregs.h | 39 | +++ b/docs/system/arm/emulation.rst |
22 | @@ -XXX,XX +XXX,XX @@ enum { | 40 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
23 | ARM_CP_SME = 1 << 19, | 41 | - FEAT_EL2 (Support for execution at EL2) |
24 | }; | 42 | - FEAT_EL3 (Support for execution at EL3) |
25 | 43 | - FEAT_EPAC (Enhanced pointer authentication) | |
26 | +/* | 44 | -- FEAT_ETS (Enhanced Translation Synchronization) |
27 | + * Interface for defining coprocessor registers. | 45 | +- FEAT_ETS2 (Enhanced Translation Synchronization) |
28 | + * Registers are defined in tables of arm_cp_reginfo structs | 46 | - FEAT_EVT (Enhanced Virtualization Traps) |
29 | + * which are passed to define_arm_cp_regs(). | 47 | - FEAT_F32MM (Single-precision Matrix Multiplication) |
30 | + */ | 48 | - FEAT_F64MM (Double-precision Matrix Multiplication) |
31 | + | 49 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
32 | +/* | ||
33 | + * When looking up a coprocessor register we look for it | ||
34 | + * via an integer which encodes all of: | ||
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | ||
50 | +/* | ||
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | ||
58 | +/* | ||
59 | + * To enable banking of coprocessor registers depending on ns-bit we | ||
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | ||
61 | + * hashtable. | ||
62 | + */ | ||
63 | +#define CP_REG_NS_SHIFT 29 | ||
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
65 | + | ||
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
69 | + | ||
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
71 | + (CP_REG_AA64_MASK | \ | ||
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | ||
79 | +/* | ||
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
81 | + * version used as a key for the coprocessor register hashtable | ||
82 | + */ | ||
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
84 | +{ | ||
85 | + uint32_t cpregid = kvmid; | ||
86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
87 | + cpregid |= CP_REG_AA64_MASK; | ||
88 | + } else { | ||
89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | ||
95 | + * entries. | ||
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | ||
99 | + return cpregid; | ||
100 | +} | ||
101 | + | ||
102 | +/* | ||
103 | + * Convert a truncated 32 bit hashtable key into the full | ||
104 | + * 64 bit KVM register ID. | ||
105 | + */ | ||
106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
107 | +{ | ||
108 | + uint64_t kvmid; | ||
109 | + | ||
110 | + if (cpregid & CP_REG_AA64_MASK) { | ||
111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
113 | + } else { | ||
114 | + kvmid = cpregid & ~(1 << 15); | ||
115 | + if (cpregid & (1 << 15)) { | ||
116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
117 | + } else { | ||
118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
119 | + } | ||
120 | + } | ||
121 | + return kvmid; | ||
122 | +} | ||
123 | + | ||
124 | /* | ||
125 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
126 | * the AArch32 and AArch64 execution states this register is visible in. | ||
127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
128 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
129 | --- a/target/arm/cpu.h | 51 | --- a/target/arm/tcg/cpu32.c |
130 | +++ b/target/arm/cpu.h | 52 | +++ b/target/arm/tcg/cpu32.c |
131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | 53 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | 54 | cpu->isar.id_mmfr4 = t; |
133 | uint32_t cur_el, bool secure); | 55 | |
134 | 56 | t = cpu->isar.id_mmfr5; | |
135 | -/* Interface for defining coprocessor registers. | 57 | - t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ |
136 | - * Registers are defined in tables of arm_cp_reginfo structs | 58 | + t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */ |
137 | - * which are passed to define_arm_cp_regs(). | 59 | cpu->isar.id_mmfr5 = t; |
138 | - */ | 60 | |
139 | - | 61 | t = cpu->isar.id_pfr0; |
140 | -/* When looking up a coprocessor register we look for it | 62 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
141 | - * via an integer which encodes all of: | 63 | index XXXXXXX..XXXXXXX 100644 |
142 | - * coprocessor number | 64 | --- a/target/arm/tcg/cpu64.c |
143 | - * Crn, Crm, opc1, opc2 fields | 65 | +++ b/target/arm/tcg/cpu64.c |
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | 66 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
145 | - * or via MRRC/MCRR?) | 67 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ |
146 | - * non-secure/secure bank (AArch32 only) | 68 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ |
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | 69 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ |
148 | - * (In this case crn and opc2 should be zero.) | 70 | - t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */ |
149 | - * For AArch64, there is no 32/64 bit size distinction; | 71 | + t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */ |
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | 72 | t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ |
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | 73 | t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */ |
152 | - * to be easy to convert to and from the KVM encodings, and also | 74 | cpu->isar.id_aa64mmfr1 = t; |
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
188 | -{ | ||
189 | - uint32_t cpregid = kvmid; | ||
190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
191 | - cpregid |= CP_REG_AA64_MASK; | ||
192 | - } else { | ||
193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
201 | - } | ||
202 | - return cpregid; | ||
203 | -} | ||
204 | - | ||
205 | -/* Convert a truncated 32 bit hashtable key into the full | ||
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
209 | -{ | ||
210 | - uint64_t kvmid; | ||
211 | - | ||
212 | - if (cpregid & CP_REG_AA64_MASK) { | ||
213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
215 | - } else { | ||
216 | - kvmid = cpregid & ~(1 << 15); | ||
217 | - if (cpregid & (1 << 15)) { | ||
218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
219 | - } else { | ||
220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
221 | - } | ||
222 | - } | ||
223 | - return kvmid; | ||
224 | -} | ||
225 | - | ||
226 | /* Return the highest implemented Exception Level */ | ||
227 | static inline int arm_highest_el(CPUARMState *env) | ||
228 | { | ||
229 | -- | 75 | -- |
230 | 2.34.1 | 76 | 2.34.1 |
231 | 77 | ||
232 | 78 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Newer versions of the Arm ARM (e.g. rev K.a) now define fields for |
---|---|---|---|
2 | ID_AA64MMFR3_EL1. Implement this register, so that we can set the | ||
3 | fields if we need to. There's no behaviour change here since we | ||
4 | don't currently set the register value to non-zero. | ||
2 | 5 | ||
3 | Although the 'eabi' field is only used in user emulation where | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | CPU reset doesn't occur, it doesn't belong to the area to reset. | ||
5 | Move it after the 'end_reset_fields' for consistency. | ||
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20230206223502.25122-7-philmd@linaro.org | 9 | Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | 10 | --- |
12 | target/arm/cpu.h | 9 ++++----- | 11 | target/arm/cpu.h | 17 +++++++++++++++++ |
13 | 1 file changed, 4 insertions(+), 5 deletions(-) | 12 | target/arm/helper.c | 6 ++++-- |
13 | target/arm/hvf/hvf.c | 2 ++ | ||
14 | target/arm/kvm.c | 2 ++ | ||
15 | 4 files changed, 25 insertions(+), 2 deletions(-) | ||
14 | 16 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu.h |
18 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu.h |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 21 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; | 22 | uint64_t id_aa64mmfr0; |
23 | uint64_t id_aa64mmfr1; | ||
24 | uint64_t id_aa64mmfr2; | ||
25 | + uint64_t id_aa64mmfr3; | ||
26 | uint64_t id_aa64dfr0; | ||
27 | uint64_t id_aa64dfr1; | ||
28 | uint64_t id_aa64zfr0; | ||
29 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) | ||
30 | FIELD(ID_AA64MMFR2, EVT, 56, 4) | ||
31 | FIELD(ID_AA64MMFR2, E0PD, 60, 4) | ||
32 | |||
33 | +FIELD(ID_AA64MMFR3, TCRX, 0, 4) | ||
34 | +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) | ||
35 | +FIELD(ID_AA64MMFR3, S1PIE, 8, 4) | ||
36 | +FIELD(ID_AA64MMFR3, S2PIE, 12, 4) | ||
37 | +FIELD(ID_AA64MMFR3, S1POE, 16, 4) | ||
38 | +FIELD(ID_AA64MMFR3, S2POE, 20, 4) | ||
39 | +FIELD(ID_AA64MMFR3, AIE, 24, 4) | ||
40 | +FIELD(ID_AA64MMFR3, MEC, 28, 4) | ||
41 | +FIELD(ID_AA64MMFR3, D128, 32, 4) | ||
42 | +FIELD(ID_AA64MMFR3, D128_2, 36, 4) | ||
43 | +FIELD(ID_AA64MMFR3, SNERR, 40, 4) | ||
44 | +FIELD(ID_AA64MMFR3, ANERR, 44, 4) | ||
45 | +FIELD(ID_AA64MMFR3, SDERR, 52, 4) | ||
46 | +FIELD(ID_AA64MMFR3, ADERR, 56, 4) | ||
47 | +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) | ||
48 | + | ||
49 | FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) | ||
50 | FIELD(ID_AA64DFR0, TRACEVER, 4, 4) | ||
51 | FIELD(ID_AA64DFR0, PMUVER, 8, 4) | ||
52 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/helper.c | ||
55 | +++ b/target/arm/helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
57 | .access = PL1_R, .type = ARM_CP_CONST, | ||
58 | .accessfn = access_aa64_tid3, | ||
59 | .resetvalue = cpu->isar.id_aa64mmfr2 }, | ||
60 | - { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
61 | + { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64, | ||
62 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | ||
63 | .access = PL1_R, .type = ARM_CP_CONST, | ||
64 | .accessfn = access_aa64_tid3, | ||
65 | - .resetvalue = 0 }, | ||
66 | + .resetvalue = cpu->isar.id_aa64mmfr3 }, | ||
67 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
68 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | ||
69 | .access = PL1_R, .type = ARM_CP_CONST, | ||
70 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
71 | .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, | ||
72 | { .name = "ID_AA64MMFR2_EL1", | ||
73 | .exported_bits = R_ID_AA64MMFR2_AT_MASK }, | ||
74 | + { .name = "ID_AA64MMFR3_EL1", | ||
75 | + .exported_bits = 0 }, | ||
76 | { .name = "ID_AA64MMFR*_EL1_RESERVED", | ||
77 | .is_glob = true }, | ||
78 | { .name = "ID_AA64DFR0_EL1", | ||
79 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/target/arm/hvf/hvf.c | ||
82 | +++ b/target/arm/hvf/hvf.c | ||
83 | @@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = { | ||
21 | #endif | 84 | #endif |
22 | 85 | { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, | |
23 | -#if defined(CONFIG_USER_ONLY) | 86 | { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, |
24 | - /* For usermode syscall translation. */ | 87 | + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ |
25 | - bool eabi; | 88 | |
26 | -#endif | 89 | { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, |
27 | - | 90 | { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, |
28 | struct CPUBreakpoint *cpu_breakpoint[16]; | 91 | @@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
29 | struct CPUWatchpoint *cpu_watchpoint[16]; | 92 | { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, |
30 | 93 | { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, | |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 94 | { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, |
32 | const struct arm_boot_info *boot_info; | 95 | + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ |
33 | /* Store GICv3CPUState to access from this struct */ | 96 | }; |
34 | void *gicv3state; | 97 | hv_vcpu_t fd; |
35 | +#if defined(CONFIG_USER_ONLY) | 98 | hv_return_t r = HV_SUCCESS; |
36 | + /* For usermode syscall translation. */ | 99 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c |
37 | + bool eabi; | 100 | index XXXXXXX..XXXXXXX 100644 |
38 | +#endif /* CONFIG_USER_ONLY */ | 101 | --- a/target/arm/kvm.c |
39 | 102 | +++ b/target/arm/kvm.c | |
40 | #ifdef TARGET_TAGGED_ADDRESSES | 103 | @@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
41 | /* Linux syscall tagged address support */ | 104 | ARM64_SYS_REG(3, 0, 0, 7, 1)); |
105 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, | ||
106 | ARM64_SYS_REG(3, 0, 0, 7, 2)); | ||
107 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, | ||
108 | + ARM64_SYS_REG(3, 0, 0, 7, 3)); | ||
109 | |||
110 | /* | ||
111 | * Note that if AArch32 support is not present in the host, | ||
42 | -- | 112 | -- |
43 | 2.34.1 | 113 | 2.34.1 |
44 | 114 | ||
45 | 115 | diff view generated by jsdifflib |
1 | From: Claudio Fontana <cfontana@suse.de> | 1 | FEAT_Spec_FPACC is a feature describing speculative behaviour in the |
---|---|---|---|
2 | event of a PAC authontication failure when FEAT_FPACCOMBINE is | ||
3 | implemented. FEAT_Spec_FPACC means that the speculative use of | ||
4 | pointers processed by a PAC Authentication is not materially | ||
5 | different in terms of the impact on cached microarchitectural state | ||
6 | (caches, TLBs, etc) between passing and failing of the PAC | ||
7 | Authentication. | ||
2 | 8 | ||
3 | make it clearer from the name that this is a tcg-only function. | 9 | QEMU doesn't do speculative execution, so we can advertise |
10 | this feature. | ||
4 | 11 | ||
5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 15 | Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | 16 | --- |
12 | target/arm/helper.c | 4 ++-- | 17 | docs/system/arm/emulation.rst | 1 + |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 18 | target/arm/tcg/cpu64.c | 4 ++++ |
19 | 2 files changed, 5 insertions(+) | ||
14 | 20 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 21 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 23 | --- a/docs/system/arm/emulation.rst |
18 | +++ b/target/arm/helper.c | 24 | +++ b/docs/system/arm/emulation.rst |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 25 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
20 | * trapped to the hypervisor in KVM. | 26 | - FEAT_FP16 (Half-precision floating-point data processing) |
21 | */ | 27 | - FEAT_FPAC (Faulting on AUT* instructions) |
22 | #ifdef CONFIG_TCG | 28 | - FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) |
23 | -static void handle_semihosting(CPUState *cs) | 29 | +- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions) |
24 | +static void tcg_handle_semihosting(CPUState *cs) | 30 | - FEAT_FRINTTS (Floating-point to integer instructions) |
25 | { | 31 | - FEAT_FlagM (Flag manipulation instructions v2) |
26 | ARMCPU *cpu = ARM_CPU(cs); | 32 | - FEAT_FlagM2 (Enhancements to flag manipulation instructions) |
27 | CPUARMState *env = &cpu->env; | 33 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | 34 | index XXXXXXX..XXXXXXX 100644 |
29 | */ | 35 | --- a/target/arm/tcg/cpu64.c |
30 | #ifdef CONFIG_TCG | 36 | +++ b/target/arm/tcg/cpu64.c |
31 | if (cs->exception_index == EXCP_SEMIHOST) { | 37 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
32 | - handle_semihosting(cs); | 38 | t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ |
33 | + tcg_handle_semihosting(cs); | 39 | cpu->isar.id_aa64mmfr2 = t; |
34 | return; | 40 | |
35 | } | 41 | + t = cpu->isar.id_aa64mmfr3; |
36 | #endif | 42 | + t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ |
43 | + cpu->isar.id_aa64mmfr3 = t; | ||
44 | + | ||
45 | t = cpu->isar.id_aa64zfr0; | ||
46 | t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); | ||
47 | t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ | ||
37 | -- | 48 | -- |
38 | 2.34.1 | 49 | 2.34.1 |
39 | 50 | ||
40 | 51 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | The Linux kernel 5.10.16 binary for sunxi has been removed from |
---|---|---|---|
2 | apt.armbian.com. This means that the avocado tests for these machines | ||
3 | will be skipped (status CANCEL) if the old binary isn't present in | ||
4 | the avocado cache. | ||
2 | 5 | ||
3 | This allows the test to be skipped when TCG is not present in the QEMU | 6 | Update to 6.6.16, in the same way we did in commit e384db41d8661 |
4 | binary. | 7 | when we moved to 5.10.16 in 2021. |
5 | 8 | ||
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 9 | Cc: qemu-stable@nongnu.org |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284 |
8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
13 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
14 | Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
15 | Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org | ||
10 | --- | 16 | --- |
11 | tests/avocado/boot_linux_console.py | 1 + | 17 | tests/avocado/boot_linux_console.py | 70 ++++++++++++++--------------- |
12 | tests/avocado/reverse_debugging.py | 8 ++++++++ | 18 | tests/avocado/replay_kernel.py | 8 ++-- |
13 | 2 files changed, 9 insertions(+) | 19 | 2 files changed, 39 insertions(+), 39 deletions(-) |
14 | 20 | ||
15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py | 21 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py |
16 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/tests/avocado/boot_linux_console.py | 23 | --- a/tests/avocado/boot_linux_console.py |
18 | +++ b/tests/avocado/boot_linux_console.py | 24 | +++ b/tests/avocado/boot_linux_console.py |
19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): | 25 | @@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self): |
20 | 26 | :avocado: tags=accel:tcg | |
21 | def test_aarch64_raspi3_atf(self): | ||
22 | """ | 27 | """ |
23 | + :avocado: tags=accel:tcg | 28 | deb_url = ('https://apt.armbian.com/pool/main/l/' |
24 | :avocado: tags=arch:aarch64 | 29 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') |
25 | :avocado: tags=machine:raspi3b | 30 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' |
26 | :avocado: tags=cpu:cortex-a53 | 31 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') |
27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py | 32 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' |
33 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
34 | kernel_path = self.extract_from_deb(deb_path, | ||
35 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
36 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' | ||
37 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
38 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' | ||
39 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
40 | initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
41 | '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self): | ||
43 | :avocado: tags=accel:tcg | ||
44 | """ | ||
45 | deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
46 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') | ||
47 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
48 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
49 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
50 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
51 | kernel_path = self.extract_from_deb(deb_path, | ||
52 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
53 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' | ||
54 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
55 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' | ||
56 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
57 | rootfs_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
58 | '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
59 | @@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self): | ||
60 | :avocado: tags=machine:bpim2u | ||
61 | :avocado: tags=accel:tcg | ||
62 | """ | ||
63 | - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' | ||
64 | - 'linux-image-current-sunxi_21.02.2_armhf.deb') | ||
65 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
66 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
67 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
68 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
69 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
70 | kernel_path = self.extract_from_deb(deb_path, | ||
71 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
72 | - dtb_path = ('/usr/lib/linux-image-current-sunxi/' | ||
73 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
74 | + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' | ||
75 | 'sun8i-r40-bananapi-m2-ultra.dtb') | ||
76 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self): | ||
79 | :avocado: tags=accel:tcg | ||
80 | :avocado: tags=machine:bpim2u | ||
81 | """ | ||
82 | - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' | ||
83 | - 'linux-image-current-sunxi_21.02.2_armhf.deb') | ||
84 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
85 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
86 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
87 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
88 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
89 | kernel_path = self.extract_from_deb(deb_path, | ||
90 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
91 | - dtb_path = ('/usr/lib/linux-image-current-sunxi/' | ||
92 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
93 | + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' | ||
94 | 'sun8i-r40-bananapi-m2-ultra.dtb') | ||
95 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
96 | initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
97 | @@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self): | ||
98 | """ | ||
99 | self.require_netdev('user') | ||
100 | |||
101 | - deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/' | ||
102 | - 'linux-image-current-sunxi_21.02.2_armhf.deb') | ||
103 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
104 | + deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
105 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
106 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
107 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
108 | kernel_path = self.extract_from_deb(deb_path, | ||
109 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
110 | - dtb_path = ('/usr/lib/linux-image-current-sunxi/' | ||
111 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
112 | + dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/' | ||
113 | 'sun8i-r40-bananapi-m2-ultra.dtb') | ||
114 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
115 | rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' | ||
116 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self): | ||
117 | :avocado: tags=accel:tcg | ||
118 | """ | ||
119 | deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
120 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') | ||
121 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
122 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
123 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
124 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
125 | kernel_path = self.extract_from_deb(deb_path, | ||
126 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
127 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
128 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
129 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
130 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
131 | |||
132 | self.vm.set_console() | ||
133 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self): | ||
134 | :avocado: tags=machine:orangepi-pc | ||
135 | """ | ||
136 | deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
137 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') | ||
138 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
139 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
140 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
141 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
142 | kernel_path = self.extract_from_deb(deb_path, | ||
143 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
144 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
145 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
146 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
147 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
148 | initrd_url = ('https://github.com/groeck/linux-build-test/raw/' | ||
149 | '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' | ||
150 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self): | ||
151 | self.require_netdev('user') | ||
152 | |||
153 | deb_url = ('https://apt.armbian.com/pool/main/l/' | ||
154 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') | ||
155 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' | ||
156 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') | ||
157 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' | ||
158 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) | ||
159 | kernel_path = self.extract_from_deb(deb_path, | ||
160 | - '/boot/vmlinuz-5.10.16-sunxi') | ||
161 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
162 | + '/boot/vmlinuz-6.6.16-current-sunxi') | ||
163 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb' | ||
164 | dtb_path = self.extract_from_deb(deb_path, dtb_path) | ||
165 | rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/' | ||
166 | 'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz') | ||
167 | diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py | ||
28 | index XXXXXXX..XXXXXXX 100644 | 168 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/tests/avocado/reverse_debugging.py | 169 | --- a/tests/avocado/replay_kernel.py |
30 | +++ b/tests/avocado/reverse_debugging.py | 170 | +++ b/tests/avocado/replay_kernel.py |
31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): | 171 | @@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self): |
32 | vm.shutdown() | 172 | :avocado: tags=machine:cubieboard |
33 | 173 | """ | |
34 | class ReverseDebugging_X86_64(ReverseDebugging): | 174 | deb_url = ('https://apt.armbian.com/pool/main/l/' |
35 | + """ | 175 | - 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb') |
36 | + :avocado: tags=accel:tcg | 176 | - deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0' |
37 | + """ | 177 | + 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb') |
38 | + | 178 | + deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b' |
39 | REG_PC = 0x10 | 179 | deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) |
40 | REG_CS = 0x12 | 180 | kernel_path = self.extract_from_deb(deb_path, |
41 | def get_pc(self, g): | 181 | - '/boot/vmlinuz-5.10.16-sunxi') |
42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): | 182 | - dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb' |
43 | self.reverse_debugging() | 183 | + '/boot/vmlinuz-6.6.16-current-sunxi') |
44 | 184 | + dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb' | |
45 | class ReverseDebugging_AArch64(ReverseDebugging): | 185 | dtb_path = self.extract_from_deb(deb_path, dtb_path) |
46 | + """ | 186 | initrd_url = ('https://github.com/groeck/linux-build-test/raw/' |
47 | + :avocado: tags=accel:tcg | 187 | '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' |
48 | + """ | ||
49 | + | ||
50 | REG_PC = 32 | ||
51 | |||
52 | # unidentified gitlab timeout problem | ||
53 | -- | 188 | -- |
54 | 2.34.1 | 189 | 2.34.1 |
55 | |||
56 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | The generic timer frequency is settable by board code via a QOM |
---|---|---|---|
2 | property "cntfrq", but otherwise defaults to 62.5MHz. The way this | ||
3 | is done includes some complication resulting from how this was | ||
4 | originally a fixed value with no QOM property. Clean it up: | ||
2 | 5 | ||
3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() | 6 | * always set cpu->gt_cntfrq_hz to some sensible value, whether |
4 | are only used for system emulation in m_helper.c. | 7 | the CPU has the generic timer or not, and whether it's system |
5 | Move the definitions to avoid prototype forward declarations. | 8 | or user-only emulation |
9 | * this means we can always use gt_cntfrq_hz, and never need | ||
10 | the old GTIMER_SCALE define | ||
11 | * set the default value in exactly one place, in the realize fn | ||
6 | 12 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 13 | The aim here is to pave the way for handling the ARMv8.6 requirement |
14 | that the generic timer frequency is always 1GHz. We're going to do | ||
15 | that by having old CPU types keep their legacy-in-QEMU behaviour and | ||
16 | having the default for any new CPU types be a 1GHz rather han 62.5MHz | ||
17 | cntfrq, so we want the point where the default is decided to be in | ||
18 | one place, and in code, not in a DEFINE_PROP_UINT64() initializer. | ||
19 | |||
20 | This commit should have no behavioural changes. | ||
21 | |||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230206223502.25122-4-philmd@linaro.org | 25 | Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | 26 | --- |
12 | target/arm/internals.h | 14 -------- | 27 | target/arm/internals.h | 7 ++++--- |
13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- | 28 | target/arm/cpu.c | 31 +++++++++++++++++-------------- |
14 | 2 files changed, 37 insertions(+), 51 deletions(-) | 29 | target/arm/helper.c | 16 ++++++++-------- |
30 | 3 files changed, 29 insertions(+), 25 deletions(-) | ||
15 | 31 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 32 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
17 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 34 | --- a/target/arm/internals.h |
19 | +++ b/target/arm/internals.h | 35 | +++ b/target/arm/internals.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) | 36 | @@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp) |
21 | 37 | || excp == EXCP_SEMIHOST; | |
22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); | 38 | } |
23 | 39 | ||
24 | -/* | 40 | -/* Scale factor for generic timers, ie number of ns per tick. |
25 | - * Return the MMU index for a v7M CPU with all relevant information | 41 | - * This gives a 62.5MHz timer. |
26 | - * manually specified. | 42 | +/* |
27 | - */ | 43 | + * Default frequency for the generic timer, in Hz. |
28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 44 | + * This is 62.5MHz, which gives a 16 ns tick period. |
29 | - bool secstate, bool priv, bool negpri); | 45 | */ |
30 | - | 46 | -#define GTIMER_SCALE 16 |
31 | -/* | 47 | +#define GTIMER_DEFAULT_HZ 62500000 |
32 | - * Return the MMU index for a v7M CPU in the specified security and | 48 | |
33 | - * privilege state. | 49 | /* Bit definitions for the v7M CONTROL register */ |
34 | - */ | 50 | FIELD(V7M_CONTROL, NPRIV, 0, 1) |
35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 51 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
36 | - bool secstate, bool priv); | ||
37 | - | ||
38 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | ||
40 | |||
41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/target/arm/m_helper.c | 53 | --- a/target/arm/cpu.c |
44 | +++ b/target/arm/m_helper.c | 54 | +++ b/target/arm/cpu.c |
45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 55 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj) |
46 | 56 | } | |
47 | #else /* !CONFIG_USER_ONLY */ | 57 | } |
48 | 58 | ||
49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 59 | +/* |
50 | + bool secstate, bool priv, bool negpri) | 60 | + * 0 means "unset, use the default value". That default might vary depending |
51 | +{ | 61 | + * on the CPU type, and is set in the realize fn. |
52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | 62 | + */ |
53 | + | 63 | static Property arm_cpu_gt_cntfrq_property = |
54 | + if (priv) { | 64 | - DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, |
55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; | 65 | - NANOSECONDS_PER_SECOND / GTIMER_SCALE); |
66 | + DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0); | ||
67 | |||
68 | static Property arm_cpu_reset_cbar_property = | ||
69 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); | ||
70 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
71 | return; | ||
72 | } | ||
73 | |||
74 | + if (!cpu->gt_cntfrq_hz) { | ||
75 | + /* | ||
76 | + * 0 means "the board didn't set a value, use the default". | ||
77 | + * The default value of the generic timer frequency (as seen in | ||
78 | + * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns. | ||
79 | + * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the | ||
80 | + * board doesn't set it. | ||
81 | + */ | ||
82 | + cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; | ||
56 | + } | 83 | + } |
57 | + | 84 | + |
58 | + if (negpri) { | 85 | #ifndef CONFIG_USER_ONLY |
59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | 86 | /* The NVIC and M-profile CPU are two halves of a single piece of |
60 | + } | 87 | * hardware; trying to use one without the other is a command line |
88 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
89 | } | ||
90 | |||
91 | { | ||
92 | - uint64_t scale; | ||
93 | - | ||
94 | - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { | ||
95 | - if (!cpu->gt_cntfrq_hz) { | ||
96 | - error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", | ||
97 | - cpu->gt_cntfrq_hz); | ||
98 | - return; | ||
99 | - } | ||
100 | - scale = gt_cntfrq_period_ns(cpu); | ||
101 | - } else { | ||
102 | - scale = GTIMER_SCALE; | ||
103 | - } | ||
104 | + uint64_t scale = gt_cntfrq_period_ns(cpu); | ||
105 | |||
106 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale, | ||
107 | arm_gt_ptimer_cb, cpu); | ||
108 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/target/arm/helper.c | ||
111 | +++ b/target/arm/helper.c | ||
112 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
113 | .resetvalue = 0 }, | ||
114 | }; | ||
115 | |||
116 | +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) | ||
117 | +{ | ||
118 | + ARMCPU *cpu = env_archcpu(env); | ||
61 | + | 119 | + |
62 | + if (secstate) { | 120 | + cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; |
63 | + mmu_idx |= ARM_MMU_IDX_M_S; | ||
64 | + } | ||
65 | + | ||
66 | + return mmu_idx; | ||
67 | +} | 121 | +} |
68 | + | 122 | + |
69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 123 | #ifndef CONFIG_USER_ONLY |
70 | + bool secstate, bool priv) | 124 | |
71 | +{ | 125 | static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri, |
72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | 126 | @@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque) |
73 | + | 127 | gt_recalc_timer(cpu, GTIMER_HYPVIRT); |
74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | ||
75 | +} | ||
76 | + | ||
77 | +/* Return the MMU index for a v7M CPU in the specified security state */ | ||
78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
79 | +{ | ||
80 | + bool priv = arm_v7m_is_handler_mode(env) || | ||
81 | + !(env->v7m.control[secstate] & 1); | ||
82 | + | ||
83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
84 | +} | ||
85 | + | ||
86 | /* | ||
87 | * What kind of stack write are we doing? This affects how exceptions | ||
88 | * generated during the stacking are treated. | ||
89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
90 | return tt_resp; | ||
91 | } | 128 | } |
92 | 129 | ||
93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 130 | -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque) |
94 | - bool secstate, bool priv, bool negpri) | ||
95 | -{ | 131 | -{ |
96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | 132 | - ARMCPU *cpu = env_archcpu(env); |
97 | - | 133 | - |
98 | - if (priv) { | 134 | - cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz; |
99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; | ||
100 | - } | ||
101 | - | ||
102 | - if (negpri) { | ||
103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
104 | - } | ||
105 | - | ||
106 | - if (secstate) { | ||
107 | - mmu_idx |= ARM_MMU_IDX_M_S; | ||
108 | - } | ||
109 | - | ||
110 | - return mmu_idx; | ||
111 | -} | 135 | -} |
112 | - | 136 | - |
113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 137 | static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
114 | - bool secstate, bool priv) | 138 | /* |
115 | -{ | 139 | * Note that CNTFRQ is purely reads-as-written for the benefit |
116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | 140 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { |
117 | - | 141 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0, |
118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | 142 | .type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */, |
119 | -} | 143 | .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq), |
120 | - | 144 | - .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE, |
121 | -/* Return the MMU index for a v7M CPU in the specified security state */ | 145 | + .resetfn = arm_gt_cntfrq_reset, |
122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 146 | }, |
123 | -{ | 147 | { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, |
124 | - bool priv = arm_v7m_is_handler_mode(env) || | 148 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, |
125 | - !(env->v7m.control[secstate] & 1); | ||
126 | - | ||
127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
128 | -} | ||
129 | - | ||
130 | #endif /* !CONFIG_USER_ONLY */ | ||
131 | -- | 149 | -- |
132 | 2.34.1 | 150 | 2.34.1 |
133 | 151 | ||
134 | 152 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Currently QEMU CPUs always run with a generic timer counter frequency |
---|---|---|---|
2 | of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of | ||
3 | the TF-A firmware that sbsa-ref runs, the frequency of the generic | ||
4 | timer is hardcoded into the firmware, and so if the CPU actually has | ||
5 | a different frequency then timers in the guest will be set | ||
6 | incorrectly. | ||
2 | 7 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | 8 | The default frequency used by the 'max' CPU is about to change, so |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 9 | make the sbsa-ref board force the CPU frequency to the value which |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | the firmware expects. |
6 | Message-id: 20230206223502.25122-6-philmd@linaro.org | 11 | |
12 | Newer versions of TF-A will read the frequency from the CPU's | ||
13 | CNTFRQ_EL0 register: | ||
14 | https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148 | ||
15 | so in the longer term we could make this board use the 1GHz | ||
16 | frequency. We will need to make sure we update the binaries used | ||
17 | by our avocado test | ||
18 | Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef | ||
19 | before we can do that. | ||
20 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
23 | Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> | ||
24 | Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org | ||
8 | --- | 25 | --- |
9 | linux-user/user-internals.h | 2 +- | 26 | hw/arm/sbsa-ref.c | 15 +++++++++++++++ |
10 | target/arm/cpu.h | 2 +- | 27 | 1 file changed, 15 insertions(+) |
11 | linux-user/arm/cpu_loop.c | 4 ++-- | ||
12 | 3 files changed, 4 insertions(+), 4 deletions(-) | ||
13 | 28 | ||
14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h | 29 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
15 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/linux-user/user-internals.h | 31 | --- a/hw/arm/sbsa-ref.c |
17 | +++ b/linux-user/user-internals.h | 32 | +++ b/hw/arm/sbsa-ref.c |
18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); | 33 | @@ -XXX,XX +XXX,XX @@ |
19 | #ifdef TARGET_ARM | 34 | #define NUM_SMMU_IRQS 4 |
20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) | 35 | #define NUM_SATA_PORTS 6 |
21 | { | 36 | |
22 | - return cpu_env->eabi == 1; | 37 | +/* |
23 | + return cpu_env->eabi; | 38 | + * Generic timer frequency in Hz (which drives both the CPU generic timers |
24 | } | 39 | + * and the SBSA watchdog-timer). Older versions of the TF-A firmware |
25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) | 40 | + * typically used with sbsa-ref (including the binaries in our Avocado test |
26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } | 41 | + * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef |
27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 42 | + * assume it is this value. |
28 | index XXXXXXX..XXXXXXX 100644 | 43 | + * |
29 | --- a/target/arm/cpu.h | 44 | + * TODO: this value is not architecturally correct for an Armv8.6 or |
30 | +++ b/target/arm/cpu.h | 45 | + * better CPU, so we should move to 1GHz once the TF-A fix above has |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 46 | + * made it into a release and into our Avocado test. |
32 | 47 | + */ | |
33 | #if defined(CONFIG_USER_ONLY) | 48 | +#define SBSA_GTIMER_HZ 62500000 |
34 | /* For usermode syscall translation. */ | 49 | + |
35 | - int eabi; | 50 | enum { |
36 | + bool eabi; | 51 | SBSA_FLASH, |
37 | #endif | 52 | SBSA_MEM, |
38 | 53 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine) | |
39 | struct CPUBreakpoint *cpu_breakpoint[16]; | 54 | &error_abort); |
40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | 55 | } |
41 | index XXXXXXX..XXXXXXX 100644 | 56 | |
42 | --- a/linux-user/arm/cpu_loop.c | 57 | + object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort); |
43 | +++ b/linux-user/arm/cpu_loop.c | 58 | + |
44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | 59 | object_property_set_link(cpuobj, "memory", OBJECT(sysmem), |
45 | break; | 60 | &error_abort); |
46 | case EXCP_SWI: | ||
47 | { | ||
48 | - env->eabi = 1; | ||
49 | + env->eabi = true; | ||
50 | /* system call */ | ||
51 | if (env->thumb) { | ||
52 | /* Thumb is always EABI style with syscall number in r7 */ | ||
53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
54 | * > 0xfffff and are handled below as out-of-range. | ||
55 | */ | ||
56 | n ^= ARM_SYSCALL_BASE; | ||
57 | - env->eabi = 0; | ||
58 | + env->eabi = false; | ||
59 | } | ||
60 | } | ||
61 | 61 | ||
62 | -- | 62 | -- |
63 | 2.34.1 | 63 | 2.34.1 |
64 | 64 | ||
65 | 65 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Currently the sbsa_gdwt watchdog device hardcodes its frequency at |
---|---|---|---|
2 | 62.5MHz. In real hardware, this watchdog is supposed to be driven | ||
3 | from the system counter, which also drives the CPU generic timers. | ||
4 | Newer CPU types (in particular from Armv8.6) should have a CPU | ||
5 | generic timer frequency of 1GHz, so we can't leave the watchdog | ||
6 | on the old QEMU default of 62.5GHz. | ||
2 | 7 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Make the frequency a QOM property so it can be set by the board, |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 9 | and have our only board that uses this device set that frequency |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | to the same value it sets the CPU frequency. |
6 | Message-id: 20230206223502.25122-3-philmd@linaro.org | 11 | |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org | ||
8 | --- | 15 | --- |
9 | target/arm/m_helper.c | 11 ++++++++--- | 16 | include/hw/watchdog/sbsa_gwdt.h | 3 +-- |
10 | 1 file changed, 8 insertions(+), 3 deletions(-) | 17 | hw/arm/sbsa-ref.c | 1 + |
18 | hw/watchdog/sbsa_gwdt.c | 15 ++++++++++++++- | ||
19 | 3 files changed, 16 insertions(+), 3 deletions(-) | ||
11 | 20 | ||
12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 21 | diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h |
13 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/m_helper.c | 23 | --- a/include/hw/watchdog/sbsa_gwdt.h |
15 | +++ b/target/arm/m_helper.c | 24 | +++ b/include/hw/watchdog/sbsa_gwdt.h |
16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 25 | @@ -XXX,XX +XXX,XX @@ |
17 | return 0; | 26 | #define SBSA_GWDT_RMMIO_SIZE 0x1000 |
27 | #define SBSA_GWDT_CMMIO_SIZE 0x1000 | ||
28 | |||
29 | -#define SBSA_TIMER_FREQ 62500000 /* Hz */ | ||
30 | - | ||
31 | typedef struct SBSA_GWDTState { | ||
32 | /* <private> */ | ||
33 | SysBusDevice parent_obj; | ||
34 | @@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState { | ||
35 | qemu_irq irq; | ||
36 | |||
37 | QEMUTimer *timer; | ||
38 | + uint64_t freq; | ||
39 | |||
40 | uint32_t id; | ||
41 | uint32_t wcs; | ||
42 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/arm/sbsa-ref.c | ||
45 | +++ b/hw/arm/sbsa-ref.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms) | ||
47 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | ||
48 | int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0]; | ||
49 | |||
50 | + qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ); | ||
51 | sysbus_realize_and_unref(s, &error_fatal); | ||
52 | sysbus_mmio_map(s, 0, rbase); | ||
53 | sysbus_mmio_map(s, 1, cbase); | ||
54 | diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/watchdog/sbsa_gwdt.c | ||
57 | +++ b/hw/watchdog/sbsa_gwdt.c | ||
58 | @@ -XXX,XX +XXX,XX @@ | ||
59 | #include "qemu/osdep.h" | ||
60 | #include "sysemu/reset.h" | ||
61 | #include "sysemu/watchdog.h" | ||
62 | +#include "hw/qdev-properties.h" | ||
63 | #include "hw/watchdog/sbsa_gwdt.h" | ||
64 | #include "qemu/timer.h" | ||
65 | #include "migration/vmstate.h" | ||
66 | @@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype) | ||
67 | timeout = s->woru; | ||
68 | timeout <<= 32; | ||
69 | timeout |= s->worl; | ||
70 | - timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ); | ||
71 | + timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq); | ||
72 | timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
73 | |||
74 | if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) && | ||
75 | @@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp) | ||
76 | dev); | ||
18 | } | 77 | } |
19 | 78 | ||
20 | -#else | 79 | +static Property wdt_sbsa_gwdt_props[] = { |
21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 80 | + /* |
22 | +{ | 81 | + * Timer frequency in Hz. This must match the frequency used by |
23 | + return ARMMMUIdx_MUser; | 82 | + * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy |
24 | +} | 83 | + * CPU timer frequency default. |
84 | + */ | ||
85 | + DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq, | ||
86 | + 62500000), | ||
87 | + DEFINE_PROP_END_OF_LIST(), | ||
88 | +}; | ||
25 | + | 89 | + |
26 | +#else /* !CONFIG_USER_ONLY */ | 90 | static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) |
27 | 91 | { | |
28 | /* | 92 | DeviceClass *dc = DEVICE_CLASS(klass); |
29 | * What kind of stack write are we doing? This affects how exceptions | 93 | @@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) |
30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 94 | set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories); |
31 | return tt_resp; | 95 | dc->vmsd = &vmstate_sbsa_gwdt; |
96 | dc->desc = "SBSA-compliant generic watchdog device"; | ||
97 | + device_class_set_props(dc, wdt_sbsa_gwdt_props); | ||
32 | } | 98 | } |
33 | 99 | ||
34 | -#endif /* !CONFIG_USER_ONLY */ | 100 | static const TypeInfo wdt_sbsa_gwdt_info = { |
35 | - | ||
36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
37 | bool secstate, bool priv, bool negpri) | ||
38 | { | ||
39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
40 | |||
41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
42 | } | ||
43 | + | ||
44 | +#endif /* !CONFIG_USER_ONLY */ | ||
45 | -- | 101 | -- |
46 | 2.34.1 | 102 | 2.34.1 |
47 | 103 | ||
48 | 104 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | In previous versions of the Arm architecture, the frequency of the |
---|---|---|---|
2 | 2 | generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, | |
3 | There is no point in using a void pointer to access the NVIC. | 3 | and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. |
4 | Use the real type to avoid casting it while debugging. | 4 | In Armv8.6, the architecture standardized this frequency to 1GHz. |
5 | 5 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | Because there is no ID register feature field that indicates whether |
7 | a CPU is v8.6 or that it ought to have this counter frequency, we | ||
8 | implement this by changing our default CNTFRQ value for all CPUs, | ||
9 | with exceptions for backwards compatibility: | ||
10 | |||
11 | * CPU types which we already implement will retain the old | ||
12 | default value. None of these are v8.6 CPUs, so this is | ||
13 | architecturally OK. | ||
14 | * CPUs used in versioned machine types with a version of 9.0 | ||
15 | or earlier will retain the old default value. | ||
16 | |||
17 | The upshot is that the only CPU type that changes is 'max'; but any | ||
18 | new type we add in future (whether v8.6 or not) will also get the new | ||
19 | 1GHz default. | ||
20 | |||
21 | It remains the case that the machine model can override the default | ||
22 | value via the 'cntfrq' QOM property (regardless of the CPU type). | ||
23 | |||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20230206223502.25122-11-philmd@linaro.org | 26 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org |
10 | --- | 28 | --- |
11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- | 29 | target/arm/cpu.h | 11 +++++++++++ |
12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- | 30 | target/arm/internals.h | 12 ++++++++++-- |
13 | target/arm/cpu.c | 1 + | 31 | hw/core/machine.c | 4 +++- |
14 | target/arm/m_helper.c | 2 +- | 32 | target/arm/cpu.c | 23 +++++++++++++++++------ |
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | 33 | target/arm/cpu64.c | 2 ++ |
34 | target/arm/tcg/cpu32.c | 4 ++++ | ||
35 | target/arm/tcg/cpu64.c | 18 ++++++++++++++++++ | ||
36 | 7 files changed, 65 insertions(+), 9 deletions(-) | ||
16 | 37 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 38 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 40 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 41 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { | 42 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
22 | 43 | */ | |
23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | 44 | bool host_cpu_probe_failed; |
24 | 45 | ||
25 | +typedef struct NVICState NVICState; | 46 | + /* QOM property to indicate we should use the back-compat CNTFRQ default */ |
47 | + bool backcompat_cntfrq; | ||
26 | + | 48 | + |
27 | typedef struct CPUArchState { | 49 | /* Specify the number of cores in this CPU cluster. Used for the L2CTLR |
28 | /* Regs for current mode. */ | 50 | * register. |
29 | uint32_t regs[16]; | 51 | */ |
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 52 | @@ -XXX,XX +XXX,XX @@ enum arm_features { |
31 | } sau; | 53 | ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ |
32 | 54 | ARM_FEATURE_M_MAIN, /* M profile Main Extension */ | |
33 | #if !defined(CONFIG_USER_ONLY) | 55 | ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ |
34 | - void *nvic; | 56 | + /* |
35 | + NVICState *nvic; | 57 | + * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz |
36 | const struct arm_boot_info *boot_info; | 58 | + * if the board doesn't set a value, instead of 1GHz. It is for backwards |
37 | /* Store GICv3CPUState to access from this struct */ | 59 | + * compatibility and used only with CPU definitions that were already |
38 | void *gicv3state; | 60 | + * in QEMU before we changed the default. It should not be set on any |
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | 61 | + * CPU types added in future. |
40 | 62 | + */ | |
41 | /* Interface between CPU and Interrupt controller. */ | 63 | + ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */ |
42 | #ifndef CONFIG_USER_ONLY | 64 | }; |
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | 65 | |
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | 66 | static inline int arm_feature(CPUARMState *env, int feature) |
45 | #else | 67 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | 68 | index XXXXXXX..XXXXXXX 100644 |
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | 69 | --- a/target/arm/internals.h |
48 | { | 70 | +++ b/target/arm/internals.h |
49 | return true; | 71 | @@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp) |
50 | } | 72 | |
51 | #endif | 73 | /* |
52 | /** | 74 | * Default frequency for the generic timer, in Hz. |
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | 75 | - * This is 62.5MHz, which gives a 16 ns tick period. |
54 | - * @opaque: the NVIC | 76 | + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before |
55 | + * @s: the NVIC | 77 | + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, |
56 | * @irq: the exception number to mark pending | 78 | + * which gives a 16ns tick period. |
57 | * @secure: false for non-banked exceptions or for the nonsecure | 79 | + * |
58 | * version of a banked exception, true for the secure version of a banked | 80 | + * We will use the back-compat value: |
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | 81 | + * - for QEMU CPU types added before we standardized on 1GHz |
60 | * if @secure is true and @irq does not specify one of the fixed set | 82 | + * - for versioned machine types with a version of 9.0 or earlier |
61 | * of architecturally banked exceptions. | 83 | + * In any case, the machine model may override via the cntfrq property. |
62 | */ | 84 | */ |
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | 85 | -#define GTIMER_DEFAULT_HZ 62500000 |
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | 86 | +#define GTIMER_DEFAULT_HZ 1000000000 |
65 | /** | 87 | +#define GTIMER_BACKCOMPAT_HZ 62500000 |
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | 88 | |
67 | - * @opaque: the NVIC | 89 | /* Bit definitions for the v7M CONTROL register */ |
68 | + * @s: the NVIC | 90 | FIELD(V7M_CONTROL, NPRIV, 0, 1) |
69 | * @irq: the exception number to mark pending | 91 | diff --git a/hw/core/machine.c b/hw/core/machine.c |
70 | * @secure: false for non-banked exceptions or for the nonsecure | 92 | index XXXXXXX..XXXXXXX 100644 |
71 | * version of a banked exception, true for the secure version of a banked | 93 | --- a/hw/core/machine.c |
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | 94 | +++ b/hw/core/machine.c |
73 | * exceptions (exceptions generated in the course of trying to take | 95 | @@ -XXX,XX +XXX,XX @@ |
74 | * a different exception). | 96 | #include "hw/virtio/virtio-iommu.h" |
75 | */ | 97 | #include "audio/audio.h" |
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | 98 | |
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | 99 | -GlobalProperty hw_compat_9_0[] = {}; |
78 | /** | 100 | +GlobalProperty hw_compat_9_0[] = { |
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | 101 | + {"arm-cpu", "backcompat-cntfrq", "true" }, |
80 | - * @opaque: the NVIC | 102 | +}; |
81 | + * @s: the NVIC | 103 | const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); |
82 | * @irq: the exception number to mark pending | 104 | |
83 | * @secure: false for non-banked exceptions or for the nonsecure | 105 | GlobalProperty hw_compat_8_2[] = { |
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | ||
174 | --- a/hw/intc/armv7m_nvic.c | ||
175 | +++ b/hw/intc/armv7m_nvic.c | ||
176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | ||
177 | return MIN(running, s->exception_prio); | ||
178 | } | ||
179 | |||
180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
182 | { | ||
183 | /* Return true if the requested execution priority is negative | ||
184 | * for the specified security state, ie that security state | ||
185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
186 | * mean we don't allow FAULTMASK_NS to actually make the execution | ||
187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | ||
188 | */ | ||
189 | - NVICState *s = opaque; | ||
190 | - | ||
191 | if (s->cpu->env.v7m.faultmask[secure]) { | ||
192 | return true; | ||
193 | } | ||
194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
200 | { | ||
201 | - NVICState *s = opaque; | ||
202 | - | ||
203 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
204 | } | ||
205 | |||
206 | -int armv7m_nvic_raw_execution_priority(void *opaque) | ||
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | ||
227 | } | ||
228 | |||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | ||
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | ||
231 | { | ||
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | ||
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | ||
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 106 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
308 | index XXXXXXX..XXXXXXX 100644 | 107 | index XXXXXXX..XXXXXXX 100644 |
309 | --- a/target/arm/cpu.c | 108 | --- a/target/arm/cpu.c |
310 | +++ b/target/arm/cpu.c | 109 | +++ b/target/arm/cpu.c |
311 | @@ -XXX,XX +XXX,XX @@ | 110 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
312 | #if !defined(CONFIG_USER_ONLY) | 111 | |
313 | #include "hw/loader.h" | 112 | if (!cpu->gt_cntfrq_hz) { |
314 | #include "hw/boards.h" | 113 | /* |
315 | +#include "hw/intc/armv7m_nvic.h" | 114 | - * 0 means "the board didn't set a value, use the default". |
316 | #endif | 115 | - * The default value of the generic timer frequency (as seen in |
317 | #include "sysemu/tcg.h" | 116 | - * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns. |
318 | #include "sysemu/qtest.h" | 117 | - * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the |
319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 118 | - * board doesn't set it. |
320 | index XXXXXXX..XXXXXXX 100644 | 119 | + * 0 means "the board didn't set a value, use the default". (We also |
321 | --- a/target/arm/m_helper.c | 120 | + * get here for the CONFIG_USER_ONLY case.) |
322 | +++ b/target/arm/m_helper.c | 121 | + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before |
323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | 122 | + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, |
324 | * that we will need later in order to do lazy FP reg stacking. | 123 | + * which gives a 16ns tick period. |
325 | */ | 124 | + * |
326 | bool is_secure = env->v7m.secure; | 125 | + * We will use the back-compat value: |
327 | - void *nvic = env->nvic; | 126 | + * - for QEMU CPU types added before we standardized on 1GHz |
328 | + NVICState *nvic = env->nvic; | 127 | + * - for versioned machine types with a version of 9.0 or earlier |
128 | */ | ||
129 | - cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; | ||
130 | + if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || | ||
131 | + cpu->backcompat_cntfrq) { | ||
132 | + cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; | ||
133 | + } else { | ||
134 | + cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; | ||
135 | + } | ||
136 | } | ||
137 | |||
138 | #ifndef CONFIG_USER_ONLY | ||
139 | @@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = { | ||
140 | mp_affinity, ARM64_AFFINITY_INVALID), | ||
141 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), | ||
142 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), | ||
143 | + /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ | ||
144 | + DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), | ||
145 | DEFINE_PROP_END_OF_LIST() | ||
146 | }; | ||
147 | |||
148 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
149 | index XXXXXXX..XXXXXXX 100644 | ||
150 | --- a/target/arm/cpu64.c | ||
151 | +++ b/target/arm/cpu64.c | ||
152 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
153 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
154 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
155 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
156 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
157 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
158 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
159 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
160 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
161 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
162 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
163 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
164 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
165 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
166 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
167 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
168 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
169 | index XXXXXXX..XXXXXXX 100644 | ||
170 | --- a/target/arm/tcg/cpu32.c | ||
171 | +++ b/target/arm/tcg/cpu32.c | ||
172 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
173 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
174 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
175 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
176 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
177 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
178 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
179 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
180 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
181 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
182 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
183 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
184 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
185 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
186 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
187 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
188 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) | ||
189 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
190 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
191 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
192 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
193 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
194 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | ||
195 | cpu->midr = 0x411fd133; /* r1p3 */ | ||
196 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
197 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
198 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
199 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
200 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
201 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
202 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
203 | set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
204 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
205 | index XXXXXXX..XXXXXXX 100644 | ||
206 | --- a/target/arm/tcg/cpu64.c | ||
207 | +++ b/target/arm/tcg/cpu64.c | ||
208 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj) | ||
209 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
210 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
211 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
212 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
213 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
214 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
215 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
216 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj) | ||
217 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
218 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
219 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
220 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
221 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
222 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
223 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
224 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
225 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
226 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
227 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
228 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
229 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
230 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
231 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
232 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj) | ||
233 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
234 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
235 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
236 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
237 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
238 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
239 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
240 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) | ||
241 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
242 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
243 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
244 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
245 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
246 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
247 | set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
248 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj) | ||
249 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
250 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
251 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
252 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
253 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
254 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
255 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
256 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) | ||
257 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
258 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
259 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
260 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
261 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
262 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
263 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
264 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj) | ||
265 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
266 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
267 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
268 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
269 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
270 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
271 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
272 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj) | ||
273 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
274 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
275 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
276 | + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
277 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
278 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
279 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
280 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
281 | uint64_t t; | ||
282 | uint32_t u; | ||
283 | |||
284 | + /* | ||
285 | + * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default | ||
286 | + * to because we started with aarch64_a57_initfn(). A 'max' CPU might | ||
287 | + * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and | ||
288 | + * because it is our "may change" CPU type we are OK with it not being | ||
289 | + * backwards-compatible with how it worked in old QEMU. | ||
290 | + */ | ||
291 | + unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); | ||
292 | + | ||
329 | /* | 293 | /* |
330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits | 294 | * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real |
331 | * are banked and we want to update the bit in the bank for the | 295 | * one and try to apply errata workarounds or use impdef features we |
332 | -- | 296 | -- |
333 | 2.34.1 | 297 | 2.34.1 |
334 | 298 | ||
335 | 299 | diff view generated by jsdifflib |
1 | From: Mostafa Saleh <smostafa@google.com> | 1 | From: Alexandra Diupina <adiupina@astralinux.ru> |
---|---|---|---|
2 | 2 | ||
3 | GBPA register can be used to globally abort all | 3 | The DMA descriptor structures for this device have |
4 | transactions. | 4 | a set of "address extension" fields which extend the 32 |
5 | bit source addresses with an extra 16 bits to give a | ||
6 | 48 bit address: | ||
7 | https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field | ||
5 | 8 | ||
6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". | 9 | However, we misimplemented this address extension in several ways: |
7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to | 10 | * we only extracted 12 bits of the extension fields, not 16 |
8 | be zero(Do not abort incoming transactions). | 11 | * we didn't shift the extension field up far enough |
12 | * we accidentally did the shift as 32-bit arithmetic, which | ||
13 | meant that we would have an overflow instead of setting | ||
14 | bits [47:32] of the resulting 64-bit address | ||
9 | 15 | ||
10 | Other fields have default values of Use Incoming. | 16 | Add a type cast and use extract64() instead of extract32() |
17 | to avoid integer overflow on addition. Fix bit fields | ||
18 | extraction according to documentation. | ||
11 | 19 | ||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | 20 | Found by Linux Verification Center (linuxtesting.org) with SVACE. |
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | 21 | ||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | 22 | Cc: qemu-stable@nongnu.org |
16 | in a new subsection for forward migration compatibility. | 23 | Fixes: d3c6369a96 ("introduce xlnx-dpdma") |
17 | GBPA is only migrated if its value is different from the reset value. | 24 | Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> |
18 | It does this to be backward migration compatible if SW didn't write | 25 | Message-id: 20240428181131.23801-1-adiupina@astralinux.ru |
19 | the register. | 26 | [PMM: adjusted commit message] |
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | --- | 29 | --- |
28 | hw/arm/smmuv3-internal.h | 7 +++++++ | 30 | hw/dma/xlnx_dpdma.c | 20 ++++++++++---------- |
29 | include/hw/arm/smmuv3.h | 1 + | 31 | 1 file changed, 10 insertions(+), 10 deletions(-) |
30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- | ||
31 | 3 files changed, 50 insertions(+), 1 deletion(-) | ||
32 | 32 | ||
33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | 33 | diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c |
34 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/hw/arm/smmuv3-internal.h | 35 | --- a/hw/dma/xlnx_dpdma.c |
36 | +++ b/hw/arm/smmuv3-internal.h | 36 | +++ b/hw/dma/xlnx_dpdma.c |
37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) | 37 | @@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc, |
38 | REG32(CR1, 0x28) | 38 | |
39 | REG32(CR2, 0x2c) | 39 | switch (frag) { |
40 | REG32(STATUSR, 0x40) | 40 | case 0: |
41 | +REG32(GBPA, 0x44) | 41 | - addr = desc->source_address |
42 | + FIELD(GBPA, ABORT, 20, 1) | 42 | - + (extract32(desc->address_extension, 16, 12) << 20); |
43 | + FIELD(GBPA, UPDATE, 31, 1) | 43 | + addr = (uint64_t)desc->source_address |
44 | + | 44 | + + (extract64(desc->address_extension, 16, 16) << 32); |
45 | +/* Use incoming. */ | 45 | break; |
46 | +#define SMMU_GBPA_RESET_VAL 0x1000 | 46 | case 1: |
47 | + | 47 | - addr = desc->source_address2 |
48 | REG32(IRQ_CTRL, 0x50) | 48 | - + (extract32(desc->address_extension_23, 0, 12) << 8); |
49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) | 49 | + addr = (uint64_t)desc->source_address2 |
50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) | 50 | + + (extract64(desc->address_extension_23, 0, 16) << 32); |
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | 51 | break; |
52 | index XXXXXXX..XXXXXXX 100644 | 52 | case 2: |
53 | --- a/include/hw/arm/smmuv3.h | 53 | - addr = desc->source_address3 |
54 | +++ b/include/hw/arm/smmuv3.h | 54 | - + (extract32(desc->address_extension_23, 16, 12) << 20); |
55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { | 55 | + addr = (uint64_t)desc->source_address3 |
56 | uint32_t cr[3]; | 56 | + + (extract64(desc->address_extension_23, 16, 16) << 32); |
57 | uint32_t cr0ack; | 57 | break; |
58 | uint32_t statusr; | 58 | case 3: |
59 | + uint32_t gbpa; | 59 | - addr = desc->source_address4 |
60 | uint32_t irq_ctrl; | 60 | - + (extract32(desc->address_extension_45, 0, 12) << 8); |
61 | uint32_t gerror; | 61 | + addr = (uint64_t)desc->source_address4 |
62 | uint32_t gerrorn; | 62 | + + (extract64(desc->address_extension_45, 0, 16) << 32); |
63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | 63 | break; |
64 | index XXXXXXX..XXXXXXX 100644 | 64 | case 4: |
65 | --- a/hw/arm/smmuv3.c | 65 | - addr = desc->source_address5 |
66 | +++ b/hw/arm/smmuv3.c | 66 | - + (extract32(desc->address_extension_45, 16, 12) << 20); |
67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | 67 | + addr = (uint64_t)desc->source_address5 |
68 | s->gerror = 0; | 68 | + + (extract64(desc->address_extension_45, 16, 16) << 32); |
69 | s->gerrorn = 0; | 69 | break; |
70 | s->statusr = 0; | 70 | default: |
71 | + s->gbpa = SMMU_GBPA_RESET_VAL; | 71 | addr = 0; |
72 | } | ||
73 | |||
74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
76 | qemu_mutex_lock(&s->mutex); | ||
77 | |||
78 | if (!smmu_enabled(s)) { | ||
79 | - status = SMMU_TRANS_DISABLE; | ||
80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { | ||
81 | + status = SMMU_TRANS_ABORT; | ||
82 | + } else { | ||
83 | + status = SMMU_TRANS_DISABLE; | ||
84 | + } | ||
85 | goto epilogue; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | ||
89 | case A_GERROR_IRQ_CFG2: | ||
90 | s->gerror_irq_cfg2 = data; | ||
91 | return MEMTX_OK; | ||
92 | + case A_GBPA: | ||
93 | + /* | ||
94 | + * If UPDATE is not set, the write is ignored. This is the only | ||
95 | + * permitted behavior in SMMUv3.2 and later. | ||
96 | + */ | ||
97 | + if (data & R_GBPA_UPDATE_MASK) { | ||
98 | + /* Ignore update bit as write is synchronous. */ | ||
99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; | ||
100 | + } | ||
101 | + return MEMTX_OK; | ||
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
116 | }, | ||
117 | }; | ||
118 | |||
119 | +static bool smmuv3_gbpa_needed(void *opaque) | ||
120 | +{ | ||
121 | + SMMUv3State *s = opaque; | ||
122 | + | ||
123 | + /* Only migrate GBPA if it has different reset value. */ | ||
124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; | ||
125 | +} | ||
126 | + | ||
127 | +static const VMStateDescription vmstate_gbpa = { | ||
128 | + .name = "smmuv3/gbpa", | ||
129 | + .version_id = 1, | ||
130 | + .minimum_version_id = 1, | ||
131 | + .needed = smmuv3_gbpa_needed, | ||
132 | + .fields = (VMStateField[]) { | ||
133 | + VMSTATE_UINT32(gbpa, SMMUv3State), | ||
134 | + VMSTATE_END_OF_LIST() | ||
135 | + } | ||
136 | +}; | ||
137 | + | ||
138 | static const VMStateDescription vmstate_smmuv3 = { | ||
139 | .name = "smmuv3", | ||
140 | .version_id = 1, | ||
141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { | ||
142 | |||
143 | VMSTATE_END_OF_LIST(), | ||
144 | }, | ||
145 | + .subsections = (const VMStateDescription * []) { | ||
146 | + &vmstate_gbpa, | ||
147 | + NULL | ||
148 | + } | ||
149 | }; | ||
150 | |||
151 | static void smmuv3_instance_init(Object *obj) | ||
152 | -- | 72 | -- |
153 | 2.34.1 | 73 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Claudio Fontana <cfontana@suse.de> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | 3 | "make check-qtest-aarch64" recently started failing on FreeBSD builds, |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | and valgrind on Linux also detected that there is something fishy with |
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 5 | the new stm32l4x5-usart: The code forgot to set the correct class_size |
6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | here, so the various class_init functions in this file wrote beyond |
7 | the allocated buffer when setting the subc->type field. | ||
8 | |||
9 | Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton") | ||
10 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Message-id: 20240429075908.36302-1-thuth@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 14 | --- |
9 | target/arm/helper.c | 12 +++++++----- | 15 | hw/char/stm32l4x5_usart.c | 1 + |
10 | 1 file changed, 7 insertions(+), 5 deletions(-) | 16 | 1 file changed, 1 insertion(+) |
11 | 17 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 20 | --- a/hw/char/stm32l4x5_usart.c |
15 | +++ b/target/arm/helper.c | 21 | +++ b/hw/char/stm32l4x5_usart.c |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 22 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = { |
17 | unsigned int cur_el = arm_current_el(env); | 23 | .parent = TYPE_SYS_BUS_DEVICE, |
18 | int rt; | 24 | .instance_size = sizeof(Stm32l4x5UsartBaseState), |
19 | 25 | .instance_init = stm32l4x5_usart_base_init, | |
20 | - /* | 26 | + .class_size = sizeof(Stm32l4x5UsartBaseClass), |
21 | - * Note that new_el can never be 0. If cur_el is 0, then | 27 | .class_init = stm32l4x5_usart_base_class_init, |
22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. | 28 | .abstract = true, |
23 | - */ | 29 | }, { |
24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | ||
25 | + if (tcg_enabled()) { | ||
26 | + /* | ||
27 | + * Note that new_el can never be 0. If cur_el is 0, then | ||
28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. | ||
29 | + */ | ||
30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | ||
31 | + } | ||
32 | |||
33 | if (cur_el < new_el) { | ||
34 | /* | ||
35 | -- | 30 | -- |
36 | 2.34.1 | 31 | 2.34.1 |
37 | 32 | ||
38 | 33 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Use little endian for derivative OTP fuse key. |
4 | |||
5 | Cc: qemu-stable@nongnu.org | ||
6 | Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") | ||
7 | Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20230206223502.25122-8-philmd@linaro.org | 9 | Message-id: 20240422125813.1403-1-philmd@linaro.org |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/cpu.h | 3 ++- | 13 | hw/arm/npcm7xx.c | 3 ++- |
9 | 1 file changed, 2 insertions(+), 1 deletion(-) | 14 | 1 file changed, 2 insertions(+), 1 deletion(-) |
10 | 15 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c |
12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 18 | --- a/hw/arm/npcm7xx.c |
14 | +++ b/target/arm/cpu.h | 19 | +++ b/hw/arm/npcm7xx.c |
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 20 | @@ -XXX,XX +XXX,XX @@ |
16 | 21 | #include "hw/qdev-clock.h" | |
17 | void *nvic; | 22 | #include "hw/qdev-properties.h" |
18 | const struct arm_boot_info *boot_info; | 23 | #include "qapi/error.h" |
19 | +#if !defined(CONFIG_USER_ONLY) | 24 | +#include "qemu/bswap.h" |
20 | /* Store GICv3CPUState to access from this struct */ | 25 | #include "qemu/units.h" |
21 | void *gicv3state; | 26 | #include "sysemu/sysemu.h" |
22 | -#if defined(CONFIG_USER_ONLY) | 27 | #include "target/arm/cpu-qom.h" |
23 | +#else /* CONFIG_USER_ONLY */ | 28 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s) |
24 | /* For usermode syscall translation. */ | 29 | * The initial mask of disabled modules indicates the chip derivative (e.g. |
25 | bool eabi; | 30 | * NPCM750 or NPCM730). |
26 | #endif /* CONFIG_USER_ONLY */ | 31 | */ |
32 | - value = tswap32(nc->disabled_modules); | ||
33 | + value = cpu_to_le32(nc->disabled_modules); | ||
34 | npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE, | ||
35 | sizeof(value)); | ||
36 | } | ||
27 | -- | 37 | -- |
28 | 2.34.1 | 38 | 2.34.1 |
29 | 39 | ||
30 | 40 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | Nuvoton's PSPI is a general purpose SPI module which enables | 3 | This device implements the IM120417002 colors shield v1.1 for Arduino |
4 | connections to SPI-based peripheral devices. | 4 | (which relies on the DM163 8x3-channel led driving logic) and features |
5 | a simple display of an 8x8 RGB matrix. The columns of the matrix are | ||
6 | driven by the DM163 and the rows are driven externally. | ||
5 | 7 | ||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 8 | Acked-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Reviewed-by: Chris Rauer <crauer@google.com> | 9 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | 10 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr | ||
13 | [PMM: updated to new reset hold method prototype] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 15 | --- |
12 | MAINTAINERS | 6 +- | 16 | docs/system/arm/b-l475e-iot01a.rst | 3 +- |
13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ | 17 | include/hw/display/dm163.h | 59 +++++ |
14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ | 18 | hw/display/dm163.c | 349 +++++++++++++++++++++++++++++ |
15 | hw/ssi/meson.build | 2 +- | 19 | hw/display/Kconfig | 3 + |
16 | hw/ssi/trace-events | 5 + | 20 | hw/display/meson.build | 1 + |
17 | 5 files changed, 283 insertions(+), 4 deletions(-) | 21 | hw/display/trace-events | 14 ++ |
18 | create mode 100644 include/hw/ssi/npcm_pspi.h | 22 | 6 files changed, 428 insertions(+), 1 deletion(-) |
19 | create mode 100644 hw/ssi/npcm_pspi.c | 23 | create mode 100644 include/hw/display/dm163.h |
24 | create mode 100644 hw/display/dm163.c | ||
20 | 25 | ||
21 | diff --git a/MAINTAINERS b/MAINTAINERS | 26 | diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst |
22 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/MAINTAINERS | 28 | --- a/docs/system/arm/b-l475e-iot01a.rst |
24 | +++ b/MAINTAINERS | 29 | +++ b/docs/system/arm/b-l475e-iot01a.rst |
25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> | 30 | @@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors. |
26 | M: Hao Wu <wuhaotsh@google.com> | 31 | Supported devices |
27 | L: qemu-arm@nongnu.org | 32 | """"""""""""""""" |
28 | S: Supported | 33 | |
29 | -F: hw/*/npcm7xx* | 34 | -Currently B-L475E-IOT01A machine's only supports the following devices: |
30 | -F: include/hw/*/npcm7xx* | 35 | +Currently B-L475E-IOT01A machines support the following devices: |
31 | -F: tests/qtest/npcm7xx* | 36 | |
32 | +F: hw/*/npcm* | 37 | - Cortex-M4F based STM32L4x5 SoC |
33 | +F: include/hw/*/npcm* | 38 | - STM32L4x5 EXTI (Extended interrupts and events controller) |
34 | +F: tests/qtest/npcm* | 39 | @@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices: |
35 | F: pc-bios/npcm7xx_bootrom.bin | 40 | - STM32L4x5 RCC (Reset and clock control) |
36 | F: roms/vbootrom | 41 | - STM32L4x5 GPIOs (General-purpose I/Os) |
37 | F: docs/system/arm/nuvoton.rst | 42 | - STM32L4x5 USARTs, UARTs and LPUART (Serial ports) |
38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h | 43 | +- optional 8x8 led display (based on DM163 driver) |
44 | |||
45 | Missing devices | ||
46 | """"""""""""""" | ||
47 | diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h | ||
39 | new file mode 100644 | 48 | new file mode 100644 |
40 | index XXXXXXX..XXXXXXX | 49 | index XXXXXXX..XXXXXXX |
41 | --- /dev/null | 50 | --- /dev/null |
42 | +++ b/include/hw/ssi/npcm_pspi.h | 51 | +++ b/include/hw/display/dm163.h |
43 | @@ -XXX,XX +XXX,XX @@ | 52 | @@ -XXX,XX +XXX,XX @@ |
44 | +/* | 53 | +/* |
45 | + * Nuvoton Peripheral SPI Module | 54 | + * QEMU DM163 8x3-channel constant current led driver |
55 | + * driving columns of associated 8x8 RGB matrix. | ||
46 | + * | 56 | + * |
47 | + * Copyright 2023 Google LLC | 57 | + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net> |
58 | + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
59 | + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
48 | + * | 60 | + * |
49 | + * This program is free software; you can redistribute it and/or modify it | 61 | + * SPDX-License-Identifier: GPL-2.0-or-later |
50 | + * under the terms of the GNU General Public License as published by the | ||
51 | + * Free Software Foundation; either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
57 | + * for more details. | ||
58 | + */ | 62 | + */ |
59 | +#ifndef NPCM_PSPI_H | 63 | + |
60 | +#define NPCM_PSPI_H | 64 | +#ifndef HW_DISPLAY_DM163_H |
61 | + | 65 | +#define HW_DISPLAY_DM163_H |
62 | +#include "hw/ssi/ssi.h" | 66 | + |
63 | +#include "hw/sysbus.h" | 67 | +#include "qom/object.h" |
64 | + | 68 | +#include "hw/qdev-core.h" |
65 | +/* | 69 | + |
66 | + * Number of registers in our device state structure. Don't change this without | 70 | +#define TYPE_DM163 "dm163" |
67 | + * incrementing the version_id in the vmstate. | 71 | +OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163); |
68 | + */ | 72 | + |
69 | +#define NPCM_PSPI_NR_REGS 3 | 73 | +#define RGB_MATRIX_NUM_ROWS 8 |
70 | + | 74 | +#define RGB_MATRIX_NUM_COLS 8 |
71 | +/** | 75 | +#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3) |
72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. | 76 | +/* The last row is filled with 0 (turned off row) */ |
73 | + * @parent: System bus device. | 77 | +#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1) |
74 | + * @mmio: Memory region for register access. | 78 | + |
75 | + * @spi: The SPI bus mastered by this controller. | 79 | +typedef struct DM163State { |
76 | + * @regs: Register contents. | 80 | + DeviceState parent_obj; |
77 | + * @irq: The interrupt request queue for this module. | 81 | + |
78 | + * | 82 | + /* DM163 driver */ |
79 | + * Each PSPI has a shared bank of registers, and controls up to four chip | 83 | + uint64_t bank0_shift_register[3]; |
80 | + * selects. Each chip select has a dedicated memory region which may be used to | 84 | + uint64_t bank1_shift_register[3]; |
81 | + * read and write the flash connected to that chip select as if it were memory. | 85 | + uint16_t latched_outputs[DM163_NUM_LEDS]; |
82 | + */ | 86 | + uint16_t outputs[DM163_NUM_LEDS]; |
83 | +typedef struct NPCMPSPIState { | 87 | + qemu_irq sout; |
84 | + SysBusDevice parent; | 88 | + |
85 | + | 89 | + uint8_t sin; |
86 | + MemoryRegion mmio; | 90 | + uint8_t dck; |
87 | + | 91 | + uint8_t rst_b; |
88 | + SSIBus *spi; | 92 | + uint8_t lat_b; |
89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; | 93 | + uint8_t selbk; |
90 | + qemu_irq irq; | 94 | + uint8_t en_b; |
91 | +} NPCMPSPIState; | 95 | + |
92 | + | 96 | + /* IM120417002 colors shield */ |
93 | +#define TYPE_NPCM_PSPI "npcm-pspi" | 97 | + uint8_t activated_rows; |
94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) | 98 | + |
95 | + | 99 | + /* 8x8 RGB matrix */ |
96 | +#endif /* NPCM_PSPI_H */ | 100 | + QemuConsole *console; |
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | 101 | + uint8_t redraw; |
102 | + /* Rows currently being displayed on the matrix. */ | ||
103 | + /* The last row is filled with 0 (turned off row) */ | ||
104 | + uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS]; | ||
105 | + uint8_t last_buffer_idx; | ||
106 | + uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS]; | ||
107 | + /* Used to simulate retinal persistence of rows */ | ||
108 | + uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS]; | ||
109 | +} DM163State; | ||
110 | + | ||
111 | +#endif /* HW_DISPLAY_DM163_H */ | ||
112 | diff --git a/hw/display/dm163.c b/hw/display/dm163.c | ||
98 | new file mode 100644 | 113 | new file mode 100644 |
99 | index XXXXXXX..XXXXXXX | 114 | index XXXXXXX..XXXXXXX |
100 | --- /dev/null | 115 | --- /dev/null |
101 | +++ b/hw/ssi/npcm_pspi.c | 116 | +++ b/hw/display/dm163.c |
102 | @@ -XXX,XX +XXX,XX @@ | 117 | @@ -XXX,XX +XXX,XX @@ |
103 | +/* | 118 | +/* |
104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) | 119 | + * QEMU DM163 8x3-channel constant current led driver |
120 | + * driving columns of associated 8x8 RGB matrix. | ||
105 | + * | 121 | + * |
106 | + * Copyright 2023 Google LLC | 122 | + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net> |
123 | + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
124 | + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
107 | + * | 125 | + * |
108 | + * This program is free software; you can redistribute it and/or modify it | 126 | + * SPDX-License-Identifier: GPL-2.0-or-later |
109 | + * under the terms of the GNU General Public License as published by the | ||
110 | + * Free Software Foundation; either version 2 of the License, or | ||
111 | + * (at your option) any later version. | ||
112 | + * | ||
113 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
116 | + * for more details. | ||
117 | + */ | 127 | + */ |
118 | + | 128 | + |
129 | +/* | ||
130 | + * The reference used for the DM163 is the following : | ||
131 | + * http://www.siti.com.tw/product/spec/LED/DM163.pdf | ||
132 | + */ | ||
133 | + | ||
119 | +#include "qemu/osdep.h" | 134 | +#include "qemu/osdep.h" |
120 | + | 135 | +#include "qapi/error.h" |
136 | +#include "migration/vmstate.h" | ||
121 | +#include "hw/irq.h" | 137 | +#include "hw/irq.h" |
122 | +#include "hw/registerfields.h" | 138 | +#include "hw/qdev-properties.h" |
123 | +#include "hw/ssi/npcm_pspi.h" | 139 | +#include "hw/display/dm163.h" |
124 | +#include "migration/vmstate.h" | 140 | +#include "ui/console.h" |
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
127 | +#include "qemu/log.h" | ||
128 | +#include "qemu/module.h" | ||
129 | +#include "qemu/units.h" | ||
130 | + | ||
131 | +#include "trace.h" | 141 | +#include "trace.h" |
132 | + | 142 | + |
133 | +REG16(PSPI_DATA, 0x0) | 143 | +#define LED_SQUARE_SIZE 100 |
134 | +REG16(PSPI_CTL1, 0x2) | 144 | +/* Number of frames a row stays visible after being turned off. */ |
135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) | 145 | +#define ROW_PERSISTENCE 3 |
136 | + FIELD(PSPI_CTL1, MOD, 2, 1) | 146 | +#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1) |
137 | + FIELD(PSPI_CTL1, EIR, 5, 1) | 147 | + |
138 | + FIELD(PSPI_CTL1, EIW, 6, 1) | 148 | +static const VMStateDescription vmstate_dm163 = { |
139 | + FIELD(PSPI_CTL1, SCM, 7, 1) | 149 | + .name = TYPE_DM163, |
140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) | 150 | + .version_id = 1, |
141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) | 151 | + .minimum_version_id = 1, |
142 | +REG16(PSPI_STAT, 0x4) | 152 | + .fields = (const VMStateField[]) { |
143 | + FIELD(PSPI_STAT, BSY, 0, 1) | 153 | + VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3), |
144 | + FIELD(PSPI_STAT, RBF, 1, 1) | 154 | + VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3), |
145 | + | 155 | + VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS), |
146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) | 156 | + VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS), |
147 | +{ | 157 | + VMSTATE_UINT8(dck, DM163State), |
148 | + int level = 0; | 158 | + VMSTATE_UINT8(en_b, DM163State), |
149 | + | 159 | + VMSTATE_UINT8(lat_b, DM163State), |
150 | + /* Only fire IRQ when the module is enabled. */ | 160 | + VMSTATE_UINT8(rst_b, DM163State), |
151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { | 161 | + VMSTATE_UINT8(selbk, DM163State), |
152 | + /* Update interrupt as BSY is cleared. */ | 162 | + VMSTATE_UINT8(sin, DM163State), |
153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && | 163 | + VMSTATE_UINT8(activated_rows, DM163State), |
154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { | 164 | + VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE, |
155 | + level = 1; | 165 | + RGB_MATRIX_NUM_COLS), |
166 | + VMSTATE_UINT8(last_buffer_idx, DM163State), | ||
167 | + VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS), | ||
168 | + VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State, | ||
169 | + RGB_MATRIX_NUM_ROWS), | ||
170 | + VMSTATE_END_OF_LIST() | ||
171 | + } | ||
172 | +}; | ||
173 | + | ||
174 | +static void dm163_reset_hold(Object *obj, ResetType type) | ||
175 | +{ | ||
176 | + DM163State *s = DM163(obj); | ||
177 | + | ||
178 | + s->sin = 0; | ||
179 | + s->dck = 0; | ||
180 | + s->rst_b = 0; | ||
181 | + /* Ensuring the first falling edge of lat_b isn't missed */ | ||
182 | + s->lat_b = 1; | ||
183 | + s->selbk = 0; | ||
184 | + s->en_b = 0; | ||
185 | + /* Reset stops the PWM, not the shift and latched registers. */ | ||
186 | + memset(s->outputs, 0, sizeof(s->outputs)); | ||
187 | + | ||
188 | + s->activated_rows = 0; | ||
189 | + s->redraw = 0; | ||
190 | + trace_dm163_redraw(s->redraw); | ||
191 | + for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) { | ||
192 | + memset(s->buffer[i], 0, sizeof(s->buffer[0])); | ||
193 | + } | ||
194 | + s->last_buffer_idx = 0; | ||
195 | + memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row)); | ||
196 | + memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay)); | ||
197 | +} | ||
198 | + | ||
199 | +static void dm163_dck_gpio_handler(void *opaque, int line, int new_state) | ||
200 | +{ | ||
201 | + DM163State *s = opaque; | ||
202 | + | ||
203 | + if (new_state && !s->dck) { | ||
204 | + /* | ||
205 | + * On raising dck, sample selbk to get the bank to use, and | ||
206 | + * sample sin for the bit to enter into the bank shift buffer. | ||
207 | + */ | ||
208 | + uint64_t *sb = | ||
209 | + s->selbk ? s->bank1_shift_register : s->bank0_shift_register; | ||
210 | + /* Output the outgoing bit on sout */ | ||
211 | + const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) : | ||
212 | + sb[2] & MAKE_64BIT_MASK(15, 1)) != 0; | ||
213 | + qemu_set_irq(s->sout, sout); | ||
214 | + /* Enter sin into the shift buffer */ | ||
215 | + sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1); | ||
216 | + sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1); | ||
217 | + sb[0] = (sb[0] << 1) | s->sin; | ||
218 | + } | ||
219 | + | ||
220 | + s->dck = new_state; | ||
221 | + trace_dm163_dck(new_state); | ||
222 | +} | ||
223 | + | ||
224 | +static void dm163_propagate_outputs(DM163State *s) | ||
225 | +{ | ||
226 | + s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS; | ||
227 | + /* Values are output when reset is high and enable is low. */ | ||
228 | + if (s->rst_b && !s->en_b) { | ||
229 | + memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs)); | ||
230 | + } else { | ||
231 | + memset(s->outputs, 0, sizeof(s->outputs)); | ||
232 | + } | ||
233 | + for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) { | ||
234 | + /* Grouping the 3 RGB channels in a pixel value */ | ||
235 | + const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8); | ||
236 | + const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8); | ||
237 | + const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8); | ||
238 | + uint32_t rgba = 0; | ||
239 | + | ||
240 | + trace_dm163_channels(3 * x + 2, r); | ||
241 | + trace_dm163_channels(3 * x + 1, g); | ||
242 | + trace_dm163_channels(3 * x + 0, b); | ||
243 | + | ||
244 | + rgba = deposit32(rgba, 0, 8, r); | ||
245 | + rgba = deposit32(rgba, 8, 8, g); | ||
246 | + rgba = deposit32(rgba, 16, 8, b); | ||
247 | + | ||
248 | + /* Led values are sent from the last one to the first one */ | ||
249 | + s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba; | ||
250 | + } | ||
251 | + for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) { | ||
252 | + if (s->activated_rows & (1 << row)) { | ||
253 | + s->buffer_idx_of_row[row] = s->last_buffer_idx; | ||
254 | + s->redraw |= (1 << row); | ||
255 | + trace_dm163_redraw(s->redraw); | ||
156 | + } | 256 | + } |
157 | + | 257 | + } |
158 | + /* Update interrupt as RBF is set. */ | 258 | +} |
159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && | 259 | + |
160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { | 260 | +static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state) |
161 | + level = 1; | 261 | +{ |
262 | + DM163State *s = opaque; | ||
263 | + | ||
264 | + s->en_b = new_state; | ||
265 | + dm163_propagate_outputs(s); | ||
266 | + trace_dm163_en_b(new_state); | ||
267 | +} | ||
268 | + | ||
269 | +static uint8_t dm163_bank0(const DM163State *s, uint8_t led) | ||
270 | +{ | ||
271 | + /* | ||
272 | + * Bank 0 uses 6 bits per led, so a value may be stored accross | ||
273 | + * two uint64_t entries. | ||
274 | + */ | ||
275 | + const uint8_t low_bit = 6 * led; | ||
276 | + const uint8_t low_word = low_bit / 64; | ||
277 | + const uint8_t high_word = (low_bit + 5) / 64; | ||
278 | + const uint8_t low_shift = low_bit % 64; | ||
279 | + | ||
280 | + if (low_word == high_word) { | ||
281 | + /* Simple case: the value belongs to one entry. */ | ||
282 | + return extract64(s->bank0_shift_register[low_word], low_shift, 6); | ||
283 | + } | ||
284 | + | ||
285 | + const uint8_t nb_bits_in_low_word = 64 - low_shift; | ||
286 | + const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word; | ||
287 | + | ||
288 | + const uint64_t bits_in_low_word = \ | ||
289 | + extract64(s->bank0_shift_register[low_word], low_shift, | ||
290 | + nb_bits_in_low_word); | ||
291 | + const uint64_t bits_in_high_word = \ | ||
292 | + extract64(s->bank0_shift_register[high_word], 0, | ||
293 | + nb_bits_in_high_word); | ||
294 | + uint8_t val = 0; | ||
295 | + | ||
296 | + val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word); | ||
297 | + val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word, | ||
298 | + bits_in_high_word); | ||
299 | + | ||
300 | + return val; | ||
301 | +} | ||
302 | + | ||
303 | +static uint8_t dm163_bank1(const DM163State *s, uint8_t led) | ||
304 | +{ | ||
305 | + const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS]; | ||
306 | + return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8); | ||
307 | +} | ||
308 | + | ||
309 | +static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state) | ||
310 | +{ | ||
311 | + DM163State *s = opaque; | ||
312 | + | ||
313 | + if (s->lat_b && !new_state) { | ||
314 | + for (int led = 0; led < DM163_NUM_LEDS; led++) { | ||
315 | + s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led); | ||
162 | + } | 316 | + } |
163 | + } | 317 | + dm163_propagate_outputs(s); |
164 | + qemu_set_irq(s->irq, level); | 318 | + } |
165 | +} | 319 | + |
166 | + | 320 | + s->lat_b = new_state; |
167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) | 321 | + trace_dm163_lat_b(new_state); |
168 | +{ | 322 | +} |
169 | + uint16_t value = s->regs[R_PSPI_DATA]; | 323 | + |
170 | + | 324 | +static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state) |
171 | + /* Clear stat bits as the value are read out. */ | 325 | +{ |
172 | + s->regs[R_PSPI_STAT] = 0; | 326 | + DM163State *s = opaque; |
173 | + | 327 | + |
174 | + return value; | 328 | + s->rst_b = new_state; |
175 | +} | 329 | + dm163_propagate_outputs(s); |
176 | + | 330 | + trace_dm163_rst_b(new_state); |
177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) | 331 | +} |
178 | +{ | 332 | + |
179 | + uint16_t value = 0; | 333 | +static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state) |
180 | + | 334 | +{ |
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | 335 | + DM163State *s = opaque; |
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | 336 | + |
183 | + } | 337 | + s->selbk = new_state; |
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | 338 | + trace_dm163_selbk(new_state); |
185 | + s->regs[R_PSPI_DATA] = value; | 339 | +} |
186 | + | 340 | + |
187 | + /* Mark data as available */ | 341 | +static void dm163_sin_gpio_handler(void *opaque, int line, int new_state) |
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | 342 | +{ |
189 | +} | 343 | + DM163State *s = opaque; |
190 | + | 344 | + |
191 | +/* Control register read handler. */ | 345 | + s->sin = new_state; |
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | 346 | + trace_dm163_sin(new_state); |
193 | + unsigned int size) | 347 | +} |
194 | +{ | 348 | + |
195 | + NPCMPSPIState *s = opaque; | 349 | +static void dm163_rows_gpio_handler(void *opaque, int line, int new_state) |
196 | + uint16_t value; | 350 | +{ |
197 | + | 351 | + DM163State *s = opaque; |
198 | + switch (addr) { | 352 | + |
199 | + case A_PSPI_DATA: | 353 | + if (new_state) { |
200 | + value = npcm_pspi_read_data(s); | 354 | + s->activated_rows |= (1 << line); |
201 | + break; | 355 | + s->buffer_idx_of_row[line] = s->last_buffer_idx; |
202 | + | 356 | + s->redraw |= (1 << line); |
203 | + case A_PSPI_CTL1: | 357 | + trace_dm163_redraw(s->redraw); |
204 | + value = s->regs[R_PSPI_CTL1]; | 358 | + } else { |
205 | + break; | 359 | + s->activated_rows &= ~(1 << line); |
206 | + | 360 | + s->row_persistence_delay[line] = ROW_PERSISTENCE; |
207 | + case A_PSPI_STAT: | 361 | + } |
208 | + value = s->regs[R_PSPI_STAT]; | 362 | + trace_dm163_activated_rows(s->activated_rows); |
209 | + break; | 363 | +} |
210 | + | 364 | + |
211 | + default: | 365 | +static void dm163_invalidate_display(void *opaque) |
212 | + qemu_log_mask(LOG_GUEST_ERROR, | 366 | +{ |
213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | 367 | + DM163State *s = (DM163State *)opaque; |
214 | + DEVICE(s)->canonical_path, addr); | 368 | + s->redraw = 0xFF; |
215 | + return 0; | 369 | + trace_dm163_redraw(s->redraw); |
216 | + } | 370 | +} |
217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); | 371 | + |
218 | + npcm_pspi_update_irq(s); | 372 | +static void update_row_persistence_delay(DM163State *s, unsigned row) |
219 | + | 373 | +{ |
220 | + return value; | 374 | + if (s->row_persistence_delay[row]) { |
221 | +} | 375 | + s->row_persistence_delay[row]--; |
222 | + | 376 | + } else { |
223 | +/* Control register write handler. */ | 377 | + /* |
224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, | 378 | + * If the ROW_PERSISTENCE delay is up, |
225 | + unsigned int size) | 379 | + * the row is turned off. |
226 | +{ | 380 | + */ |
227 | + NPCMPSPIState *s = opaque; | 381 | + s->buffer_idx_of_row[row] = TURNED_OFF_ROW; |
228 | + uint16_t value = v; | 382 | + s->redraw |= (1 << row); |
229 | + | 383 | + trace_dm163_redraw(s->redraw); |
230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); | 384 | + } |
231 | + | 385 | +} |
232 | + switch (addr) { | 386 | + |
233 | + case A_PSPI_DATA: | 387 | +static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest, |
234 | + npcm_pspi_write_data(s, value); | 388 | + unsigned row) |
235 | + break; | 389 | +{ |
236 | + | 390 | + for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) { |
237 | + case A_PSPI_CTL1: | 391 | + for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) { |
238 | + s->regs[R_PSPI_CTL1] = value; | 392 | + /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */ |
239 | + break; | 393 | + *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE]; |
240 | + | 394 | + } |
241 | + case A_PSPI_STAT: | 395 | + } |
242 | + qemu_log_mask(LOG_GUEST_ERROR, | 396 | + |
243 | + "%s: write to read-only register PSPI_STAT: 0x%08" | 397 | + dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row, |
244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); | 398 | + RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE); |
245 | + break; | 399 | + s->redraw &= ~(1 << row); |
246 | + | 400 | + trace_dm163_redraw(s->redraw); |
247 | + default: | 401 | + |
248 | + qemu_log_mask(LOG_GUEST_ERROR, | 402 | + return dest; |
249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | 403 | +} |
250 | + DEVICE(s)->canonical_path, addr); | 404 | + |
251 | + return; | 405 | +static void dm163_update_display(void *opaque) |
252 | + } | 406 | +{ |
253 | + npcm_pspi_update_irq(s); | 407 | + DM163State *s = (DM163State *)opaque; |
254 | +} | 408 | + DisplaySurface *surface = qemu_console_surface(s->console); |
255 | + | 409 | + uint32_t *dest; |
256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { | 410 | + |
257 | + .read = npcm_pspi_ctrl_read, | 411 | + dest = surface_data(surface); |
258 | + .write = npcm_pspi_ctrl_write, | 412 | + for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) { |
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | 413 | + update_row_persistence_delay(s, row); |
260 | + .valid = { | 414 | + if (!extract8(s->redraw, row, 1)) { |
261 | + .min_access_size = 1, | 415 | + dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS; |
262 | + .max_access_size = 2, | 416 | + continue; |
263 | + .unaligned = false, | 417 | + } |
264 | + }, | 418 | + dest = update_display_of_row(s, dest, row); |
265 | + .impl = { | 419 | + } |
266 | + .min_access_size = 2, | 420 | +} |
267 | + .max_access_size = 2, | 421 | + |
268 | + .unaligned = false, | 422 | +static const GraphicHwOps dm163_ops = { |
269 | + }, | 423 | + .invalidate = dm163_invalidate_display, |
424 | + .gfx_update = dm163_update_display, | ||
270 | +}; | 425 | +}; |
271 | + | 426 | + |
272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) | 427 | +static void dm163_realize(DeviceState *dev, Error **errp) |
273 | +{ | 428 | +{ |
274 | + NPCMPSPIState *s = NPCM_PSPI(obj); | 429 | + DM163State *s = DM163(dev); |
275 | + | 430 | + |
276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); | 431 | + qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS); |
277 | + memset(s->regs, 0, sizeof(s->regs)); | 432 | + qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1); |
278 | +} | 433 | + qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1); |
279 | + | 434 | + qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1); |
280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) | 435 | + qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1); |
281 | +{ | 436 | + qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1); |
282 | + NPCMPSPIState *s = NPCM_PSPI(dev); | 437 | + qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1); |
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 438 | + qdev_init_gpio_out_named(dev, &s->sout, "sout", 1); |
284 | + Object *obj = OBJECT(dev); | 439 | + |
285 | + | 440 | + s->console = graphic_console_init(dev, 0, &dm163_ops, s); |
286 | + s->spi = ssi_create_bus(dev, "pspi"); | 441 | + qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, |
287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, | 442 | + RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE); |
288 | + "mmio", 4 * KiB); | 443 | +} |
289 | + sysbus_init_mmio(sbd, &s->mmio); | 444 | + |
290 | + sysbus_init_irq(sbd, &s->irq); | 445 | +static void dm163_class_init(ObjectClass *klass, void *data) |
291 | +} | 446 | +{ |
292 | + | 447 | + DeviceClass *dc = DEVICE_CLASS(klass); |
293 | +static const VMStateDescription vmstate_npcm_pspi = { | 448 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
294 | + .name = "npcm-pspi", | 449 | + |
295 | + .version_id = 0, | 450 | + dc->desc = "DM163"; |
296 | + .minimum_version_id = 0, | 451 | + dc->vmsd = &vmstate_dm163; |
297 | + .fields = (VMStateField[]) { | 452 | + dc->realize = dm163_realize; |
298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), | 453 | + rc->phases.hold = dm163_reset_hold; |
299 | + VMSTATE_END_OF_LIST(), | 454 | + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
300 | + }, | 455 | +} |
456 | + | ||
457 | +static const TypeInfo dm163_types[] = { | ||
458 | + { | ||
459 | + .name = TYPE_DM163, | ||
460 | + .parent = TYPE_DEVICE, | ||
461 | + .instance_size = sizeof(DM163State), | ||
462 | + .class_init = dm163_class_init | ||
463 | + } | ||
301 | +}; | 464 | +}; |
302 | + | 465 | + |
303 | + | 466 | +DEFINE_TYPES(dm163_types) |
304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) | 467 | diff --git a/hw/display/Kconfig b/hw/display/Kconfig |
305 | +{ | ||
306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
307 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
308 | + | ||
309 | + dc->desc = "NPCM Peripheral SPI Module"; | ||
310 | + dc->realize = npcm_pspi_realize; | ||
311 | + dc->vmsd = &vmstate_npcm_pspi; | ||
312 | + rc->phases.enter = npcm_pspi_enter_reset; | ||
313 | +} | ||
314 | + | ||
315 | +static const TypeInfo npcm_pspi_types[] = { | ||
316 | + { | ||
317 | + .name = TYPE_NPCM_PSPI, | ||
318 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
322 | +}; | ||
323 | +DEFINE_TYPES(npcm_pspi_types); | ||
324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build | ||
325 | index XXXXXXX..XXXXXXX 100644 | 468 | index XXXXXXX..XXXXXXX 100644 |
326 | --- a/hw/ssi/meson.build | 469 | --- a/hw/display/Kconfig |
327 | +++ b/hw/ssi/meson.build | 470 | +++ b/hw/display/Kconfig |
328 | @@ -XXX,XX +XXX,XX @@ | 471 | @@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT |
329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) | 472 | bool |
330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) | 473 | # defaults to "N", enabled by specific boards |
331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) | 474 | depends on PIXMAN |
332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) | 475 | + |
333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) | 476 | +config DM163 |
334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) | 477 | + bool |
335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) | 478 | diff --git a/hw/display/meson.build b/hw/display/meson.build |
336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
337 | index XXXXXXX..XXXXXXX 100644 | 479 | index XXXXXXX..XXXXXXX 100644 |
338 | --- a/hw/ssi/trace-events | 480 | --- a/hw/display/meson.build |
339 | +++ b/hw/ssi/trace-events | 481 | +++ b/hw/display/meson.build |
340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: | 482 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c')) |
341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | 483 | |
342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | 484 | system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) |
343 | 485 | system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c')) | |
344 | +# npcm_pspi.c | 486 | +system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c')) |
345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" | 487 | |
346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | 488 | if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or |
347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | 489 | config_all_devices.has_key('CONFIG_VGA_PCI') or |
348 | + | 490 | diff --git a/hw/display/trace-events b/hw/display/trace-events |
349 | # ibex_spi_host.c | 491 | index XXXXXXX..XXXXXXX 100644 |
350 | 492 | --- a/hw/display/trace-events | |
351 | ibex_spi_host_reset(const char *msg) "%s" | 493 | +++ b/hw/display/trace-events |
494 | @@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI | ||
495 | macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32 | ||
496 | macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32 | ||
497 | macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d" | ||
498 | + | ||
499 | +# dm163.c | ||
500 | +dm163_redraw(uint8_t redraw) "0x%02x" | ||
501 | +dm163_dck(unsigned new_state) "dck : %u" | ||
502 | +dm163_en_b(unsigned new_state) "en_b : %u" | ||
503 | +dm163_rst_b(unsigned new_state) "rst_b : %u" | ||
504 | +dm163_lat_b(unsigned new_state) "lat_b : %u" | ||
505 | +dm163_sin(unsigned new_state) "sin : %u" | ||
506 | +dm163_selbk(unsigned new_state) "selbk : %u" | ||
507 | +dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 "" | ||
508 | +dm163_bits_ppi(unsigned dest_width) "dest_width : %u" | ||
509 | +dm163_leds(int led, uint32_t value) "led %d: 0x%x" | ||
510 | +dm163_channels(int channel, uint8_t value) "channel %d: 0x%x" | ||
511 | +dm163_refresh_rate(uint32_t rr) "refresh rate %d" | ||
352 | -- | 512 | -- |
353 | 2.34.1 | 513 | 2.34.1 |
514 | |||
515 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | Move this earlier to make the next patch diff cleaner. While here | 3 | Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC |
4 | update the comment slightly to not give the impression that the | 4 | to the optional DM163 display from the board code (GPIOs outputs need |
5 | misalignment affects only TCG. | 5 | to be connected to both SYSCFG inputs and DM163 inputs). |
6 | 6 | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. |
8 | |||
9 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
10 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 12 | Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr |
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 14 | --- |
13 | target/arm/machine.c | 18 +++++++++--------- | 15 | hw/arm/stm32l4x5_soc.c | 6 ++++-- |
14 | 1 file changed, 9 insertions(+), 9 deletions(-) | 16 | tests/qtest/stm32l4x5_gpio-test.c | 13 ++++++++----- |
17 | tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++------- | ||
18 | 3 files changed, 22 insertions(+), 14 deletions(-) | ||
15 | 19 | ||
16 | diff --git a/target/arm/machine.c b/target/arm/machine.c | 20 | diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c |
17 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/machine.c | 22 | --- a/hw/arm/stm32l4x5_soc.c |
19 | +++ b/target/arm/machine.c | 23 | +++ b/hw/arm/stm32l4x5_soc.c |
20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | 24 | @@ -XXX,XX +XXX,XX @@ |
25 | /* | ||
26 | * STM32L4x5 SoC family | ||
27 | * | ||
28 | - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
29 | - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
30 | + * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
31 | + * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
32 | * | ||
33 | * SPDX-License-Identifier: GPL-2.0-or-later | ||
34 | * | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) | ||
21 | } | 36 | } |
22 | } | 37 | } |
23 | 38 | ||
24 | + /* | 39 | + qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL); |
25 | + * Misaligned thumb pc is architecturally impossible. Fail the | ||
26 | + * incoming migration. For TCG it would trigger the assert in | ||
27 | + * thumb_tr_translate_insn(). | ||
28 | + */ | ||
29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
30 | + return -1; | ||
31 | + } | ||
32 | + | 40 | + |
33 | hw_breakpoint_update_all(cpu); | 41 | /* EXTI device */ |
34 | hw_watchpoint_update_all(cpu); | 42 | busdev = SYS_BUS_DEVICE(&s->exti); |
35 | 43 | if (!sysbus_realize(busdev, errp)) { | |
36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | 44 | diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c |
37 | } | 45 | index XXXXXXX..XXXXXXX 100644 |
38 | } | 46 | --- a/tests/qtest/stm32l4x5_gpio-test.c |
39 | 47 | +++ b/tests/qtest/stm32l4x5_gpio-test.c | |
40 | - /* | 48 | @@ -XXX,XX +XXX,XX @@ |
41 | - * Misaligned thumb pc is architecturally impossible. | 49 | #define OTYPER_PUSH_PULL 0 |
42 | - * We have an assert in thumb_tr_translate_insn to verify this. | 50 | #define OTYPER_OPEN_DRAIN 1 |
43 | - * Fail an incoming migrate to avoid this assert. | 51 | |
44 | - */ | 52 | +/* SoC forwards GPIOs to SysCfg */ |
45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | 53 | +#define SYSCFG "/machine/soc" |
46 | - return -1; | 54 | + |
47 | - } | 55 | const uint32_t moder_reset[NUM_GPIOS] = { |
48 | - | 56 | 0xABFFFFFF, |
49 | if (!kvm_enabled()) { | 57 | 0xFFFFFEBF, |
50 | pmu_op_finish(&cpu->env); | 58 | @@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data) |
51 | } | 59 | uint32_t gpio = test_gpio_addr(data); |
60 | unsigned int gpio_id = get_gpio_id(gpio); | ||
61 | |||
62 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
63 | + qtest_irq_intercept_in(global_qtest, SYSCFG); | ||
64 | |||
65 | /* Set a bit in ODR and check nothing happens */ | ||
66 | gpio_set_bit(gpio, ODR, pin, 1); | ||
67 | @@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data) | ||
68 | uint32_t gpio = test_gpio_addr(data); | ||
69 | unsigned int gpio_id = get_gpio_id(gpio); | ||
70 | |||
71 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
72 | + qtest_irq_intercept_in(global_qtest, SYSCFG); | ||
73 | |||
74 | /* Configure a line as input, raise it, and check that the pin is high */ | ||
75 | gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); | ||
76 | @@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data) | ||
77 | uint32_t gpio = test_gpio_addr(data); | ||
78 | unsigned int gpio_id = get_gpio_id(gpio); | ||
79 | |||
80 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
81 | + qtest_irq_intercept_in(global_qtest, SYSCFG); | ||
82 | |||
83 | /* Configure a line as input with pull-up, check the line is set high */ | ||
84 | gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); | ||
85 | @@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data) | ||
86 | uint32_t gpio = test_gpio_addr(data); | ||
87 | uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); | ||
88 | |||
89 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
90 | + qtest_irq_intercept_in(global_qtest, SYSCFG); | ||
91 | |||
92 | /* Setting a line high externally, configuring it in push-pull output */ | ||
93 | /* And checking the pin was disconnected */ | ||
94 | @@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data) | ||
95 | uint32_t gpio = test_gpio_addr(data); | ||
96 | uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); | ||
97 | |||
98 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
99 | + qtest_irq_intercept_in(global_qtest, SYSCFG); | ||
100 | |||
101 | /* Setting a line high externally, configuring it in open-drain output */ | ||
102 | /* And checking the pin was disconnected */ | ||
103 | diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/tests/qtest/stm32l4x5_syscfg-test.c | ||
106 | +++ b/tests/qtest/stm32l4x5_syscfg-test.c | ||
107 | @@ -XXX,XX +XXX,XX @@ | ||
108 | /* | ||
109 | * QTest testcase for STM32L4x5_SYSCFG | ||
110 | * | ||
111 | - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
112 | - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
113 | + * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
114 | + * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
115 | * | ||
116 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
117 | * See the COPYING file in the top-level directory. | ||
118 | @@ -XXX,XX +XXX,XX @@ | ||
119 | #define SYSCFG_SWPR2 0x28 | ||
120 | #define INVALID_ADDR 0x2C | ||
121 | |||
122 | +/* SoC forwards GPIOs to SysCfg */ | ||
123 | +#define SYSCFG "/machine/soc" | ||
124 | +#define EXTI "/machine/soc/exti" | ||
125 | + | ||
126 | static void syscfg_writel(unsigned int offset, uint32_t value) | ||
127 | { | ||
128 | writel(SYSCFG_BASE_ADDR + offset, value); | ||
129 | @@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset) | ||
130 | |||
131 | static void syscfg_set_irq(int num, int level) | ||
132 | { | ||
133 | - qtest_set_irq_in(global_qtest, "/machine/soc/syscfg", | ||
134 | - NULL, num, level); | ||
135 | + qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level); | ||
136 | } | ||
137 | |||
138 | static void system_reset(void) | ||
139 | @@ -XXX,XX +XXX,XX @@ static void test_interrupt(void) | ||
140 | * Test that GPIO rising lines result in an irq | ||
141 | * with the right configuration | ||
142 | */ | ||
143 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); | ||
144 | + qtest_irq_intercept_in(global_qtest, EXTI); | ||
145 | |||
146 | /* GPIOA is the default source for EXTI lines 0 to 15 */ | ||
147 | |||
148 | @@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void) | ||
149 | * Test that syscfg irq sets the right exti irq | ||
150 | */ | ||
151 | |||
152 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); | ||
153 | + qtest_irq_intercept_in(global_qtest, EXTI); | ||
154 | |||
155 | syscfg_set_irq(0, 1); | ||
156 | |||
157 | @@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void) | ||
158 | * Test that an irq is generated only by the right GPIO | ||
159 | */ | ||
160 | |||
161 | - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); | ||
162 | + qtest_irq_intercept_in(global_qtest, EXTI); | ||
163 | |||
164 | /* GPIOA is the default source for EXTI lines 0 to 15 */ | ||
165 | |||
52 | -- | 166 | -- |
53 | 2.34.1 | 167 | 2.34.1 |
54 | 168 | ||
55 | 169 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
5 | Message-id: 20230206223502.25122-5-philmd@linaro.org | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | target/arm/helper.c | 12 ++++++++++-- | 9 | hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++------------- |
9 | 1 file changed, 10 insertions(+), 2 deletions(-) | 10 | 1 file changed, 32 insertions(+), 14 deletions(-) |
10 | 11 | ||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/helper.c | 14 | --- a/hw/arm/b-l475e-iot01a.c |
14 | +++ b/target/arm/helper.c | 15 | +++ b/hw/arm/b-l475e-iot01a.c |
15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | 16 | @@ -XXX,XX +XXX,XX @@ |
16 | } | 17 | * B-L475E-IOT01A Discovery Kit machine |
18 | * (B-L475E-IOT01A IoT Node) | ||
19 | * | ||
20 | - * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
21 | - * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
22 | + * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
23 | + * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
24 | * | ||
25 | * SPDX-License-Identifier: GPL-2.0-or-later | ||
26 | * | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | |||
29 | /* B-L475E-IOT01A implementation is derived from netduinoplus2 */ | ||
30 | |||
31 | -static void b_l475e_iot01a_init(MachineState *machine) | ||
32 | +#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") | ||
33 | +OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) | ||
34 | + | ||
35 | +typedef struct Bl475eMachineState { | ||
36 | + MachineState parent_obj; | ||
37 | + | ||
38 | + Stm32l4x5SocState soc; | ||
39 | +} Bl475eMachineState; | ||
40 | + | ||
41 | +static void bl475e_init(MachineState *machine) | ||
42 | { | ||
43 | + Bl475eMachineState *s = B_L475E_IOT01A(machine); | ||
44 | const Stm32l4x5SocClass *sc; | ||
45 | - DeviceState *dev; | ||
46 | |||
47 | - dev = qdev_new(TYPE_STM32L4X5XG_SOC); | ||
48 | - object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); | ||
49 | - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
50 | + object_initialize_child(OBJECT(machine), "soc", &s->soc, | ||
51 | + TYPE_STM32L4X5XG_SOC); | ||
52 | + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); | ||
53 | |||
54 | - sc = STM32L4X5_SOC_GET_CLASS(dev); | ||
55 | - armv7m_load_kernel(ARM_CPU(first_cpu), | ||
56 | - machine->kernel_filename, | ||
57 | - 0, sc->flash_size); | ||
58 | + sc = STM32L4X5_SOC_GET_CLASS(&s->soc); | ||
59 | + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0, | ||
60 | + sc->flash_size); | ||
17 | } | 61 | } |
18 | 62 | ||
19 | +#ifndef CONFIG_USER_ONLY | 63 | -static void b_l475e_iot01a_machine_init(MachineClass *mc) |
20 | /* | 64 | +static void bl475e_machine_init(ObjectClass *oc, void *data) |
21 | * We don't know until after realize whether there's a GICv3 | 65 | { |
22 | * attached, and that is what registers the gicv3 sysregs. | 66 | + MachineClass *mc = MACHINE_CLASS(oc); |
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | 67 | static const char *machine_valid_cpu_types[] = { |
24 | return pfr1; | 68 | ARM_CPU_TYPE_NAME("cortex-m4"), |
69 | NULL | ||
70 | }; | ||
71 | mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)"; | ||
72 | - mc->init = b_l475e_iot01a_init; | ||
73 | + mc->init = bl475e_init; | ||
74 | mc->valid_cpu_types = machine_valid_cpu_types; | ||
75 | |||
76 | /* SRAM pre-allocated as part of the SoC instantiation */ | ||
77 | mc->default_ram_size = 0; | ||
25 | } | 78 | } |
26 | 79 | ||
27 | -#ifndef CONFIG_USER_ONLY | 80 | -DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init) |
28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | 81 | +static const TypeInfo bl475e_machine_type[] = { |
29 | { | 82 | + { |
30 | ARMCPU *cpu = env_archcpu(env); | 83 | + .name = TYPE_B_L475E_IOT01A, |
31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 84 | + .parent = TYPE_MACHINE, |
32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | 85 | + .instance_size = sizeof(Bl475eMachineState), |
33 | .access = PL1_R, .type = ARM_CP_NO_RAW, | 86 | + .class_init = bl475e_machine_init, |
34 | .accessfn = access_aa32_tid3, | 87 | + } |
35 | +#ifdef CONFIG_USER_ONLY | 88 | +}; |
36 | + .type = ARM_CP_CONST, | 89 | + |
37 | + .resetvalue = cpu->isar.id_pfr1, | 90 | +DEFINE_TYPES(bl475e_machine_type) |
38 | +#else | ||
39 | + .type = ARM_CP_NO_RAW, | ||
40 | + .accessfn = access_aa32_tid3, | ||
41 | .readfn = id_pfr1_read, | ||
42 | - .writefn = arm_cp_write_ignore }, | ||
43 | + .writefn = arm_cp_write_ignore | ||
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
49 | -- | 91 | -- |
50 | 2.34.1 | 92 | 2.34.1 |
51 | 93 | ||
52 | 94 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Message-id: 20230206223502.25122-9-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 2 +- | ||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
16 | } sau; | ||
17 | |||
18 | void *nvic; | ||
19 | - const struct arm_boot_info *boot_info; | ||
20 | #if !defined(CONFIG_USER_ONLY) | ||
21 | + const struct arm_boot_info *boot_info; | ||
22 | /* Store GICv3CPUState to access from this struct */ | ||
23 | void *gicv3state; | ||
24 | #else /* CONFIG_USER_ONLY */ | ||
25 | -- | ||
26 | 2.34.1 | ||
27 | |||
28 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20230206223502.25122-10-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | target/arm/cpu.h | 2 +- | ||
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/target/arm/cpu.h | ||
14 | +++ b/target/arm/cpu.h | ||
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
16 | uint32_t ctrl; | ||
17 | } sau; | ||
18 | |||
19 | - void *nvic; | ||
20 | #if !defined(CONFIG_USER_ONLY) | ||
21 | + void *nvic; | ||
22 | const struct arm_boot_info *boot_info; | ||
23 | /* Store GICv3CPUState to access from this struct */ | ||
24 | void *gicv3state; | ||
25 | -- | ||
26 | 2.34.1 | ||
27 | |||
28 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | While dozens of files include "cpu.h", only 3 files require | ||
4 | these NVIC helper declarations. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20230206223502.25122-12-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/cpu.h | 123 ---------------------------------- | ||
13 | target/arm/cpu.c | 4 +- | ||
14 | target/arm/cpu_tcg.c | 3 + | ||
15 | target/arm/m_helper.c | 3 + | ||
16 | 5 files changed, 132 insertions(+), 124 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/intc/armv7m_nvic.h | ||
21 | +++ b/include/hw/intc/armv7m_nvic.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | ||
23 | qemu_irq sysresetreq; | ||
24 | }; | ||
25 | |||
26 | +/* Interface between CPU and Interrupt controller. */ | ||
27 | +/** | ||
28 | + * armv7m_nvic_set_pending: mark the specified exception as pending | ||
29 | + * @s: the NVIC | ||
30 | + * @irq: the exception number to mark pending | ||
31 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
32 | + * version of a banked exception, true for the secure version of a banked | ||
33 | + * exception. | ||
34 | + * | ||
35 | + * Marks the specified exception as pending. Note that we will assert() | ||
36 | + * if @secure is true and @irq does not specify one of the fixed set | ||
37 | + * of architecturally banked exceptions. | ||
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
148 | + | ||
149 | #endif | ||
150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/cpu.h | ||
153 | +++ b/target/arm/cpu.h | ||
154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
156 | uint32_t cur_el, bool secure); | ||
157 | |||
158 | -/* Interface between CPU and Interrupt controller. */ | ||
159 | -#ifndef CONFIG_USER_ONLY | ||
160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
161 | -#else | ||
162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
163 | -{ | ||
164 | - return true; | ||
165 | -} | ||
166 | -#endif | ||
167 | -/** | ||
168 | - * armv7m_nvic_set_pending: mark the specified exception as pending | ||
169 | - * @s: the NVIC | ||
170 | - * @irq: the exception number to mark pending | ||
171 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
172 | - * version of a banked exception, true for the secure version of a banked | ||
173 | - * exception. | ||
174 | - * | ||
175 | - * Marks the specified exception as pending. Note that we will assert() | ||
176 | - * if @secure is true and @irq does not specify one of the fixed set | ||
177 | - * of architecturally banked exceptions. | ||
178 | - */ | ||
179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
180 | -/** | ||
181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
182 | - * @s: the NVIC | ||
183 | - * @irq: the exception number to mark pending | ||
184 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
279 | -#endif | ||
280 | - | ||
281 | /* Interface for defining coprocessor registers. | ||
282 | * Registers are defined in tables of arm_cp_reginfo structs | ||
283 | * which are passed to define_arm_cp_regs(). | ||
284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/target/arm/cpu.c | ||
287 | +++ b/target/arm/cpu.c | ||
288 | @@ -XXX,XX +XXX,XX @@ | ||
289 | #if !defined(CONFIG_USER_ONLY) | ||
290 | #include "hw/loader.h" | ||
291 | #include "hw/boards.h" | ||
292 | +#ifdef CONFIG_TCG | ||
293 | #include "hw/intc/armv7m_nvic.h" | ||
294 | -#endif | ||
295 | +#endif /* CONFIG_TCG */ | ||
296 | +#endif /* !CONFIG_USER_ONLY */ | ||
297 | #include "sysemu/tcg.h" | ||
298 | #include "sysemu/qtest.h" | ||
299 | #include "sysemu/hw_accel.h" | ||
300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
301 | index XXXXXXX..XXXXXXX 100644 | ||
302 | --- a/target/arm/cpu_tcg.c | ||
303 | +++ b/target/arm/cpu_tcg.c | ||
304 | @@ -XXX,XX +XXX,XX @@ | ||
305 | #include "hw/boards.h" | ||
306 | #endif | ||
307 | #include "cpregs.h" | ||
308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
309 | +#include "hw/intc/armv7m_nvic.h" | ||
310 | +#endif | ||
311 | |||
312 | |||
313 | /* Share AArch32 -cpu max features with AArch64. */ | ||
314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/m_helper.c | ||
317 | +++ b/target/arm/m_helper.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
328 | -- | ||
329 | 2.34.1 | ||
330 | |||
331 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
2 | 1 | ||
3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros | ||
4 | that take a long time to boot up, especially for an --enable-debug | ||
5 | build. The total code coverage they give is: | ||
6 | |||
7 | Overall coverage rate: | ||
8 | lines......: 11.2% (59584 of 530123 lines) | ||
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | tests/avocado/boot_linux.py | 48 ++++---------------- | ||
35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- | ||
36 | 2 files changed, 65 insertions(+), 46 deletions(-) | ||
37 | |||
38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/tests/avocado/boot_linux.py | ||
41 | +++ b/tests/avocado/boot_linux.py | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): | ||
43 | self.launch_and_wait(set_up_ssh_connection=False) | ||
44 | |||
45 | |||
46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very | ||
47 | -# heavyweight. There are lighter weight distros which we use in the | ||
48 | -# machine_aarch64_virt.py tests. | ||
49 | +# For Aarch64 we only boot KVM tests in CI as booting the current | ||
50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight | ||
51 | +# distros which we use in the machine_aarch64_virt.py tests. | ||
52 | class BootLinuxAarch64(LinuxTest): | ||
53 | """ | ||
54 | :avocado: tags=arch:aarch64 | ||
55 | :avocado: tags=machine:virt | ||
56 | - :avocado: tags=machine:gic-version=2 | ||
57 | """ | ||
58 | timeout = 720 | ||
59 | |||
60 | - def add_common_args(self): | ||
61 | - self.vm.add_args('-bios', | ||
62 | - os.path.join(BUILD_DIR, 'pc-bios', | ||
63 | - 'edk2-aarch64-code.fd')) | ||
64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
66 | - | ||
67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
68 | - def test_fedora_cloud_tcg_gicv2(self): | ||
69 | - """ | ||
70 | - :avocado: tags=accel:tcg | ||
71 | - :avocado: tags=cpu:max | ||
72 | - :avocado: tags=device:gicv2 | ||
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/tests/avocado/machine_aarch64_virt.py | ||
114 | +++ b/tests/avocado/machine_aarch64_virt.py | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | |||
117 | import time | ||
118 | import os | ||
119 | +import logging | ||
120 | |||
121 | from avocado_qemu import QemuSystemTest | ||
122 | from avocado_qemu import wait_for_console_pattern | ||
123 | from avocado_qemu import exec_command | ||
124 | from avocado_qemu import BUILD_DIR | ||
125 | +from avocado.utils import process | ||
126 | +from avocado.utils.path import find_command | ||
127 | |||
128 | class Aarch64VirtMachine(QemuSystemTest): | ||
129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' | ||
130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): | ||
131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') | ||
132 | |||
133 | |||
134 | - def test_aarch64_virt(self): | ||
135 | + def common_aarch64_virt(self, machine): | ||
136 | """ | ||
137 | - :avocado: tags=arch:aarch64 | ||
138 | - :avocado: tags=machine:virt | ||
139 | - :avocado: tags=accel:tcg | ||
140 | - :avocado: tags=cpu:max | ||
141 | + Common code to launch basic virt machine with kernel+initrd | ||
142 | + and a scratch disk. | ||
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
215 | -- | ||
216 | 2.34.1 | ||
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with | 3 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> |
4 | a QEMU configured using --without-default-devices, we get: | 4 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> |
5 | 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
6 | $ qemu-system-aarch64 -M xlnx-zcu102 | 6 | Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr |
7 | qemu-system-aarch64: missing object type 'usb_dwc3' | ||
8 | Abort trap: 6 | ||
9 | |||
10 | Fix by adding the missing Kconfig dependency. | ||
11 | |||
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 8 | --- |
18 | hw/arm/Kconfig | 1 + | 9 | hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++-- |
19 | 1 file changed, 1 insertion(+) | 10 | hw/arm/Kconfig | 1 + |
11 | 2 files changed, 58 insertions(+), 2 deletions(-) | ||
20 | 12 | ||
13 | diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/b-l475e-iot01a.c | ||
16 | +++ b/hw/arm/b-l475e-iot01a.c | ||
17 | @@ -XXX,XX +XXX,XX @@ | ||
18 | #include "hw/boards.h" | ||
19 | #include "hw/qdev-properties.h" | ||
20 | #include "qemu/error-report.h" | ||
21 | -#include "hw/arm/stm32l4x5_soc.h" | ||
22 | #include "hw/arm/boot.h" | ||
23 | +#include "hw/core/split-irq.h" | ||
24 | +#include "hw/arm/stm32l4x5_soc.h" | ||
25 | +#include "hw/gpio/stm32l4x5_gpio.h" | ||
26 | +#include "hw/display/dm163.h" | ||
27 | |||
28 | -/* B-L475E-IOT01A implementation is derived from netduinoplus2 */ | ||
29 | +/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */ | ||
30 | + | ||
31 | +/* | ||
32 | + * There are actually 14 input pins in the DM163 device. | ||
33 | + * Here the DM163 input pin EN isn't connected to the STM32L4x5 | ||
34 | + * GPIOs as the IM120417002 colors shield doesn't actually use | ||
35 | + * this pin to drive the RGB matrix. | ||
36 | + */ | ||
37 | +#define NUM_DM163_INPUTS 13 | ||
38 | + | ||
39 | +static const unsigned dm163_input[NUM_DM163_INPUTS] = { | ||
40 | + 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */ | ||
41 | + 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */ | ||
42 | + 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */ | ||
43 | + 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */ | ||
44 | + 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */ | ||
45 | + 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */ | ||
46 | + 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */ | ||
47 | + 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */ | ||
48 | + 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */ | ||
49 | + 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */ | ||
50 | + 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */ | ||
51 | + 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */ | ||
52 | + 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */ | ||
53 | +}; | ||
54 | |||
55 | #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") | ||
56 | OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState { | ||
58 | MachineState parent_obj; | ||
59 | |||
60 | Stm32l4x5SocState soc; | ||
61 | + SplitIRQ gpio_splitters[NUM_DM163_INPUTS]; | ||
62 | + DM163State dm163; | ||
63 | } Bl475eMachineState; | ||
64 | |||
65 | static void bl475e_init(MachineState *machine) | ||
66 | { | ||
67 | Bl475eMachineState *s = B_L475E_IOT01A(machine); | ||
68 | const Stm32l4x5SocClass *sc; | ||
69 | + DeviceState *dev, *gpio_out_splitter; | ||
70 | + unsigned gpio, pin; | ||
71 | |||
72 | object_initialize_child(OBJECT(machine), "soc", &s->soc, | ||
73 | TYPE_STM32L4X5XG_SOC); | ||
74 | @@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine) | ||
75 | sc = STM32L4X5_SOC_GET_CLASS(&s->soc); | ||
76 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0, | ||
77 | sc->flash_size); | ||
78 | + | ||
79 | + if (object_class_by_name(TYPE_DM163)) { | ||
80 | + object_initialize_child(OBJECT(machine), "dm163", | ||
81 | + &s->dm163, TYPE_DM163); | ||
82 | + dev = DEVICE(&s->dm163); | ||
83 | + qdev_realize(dev, NULL, &error_abort); | ||
84 | + | ||
85 | + for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) { | ||
86 | + object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]", | ||
87 | + &s->gpio_splitters[i], TYPE_SPLIT_IRQ); | ||
88 | + gpio_out_splitter = DEVICE(&s->gpio_splitters[i]); | ||
89 | + qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2); | ||
90 | + qdev_realize(gpio_out_splitter, NULL, &error_fatal); | ||
91 | + | ||
92 | + qdev_connect_gpio_out(gpio_out_splitter, 0, | ||
93 | + qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i])); | ||
94 | + qdev_connect_gpio_out(gpio_out_splitter, 1, | ||
95 | + qdev_get_gpio_in(dev, i)); | ||
96 | + gpio = dm163_input[i] / GPIO_NUM_PINS; | ||
97 | + pin = dm163_input[i] % GPIO_NUM_PINS; | ||
98 | + qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, | ||
99 | + qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0)); | ||
100 | + } | ||
101 | + } | ||
102 | } | ||
103 | |||
104 | static void bl475e_machine_init(ObjectClass *oc, void *data) | ||
21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 105 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
22 | index XXXXXXX..XXXXXXX 100644 | 106 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Kconfig | 107 | --- a/hw/arm/Kconfig |
24 | +++ b/hw/arm/Kconfig | 108 | +++ b/hw/arm/Kconfig |
25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM | 109 | @@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A |
26 | select XLNX_CSU_DMA | 110 | default y |
27 | select XLNX_ZYNQMP | 111 | depends on TCG && ARM |
28 | select XLNX_ZDMA | 112 | select STM32L4X5_SOC |
29 | + select USB_DWC3 | 113 | + imply DM163 |
30 | 114 | ||
31 | config XLNX_VERSAL | 115 | config STM32L4X5_SOC |
32 | bool | 116 | bool |
33 | -- | 117 | -- |
34 | 2.34.1 | 118 | 2.34.1 |
35 | 119 | ||
36 | 120 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cornelia Huck <cohuck@redhat.com> | ||
2 | 1 | ||
3 | Just use current_accel_name() directly. | ||
4 | |||
5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> | ||
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/virt.c | 6 +++--- | ||
11 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/virt.c | ||
16 | +++ b/hw/arm/virt.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { | ||
19 | error_report("mach-virt: %s does not support providing " | ||
20 | "Security extensions (TrustZone) to the guest CPU", | ||
21 | - kvm_enabled() ? "KVM" : "HVF"); | ||
22 | + current_accel_name()); | ||
23 | exit(1); | ||
24 | } | ||
25 | |||
26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | ||
27 | error_report("mach-virt: %s does not support providing " | ||
28 | "Virtualization extensions to the guest CPU", | ||
29 | - kvm_enabled() ? "KVM" : "HVF"); | ||
30 | + current_accel_name()); | ||
31 | exit(1); | ||
32 | } | ||
33 | |||
34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { | ||
35 | error_report("mach-virt: %s does not support providing " | ||
36 | "MTE to the guest CPU", | ||
37 | - kvm_enabled() ? "KVM" : "HVF"); | ||
38 | + current_accel_name()); | ||
39 | exit(1); | ||
40 | } | ||
41 | |||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
2 | 1 | ||
3 | Havard is no longer working on the Nuvoton systems for a while | ||
4 | and won't be able to do any work on it in the future. So I'll | ||
5 | take over maintaining the Nuvoton system from him. | ||
6 | |||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/MAINTAINERS | ||
19 | +++ b/MAINTAINERS | ||
20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h | ||
21 | F: docs/system/arm/musicpal.rst | ||
22 | |||
23 | Nuvoton NPCM7xx | ||
24 | -M: Havard Skinnemoen <hskinnemoen@google.com> | ||
25 | M: Tyrone Ting <kfting@nuvoton.com> | ||
26 | +M: Hao Wu <wuhaotsh@google.com> | ||
27 | L: qemu-arm@nongnu.org | ||
28 | S: Supported | ||
29 | F: hw/*/npcm7xx* | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
2 | 1 | ||
3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
4 | Reviewed-by: Titus Rwantare <titusr@google.com> | ||
5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | docs/system/arm/nuvoton.rst | 2 +- | ||
10 | include/hw/arm/npcm7xx.h | 2 ++ | ||
11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- | ||
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | ||
13 | |||
14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/docs/system/arm/nuvoton.rst | ||
17 | +++ b/docs/system/arm/nuvoton.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ Supported devices | ||
19 | * SMBus controller (SMBF) | ||
20 | * Ethernet controller (EMC) | ||
21 | * Tachometer | ||
22 | + * Peripheral SPI controller (PSPI) | ||
23 | |||
24 | Missing devices | ||
25 | --------------- | ||
26 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
27 | |||
28 | * Ethernet controller (GMAC) | ||
29 | * USB device (USBD) | ||
30 | - * Peripheral SPI controller (PSPI) | ||
31 | * SD/MMC host | ||
32 | * PECI interface | ||
33 | * PCI and PCIe root complex and bridges | ||
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/npcm7xx.h | ||
37 | +++ b/include/hw/arm/npcm7xx.h | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hw/nvram/npcm7xx_otp.h" | ||
40 | #include "hw/timer/npcm7xx_timer.h" | ||
41 | #include "hw/ssi/npcm7xx_fiu.h" | ||
42 | +#include "hw/ssi/npcm_pspi.h" | ||
43 | #include "hw/usb/hcd-ehci.h" | ||
44 | #include "hw/usb/hcd-ohci.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { | ||
47 | NPCM7xxFIUState fiu[2]; | ||
48 | NPCM7xxEMCState emc[2]; | ||
49 | NPCM7xxSDHCIState mmc; | ||
50 | + NPCMPSPIState pspi[2]; | ||
51 | }; | ||
52 | |||
53 | #define TYPE_NPCM7XX "npcm7xx" | ||
54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/arm/npcm7xx.c | ||
57 | +++ b/hw/arm/npcm7xx.c | ||
58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
59 | NPCM7XX_EMC1RX_IRQ = 15, | ||
60 | NPCM7XX_EMC1TX_IRQ, | ||
61 | NPCM7XX_MMC_IRQ = 26, | ||
62 | + NPCM7XX_PSPI2_IRQ = 28, | ||
63 | + NPCM7XX_PSPI1_IRQ = 31, | ||
64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ | ||
65 | NPCM7XX_TIMER1_IRQ, | ||
66 | NPCM7XX_TIMER2_IRQ, | ||
67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { | ||
68 | 0xf0826000, | ||
69 | }; | ||
70 | |||
71 | +/* Register base address for each PSPI Module */ | ||
72 | +static const hwaddr npcm7xx_pspi_addr[] = { | ||
73 | + 0xf0200000, | ||
74 | + 0xf0201000, | ||
75 | +}; | ||
76 | + | ||
77 | static const struct { | ||
78 | hwaddr regs_addr; | ||
79 | uint32_t unconnected_pins; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | ||
81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); | ||
82 | } | ||
83 | |||
84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); | ||
86 | + } | ||
87 | + | ||
88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); | ||
89 | } | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, | ||
93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); | ||
94 | |||
95 | + /* PSPI */ | ||
96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); | ||
97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | ||
98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); | ||
99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; | ||
100 | + | ||
101 | + sysbus_realize(sbd, &error_abort); | ||
102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); | ||
103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); | ||
104 | + } | ||
105 | + | ||
106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); | ||
107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | ||
108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | ||
109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | ||
111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | ||
112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); | ||
114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); | ||
115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); | ||
116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); | ||
117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); | ||
118 | -- | ||
119 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
2 | 1 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/smmu-common.h | 2 -- | ||
13 | hw/arm/smmu-common.c | 2 +- | ||
14 | 2 files changed, 1 insertion(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/smmu-common.h | ||
19 | +++ b/include/hw/arm/smmu-common.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define SMMU_PCI_DEVFN_MAX 256 | ||
22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) | ||
23 | |||
24 | -#define SMMU_MAX_VA_BITS 48 | ||
25 | - | ||
26 | /* | ||
27 | * Page table walk error types | ||
28 | */ | ||
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/smmu-common.c | ||
32 | +++ b/hw/arm/smmu-common.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
34 | |||
35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | ||
36 | s->mrtypename, | ||
37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); | ||
38 | + OBJECT(s), name, UINT64_MAX); | ||
39 | address_space_init(&sdev->as, | ||
40 | MEMORY_REGION(&sdev->iommu), name); | ||
41 | trace_smmu_add_mr(name); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Inès Varhol <ines.varhol@telecom-paris.fr> |
---|---|---|---|
2 | 2 | ||
3 | These tests set -accel tcg, so restrict them to when TCG is present. | 3 | `test_dm163_bank()` |
4 | 4 | Checks that the pin "sout" of the DM163 led driver outputs the values | |
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 5 | received on pin "sin" with the expected latency (depending on the bank). |
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | 6 | |
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 7 | `test_dm163_gpio_connection()` |
8 | Check that changes to relevant STM32L4x5 GPIO pins are propagated to the | ||
9 | DM163 device. | ||
10 | |||
11 | Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
12 | Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
13 | Acked-by: Thomas Huth <thuth@redhat.com> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
15 | Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 17 | --- |
10 | tests/qtest/meson.build | 4 ++-- | 18 | tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++ |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 19 | tests/qtest/meson.build | 2 + |
12 | 20 | 2 files changed, 196 insertions(+) | |
21 | create mode 100644 tests/qtest/dm163-test.c | ||
22 | |||
23 | diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c | ||
24 | new file mode 100644 | ||
25 | index XXXXXXX..XXXXXXX | ||
26 | --- /dev/null | ||
27 | +++ b/tests/qtest/dm163-test.c | ||
28 | @@ -XXX,XX +XXX,XX @@ | ||
29 | +/* | ||
30 | + * QTest testcase for DM163 | ||
31 | + * | ||
32 | + * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net> | ||
33 | + * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
34 | + * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr> | ||
35 | + * | ||
36 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
37 | + */ | ||
38 | + | ||
39 | +#include "qemu/osdep.h" | ||
40 | +#include "libqtest.h" | ||
41 | + | ||
42 | +enum DM163_INPUTS { | ||
43 | + SIN = 8, | ||
44 | + DCK = 9, | ||
45 | + RST_B = 10, | ||
46 | + LAT_B = 11, | ||
47 | + SELBK = 12, | ||
48 | + EN_B = 13 | ||
49 | +}; | ||
50 | + | ||
51 | +#define DEVICE_NAME "/machine/dm163" | ||
52 | +#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \ | ||
53 | + value) | ||
54 | +#define GPIO_PULSE(name) \ | ||
55 | + do { \ | ||
56 | + GPIO_OUT(name, 1); \ | ||
57 | + GPIO_OUT(name, 0); \ | ||
58 | + } while (0) | ||
59 | + | ||
60 | + | ||
61 | +static void rise_gpio_pin_dck(QTestState *qts) | ||
62 | +{ | ||
63 | + /* Configure output mode for pin PB1 */ | ||
64 | + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); | ||
65 | + /* Write 1 in ODR for PB1 */ | ||
66 | + qtest_writel(qts, 0x48000414, 0x00000002); | ||
67 | +} | ||
68 | + | ||
69 | +static void lower_gpio_pin_dck(QTestState *qts) | ||
70 | +{ | ||
71 | + /* Configure output mode for pin PB1 */ | ||
72 | + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); | ||
73 | + /* Write 0 in ODR for PB1 */ | ||
74 | + qtest_writel(qts, 0x48000414, 0x00000000); | ||
75 | +} | ||
76 | + | ||
77 | +static void rise_gpio_pin_selbk(QTestState *qts) | ||
78 | +{ | ||
79 | + /* Configure output mode for pin PC5 */ | ||
80 | + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); | ||
81 | + /* Write 1 in ODR for PC5 */ | ||
82 | + qtest_writel(qts, 0x48000814, 0x00000020); | ||
83 | +} | ||
84 | + | ||
85 | +static void lower_gpio_pin_selbk(QTestState *qts) | ||
86 | +{ | ||
87 | + /* Configure output mode for pin PC5 */ | ||
88 | + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); | ||
89 | + /* Write 0 in ODR for PC5 */ | ||
90 | + qtest_writel(qts, 0x48000814, 0x00000000); | ||
91 | +} | ||
92 | + | ||
93 | +static void rise_gpio_pin_lat_b(QTestState *qts) | ||
94 | +{ | ||
95 | + /* Configure output mode for pin PC4 */ | ||
96 | + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); | ||
97 | + /* Write 1 in ODR for PC4 */ | ||
98 | + qtest_writel(qts, 0x48000814, 0x00000010); | ||
99 | +} | ||
100 | + | ||
101 | +static void lower_gpio_pin_lat_b(QTestState *qts) | ||
102 | +{ | ||
103 | + /* Configure output mode for pin PC4 */ | ||
104 | + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); | ||
105 | + /* Write 0 in ODR for PC4 */ | ||
106 | + qtest_writel(qts, 0x48000814, 0x00000000); | ||
107 | +} | ||
108 | + | ||
109 | +static void rise_gpio_pin_rst_b(QTestState *qts) | ||
110 | +{ | ||
111 | + /* Configure output mode for pin PC3 */ | ||
112 | + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); | ||
113 | + /* Write 1 in ODR for PC3 */ | ||
114 | + qtest_writel(qts, 0x48000814, 0x00000008); | ||
115 | +} | ||
116 | + | ||
117 | +static void lower_gpio_pin_rst_b(QTestState *qts) | ||
118 | +{ | ||
119 | + /* Configure output mode for pin PC3 */ | ||
120 | + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); | ||
121 | + /* Write 0 in ODR for PC3 */ | ||
122 | + qtest_writel(qts, 0x48000814, 0x00000000); | ||
123 | +} | ||
124 | + | ||
125 | +static void rise_gpio_pin_sin(QTestState *qts) | ||
126 | +{ | ||
127 | + /* Configure output mode for pin PA4 */ | ||
128 | + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); | ||
129 | + /* Write 1 in ODR for PA4 */ | ||
130 | + qtest_writel(qts, 0x48000014, 0x00000010); | ||
131 | +} | ||
132 | + | ||
133 | +static void lower_gpio_pin_sin(QTestState *qts) | ||
134 | +{ | ||
135 | + /* Configure output mode for pin PA4 */ | ||
136 | + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); | ||
137 | + /* Write 0 in ODR for PA4 */ | ||
138 | + qtest_writel(qts, 0x48000014, 0x00000000); | ||
139 | +} | ||
140 | + | ||
141 | +static void test_dm163_bank(const void *opaque) | ||
142 | +{ | ||
143 | + const unsigned bank = (uintptr_t) opaque; | ||
144 | + const int width = bank ? 192 : 144; | ||
145 | + | ||
146 | + QTestState *qts = qtest_initf("-M b-l475e-iot01a"); | ||
147 | + qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout"); | ||
148 | + GPIO_OUT(RST_B, 1); | ||
149 | + GPIO_OUT(EN_B, 0); | ||
150 | + GPIO_OUT(DCK, 0); | ||
151 | + GPIO_OUT(SELBK, bank); | ||
152 | + GPIO_OUT(LAT_B, 1); | ||
153 | + | ||
154 | + /* Fill bank with zeroes */ | ||
155 | + GPIO_OUT(SIN, 0); | ||
156 | + for (int i = 0; i < width; i++) { | ||
157 | + GPIO_PULSE(DCK); | ||
158 | + } | ||
159 | + /* Fill bank with ones, check that we get the previous zeroes */ | ||
160 | + GPIO_OUT(SIN, 1); | ||
161 | + for (int i = 0; i < width; i++) { | ||
162 | + GPIO_PULSE(DCK); | ||
163 | + g_assert(!qtest_get_irq(qts, 0)); | ||
164 | + } | ||
165 | + | ||
166 | + /* Pulse one more bit in the bank, check that we get a one */ | ||
167 | + GPIO_PULSE(DCK); | ||
168 | + g_assert(qtest_get_irq(qts, 0)); | ||
169 | + | ||
170 | + qtest_quit(qts); | ||
171 | +} | ||
172 | + | ||
173 | +static void test_dm163_gpio_connection(void) | ||
174 | +{ | ||
175 | + QTestState *qts = qtest_init("-M b-l475e-iot01a"); | ||
176 | + qtest_irq_intercept_in(qts, DEVICE_NAME); | ||
177 | + | ||
178 | + g_assert_false(qtest_get_irq(qts, SIN)); | ||
179 | + g_assert_false(qtest_get_irq(qts, DCK)); | ||
180 | + g_assert_false(qtest_get_irq(qts, RST_B)); | ||
181 | + g_assert_false(qtest_get_irq(qts, LAT_B)); | ||
182 | + g_assert_false(qtest_get_irq(qts, SELBK)); | ||
183 | + | ||
184 | + rise_gpio_pin_dck(qts); | ||
185 | + g_assert_true(qtest_get_irq(qts, DCK)); | ||
186 | + lower_gpio_pin_dck(qts); | ||
187 | + g_assert_false(qtest_get_irq(qts, DCK)); | ||
188 | + | ||
189 | + rise_gpio_pin_lat_b(qts); | ||
190 | + g_assert_true(qtest_get_irq(qts, LAT_B)); | ||
191 | + lower_gpio_pin_lat_b(qts); | ||
192 | + g_assert_false(qtest_get_irq(qts, LAT_B)); | ||
193 | + | ||
194 | + rise_gpio_pin_selbk(qts); | ||
195 | + g_assert_true(qtest_get_irq(qts, SELBK)); | ||
196 | + lower_gpio_pin_selbk(qts); | ||
197 | + g_assert_false(qtest_get_irq(qts, SELBK)); | ||
198 | + | ||
199 | + rise_gpio_pin_rst_b(qts); | ||
200 | + g_assert_true(qtest_get_irq(qts, RST_B)); | ||
201 | + lower_gpio_pin_rst_b(qts); | ||
202 | + g_assert_false(qtest_get_irq(qts, RST_B)); | ||
203 | + | ||
204 | + rise_gpio_pin_sin(qts); | ||
205 | + g_assert_true(qtest_get_irq(qts, SIN)); | ||
206 | + lower_gpio_pin_sin(qts); | ||
207 | + g_assert_false(qtest_get_irq(qts, SIN)); | ||
208 | + | ||
209 | + g_assert_false(qtest_get_irq(qts, DCK)); | ||
210 | + g_assert_false(qtest_get_irq(qts, LAT_B)); | ||
211 | + g_assert_false(qtest_get_irq(qts, SELBK)); | ||
212 | + g_assert_false(qtest_get_irq(qts, RST_B)); | ||
213 | +} | ||
214 | + | ||
215 | +int main(int argc, char **argv) | ||
216 | +{ | ||
217 | + g_test_init(&argc, &argv, NULL); | ||
218 | + qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank); | ||
219 | + qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank); | ||
220 | + qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection); | ||
221 | + return g_test_run(); | ||
222 | +} | ||
13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | 223 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
14 | index XXXXXXX..XXXXXXX 100644 | 224 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/tests/qtest/meson.build | 225 | --- a/tests/qtest/meson.build |
16 | +++ b/tests/qtest/meson.build | 226 | +++ b/tests/qtest/meson.build |
17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ | 227 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ |
18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | 228 | (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \ |
19 | qtests_aarch64 = \ | 229 | (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \ |
20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ | 230 | (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \ |
21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ | 231 | + (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and |
22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ | 232 | + config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ |
23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ | ||
24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ | ||
25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ | ||
26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | ||
27 | ['arm-cpu-features', | 233 | ['arm-cpu-features', |
234 | 'boot-serial-test'] | ||
235 | |||
28 | -- | 236 | -- |
29 | 2.34.1 | 237 | 2.34.1 |
238 | |||
239 | diff view generated by jsdifflib |