1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: | 1 | The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a: |
---|---|---|---|
2 | 2 | ||
3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) | 3 | Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306 |
8 | 8 | ||
9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: | 9 | for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f: |
10 | 10 | ||
11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) | 11 | hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | target-arm queue: | 14 | target-arm queue: |
15 | * Some mostly M-profile-related code cleanups | 15 | * allwinner-h3: Fix I2C controller model for Sun6i SoCs |
16 | * avocado: Retire the boot_linux.py AArch64 TCG tests | 16 | * allwinner-h3: Add missing i2c controllers |
17 | * hw/arm/smmuv3: Add GBPA register | 17 | * Expose M-profile system registers to gdbstub |
18 | * arm/virt: don't try to spell out the accelerator | 18 | * Expose pauth information to gdbstub |
19 | * hw/arm: Attach PSPI module to NPCM7XX SoC | 19 | * Support direct boot for Linux/arm64 EFI zboot images |
20 | * Some cleanup/refactoring patches aiming towards | 20 | * Fix incorrect stage 2 MMU setup validation |
21 | allowing building Arm targets without CONFIG_TCG | ||
22 | 21 | ||
23 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
24 | Alex Bennée (1): | 23 | Ard Biesheuvel (1): |
25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py | 24 | hw: arm: Support direct boot for Linux/arm64 EFI zboot images |
26 | 25 | ||
27 | Claudio Fontana (3): | 26 | David Reiss (2): |
28 | target/arm: rename handle_semihosting to tcg_handle_semihosting | 27 | target/arm: Export arm_v7m_mrs_control |
29 | target/arm: wrap psci call with tcg_enabled | 28 | target/arm: Export arm_v7m_get_sp_ptr |
30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() | ||
31 | 29 | ||
32 | Cornelia Huck (1): | 30 | Richard Henderson (16): |
33 | arm/virt: don't try to spell out the accelerator | 31 | target/arm: Normalize aarch64 gdbstub get/set function names |
32 | target/arm: Unexport arm_gen_dynamic_sysreg_xml | ||
33 | target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c | ||
34 | target/arm: Split out output_vector_union_type | ||
35 | target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml | ||
36 | target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml | ||
37 | target/arm: Fix svep width in arm_gen_dynamic_svereg_xml | ||
38 | target/arm: Add name argument to output_vector_union_type | ||
39 | target/arm: Simplify iteration over bit widths | ||
40 | target/arm: Create pauth_ptr_mask | ||
41 | target/arm: Implement gdbstub pauth extension | ||
42 | target/arm: Implement gdbstub m-profile systemreg and secext | ||
43 | target/arm: Handle m-profile in arm_is_secure | ||
44 | target/arm: Stub arm_hcr_el2_eff for m-profile | ||
45 | target/arm: Diagnose incorrect usage of arm_is_secure subroutines | ||
46 | target/arm: Rewrite check_s2_mmu_setup | ||
34 | 47 | ||
35 | Fabiano Rosas (7): | 48 | qianfan Zhao (2): |
36 | target/arm: Move PC alignment check | 49 | hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs |
37 | target/arm: Move cpregs code out of cpu.h | 50 | hw: arm: allwinner-h3: Fix and complete H3 i2c devices |
38 | tests/avocado: Skip tests that require a missing accelerator | ||
39 | tests/avocado: Tag TCG tests with accel:tcg | ||
40 | target/arm: Use "max" as default cpu for the virt machine with KVM | ||
41 | tests/qtest: arm-cpu-features: Match tests to required accelerators | ||
42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG | ||
43 | 51 | ||
44 | Hao Wu (3): | 52 | configs/targets/aarch64-linux-user.mak | 2 +- |
45 | MAINTAINERS: Add myself to maintainers and remove Havard | 53 | configs/targets/aarch64-softmmu.mak | 2 +- |
46 | hw/ssi: Add Nuvoton PSPI Module | 54 | configs/targets/aarch64_be-linux-user.mak | 2 +- |
47 | hw/arm: Attach PSPI module to NPCM7XX SoC | 55 | include/hw/arm/allwinner-h3.h | 6 + |
48 | 56 | include/hw/i2c/allwinner-i2c.h | 6 + | |
49 | Jean-Philippe Brucker (2): | 57 | include/hw/loader.h | 19 ++ |
50 | hw/arm/smmu-common: Support 64-bit addresses | 58 | target/arm/cpu.h | 17 +- |
51 | hw/arm/smmu-common: Fix TTB1 handling | 59 | target/arm/internals.h | 34 +++- |
52 | 60 | hw/arm/allwinner-h3.c | 29 +++- | |
53 | Mostafa Saleh (1): | 61 | hw/arm/boot.c | 6 + |
54 | hw/arm/smmuv3: Add GBPA register | 62 | hw/core/loader.c | 91 ++++++++++ |
55 | 63 | hw/i2c/allwinner-i2c.c | 26 ++- | |
56 | Philippe Mathieu-Daudé (12): | 64 | target/arm/gdbstub.c | 278 ++++++++++++++++++------------ |
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | 65 | target/arm/gdbstub64.c | 175 ++++++++++++++++++- |
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | 66 | target/arm/helper.c | 3 + |
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | 67 | target/arm/ptw.c | 173 +++++++++++-------- |
60 | target/arm: Constify ID_PFR1 on user emulation | 68 | target/arm/tcg/m_helper.c | 90 +++++----- |
61 | target/arm: Convert CPUARMState::eabi to boolean | 69 | target/arm/tcg/pauth_helper.c | 26 ++- |
62 | target/arm: Avoid resetting CPUARMState::eabi field | 70 | gdb-xml/aarch64-pauth.xml | 15 ++ |
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | 71 | 19 files changed, 742 insertions(+), 258 deletions(-) |
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | 72 | create mode 100644 gdb-xml/aarch64-pauth.xml |
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | |||
70 | MAINTAINERS | 8 +- | ||
71 | docs/system/arm/nuvoton.rst | 2 +- | ||
72 | hw/arm/smmuv3-internal.h | 7 + | ||
73 | include/hw/arm/npcm7xx.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 2 - | ||
75 | include/hw/arm/smmuv3.h | 1 + | ||
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | ||
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | ||
78 | linux-user/user-internals.h | 2 +- | ||
79 | target/arm/cpregs.h | 98 ++++++++++++++ | ||
80 | target/arm/cpu.h | 228 ++------------------------------- | ||
81 | target/arm/internals.h | 14 -- | ||
82 | hw/arm/npcm7xx.c | 25 +++- | ||
83 | hw/arm/smmu-common.c | 4 +- | ||
84 | hw/arm/smmuv3.c | 43 ++++++- | ||
85 | hw/arm/virt.c | 10 +- | ||
86 | hw/intc/armv7m_nvic.c | 38 ++---- | ||
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | ||
88 | linux-user/arm/cpu_loop.c | 4 +- | ||
89 | target/arm/cpu.c | 5 +- | ||
90 | target/arm/cpu_tcg.c | 3 + | ||
91 | target/arm/helper.c | 31 +++-- | ||
92 | target/arm/m_helper.c | 86 +++++++------ | ||
93 | target/arm/machine.c | 18 +-- | ||
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | ||
95 | hw/arm/Kconfig | 1 + | ||
96 | hw/ssi/meson.build | 2 +- | ||
97 | hw/ssi/trace-events | 5 + | ||
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | ||
99 | tests/avocado/boot_linux.py | 48 ++----- | ||
100 | tests/avocado/boot_linux_console.py | 1 + | ||
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | ||
102 | tests/avocado/reverse_debugging.py | 8 ++ | ||
103 | tests/qtest/meson.build | 4 +- | ||
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | ||
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
106 | create mode 100644 hw/ssi/npcm_pspi.c | ||
107 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, | ||
4 | similarly to automatic conversion from commit 8063396bf3 | ||
5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/intc/armv7m_nvic.h | 5 +---- | ||
13 | 1 file changed, 1 insertion(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/intc/armv7m_nvic.h | ||
18 | +++ b/include/hw/intc/armv7m_nvic.h | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "qom/object.h" | ||
21 | |||
22 | #define TYPE_NVIC "armv7m_nvic" | ||
23 | - | ||
24 | -typedef struct NVICState NVICState; | ||
25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, | ||
26 | - TYPE_NVIC) | ||
27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) | ||
28 | |||
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
31 | -- | ||
32 | 2.34.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Make the form of the function names between fp and sve the same: |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. |
5 | Message-id: 20230206223502.25122-5-philmd@linaro.org | 5 | - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. |
6 | |||
7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230227213329.793795-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/helper.c | 12 ++++++++++-- | 13 | target/arm/internals.h | 8 ++++---- |
9 | 1 file changed, 10 insertions(+), 2 deletions(-) | 14 | target/arm/gdbstub.c | 9 +++++---- |
15 | target/arm/gdbstub64.c | 8 ++++---- | ||
16 | 3 files changed, 13 insertions(+), 12 deletions(-) | ||
10 | 17 | ||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/helper.c | 20 | --- a/target/arm/internals.h |
14 | +++ b/target/arm/helper.c | 21 | +++ b/target/arm/internals.h |
15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | 22 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) |
23 | } | ||
24 | |||
25 | #ifdef TARGET_AARCH64 | ||
26 | -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg); | ||
27 | -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg); | ||
28 | -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
29 | -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
30 | +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
31 | +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
32 | +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
33 | +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
34 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); | ||
35 | void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); | ||
36 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); | ||
37 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/gdbstub.c | ||
40 | +++ b/target/arm/gdbstub.c | ||
41 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
42 | */ | ||
43 | #ifdef TARGET_AARCH64 | ||
44 | if (isar_feature_aa64_sve(&cpu->isar)) { | ||
45 | - gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg, | ||
46 | - arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs), | ||
47 | + int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); | ||
48 | + gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, | ||
49 | + aarch64_gdb_set_sve_reg, nreg, | ||
50 | "sve-registers.xml", 0); | ||
51 | } else { | ||
52 | - gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, | ||
53 | - aarch64_fpu_gdb_set_reg, | ||
54 | + gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, | ||
55 | + aarch64_gdb_set_fpu_reg, | ||
56 | 34, "aarch64-fpu.xml", 0); | ||
57 | } | ||
58 | #endif | ||
59 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/target/arm/gdbstub64.c | ||
62 | +++ b/target/arm/gdbstub64.c | ||
63 | @@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) | ||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | -int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
68 | +int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
69 | { | ||
70 | switch (reg) { | ||
71 | case 0 ... 31: | ||
72 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
16 | } | 73 | } |
17 | } | 74 | } |
18 | 75 | ||
19 | +#ifndef CONFIG_USER_ONLY | 76 | -int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
20 | /* | 77 | +int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) |
21 | * We don't know until after realize whether there's a GICv3 | 78 | { |
22 | * attached, and that is what registers the gicv3 sysregs. | 79 | switch (reg) { |
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) | 80 | case 0 ... 31: |
24 | return pfr1; | 81 | @@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) |
82 | } | ||
25 | } | 83 | } |
26 | 84 | ||
27 | -#ifndef CONFIG_USER_ONLY | 85 | -int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) |
28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | 86 | +int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) |
29 | { | 87 | { |
30 | ARMCPU *cpu = env_archcpu(env); | 88 | ARMCPU *cpu = env_archcpu(env); |
31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 89 | |
32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, | 90 | @@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) |
33 | .access = PL1_R, .type = ARM_CP_NO_RAW, | 91 | return 0; |
34 | .accessfn = access_aa32_tid3, | 92 | } |
35 | +#ifdef CONFIG_USER_ONLY | 93 | |
36 | + .type = ARM_CP_CONST, | 94 | -int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg) |
37 | + .resetvalue = cpu->isar.id_pfr1, | 95 | +int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) |
38 | +#else | 96 | { |
39 | + .type = ARM_CP_NO_RAW, | 97 | ARMCPU *cpu = env_archcpu(env); |
40 | + .accessfn = access_aa32_tid3, | 98 | |
41 | .readfn = id_pfr1_read, | ||
42 | - .writefn = arm_cp_write_ignore }, | ||
43 | + .writefn = arm_cp_write_ignore | ||
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
49 | -- | 99 | -- |
50 | 2.34.1 | 100 | 2.34.1 |
51 | 101 | ||
52 | 102 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | There is no point in using a void pointer to access the NVIC. | 3 | This function is not used outside gdbstub.c. |
4 | Use the real type to avoid casting it while debugging. | ||
5 | 4 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 5 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20230206223502.25122-11-philmd@linaro.org | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20230227213329.793795-3-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- | 11 | target/arm/cpu.h | 1 - |
12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- | 12 | target/arm/gdbstub.c | 2 +- |
13 | target/arm/cpu.c | 1 + | 13 | 2 files changed, 1 insertion(+), 2 deletions(-) |
14 | target/arm/m_helper.c | 2 +- | ||
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | ||
16 | 14 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { | 19 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
22 | 20 | * Helpers to dynamically generates XML descriptions of the sysregs | |
23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | 21 | * and SVE registers. Returns the number of registers in each set. |
24 | |||
25 | +typedef struct NVICState NVICState; | ||
26 | + | ||
27 | typedef struct CPUArchState { | ||
28 | /* Regs for current mode. */ | ||
29 | uint32_t regs[16]; | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
31 | } sau; | ||
32 | |||
33 | #if !defined(CONFIG_USER_ONLY) | ||
34 | - void *nvic; | ||
35 | + NVICState *nvic; | ||
36 | const struct arm_boot_info *boot_info; | ||
37 | /* Store GICv3CPUState to access from this struct */ | ||
38 | void *gicv3state; | ||
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
40 | |||
41 | /* Interface between CPU and Interrupt controller. */ | ||
42 | #ifndef CONFIG_USER_ONLY | ||
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | ||
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
45 | #else | ||
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
48 | { | ||
49 | return true; | ||
50 | } | ||
51 | #endif | ||
52 | /** | ||
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | ||
54 | - * @opaque: the NVIC | ||
55 | + * @s: the NVIC | ||
56 | * @irq: the exception number to mark pending | ||
57 | * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | * version of a banked exception, true for the secure version of a banked | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
60 | * if @secure is true and @irq does not specify one of the fixed set | ||
61 | * of architecturally banked exceptions. | ||
62 | */ | 22 | */ |
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | 23 | -int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); |
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | 24 | int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); |
65 | /** | 25 | |
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | 26 | /* Returns the dynamically generated XML for the gdb stub. |
67 | - * @opaque: the NVIC | 27 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
68 | + * @s: the NVIC | ||
69 | * @irq: the exception number to mark pending | ||
70 | * @secure: false for non-banked exceptions or for the nonsecure | ||
71 | * version of a banked exception, true for the secure version of a banked | ||
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
73 | * exceptions (exceptions generated in the course of trying to take | ||
74 | * a different exception). | ||
75 | */ | ||
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
78 | /** | ||
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
80 | - * @opaque: the NVIC | ||
81 | + * @s: the NVIC | ||
82 | * @irq: the exception number to mark pending | ||
83 | * @secure: false for non-banked exceptions or for the nonsecure | ||
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
174 | --- a/hw/intc/armv7m_nvic.c | 29 | --- a/target/arm/gdbstub.c |
175 | +++ b/hw/intc/armv7m_nvic.c | 30 | +++ b/target/arm/gdbstub.c |
176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) | 31 | @@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, |
177 | return MIN(running, s->exception_prio); | ||
178 | } | ||
179 | |||
180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
182 | { | ||
183 | /* Return true if the requested execution priority is negative | ||
184 | * for the specified security state, ie that security state | ||
185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
186 | * mean we don't allow FAULTMASK_NS to actually make the execution | ||
187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). | ||
188 | */ | ||
189 | - NVICState *s = opaque; | ||
190 | - | ||
191 | if (s->cpu->env.v7m.faultmask[secure]) { | ||
192 | return true; | ||
193 | } | ||
194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
200 | { | ||
201 | - NVICState *s = opaque; | ||
202 | - | ||
203 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
204 | } | ||
205 | |||
206 | -int armv7m_nvic_raw_execution_priority(void *opaque) | ||
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | 32 | } |
227 | } | 33 | } |
228 | 34 | ||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | 35 | -int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) |
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | 36 | +static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) |
231 | { | 37 | { |
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | 38 | ARMCPU *cpu = ARM_CPU(cs); |
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | 39 | GString *s = g_string_new(NULL); |
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
308 | index XXXXXXX..XXXXXXX 100644 | ||
309 | --- a/target/arm/cpu.c | ||
310 | +++ b/target/arm/cpu.c | ||
311 | @@ -XXX,XX +XXX,XX @@ | ||
312 | #if !defined(CONFIG_USER_ONLY) | ||
313 | #include "hw/loader.h" | ||
314 | #include "hw/boards.h" | ||
315 | +#include "hw/intc/armv7m_nvic.h" | ||
316 | #endif | ||
317 | #include "sysemu/tcg.h" | ||
318 | #include "sysemu/qtest.h" | ||
319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/target/arm/m_helper.c | ||
322 | +++ b/target/arm/m_helper.c | ||
323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | ||
324 | * that we will need later in order to do lazy FP reg stacking. | ||
325 | */ | ||
326 | bool is_secure = env->v7m.secure; | ||
327 | - void *nvic = env->nvic; | ||
328 | + NVICState *nvic = env->nvic; | ||
329 | /* | ||
330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits | ||
331 | * are banked and we want to update the bit in the bank for the | ||
332 | -- | 40 | -- |
333 | 2.34.1 | 41 | 2.34.1 |
334 | 42 | ||
335 | 43 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Although the 'eabi' field is only used in user emulation where | 3 | The function is only used for aarch64, so move it to the |
4 | CPU reset doesn't occur, it doesn't belong to the area to reset. | 4 | file that has the other aarch64 gdbstub stuff. Move the |
5 | Move it after the 'end_reset_fields' for consistency. | 5 | declaration to internals.h. |
6 | 6 | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20230206223502.25122-7-philmd@linaro.org | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20230227213329.793795-4-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | target/arm/cpu.h | 9 ++++----- | 13 | target/arm/cpu.h | 6 --- |
13 | 1 file changed, 4 insertions(+), 5 deletions(-) | 14 | target/arm/internals.h | 1 + |
15 | target/arm/gdbstub.c | 120 ----------------------------------------- | ||
16 | target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++ | ||
17 | 4 files changed, 119 insertions(+), 126 deletions(-) | ||
14 | 18 | ||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 21 | --- a/target/arm/cpu.h |
18 | +++ b/target/arm/cpu.h | 22 | +++ b/target/arm/cpu.h |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 23 | @@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; | 24 | int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
21 | #endif | 25 | int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
22 | 26 | ||
23 | -#if defined(CONFIG_USER_ONLY) | 27 | -/* |
24 | - /* For usermode syscall translation. */ | 28 | - * Helpers to dynamically generates XML descriptions of the sysregs |
25 | - bool eabi; | 29 | - * and SVE registers. Returns the number of registers in each set. |
26 | -#endif | 30 | - */ |
27 | - | 31 | -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); |
28 | struct CPUBreakpoint *cpu_breakpoint[16]; | 32 | - |
29 | struct CPUWatchpoint *cpu_watchpoint[16]; | 33 | /* Returns the dynamically generated XML for the gdb stub. |
30 | 34 | * Returns a pointer to the XML contents for the specified XML file or NULL | |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 35 | * if the XML name doesn't match the predefined one. |
32 | const struct arm_boot_info *boot_info; | 36 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
33 | /* Store GICv3CPUState to access from this struct */ | 37 | index XXXXXXX..XXXXXXX 100644 |
34 | void *gicv3state; | 38 | --- a/target/arm/internals.h |
35 | +#if defined(CONFIG_USER_ONLY) | 39 | +++ b/target/arm/internals.h |
36 | + /* For usermode syscall translation. */ | 40 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env) |
37 | + bool eabi; | 41 | } |
38 | +#endif /* CONFIG_USER_ONLY */ | 42 | |
39 | 43 | #ifdef TARGET_AARCH64 | |
40 | #ifdef TARGET_TAGGED_ADDRESSES | 44 | +int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); |
41 | /* Linux syscall tagged address support */ | 45 | int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); |
46 | int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
47 | int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
48 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/gdbstub.c | ||
51 | +++ b/target/arm/gdbstub.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | ||
53 | return cpu->dyn_sysreg_xml.num; | ||
54 | } | ||
55 | |||
56 | -struct TypeSize { | ||
57 | - const char *gdb_type; | ||
58 | - int size; | ||
59 | - const char sz, suffix; | ||
60 | -}; | ||
61 | - | ||
62 | -static const struct TypeSize vec_lanes[] = { | ||
63 | - /* quads */ | ||
64 | - { "uint128", 128, 'q', 'u' }, | ||
65 | - { "int128", 128, 'q', 's' }, | ||
66 | - /* 64 bit */ | ||
67 | - { "ieee_double", 64, 'd', 'f' }, | ||
68 | - { "uint64", 64, 'd', 'u' }, | ||
69 | - { "int64", 64, 'd', 's' }, | ||
70 | - /* 32 bit */ | ||
71 | - { "ieee_single", 32, 's', 'f' }, | ||
72 | - { "uint32", 32, 's', 'u' }, | ||
73 | - { "int32", 32, 's', 's' }, | ||
74 | - /* 16 bit */ | ||
75 | - { "ieee_half", 16, 'h', 'f' }, | ||
76 | - { "uint16", 16, 'h', 'u' }, | ||
77 | - { "int16", 16, 'h', 's' }, | ||
78 | - /* bytes */ | ||
79 | - { "uint8", 8, 'b', 'u' }, | ||
80 | - { "int8", 8, 'b', 's' }, | ||
81 | -}; | ||
82 | - | ||
83 | - | ||
84 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
85 | -{ | ||
86 | - ARMCPU *cpu = ARM_CPU(cs); | ||
87 | - GString *s = g_string_new(NULL); | ||
88 | - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
89 | - g_autoptr(GString) ts = g_string_new(""); | ||
90 | - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | ||
91 | - info->num = 0; | ||
92 | - g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
93 | - g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
94 | - g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
95 | - | ||
96 | - /* First define types and totals in a whole VL */ | ||
97 | - for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
98 | - int count = reg_width / vec_lanes[i].size; | ||
99 | - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | ||
100 | - g_string_append_printf(s, | ||
101 | - "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | ||
102 | - ts->str, vec_lanes[i].gdb_type, count); | ||
103 | - } | ||
104 | - /* | ||
105 | - * Now define a union for each size group containing unsigned and | ||
106 | - * signed and potentially float versions of each size from 128 to | ||
107 | - * 8 bits. | ||
108 | - */ | ||
109 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
110 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
111 | - g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
112 | - for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
113 | - if (vec_lanes[j].size == bits) { | ||
114 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
115 | - vec_lanes[j].suffix, | ||
116 | - vec_lanes[j].sz, vec_lanes[j].suffix); | ||
117 | - } | ||
118 | - } | ||
119 | - g_string_append(s, "</union>"); | ||
120 | - } | ||
121 | - /* And now the final union of unions */ | ||
122 | - g_string_append(s, "<union id=\"svev\">"); | ||
123 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
124 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
125 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
126 | - suf[i], suf[i]); | ||
127 | - } | ||
128 | - g_string_append(s, "</union>"); | ||
129 | - | ||
130 | - /* Finally the sve prefix type */ | ||
131 | - g_string_append_printf(s, | ||
132 | - "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
133 | - reg_width / 8); | ||
134 | - | ||
135 | - /* Then define each register in parts for each vq */ | ||
136 | - for (i = 0; i < 32; i++) { | ||
137 | - g_string_append_printf(s, | ||
138 | - "<reg name=\"z%d\" bitsize=\"%d\"" | ||
139 | - " regnum=\"%d\" type=\"svev\"/>", | ||
140 | - i, reg_width, base_reg++); | ||
141 | - info->num++; | ||
142 | - } | ||
143 | - /* fpscr & status registers */ | ||
144 | - g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
145 | - " regnum=\"%d\" group=\"float\"" | ||
146 | - " type=\"int\"/>", base_reg++); | ||
147 | - g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
148 | - " regnum=\"%d\" group=\"float\"" | ||
149 | - " type=\"int\"/>", base_reg++); | ||
150 | - info->num += 2; | ||
151 | - | ||
152 | - for (i = 0; i < 16; i++) { | ||
153 | - g_string_append_printf(s, | ||
154 | - "<reg name=\"p%d\" bitsize=\"%d\"" | ||
155 | - " regnum=\"%d\" type=\"svep\"/>", | ||
156 | - i, cpu->sve_max_vq * 16, base_reg++); | ||
157 | - info->num++; | ||
158 | - } | ||
159 | - g_string_append_printf(s, | ||
160 | - "<reg name=\"ffr\" bitsize=\"%d\"" | ||
161 | - " regnum=\"%d\" group=\"vector\"" | ||
162 | - " type=\"svep\"/>", | ||
163 | - cpu->sve_max_vq * 16, base_reg++); | ||
164 | - g_string_append_printf(s, | ||
165 | - "<reg name=\"vg\" bitsize=\"64\"" | ||
166 | - " regnum=\"%d\" type=\"int\"/>", | ||
167 | - base_reg++); | ||
168 | - info->num += 2; | ||
169 | - g_string_append_printf(s, "</feature>"); | ||
170 | - cpu->dyn_svereg_xml.desc = g_string_free(s, false); | ||
171 | - | ||
172 | - return cpu->dyn_svereg_xml.num; | ||
173 | -} | ||
174 | - | ||
175 | - | ||
176 | const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
177 | { | ||
178 | ARMCPU *cpu = ARM_CPU(cs); | ||
179 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
180 | index XXXXXXX..XXXXXXX 100644 | ||
181 | --- a/target/arm/gdbstub64.c | ||
182 | +++ b/target/arm/gdbstub64.c | ||
183 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
184 | |||
185 | return 0; | ||
186 | } | ||
187 | + | ||
188 | +struct TypeSize { | ||
189 | + const char *gdb_type; | ||
190 | + short size; | ||
191 | + char sz, suffix; | ||
192 | +}; | ||
193 | + | ||
194 | +static const struct TypeSize vec_lanes[] = { | ||
195 | + /* quads */ | ||
196 | + { "uint128", 128, 'q', 'u' }, | ||
197 | + { "int128", 128, 'q', 's' }, | ||
198 | + /* 64 bit */ | ||
199 | + { "ieee_double", 64, 'd', 'f' }, | ||
200 | + { "uint64", 64, 'd', 'u' }, | ||
201 | + { "int64", 64, 'd', 's' }, | ||
202 | + /* 32 bit */ | ||
203 | + { "ieee_single", 32, 's', 'f' }, | ||
204 | + { "uint32", 32, 's', 'u' }, | ||
205 | + { "int32", 32, 's', 's' }, | ||
206 | + /* 16 bit */ | ||
207 | + { "ieee_half", 16, 'h', 'f' }, | ||
208 | + { "uint16", 16, 'h', 'u' }, | ||
209 | + { "int16", 16, 'h', 's' }, | ||
210 | + /* bytes */ | ||
211 | + { "uint8", 8, 'b', 'u' }, | ||
212 | + { "int8", 8, 'b', 's' }, | ||
213 | +}; | ||
214 | + | ||
215 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
216 | +{ | ||
217 | + ARMCPU *cpu = ARM_CPU(cs); | ||
218 | + GString *s = g_string_new(NULL); | ||
219 | + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
220 | + g_autoptr(GString) ts = g_string_new(""); | ||
221 | + int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | ||
222 | + info->num = 0; | ||
223 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
224 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
225 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
226 | + | ||
227 | + /* First define types and totals in a whole VL */ | ||
228 | + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
229 | + int count = reg_width / vec_lanes[i].size; | ||
230 | + g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | ||
231 | + g_string_append_printf(s, | ||
232 | + "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | ||
233 | + ts->str, vec_lanes[i].gdb_type, count); | ||
234 | + } | ||
235 | + /* | ||
236 | + * Now define a union for each size group containing unsigned and | ||
237 | + * signed and potentially float versions of each size from 128 to | ||
238 | + * 8 bits. | ||
239 | + */ | ||
240 | + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
241 | + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
242 | + g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
243 | + for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
244 | + if (vec_lanes[j].size == bits) { | ||
245 | + g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
246 | + vec_lanes[j].suffix, | ||
247 | + vec_lanes[j].sz, vec_lanes[j].suffix); | ||
248 | + } | ||
249 | + } | ||
250 | + g_string_append(s, "</union>"); | ||
251 | + } | ||
252 | + /* And now the final union of unions */ | ||
253 | + g_string_append(s, "<union id=\"svev\">"); | ||
254 | + for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
255 | + const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
256 | + g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
257 | + suf[i], suf[i]); | ||
258 | + } | ||
259 | + g_string_append(s, "</union>"); | ||
260 | + | ||
261 | + /* Finally the sve prefix type */ | ||
262 | + g_string_append_printf(s, | ||
263 | + "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
264 | + reg_width / 8); | ||
265 | + | ||
266 | + /* Then define each register in parts for each vq */ | ||
267 | + for (i = 0; i < 32; i++) { | ||
268 | + g_string_append_printf(s, | ||
269 | + "<reg name=\"z%d\" bitsize=\"%d\"" | ||
270 | + " regnum=\"%d\" type=\"svev\"/>", | ||
271 | + i, reg_width, base_reg++); | ||
272 | + info->num++; | ||
273 | + } | ||
274 | + /* fpscr & status registers */ | ||
275 | + g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
276 | + " regnum=\"%d\" group=\"float\"" | ||
277 | + " type=\"int\"/>", base_reg++); | ||
278 | + g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
279 | + " regnum=\"%d\" group=\"float\"" | ||
280 | + " type=\"int\"/>", base_reg++); | ||
281 | + info->num += 2; | ||
282 | + | ||
283 | + for (i = 0; i < 16; i++) { | ||
284 | + g_string_append_printf(s, | ||
285 | + "<reg name=\"p%d\" bitsize=\"%d\"" | ||
286 | + " regnum=\"%d\" type=\"svep\"/>", | ||
287 | + i, cpu->sve_max_vq * 16, base_reg++); | ||
288 | + info->num++; | ||
289 | + } | ||
290 | + g_string_append_printf(s, | ||
291 | + "<reg name=\"ffr\" bitsize=\"%d\"" | ||
292 | + " regnum=\"%d\" group=\"vector\"" | ||
293 | + " type=\"svep\"/>", | ||
294 | + cpu->sve_max_vq * 16, base_reg++); | ||
295 | + g_string_append_printf(s, | ||
296 | + "<reg name=\"vg\" bitsize=\"64\"" | ||
297 | + " regnum=\"%d\" type=\"int\"/>", | ||
298 | + base_reg++); | ||
299 | + info->num += 2; | ||
300 | + g_string_append_printf(s, "</feature>"); | ||
301 | + info->desc = g_string_free(s, false); | ||
302 | + | ||
303 | + return info->num; | ||
304 | +} | ||
42 | -- | 305 | -- |
43 | 2.34.1 | 306 | 2.34.1 |
44 | 307 | ||
45 | 308 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These tests set -accel tcg, so restrict them to when TCG is present. | 3 | Create a subroutine for creating the union of unions |
4 | of the various type sizes that a vector may contain. | ||
4 | 5 | ||
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 6 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230227213329.793795-5-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | tests/qtest/meson.build | 4 ++-- | 12 | target/arm/gdbstub64.c | 83 +++++++++++++++++++++++------------------- |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 13 | 1 file changed, 45 insertions(+), 38 deletions(-) |
12 | 14 | ||
13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | 15 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/tests/qtest/meson.build | 17 | --- a/target/arm/gdbstub64.c |
16 | +++ b/tests/qtest/meson.build | 18 | +++ b/target/arm/gdbstub64.c |
17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ | 19 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) |
18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | 20 | return 0; |
19 | qtests_aarch64 = \ | 21 | } |
20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ | 22 | |
21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ | 23 | -struct TypeSize { |
22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ | 24 | - const char *gdb_type; |
23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ | 25 | - short size; |
24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ | 26 | - char sz, suffix; |
25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ | 27 | -}; |
26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | 28 | - |
27 | ['arm-cpu-features', | 29 | -static const struct TypeSize vec_lanes[] = { |
30 | - /* quads */ | ||
31 | - { "uint128", 128, 'q', 'u' }, | ||
32 | - { "int128", 128, 'q', 's' }, | ||
33 | - /* 64 bit */ | ||
34 | - { "ieee_double", 64, 'd', 'f' }, | ||
35 | - { "uint64", 64, 'd', 'u' }, | ||
36 | - { "int64", 64, 'd', 's' }, | ||
37 | - /* 32 bit */ | ||
38 | - { "ieee_single", 32, 's', 'f' }, | ||
39 | - { "uint32", 32, 's', 'u' }, | ||
40 | - { "int32", 32, 's', 's' }, | ||
41 | - /* 16 bit */ | ||
42 | - { "ieee_half", 16, 'h', 'f' }, | ||
43 | - { "uint16", 16, 'h', 'u' }, | ||
44 | - { "int16", 16, 'h', 's' }, | ||
45 | - /* bytes */ | ||
46 | - { "uint8", 8, 'b', 'u' }, | ||
47 | - { "int8", 8, 'b', 's' }, | ||
48 | -}; | ||
49 | - | ||
50 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
51 | +static void output_vector_union_type(GString *s, int reg_width) | ||
52 | { | ||
53 | - ARMCPU *cpu = ARM_CPU(cs); | ||
54 | - GString *s = g_string_new(NULL); | ||
55 | - DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
56 | + struct TypeSize { | ||
57 | + const char *gdb_type; | ||
58 | + short size; | ||
59 | + char sz, suffix; | ||
60 | + }; | ||
61 | + | ||
62 | + static const struct TypeSize vec_lanes[] = { | ||
63 | + /* quads */ | ||
64 | + { "uint128", 128, 'q', 'u' }, | ||
65 | + { "int128", 128, 'q', 's' }, | ||
66 | + /* 64 bit */ | ||
67 | + { "ieee_double", 64, 'd', 'f' }, | ||
68 | + { "uint64", 64, 'd', 'u' }, | ||
69 | + { "int64", 64, 'd', 's' }, | ||
70 | + /* 32 bit */ | ||
71 | + { "ieee_single", 32, 's', 'f' }, | ||
72 | + { "uint32", 32, 's', 'u' }, | ||
73 | + { "int32", 32, 's', 's' }, | ||
74 | + /* 16 bit */ | ||
75 | + { "ieee_half", 16, 'h', 'f' }, | ||
76 | + { "uint16", 16, 'h', 'u' }, | ||
77 | + { "int16", 16, 'h', 's' }, | ||
78 | + /* bytes */ | ||
79 | + { "uint8", 8, 'b', 'u' }, | ||
80 | + { "int8", 8, 'b', 's' }, | ||
81 | + }; | ||
82 | + | ||
83 | + static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
84 | + | ||
85 | g_autoptr(GString) ts = g_string_new(""); | ||
86 | - int i, j, bits, reg_width = (cpu->sve_max_vq * 128); | ||
87 | - info->num = 0; | ||
88 | - g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
89 | - g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
90 | - g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
91 | + int i, j, bits; | ||
92 | |||
93 | /* First define types and totals in a whole VL */ | ||
94 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
95 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
96 | * 8 bits. | ||
97 | */ | ||
98 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
99 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
100 | g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
101 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
102 | if (vec_lanes[j].size == bits) { | ||
103 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
104 | /* And now the final union of unions */ | ||
105 | g_string_append(s, "<union id=\"svev\">"); | ||
106 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
107 | - const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
108 | g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
109 | suf[i], suf[i]); | ||
110 | } | ||
111 | g_string_append(s, "</union>"); | ||
112 | +} | ||
113 | + | ||
114 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
115 | +{ | ||
116 | + ARMCPU *cpu = ARM_CPU(cs); | ||
117 | + GString *s = g_string_new(NULL); | ||
118 | + DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; | ||
119 | + int i, reg_width = (cpu->sve_max_vq * 128); | ||
120 | + info->num = 0; | ||
121 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
122 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
123 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
124 | + | ||
125 | + output_vector_union_type(s, reg_width); | ||
126 | |||
127 | /* Finally the sve prefix type */ | ||
128 | g_string_append_printf(s, | ||
28 | -- | 129 | -- |
29 | 2.34.1 | 130 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Claudio Fontana <cfontana@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | make it clearer from the name that this is a tcg-only function. | 3 | Rather than increment base_reg and num, compute num from the change |
4 | to base_reg at the end. Clean up some nearby comments. | ||
4 | 5 | ||
5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20230227213329.793795-6-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/helper.c | 4 ++-- | 11 | target/arm/gdbstub64.c | 27 ++++++++++++++++----------- |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 16 insertions(+), 11 deletions(-) |
14 | 13 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 16 | --- a/target/arm/gdbstub64.c |
18 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/gdbstub64.c |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 18 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width) |
20 | * trapped to the hypervisor in KVM. | 19 | g_string_append(s, "</union>"); |
21 | */ | 20 | } |
22 | #ifdef CONFIG_TCG | 21 | |
23 | -static void handle_semihosting(CPUState *cs) | 22 | -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) |
24 | +static void tcg_handle_semihosting(CPUState *cs) | 23 | +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) |
25 | { | 24 | { |
26 | ARMCPU *cpu = ARM_CPU(cs); | 25 | ARMCPU *cpu = ARM_CPU(cs); |
27 | CPUARMState *env = &cpu->env; | 26 | GString *s = g_string_new(NULL); |
28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | 27 | DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; |
29 | */ | 28 | - int i, reg_width = (cpu->sve_max_vq * 128); |
30 | #ifdef CONFIG_TCG | 29 | - info->num = 0; |
31 | if (cs->exception_index == EXCP_SEMIHOST) { | 30 | + int reg_width = cpu->sve_max_vq * 128; |
32 | - handle_semihosting(cs); | 31 | + int base_reg = orig_base_reg; |
33 | + tcg_handle_semihosting(cs); | 32 | + int i; |
34 | return; | 33 | + |
34 | g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
35 | g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
36 | g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); | ||
37 | |||
38 | + /* Create the vector union type. */ | ||
39 | output_vector_union_type(s, reg_width); | ||
40 | |||
41 | - /* Finally the sve prefix type */ | ||
42 | + /* Create the predicate vector type. */ | ||
43 | g_string_append_printf(s, | ||
44 | "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", | ||
45 | reg_width / 8); | ||
46 | |||
47 | - /* Then define each register in parts for each vq */ | ||
48 | + /* Define the vector registers. */ | ||
49 | for (i = 0; i < 32; i++) { | ||
50 | g_string_append_printf(s, | ||
51 | "<reg name=\"z%d\" bitsize=\"%d\"" | ||
52 | " regnum=\"%d\" type=\"svev\"/>", | ||
53 | i, reg_width, base_reg++); | ||
54 | - info->num++; | ||
35 | } | 55 | } |
36 | #endif | 56 | + |
57 | /* fpscr & status registers */ | ||
58 | g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" | ||
59 | " regnum=\"%d\" group=\"float\"" | ||
60 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) | ||
61 | g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" | ||
62 | " regnum=\"%d\" group=\"float\"" | ||
63 | " type=\"int\"/>", base_reg++); | ||
64 | - info->num += 2; | ||
65 | |||
66 | + /* Define the predicate registers. */ | ||
67 | for (i = 0; i < 16; i++) { | ||
68 | g_string_append_printf(s, | ||
69 | "<reg name=\"p%d\" bitsize=\"%d\"" | ||
70 | " regnum=\"%d\" type=\"svep\"/>", | ||
71 | i, cpu->sve_max_vq * 16, base_reg++); | ||
72 | - info->num++; | ||
73 | } | ||
74 | g_string_append_printf(s, | ||
75 | "<reg name=\"ffr\" bitsize=\"%d\"" | ||
76 | " regnum=\"%d\" group=\"vector\"" | ||
77 | " type=\"svep\"/>", | ||
78 | cpu->sve_max_vq * 16, base_reg++); | ||
79 | + | ||
80 | + /* Define the vector length pseudo-register. */ | ||
81 | g_string_append_printf(s, | ||
82 | "<reg name=\"vg\" bitsize=\"64\"" | ||
83 | " regnum=\"%d\" type=\"int\"/>", | ||
84 | base_reg++); | ||
85 | - info->num += 2; | ||
86 | - g_string_append_printf(s, "</feature>"); | ||
87 | - info->desc = g_string_free(s, false); | ||
88 | |||
89 | + g_string_append_printf(s, "</feature>"); | ||
90 | + | ||
91 | + info->desc = g_string_free(s, false); | ||
92 | + info->num = base_reg - orig_base_reg; | ||
93 | return info->num; | ||
94 | } | ||
37 | -- | 95 | -- |
38 | 2.34.1 | 96 | 2.34.1 |
39 | 97 | ||
40 | 98 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This allows the test to be skipped when TCG is not present in the QEMU | 3 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
4 | binary. | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 6 | Message-id: 20230227213329.793795-7-richard.henderson@linaro.org |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 8 | --- |
11 | tests/avocado/boot_linux_console.py | 1 + | 9 | target/arm/gdbstub64.c | 5 +++-- |
12 | tests/avocado/reverse_debugging.py | 8 ++++++++ | 10 | 1 file changed, 3 insertions(+), 2 deletions(-) |
13 | 2 files changed, 9 insertions(+) | ||
14 | 11 | ||
15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py | 12 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/tests/avocado/boot_linux_console.py | 14 | --- a/target/arm/gdbstub64.c |
18 | +++ b/tests/avocado/boot_linux_console.py | 15 | +++ b/target/arm/gdbstub64.c |
19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): | 16 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) |
20 | 17 | GString *s = g_string_new(NULL); | |
21 | def test_aarch64_raspi3_atf(self): | 18 | DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; |
22 | """ | 19 | int reg_width = cpu->sve_max_vq * 128; |
23 | + :avocado: tags=accel:tcg | 20 | + int pred_width = cpu->sve_max_vq * 16; |
24 | :avocado: tags=arch:aarch64 | 21 | int base_reg = orig_base_reg; |
25 | :avocado: tags=machine:raspi3b | 22 | int i; |
26 | :avocado: tags=cpu:cortex-a53 | 23 | |
27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py | 24 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) |
28 | index XXXXXXX..XXXXXXX 100644 | 25 | g_string_append_printf(s, |
29 | --- a/tests/avocado/reverse_debugging.py | 26 | "<reg name=\"p%d\" bitsize=\"%d\"" |
30 | +++ b/tests/avocado/reverse_debugging.py | 27 | " regnum=\"%d\" type=\"svep\"/>", |
31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): | 28 | - i, cpu->sve_max_vq * 16, base_reg++); |
32 | vm.shutdown() | 29 | + i, pred_width, base_reg++); |
33 | 30 | } | |
34 | class ReverseDebugging_X86_64(ReverseDebugging): | 31 | g_string_append_printf(s, |
35 | + """ | 32 | "<reg name=\"ffr\" bitsize=\"%d\"" |
36 | + :avocado: tags=accel:tcg | 33 | " regnum=\"%d\" group=\"vector\"" |
37 | + """ | 34 | " type=\"svep\"/>", |
38 | + | 35 | - cpu->sve_max_vq * 16, base_reg++); |
39 | REG_PC = 0x10 | 36 | + pred_width, base_reg++); |
40 | REG_CS = 0x12 | 37 | |
41 | def get_pc(self, g): | 38 | /* Define the vector length pseudo-register. */ |
42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): | 39 | g_string_append_printf(s, |
43 | self.reverse_debugging() | ||
44 | |||
45 | class ReverseDebugging_AArch64(ReverseDebugging): | ||
46 | + """ | ||
47 | + :avocado: tags=accel:tcg | ||
48 | + """ | ||
49 | + | ||
50 | REG_PC = 32 | ||
51 | |||
52 | # unidentified gitlab timeout problem | ||
53 | -- | 40 | -- |
54 | 2.34.1 | 41 | 2.34.1 |
55 | 42 | ||
56 | 43 | diff view generated by jsdifflib |
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | 3 | Define svep based on the size of the predicates, |
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | 4 | not the primary vector registers. |
5 | the TTB1 check. | ||
6 | 5 | ||
7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20230227213329.793795-8-richard.henderson@linaro.org |
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | hw/arm/smmu-common.c | 2 +- | 11 | target/arm/gdbstub64.c | 2 +- |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
16 | 13 | ||
17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | 14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/smmu-common.c | 16 | --- a/target/arm/gdbstub64.c |
20 | +++ b/hw/arm/smmu-common.c | 17 | +++ b/target/arm/gdbstub64.c |
21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | 18 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) |
22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | 19 | /* Create the predicate vector type. */ |
23 | return &cfg->tt[0]; | 20 | g_string_append_printf(s, |
24 | } else if (cfg->tt[1].tsz && | 21 | "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", |
25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { | 22 | - reg_width / 8); |
26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { | 23 | + pred_width / 8); |
27 | /* there is a ttbr1 region and we are in it (high bits all one) */ | 24 | |
28 | return &cfg->tt[1]; | 25 | /* Define the vector registers. */ |
29 | } else if (!cfg->tt[0].tsz) { | 26 | for (i = 0; i < 32; i++) { |
30 | -- | 27 | -- |
31 | 2.34.1 | 28 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | 3 | This will make the function usable between SVE and SME. |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Message-id: 20230206223502.25122-3-philmd@linaro.org | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230227213329.793795-9-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 10 | --- |
9 | target/arm/m_helper.c | 11 ++++++++--- | 11 | target/arm/gdbstub64.c | 28 ++++++++++++++-------------- |
10 | 1 file changed, 8 insertions(+), 3 deletions(-) | 12 | 1 file changed, 14 insertions(+), 14 deletions(-) |
11 | 13 | ||
12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 14 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/m_helper.c | 16 | --- a/target/arm/gdbstub64.c |
15 | +++ b/target/arm/m_helper.c | 17 | +++ b/target/arm/gdbstub64.c |
16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 18 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) |
17 | return 0; | 19 | return 0; |
18 | } | 20 | } |
19 | 21 | ||
20 | -#else | 22 | -static void output_vector_union_type(GString *s, int reg_width) |
21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 23 | +static void output_vector_union_type(GString *s, int reg_width, |
22 | +{ | 24 | + const char *name) |
23 | + return ARMMMUIdx_MUser; | 25 | { |
24 | +} | 26 | struct TypeSize { |
27 | const char *gdb_type; | ||
28 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width) | ||
29 | }; | ||
30 | |||
31 | static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; | ||
32 | - | ||
33 | - g_autoptr(GString) ts = g_string_new(""); | ||
34 | int i, j, bits; | ||
35 | |||
36 | /* First define types and totals in a whole VL */ | ||
37 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { | ||
38 | - int count = reg_width / vec_lanes[i].size; | ||
39 | - g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix); | ||
40 | g_string_append_printf(s, | ||
41 | - "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>", | ||
42 | - ts->str, vec_lanes[i].gdb_type, count); | ||
43 | + "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>", | ||
44 | + name, vec_lanes[i].sz, vec_lanes[i].suffix, | ||
45 | + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); | ||
46 | } | ||
25 | + | 47 | + |
26 | +#else /* !CONFIG_USER_ONLY */ | 48 | /* |
27 | 49 | * Now define a union for each size group containing unsigned and | |
28 | /* | 50 | * signed and potentially float versions of each size from 128 to |
29 | * What kind of stack write are we doing? This affects how exceptions | 51 | * 8 bits. |
30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 52 | */ |
31 | return tt_resp; | 53 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { |
54 | - g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]); | ||
55 | + g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]); | ||
56 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { | ||
57 | if (vec_lanes[j].size == bits) { | ||
58 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>", | ||
59 | - vec_lanes[j].suffix, | ||
60 | + g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>", | ||
61 | + vec_lanes[j].suffix, name, | ||
62 | vec_lanes[j].sz, vec_lanes[j].suffix); | ||
63 | } | ||
64 | } | ||
65 | g_string_append(s, "</union>"); | ||
66 | } | ||
67 | + | ||
68 | /* And now the final union of unions */ | ||
69 | - g_string_append(s, "<union id=\"svev\">"); | ||
70 | + g_string_append_printf(s, "<union id=\"%s\">", name); | ||
71 | for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { | ||
72 | - g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>", | ||
73 | - suf[i], suf[i]); | ||
74 | + g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>", | ||
75 | + suf[i], name, suf[i]); | ||
76 | } | ||
77 | g_string_append(s, "</union>"); | ||
32 | } | 78 | } |
33 | 79 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) | |
34 | -#endif /* !CONFIG_USER_ONLY */ | 80 | g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); |
35 | - | 81 | |
36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 82 | /* Create the vector union type. */ |
37 | bool secstate, bool priv, bool negpri) | 83 | - output_vector_union_type(s, reg_width); |
38 | { | 84 | + output_vector_union_type(s, reg_width, "svev"); |
39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 85 | |
40 | 86 | /* Create the predicate vector type. */ | |
41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | 87 | g_string_append_printf(s, |
42 | } | ||
43 | + | ||
44 | +#endif /* !CONFIG_USER_ONLY */ | ||
45 | -- | 88 | -- |
46 | 2.34.1 | 89 | 2.34.1 |
47 | 90 | ||
48 | 91 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 3 | Order suf[] by the log8 of the width. |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Use ARRAY_SIZE instead of hard-coding 128. |
5 | Acked-by: Thomas Huth <thuth@redhat.com> | 5 | |
6 | This changes the order of the union definitions, | ||
7 | but retains the order of the union-of-union members. | ||
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20230227213329.793795-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- | 14 | target/arm/gdbstub64.c | 10 ++++++---- |
9 | 1 file changed, 18 insertions(+), 10 deletions(-) | 15 | 1 file changed, 6 insertions(+), 4 deletions(-) |
10 | 16 | ||
11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | 17 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/tests/qtest/arm-cpu-features.c | 19 | --- a/target/arm/gdbstub64.c |
14 | +++ b/tests/qtest/arm-cpu-features.c | 20 | +++ b/target/arm/gdbstub64.c |
15 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, |
16 | #define SVE_MAX_VQ 16 | 22 | { "int8", 8, 'b', 's' }, |
17 | 23 | }; | |
18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " | 24 | |
19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " | 25 | - static const char suf[] = { 'q', 'd', 's', 'h', 'b' }; |
20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " | 26 | - int i, j, bits; |
21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ | 27 | + static const char suf[] = { 'b', 'h', 's', 'd', 'q' }; |
22 | " 'arguments': { 'type': 'full', " | 28 | + int i, j; |
23 | #define QUERY_TAIL "}}" | 29 | |
24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | 30 | /* First define types and totals in a whole VL */ |
25 | { | 31 | for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { |
26 | g_test_init(&argc, &argv, NULL); | 32 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, |
27 | 33 | * signed and potentially float versions of each size from 128 to | |
28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", | 34 | * 8 bits. |
29 | - NULL, test_query_cpu_model_expansion); | 35 | */ |
30 | + if (qtest_has_accel("tcg")) { | 36 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { |
31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", | 37 | + for (i = 0; i < ARRAY_SIZE(suf); i++) { |
32 | + NULL, test_query_cpu_model_expansion); | 38 | + int bits = 8 << i; |
33 | + } | ||
34 | + | 39 | + |
35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { | 40 | g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]); |
36 | + goto out; | 41 | for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) { |
37 | + } | 42 | if (vec_lanes[j].size == bits) { |
38 | 43 | @@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width, | |
39 | /* | 44 | |
40 | * For now we only run KVM specific tests with AArch64 QEMU in | 45 | /* And now the final union of unions */ |
41 | * order avoid attempting to run an AArch32 QEMU with KVM on | 46 | g_string_append_printf(s, "<union id=\"%s\">", name); |
42 | * AArch64 hosts. That won't work and isn't easy to detect. | 47 | - for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) { |
43 | */ | 48 | + for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) { |
44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { | 49 | g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>", |
45 | + if (qtest_has_accel("kvm")) { | 50 | suf[i], name, suf[i]); |
46 | /* | ||
47 | * This tests target the 'host' CPU type, so register it only if | ||
48 | * KVM is available. | ||
49 | */ | ||
50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", | ||
51 | NULL, test_query_cpu_model_expansion_kvm); | ||
52 | - } | ||
53 | |||
54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { | ||
55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
56 | - NULL, sve_tests_sve_max_vq_8); | ||
57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
58 | - NULL, sve_tests_sve_off); | ||
59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", | ||
60 | NULL, sve_tests_sve_off_kvm); | ||
61 | } | 51 | } |
62 | |||
63 | + if (qtest_has_accel("tcg")) { | ||
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
69 | + | ||
70 | +out: | ||
71 | return g_test_run(); | ||
72 | } | ||
73 | -- | 52 | -- |
74 | 2.34.1 | 53 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() | 3 | Keep the logic for pauth within pauth_helper.c, and expose |
4 | are only used for system emulation in m_helper.c. | 4 | a helper function for use with the gdbstub pac extension. |
5 | Move the definitions to avoid prototype forward declarations. | ||
6 | 5 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230206223502.25122-4-philmd@linaro.org | 8 | Message-id: 20230227213329.793795-11-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/internals.h | 14 -------- | 11 | target/arm/internals.h | 10 ++++++++++ |
13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- | 12 | target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++---- |
14 | 2 files changed, 37 insertions(+), 51 deletions(-) | 13 | 2 files changed, 32 insertions(+), 4 deletions(-) |
15 | 14 | ||
16 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 15 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/internals.h | 17 | --- a/target/arm/internals.h |
19 | +++ b/target/arm/internals.h | 18 | +++ b/target/arm/internals.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) | 19 | @@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env); |
21 | 20 | bool arm_singlestep_active(CPUARMState *env); | |
22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); | 21 | bool arm_generate_debug_exceptions(CPUARMState *env); |
23 | 22 | ||
24 | -/* | 23 | +/** |
25 | - * Return the MMU index for a v7M CPU with all relevant information | 24 | + * pauth_ptr_mask: |
26 | - * manually specified. | 25 | + * @env: cpu context |
27 | - */ | 26 | + * @ptr: selects between TTBR0 and TTBR1 |
28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 27 | + * @data: selects between TBI and TBID |
29 | - bool secstate, bool priv, bool negpri); | 28 | + * |
30 | - | 29 | + * Return a mask of the bits of @ptr that contain the authentication code. |
31 | -/* | 30 | + */ |
32 | - * Return the MMU index for a v7M CPU in the specified security and | 31 | +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); |
33 | - * privilege state. | 32 | + |
34 | - */ | 33 | /* Add the cpreg definitions for debug related system registers */ |
35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 34 | void define_debug_regs(ARMCPU *cpu); |
36 | - bool secstate, bool priv); | 35 | |
37 | - | 36 | diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c |
38 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | ||
40 | |||
41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/target/arm/m_helper.c | 38 | --- a/target/arm/tcg/pauth_helper.c |
44 | +++ b/target/arm/m_helper.c | 39 | +++ b/target/arm/tcg/pauth_helper.c |
45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 40 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, |
46 | 41 | return pac | ext | ptr; | |
47 | #else /* !CONFIG_USER_ONLY */ | 42 | } |
48 | 43 | ||
49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 44 | -static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) |
50 | + bool secstate, bool priv, bool negpri) | 45 | +static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) |
51 | +{ | 46 | { |
52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | 47 | - /* Note that bit 55 is used whether or not the regime has 2 ranges. */ |
53 | + | 48 | - uint64_t extfield = sextract64(ptr, 55, 1); |
54 | + if (priv) { | 49 | int bot_pac_bit = 64 - param.tsz; |
55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; | 50 | int top_pac_bit = 64 - 8 * param.tbi; |
56 | + } | 51 | |
57 | + | 52 | - return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield); |
58 | + if (negpri) { | 53 | + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); |
59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
60 | + } | ||
61 | + | ||
62 | + if (secstate) { | ||
63 | + mmu_idx |= ARM_MMU_IDX_M_S; | ||
64 | + } | ||
65 | + | ||
66 | + return mmu_idx; | ||
67 | +} | 54 | +} |
68 | + | 55 | + |
69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 56 | +static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) |
70 | + bool secstate, bool priv) | ||
71 | +{ | 57 | +{ |
72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | 58 | + uint64_t mask = pauth_ptr_mask_internal(param); |
73 | + | 59 | + |
74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | 60 | + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ |
61 | + if (extract64(ptr, 55, 1)) { | ||
62 | + return ptr | mask; | ||
63 | + } else { | ||
64 | + return ptr & ~mask; | ||
65 | + } | ||
75 | +} | 66 | +} |
76 | + | 67 | + |
77 | +/* Return the MMU index for a v7M CPU in the specified security state */ | 68 | +uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) |
78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
79 | +{ | 69 | +{ |
80 | + bool priv = arm_v7m_is_handler_mode(env) || | 70 | + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); |
81 | + !(env->v7m.control[secstate] & 1); | 71 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); |
82 | + | 72 | + |
83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | 73 | + return pauth_ptr_mask_internal(param); |
84 | +} | ||
85 | + | ||
86 | /* | ||
87 | * What kind of stack write are we doing? This affects how exceptions | ||
88 | * generated during the stacking are treated. | ||
89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
90 | return tt_resp; | ||
91 | } | 74 | } |
92 | 75 | ||
93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 76 | static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, |
94 | - bool secstate, bool priv, bool negpri) | ||
95 | -{ | ||
96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | ||
97 | - | ||
98 | - if (priv) { | ||
99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; | ||
100 | - } | ||
101 | - | ||
102 | - if (negpri) { | ||
103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
104 | - } | ||
105 | - | ||
106 | - if (secstate) { | ||
107 | - mmu_idx |= ARM_MMU_IDX_M_S; | ||
108 | - } | ||
109 | - | ||
110 | - return mmu_idx; | ||
111 | -} | ||
112 | - | ||
113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
114 | - bool secstate, bool priv) | ||
115 | -{ | ||
116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | ||
117 | - | ||
118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | ||
119 | -} | ||
120 | - | ||
121 | -/* Return the MMU index for a v7M CPU in the specified security state */ | ||
122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
123 | -{ | ||
124 | - bool priv = arm_v7m_is_handler_mode(env) || | ||
125 | - !(env->v7m.control[secstate] & 1); | ||
126 | - | ||
127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | ||
128 | -} | ||
129 | - | ||
130 | #endif /* !CONFIG_USER_ONLY */ | ||
131 | -- | 77 | -- |
132 | 2.34.1 | 78 | 2.34.1 |
133 | |||
134 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20230206223502.25122-6-philmd@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | linux-user/user-internals.h | 2 +- | ||
10 | target/arm/cpu.h | 2 +- | ||
11 | linux-user/arm/cpu_loop.c | 4 ++-- | ||
12 | 3 files changed, 4 insertions(+), 4 deletions(-) | ||
13 | |||
14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/linux-user/user-internals.h | ||
17 | +++ b/linux-user/user-internals.h | ||
18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); | ||
19 | #ifdef TARGET_ARM | ||
20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) | ||
21 | { | ||
22 | - return cpu_env->eabi == 1; | ||
23 | + return cpu_env->eabi; | ||
24 | } | ||
25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) | ||
26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } | ||
27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/cpu.h | ||
30 | +++ b/target/arm/cpu.h | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
32 | |||
33 | #if defined(CONFIG_USER_ONLY) | ||
34 | /* For usermode syscall translation. */ | ||
35 | - int eabi; | ||
36 | + bool eabi; | ||
37 | #endif | ||
38 | |||
39 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/linux-user/arm/cpu_loop.c | ||
43 | +++ b/linux-user/arm/cpu_loop.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
45 | break; | ||
46 | case EXCP_SWI: | ||
47 | { | ||
48 | - env->eabi = 1; | ||
49 | + env->eabi = true; | ||
50 | /* system call */ | ||
51 | if (env->thumb) { | ||
52 | /* Thumb is always EABI style with syscall number in r7 */ | ||
53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) | ||
54 | * > 0xfffff and are handled below as out-of-range. | ||
55 | */ | ||
56 | n ^= ARM_SYSCALL_BASE; | ||
57 | - env->eabi = 0; | ||
58 | + env->eabi = false; | ||
59 | } | ||
60 | } | ||
61 | |||
62 | -- | ||
63 | 2.34.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Nuvoton's PSPI is a general purpose SPI module which enables | 3 | The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK |
4 | connections to SPI-based peripheral devices. | 4 | ptrace register set. |
5 | 5 | ||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 6 | The original gdb feature consists of two masks, data and code, which are |
7 | Reviewed-by: Chris Rauer <crauer@google.com> | 7 | used to mask out the authentication code within a pointer. Following |
8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | 8 | discussion with Luis Machado, add two more masks in order to support |
9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com | 9 | pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). |
10 | |||
11 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20230227213329.793795-12-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 16 | --- |
12 | MAINTAINERS | 6 +- | 17 | configs/targets/aarch64-linux-user.mak | 2 +- |
13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ | 18 | configs/targets/aarch64-softmmu.mak | 2 +- |
14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ | 19 | configs/targets/aarch64_be-linux-user.mak | 2 +- |
15 | hw/ssi/meson.build | 2 +- | 20 | target/arm/internals.h | 2 ++ |
16 | hw/ssi/trace-events | 5 + | 21 | target/arm/gdbstub.c | 5 ++++ |
17 | 5 files changed, 283 insertions(+), 4 deletions(-) | 22 | target/arm/gdbstub64.c | 34 +++++++++++++++++++++++ |
18 | create mode 100644 include/hw/ssi/npcm_pspi.h | 23 | gdb-xml/aarch64-pauth.xml | 15 ++++++++++ |
19 | create mode 100644 hw/ssi/npcm_pspi.c | 24 | 7 files changed, 59 insertions(+), 3 deletions(-) |
25 | create mode 100644 gdb-xml/aarch64-pauth.xml | ||
20 | 26 | ||
21 | diff --git a/MAINTAINERS b/MAINTAINERS | 27 | diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak |
22 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/MAINTAINERS | 29 | --- a/configs/targets/aarch64-linux-user.mak |
24 | +++ b/MAINTAINERS | 30 | +++ b/configs/targets/aarch64-linux-user.mak |
25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> | 31 | @@ -XXX,XX +XXX,XX @@ |
26 | M: Hao Wu <wuhaotsh@google.com> | 32 | TARGET_ARCH=aarch64 |
27 | L: qemu-arm@nongnu.org | 33 | TARGET_BASE_ARCH=arm |
28 | S: Supported | 34 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml |
29 | -F: hw/*/npcm7xx* | 35 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml |
30 | -F: include/hw/*/npcm7xx* | 36 | TARGET_HAS_BFLT=y |
31 | -F: tests/qtest/npcm7xx* | 37 | CONFIG_SEMIHOSTING=y |
32 | +F: hw/*/npcm* | 38 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y |
33 | +F: include/hw/*/npcm* | 39 | diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak |
34 | +F: tests/qtest/npcm* | 40 | index XXXXXXX..XXXXXXX 100644 |
35 | F: pc-bios/npcm7xx_bootrom.bin | 41 | --- a/configs/targets/aarch64-softmmu.mak |
36 | F: roms/vbootrom | 42 | +++ b/configs/targets/aarch64-softmmu.mak |
37 | F: docs/system/arm/nuvoton.rst | 43 | @@ -XXX,XX +XXX,XX @@ |
38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h | 44 | TARGET_ARCH=aarch64 |
45 | TARGET_BASE_ARCH=arm | ||
46 | TARGET_SUPPORTS_MTTCG=y | ||
47 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml | ||
48 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml | ||
49 | TARGET_NEED_FDT=y | ||
50 | diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/configs/targets/aarch64_be-linux-user.mak | ||
53 | +++ b/configs/targets/aarch64_be-linux-user.mak | ||
54 | @@ -XXX,XX +XXX,XX @@ | ||
55 | TARGET_ARCH=aarch64 | ||
56 | TARGET_BASE_ARCH=arm | ||
57 | TARGET_BIG_ENDIAN=y | ||
58 | -TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml | ||
59 | +TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml | ||
60 | TARGET_HAS_BFLT=y | ||
61 | CONFIG_SEMIHOSTING=y | ||
62 | CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y | ||
63 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/internals.h | ||
66 | +++ b/target/arm/internals.h | ||
67 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
68 | int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
69 | int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
70 | int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
71 | +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); | ||
72 | +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); | ||
73 | void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); | ||
74 | void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); | ||
75 | void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); | ||
76 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/gdbstub.c | ||
79 | +++ b/target/arm/gdbstub.c | ||
80 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
81 | aarch64_gdb_set_fpu_reg, | ||
82 | 34, "aarch64-fpu.xml", 0); | ||
83 | } | ||
84 | + if (isar_feature_aa64_pauth(&cpu->isar)) { | ||
85 | + gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, | ||
86 | + aarch64_gdb_set_pauth_reg, | ||
87 | + 4, "aarch64-pauth.xml", 0); | ||
88 | + } | ||
89 | #endif | ||
90 | } else { | ||
91 | if (arm_feature(env, ARM_FEATURE_NEON)) { | ||
92 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/gdbstub64.c | ||
95 | +++ b/target/arm/gdbstub64.c | ||
96 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | +int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
101 | +{ | ||
102 | + switch (reg) { | ||
103 | + case 0: /* pauth_dmask */ | ||
104 | + case 1: /* pauth_cmask */ | ||
105 | + case 2: /* pauth_dmask_high */ | ||
106 | + case 3: /* pauth_cmask_high */ | ||
107 | + /* | ||
108 | + * Note that older versions of this feature only contained | ||
109 | + * pauth_{d,c}mask, for use with Linux user processes, and | ||
110 | + * thus exclusively in the low half of the address space. | ||
111 | + * | ||
112 | + * To support system mode, and to debug kernels, two new regs | ||
113 | + * were added to cover the high half of the address space. | ||
114 | + * For the purpose of pauth_ptr_mask, we can use any well-formed | ||
115 | + * address within the address space half -- here, 0 and -1. | ||
116 | + */ | ||
117 | + { | ||
118 | + bool is_data = !(reg & 1); | ||
119 | + bool is_high = reg & 2; | ||
120 | + uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); | ||
121 | + return gdb_get_reg64(buf, mask); | ||
122 | + } | ||
123 | + default: | ||
124 | + return 0; | ||
125 | + } | ||
126 | +} | ||
127 | + | ||
128 | +int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) | ||
129 | +{ | ||
130 | + /* All pseudo registers are read-only. */ | ||
131 | + return 0; | ||
132 | +} | ||
133 | + | ||
134 | static void output_vector_union_type(GString *s, int reg_width, | ||
135 | const char *name) | ||
136 | { | ||
137 | diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml | ||
39 | new file mode 100644 | 138 | new file mode 100644 |
40 | index XXXXXXX..XXXXXXX | 139 | index XXXXXXX..XXXXXXX |
41 | --- /dev/null | 140 | --- /dev/null |
42 | +++ b/include/hw/ssi/npcm_pspi.h | 141 | +++ b/gdb-xml/aarch64-pauth.xml |
43 | @@ -XXX,XX +XXX,XX @@ | 142 | @@ -XXX,XX +XXX,XX @@ |
44 | +/* | 143 | +<?xml version="1.0"?> |
45 | + * Nuvoton Peripheral SPI Module | 144 | +<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc. |
46 | + * | ||
47 | + * Copyright 2023 Google LLC | ||
48 | + * | ||
49 | + * This program is free software; you can redistribute it and/or modify it | ||
50 | + * under the terms of the GNU General Public License as published by the | ||
51 | + * Free Software Foundation; either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
57 | + * for more details. | ||
58 | + */ | ||
59 | +#ifndef NPCM_PSPI_H | ||
60 | +#define NPCM_PSPI_H | ||
61 | + | 145 | + |
62 | +#include "hw/ssi/ssi.h" | 146 | + Copying and distribution of this file, with or without modification, |
63 | +#include "hw/sysbus.h" | 147 | + are permitted in any medium without royalty provided the copyright |
148 | + notice and this notice are preserved. --> | ||
64 | + | 149 | + |
65 | +/* | 150 | +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> |
66 | + * Number of registers in our device state structure. Don't change this without | 151 | +<feature name="org.gnu.gdb.aarch64.pauth"> |
67 | + * incrementing the version_id in the vmstate. | 152 | + <reg name="pauth_dmask" bitsize="64"/> |
68 | + */ | 153 | + <reg name="pauth_cmask" bitsize="64"/> |
69 | +#define NPCM_PSPI_NR_REGS 3 | 154 | + <reg name="pauth_dmask_high" bitsize="64"/> |
155 | + <reg name="pauth_cmask_high" bitsize="64"/> | ||
156 | +</feature> | ||
70 | + | 157 | + |
71 | +/** | ||
72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. | ||
73 | + * @parent: System bus device. | ||
74 | + * @mmio: Memory region for register access. | ||
75 | + * @spi: The SPI bus mastered by this controller. | ||
76 | + * @regs: Register contents. | ||
77 | + * @irq: The interrupt request queue for this module. | ||
78 | + * | ||
79 | + * Each PSPI has a shared bank of registers, and controls up to four chip | ||
80 | + * selects. Each chip select has a dedicated memory region which may be used to | ||
81 | + * read and write the flash connected to that chip select as if it were memory. | ||
82 | + */ | ||
83 | +typedef struct NPCMPSPIState { | ||
84 | + SysBusDevice parent; | ||
85 | + | ||
86 | + MemoryRegion mmio; | ||
87 | + | ||
88 | + SSIBus *spi; | ||
89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; | ||
90 | + qemu_irq irq; | ||
91 | +} NPCMPSPIState; | ||
92 | + | ||
93 | +#define TYPE_NPCM_PSPI "npcm-pspi" | ||
94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) | ||
95 | + | ||
96 | +#endif /* NPCM_PSPI_H */ | ||
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | ||
98 | new file mode 100644 | ||
99 | index XXXXXXX..XXXXXXX | ||
100 | --- /dev/null | ||
101 | +++ b/hw/ssi/npcm_pspi.c | ||
102 | @@ -XXX,XX +XXX,XX @@ | ||
103 | +/* | ||
104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) | ||
105 | + * | ||
106 | + * Copyright 2023 Google LLC | ||
107 | + * | ||
108 | + * This program is free software; you can redistribute it and/or modify it | ||
109 | + * under the terms of the GNU General Public License as published by the | ||
110 | + * Free Software Foundation; either version 2 of the License, or | ||
111 | + * (at your option) any later version. | ||
112 | + * | ||
113 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
116 | + * for more details. | ||
117 | + */ | ||
118 | + | ||
119 | +#include "qemu/osdep.h" | ||
120 | + | ||
121 | +#include "hw/irq.h" | ||
122 | +#include "hw/registerfields.h" | ||
123 | +#include "hw/ssi/npcm_pspi.h" | ||
124 | +#include "migration/vmstate.h" | ||
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
127 | +#include "qemu/log.h" | ||
128 | +#include "qemu/module.h" | ||
129 | +#include "qemu/units.h" | ||
130 | + | ||
131 | +#include "trace.h" | ||
132 | + | ||
133 | +REG16(PSPI_DATA, 0x0) | ||
134 | +REG16(PSPI_CTL1, 0x2) | ||
135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) | ||
136 | + FIELD(PSPI_CTL1, MOD, 2, 1) | ||
137 | + FIELD(PSPI_CTL1, EIR, 5, 1) | ||
138 | + FIELD(PSPI_CTL1, EIW, 6, 1) | ||
139 | + FIELD(PSPI_CTL1, SCM, 7, 1) | ||
140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) | ||
141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) | ||
142 | +REG16(PSPI_STAT, 0x4) | ||
143 | + FIELD(PSPI_STAT, BSY, 0, 1) | ||
144 | + FIELD(PSPI_STAT, RBF, 1, 1) | ||
145 | + | ||
146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) | ||
147 | +{ | ||
148 | + int level = 0; | ||
149 | + | ||
150 | + /* Only fire IRQ when the module is enabled. */ | ||
151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { | ||
152 | + /* Update interrupt as BSY is cleared. */ | ||
153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && | ||
154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { | ||
155 | + level = 1; | ||
156 | + } | ||
157 | + | ||
158 | + /* Update interrupt as RBF is set. */ | ||
159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && | ||
160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { | ||
161 | + level = 1; | ||
162 | + } | ||
163 | + } | ||
164 | + qemu_set_irq(s->irq, level); | ||
165 | +} | ||
166 | + | ||
167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) | ||
168 | +{ | ||
169 | + uint16_t value = s->regs[R_PSPI_DATA]; | ||
170 | + | ||
171 | + /* Clear stat bits as the value are read out. */ | ||
172 | + s->regs[R_PSPI_STAT] = 0; | ||
173 | + | ||
174 | + return value; | ||
175 | +} | ||
176 | + | ||
177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) | ||
178 | +{ | ||
179 | + uint16_t value = 0; | ||
180 | + | ||
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | ||
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | ||
183 | + } | ||
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | ||
185 | + s->regs[R_PSPI_DATA] = value; | ||
186 | + | ||
187 | + /* Mark data as available */ | ||
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | ||
189 | +} | ||
190 | + | ||
191 | +/* Control register read handler. */ | ||
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | ||
193 | + unsigned int size) | ||
194 | +{ | ||
195 | + NPCMPSPIState *s = opaque; | ||
196 | + uint16_t value; | ||
197 | + | ||
198 | + switch (addr) { | ||
199 | + case A_PSPI_DATA: | ||
200 | + value = npcm_pspi_read_data(s); | ||
201 | + break; | ||
202 | + | ||
203 | + case A_PSPI_CTL1: | ||
204 | + value = s->regs[R_PSPI_CTL1]; | ||
205 | + break; | ||
206 | + | ||
207 | + case A_PSPI_STAT: | ||
208 | + value = s->regs[R_PSPI_STAT]; | ||
209 | + break; | ||
210 | + | ||
211 | + default: | ||
212 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
214 | + DEVICE(s)->canonical_path, addr); | ||
215 | + return 0; | ||
216 | + } | ||
217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); | ||
218 | + npcm_pspi_update_irq(s); | ||
219 | + | ||
220 | + return value; | ||
221 | +} | ||
222 | + | ||
223 | +/* Control register write handler. */ | ||
224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, | ||
225 | + unsigned int size) | ||
226 | +{ | ||
227 | + NPCMPSPIState *s = opaque; | ||
228 | + uint16_t value = v; | ||
229 | + | ||
230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); | ||
231 | + | ||
232 | + switch (addr) { | ||
233 | + case A_PSPI_DATA: | ||
234 | + npcm_pspi_write_data(s, value); | ||
235 | + break; | ||
236 | + | ||
237 | + case A_PSPI_CTL1: | ||
238 | + s->regs[R_PSPI_CTL1] = value; | ||
239 | + break; | ||
240 | + | ||
241 | + case A_PSPI_STAT: | ||
242 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
243 | + "%s: write to read-only register PSPI_STAT: 0x%08" | ||
244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); | ||
245 | + break; | ||
246 | + | ||
247 | + default: | ||
248 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
250 | + DEVICE(s)->canonical_path, addr); | ||
251 | + return; | ||
252 | + } | ||
253 | + npcm_pspi_update_irq(s); | ||
254 | +} | ||
255 | + | ||
256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { | ||
257 | + .read = npcm_pspi_ctrl_read, | ||
258 | + .write = npcm_pspi_ctrl_write, | ||
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
260 | + .valid = { | ||
261 | + .min_access_size = 1, | ||
262 | + .max_access_size = 2, | ||
263 | + .unaligned = false, | ||
264 | + }, | ||
265 | + .impl = { | ||
266 | + .min_access_size = 2, | ||
267 | + .max_access_size = 2, | ||
268 | + .unaligned = false, | ||
269 | + }, | ||
270 | +}; | ||
271 | + | ||
272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) | ||
273 | +{ | ||
274 | + NPCMPSPIState *s = NPCM_PSPI(obj); | ||
275 | + | ||
276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); | ||
277 | + memset(s->regs, 0, sizeof(s->regs)); | ||
278 | +} | ||
279 | + | ||
280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) | ||
281 | +{ | ||
282 | + NPCMPSPIState *s = NPCM_PSPI(dev); | ||
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
284 | + Object *obj = OBJECT(dev); | ||
285 | + | ||
286 | + s->spi = ssi_create_bus(dev, "pspi"); | ||
287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, | ||
288 | + "mmio", 4 * KiB); | ||
289 | + sysbus_init_mmio(sbd, &s->mmio); | ||
290 | + sysbus_init_irq(sbd, &s->irq); | ||
291 | +} | ||
292 | + | ||
293 | +static const VMStateDescription vmstate_npcm_pspi = { | ||
294 | + .name = "npcm-pspi", | ||
295 | + .version_id = 0, | ||
296 | + .minimum_version_id = 0, | ||
297 | + .fields = (VMStateField[]) { | ||
298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), | ||
299 | + VMSTATE_END_OF_LIST(), | ||
300 | + }, | ||
301 | +}; | ||
302 | + | ||
303 | + | ||
304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) | ||
305 | +{ | ||
306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
307 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
308 | + | ||
309 | + dc->desc = "NPCM Peripheral SPI Module"; | ||
310 | + dc->realize = npcm_pspi_realize; | ||
311 | + dc->vmsd = &vmstate_npcm_pspi; | ||
312 | + rc->phases.enter = npcm_pspi_enter_reset; | ||
313 | +} | ||
314 | + | ||
315 | +static const TypeInfo npcm_pspi_types[] = { | ||
316 | + { | ||
317 | + .name = TYPE_NPCM_PSPI, | ||
318 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
322 | +}; | ||
323 | +DEFINE_TYPES(npcm_pspi_types); | ||
324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build | ||
325 | index XXXXXXX..XXXXXXX 100644 | ||
326 | --- a/hw/ssi/meson.build | ||
327 | +++ b/hw/ssi/meson.build | ||
328 | @@ -XXX,XX +XXX,XX @@ | ||
329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) | ||
330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) | ||
331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) | ||
332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) | ||
333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) | ||
334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) | ||
335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) | ||
336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
337 | index XXXXXXX..XXXXXXX 100644 | ||
338 | --- a/hw/ssi/trace-events | ||
339 | +++ b/hw/ssi/trace-events | ||
340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: | ||
341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
343 | |||
344 | +# npcm_pspi.c | ||
345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" | ||
346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
348 | + | ||
349 | # ibex_spi_host.c | ||
350 | |||
351 | ibex_spi_host_reset(const char *msg) "%s" | ||
352 | -- | 158 | -- |
353 | 2.34.1 | 159 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: David Reiss <dreiss@meta.com> |
---|---|---|---|
2 | 2 | ||
3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with | 3 | Allow the function to be used outside of m_helper.c. |
4 | a QEMU configured using --without-default-devices, we get: | 4 | Rename with an "arm_" prefix. |
5 | 5 | ||
6 | $ qemu-system-aarch64 -M xlnx-zcu102 | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | qemu-system-aarch64: missing object type 'usb_dwc3' | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Abort trap: 6 | 8 | Signed-off-by: David Reiss <dreiss@meta.com> |
9 | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | |
10 | Fix by adding the missing Kconfig dependency. | 10 | Message-id: 20230227213329.793795-13-richard.henderson@linaro.org |
11 | 11 | [rth: Split out of a larger patch] | |
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 14 | --- |
18 | hw/arm/Kconfig | 1 + | 15 | target/arm/internals.h | 3 +++ |
19 | 1 file changed, 1 insertion(+) | 16 | target/arm/tcg/m_helper.c | 6 +++--- |
17 | 2 files changed, 6 insertions(+), 3 deletions(-) | ||
20 | 18 | ||
21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
22 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/Kconfig | 21 | --- a/target/arm/internals.h |
24 | +++ b/hw/arm/Kconfig | 22 | +++ b/target/arm/internals.h |
25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM | 23 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); |
26 | select XLNX_CSU_DMA | 24 | void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); |
27 | select XLNX_ZYNQMP | 25 | #endif |
28 | select XLNX_ZDMA | 26 | |
29 | + select USB_DWC3 | 27 | +/* Read the CONTROL register as the MRS instruction would. */ |
30 | 28 | +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); | |
31 | config XLNX_VERSAL | 29 | + |
32 | bool | 30 | #ifdef CONFIG_USER_ONLY |
31 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
32 | #else | ||
33 | diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/tcg/m_helper.c | ||
36 | +++ b/target/arm/tcg/m_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) | ||
38 | return xpsr_read(env) & mask; | ||
39 | } | ||
40 | |||
41 | -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) | ||
42 | +uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) | ||
43 | { | ||
44 | uint32_t value = env->v7m.control[secure]; | ||
45 | |||
46 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
47 | case 0 ... 7: /* xPSR sub-fields */ | ||
48 | return v7m_mrs_xpsr(env, reg, 0); | ||
49 | case 20: /* CONTROL */ | ||
50 | - return v7m_mrs_control(env, 0); | ||
51 | + return arm_v7m_mrs_control(env, 0); | ||
52 | default: | ||
53 | /* Unprivileged reads others as zero. */ | ||
54 | return 0; | ||
55 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | ||
56 | case 0 ... 7: /* xPSR sub-fields */ | ||
57 | return v7m_mrs_xpsr(env, reg, el); | ||
58 | case 20: /* CONTROL */ | ||
59 | - return v7m_mrs_control(env, env->v7m.secure); | ||
60 | + return arm_v7m_mrs_control(env, env->v7m.secure); | ||
61 | case 0x94: /* CONTROL_NS */ | ||
62 | /* | ||
63 | * We have to handle this here because unprivileged Secure code | ||
33 | -- | 64 | -- |
34 | 2.34.1 | 65 | 2.34.1 |
35 | 66 | ||
36 | 67 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: David Reiss <dreiss@meta.com> |
---|---|---|---|
2 | 2 | ||
3 | If a test was tagged with the "accel" tag and the specified | 3 | Allow the function to be used outside of m_helper.c. |
4 | accelerator it not present in the qemu binary, cancel the test. | 4 | Move to be outside of ifndef CONFIG_USER_ONLY block. |
5 | Rename from get_v7m_sp_ptr. | ||
5 | 6 | ||
6 | We can now write tests without explicit calls to require_accelerator, | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | just the tag is enough. | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | 9 | Signed-off-by: David Reiss <dreiss@meta.com> | |
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20230227213329.793795-14-richard.henderson@linaro.org |
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 12 | [rth: Split out of a larger patch] |
13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ | 16 | target/arm/internals.h | 10 +++++ |
15 | 1 file changed, 4 insertions(+) | 17 | target/arm/tcg/m_helper.c | 84 +++++++++++++++++++-------------------- |
18 | 2 files changed, 51 insertions(+), 43 deletions(-) | ||
16 | 19 | ||
17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py | 20 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
18 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/tests/avocado/avocado_qemu/__init__.py | 22 | --- a/target/arm/internals.h |
20 | +++ b/tests/avocado/avocado_qemu/__init__.py | 23 | +++ b/target/arm/internals.h |
21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): | 24 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); |
22 | 25 | /* Read the CONTROL register as the MRS instruction would. */ | |
23 | super().setUp('qemu-system-') | 26 | uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure); |
24 | 27 | ||
25 | + accel_required = self._get_unique_tag_val('accel') | 28 | +/* |
26 | + if accel_required: | 29 | + * Return a pointer to the location where we currently store the |
27 | + self.require_accelerator(accel_required) | 30 | + * stack pointer for the requested security state and thread mode. |
31 | + * This pointer will become invalid if the CPU state is updated | ||
32 | + * such that the stack pointers are switched around (eg changing | ||
33 | + * the SPSEL control bit). | ||
34 | + */ | ||
35 | +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, | ||
36 | + bool threadmode, bool spsel); | ||
28 | + | 37 | + |
29 | self.machine = self.params.get('machine', | 38 | #ifdef CONFIG_USER_ONLY |
30 | default=self._get_unique_tag_val('machine')) | 39 | static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
31 | 40 | #else | |
41 | diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/tcg/m_helper.c | ||
44 | +++ b/target/arm/tcg/m_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | ||
46 | arm_rebuild_hflags(env); | ||
47 | } | ||
48 | |||
49 | -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode, | ||
50 | - bool spsel) | ||
51 | -{ | ||
52 | - /* | ||
53 | - * Return a pointer to the location where we currently store the | ||
54 | - * stack pointer for the requested security state and thread mode. | ||
55 | - * This pointer will become invalid if the CPU state is updated | ||
56 | - * such that the stack pointers are switched around (eg changing | ||
57 | - * the SPSEL control bit). | ||
58 | - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | ||
59 | - * Unlike that pseudocode, we require the caller to pass us in the | ||
60 | - * SPSEL control bit value; this is because we also use this | ||
61 | - * function in handling of pushing of the callee-saves registers | ||
62 | - * part of the v8M stack frame (pseudocode PushCalleeStack()), | ||
63 | - * and in the tailchain codepath the SPSEL bit comes from the exception | ||
64 | - * return magic LR value from the previous exception. The pseudocode | ||
65 | - * opencodes the stack-selection in PushCalleeStack(), but we prefer | ||
66 | - * to make this utility function generic enough to do the job. | ||
67 | - */ | ||
68 | - bool want_psp = threadmode && spsel; | ||
69 | - | ||
70 | - if (secure == env->v7m.secure) { | ||
71 | - if (want_psp == v7m_using_psp(env)) { | ||
72 | - return &env->regs[13]; | ||
73 | - } else { | ||
74 | - return &env->v7m.other_sp; | ||
75 | - } | ||
76 | - } else { | ||
77 | - if (want_psp) { | ||
78 | - return &env->v7m.other_ss_psp; | ||
79 | - } else { | ||
80 | - return &env->v7m.other_ss_msp; | ||
81 | - } | ||
82 | - } | ||
83 | -} | ||
84 | - | ||
85 | static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, | ||
86 | uint32_t *pvec) | ||
87 | { | ||
88 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
89 | !mode; | ||
90 | |||
91 | mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv); | ||
92 | - frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode, | ||
93 | - lr & R_V7M_EXCRET_SPSEL_MASK); | ||
94 | + frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode, | ||
95 | + lr & R_V7M_EXCRET_SPSEL_MASK); | ||
96 | want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK); | ||
97 | if (want_psp) { | ||
98 | limit = env->v7m.psplim[M_REG_S]; | ||
99 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
100 | * use 'frame_sp_p' after we do something that makes it invalid. | ||
101 | */ | ||
102 | bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK; | ||
103 | - uint32_t *frame_sp_p = get_v7m_sp_ptr(env, | ||
104 | - return_to_secure, | ||
105 | - !return_to_handler, | ||
106 | - spsel); | ||
107 | + uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure, | ||
108 | + !return_to_handler, spsel); | ||
109 | uint32_t frameptr = *frame_sp_p; | ||
110 | bool pop_ok = true; | ||
111 | ARMMMUIdx mmu_idx; | ||
112 | @@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu) | ||
113 | threadmode = !arm_v7m_is_handler_mode(env); | ||
114 | spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; | ||
115 | |||
116 | - frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel); | ||
117 | + frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel); | ||
118 | frameptr = *frame_sp_p; | ||
119 | |||
120 | /* | ||
121 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
122 | } | ||
123 | |||
124 | #endif /* !CONFIG_USER_ONLY */ | ||
125 | + | ||
126 | +uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, | ||
127 | + bool spsel) | ||
128 | +{ | ||
129 | + /* | ||
130 | + * Return a pointer to the location where we currently store the | ||
131 | + * stack pointer for the requested security state and thread mode. | ||
132 | + * This pointer will become invalid if the CPU state is updated | ||
133 | + * such that the stack pointers are switched around (eg changing | ||
134 | + * the SPSEL control bit). | ||
135 | + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). | ||
136 | + * Unlike that pseudocode, we require the caller to pass us in the | ||
137 | + * SPSEL control bit value; this is because we also use this | ||
138 | + * function in handling of pushing of the callee-saves registers | ||
139 | + * part of the v8M stack frame (pseudocode PushCalleeStack()), | ||
140 | + * and in the tailchain codepath the SPSEL bit comes from the exception | ||
141 | + * return magic LR value from the previous exception. The pseudocode | ||
142 | + * opencodes the stack-selection in PushCalleeStack(), but we prefer | ||
143 | + * to make this utility function generic enough to do the job. | ||
144 | + */ | ||
145 | + bool want_psp = threadmode && spsel; | ||
146 | + | ||
147 | + if (secure == env->v7m.secure) { | ||
148 | + if (want_psp == v7m_using_psp(env)) { | ||
149 | + return &env->regs[13]; | ||
150 | + } else { | ||
151 | + return &env->v7m.other_sp; | ||
152 | + } | ||
153 | + } else { | ||
154 | + if (want_psp) { | ||
155 | + return &env->v7m.other_ss_psp; | ||
156 | + } else { | ||
157 | + return &env->v7m.other_ss_msp; | ||
158 | + } | ||
159 | + } | ||
160 | +} | ||
32 | -- | 161 | -- |
33 | 2.34.1 | 162 | 2.34.1 |
34 | 163 | ||
35 | 164 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 3 | The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | go ahead and implement the other system registers as well. |
5 | Message-id: 20230206223502.25122-10-philmd@linaro.org | 5 | |
6 | Since there is significant overlap between the two, implement | ||
7 | them with common code. The only exception is the systemreg | ||
8 | view of CONTROL, which merges the banked bits as per MRS. | ||
9 | |||
10 | Signed-off-by: David Reiss <dreiss@meta.com> | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20230227213329.793795-15-richard.henderson@linaro.org | ||
13 | [rth: Substatial rewrite using enumerator and shared code.] | ||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 17 | --- |
8 | target/arm/cpu.h | 2 +- | 18 | target/arm/cpu.h | 2 + |
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 19 | target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++ |
20 | 2 files changed, 180 insertions(+) | ||
10 | 21 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 24 | --- a/target/arm/cpu.h |
14 | +++ b/target/arm/cpu.h | 25 | +++ b/target/arm/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 26 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
16 | uint32_t ctrl; | 27 | |
17 | } sau; | 28 | DynamicGDBXMLInfo dyn_sysreg_xml; |
18 | 29 | DynamicGDBXMLInfo dyn_svereg_xml; | |
19 | - void *nvic; | 30 | + DynamicGDBXMLInfo dyn_m_systemreg_xml; |
20 | #if !defined(CONFIG_USER_ONLY) | 31 | + DynamicGDBXMLInfo dyn_m_secextreg_xml; |
21 | + void *nvic; | 32 | |
22 | const struct arm_boot_info *boot_info; | 33 | /* Timers used by the generic (architected) timer */ |
23 | /* Store GICv3CPUState to access from this struct */ | 34 | QEMUTimer *gt_timer[NUM_GTIMERS]; |
24 | void *gicv3state; | 35 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/gdbstub.c | ||
38 | +++ b/target/arm/gdbstub.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) | ||
40 | return cpu->dyn_sysreg_xml.num; | ||
41 | } | ||
42 | |||
43 | +typedef enum { | ||
44 | + M_SYSREG_MSP, | ||
45 | + M_SYSREG_PSP, | ||
46 | + M_SYSREG_PRIMASK, | ||
47 | + M_SYSREG_CONTROL, | ||
48 | + M_SYSREG_BASEPRI, | ||
49 | + M_SYSREG_FAULTMASK, | ||
50 | + M_SYSREG_MSPLIM, | ||
51 | + M_SYSREG_PSPLIM, | ||
52 | +} MProfileSysreg; | ||
53 | + | ||
54 | +static const struct { | ||
55 | + const char *name; | ||
56 | + int feature; | ||
57 | +} m_sysreg_def[] = { | ||
58 | + [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M }, | ||
59 | + [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M }, | ||
60 | + [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M }, | ||
61 | + [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M }, | ||
62 | + [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN }, | ||
63 | + [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN }, | ||
64 | + [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 }, | ||
65 | + [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 }, | ||
66 | +}; | ||
67 | + | ||
68 | +static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec) | ||
69 | +{ | ||
70 | + uint32_t *ptr; | ||
71 | + | ||
72 | + switch (reg) { | ||
73 | + case M_SYSREG_MSP: | ||
74 | + ptr = arm_v7m_get_sp_ptr(env, sec, false, true); | ||
75 | + break; | ||
76 | + case M_SYSREG_PSP: | ||
77 | + ptr = arm_v7m_get_sp_ptr(env, sec, true, true); | ||
78 | + break; | ||
79 | + case M_SYSREG_MSPLIM: | ||
80 | + ptr = &env->v7m.msplim[sec]; | ||
81 | + break; | ||
82 | + case M_SYSREG_PSPLIM: | ||
83 | + ptr = &env->v7m.psplim[sec]; | ||
84 | + break; | ||
85 | + case M_SYSREG_PRIMASK: | ||
86 | + ptr = &env->v7m.primask[sec]; | ||
87 | + break; | ||
88 | + case M_SYSREG_BASEPRI: | ||
89 | + ptr = &env->v7m.basepri[sec]; | ||
90 | + break; | ||
91 | + case M_SYSREG_FAULTMASK: | ||
92 | + ptr = &env->v7m.faultmask[sec]; | ||
93 | + break; | ||
94 | + case M_SYSREG_CONTROL: | ||
95 | + ptr = &env->v7m.control[sec]; | ||
96 | + break; | ||
97 | + default: | ||
98 | + return NULL; | ||
99 | + } | ||
100 | + return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL; | ||
101 | +} | ||
102 | + | ||
103 | +static int m_sysreg_get(CPUARMState *env, GByteArray *buf, | ||
104 | + MProfileSysreg reg, bool secure) | ||
105 | +{ | ||
106 | + uint32_t *ptr = m_sysreg_ptr(env, reg, secure); | ||
107 | + | ||
108 | + if (ptr == NULL) { | ||
109 | + return 0; | ||
110 | + } | ||
111 | + return gdb_get_reg32(buf, *ptr); | ||
112 | +} | ||
113 | + | ||
114 | +static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg) | ||
115 | +{ | ||
116 | + /* | ||
117 | + * Here, we emulate MRS instruction, where CONTROL has a mix of | ||
118 | + * banked and non-banked bits. | ||
119 | + */ | ||
120 | + if (reg == M_SYSREG_CONTROL) { | ||
121 | + return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure)); | ||
122 | + } | ||
123 | + return m_sysreg_get(env, buf, reg, env->v7m.secure); | ||
124 | +} | ||
125 | + | ||
126 | +static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) | ||
127 | +{ | ||
128 | + return 0; /* TODO */ | ||
129 | +} | ||
130 | + | ||
131 | +static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) | ||
132 | +{ | ||
133 | + ARMCPU *cpu = ARM_CPU(cs); | ||
134 | + CPUARMState *env = &cpu->env; | ||
135 | + GString *s = g_string_new(NULL); | ||
136 | + int base_reg = orig_base_reg; | ||
137 | + int i; | ||
138 | + | ||
139 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
140 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
141 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n"); | ||
142 | + | ||
143 | + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { | ||
144 | + if (arm_feature(env, m_sysreg_def[i].feature)) { | ||
145 | + g_string_append_printf(s, | ||
146 | + "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
147 | + m_sysreg_def[i].name, base_reg++); | ||
148 | + } | ||
149 | + } | ||
150 | + | ||
151 | + g_string_append_printf(s, "</feature>"); | ||
152 | + cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false); | ||
153 | + cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg; | ||
154 | + | ||
155 | + return cpu->dyn_m_systemreg_xml.num; | ||
156 | +} | ||
157 | + | ||
158 | +#ifndef CONFIG_USER_ONLY | ||
159 | +/* | ||
160 | + * For user-only, we see the non-secure registers via m_systemreg above. | ||
161 | + * For secext, encode the non-secure view as even and secure view as odd. | ||
162 | + */ | ||
163 | +static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg) | ||
164 | +{ | ||
165 | + return m_sysreg_get(env, buf, reg >> 1, reg & 1); | ||
166 | +} | ||
167 | + | ||
168 | +static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) | ||
169 | +{ | ||
170 | + return 0; /* TODO */ | ||
171 | +} | ||
172 | + | ||
173 | +static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) | ||
174 | +{ | ||
175 | + ARMCPU *cpu = ARM_CPU(cs); | ||
176 | + GString *s = g_string_new(NULL); | ||
177 | + int base_reg = orig_base_reg; | ||
178 | + int i; | ||
179 | + | ||
180 | + g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
181 | + g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
182 | + g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n"); | ||
183 | + | ||
184 | + for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) { | ||
185 | + g_string_append_printf(s, | ||
186 | + "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
187 | + m_sysreg_def[i].name, base_reg++); | ||
188 | + g_string_append_printf(s, | ||
189 | + "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n", | ||
190 | + m_sysreg_def[i].name, base_reg++); | ||
191 | + } | ||
192 | + | ||
193 | + g_string_append_printf(s, "</feature>"); | ||
194 | + cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false); | ||
195 | + cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg; | ||
196 | + | ||
197 | + return cpu->dyn_m_secextreg_xml.num; | ||
198 | +} | ||
199 | +#endif | ||
200 | + | ||
201 | const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
202 | { | ||
203 | ARMCPU *cpu = ARM_CPU(cs); | ||
204 | @@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) | ||
205 | return cpu->dyn_sysreg_xml.desc; | ||
206 | } else if (strcmp(xmlname, "sve-registers.xml") == 0) { | ||
207 | return cpu->dyn_svereg_xml.desc; | ||
208 | + } else if (strcmp(xmlname, "arm-m-system.xml") == 0) { | ||
209 | + return cpu->dyn_m_systemreg_xml.desc; | ||
210 | +#ifndef CONFIG_USER_ONLY | ||
211 | + } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) { | ||
212 | + return cpu->dyn_m_secextreg_xml.desc; | ||
213 | +#endif | ||
214 | } | ||
215 | return NULL; | ||
216 | } | ||
217 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
218 | arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), | ||
219 | "system-registers.xml", 0); | ||
220 | |||
221 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
222 | + gdb_register_coprocessor(cs, | ||
223 | + arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, | ||
224 | + arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), | ||
225 | + "arm-m-system.xml", 0); | ||
226 | +#ifndef CONFIG_USER_ONLY | ||
227 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
228 | + gdb_register_coprocessor(cs, | ||
229 | + arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, | ||
230 | + arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), | ||
231 | + "arm-m-secext.xml", 0); | ||
232 | + } | ||
233 | +#endif | ||
234 | + } | ||
235 | } | ||
25 | -- | 236 | -- |
26 | 2.34.1 | 237 | 2.34.1 |
27 | |||
28 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421 |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20230206223502.25122-9-philmd@linaro.org | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20230227225832.816605-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | target/arm/cpu.h | 2 +- | 9 | target/arm/cpu.h | 3 +++ |
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | 1 file changed, 3 insertions(+) |
10 | 11 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 12 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 14 | --- a/target/arm/cpu.h |
14 | +++ b/target/arm/cpu.h | 15 | +++ b/target/arm/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 16 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) |
16 | } sau; | 17 | /* Return true if the processor is in secure state */ |
17 | 18 | static inline bool arm_is_secure(CPUARMState *env) | |
18 | void *nvic; | 19 | { |
19 | - const struct arm_boot_info *boot_info; | 20 | + if (arm_feature(env, ARM_FEATURE_M)) { |
20 | #if !defined(CONFIG_USER_ONLY) | 21 | + return env->v7m.secure; |
21 | + const struct arm_boot_info *boot_info; | 22 | + } |
22 | /* Store GICv3CPUState to access from this struct */ | 23 | if (arm_is_el3_or_mon(env)) { |
23 | void *gicv3state; | 24 | return true; |
24 | #else /* CONFIG_USER_ONLY */ | 25 | } |
25 | -- | 26 | -- |
26 | 2.34.1 | 27 | 2.34.1 |
27 | |||
28 | diff view generated by jsdifflib |
1 | From: Claudio Fontana <cfontana@suse.de> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | 3 | M-profile doesn't have HCR_EL2. While we could test features |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | before each call, zero is a generally safe return value to |
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 5 | disable the code in the caller. This test is required to |
6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | avoid an assert in arm_is_secure_below_el3. |
7 | |||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230227225832.816605-3-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 12 | --- |
9 | target/arm/helper.c | 12 +++++++----- | 13 | target/arm/helper.c | 3 +++ |
10 | 1 file changed, 7 insertions(+), 5 deletions(-) | 14 | 1 file changed, 3 insertions(+) |
11 | 15 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 18 | --- a/target/arm/helper.c |
15 | +++ b/target/arm/helper.c | 19 | +++ b/target/arm/helper.c |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 20 | @@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) |
17 | unsigned int cur_el = arm_current_el(env); | 21 | |
18 | int rt; | 22 | uint64_t arm_hcr_el2_eff(CPUARMState *env) |
19 | 23 | { | |
20 | - /* | 24 | + if (arm_feature(env, ARM_FEATURE_M)) { |
21 | - * Note that new_el can never be 0. If cur_el is 0, then | 25 | + return 0; |
22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. | ||
23 | - */ | ||
24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | ||
25 | + if (tcg_enabled()) { | ||
26 | + /* | ||
27 | + * Note that new_el can never be 0. If cur_el is 0, then | ||
28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. | ||
29 | + */ | ||
30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | ||
31 | + } | 26 | + } |
32 | 27 | return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); | |
33 | if (cur_el < new_el) { | 28 | } |
34 | /* | 29 | |
35 | -- | 30 | -- |
36 | 2.34.1 | 31 | 2.34.1 |
37 | |||
38 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 3 | In several places we use arm_is_secure_below_el3 and |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | arm_is_el3_or_mon separately from arm_is_secure. |
5 | Message-id: 20230206223502.25122-8-philmd@linaro.org | 5 | These functions make no sense for m-profile, and |
6 | would indicate prior incorrect feature testing. | ||
7 | |||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20230227225832.816605-4-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/cpu.h | 3 ++- | 14 | target/arm/cpu.h | 5 ++++- |
9 | 1 file changed, 2 insertions(+), 1 deletion(-) | 15 | 1 file changed, 4 insertions(+), 1 deletion(-) |
10 | 16 | ||
11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/cpu.h |
14 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | 21 | @@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature) |
16 | 22 | void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); | |
17 | void *nvic; | 23 | |
18 | const struct arm_boot_info *boot_info; | 24 | #if !defined(CONFIG_USER_ONLY) |
19 | +#if !defined(CONFIG_USER_ONLY) | 25 | -/* Return true if exception levels below EL3 are in secure state, |
20 | /* Store GICv3CPUState to access from this struct */ | 26 | +/* |
21 | void *gicv3state; | 27 | + * Return true if exception levels below EL3 are in secure state, |
22 | -#if defined(CONFIG_USER_ONLY) | 28 | * or would be following an exception return to that level. |
23 | +#else /* CONFIG_USER_ONLY */ | 29 | * Unlike arm_is_secure() (which is always a question about the |
24 | /* For usermode syscall translation. */ | 30 | * _current_ state of the CPU) this doesn't care about the current |
25 | bool eabi; | 31 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); |
26 | #endif /* CONFIG_USER_ONLY */ | 32 | */ |
33 | static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
34 | { | ||
35 | + assert(!arm_feature(env, ARM_FEATURE_M)); | ||
36 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
37 | return !(env->cp15.scr_el3 & SCR_NS); | ||
38 | } else { | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env) | ||
40 | /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ | ||
41 | static inline bool arm_is_el3_or_mon(CPUARMState *env) | ||
42 | { | ||
43 | + assert(!arm_feature(env, ARM_FEATURE_M)); | ||
44 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
45 | if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { | ||
46 | /* CPU currently in AArch64 state and EL3 */ | ||
27 | -- | 47 | -- |
28 | 2.34.1 | 48 | 2.34.1 |
29 | 49 | ||
30 | 50 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | While dozens of files include "cpu.h", only 3 files require | ||
4 | these NVIC helper declarations. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Message-id: 20230206223502.25122-12-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/cpu.h | 123 ---------------------------------- | ||
13 | target/arm/cpu.c | 4 +- | ||
14 | target/arm/cpu_tcg.c | 3 + | ||
15 | target/arm/m_helper.c | 3 + | ||
16 | 5 files changed, 132 insertions(+), 124 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/intc/armv7m_nvic.h | ||
21 | +++ b/include/hw/intc/armv7m_nvic.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { | ||
23 | qemu_irq sysresetreq; | ||
24 | }; | ||
25 | |||
26 | +/* Interface between CPU and Interrupt controller. */ | ||
27 | +/** | ||
28 | + * armv7m_nvic_set_pending: mark the specified exception as pending | ||
29 | + * @s: the NVIC | ||
30 | + * @irq: the exception number to mark pending | ||
31 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
32 | + * version of a banked exception, true for the secure version of a banked | ||
33 | + * exception. | ||
34 | + * | ||
35 | + * Marks the specified exception as pending. Note that we will assert() | ||
36 | + * if @secure is true and @irq does not specify one of the fixed set | ||
37 | + * of architecturally banked exceptions. | ||
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
148 | + | ||
149 | #endif | ||
150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/cpu.h | ||
153 | +++ b/target/arm/cpu.h | ||
154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
156 | uint32_t cur_el, bool secure); | ||
157 | |||
158 | -/* Interface between CPU and Interrupt controller. */ | ||
159 | -#ifndef CONFIG_USER_ONLY | ||
160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
161 | -#else | ||
162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
163 | -{ | ||
164 | - return true; | ||
165 | -} | ||
166 | -#endif | ||
167 | -/** | ||
168 | - * armv7m_nvic_set_pending: mark the specified exception as pending | ||
169 | - * @s: the NVIC | ||
170 | - * @irq: the exception number to mark pending | ||
171 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
172 | - * version of a banked exception, true for the secure version of a banked | ||
173 | - * exception. | ||
174 | - * | ||
175 | - * Marks the specified exception as pending. Note that we will assert() | ||
176 | - * if @secure is true and @irq does not specify one of the fixed set | ||
177 | - * of architecturally banked exceptions. | ||
178 | - */ | ||
179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
180 | -/** | ||
181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
182 | - * @s: the NVIC | ||
183 | - * @irq: the exception number to mark pending | ||
184 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
279 | -#endif | ||
280 | - | ||
281 | /* Interface for defining coprocessor registers. | ||
282 | * Registers are defined in tables of arm_cp_reginfo structs | ||
283 | * which are passed to define_arm_cp_regs(). | ||
284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/target/arm/cpu.c | ||
287 | +++ b/target/arm/cpu.c | ||
288 | @@ -XXX,XX +XXX,XX @@ | ||
289 | #if !defined(CONFIG_USER_ONLY) | ||
290 | #include "hw/loader.h" | ||
291 | #include "hw/boards.h" | ||
292 | +#ifdef CONFIG_TCG | ||
293 | #include "hw/intc/armv7m_nvic.h" | ||
294 | -#endif | ||
295 | +#endif /* CONFIG_TCG */ | ||
296 | +#endif /* !CONFIG_USER_ONLY */ | ||
297 | #include "sysemu/tcg.h" | ||
298 | #include "sysemu/qtest.h" | ||
299 | #include "sysemu/hw_accel.h" | ||
300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
301 | index XXXXXXX..XXXXXXX 100644 | ||
302 | --- a/target/arm/cpu_tcg.c | ||
303 | +++ b/target/arm/cpu_tcg.c | ||
304 | @@ -XXX,XX +XXX,XX @@ | ||
305 | #include "hw/boards.h" | ||
306 | #endif | ||
307 | #include "cpregs.h" | ||
308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
309 | +#include "hw/intc/armv7m_nvic.h" | ||
310 | +#endif | ||
311 | |||
312 | |||
313 | /* Share AArch32 -cpu max features with AArch64. */ | ||
314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/m_helper.c | ||
317 | +++ b/target/arm/m_helper.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
328 | -- | ||
329 | 2.34.1 | ||
330 | |||
331 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
2 | 1 | ||
3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros | ||
4 | that take a long time to boot up, especially for an --enable-debug | ||
5 | build. The total code coverage they give is: | ||
6 | |||
7 | Overall coverage rate: | ||
8 | lines......: 11.2% (59584 of 530123 lines) | ||
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | tests/avocado/boot_linux.py | 48 ++++---------------- | ||
35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- | ||
36 | 2 files changed, 65 insertions(+), 46 deletions(-) | ||
37 | |||
38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/tests/avocado/boot_linux.py | ||
41 | +++ b/tests/avocado/boot_linux.py | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): | ||
43 | self.launch_and_wait(set_up_ssh_connection=False) | ||
44 | |||
45 | |||
46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very | ||
47 | -# heavyweight. There are lighter weight distros which we use in the | ||
48 | -# machine_aarch64_virt.py tests. | ||
49 | +# For Aarch64 we only boot KVM tests in CI as booting the current | ||
50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight | ||
51 | +# distros which we use in the machine_aarch64_virt.py tests. | ||
52 | class BootLinuxAarch64(LinuxTest): | ||
53 | """ | ||
54 | :avocado: tags=arch:aarch64 | ||
55 | :avocado: tags=machine:virt | ||
56 | - :avocado: tags=machine:gic-version=2 | ||
57 | """ | ||
58 | timeout = 720 | ||
59 | |||
60 | - def add_common_args(self): | ||
61 | - self.vm.add_args('-bios', | ||
62 | - os.path.join(BUILD_DIR, 'pc-bios', | ||
63 | - 'edk2-aarch64-code.fd')) | ||
64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
66 | - | ||
67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
68 | - def test_fedora_cloud_tcg_gicv2(self): | ||
69 | - """ | ||
70 | - :avocado: tags=accel:tcg | ||
71 | - :avocado: tags=cpu:max | ||
72 | - :avocado: tags=device:gicv2 | ||
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/tests/avocado/machine_aarch64_virt.py | ||
114 | +++ b/tests/avocado/machine_aarch64_virt.py | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | |||
117 | import time | ||
118 | import os | ||
119 | +import logging | ||
120 | |||
121 | from avocado_qemu import QemuSystemTest | ||
122 | from avocado_qemu import wait_for_console_pattern | ||
123 | from avocado_qemu import exec_command | ||
124 | from avocado_qemu import BUILD_DIR | ||
125 | +from avocado.utils import process | ||
126 | +from avocado.utils.path import find_command | ||
127 | |||
128 | class Aarch64VirtMachine(QemuSystemTest): | ||
129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' | ||
130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): | ||
131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') | ||
132 | |||
133 | |||
134 | - def test_aarch64_virt(self): | ||
135 | + def common_aarch64_virt(self, machine): | ||
136 | """ | ||
137 | - :avocado: tags=arch:aarch64 | ||
138 | - :avocado: tags=machine:virt | ||
139 | - :avocado: tags=accel:tcg | ||
140 | - :avocado: tags=cpu:max | ||
141 | + Common code to launch basic virt machine with kernel+initrd | ||
142 | + and a scratch disk. | ||
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
215 | -- | ||
216 | 2.34.1 | ||
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Hao Wu <wuhaotsh@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | 3 | Integrate neighboring code from get_phys_addr_lpae which computed |
4 | Reviewed-by: Titus Rwantare <titusr@google.com> | 4 | starting level, as it is easier to validate when doing both at the |
5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | 5 | same time. Mirror the checks at the start of AArch{64,32}.S2Walk, |
6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com | 6 | especially S2InvalidSL and S2InconsistentSL. |
7 | |||
8 | This reverts 49ba115bb74, which was incorrect -- there is nothing | ||
9 | in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the | ||
10 | pseudocode is consistent in referencing PAMax. | ||
11 | |||
12 | Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup") | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20230227225832.816605-5-richard.henderson@linaro.org | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 17 | --- |
9 | docs/system/arm/nuvoton.rst | 2 +- | 18 | target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- |
10 | include/hw/arm/npcm7xx.h | 2 ++ | 19 | 1 file changed, 97 insertions(+), 76 deletions(-) |
11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- | 20 | |
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | 21 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
13 | |||
14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/docs/system/arm/nuvoton.rst | 23 | --- a/target/arm/ptw.c |
17 | +++ b/docs/system/arm/nuvoton.rst | 24 | +++ b/target/arm/ptw.c |
18 | @@ -XXX,XX +XXX,XX @@ Supported devices | 25 | @@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, |
19 | * SMBus controller (SMBF) | 26 | * check_s2_mmu_setup |
20 | * Ethernet controller (EMC) | 27 | * @cpu: ARMCPU |
21 | * Tachometer | 28 | * @is_aa64: True if the translation regime is in AArch64 state |
22 | + * Peripheral SPI controller (PSPI) | 29 | - * @startlevel: Suggested starting level |
23 | 30 | - * @inputsize: Bitsize of IPAs | |
24 | Missing devices | 31 | + * @tcr: VTCR_EL2 or VSTCR_EL2 |
25 | --------------- | 32 | + * @ds: Effective value of TCR.DS. |
26 | @@ -XXX,XX +XXX,XX @@ Missing devices | 33 | + * @iasize: Bitsize of IPAs |
27 | 34 | * @stride: Page-table stride (See the ARM ARM) | |
28 | * Ethernet controller (GMAC) | 35 | * |
29 | * USB device (USBD) | 36 | - * Returns true if the suggested S2 translation parameters are OK and |
30 | - * Peripheral SPI controller (PSPI) | 37 | - * false otherwise. |
31 | * SD/MMC host | 38 | + * Decode the starting level of the S2 lookup, returning INT_MIN if |
32 | * PECI interface | 39 | + * the configuration is invalid. |
33 | * PCI and PCIe root complex and bridges | 40 | */ |
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | 41 | -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, |
35 | index XXXXXXX..XXXXXXX 100644 | 42 | - int inputsize, int stride, int outputsize) |
36 | --- a/include/hw/arm/npcm7xx.h | 43 | +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, |
37 | +++ b/include/hw/arm/npcm7xx.h | 44 | + bool ds, int iasize, int stride) |
38 | @@ -XXX,XX +XXX,XX @@ | 45 | { |
39 | #include "hw/nvram/npcm7xx_otp.h" | 46 | - const int grainsize = stride + 3; |
40 | #include "hw/timer/npcm7xx_timer.h" | 47 | - int startsizecheck; |
41 | #include "hw/ssi/npcm7xx_fiu.h" | 48 | - |
42 | +#include "hw/ssi/npcm_pspi.h" | 49 | - /* |
43 | #include "hw/usb/hcd-ehci.h" | 50 | - * Negative levels are usually not allowed... |
44 | #include "hw/usb/hcd-ohci.h" | 51 | - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which |
45 | #include "target/arm/cpu.h" | 52 | - * begins with level -1. Note that previous feature tests will have |
46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { | 53 | - * eliminated this combination if it is not enabled. |
47 | NPCM7xxFIUState fiu[2]; | 54 | - */ |
48 | NPCM7xxEMCState emc[2]; | 55 | - if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) { |
49 | NPCM7xxSDHCIState mmc; | 56 | - return false; |
50 | + NPCMPSPIState pspi[2]; | 57 | - } |
51 | }; | 58 | - |
52 | 59 | - startsizecheck = inputsize - ((3 - level) * stride + grainsize); | |
53 | #define TYPE_NPCM7XX "npcm7xx" | 60 | - if (startsizecheck < 1 || startsizecheck > stride + 4) { |
54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | 61 | - return false; |
55 | index XXXXXXX..XXXXXXX 100644 | 62 | - } |
56 | --- a/hw/arm/npcm7xx.c | 63 | + int sl0, sl2, startlevel, granulebits, levels; |
57 | +++ b/hw/arm/npcm7xx.c | 64 | + int s1_min_iasize, s1_max_iasize; |
58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | 65 | |
59 | NPCM7XX_EMC1RX_IRQ = 15, | 66 | + sl0 = extract32(tcr, 6, 2); |
60 | NPCM7XX_EMC1TX_IRQ, | 67 | if (is_aa64) { |
61 | NPCM7XX_MMC_IRQ = 26, | 68 | + /* |
62 | + NPCM7XX_PSPI2_IRQ = 28, | 69 | + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of |
63 | + NPCM7XX_PSPI1_IRQ = 31, | 70 | + * get_phys_addr_lpae, that used aa64_va_parameters which apply |
64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ | 71 | + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. |
65 | NPCM7XX_TIMER1_IRQ, | 72 | + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to |
66 | NPCM7XX_TIMER2_IRQ, | 73 | + * inputsize is 64 - 24 = 40. |
67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { | 74 | + */ |
68 | 0xf0826000, | 75 | + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { |
69 | }; | 76 | + goto fail; |
70 | 77 | + } | |
71 | +/* Register base address for each PSPI Module */ | 78 | + |
72 | +static const hwaddr npcm7xx_pspi_addr[] = { | 79 | + /* |
73 | + 0xf0200000, | 80 | + * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, |
74 | + 0xf0201000, | 81 | + * so interleave AArch64.S2StartLevel. |
75 | +}; | 82 | + */ |
76 | + | 83 | switch (stride) { |
77 | static const struct { | 84 | - case 13: /* 64KB Pages. */ |
78 | hwaddr regs_addr; | 85 | - if (level == 0 || (level == 1 && outputsize <= 42)) { |
79 | uint32_t unconnected_pins; | 86 | - return false; |
80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) | 87 | + case 9: /* 4KB */ |
81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); | 88 | + /* SL2 is RES0 unless DS=1 & 4KB granule. */ |
89 | + sl2 = extract64(tcr, 33, 1); | ||
90 | + if (ds && sl2) { | ||
91 | + if (sl0 != 0) { | ||
92 | + goto fail; | ||
93 | + } | ||
94 | + startlevel = -1; | ||
95 | + } else { | ||
96 | + startlevel = 2 - sl0; | ||
97 | + switch (sl0) { | ||
98 | + case 2: | ||
99 | + if (arm_pamax(cpu) < 44) { | ||
100 | + goto fail; | ||
101 | + } | ||
102 | + break; | ||
103 | + case 3: | ||
104 | + if (!cpu_isar_feature(aa64_st, cpu)) { | ||
105 | + goto fail; | ||
106 | + } | ||
107 | + startlevel = 3; | ||
108 | + break; | ||
109 | + } | ||
110 | } | ||
111 | break; | ||
112 | - case 11: /* 16KB Pages. */ | ||
113 | - if (level == 0 || (level == 1 && outputsize <= 40)) { | ||
114 | - return false; | ||
115 | + case 11: /* 16KB */ | ||
116 | + switch (sl0) { | ||
117 | + case 2: | ||
118 | + if (arm_pamax(cpu) < 42) { | ||
119 | + goto fail; | ||
120 | + } | ||
121 | + break; | ||
122 | + case 3: | ||
123 | + if (!ds) { | ||
124 | + goto fail; | ||
125 | + } | ||
126 | + break; | ||
127 | } | ||
128 | + startlevel = 3 - sl0; | ||
129 | break; | ||
130 | - case 9: /* 4KB Pages. */ | ||
131 | - if (level == 0 && outputsize <= 42) { | ||
132 | - return false; | ||
133 | + case 13: /* 64KB */ | ||
134 | + switch (sl0) { | ||
135 | + case 2: | ||
136 | + if (arm_pamax(cpu) < 44) { | ||
137 | + goto fail; | ||
138 | + } | ||
139 | + break; | ||
140 | + case 3: | ||
141 | + goto fail; | ||
142 | } | ||
143 | + startlevel = 3 - sl0; | ||
144 | break; | ||
145 | default: | ||
146 | g_assert_not_reached(); | ||
147 | } | ||
148 | - | ||
149 | - /* Inputsize checks. */ | ||
150 | - if (inputsize > outputsize && | ||
151 | - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { | ||
152 | - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */ | ||
153 | - return false; | ||
154 | - } | ||
155 | } else { | ||
156 | - /* AArch32 only supports 4KB pages. Assert on that. */ | ||
157 | + /* | ||
158 | + * Things are simpler for AArch32 EL2, with only 4k pages. | ||
159 | + * There is no separate S2InvalidSL function, but AArch32.S2Walk | ||
160 | + * begins with walkparms.sl0 in {'1x'}. | ||
161 | + */ | ||
162 | assert(stride == 9); | ||
163 | - | ||
164 | - if (level == 0) { | ||
165 | - return false; | ||
166 | + if (sl0 >= 2) { | ||
167 | + goto fail; | ||
168 | } | ||
169 | + startlevel = 2 - sl0; | ||
82 | } | 170 | } |
83 | 171 | - return true; | |
84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | 172 | + |
85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); | 173 | + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ |
174 | + levels = 3 - startlevel; | ||
175 | + granulebits = stride + 3; | ||
176 | + | ||
177 | + s1_min_iasize = levels * stride + granulebits + 1; | ||
178 | + s1_max_iasize = s1_min_iasize + (stride - 1) + 4; | ||
179 | + | ||
180 | + if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) { | ||
181 | + return startlevel; | ||
86 | + } | 182 | + } |
87 | + | 183 | + |
88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); | 184 | + fail: |
185 | + return INT_MIN; | ||
89 | } | 186 | } |
90 | 187 | ||
91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | 188 | /** |
92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, | 189 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); | 190 | */ |
94 | 191 | level = 4 - (inputsize - 4) / stride; | |
95 | + /* PSPI */ | 192 | } else { |
96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); | 193 | - /* |
97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { | 194 | - * For stage 2 translations the starting level is specified by the |
98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); | 195 | - * VTCR_EL2.SL0 field (whose interpretation depends on the page size) |
99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; | 196 | - */ |
100 | + | 197 | - uint32_t sl0 = extract32(tcr, 6, 2); |
101 | + sysbus_realize(sbd, &error_abort); | 198 | - uint32_t sl2 = extract64(tcr, 33, 1); |
102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); | 199 | - int32_t startlevel; |
103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); | 200 | - bool ok; |
104 | + } | 201 | - |
105 | + | 202 | - /* SL2 is RES0 unless DS=1 & 4kb granule. */ |
106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); | 203 | - if (param.ds && stride == 9 && sl2) { |
107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); | 204 | - if (sl0 != 0) { |
108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); | 205 | - level = 0; |
109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | 206 | - goto do_translation_fault; |
110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); | 207 | - } |
111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | 208 | - startlevel = -1; |
112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | 209 | - } else if (!aarch64 || stride == 9) { |
113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); | 210 | - /* AArch32 or 4KB pages */ |
114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); | 211 | - startlevel = 2 - sl0; |
115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); | 212 | - |
116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); | 213 | - if (cpu_isar_feature(aa64_st, cpu)) { |
117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); | 214 | - startlevel &= 3; |
215 | - } | ||
216 | - } else { | ||
217 | - /* 16KB or 64KB pages */ | ||
218 | - startlevel = 3 - sl0; | ||
219 | - } | ||
220 | - | ||
221 | - /* Check that the starting level is valid. */ | ||
222 | - ok = check_s2_mmu_setup(cpu, aarch64, startlevel, | ||
223 | - inputsize, stride, outputsize); | ||
224 | - if (!ok) { | ||
225 | + int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, | ||
226 | + inputsize, stride); | ||
227 | + if (startlevel == INT_MIN) { | ||
228 | + level = 0; | ||
229 | goto do_translation_fault; | ||
230 | } | ||
231 | level = startlevel; | ||
118 | -- | 232 | -- |
119 | 2.34.1 | 233 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: Ard Biesheuvel <ardb@kernel.org> |
---|---|---|---|
2 | 2 | ||
3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have | 3 | Fedora 39 will ship its arm64 kernels in the new generic EFI zboot |
4 | a cpregs.h header which is more suitable for this code. | 4 | format, using gzip compression for the payload. |
5 | 5 | ||
6 | Code moved verbatim. | 6 | For doing EFI boot in QEMU, this is completely transparent, as the |
7 | firmware or bootloader will take care of this. However, for direct | ||
8 | kernel boot without firmware, we will lose the ability to boot such | ||
9 | distro kernels unless we deal with the new format directly. | ||
7 | 10 | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | 11 | EFI zboot images contain metadata in the header regarding the placement |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | of the compressed payload inside the image, and the type of compression |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 13 | used. This means we can wire up the existing gzip support without too |
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 14 | much hassle, by parsing the header and grabbing the payload from inside |
15 | the loaded zboot image. | ||
16 | |||
17 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Cc: Alex Bennée <alex.bennee@linaro.org> | ||
19 | Cc: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
21 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | ||
22 | Message-id: 20230303160109.3626966-1-ardb@kernel.org | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
24 | [PMM: tweaked comment formatting, fixed checkpatch nits] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 26 | --- |
14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ | 27 | include/hw/loader.h | 19 ++++++++++ |
15 | target/arm/cpu.h | 91 ----------------------------------------- | 28 | hw/arm/boot.c | 6 +++ |
16 | 2 files changed, 98 insertions(+), 91 deletions(-) | 29 | hw/core/loader.c | 91 +++++++++++++++++++++++++++++++++++++++++++++ |
30 | 3 files changed, 116 insertions(+) | ||
17 | 31 | ||
18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | 32 | diff --git a/include/hw/loader.h b/include/hw/loader.h |
19 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpregs.h | 34 | --- a/include/hw/loader.h |
21 | +++ b/target/arm/cpregs.h | 35 | +++ b/include/hw/loader.h |
22 | @@ -XXX,XX +XXX,XX @@ enum { | 36 | @@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz, |
23 | ARM_CP_SME = 1 << 19, | 37 | uint8_t **buffer); |
24 | }; | 38 | ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz); |
25 | 39 | ||
26 | +/* | 40 | +/** |
27 | + * Interface for defining coprocessor registers. | 41 | + * unpack_efi_zboot_image: |
28 | + * Registers are defined in tables of arm_cp_reginfo structs | 42 | + * @buffer: pointer to a variable holding the address of a buffer containing the |
29 | + * which are passed to define_arm_cp_regs(). | 43 | + * image |
44 | + * @size: pointer to a variable holding the size of the buffer | ||
45 | + * | ||
46 | + * Check whether the buffer contains a EFI zboot image, and if it does, extract | ||
47 | + * the compressed payload and decompress it into a new buffer. If successful, | ||
48 | + * the old buffer is freed, and the *buffer and size variables pointed to by the | ||
49 | + * function arguments are updated to refer to the newly populated buffer. | ||
50 | + * | ||
51 | + * Returns 0 if the image could not be identified as a EFI zboot image. | ||
52 | + * Returns -1 if the buffer contents were identified as a EFI zboot image, but | ||
53 | + * unpacking failed for any reason. | ||
54 | + * Returns the size of the decompressed payload if decompression was performed | ||
55 | + * successfully. | ||
30 | + */ | 56 | + */ |
57 | +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size); | ||
58 | + | ||
59 | #define ELF_LOAD_FAILED -1 | ||
60 | #define ELF_LOAD_NOT_ELF -2 | ||
61 | #define ELF_LOAD_WRONG_ARCH -3 | ||
62 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/hw/arm/boot.c | ||
65 | +++ b/hw/arm/boot.c | ||
66 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | ||
67 | return -1; | ||
68 | } | ||
69 | size = len; | ||
70 | + | ||
71 | + /* Unpack the image if it is a EFI zboot image */ | ||
72 | + if (unpack_efi_zboot_image(&buffer, &size) < 0) { | ||
73 | + g_free(buffer); | ||
74 | + return -1; | ||
75 | + } | ||
76 | } | ||
77 | |||
78 | /* check the arm64 magic header value -- very old kernels may not have it */ | ||
79 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/core/loader.c | ||
82 | +++ b/hw/core/loader.c | ||
83 | @@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz) | ||
84 | return bytes; | ||
85 | } | ||
86 | |||
87 | +/* The PE/COFF MS-DOS stub magic number */ | ||
88 | +#define EFI_PE_MSDOS_MAGIC "MZ" | ||
31 | + | 89 | + |
32 | +/* | 90 | +/* |
33 | + * When looking up a coprocessor register we look for it | 91 | + * The Linux header magic number for a EFI PE/COFF |
34 | + * via an integer which encodes all of: | 92 | + * image targetting an unspecified architecture. |
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | 93 | + */ |
50 | +/* | 94 | +#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81" |
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | 95 | + |
58 | +/* | 96 | +/* |
59 | + * To enable banking of coprocessor registers depending on ns-bit we | 97 | + * Bootable Linux kernel images may be packaged as EFI zboot images, which are |
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | 98 | + * self-decompressing executables when loaded via EFI. The compressed payload |
61 | + * hashtable. | 99 | + * can also be extracted from the image and decompressed by a non-EFI loader. |
100 | + * | ||
101 | + * The de facto specification for this format is at the following URL: | ||
102 | + * | ||
103 | + * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S | ||
104 | + * | ||
105 | + * This definition is based on Linux upstream commit 29636a5ce87beba. | ||
62 | + */ | 106 | + */ |
63 | +#define CP_REG_NS_SHIFT 29 | 107 | +struct linux_efi_zboot_header { |
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | 108 | + uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */ |
65 | + | 109 | + uint8_t reserved0[2]; |
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | 110 | + uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */ |
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | 111 | + uint32_t payload_offset; /* LE offset to compressed payload */ |
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | 112 | + uint32_t payload_size; /* LE size of the compressed payload */ |
69 | + | 113 | + uint8_t reserved1[8]; |
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | 114 | + char compression_type[32]; /* Compression type, NUL terminated */ |
71 | + (CP_REG_AA64_MASK | \ | 115 | + uint8_t linux_magic[4]; /* Linux header magic */ |
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | 116 | + uint32_t pe_header_offset; /* LE offset to the PE header */ |
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | 117 | +}; |
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | 118 | + |
79 | +/* | 119 | +/* |
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | 120 | + * Check whether *buffer points to a Linux EFI zboot image in memory. |
81 | + * version used as a key for the coprocessor register hashtable | 121 | + * |
122 | + * If it does, attempt to decompress it to a new buffer, and free the old one. | ||
123 | + * If any of this fails, return an error to the caller. | ||
124 | + * | ||
125 | + * If the image is not a Linux EFI zboot image, do nothing and return success. | ||
82 | + */ | 126 | + */ |
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | 127 | +ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size) |
84 | +{ | 128 | +{ |
85 | + uint32_t cpregid = kvmid; | 129 | + const struct linux_efi_zboot_header *header; |
86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | 130 | + uint8_t *data = NULL; |
87 | + cpregid |= CP_REG_AA64_MASK; | 131 | + int ploff, plsize; |
88 | + } else { | 132 | + ssize_t bytes; |
89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | 133 | + |
93 | + /* | 134 | + /* ignore if this is too small to be a EFI zboot image */ |
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | 135 | + if (*size < sizeof(*header)) { |
95 | + * entries. | 136 | + return 0; |
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | 137 | + } |
99 | + return cpregid; | ||
100 | +} | ||
101 | + | 138 | + |
102 | +/* | 139 | + header = (struct linux_efi_zboot_header *)*buffer; |
103 | + * Convert a truncated 32 bit hashtable key into the full | ||
104 | + * 64 bit KVM register ID. | ||
105 | + */ | ||
106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
107 | +{ | ||
108 | + uint64_t kvmid; | ||
109 | + | 140 | + |
110 | + if (cpregid & CP_REG_AA64_MASK) { | 141 | + /* ignore if this is not a Linux EFI zboot image */ |
111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; | 142 | + if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 || |
112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | 143 | + memcmp(&header->zimg, "zimg", 4) != 0 || |
113 | + } else { | 144 | + memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) { |
114 | + kvmid = cpregid & ~(1 << 15); | 145 | + return 0; |
115 | + if (cpregid & (1 << 15)) { | ||
116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
117 | + } else { | ||
118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
119 | + } | ||
120 | + } | 146 | + } |
121 | + return kvmid; | 147 | + |
148 | + if (strcmp(header->compression_type, "gzip") != 0) { | ||
149 | + fprintf(stderr, | ||
150 | + "unable to handle EFI zboot image with \"%.*s\" compression\n", | ||
151 | + (int)sizeof(header->compression_type) - 1, | ||
152 | + header->compression_type); | ||
153 | + return -1; | ||
154 | + } | ||
155 | + | ||
156 | + ploff = ldl_le_p(&header->payload_offset); | ||
157 | + plsize = ldl_le_p(&header->payload_size); | ||
158 | + | ||
159 | + if (ploff < 0 || plsize < 0 || ploff + plsize > *size) { | ||
160 | + fprintf(stderr, "unable to handle corrupt EFI zboot image\n"); | ||
161 | + return -1; | ||
162 | + } | ||
163 | + | ||
164 | + data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES); | ||
165 | + bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize); | ||
166 | + if (bytes < 0) { | ||
167 | + fprintf(stderr, "failed to decompress EFI zboot image\n"); | ||
168 | + g_free(data); | ||
169 | + return -1; | ||
170 | + } | ||
171 | + | ||
172 | + g_free(*buffer); | ||
173 | + *buffer = g_realloc(data, bytes); | ||
174 | + *size = bytes; | ||
175 | + return bytes; | ||
122 | +} | 176 | +} |
123 | + | 177 | + |
124 | /* | 178 | /* |
125 | * Valid values for ARMCPRegInfo state field, indicating which of | 179 | * Functions for reboot-persistent memory regions. |
126 | * the AArch32 and AArch64 execution states this register is visible in. | 180 | * - used for vga bios and option roms. |
127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/cpu.h | ||
130 | +++ b/target/arm/cpu.h | ||
131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
133 | uint32_t cur_el, bool secure); | ||
134 | |||
135 | -/* Interface for defining coprocessor registers. | ||
136 | - * Registers are defined in tables of arm_cp_reginfo structs | ||
137 | - * which are passed to define_arm_cp_regs(). | ||
138 | - */ | ||
139 | - | ||
140 | -/* When looking up a coprocessor register we look for it | ||
141 | - * via an integer which encodes all of: | ||
142 | - * coprocessor number | ||
143 | - * Crn, Crm, opc1, opc2 fields | ||
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
145 | - * or via MRRC/MCRR?) | ||
146 | - * non-secure/secure bank (AArch32 only) | ||
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
148 | - * (In this case crn and opc2 should be zero.) | ||
149 | - * For AArch64, there is no 32/64 bit size distinction; | ||
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
152 | - * to be easy to convert to and from the KVM encodings, and also | ||
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
188 | -{ | ||
189 | - uint32_t cpregid = kvmid; | ||
190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
191 | - cpregid |= CP_REG_AA64_MASK; | ||
192 | - } else { | ||
193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
201 | - } | ||
202 | - return cpregid; | ||
203 | -} | ||
204 | - | ||
205 | -/* Convert a truncated 32 bit hashtable key into the full | ||
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
209 | -{ | ||
210 | - uint64_t kvmid; | ||
211 | - | ||
212 | - if (cpregid & CP_REG_AA64_MASK) { | ||
213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
215 | - } else { | ||
216 | - kvmid = cpregid & ~(1 << 15); | ||
217 | - if (cpregid & (1 << 15)) { | ||
218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
219 | - } else { | ||
220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
221 | - } | ||
222 | - } | ||
223 | - return kvmid; | ||
224 | -} | ||
225 | - | ||
226 | /* Return the highest implemented Exception Level */ | ||
227 | static inline int arm_highest_el(CPUARMState *env) | ||
228 | { | ||
229 | -- | 181 | -- |
230 | 2.34.1 | 182 | 2.34.1 |
231 | 183 | ||
232 | 184 | diff view generated by jsdifflib |
1 | From: Mostafa Saleh <smostafa@google.com> | 1 | From: qianfan Zhao <qianfanguijin@163.com> |
---|---|---|---|
2 | 2 | ||
3 | GBPA register can be used to globally abort all | 3 | TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect) |
4 | transactions. | 4 | register on SUN6i based SoCs, we should lower interrupt when the guest |
5 | set this bit. | ||
5 | 6 | ||
6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". | 7 | The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no |
7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to | 8 | device connected on the i2c bus, next is the trace log: |
8 | be zero(Do not abort incoming transactions). | ||
9 | 9 | ||
10 | Other fields have default values of Use Incoming. | 10 | allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN |
11 | allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN | ||
12 | allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN | ||
13 | allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK | ||
14 | allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN | ||
15 | allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
16 | allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
17 | allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE | ||
18 | allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN | ||
19 | allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
20 | allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN | ||
21 | allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE | ||
22 | ... | ||
11 | 23 | ||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | 24 | Fix it. |
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | 25 | ||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | 26 | Signed-off-by: qianfan Zhao <qianfanguijin@163.com> |
16 | in a new subsection for forward migration compatibility. | 27 | Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> |
17 | GBPA is only migrated if its value is different from the reset value. | 28 | Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> |
18 | It does this to be backward migration compatible if SW didn't write | ||
19 | the register. | ||
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | --- | 31 | --- |
28 | hw/arm/smmuv3-internal.h | 7 +++++++ | 32 | include/hw/i2c/allwinner-i2c.h | 6 ++++++ |
29 | include/hw/arm/smmuv3.h | 1 + | 33 | hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++-- |
30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- | 34 | 2 files changed, 30 insertions(+), 2 deletions(-) |
31 | 3 files changed, 50 insertions(+), 1 deletion(-) | ||
32 | 35 | ||
33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | 36 | diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h |
34 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/hw/arm/smmuv3-internal.h | 38 | --- a/include/hw/i2c/allwinner-i2c.h |
36 | +++ b/hw/arm/smmuv3-internal.h | 39 | +++ b/include/hw/i2c/allwinner-i2c.h |
37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) | 40 | @@ -XXX,XX +XXX,XX @@ |
38 | REG32(CR1, 0x28) | 41 | #include "qom/object.h" |
39 | REG32(CR2, 0x2c) | 42 | |
40 | REG32(STATUSR, 0x40) | 43 | #define TYPE_AW_I2C "allwinner.i2c" |
41 | +REG32(GBPA, 0x44) | ||
42 | + FIELD(GBPA, ABORT, 20, 1) | ||
43 | + FIELD(GBPA, UPDATE, 31, 1) | ||
44 | + | 44 | + |
45 | +/* Use incoming. */ | 45 | +/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */ |
46 | +#define SMMU_GBPA_RESET_VAL 0x1000 | 46 | +#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i" |
47 | + | 47 | + |
48 | REG32(IRQ_CTRL, 0x50) | 48 | OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C) |
49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) | 49 | |
50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) | 50 | #define AW_I2C_MEM_SIZE 0x24 |
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | 51 | @@ -XXX,XX +XXX,XX @@ struct AWI2CState { |
52 | uint8_t srst; | ||
53 | uint8_t efr; | ||
54 | uint8_t lcr; | ||
55 | + | ||
56 | + bool irq_clear_inverted; | ||
57 | }; | ||
58 | |||
59 | #endif /* ALLWINNER_I2C_H */ | ||
60 | diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | 61 | index XXXXXXX..XXXXXXX 100644 |
53 | --- a/include/hw/arm/smmuv3.h | 62 | --- a/hw/i2c/allwinner-i2c.c |
54 | +++ b/include/hw/arm/smmuv3.h | 63 | +++ b/hw/i2c/allwinner-i2c.c |
55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { | 64 | @@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset, |
56 | uint32_t cr[3]; | 65 | s->stat = STAT_FROM_STA(STAT_IDLE); |
57 | uint32_t cr0ack; | 66 | s->cntr &= ~TWI_CNTR_M_STP; |
58 | uint32_t statusr; | 67 | } |
59 | + uint32_t gbpa; | 68 | - if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) { |
60 | uint32_t irq_ctrl; | 69 | - /* Interrupt flag cleared */ |
61 | uint32_t gerror; | 70 | + |
62 | uint32_t gerrorn; | 71 | + if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) { |
63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | 72 | + /* Write 0 to clear this flag */ |
64 | index XXXXXXX..XXXXXXX 100644 | 73 | + qemu_irq_lower(s->irq); |
65 | --- a/hw/arm/smmuv3.c | 74 | + } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) { |
66 | +++ b/hw/arm/smmuv3.c | 75 | + /* Write 1 to clear this flag */ |
67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | 76 | + s->cntr &= ~TWI_CNTR_INT_FLAG; |
68 | s->gerror = 0; | 77 | qemu_irq_lower(s->irq); |
69 | s->gerrorn = 0; | 78 | } |
70 | s->statusr = 0; | 79 | + |
71 | + s->gbpa = SMMU_GBPA_RESET_VAL; | 80 | if ((s->cntr & TWI_CNTR_A_ACK) == 0) { |
72 | } | 81 | if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { |
73 | 82 | s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); | |
74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | 83 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = { |
75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | 84 | .class_init = allwinner_i2c_class_init, |
76 | qemu_mutex_lock(&s->mutex); | ||
77 | |||
78 | if (!smmu_enabled(s)) { | ||
79 | - status = SMMU_TRANS_DISABLE; | ||
80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { | ||
81 | + status = SMMU_TRANS_ABORT; | ||
82 | + } else { | ||
83 | + status = SMMU_TRANS_DISABLE; | ||
84 | + } | ||
85 | goto epilogue; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | ||
89 | case A_GERROR_IRQ_CFG2: | ||
90 | s->gerror_irq_cfg2 = data; | ||
91 | return MEMTX_OK; | ||
92 | + case A_GBPA: | ||
93 | + /* | ||
94 | + * If UPDATE is not set, the write is ignored. This is the only | ||
95 | + * permitted behavior in SMMUv3.2 and later. | ||
96 | + */ | ||
97 | + if (data & R_GBPA_UPDATE_MASK) { | ||
98 | + /* Ignore update bit as write is synchronous. */ | ||
99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; | ||
100 | + } | ||
101 | + return MEMTX_OK; | ||
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
116 | }, | ||
117 | }; | 85 | }; |
118 | 86 | ||
119 | +static bool smmuv3_gbpa_needed(void *opaque) | 87 | +static void allwinner_i2c_sun6i_init(Object *obj) |
120 | +{ | 88 | +{ |
121 | + SMMUv3State *s = opaque; | 89 | + AWI2CState *s = AW_I2C(obj); |
122 | + | 90 | + |
123 | + /* Only migrate GBPA if it has different reset value. */ | 91 | + s->irq_clear_inverted = true; |
124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; | ||
125 | +} | 92 | +} |
126 | + | 93 | + |
127 | +static const VMStateDescription vmstate_gbpa = { | 94 | +static const TypeInfo allwinner_i2c_sun6i_type_info = { |
128 | + .name = "smmuv3/gbpa", | 95 | + .name = TYPE_AW_I2C_SUN6I, |
129 | + .version_id = 1, | 96 | + .parent = TYPE_SYS_BUS_DEVICE, |
130 | + .minimum_version_id = 1, | 97 | + .instance_size = sizeof(AWI2CState), |
131 | + .needed = smmuv3_gbpa_needed, | 98 | + .instance_init = allwinner_i2c_sun6i_init, |
132 | + .fields = (VMStateField[]) { | 99 | + .class_init = allwinner_i2c_class_init, |
133 | + VMSTATE_UINT32(gbpa, SMMUv3State), | ||
134 | + VMSTATE_END_OF_LIST() | ||
135 | + } | ||
136 | +}; | 100 | +}; |
137 | + | 101 | + |
138 | static const VMStateDescription vmstate_smmuv3 = { | 102 | static void allwinner_i2c_register_types(void) |
139 | .name = "smmuv3", | 103 | { |
140 | .version_id = 1, | 104 | type_register_static(&allwinner_i2c_type_info); |
141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { | 105 | + type_register_static(&allwinner_i2c_sun6i_type_info); |
142 | 106 | } | |
143 | VMSTATE_END_OF_LIST(), | 107 | |
144 | }, | 108 | type_init(allwinner_i2c_register_types) |
145 | + .subsections = (const VMStateDescription * []) { | ||
146 | + &vmstate_gbpa, | ||
147 | + NULL | ||
148 | + } | ||
149 | }; | ||
150 | |||
151 | static void smmuv3_instance_init(Object *obj) | ||
152 | -- | 109 | -- |
153 | 2.34.1 | 110 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Cornelia Huck <cohuck@redhat.com> | ||
2 | 1 | ||
3 | Just use current_accel_name() directly. | ||
4 | |||
5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> | ||
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/virt.c | 6 +++--- | ||
11 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/virt.c | ||
16 | +++ b/hw/arm/virt.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { | ||
19 | error_report("mach-virt: %s does not support providing " | ||
20 | "Security extensions (TrustZone) to the guest CPU", | ||
21 | - kvm_enabled() ? "KVM" : "HVF"); | ||
22 | + current_accel_name()); | ||
23 | exit(1); | ||
24 | } | ||
25 | |||
26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { | ||
27 | error_report("mach-virt: %s does not support providing " | ||
28 | "Virtualization extensions to the guest CPU", | ||
29 | - kvm_enabled() ? "KVM" : "HVF"); | ||
30 | + current_accel_name()); | ||
31 | exit(1); | ||
32 | } | ||
33 | |||
34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { | ||
35 | error_report("mach-virt: %s does not support providing " | ||
36 | "MTE to the guest CPU", | ||
37 | - kvm_enabled() ? "KVM" : "HVF"); | ||
38 | + current_accel_name()); | ||
39 | exit(1); | ||
40 | } | ||
41 | |||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
2 | 1 | ||
3 | Havard is no longer working on the Nuvoton systems for a while | ||
4 | and won't be able to do any work on it in the future. So I'll | ||
5 | take over maintaining the Nuvoton system from him. | ||
6 | |||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/MAINTAINERS | ||
19 | +++ b/MAINTAINERS | ||
20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h | ||
21 | F: docs/system/arm/musicpal.rst | ||
22 | |||
23 | Nuvoton NPCM7xx | ||
24 | -M: Havard Skinnemoen <hskinnemoen@google.com> | ||
25 | M: Tyrone Ting <kfting@nuvoton.com> | ||
26 | +M: Hao Wu <wuhaotsh@google.com> | ||
27 | L: qemu-arm@nongnu.org | ||
28 | S: Supported | ||
29 | F: hw/*/npcm7xx* | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
2 | 1 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/smmu-common.h | 2 -- | ||
13 | hw/arm/smmu-common.c | 2 +- | ||
14 | 2 files changed, 1 insertion(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/smmu-common.h | ||
19 | +++ b/include/hw/arm/smmu-common.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define SMMU_PCI_DEVFN_MAX 256 | ||
22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) | ||
23 | |||
24 | -#define SMMU_MAX_VA_BITS 48 | ||
25 | - | ||
26 | /* | ||
27 | * Page table walk error types | ||
28 | */ | ||
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/smmu-common.c | ||
32 | +++ b/hw/arm/smmu-common.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
34 | |||
35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | ||
36 | s->mrtypename, | ||
37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); | ||
38 | + OBJECT(s), name, UINT64_MAX); | ||
39 | address_space_init(&sdev->as, | ||
40 | MEMORY_REGION(&sdev->iommu), name); | ||
41 | trace_smmu_add_mr(name); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Claudio Fontana <cfontana@suse.de> | ||
2 | 1 | ||
3 | for "all" builds (tcg + kvm), we want to avoid doing | ||
4 | the psci check if tcg is built-in, but not enabled. | ||
5 | |||
6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/helper.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper.c | ||
18 | +++ b/target/arm/helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | #include "hw/irq.h" | ||
21 | #include "sysemu/cpu-timers.h" | ||
22 | #include "sysemu/kvm.h" | ||
23 | +#include "sysemu/tcg.h" | ||
24 | #include "qapi/qapi-commands-machine-target.h" | ||
25 | #include "qapi/error.h" | ||
26 | #include "qemu/guest-random.h" | ||
27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
28 | env->exception.syndrome); | ||
29 | } | ||
30 | |||
31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { | ||
32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { | ||
33 | arm_handle_psci_call(cpu); | ||
34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); | ||
35 | return; | ||
36 | -- | ||
37 | 2.34.1 | ||
38 | |||
39 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
2 | 1 | ||
3 | Move this earlier to make the next patch diff cleaner. While here | ||
4 | update the comment slightly to not give the impression that the | ||
5 | misalignment affects only TCG. | ||
6 | |||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/machine.c | 18 +++++++++--------- | ||
14 | 1 file changed, 9 insertions(+), 9 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/machine.c | ||
19 | +++ b/target/arm/machine.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
21 | } | ||
22 | } | ||
23 | |||
24 | + /* | ||
25 | + * Misaligned thumb pc is architecturally impossible. Fail the | ||
26 | + * incoming migration. For TCG it would trigger the assert in | ||
27 | + * thumb_tr_translate_insn(). | ||
28 | + */ | ||
29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
30 | + return -1; | ||
31 | + } | ||
32 | + | ||
33 | hw_breakpoint_update_all(cpu); | ||
34 | hw_watchpoint_update_all(cpu); | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
37 | } | ||
38 | } | ||
39 | |||
40 | - /* | ||
41 | - * Misaligned thumb pc is architecturally impossible. | ||
42 | - * We have an assert in thumb_tr_translate_insn to verify this. | ||
43 | - * Fail an incoming migrate to avoid this assert. | ||
44 | - */ | ||
45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { | ||
46 | - return -1; | ||
47 | - } | ||
48 | - | ||
49 | if (!kvm_enabled()) { | ||
50 | pmu_op_finish(&cpu->env); | ||
51 | } | ||
52 | -- | ||
53 | 2.34.1 | ||
54 | |||
55 | diff view generated by jsdifflib |
1 | From: Fabiano Rosas <farosas@suse.de> | 1 | From: qianfan Zhao <qianfanguijin@163.com> |
---|---|---|---|
2 | 2 | ||
3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a | 3 | Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. |
4 | KVM-only build the 'max' cpu. | 4 | The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear |
5 | control register's INT_FLAG bit. | ||
5 | 6 | ||
6 | Note that we cannot use 'host' here because the qtests can run without | 7 | Signed-off-by: qianfan Zhao <qianfanguijin@163.com> |
7 | any other accelerator (than qtest) and 'host' depends on KVM being | 8 | Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> |
8 | enabled. | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 11 | --- |
15 | hw/arm/virt.c | 4 ++++ | 12 | include/hw/arm/allwinner-h3.h | 6 ++++++ |
16 | 1 file changed, 4 insertions(+) | 13 | hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++---- |
14 | 2 files changed, 31 insertions(+), 4 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 16 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/virt.c | 18 | --- a/include/hw/arm/allwinner-h3.h |
21 | +++ b/hw/arm/virt.c | 19 | +++ b/include/hw/arm/allwinner-h3.h |
22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 20 | @@ -XXX,XX +XXX,XX @@ enum { |
23 | mc->minimum_page_bits = 12; | 21 | AW_H3_DEV_UART3, |
24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; | 22 | AW_H3_DEV_EMAC, |
25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | 23 | AW_H3_DEV_TWI0, |
26 | +#ifdef CONFIG_TCG | 24 | + AW_H3_DEV_TWI1, |
27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | 25 | + AW_H3_DEV_TWI2, |
28 | +#else | 26 | AW_H3_DEV_DRAMCOM, |
29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); | 27 | AW_H3_DEV_DRAMCTL, |
30 | +#endif | 28 | AW_H3_DEV_DRAMPHY, |
31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | 29 | @@ -XXX,XX +XXX,XX @@ enum { |
32 | mc->kvm_type = virt_kvm_type; | 30 | AW_H3_DEV_GIC_VCPU, |
33 | assert(!mc->get_hotplug_handler); | 31 | AW_H3_DEV_RTC, |
32 | AW_H3_DEV_CPUCFG, | ||
33 | + AW_H3_DEV_R_TWI, | ||
34 | AW_H3_DEV_SDRAM | ||
35 | }; | ||
36 | |||
37 | @@ -XXX,XX +XXX,XX @@ struct AwH3State { | ||
38 | AwSidState sid; | ||
39 | AwSdHostState mmc0; | ||
40 | AWI2CState i2c0; | ||
41 | + AWI2CState i2c1; | ||
42 | + AWI2CState i2c2; | ||
43 | + AWI2CState r_twi; | ||
44 | AwSun8iEmacState emac; | ||
45 | AwRtcState rtc; | ||
46 | GICState gic; | ||
47 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/arm/allwinner-h3.c | ||
50 | +++ b/hw/arm/allwinner-h3.c | ||
51 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
52 | [AW_H3_DEV_UART2] = 0x01c28800, | ||
53 | [AW_H3_DEV_UART3] = 0x01c28c00, | ||
54 | [AW_H3_DEV_TWI0] = 0x01c2ac00, | ||
55 | + [AW_H3_DEV_TWI1] = 0x01c2b000, | ||
56 | + [AW_H3_DEV_TWI2] = 0x01c2b400, | ||
57 | [AW_H3_DEV_EMAC] = 0x01c30000, | ||
58 | [AW_H3_DEV_DRAMCOM] = 0x01c62000, | ||
59 | [AW_H3_DEV_DRAMCTL] = 0x01c63000, | ||
60 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | ||
61 | [AW_H3_DEV_GIC_VCPU] = 0x01c86000, | ||
62 | [AW_H3_DEV_RTC] = 0x01f00000, | ||
63 | [AW_H3_DEV_CPUCFG] = 0x01f01c00, | ||
64 | + [AW_H3_DEV_R_TWI] = 0x01f02400, | ||
65 | [AW_H3_DEV_SDRAM] = 0x40000000 | ||
66 | }; | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
69 | { "uart1", 0x01c28400, 1 * KiB }, | ||
70 | { "uart2", 0x01c28800, 1 * KiB }, | ||
71 | { "uart3", 0x01c28c00, 1 * KiB }, | ||
72 | - { "twi1", 0x01c2b000, 1 * KiB }, | ||
73 | - { "twi2", 0x01c2b400, 1 * KiB }, | ||
74 | { "scr", 0x01c2c400, 1 * KiB }, | ||
75 | { "gpu", 0x01c40000, 64 * KiB }, | ||
76 | { "hstmr", 0x01c60000, 4 * KiB }, | ||
77 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
78 | { "r_prcm", 0x01f01400, 1 * KiB }, | ||
79 | { "r_twd", 0x01f01800, 1 * KiB }, | ||
80 | { "r_cir-rx", 0x01f02000, 1 * KiB }, | ||
81 | - { "r_twi", 0x01f02400, 1 * KiB }, | ||
82 | { "r_uart", 0x01f02800, 1 * KiB }, | ||
83 | { "r_pio", 0x01f02c00, 1 * KiB }, | ||
84 | { "r_pwm", 0x01f03800, 1 * KiB }, | ||
85 | @@ -XXX,XX +XXX,XX @@ enum { | ||
86 | AW_H3_GIC_SPI_UART2 = 2, | ||
87 | AW_H3_GIC_SPI_UART3 = 3, | ||
88 | AW_H3_GIC_SPI_TWI0 = 6, | ||
89 | + AW_H3_GIC_SPI_TWI1 = 7, | ||
90 | + AW_H3_GIC_SPI_TWI2 = 8, | ||
91 | AW_H3_GIC_SPI_TIMER0 = 18, | ||
92 | AW_H3_GIC_SPI_TIMER1 = 19, | ||
93 | + AW_H3_GIC_SPI_R_TWI = 44, | ||
94 | AW_H3_GIC_SPI_MMC0 = 60, | ||
95 | AW_H3_GIC_SPI_EHCI0 = 72, | ||
96 | AW_H3_GIC_SPI_OHCI0 = 73, | ||
97 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
98 | |||
99 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I); | ||
100 | |||
101 | - object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C); | ||
102 | + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); | ||
103 | + object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I); | ||
104 | + object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I); | ||
105 | + object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I); | ||
106 | } | ||
107 | |||
108 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
109 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
110 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, | ||
111 | qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0)); | ||
112 | |||
113 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal); | ||
114 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]); | ||
115 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0, | ||
116 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1)); | ||
117 | + | ||
118 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal); | ||
119 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]); | ||
120 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0, | ||
121 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2)); | ||
122 | + | ||
123 | + sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal); | ||
124 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]); | ||
125 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0, | ||
126 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI)); | ||
127 | + | ||
128 | /* Unimplemented devices */ | ||
129 | for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | ||
130 | create_unimplemented_device(unimplemented[i].device_name, | ||
34 | -- | 131 | -- |
35 | 2.34.1 | 132 | 2.34.1 | diff view generated by jsdifflib |