On Tue, Feb 14, 2023 at 04:23:45PM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> This new version contains suggestions made by Weiwei Li in v1. Most
> notable change is patch 4 from v1, moving up to patch 2 now, to allow
> the riscv_cpu_cfg() helper to be used in the MISA CSR patch.
>
>
> Changes in v2:
> - former patch 4 moved to patch 2
> - patch 3 (former 2):
> - use riscv_cpu_cfg()
> - patch 9:
> - remove the uneeded RISCVCPUConfig and access mmu via
> cpu_cfg->cfg.mmu
> - v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg02780.html
>
> Daniel Henrique Barboza (11):
> target/riscv: do not mask unsupported QEMU extensions in write_misa()
> target/riscv: introduce riscv_cpu_cfg()
> target/riscv: allow users to actually write the MISA CSR
> target/riscv: remove RISCV_FEATURE_MISA
> target/riscv: remove RISCV_FEATURE_DEBUG
> target/riscv/cpu.c: error out if EPMP is enabled without PMP
> target/riscv: remove RISCV_FEATURE_EPMP
> target/riscv: remove RISCV_FEATURE_PMP
> hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in
> create_fdt_socket_cpus()
> target/riscv: remove RISCV_FEATURE_MMU
> target/riscv/cpu: remove CPUArchState::features and friends
>
> hw/riscv/virt.c | 7 ++++---
> target/riscv/cpu.c | 20 +++++---------------
> target/riscv/cpu.h | 29 ++++++-----------------------
> target/riscv/cpu_helper.c | 6 +++---
> target/riscv/csr.c | 15 ++++++---------
> target/riscv/machine.c | 11 ++++-------
> target/riscv/monitor.c | 2 +-
> target/riscv/op_helper.c | 2 +-
> target/riscv/pmp.c | 8 ++++----
> 9 files changed, 34 insertions(+), 66 deletions(-)
>
> --
> 2.39.1
>
>
For the series
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>