On Wed, Feb 15, 2023 at 08:32:39PM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 20:32:39 +0800
> From: "wangyanan (Y)" <wangyanan55@huawei.com>
> Subject: Re: [PATCH RESEND 16/18] i386: Fix NumSharingCache for
> CPUID[0x8000001D].EAX[bits 25:14]
>
> 在 2023/2/13 17:36, Zhao Liu 写道:
> > From: Zhao Liu <zhao1.liu@intel.com>
> >
> > >From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14])
> > means [1]:
> >
> > The number of logical processors sharing this cache is the value of
> > this field incremented by 1. To determine which logical processors are
> > sharing a cache, determine a Share Id for each processor as follows:
> >
> > ShareId = LocalApicId >> log2(NumSharingCache+1)
> >
> > Logical processors with the same ShareId then share a cache. If
> > NumSharingCache+1 is not a power of two, round it up to the next power
> > of two.
> >
> > >From the description above, the caculation of this feild should be same
> > as CPUID[4].EAX[bits 25:14] for intel cpus. So also use the offsets of
> > APIC ID to caculate this field.
> >
> > Note: I don't have the hardware available, hope someone can help me to
> > confirm whether this calculation is correct, thanks!
> >
> > [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology
> > Information
> >
> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> > ---
> > target/i386/cpu.c | 10 ++++------
> > 1 file changed, 4 insertions(+), 6 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 96ef96860604..d691c02e3c06 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -355,7 +355,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
> > uint32_t *eax, uint32_t *ebx,
> > uint32_t *ecx, uint32_t *edx)
> > {
> > - uint32_t l3_threads;
> > + uint32_t sharing_apic_ids;
> maybe num_apic_ids or num_ids？
Thanks, num is better as a prefix. I would use num_apic_ids.
Zhao
> > assert(cache->size == cache->line_size * cache->associativity *
> > cache->partitions * cache->sets);
> > @@ -364,13 +364,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
> > /* L3 is shared among multiple cores */
> > if (cache->level == 3) {
> > - l3_threads = topo_info->modules_per_die *
> > - topo_info->cores_per_module *
> > - topo_info->threads_per_core;
> > - *eax |= (l3_threads - 1) << 14;
> > + sharing_apic_ids = 1 << apicid_die_offset(topo_info);
> > } else {
> > - *eax |= ((topo_info->threads_per_core - 1) << 14);
> > + sharing_apic_ids = 1 << apicid_core_offset(topo_info);
> > }
> > + *eax |= (sharing_apic_ids - 1) << 14;
> > assert(cache->line_size > 0);
> > assert(cache->partitions > 0);
>