[PULL 00/25] aspeed queue
[PULL 0/3] aspeed queue
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The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:
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The following changes since commit 527dede083d3e3e5a13ee996776926e0a0c4e258:
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Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)
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Merge tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu into staging (2025-03-20 08:41:25 -0400)
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are available in the Git repository at:
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are available in the Git repository at:
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https://github.com/legoater/qemu/ tags/pull-aspeed-20230207
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https://github.com/legoater/qemu/ tags/pull-aspeed-20250323
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8
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for you to fetch changes up to bf81b8f8acda4f1f774adc5f8e76225d472c6ae5:
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for you to fetch changes up to 78877b2e06464f49f777e086845e094ea7bc82ef:
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aspeed/sdmc: Drop unnecessary scu include (2023-02-07 09:02:05 +0100)
11
hw/misc/aspeed_hace: Fix buffer overflow in has_padding function (2025-03-23 18:42:16 +0100)
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
aspeed queue:
14
aspeed queue:
15
15
16
* various small cleanups and fixes
16
* Fix AST2700 SoC model
17
* new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC
18
* at24c_eeprom extension to define eeprom contents with static arrays
19
* ast10x0 model and test improvements
20
* avocado update of images to use the latest
21
17
22
----------------------------------------------------------------
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----------------------------------------------------------------
23
Cédric Le Goater (3):
19
Jamin Lin (1):
24
tests/avocado/machine_aspeed.py: update buildroot tests
20
hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
25
tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
26
hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
27
21
28
Guenter Roeck (2):
22
Steven Lee (1):
29
aspeed: Add Supermicro X11 SPI machine type
23
hw/intc/aspeed: Fix IRQ handler mask check
30
m25p80: Add the is25wp256 SFPD table
31
24
32
Joel Stanley (2):
25
Troy Lee (1):
33
avocado/boot_linux_console.py: Update ast2600 test
26
aspeed: Fix maximum number of spi controller
34
aspeed/sdmc: Drop unnecessary scu include
35
27
36
Peter Delevoryas (5):
28
include/hw/arm/aspeed_soc.h | 2 +-
37
hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
29
hw/intc/aspeed_intc.c | 2 +-
38
hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
30
hw/misc/aspeed_hace.c | 5 +++++
39
hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
31
3 files changed, 7 insertions(+), 2 deletions(-)
40
hw/arm/aspeed: Add aspeed_eeprom.c
41
hw/nvram/eeprom_at24c: Make reset behavior more like hardware
42
43
Philippe Mathieu-Daudé (12):
44
tests/avocado: Introduce file_truncate()
45
tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiB
46
hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
47
hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
48
hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
49
hw/misc/aspeed_hace: Do not crash if address_space_map() failed
50
hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
51
hw/arm/aspeed_ast10x0: Map I3C peripheral
52
hw/arm/aspeed_ast10x0: Map the secure SRAM
53
hw/arm/aspeed_ast10x0: Map HACE peripheral
54
hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
55
tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
56
57
Stephen Longfield (1):
58
hw/net: Fix read of uninitialized memory in ftgmac100
59
60
hw/arm/aspeed_eeprom.h | 19 +++++
61
hw/block/m25p80_sfdp.h | 2 +
62
include/hw/arm/aspeed_soc.h | 14 ++++
63
include/hw/loader.h | 3 -
64
include/hw/nvram/eeprom_at24c.h | 39 ++++++++++
65
include/hw/watchdog/wdt_aspeed.h | 4 +-
66
hw/arm/aspeed.c | 142 ++++++++++++++++++++----------------
67
hw/arm/aspeed_ast10x0.c | 83 ++++++++++++++++++++-
68
hw/arm/aspeed_ast2600.c | 4 +-
69
hw/arm/aspeed_eeprom.c | 82 +++++++++++++++++++++
70
hw/arm/aspeed_soc.c | 4 +-
71
hw/arm/msf2-som.c | 5 +-
72
hw/arm/npcm7xx_boards.c | 20 ++---
73
hw/block/m25p80.c | 3 +-
74
hw/block/m25p80_sfdp.c | 40 ++++++++++
75
hw/misc/aspeed_hace.c | 21 ++++--
76
hw/misc/aspeed_sdmc.c | 1 -
77
hw/net/ftgmac100.c | 4 +-
78
hw/nvram/eeprom_at24c.c | 58 ++++++++++++---
79
hw/watchdog/wdt_aspeed.c | 24 ++++--
80
hw/arm/meson.build | 1 +
81
tests/avocado/boot_linux_console.py | 19 +++--
82
tests/avocado/machine_aspeed.py | 60 +++++++++++++--
83
23 files changed, 523 insertions(+), 129 deletions(-)
84
create mode 100644 hw/arm/aspeed_eeprom.h
85
create mode 100644 include/hw/nvram/eeprom_at24c.h
86
create mode 100644 hw/arm/aspeed_eeprom.c
87
diff view generated by jsdifflib
[PULL 01/25] tests/avocado: Introduce file_truncate()
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Link: https://lore.kernel.org/r/20230120134314.81956-2-philmd@linaro.org
5
[ clg: remove image_pow2ceil_expand() factoring ]
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
---
8
tests/avocado/boot_linux_console.py | 5 +++++
9
1 file changed, 5 insertions(+)
10
11
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/avocado/boot_linux_console.py
14
+++ b/tests/avocado/boot_linux_console.py
15
@@ -XXX,XX +XXX,XX @@
16
def pow2ceil(x):
17
return 1 if x == 0 else 2**(x - 1).bit_length()
18
19
+def file_truncate(path, size):
20
+ if size != os.path.getsize(path):
21
+ with open(path, 'ab+') as fd:
22
+ fd.truncate(size)
23
+
24
"""
25
Expand file size to next power of 2
26
"""
27
--
28
2.39.1
29
30
diff view generated by jsdifflib
[PULL 02/25] tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiB
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
The M2S-FG484 SOM uses a 16 MiB SPI flash (Spansion
4
S25FL128SDPBHICO). Since the test asset is bigger,
5
truncate it to the correct size to avoid when running
6
the test_arm_emcraft_sf2 test:
7
8
qemu-system-arm: device requires 16777216 bytes, block backend provides 67108864 bytes
9
10
Add comment regarding the M2S-FG484 SOM hardware in
11
hw/arm/msf2-som.c.
12
13
Reported-by: Cédric Le Goater <clg@kaod.org>
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Reviewed-by: Cédric Le Goater <clg@kaod.org>
16
Tested-by: Cédric Le Goater <clg@kaod.org>
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
---
19
hw/arm/msf2-som.c | 5 ++++-
20
tests/avocado/boot_linux_console.py | 2 ++
21
2 files changed, 6 insertions(+), 1 deletion(-)
22
23
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/msf2-som.c
26
+++ b/hw/arm/msf2-som.c
27
@@ -XXX,XX +XXX,XX @@
28
/*
29
* SmartFusion2 SOM starter kit(from Emcraft) emulation.
30
*
31
+ * M2S-FG484 SOM hardware architecture specification:
32
+ * https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
33
+ *
34
* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
35
*
36
* Permission is hereby granted, free of charge, to any person obtaining a copy
37
@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
38
39
/* Attach SPI flash to SPI0 controller */
40
spi_bus = qdev_get_child_bus(dev, "spi0");
41
- spi_flash = qdev_new("s25sl12801");
42
+ spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */
43
qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
44
if (dinfo) {
45
qdev_prop_set_drive_err(spi_flash, "drive",
46
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
47
index XXXXXXX..XXXXXXX 100644
48
--- a/tests/avocado/boot_linux_console.py
49
+++ b/tests/avocado/boot_linux_console.py
50
@@ -XXX,XX +XXX,XX @@ def test_arm_emcraft_sf2(self):
51
spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
52
spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
53
54
+ file_truncate(spi_path, 16 << 20) # Spansion S25FL128SDPBHICO is 16 MiB
55
+
56
self.vm.set_console()
57
kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE
58
self.vm.add_args('-kernel', uboot_path,
59
--
60
2.39.1
61
62
diff view generated by jsdifflib
[PULL 03/25] aspeed: Add Supermicro X11 SPI machine type
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
4
the Supermicro documentation for X11 BMCs, and it does not match the
5
devicetree file in the Linux kernel.
6
7
As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
8
while others use AST2500.
9
10
Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
11
to match the devicetree description in the Linux kernel. Hardware
12
configuration details for this machine type are guesswork and taken
13
from defaults as well as from the Linux kernel devicetree file.
14
15
The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts
16
from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2.
17
Linux booted successfully from initrd and from both SPI interfaces.
18
Ethernet interfaces were confirmed to be operational.
19
20
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
21
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
22
Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net
23
[ clg: Renamed machine to 'supermicro-x11spi-bmc' ]
24
Message-Id: <20221025165109.1226001-1-linux@roeck-us.net>
25
Signed-off-by: Cédric Le Goater <clg@kaod.org>
26
---
27
hw/arm/aspeed.c | 33 +++++++++++++++++++++++++++++++++
28
1 file changed, 33 insertions(+)
29
30
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/aspeed.c
33
+++ b/hw/arm/aspeed.c
34
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
35
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
36
SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
37
38
+/* TODO: Find the actual hardware value */
39
+#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \
40
+ AST2500_HW_STRAP1_DEFAULTS | \
41
+ SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
42
+ SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
43
+ SCU_AST2500_HW_STRAP_UART_DEBUG | \
44
+ SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
45
+ SCU_HW_STRAP_SPI_WIDTH | \
46
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
47
+
48
/* AST2500 evb hardware value: 0xF100C2E6 */
49
#define AST2500_EVB_HW_STRAP1 (( \
50
AST2500_HW_STRAP1_DEFAULTS | \
51
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
52
mc->default_ram_size = 256 * MiB;
53
}
54
55
+static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
56
+ void *data)
57
+{
58
+ MachineClass *mc = MACHINE_CLASS(oc);
59
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
60
+
61
+ mc->desc = "Supermicro X11 SPI BMC (ARM1176)";
62
+ amc->soc_name = "ast2500-a1";
63
+ amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
64
+ amc->fmc_model = "mx25l25635e";
65
+ amc->spi_model = "mx25l25635e";
66
+ amc->num_cs = 1;
67
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
68
+ amc->i2c_init = palmetto_bmc_i2c_init;
69
+ mc->default_ram_size = 512 * MiB;
70
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
71
+ aspeed_soc_num_cpus(amc->soc_name);
72
+}
73
+
74
static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
75
{
76
MachineClass *mc = MACHINE_CLASS(oc);
77
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
78
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
79
.parent = TYPE_ASPEED_MACHINE,
80
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
81
+ }, {
82
+ .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
83
+ .parent = TYPE_ASPEED_MACHINE,
84
+ .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
85
}, {
86
.name = MACHINE_TYPE_NAME("ast2500-evb"),
87
.parent = TYPE_ASPEED_MACHINE,
88
--
89
2.39.1
90
91
diff view generated by jsdifflib
[PULL 04/25] hw/net: Fix read of uninitialized memory in ftgmac100
Deleted patch
1
From: Stephen Longfield <slongfield@google.com>
2
1
3
With the `size += 4` before the call to `crc32`, the CRC calculation
4
would overrun the buffer. Size is used in the while loop starting on
5
line 1009 to determine how much data to write back, with the last
6
four bytes coming from `crc_ptr`, so do need to increase it, but should
7
do this after the computation.
8
9
I'm unsure why this use of uninitialized memory in the CRC doesn't
10
result in CRC errors, but it seems clear to me that it should not be
11
included in the calculation.
12
13
Signed-off-by: Stephen Longfield <slongfield@google.com>
14
Reviewed-by: Hao Wu <wuhaotsh@google.com>
15
Reviewed-by: Joel Stanley <joel@jms.id.au>
16
Message-Id: <20221220221437.3303721-1-slongfield@google.com>
17
Signed-off-by: Cédric Le Goater <clg@kaod.org>
18
---
19
hw/net/ftgmac100.c | 4 ++--
20
1 file changed, 2 insertions(+), 2 deletions(-)
21
22
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/net/ftgmac100.c
25
+++ b/hw/net/ftgmac100.c
26
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
27
return size;
28
}
29
30
- /* 4 bytes for the CRC. */
31
- size += 4;
32
crc = cpu_to_be32(crc32(~0, buf, size));
33
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
34
+ size += 4;
35
crc_ptr = (uint8_t *) &crc;
36
37
/* Huge frames are truncated. */
38
--
39
2.39.1
40
41
diff view generated by jsdifflib
[PULL 05/25] avocado/boot_linux_console.py: Update ast2600 test
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
Update the test_arm_ast2600_debian test to
4
5
- the latest Debian kernel
6
- use the Rainier machine instead of Tacoma
7
8
Both of which contains support for more hardware and thus exercises more
9
of the hardware Qemu models.
10
11
Signed-off-by: Joel Stanley <joel@jms.id.au>
12
Reviewed-by: Cédric Le Goater <clg@kaod.org>
13
Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
14
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
---
16
tests/avocado/boot_linux_console.py | 12 ++++++------
17
1 file changed, 6 insertions(+), 6 deletions(-)
18
19
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
20
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/avocado/boot_linux_console.py
22
+++ b/tests/avocado/boot_linux_console.py
23
@@ -XXX,XX +XXX,XX @@ def test_arm_vexpressa9(self):
24
def test_arm_ast2600_debian(self):
25
"""
26
:avocado: tags=arch:arm
27
- :avocado: tags=machine:tacoma-bmc
28
+ :avocado: tags=machine:rainier-bmc
29
"""
30
deb_url = ('http://snapshot.debian.org/archive/debian/'
31
- '20210302T203551Z/'
32
+ '20220606T211338Z/'
33
'pool/main/l/linux/'
34
- 'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
35
- deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
36
+ 'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
37
+ deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
38
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
39
algorithm='sha256')
40
- kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
41
+ kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
42
dtb_path = self.extract_from_deb(deb_path,
43
- '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
44
+ '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
45
46
self.vm.set_console()
47
self.vm.add_args('-kernel', kernel_path,
48
--
49
2.39.1
50
51
diff view generated by jsdifflib
[PULL 06/25] m25p80: Add the is25wp256 SFPD table
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
Generated from hardware using the following command and then padding
4
with 0xff to fill out a power-of-2:
5
    xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
6
7
Cc: Michael Walle <michael@walle.cc>
8
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
9
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
11
Reviewed-by: Joel Stanley <joel@jms.id.au>
12
Message-Id: <20221221122213.1458540-1-linux@roeck-us.net>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
---
15
hw/block/m25p80_sfdp.h | 2 ++
16
hw/block/m25p80.c | 3 ++-
17
hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
18
3 files changed, 44 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/block/m25p80_sfdp.h
23
+++ b/hw/block/m25p80_sfdp.h
24
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
25
26
uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
27
28
+uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
29
+
30
#endif
31
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/block/m25p80.c
34
+++ b/hw/block/m25p80.c
35
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
36
{ INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
37
{ INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
38
{ INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
39
- { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
40
+ { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K),
41
+ .sfdp_read = m25p80_sfdp_is25wp256 },
42
43
/* Macronix */
44
{ INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
45
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/block/m25p80_sfdp.c
48
+++ b/hw/block/m25p80_sfdp.c
49
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q01jvq[] = {
50
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
51
};
52
define_sfdp_read(w25q01jvq);
53
+
54
+/*
55
+ * Integrated Silicon Solution (ISSI)
56
+ */
57
+
58
+static const uint8_t sfdp_is25wp256[] = {
59
+ 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
60
+ 0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
61
+ 0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
62
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
63
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
64
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
65
+ 0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
66
+ 0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
67
+ 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
68
+ 0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
69
+ 0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
70
+ 0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
71
+ 0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
72
+ 0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
73
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
74
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
75
+ 0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
76
+ 0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
77
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
78
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
79
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
80
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
81
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
82
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
83
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
84
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
86
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
87
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
88
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
89
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
90
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
91
+};
92
+define_sfdp_read(is25wp256);
93
--
94
2.39.1
95
96
diff view generated by jsdifflib
[PULL 07/25] tests/avocado/machine_aspeed.py: update buildroot tests
Deleted patch
1
Use buildroot 2022.11 based images plus some customization :
2
1
3
- Linux version is bumped to 6.0.9 and kernel is built with a custom
4
config similar to what OpenBMC provides.
5
- U-Boot is switched to the one provided by OpenBMC for better support.
6
- defconfigs includes more target tools for dev.
7
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Message-Id: <20230119123449.531826-7-clg@kaod.org>
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
11
---
12
tests/avocado/machine_aspeed.py | 8 ++++----
13
1 file changed, 4 insertions(+), 4 deletions(-)
14
15
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tests/avocado/machine_aspeed.py
18
+++ b/tests/avocado/machine_aspeed.py
19
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self):
20
"""
21
22
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
23
- 'images/ast2500-evb/buildroot-2022.05/flash.img')
24
- image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
25
+ 'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
26
+ image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
27
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
28
algorithm='sha256')
29
30
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
31
"""
32
33
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
34
- 'images/ast2600-evb/buildroot-2022.05/flash.img')
35
- image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
36
+ 'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
37
+ image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
38
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
39
algorithm='sha256')
40
41
--
42
2.39.1
43
44
diff view generated by jsdifflib
[PULL 08/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
Deleted patch
1
Reviewed-by: Joel Stanley <joel@jms.id.au>
2
Message-Id: <20230119123449.531826-8-clg@kaod.org>
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
---
5
tests/avocado/machine_aspeed.py | 11 +++++++++--
6
1 file changed, 9 insertions(+), 2 deletions(-)
7
1
8
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tests/avocado/machine_aspeed.py
11
+++ b/tests/avocado/machine_aspeed.py
12
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
13
14
class AST2x00MachineSDK(QemuSystemTest):
15
16
- EXTRA_BOOTARGS = ' quiet'
17
+ EXTRA_BOOTARGS = (
18
+ 'quiet '
19
+ 'systemd.mask=org.openbmc.HostIpmi.service '
20
+ 'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
21
+ 'systemd.mask=modprobe@fuse.service '
22
+ 'systemd.mask=rngd.service '
23
+ 'systemd.mask=obmc-console@ttyS2.service '
24
+ )
25
26
# FIXME: Although these tests boot a whole distro they are still
27
# slower than comparable machine models. There may be some
28
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image):
29
interrupt_interactive_console_until_pattern(
30
self, 'Hit any key to stop autoboot:', 'ast#')
31
exec_command_and_wait_for_pattern(
32
- self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
33
+ self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
34
exec_command_and_wait_for_pattern(
35
self, 'boot', '## Loading kernel from FIT Image')
36
self.wait_for_console_pattern('Starting kernel ...')
37
--
38
2.39.1
39
40
diff view generated by jsdifflib
[PULL 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
Deleted patch
1
These globals were moved to MachineClass by commit 71ae9e94d9 ("pc: Move
2
option_rom_has_mr/rom_file_has_mr globals to MachineClass"). Finish cleanup.
3
1
4
Cc: Eduardo Habkost <ehabkost@redhat.com>
5
Cc: Marcel Apfelbaum <marcel@redhat.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
---
11
include/hw/loader.h | 3 ---
12
1 file changed, 3 deletions(-)
13
14
diff --git a/include/hw/loader.h b/include/hw/loader.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/loader.h
17
+++ b/include/hw/loader.h
18
@@ -XXX,XX +XXX,XX @@ void pstrcpy_targphys(const char *name,
19
hwaddr dest, int buf_size,
20
const char *source);
21
22
-extern bool option_rom_has_mr;
23
-extern bool rom_file_has_mr;
24
-
25
ssize_t rom_add_file(const char *file, const char *fw_dir,
26
hwaddr addr, int32_t bootindex,
27
bool option_rom, MemoryRegion *mr, AddressSpace *as);
28
--
29
2.39.1
30
31
diff view generated by jsdifflib
[PULL 10/25] hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
Deleted patch
1
From: Peter Delevoryas <peter@pjd.dev>
2
1
3
This helper is useful in board initialization because lets users initialize and
4
realize an EEPROM on an I2C bus with a single function call.
5
6
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Corey Minyard <cminyard@mvista.com>
10
Link: https://lore.kernel.org/r/20230128060543.95582-2-peter@pjd.dev
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
---
13
include/hw/nvram/eeprom_at24c.h | 23 +++++++++++++++++++++++
14
hw/arm/aspeed.c | 10 +---------
15
hw/arm/npcm7xx_boards.c | 20 +++++---------------
16
hw/nvram/eeprom_at24c.c | 12 ++++++++++++
17
4 files changed, 41 insertions(+), 24 deletions(-)
18
create mode 100644 include/hw/nvram/eeprom_at24c.h
19
20
diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
21
new file mode 100644
22
index XXXXXXX..XXXXXXX
23
--- /dev/null
24
+++ b/include/hw/nvram/eeprom_at24c.h
25
@@ -XXX,XX +XXX,XX @@
26
+/*
27
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
28
+ *
29
+ * SPDX-License-Identifier: GPL-2.0-only
30
+ */
31
+
32
+#ifndef EEPROM_AT24C_H
33
+#define EEPROM_AT24C_H
34
+
35
+#include "hw/i2c/i2c.h"
36
+
37
+/*
38
+ * Create and realize an AT24C EEPROM device on the heap.
39
+ * @bus: I2C bus to put it on
40
+ * @address: I2C address of the EEPROM slave when put on a bus
41
+ * @rom_size: size of the EEPROM
42
+ *
43
+ * Create the device state structure, initialize it, put it on the specified
44
+ * @bus, and drop the reference to it (the device is realized).
45
+ */
46
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
47
+
48
+#endif
49
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/hw/arm/aspeed.c
52
+++ b/hw/arm/aspeed.c
53
@@ -XXX,XX +XXX,XX @@
54
#include "hw/i2c/i2c_mux_pca954x.h"
55
#include "hw/i2c/smbus_eeprom.h"
56
#include "hw/misc/pca9552.h"
57
+#include "hw/nvram/eeprom_at24c.h"
58
#include "hw/sensor/tmp105.h"
59
#include "hw/misc/led.h"
60
#include "hw/qdev-properties.h"
61
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
62
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
63
}
64
65
-static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
66
-{
67
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
68
- DeviceState *dev = DEVICE(i2c_dev);
69
-
70
- qdev_prop_set_uint32(dev, "rom-size", rsize);
71
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
72
-}
73
-
74
static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
75
{
76
AspeedSoCState *soc = &bmc->soc;
77
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/arm/npcm7xx_boards.c
80
+++ b/hw/arm/npcm7xx_boards.c
81
@@ -XXX,XX +XXX,XX @@
82
#include "hw/i2c/i2c_mux_pca954x.h"
83
#include "hw/i2c/smbus_eeprom.h"
84
#include "hw/loader.h"
85
+#include "hw/nvram/eeprom_at24c.h"
86
#include "hw/qdev-core.h"
87
#include "hw/qdev-properties.h"
88
#include "qapi/error.h"
89
@@ -XXX,XX +XXX,XX @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
90
return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
91
}
92
93
-static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
94
- uint32_t rsize)
95
-{
96
- I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
97
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
98
- DeviceState *dev = DEVICE(i2c_dev);
99
-
100
- qdev_prop_set_uint32(dev, "rom-size", rsize);
101
- i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
102
-}
103
-
104
static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
105
NPCM7xxState *soc, const int *fan_counts)
106
{
107
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
108
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
109
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
110
111
- at24c_eeprom_init(soc, 9, 0x55, 8192);
112
- at24c_eeprom_init(soc, 10, 0x55, 8192);
113
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
114
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
115
116
/*
117
* i2c-11:
118
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
119
120
i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
121
122
- at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
123
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
124
125
i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
126
TYPE_PCA9548, 0x77);
127
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
128
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
129
i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
130
131
- at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
132
+ at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
133
134
/* TODO: Add remaining i2c devices. */
135
}
136
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
137
index XXXXXXX..XXXXXXX 100644
138
--- a/hw/nvram/eeprom_at24c.c
139
+++ b/hw/nvram/eeprom_at24c.c
140
@@ -XXX,XX +XXX,XX @@
141
#include "qapi/error.h"
142
#include "qemu/module.h"
143
#include "hw/i2c/i2c.h"
144
+#include "hw/nvram/eeprom_at24c.h"
145
#include "hw/qdev-properties.h"
146
#include "hw/qdev-properties-system.h"
147
#include "sysemu/block-backend.h"
148
@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
149
return 0;
150
}
151
152
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
153
+{
154
+ I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
155
+ DeviceState *dev = DEVICE(i2c_dev);
156
+
157
+ qdev_prop_set_uint32(dev, "rom-size", rom_size);
158
+ i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
159
+
160
+ return i2c_dev;
161
+}
162
+
163
static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
164
{
165
EEPROMState *ee = AT24C_EE(dev);
166
--
167
2.39.1
168
169
diff view generated by jsdifflib
[PULL 11/25] hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
Deleted patch
1
From: Peter Delevoryas <peter@pjd.dev>
2
1
3
aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
4
5
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Corey Minyard <cminyard@mvista.com>
10
Link: https://lore.kernel.org/r/20230128060543.95582-3-peter@pjd.dev
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
---
13
hw/arm/aspeed.c | 95 ++++++++++++++++++++++---------------------------
14
1 file changed, 43 insertions(+), 52 deletions(-)
15
16
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/aspeed.c
19
+++ b/hw/arm/aspeed.c
20
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
21
eeprom_buf);
22
}
23
24
-static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
25
-{
26
- I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
27
- DeviceState *dev = DEVICE(i2c_dev);
28
-
29
- qdev_prop_set_uint32(dev, "rom-size", rsize);
30
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
31
-}
32
-
33
static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
34
{
35
AspeedSoCState *soc = &bmc->soc;
36
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
37
AspeedSoCState *soc = &bmc->soc;
38
I2CSlave *i2c_mux;
39
40
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
41
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
42
43
create_pca9552(soc, 3, 0x61);
44
45
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
46
0x4a);
47
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
48
"pca9546", 0x70);
49
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
50
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
51
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
52
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
53
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
54
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
55
create_pca9552(soc, 4, 0x60);
56
57
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
58
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
59
create_pca9552(soc, 5, 0x61);
60
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
61
"pca9546", 0x70);
62
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
63
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
64
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
65
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
66
67
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
68
0x48);
69
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
70
0x4b);
71
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
72
"pca9546", 0x70);
73
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
74
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
75
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
76
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
77
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
78
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
79
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
80
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
81
82
create_pca9552(soc, 7, 0x30);
83
create_pca9552(soc, 7, 0x31);
84
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
85
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
86
0x48);
87
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
88
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
89
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
90
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
91
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
92
93
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
94
0x48);
95
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
96
0x4a);
97
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
98
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
99
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
100
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
101
create_pca9552(soc, 8, 0x60);
102
create_pca9552(soc, 8, 0x61);
103
/* Bus 8: ucd90320@11 */
104
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
105
106
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
107
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
108
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
109
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
110
111
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
112
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
113
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
114
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
115
116
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
117
0x48);
118
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
119
0x49);
120
i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
121
"pca9546", 0x70);
122
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
123
- aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
124
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
125
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
126
create_pca9552(soc, 11, 0x60);
127
128
129
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
130
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
131
create_pca9552(soc, 13, 0x60);
132
133
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
134
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
135
create_pca9552(soc, 14, 0x60);
136
137
- aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
138
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
139
create_pca9552(soc, 15, 0x60);
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
143
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
144
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
145
146
- aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
147
- aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
148
- aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
149
+ at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
150
+ at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
151
+ at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
152
153
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
154
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
155
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
156
i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
157
158
- aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
159
+ at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
160
i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
161
162
i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
163
- aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
164
+ at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
165
i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
166
i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
167
168
i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
169
i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
170
171
- aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
172
+ at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
173
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
174
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
175
- aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
176
- aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
177
- aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
178
- aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
179
+ at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
180
+ at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
181
+ at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
182
+ at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
183
184
- aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
185
+ at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
186
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
187
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
188
- aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
189
- aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
190
- aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
191
- aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
192
- aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
193
+ at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
194
+ at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
195
+ at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
196
+ at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
197
+ at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
198
199
for (int i = 0; i < 8; i++) {
200
- aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
201
+ at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
202
i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
203
i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
204
i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
205
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
206
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
207
i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
208
209
- aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
210
- aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
211
- aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
212
- aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
213
- aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
214
+ at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
215
+ at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
216
+ at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
217
+ at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
218
+ at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
219
220
/*
221
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
222
--
223
2.39.1
224
225
diff view generated by jsdifflib
[PULL 12/25] hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
Deleted patch
1
From: Peter Delevoryas <peter@pjd.dev>
2
1
3
Allows users to specify binary data to initialize an EEPROM, allowing users to
4
emulate data programmed at manufacturing time.
5
6
- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
7
- Added at24c_eeprom_init_rom helper function to initialize attributes
8
- If -drive property is provided, it overrides init_rom data
9
10
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
11
Reviewed-by: Joel Stanley <joel@jms.id.au>
12
Reviewed-by: Corey Minyard <cminyard@mvista.com>
13
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
Tested-by: Ninad Palsule <ninadpalsule@us.ibm.com>
15
Link: https://lore.kernel.org/r/20230128060543.95582-4-peter@pjd.dev
16
Signed-off-by: Cédric Le Goater <clg@kaod.org>
17
---
18
include/hw/nvram/eeprom_at24c.h | 16 +++++++++++++++
19
hw/nvram/eeprom_at24c.c | 36 ++++++++++++++++++++++++++++-----
20
2 files changed, 47 insertions(+), 5 deletions(-)
21
22
diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/nvram/eeprom_at24c.h
25
+++ b/include/hw/nvram/eeprom_at24c.h
26
@@ -XXX,XX +XXX,XX @@
27
*/
28
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
29
30
+
31
+/*
32
+ * Create and realize an AT24C EEPROM device on the heap with initial data.
33
+ * @bus: I2C bus to put it on
34
+ * @address: I2C address of the EEPROM slave when put on a bus
35
+ * @rom_size: size of the EEPROM
36
+ * @init_rom: Array of bytes to initialize EEPROM memory with
37
+ * @init_rom_size: Size of @init_rom, must be less than or equal to @rom_size
38
+ *
39
+ * Create the device state structure, initialize it, put it on the specified
40
+ * @bus, and drop the reference to it (the device is realized). Copies the data
41
+ * from @init_rom to the beginning of the EEPROM memory buffer.
42
+ */
43
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
44
+ const uint8_t *init_rom, uint32_t init_rom_size);
45
+
46
#endif
47
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/nvram/eeprom_at24c.c
50
+++ b/hw/nvram/eeprom_at24c.c
51
@@ -XXX,XX +XXX,XX @@ struct EEPROMState {
52
uint8_t *mem;
53
54
BlockBackend *blk;
55
+
56
+ const uint8_t *init_rom;
57
+ uint32_t init_rom_size;
58
};
59
60
static
61
@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
62
63
I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
64
{
65
- I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
66
- DeviceState *dev = DEVICE(i2c_dev);
67
+ return at24c_eeprom_init_rom(bus, address, rom_size, NULL, 0);
68
+}
69
+
70
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
71
+ const uint8_t *init_rom, uint32_t init_rom_size)
72
+{
73
+ EEPROMState *s;
74
+
75
+ s = AT24C_EE(i2c_slave_new(TYPE_AT24C_EE, address));
76
+
77
+ qdev_prop_set_uint32(DEVICE(s), "rom-size", rom_size);
78
79
- qdev_prop_set_uint32(dev, "rom-size", rom_size);
80
- i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
81
+ /* TODO: Model init_rom with QOM properties. */
82
+ s->init_rom = init_rom;
83
+ s->init_rom_size = init_rom_size;
84
85
- return i2c_dev;
86
+ i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);
87
+
88
+ return I2C_SLAVE(s);
89
}
90
91
static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
92
{
93
EEPROMState *ee = AT24C_EE(dev);
94
95
+ if (ee->init_rom_size > ee->rsize) {
96
+ error_setg(errp, "%s: init rom is larger than rom: %u > %u",
97
+ TYPE_AT24C_EE, ee->init_rom_size, ee->rsize);
98
+ return;
99
+ }
100
+
101
if (ee->blk) {
102
int64_t len = blk_getlength(ee->blk);
103
104
@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
105
}
106
107
ee->mem = g_malloc0(ee->rsize);
108
+
109
}
110
111
static
112
@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
113
114
memset(ee->mem, 0, ee->rsize);
115
116
+ if (ee->init_rom) {
117
+ memcpy(ee->mem, ee->init_rom, MIN(ee->init_rom_size, ee->rsize));
118
+ }
119
+
120
if (ee->blk) {
121
int ret = blk_pread(ee->blk, 0, ee->rsize, ee->mem, 0);
122
123
--
124
2.39.1
125
126
diff view generated by jsdifflib
[PULL 13/25] hw/arm/aspeed: Add aspeed_eeprom.c
Deleted patch
1
From: Peter Delevoryas <peter@pjd.dev>
2
1
3
- Create aspeed_eeprom.c and aspeed_eeprom.h
4
- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
5
- Include aspeed_eeprom.h in aspeed.c
6
- Add fby35_bmc_fruid data
7
- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
8
from aspeed_eeprom.c
9
10
wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
11
qemu-system-aarch64 -machine fby35-bmc -nographic -mtdblock fby35.mtd
12
...
13
user: root
14
pass: 0penBmc
15
...
16
root@bmc-oob:~# fruid-util bb
17
18
FRU Information : Baseboard
19
--------------- : ------------------
20
Chassis Type : Rack Mount Chassis
21
Chassis Part Number : N/A
22
Chassis Serial Number : N/A
23
Board Mfg Date : Fri Jan 7 10:30:00 2022
24
Board Mfg : XXXXXX
25
Board Product : Management Board wBMC
26
Board Serial : XXXXXXXXXXXXX
27
Board Part Number : XXXXXXXXXXXXXX
28
Board FRU ID : 1.0
29
Board Custom Data 1 : XXXXXXXXX
30
Board Custom Data 2 : XXXXXXXXXXXXXXXXXX
31
Product Manufacturer : XXXXXX
32
Product Name : Yosemite V3.5 EVT2
33
Product Part Number : XXXXXXXXXXXXXX
34
Product Version : EVT2
35
Product Serial : XXXXXXXXXXXXX
36
Product Asset Tag : XXXXXXX
37
Product FRU ID : 1.0
38
Product Custom Data 1 : XXXXXXXXX
39
Product Custom Data 2 : N/A
40
root@bmc-oob:~# fruid-util bmc
41
42
FRU Information : BMC
43
--------------- : ------------------
44
Board Mfg Date : Mon Jan 10 21:42:00 2022
45
Board Mfg : XXXXXX
46
Board Product : BMC Storage Module
47
Board Serial : XXXXXXXXXXXXX
48
Board Part Number : XXXXXXXXXXXXXX
49
Board FRU ID : 1.0
50
Board Custom Data 1 : XXXXXXXXX
51
Board Custom Data 2 : XXXXXXXXXXXXXXXXXX
52
Product Manufacturer : XXXXXX
53
Product Name : Yosemite V3.5 EVT2
54
Product Part Number : XXXXXXXXXXXXXX
55
Product Version : EVT2
56
Product Serial : XXXXXXXXXXXXX
57
Product Asset Tag : XXXXXXX
58
Product FRU ID : 1.0
59
Product Custom Data 1 : XXXXXXXXX
60
Product Custom Data 2 : Config A
61
root@bmc-oob:~# fruid-util nic
62
63
FRU Information : NIC
64
--------------- : ------------------
65
Board Mfg Date : Tue Nov 2 08:51:00 2021
66
Board Mfg : XXXXXXXX
67
Board Product : Mellanox ConnectX-6 DX OCP3.0
68
Board Serial : XXXXXXXXXXXXXXXXXXXXXXXX
69
Board Part Number : XXXXXXXXXXXXXXXXXXXXX
70
Board FRU ID : FRU Ver 0.02
71
Product Manufacturer : XXXXXXXX
72
Product Name : Mellanox ConnectX-6 DX OCP3.0
73
Product Part Number : XXXXXXXXXXXXXXXXXXXXX
74
Product Version : A9
75
Product Serial : XXXXXXXXXXXXXXXXXXXXXXXX
76
Product Custom Data 3 : ConnectX-6 DX
77
78
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
79
Reviewed-by: Cédric Le Goater <clg@kaod.org>
80
Reviewed-by: Joel Stanley <joel@jms.id.au>
81
Reviewed-by: Corey Minyard <cminyard@mvista.com>
82
Link: https://lore.kernel.org/r/20230128060543.95582-5-peter@pjd.dev
83
Signed-off-by: Cédric Le Goater <clg@kaod.org>
84
---
85
hw/arm/aspeed_eeprom.h | 19 ++++++++++
86
hw/arm/aspeed.c | 10 ++++--
87
hw/arm/aspeed_eeprom.c | 82 ++++++++++++++++++++++++++++++++++++++++++
88
hw/arm/meson.build | 1 +
89
4 files changed, 109 insertions(+), 3 deletions(-)
90
create mode 100644 hw/arm/aspeed_eeprom.h
91
create mode 100644 hw/arm/aspeed_eeprom.c
92
93
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
94
new file mode 100644
95
index XXXXXXX..XXXXXXX
96
--- /dev/null
97
+++ b/hw/arm/aspeed_eeprom.h
98
@@ -XXX,XX +XXX,XX @@
99
+/*
100
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
101
+ *
102
+ * SPDX-License-Identifier: GPL-2.0-only
103
+ */
104
+
105
+#ifndef ASPEED_EEPROM_H
106
+#define ASPEED_EEPROM_H
107
+
108
+#include "qemu/osdep.h"
109
+
110
+extern const uint8_t fby35_nic_fruid[];
111
+extern const uint8_t fby35_bb_fruid[];
112
+extern const uint8_t fby35_bmc_fruid[];
113
+extern const size_t fby35_nic_fruid_len;
114
+extern const size_t fby35_bb_fruid_len;
115
+extern const size_t fby35_bmc_fruid_len;
116
+
117
+#endif
118
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
119
index XXXXXXX..XXXXXXX 100644
120
--- a/hw/arm/aspeed.c
121
+++ b/hw/arm/aspeed.c
122
@@ -XXX,XX +XXX,XX @@
123
#include "hw/arm/boot.h"
124
#include "hw/arm/aspeed.h"
125
#include "hw/arm/aspeed_soc.h"
126
+#include "hw/arm/aspeed_eeprom.h"
127
#include "hw/i2c/i2c_mux_pca954x.h"
128
#include "hw/i2c/smbus_eeprom.h"
129
#include "hw/misc/pca9552.h"
130
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
131
132
at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
133
at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
134
- at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
135
- at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
136
- at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
137
+ at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
138
+ fby35_nic_fruid_len);
139
+ at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
140
+ fby35_bb_fruid_len);
141
+ at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
142
+ fby35_bmc_fruid_len);
143
144
/*
145
* TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
146
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
147
new file mode 100644
148
index XXXXXXX..XXXXXXX
149
--- /dev/null
150
+++ b/hw/arm/aspeed_eeprom.c
151
@@ -XXX,XX +XXX,XX @@
152
+/*
153
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
154
+ *
155
+ * SPDX-License-Identifier: GPL-2.0-only
156
+ */
157
+
158
+#include "aspeed_eeprom.h"
159
+
160
+const uint8_t fby35_nic_fruid[] = {
161
+ 0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
162
+ 0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
163
+ 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
164
+ 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
165
+ 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
166
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
167
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
168
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
169
+ 0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
170
+ 0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
171
+ 0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
172
+ 0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
173
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
174
+ 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
175
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
176
+ 0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
177
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
178
+ 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
179
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
180
+ 0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
181
+ 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
182
+ 0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
183
+ 0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
184
+ 0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
185
+ 0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
186
+ 0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
187
+};
188
+
189
+const uint8_t fby35_bb_fruid[] = {
190
+ 0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
191
+ 0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
192
+ 0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
193
+ 0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
194
+ 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
195
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
196
+ 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
197
+ 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
198
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
199
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
200
+ 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
201
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
202
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
203
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
204
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
205
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
206
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
207
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
208
+ 0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
209
+};
210
+
211
+const uint8_t fby35_bmc_fruid[] = {
212
+ 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
213
+ 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
214
+ 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
215
+ 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
216
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
217
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
218
+ 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
219
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
220
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
221
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
222
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
223
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
224
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
225
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
226
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
227
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
228
+ 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
229
+};
230
+
231
+const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
232
+const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
233
+const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
234
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
235
index XXXXXXX..XXXXXXX 100644
236
--- a/hw/arm/meson.build
237
+++ b/hw/arm/meson.build
238
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
239
'aspeed.c',
240
'aspeed_ast2600.c',
241
'aspeed_ast10x0.c',
242
+ 'aspeed_eeprom.c',
243
'fby35.c'))
244
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
245
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
246
--
247
2.39.1
248
249
diff view generated by jsdifflib
[PULL 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware
Deleted patch
1
From: Peter Delevoryas <peter@pjd.dev>
2
1
3
EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
4
I would expect the I2C state machine to be reset to default values, but I
5
wouldn't really expect the memory to change at all.
6
7
The current implementation of the at24c EEPROM resets its internal memory on
8
reset. This matches the specification in docs/devel/reset.rst:
9
10
Cold reset is supported by every resettable object. In QEMU, it means we reset
11
to the initial state corresponding to the start of QEMU; this might differ
12
from what is a real hardware cold reset. It differs from other resets (like
13
warm or bus resets) which may keep certain parts untouched.
14
15
But differs from my intuition. For example, if someone writes some information
16
to an EEPROM, then AC power cycles their board, they would expect the EEPROM to
17
retain that information. It's very useful to be able to test things like this
18
in QEMU as well, to verify software instrumentation like determining the cause
19
of a reboot.
20
21
Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom")
22
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
23
Reviewed-by: Joel Stanley <joel@jms.id.au>
24
Reviewed-by: Cédric Le Goater <clg@kaod.org>
25
Reviewed-by: Corey Minyard <cminyard@mvista.com>
26
Link: https://lore.kernel.org/r/20230128060543.95582-6-peter@pjd.dev
27
Signed-off-by: Cédric Le Goater <clg@kaod.org>
28
---
29
hw/nvram/eeprom_at24c.c | 22 ++++++++++------------
30
1 file changed, 10 insertions(+), 12 deletions(-)
31
32
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/nvram/eeprom_at24c.c
35
+++ b/hw/nvram/eeprom_at24c.c
36
@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
37
}
38
39
ee->mem = g_malloc0(ee->rsize);
40
-
41
-}
42
-
43
-static
44
-void at24c_eeprom_reset(DeviceState *state)
45
-{
46
- EEPROMState *ee = AT24C_EE(state);
47
-
48
- ee->changed = false;
49
- ee->cur = 0;
50
- ee->haveaddr = 0;
51
-
52
memset(ee->mem, 0, ee->rsize);
53
54
if (ee->init_rom) {
55
@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
56
}
57
}
58
59
+static
60
+void at24c_eeprom_reset(DeviceState *state)
61
+{
62
+ EEPROMState *ee = AT24C_EE(state);
63
+
64
+ ee->changed = false;
65
+ ee->cur = 0;
66
+ ee->haveaddr = 0;
67
+}
68
+
69
static Property at24c_eeprom_props[] = {
70
DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
71
DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
72
--
73
2.39.1
74
75
diff view generated by jsdifflib
[PULL 15/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Avoid confusing two different things:
4
- the WDT I/O region size ('iosize')
5
- at which offset the SoC map the WDT ('offset')
6
While it is often the same, we can map smaller region sizes
7
at larger offsets.
8
9
Here we are interested in the I/O region size, so rename as
10
'iosize'.
11
12
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
[ clg: Introduced temporary wdt_offset variable ]
15
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
---
17
include/hw/watchdog/wdt_aspeed.h | 2 +-
18
hw/arm/aspeed_ast10x0.c | 4 ++--
19
hw/arm/aspeed_ast2600.c | 4 ++--
20
hw/arm/aspeed_soc.c | 4 ++--
21
hw/watchdog/wdt_aspeed.c | 8 ++++----
22
5 files changed, 11 insertions(+), 11 deletions(-)
23
24
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/watchdog/wdt_aspeed.h
27
+++ b/include/hw/watchdog/wdt_aspeed.h
28
@@ -XXX,XX +XXX,XX @@ struct AspeedWDTState {
29
struct AspeedWDTClass {
30
SysBusDeviceClass parent_class;
31
32
- uint32_t offset;
33
+ uint32_t iosize;
34
uint32_t ext_pulse_width_mask;
35
uint32_t reset_ctrl_reg;
36
void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
37
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/aspeed_ast10x0.c
40
+++ b/hw/arm/aspeed_ast10x0.c
41
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
42
/* Watch dog */
43
for (i = 0; i < sc->wdts_num; i++) {
44
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
45
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
46
47
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
48
&error_abort);
49
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
50
return;
51
}
52
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
53
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
54
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
55
}
56
57
/* GPIO */
58
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/aspeed_ast2600.c
61
+++ b/hw/arm/aspeed_ast2600.c
62
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
63
/* Watch dog */
64
for (i = 0; i < sc->wdts_num; i++) {
65
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
66
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
67
68
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
69
&error_abort);
70
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
71
return;
72
}
73
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
74
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
75
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
76
}
77
78
/* RAM */
79
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/arm/aspeed_soc.c
82
+++ b/hw/arm/aspeed_soc.c
83
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
84
/* Watch dog */
85
for (i = 0; i < sc->wdts_num; i++) {
86
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
87
+ hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
88
89
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
90
&error_abort);
91
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
92
return;
93
}
94
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
95
- sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
96
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
97
}
98
99
/* RAM */
100
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/watchdog/wdt_aspeed.c
103
+++ b/hw/watchdog/wdt_aspeed.c
104
@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
105
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
106
107
dc->desc = "ASPEED 2400 Watchdog Controller";
108
- awc->offset = 0x20;
109
+ awc->iosize = 0x20;
110
awc->ext_pulse_width_mask = 0xff;
111
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
112
awc->wdt_reload = aspeed_wdt_reload;
113
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
114
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
115
116
dc->desc = "ASPEED 2500 Watchdog Controller";
117
- awc->offset = 0x20;
118
+ awc->iosize = 0x20;
119
awc->ext_pulse_width_mask = 0xfffff;
120
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
121
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
122
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
123
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
124
125
dc->desc = "ASPEED 2600 Watchdog Controller";
126
- awc->offset = 0x40;
127
+ awc->iosize = 0x40;
128
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
129
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
130
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
131
@@ -XXX,XX +XXX,XX @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
132
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
133
134
dc->desc = "ASPEED 1030 Watchdog Controller";
135
- awc->offset = 0x80;
136
+ awc->iosize = 0x80;
137
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
138
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
139
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
140
--
141
2.39.1
142
143
diff view generated by jsdifflib
[PULL 16/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
When booting the Zephyr demo in [1] we get:
4
5
aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <--
6
aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1)
7
8
This corresponds to this Zephyr code [2]:
9
10
static int aspeed_wdt_init(const struct device *dev)
11
{
12
const struct aspeed_wdt_config *config = dev->config;
13
struct aspeed_wdt_data *const data = dev->data;
14
uint32_t reg_val;
15
16
/* disable WDT by default */
17
reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG);
18
reg_val &= ~WDT_CTRL_ENABLE;
19
sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG);
20
21
sys_write32(data->rst_mask1,
22
config->ctrl_base + WDT_SW_RESET_MASK1_REG); <------
23
sys_write32(data->rst_mask2,
24
config->ctrl_base + WDT_SW_RESET_MASK2_REG);
25
26
return 0;
27
}
28
29
The register definitions are [3]:
30
31
#define WDT_RELOAD_VAL_REG 0x0004
32
#define WDT_RESTART_REG 0x0008
33
#define WDT_CTRL_REG 0x000C
34
#define WDT_TIMEOUT_STATUS_REG 0x0010
35
#define WDT_TIMEOUT_STATUS_CLR_REG 0x0014
36
#define WDT_RESET_MASK1_REG 0x001C
37
#define WDT_RESET_MASK2_REG 0x0020
38
#define WDT_SW_RESET_MASK1_REG 0x0028 <------
39
#define WDT_SW_RESET_MASK2_REG 0x002C
40
#define WDT_SW_RESET_CTRL_REG 0x0024
41
42
Currently QEMU only cover a MMIO region of size 0x20:
43
44
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
45
46
Change to map the whole 'iosize' which might be bigger, covering
47
the other registers. The MemoryRegionOps read/write handlers will
48
report the accesses as out-of-bounds guest-errors, but the next
49
commit will report them as unimplemented.
50
51
[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
52
[2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b
53
[3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
54
55
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
56
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
57
Signed-off-by: Cédric Le Goater <clg@kaod.org>
58
---
59
hw/watchdog/wdt_aspeed.c | 3 ++-
60
1 file changed, 2 insertions(+), 1 deletion(-)
61
62
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/watchdog/wdt_aspeed.c
65
+++ b/hw/watchdog/wdt_aspeed.c
66
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
67
{
68
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
69
AspeedWDTState *s = ASPEED_WDT(dev);
70
+ AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
71
72
assert(s->scu);
73
74
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
75
s->pclk_freq = PCLK_HZ;
76
77
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
78
- TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
79
+ TYPE_ASPEED_WDT, awc->iosize);
80
sysbus_init_mmio(sbd, &s->iomem);
81
}
82
83
--
84
2.39.1
85
86
diff view generated by jsdifflib
[PULL 17/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Add more Aspeed watchdog registers from [*].
4
5
Since guests can righteously access them, log the access at
6
'unimplemented' level instead of 'guest-errors'.
7
8
[*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
9
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
---
14
include/hw/watchdog/wdt_aspeed.h | 2 +-
15
hw/watchdog/wdt_aspeed.c | 13 +++++++++++++
16
2 files changed, 14 insertions(+), 1 deletion(-)
17
18
diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/watchdog/wdt_aspeed.h
21
+++ b/include/hw/watchdog/wdt_aspeed.h
22
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
23
#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
24
#define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
25
26
-#define ASPEED_WDT_REGS_MAX (0x20 / 4)
27
+#define ASPEED_WDT_REGS_MAX (0x30 / 4)
28
29
struct AspeedWDTState {
30
/*< private >*/
31
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/watchdog/wdt_aspeed.c
34
+++ b/hw/watchdog/wdt_aspeed.c
35
@@ -XXX,XX +XXX,XX @@
36
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
37
#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
38
#define WDT_RESET_MASK1 (0x1c / 4)
39
+#define WDT_RESET_MASK2 (0x20 / 4)
40
+
41
+#define WDT_SW_RESET_CTRL (0x24 / 4)
42
+#define WDT_SW_RESET_MASK1 (0x28 / 4)
43
+#define WDT_SW_RESET_MASK2 (0x2c / 4)
44
45
#define WDT_TIMEOUT_STATUS (0x10 / 4)
46
#define WDT_TIMEOUT_CLEAR (0x14 / 4)
47
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
48
return s->regs[WDT_RESET_MASK1];
49
case WDT_TIMEOUT_STATUS:
50
case WDT_TIMEOUT_CLEAR:
51
+ case WDT_RESET_MASK2:
52
+ case WDT_SW_RESET_CTRL:
53
+ case WDT_SW_RESET_MASK1:
54
+ case WDT_SW_RESET_MASK2:
55
qemu_log_mask(LOG_UNIMP,
56
"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
57
__func__, offset);
58
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
59
60
case WDT_TIMEOUT_STATUS:
61
case WDT_TIMEOUT_CLEAR:
62
+ case WDT_RESET_MASK2:
63
+ case WDT_SW_RESET_CTRL:
64
+ case WDT_SW_RESET_MASK1:
65
+ case WDT_SW_RESET_MASK2:
66
qemu_log_mask(LOG_UNIMP,
67
"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
68
__func__, offset);
69
--
70
2.39.1
71
72
diff view generated by jsdifflib
[PULL 19/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
[PULL 1/3] aspeed: Fix maximum number of spi controller
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Troy Lee <troy_lee@aspeedtech.com>
2
2
3
Based on booting Zephyr demo from [1] running QEMU with
3
Commit 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700
4
'-d unimp' and checking missing devices in [2].
4
A1") extends ast2700a1 spis_num to 3, but ASPEED_SPIS_NUM defines the
5
maximum number of spi controller to 2, result in ehci[0] is being
6
overwritten in runtime.
5
7
6
[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
8
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
7
[2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
9
Fixes: 6de4aa8dc544 ("hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1")
8
10
Reviewed-by: Cédric Le Goater <clg@redhat.com>
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Link: https://lore.kernel.org/qemu-devel/20250317065938.1902272-1-troy_lee@aspeedtech.com
10
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
12
Signed-off-by: Cédric Le Goater <clg@redhat.com>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Joel Stanley <joel@jms.id.au>
13
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
---
13
---
15
include/hw/arm/aspeed_soc.h | 11 +++++++++++
14
include/hw/arm/aspeed_soc.h | 2 +-
16
hw/arm/aspeed_ast10x0.c | 35 +++++++++++++++++++++++++++++++++++
15
1 file changed, 1 insertion(+), 1 deletion(-)
17
2 files changed, 46 insertions(+)
18
16
19
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
17
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/aspeed_soc.h
19
--- a/include/hw/arm/aspeed_soc.h
22
+++ b/include/hw/arm/aspeed_soc.h
20
+++ b/include/hw/arm/aspeed_soc.h
23
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
24
#define ASPEED_CPUS_NUM 2
22
#include "hw/char/serial-mm.h"
25
#define ASPEED_MACS_NUM 4
23
#include "hw/intc/arm_gicv3.h"
26
#define ASPEED_UARTS_NUM 13
24
27
+#define ASPEED_JTAG_NUM 2
25
-#define ASPEED_SPIS_NUM 2
28
26
+#define ASPEED_SPIS_NUM 3
29
struct AspeedSoCState {
27
#define ASPEED_EHCIS_NUM 2
30
/*< private >*/
28
#define ASPEED_WDTS_NUM 8
31
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
29
#define ASPEED_CPUS_NUM 4
32
UnimplementedDeviceState video;
33
UnimplementedDeviceState emmc_boot_controller;
34
UnimplementedDeviceState dpmcu;
35
+ UnimplementedDeviceState pwm;
36
+ UnimplementedDeviceState espi;
37
+ UnimplementedDeviceState udc;
38
+ UnimplementedDeviceState sgpiom;
39
+ UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
40
};
41
42
#define TYPE_ASPEED_SOC "aspeed-soc"
43
@@ -XXX,XX +XXX,XX @@ enum {
44
ASPEED_DEV_DPMCU,
45
ASPEED_DEV_DP,
46
ASPEED_DEV_I3C,
47
+ ASPEED_DEV_ESPI,
48
+ ASPEED_DEV_UDC,
49
+ ASPEED_DEV_SGPIOM,
50
+ ASPEED_DEV_JTAG0,
51
+ ASPEED_DEV_JTAG1,
52
};
53
54
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
55
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/aspeed_ast10x0.c
58
+++ b/hw/arm/aspeed_ast10x0.c
59
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
60
[ASPEED_DEV_FMC] = 0x7E620000,
61
[ASPEED_DEV_SPI1] = 0x7E630000,
62
[ASPEED_DEV_SPI2] = 0x7E640000,
63
+ [ASPEED_DEV_UDC] = 0x7E6A2000,
64
[ASPEED_DEV_SCU] = 0x7E6E2000,
65
+ [ASPEED_DEV_JTAG0] = 0x7E6E4000,
66
+ [ASPEED_DEV_JTAG1] = 0x7E6E4100,
67
[ASPEED_DEV_ADC] = 0x7E6E9000,
68
+ [ASPEED_DEV_ESPI] = 0x7E6EE000,
69
[ASPEED_DEV_SBC] = 0x7E6F2000,
70
[ASPEED_DEV_GPIO] = 0x7E780000,
71
+ [ASPEED_DEV_SGPIOM] = 0x7E780500,
72
[ASPEED_DEV_TIMER1] = 0x7E782000,
73
[ASPEED_DEV_UART1] = 0x7E783000,
74
[ASPEED_DEV_UART2] = 0x7E78D000,
75
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
76
[ASPEED_DEV_LPC] = 35,
77
[ASPEED_DEV_PECI] = 38,
78
[ASPEED_DEV_FMC] = 39,
79
+ [ASPEED_DEV_ESPI] = 42,
80
[ASPEED_DEV_PWM] = 44,
81
[ASPEED_DEV_ADC] = 46,
82
[ASPEED_DEV_SPI1] = 65,
83
[ASPEED_DEV_SPI2] = 66,
84
[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
85
[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
86
+ [ASPEED_DEV_UDC] = 9,
87
+ [ASPEED_DEV_SGPIOM] = 51,
88
+ [ASPEED_DEV_JTAG0] = 27,
89
+ [ASPEED_DEV_JTAG1] = 53,
90
};
91
92
static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
93
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
94
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
95
object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
96
TYPE_UNIMPLEMENTED_DEVICE);
97
+ object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
98
+ object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
99
+ object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
100
+ object_initialize_child(obj, "sgpiom", &s->sgpiom,
101
+ TYPE_UNIMPLEMENTED_DEVICE);
102
+ object_initialize_child(obj, "jtag[0]", &s->jtag[0],
103
+ TYPE_UNIMPLEMENTED_DEVICE);
104
+ object_initialize_child(obj, "jtag[1]", &s->jtag[1],
105
+ TYPE_UNIMPLEMENTED_DEVICE);
106
}
107
108
static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
109
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
110
sc->memmap[ASPEED_DEV_GPIO]);
111
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
112
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
113
+
114
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
115
+ sc->memmap[ASPEED_DEV_PWM], 0x100);
116
+
117
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
118
+ sc->memmap[ASPEED_DEV_ESPI], 0x800);
119
+
120
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
121
+ sc->memmap[ASPEED_DEV_UDC], 0x1000);
122
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
123
+ sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
124
+
125
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
126
+ sc->memmap[ASPEED_DEV_JTAG0], 0x20);
127
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
128
+ sc->memmap[ASPEED_DEV_JTAG1], 0x20);
129
}
130
131
static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
132
--
30
--
133
2.39.1
31
2.49.0
134
32
135
33
diff view generated by jsdifflib
[PULL 23/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
[PULL 2/3] hw/intc/aspeed: Fix IRQ handler mask check
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Steven Lee <steven_lee@aspeedtech.com>
2
2
3
This SoC uses a Cortex-M4F. QEMU only implements a M4,
3
Updated the IRQ handler mask check to AND with select variable.
4
which is good enough. Add a TODO note in case the M4F
4
This ensures that the interrupt service routine is correctly triggered
5
is added.
5
for the interrupts within the same irq group.
6
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
For example, both `eth0` and the debug UART are handled in `GICINT132`.
8
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
8
Without this fix, the debug console may hang if the `eth0` ISR is not
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
handled.
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
11
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
12
Change-Id: Ic3609eb72218dfd68be6057d78b8953b18828709
13
Reviewed-by: Cédric Le Goater <clg@redhat.com>
14
Fixes: d831c5fd8682 ("aspeed/intc: Add AST2700 support")
15
Link: https://lore.kernel.org/qemu-devel/20250320092543.4040672-2-steven_lee@aspeedtech.com
16
Signed-off-by: Cédric Le Goater <clg@redhat.com>
11
---
17
---
12
hw/arm/aspeed_ast10x0.c | 2 +-
18
hw/intc/aspeed_intc.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
19
1 file changed, 1 insertion(+), 1 deletion(-)
14
20
15
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
21
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed_ast10x0.c
23
--- a/hw/intc/aspeed_intc.c
18
+++ b/hw/arm/aspeed_ast10x0.c
24
+++ b/hw/intc/aspeed_intc.c
19
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
25
@@ -XXX,XX +XXX,XX @@ static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
20
dc->realize = aspeed_soc_ast1030_realize;
26
outpin_idx = intc_irq->outpin_idx;
21
27
inpin_idx = intc_irq->inpin_idx;
22
sc->name = "ast1030-a1";
28
23
- sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
29
- if (s->mask[inpin_idx] || s->regs[status_reg]) {
24
+ sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
30
+ if ((s->mask[inpin_idx] & select) || (s->regs[status_reg] & select)) {
25
sc->silicon_rev = AST1030_A1_SILICON_REV;
31
/*
26
sc->sram_size = 0xc0000;
32
* a. mask is not 0 means in ISR mode
27
sc->secsram_size = 0x40000; /* 256 * KiB */
33
* sources interrupt routine are executing.
28
--
34
--
29
2.39.1
35
2.49.0
30
36
31
37
diff view generated by jsdifflib
[PULL 18/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed
[PULL 3/3] hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
From: Jamin Lin <jamin_lin@aspeedtech.com>
2
2
3
address_space_map() can fail:
3
The maximum padding size is either 64 or 128 bytes and should always be smaller
4
than "req_len". If "padding_size" exceeds "req_len", then
5
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
6
large incorrect value (e.g., `0xFFXXXXXX`). This causes an out-of-bounds memory
7
access, potentially leading to a buffer overflow.
4
8
5
uart:~$ hash test
9
Added a check to ensure "padding_size" does not exceed "req_len" before
6
sha256_test
10
computing "pad_offset". This prevents "req_len - padding_size" from underflowing
7
tv[0]:
11
and avoids accessing invalid memory.
8
Segmentation fault: 11
9
Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
10
gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
11
at ../hw/misc/aspeed_hace.c:171
12
171 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {
13
(gdb) bt
14
#0 gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
15
at ../hw/misc/aspeed_hace.c:171
16
#1 do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true)
17
at ../hw/misc/aspeed_hace.c:224
18
#2 0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>)
19
at ../hw/misc/aspeed_hace.c:358
20
12
21
This change doesn't fix much, but at least the guest
13
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
22
can't crash QEMU anymore. Instead it is still usable:
14
Reviewed-by: Cédric Le Goater <clg@redhat.com>
23
15
Fixes: 5cd7d8564a8b563da724b9e6264c967f0a091afa ("aspeed/hace: Support AST2600 HACE ")
24
uart:~$ hash test
16
Link: https://lore.kernel.org/qemu-devel/20250321092623.2097234-3-jamin_lin@aspeedtech.com
25
sha256_test
17
Signed-off-by: Cédric Le Goater <clg@redhat.com>
26
tv[0]:hash_final error
27
sha384_test
28
tv[0]:hash_final error
29
sha512_test
30
tv[0]:hash_final error
31
[00:00:06.278,000] <err> hace_global: HACE poll timeout
32
[00:00:09.324,000] <err> hace_global: HACE poll timeout
33
[00:00:12.261,000] <err> hace_global: HACE poll timeout
34
uart:~$
35
36
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
37
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
38
Reviewed-by: Cédric Le Goater <clg@kaod.org>
39
Signed-off-by: Cédric Le Goater <clg@kaod.org>
40
---
18
---
41
hw/misc/aspeed_hace.c | 21 +++++++++++++++------
19
hw/misc/aspeed_hace.c | 5 +++++
42
1 file changed, 15 insertions(+), 6 deletions(-)
20
1 file changed, 5 insertions(+)
43
21
44
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
22
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
45
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/misc/aspeed_hace.c
24
--- a/hw/misc/aspeed_hace.c
47
+++ b/hw/misc/aspeed_hace.c
25
+++ b/hw/misc/aspeed_hace.c
48
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
26
@@ -XXX,XX +XXX,XX @@ static bool has_padding(AspeedHACEState *s, struct iovec *iov,
49
size_t digest_len = 0;
27
if (*total_msg_len <= s->total_req_len) {
50
int niov = 0;
28
uint32_t padding_size = s->total_req_len - *total_msg_len;
51
int i;
29
uint8_t *padding = iov->iov_base;
52
+ void *haddr;
30
+
53
31
+ if (padding_size > req_len) {
54
if (sg_mode) {
32
+ return false;
55
uint32_t len = 0;
56
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
57
addr &= SG_LIST_ADDR_MASK;
58
59
plen = len & SG_LIST_LEN_MASK;
60
- iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,
61
- MEMTXATTRS_UNSPECIFIED);
62
-
63
+ haddr = address_space_map(&s->dram_as, addr, &plen, false,
64
+ MEMTXATTRS_UNSPECIFIED);
65
+ if (haddr == NULL) {
66
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
67
+ return;
68
+ }
69
+ iov[i].iov_base = haddr;
70
if (acc_mode) {
71
niov = gen_acc_mode_iov(s, iov, i, &plen);
72
73
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
74
} else {
75
hwaddr len = s->regs[R_HASH_SRC_LEN];
76
77
+ haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
78
+ &len, false, MEMTXATTRS_UNSPECIFIED);
79
+ if (haddr == NULL) {
80
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
81
+ return;
82
+ }
33
+ }
83
+ iov[0].iov_base = haddr;
34
+
84
iov[0].iov_len = len;
35
*pad_offset = req_len - padding_size;
85
- iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
36
if (padding[*pad_offset] == 0x80) {
86
- &len, false,
37
return true;
87
- MEMTXATTRS_UNSPECIFIED);
88
i = 1;
89
90
if (s->iov_count) {
91
--
38
--
92
2.39.1
39
2.49.0
93
40
94
41
diff view generated by jsdifflib
[PULL 20/25] hw/arm/aspeed_ast10x0: Map I3C peripheral
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Since I don't have access to the datasheet, the relevant
4
values were found in:
5
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
6
7
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Cédric Le Goater <clg@kaod.org>
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
11
---
12
hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++
13
1 file changed, 16 insertions(+)
14
15
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed_ast10x0.c
18
+++ b/hw/arm/aspeed_ast10x0.c
19
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
20
[ASPEED_DEV_WDT] = 0x7E785000,
21
[ASPEED_DEV_LPC] = 0x7E789000,
22
[ASPEED_DEV_PECI] = 0x7E78B000,
23
+ [ASPEED_DEV_I3C] = 0x7E7A0000,
24
[ASPEED_DEV_I2C] = 0x7E7B0000,
25
};
26
27
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
28
[ASPEED_DEV_ADC] = 46,
29
[ASPEED_DEV_SPI1] = 65,
30
[ASPEED_DEV_SPI2] = 66,
31
+ [ASPEED_DEV_I3C] = 102, /* 102 -> 105 */
32
[ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
33
[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
34
[ASPEED_DEV_UDC] = 9,
35
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
36
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
37
object_initialize_child(obj, "i2c", &s->i2c, typename);
38
39
+ object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
40
+
41
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
42
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
43
44
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
45
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
46
}
47
48
+ /* I3C */
49
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
50
+ return;
51
+ }
52
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
53
+ for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
54
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
55
+ sc->irqmap[ASPEED_DEV_I3C] + i);
56
+ /* The AST1030 I3C controller has one IRQ per bus. */
57
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
58
+ }
59
+
60
/* PECI */
61
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
62
return;
63
--
64
2.39.1
65
66
diff view generated by jsdifflib
[PULL 21/25] hw/arm/aspeed_ast10x0: Map the secure SRAM
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Some SRAM appears to be used by the Secure Boot unit and
4
crypto accelerators. Name it 'secure sram'.
5
6
Note, the SRAM base address was already present but unused
7
(the 'SBC' index is used for the MMIO peripheral).
8
9
Interestingly using CFLAGS=-Winitializer-overrides reports:
10
11
../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
12
[ASPEED_DEV_SBC] = 0x7E6F2000,
13
^~~~~~~~~~
14
../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here
15
[ASPEED_DEV_SBC] = 0x79000000,
16
^~~~~~~~~~
17
This fixes with Zephyr:
18
19
uart:~$ rsa test
20
rsa test vector[0]:
21
[00:00:26.156,000] <err> os: ***** BUS FAULT *****
22
[00:00:26.157,000] <err> os: Precise data bus error
23
[00:00:26.157,000] <err> os: BFAR Address: 0x79000000
24
[00:00:26.158,000] <err> os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3: 0x00001800
25
[00:00:26.158,000] <err> os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr: 0x0001098d
26
[00:00:26.158,000] <err> os: xpsr: 0x81000000
27
[00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc
28
[00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
29
[00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart)
30
[00:00:26.165,000] <err> os: Halting system
31
32
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
33
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
34
[ clg: Fixed size of Secure Boot Controller Memory ]
35
Signed-off-by: Cédric Le Goater <clg@kaod.org>
36
---
37
include/hw/arm/aspeed_soc.h | 3 +++
38
hw/arm/aspeed_ast10x0.c | 11 ++++++++++-
39
2 files changed, 13 insertions(+), 1 deletion(-)
40
41
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/include/hw/arm/aspeed_soc.h
44
+++ b/include/hw/arm/aspeed_soc.h
45
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
46
AspeedSMCState spi[ASPEED_SPIS_NUM];
47
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
48
AspeedSBCState sbc;
49
+ MemoryRegion secsram;
50
UnimplementedDeviceState sbc_unimplemented;
51
AspeedSDMCState sdmc;
52
AspeedWDTState wdt[ASPEED_WDTS_NUM];
53
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
54
const char *cpu_type;
55
uint32_t silicon_rev;
56
uint64_t sram_size;
57
+ uint64_t secsram_size;
58
int spis_num;
59
int ehcis_num;
60
int wdts_num;
61
@@ -XXX,XX +XXX,XX @@ enum {
62
ASPEED_DEV_SCU,
63
ASPEED_DEV_ADC,
64
ASPEED_DEV_SBC,
65
+ ASPEED_DEV_SECSRAM,
66
ASPEED_DEV_EMMC_BC,
67
ASPEED_DEV_VIDEO,
68
ASPEED_DEV_SRAM,
69
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/arm/aspeed_ast10x0.c
72
+++ b/hw/arm/aspeed_ast10x0.c
73
@@ -XXX,XX +XXX,XX @@
74
75
static const hwaddr aspeed_soc_ast1030_memmap[] = {
76
[ASPEED_DEV_SRAM] = 0x00000000,
77
- [ASPEED_DEV_SBC] = 0x79000000,
78
+ [ASPEED_DEV_SECSRAM] = 0x79000000,
79
[ASPEED_DEV_IOMEM] = 0x7E600000,
80
[ASPEED_DEV_PWM] = 0x7E610000,
81
[ASPEED_DEV_FMC] = 0x7E620000,
82
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
83
memory_region_add_subregion(s->memory,
84
sc->memmap[ASPEED_DEV_SRAM],
85
&s->sram);
86
+ memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
87
+ sc->secsram_size, &err);
88
+ if (err != NULL) {
89
+ error_propagate(errp, err);
90
+ return;
91
+ }
92
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
93
+ &s->secsram);
94
95
/* SCU */
96
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
97
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
98
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
99
sc->silicon_rev = AST1030_A1_SILICON_REV;
100
sc->sram_size = 0xc0000;
101
+ sc->secsram_size = 0x40000; /* 256 * KiB */
102
sc->spis_num = 2;
103
sc->ehcis_num = 0;
104
sc->wdts_num = 4;
105
--
106
2.39.1
107
108
diff view generated by jsdifflib
[PULL 22/25] hw/arm/aspeed_ast10x0: Map HACE peripheral
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Since I don't have access to the datasheet, the relevant
4
values were found in:
5
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
6
7
Before on Zephyr:
8
9
uart:~$ hash test
10
sha256_test
11
tv[0]:hash_final error
12
sha384_test
13
tv[0]:hash_final error
14
sha512_test
15
tv[0]:hash_final error
16
[00:00:06.278,000] <err> hace_global: HACE poll timeout
17
[00:00:09.324,000] <err> hace_global: HACE poll timeout
18
[00:00:12.261,000] <err> hace_global: HACE poll timeout
19
20
uart:~$ crypto aes256_cbc_vault
21
aes256_cbc vault key 1
22
[00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup
23
[00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098
24
[00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340
25
[00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348
26
[00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300
27
[00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040
28
[00:00:06.699,000] <inf> hace_global: crypto_cmd_reg: 11c2098
29
[00:00:09.743,000] <inf> hace_global: HACE_STS: 0
30
[00:00:09.743,000] <err> hace_global: HACE poll timeout
31
[00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed
32
[00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free
33
uart:~$
34
35
After:
36
37
uart:~$ hash test
38
sha256_test
39
tv[0]:PASS
40
tv[1]:PASS
41
tv[2]:PASS
42
tv[3]:PASS
43
tv[4]:PASS
44
sha384_test
45
tv[0]:PASS
46
tv[1]:PASS
47
tv[2]:PASS
48
tv[3]:PASS
49
tv[4]:PASS
50
tv[5]:PASS
51
sha512_test
52
tv[0]:PASS
53
tv[1]:PASS
54
tv[2]:PASS
55
tv[3]:PASS
56
tv[4]:PASS
57
tv[5]:PASS
58
59
uart:~$ crypto aes256_cbc_vault
60
aes256_cbc vault key 1
61
Was waiting for:
62
6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
63
ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
64
30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
65
f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
66
67
But got:
68
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
69
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
71
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
72
73
[00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup
74
[00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098
75
[00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
76
[00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
77
[00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
78
[00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
79
[00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2098
80
[00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
81
[00:00:05.772,000] <inf> crypto: Output length (encryption): 80
82
[00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free
83
[00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup
84
[00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018
85
[00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
86
[00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
87
[00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
88
[00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
89
[00:00:05.772,000] <inf> hace_global: crypto_cmd_reg: 11c2018
90
[00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
91
[00:00:05.772,000] <inf> crypto: Output length (decryption): 64
92
[00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text
93
[00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free
94
uart:~$
95
96
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
97
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
98
Signed-off-by: Cédric Le Goater <clg@kaod.org>
99
---
100
hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++
101
1 file changed, 15 insertions(+)
102
103
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/arm/aspeed_ast10x0.c
106
+++ b/hw/arm/aspeed_ast10x0.c
107
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
108
[ASPEED_DEV_SPI1] = 0x7E630000,
109
[ASPEED_DEV_SPI2] = 0x7E640000,
110
[ASPEED_DEV_UDC] = 0x7E6A2000,
111
+ [ASPEED_DEV_HACE] = 0x7E6D0000,
112
[ASPEED_DEV_SCU] = 0x7E6E2000,
113
[ASPEED_DEV_JTAG0] = 0x7E6E4000,
114
[ASPEED_DEV_JTAG1] = 0x7E6E4100,
115
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
116
snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
117
object_initialize_child(obj, "gpio", &s->gpio, typename);
118
119
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
120
+ object_initialize_child(obj, "hace", &s->hace, typename);
121
+
122
object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
123
object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
124
TYPE_UNIMPLEMENTED_DEVICE);
125
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
126
}
127
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
128
129
+ /* HACE */
130
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
131
+ &error_abort);
132
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
133
+ return;
134
+ }
135
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
136
+ sc->memmap[ASPEED_DEV_HACE]);
137
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
138
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
139
+
140
/* Watch dog */
141
for (i = 0; i < sc->wdts_num; i++) {
142
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
143
--
144
2.39.1
145
146
diff view generated by jsdifflib
[PULL 24/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
Deleted patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
1
3
Add a very quick test that runs some commands in a Zephyr shell:
4
5
$ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
6
(2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07:
7
console: *** Booting Zephyr OS build v00.01.07 ***
8
console: ast1030_evb demo
9
console: SOC: AST1030-A1
10
console: uart:~$ kernel stacks
11
console: 0x36910 wdt_background (real size 1024):    unused 988    usage 36 / 1024 (3 %)
12
console: 0x36ad8 shell_uart (real size 4096):    unused 3084    usage 1012 / 4096 (24 %)
13
console: 0x2edb8 ADC0 (real size 400):    unused 260    usage 140 / 400 (35 %)
14
console: 0x2f0f0 ADC1 (real size 400):    unused 260    usage 140 / 400 (35 %)
15
console: 0x3b098 sysworkq (real size 1024):    unused 860    usage 164 / 1024 (16 %)
16
console: 0x36cc0 usbdworkq (real size 1024):    unused 860    usage 164 / 1024 (16 %)
17
console: 0x36bd8 usbworkq (real size 1024):    unused 860    usage 164 / 1024 (16 %)
18
console: 0x36a10 logging (real size 768):    unused 548    usage 220 / 768 (28 %)
19
console: 0x36ef8 idle 00 (real size 320):    unused 268    usage 52 / 320 (16 %)
20
console: 0x47800 IRQ 00 (real size 2048):    unused 1504    usage 544 / 2048 (26 %)
21
console: uart:~$ otp info scu
22
console: SCU BIT reg_protect Description
23
console: ____________________________________________________________________
24
console: 0x500 0x0 0x0 Disable ARM CM4 CPU boot (TXD5)
25
console: 0x500 0x1 0x0 /Reserved
26
console: 0x500 0x2 0x0 \ "
27
console: 0x500 0x3 0x0 Address offset of single chip ABR mode
28
console: 0x500 0x4 0x0 /Reserved
29
console: 0x500 0x5 0x0 | "
30
console: 0x500 0x6 0x0 | "
31
console: 0x500 0x7 0x0 | "
32
console: 0x500 0x8 0x0 | "
33
console: 0x500 0x9 0x0 | "
34
console: 0x500 0xA 0x0 | "
35
console: 0x500 0xB 0x0 | "
36
console: 0x500 0xC 0x0 | "
37
console: 0x500 0xD 0x0 | "
38
console: 0x500 0xE 0x0 | "
39
console: 0x500 0xF 0x0 | "
40
console: 0x500 0x10 0x0 \ "
41
console: 0x500 0x11 0x0 Disabl3 ARM JTAG debug
42
console: 0x500 0x12 0x0 /Reserved
43
console: 0x500 0x13 0x0 | "
44
console: 0x500 0x14 0x0 | "
45
console: 0x500 0x15 0x0 | "
46
console: 0x500 0x16 0x0 | "
47
console: 0x500 0x17 0x0 | "
48
console: 0x500 0x18 0x0 | "
49
console: 0x500 0x19 0x0 | "
50
console: 0x500 0x1A 0x0 | "
51
console: 0x500 0x1B 0x0 | "
52
console: 0x500 0x1C 0x0 | "
53
console: 0x500 0x1D 0x0 | "
54
console: 0x500 0x1E 0x0 | "
55
console: 0x500 0x1F 0x0 \ "
56
console: 0x510 0x0 0x0 /Reserved
57
console: 0x510 0x1 0x0 | "
58
console: 0x510 0x2 0x0 | "
59
console: 0x510 0x3 0x0 \ "
60
console: 0x510 0x4 0x0 Disable debug interfaces
61
console: 0x510 0x5 0x0 /Reserved
62
console: 0x510 0x6 0x0 | "
63
console: 0x510 0x7 0x0 \ "
64
console: 0x510 0x8 0x0 Enable boot from Uart5 by Pin Strap
65
console: 0x510 0x9 0x0 /Reserved
66
console: 0x510 0xA 0x0 \ "
67
console: 0x510 0xB 0x0 Enable boot SPI ABR
68
console: 0x510 0xC 0x0 Boot SPI ABR Mode
69
console: 0x510 0xD 0x0 /Boot SPI flash size
70
console: 0x510 0xE 0x0 | "
71
console: 0x510 0xF 0x0 \ "
72
console: 0x510 0x10 0x0 /Reserved
73
console: 0x510 0x11 0x0 | "
74
console: 0x510 0x12 0x0 | "
75
console: 0x510 0x13 0x0 | "
76
console: 0x510 0x14 0x0 | "
77
console: 0x510 0x15 0x0 \ "
78
console: 0x510 0x16 0x0 Enable boot SPI auxiliary control pins
79
console: 0x510 0x19 0x0 /Reserved
80
console: 0x510 0x1A 0x0 | "
81
console: 0x510 0x1B 0x0 | "
82
console: 0x510 0x1C 0x0 | "
83
console: 0x510 0x1D 0x0 | "
84
console: 0x510 0x1E 0x0 | "
85
console: 0x510 0x1F 0x0 \ "
86
console: 0x510 0x1E 0x0 Enable dedicate GPIO strap pins
87
console: 0x510 0x1F 0x0 Enable Secure Boot by Pin Strap
88
console: uart:~$ hwinfo devid
89
console: Length: 8
90
console: ID: 0x0000018000000180
91
console: uart:~$ crypto aes256_cbc_vault
92
console: aes256_cbc vault key 1
93
console: Was waiting for:
94
console: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
95
console: ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
96
console: 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
97
console: f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
98
console: But got:
99
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
100
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
101
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
102
console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
103
console: uart:~$ random get
104
console: 0x862460d
105
console: uart:~$ i2c scan I2C_0
106
console: 0 1 2 3 4 5 6 7 8 9 a b c d e f
107
console: 00: -- -- -- -- -- -- -- -- -- -- -- --
108
console: 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
109
console: 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
110
console: 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
111
console: 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
112
console: 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
113
console: 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
114
console: 70: -- -- -- -- -- -- -- --
115
console: 1 devices found on I2C_0
116
console: uart:~$ kernel uptime
117
console: Uptime: 9897 ms
118
console: uart:~$ kernel reboot warm
119
console: *** Booting Zephyr OS build v00.01.07 ***
120
PASS (1.08 s)
121
122
Ref: https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.07/Aspeed_Zephy_SDK_User_Guide_v00.01.07.pdf
123
124
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
125
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
126
Reviewed-by: Cédric Le Goater <clg@kaod.org>
127
Signed-off-by: Cédric Le Goater <clg@kaod.org>
128
---
129
tests/avocado/machine_aspeed.py | 41 ++++++++++++++++++++++++++++++++-
130
1 file changed, 40 insertions(+), 1 deletion(-)
131
132
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
133
index XXXXXXX..XXXXXXX 100644
134
--- a/tests/avocado/machine_aspeed.py
135
+++ b/tests/avocado/machine_aspeed.py
136
@@ -XXX,XX +XXX,XX @@ class AST1030Machine(QemuSystemTest):
137
138
timeout = 10
139
140
- def test_ast1030_zephyros(self):
141
+ def test_ast1030_zephyros_1_04(self):
142
"""
143
:avocado: tags=arch:arm
144
:avocado: tags=machine:ast1030-evb
145
+ :avocado: tags=os:zephyr
146
"""
147
tar_url = ('https://github.com/AspeedTech-BMC'
148
'/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
149
@@ -XXX,XX +XXX,XX @@ def test_ast1030_zephyros(self):
150
exec_command_and_wait_for_pattern(self, "help",
151
"Available commands")
152
153
+ def test_ast1030_zephyros_1_07(self):
154
+ """
155
+ :avocado: tags=arch:arm
156
+ :avocado: tags=machine:ast1030-evb
157
+ :avocado: tags=os:zephyr
158
+ """
159
+ tar_url = ('https://github.com/AspeedTech-BMC'
160
+ '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip')
161
+ tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2'
162
+ tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
163
+ archive.extract(tar_path, self.workdir)
164
+ kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin"
165
+ self.vm.set_console()
166
+ self.vm.add_args('-kernel', kernel_file,
167
+ '-nographic')
168
+ self.vm.launch()
169
+ wait_for_console_pattern(self, "Booting Zephyr OS")
170
+ for shell_cmd in [
171
+ 'kernel stacks',
172
+ 'otp info conf',
173
+ 'otp info scu',
174
+ 'hwinfo devid',
175
+ 'crypto aes256_cbc_vault',
176
+ 'random get',
177
+ 'jtag JTAG1 sw_xfer high TMS',
178
+ 'adc ADC0 resolution 12',
179
+ 'adc ADC0 read 42',
180
+ 'adc ADC1 read 69',
181
+ 'i2c scan I2C_0',
182
+ 'i3c attach I3C_0',
183
+ 'hash test',
184
+ 'kernel uptime',
185
+ 'kernel reboot warm',
186
+ 'kernel uptime',
187
+ 'kernel reboot cold',
188
+ 'kernel uptime',
189
+ ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
190
+
191
class AST2x00Machine(QemuSystemTest):
192
193
timeout = 90
194
--
195
2.39.1
196
197
diff view generated by jsdifflib
[PULL 25/25] aspeed/sdmc: Drop unnecessary scu include
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The model includes aspeed_scu.h but doesn't appear to require it.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-Id: <20230124062022.298230-1-joel@jms.id.au>
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
---
11
hw/misc/aspeed_sdmc.c | 1 -
12
1 file changed, 1 deletion(-)
13
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
17
+++ b/hw/misc/aspeed_sdmc.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "qemu/module.h"
20
#include "qemu/error-report.h"
21
#include "hw/misc/aspeed_sdmc.h"
22
-#include "hw/misc/aspeed_scu.h"
23
#include "hw/qdev-properties.h"
24
#include "migration/vmstate.h"
25
#include "qapi/error.h"
26
--
27
2.39.1
28
29
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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