Series comparison

-[PULL 00/25] aspeed queue
+[PULL 00/12] aspeed queue
-The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:
+The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:
-  Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)
+  Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)
 are available in the Git repository at:
-  https://github.com/legoater/qemu/ tags/pull-aspeed-20230207
+  https://github.com/legoater/qemu/ tags/pull-aspeed-20231025
-for you to fetch changes up to bf81b8f8acda4f1f774adc5f8e76225d472c6ae5:
+for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:
-  aspeed/sdmc: Drop unnecessary scu include (2023-02-07 09:02:05 +0100)
+  hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)
 ----------------------------------------------------------------
 aspeed queue:
-* various small cleanups and fixes
+* Update of Andrew's email
-* new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC
+* Split of AspeedSoCState per 2400/2600/10x0
 * at24c_eeprom extension to define eeprom contents with static arrays
 * ast10x0 model and test improvements
 * avocado update of images to use the latest
 ----------------------------------------------------------------
-Cédric Le Goater (3):
+Andrew Jeffery (1):
-      tests/avocado/machine_aspeed.py: update buildroot tests
+      MAINTAINERS: aspeed: Update Andrew's email address
       tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
       hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
-Guenter Roeck (2):
+Philippe Mathieu-Daudé (11):
-      aspeed: Add Supermicro X11 SPI machine type
+      hw/arm/aspeed: Extract code common to all boards to a common file
-      m25p80: Add the is25wp256 SFPD table
+      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
       hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
       hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
       hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
       hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
       hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
       hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
       hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
       hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
       hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
-Joel Stanley (2):
+ MAINTAINERS                               |   2 +-
-      avocado/boot_linux_console.py: Update ast2600 test
+ include/hw/arm/aspeed_soc.h               |  35 +++++-
-      aspeed/sdmc: Drop unnecessary scu include
+ hw/arm/aspeed.c                           | 101 +++++++--------
  hw/arm/aspeed_ast10x0.c                   |  53 ++++----
  hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
  hw/arm/aspeed_ast2600.c                   |  75 ++++++------
  hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
  hw/arm/fby35.c                            |  27 ++--
  hw/arm/meson.build                        |   3 +-
 files changed, 363 insertions(+), 284 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
  create mode 100644 hw/arm/aspeed_soc_common.c
-Peter Delevoryas (5):
-      hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
-      hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
-      hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
-      hw/arm/aspeed: Add aspeed_eeprom.c
-      hw/nvram/eeprom_at24c: Make reset behavior more like hardware
-Philippe Mathieu-Daudé (12):
-      tests/avocado: Introduce file_truncate()
-      tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiB
-      hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
-      hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
-      hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
-      hw/misc/aspeed_hace: Do not crash if address_space_map() failed
-      hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
-      hw/arm/aspeed_ast10x0: Map I3C peripheral
-      hw/arm/aspeed_ast10x0: Map the secure SRAM
-      hw/arm/aspeed_ast10x0: Map HACE peripheral
-      hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
-      tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
-Stephen Longfield (1):
-      hw/net: Fix read of uninitialized memory in ftgmac100
- hw/arm/aspeed_eeprom.h              |  19 +++++
- hw/block/m25p80_sfdp.h              |   2 +
- include/hw/arm/aspeed_soc.h         |  14 ++++
- include/hw/loader.h                 |   3 -
- include/hw/nvram/eeprom_at24c.h     |  39 ++++++++++
- include/hw/watchdog/wdt_aspeed.h    |   4 +-
- hw/arm/aspeed.c                     | 142 ++++++++++++++++++++----------------
- hw/arm/aspeed_ast10x0.c             |  83 ++++++++++++++++++++-
- hw/arm/aspeed_ast2600.c             |   4 +-
- hw/arm/aspeed_eeprom.c              |  82 +++++++++++++++++++++
- hw/arm/aspeed_soc.c                 |   4 +-
- hw/arm/msf2-som.c                   |   5 +-
- hw/arm/npcm7xx_boards.c             |  20 ++---
- hw/block/m25p80.c                   |   3 +-
- hw/block/m25p80_sfdp.c              |  40 ++++++++++
- hw/misc/aspeed_hace.c               |  21 ++++--
- hw/misc/aspeed_sdmc.c               |   1 -
- hw/net/ftgmac100.c                  |   4 +-
- hw/nvram/eeprom_at24c.c             |  58 ++++++++++++---
- hw/watchdog/wdt_aspeed.c            |  24 ++++--
- hw/arm/meson.build                  |   1 +
- tests/avocado/boot_linux_console.py |  19 +++--
- tests/avocado/machine_aspeed.py     |  60 +++++++++++++--
-files changed, 523 insertions(+), 129 deletions(-)
- create mode 100644 hw/arm/aspeed_eeprom.h
- create mode 100644 include/hw/nvram/eeprom_at24c.h
- create mode 100644 hw/arm/aspeed_eeprom.c

-[PULL 01/25] tests/avocado: Introduce file_truncate()
+Deleted patch
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Link: https://lore.kernel.org/r/20230120134314.81956-2-philmd@linaro.org
-[ clg: remove image_pow2ceil_expand() factoring ]
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- tests/avocado/boot_linux_console.py | 5 +++++
-file changed, 5 insertions(+)
-diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/boot_linux_console.py
-+++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@
- def pow2ceil(x):
-     return 1 if x == 0 else 2**(x - 1).bit_length()
-+def file_truncate(path, size):
-+    if size != os.path.getsize(path):
-+        with open(path, 'ab+') as fd:
-+            fd.truncate(size)
-+
- """
- Expand file size to next power of 2
- """
---
-.39.1

-[PULL 25/25] aspeed/sdmc: Drop unnecessary scu include
+[PULL 01/12] MAINTAINERS: aspeed: Update Andrew's email address
-From: Joel Stanley <joel@jms.id.au>
+From: Andrew Jeffery <andrew@codeconstruct.com.au>
-The model includes aspeed_scu.h but doesn't appear to require it.
+I've changed employers, have company email that deals with patch-based
 workflows without too much of a headache, and am trying to steer some
 content out of my personal mail.
-Signed-off-by: Joel Stanley <joel@jms.id.au>
+Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-Id: <20230124062022.298230-1-joel@jms.id.au>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/misc/aspeed_sdmc.c | 1 -
+ MAINTAINERS | 2 +-
-file changed, 1 deletion(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/aspeed_sdmc.c
+--- a/MAINTAINERS
-+++ b/hw/misc/aspeed_sdmc.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/emcraft-sf2.rst
- #include "qemu/module.h"
+ ASPEED BMCs
- #include "qemu/error-report.h"
+ M: Cédric Le Goater <clg@kaod.org>
- #include "hw/misc/aspeed_sdmc.h"
+ M: Peter Maydell <peter.maydell@linaro.org>
--#include "hw/misc/aspeed_scu.h"
+-R: Andrew Jeffery <andrew@aj.id.au>
- #include "hw/qdev-properties.h"
++R: Andrew Jeffery <andrew@codeconstruct.com.au>
- #include "migration/vmstate.h"
+ R: Joel Stanley <joel@jms.id.au>
- #include "qapi/error.h"
+ L: qemu-arm@nongnu.org
  S: Maintained
 --
-.39.1
+.41.0

-[PULL 13/25] hw/arm/aspeed: Add aspeed_eeprom.c
+[PULL 02/12] hw/arm/aspeed: Extract code common to all boards to a common file
-From: Peter Delevoryas <peter@pjd.dev>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-- Create aspeed_eeprom.c and aspeed_eeprom.h
+aspeed_soc.c contains definitions specific to the AST2400
-- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
+and AST2500 SoCs, but also some definitions for other AST
-- Include aspeed_eeprom.h in aspeed.c
+SoCs: move them to a common file.
-- Add fby35_bmc_fruid data
-- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
   from aspeed_eeprom.c
 wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
 qemu-system-aarch64 -machine fby35-bmc -nographic -mtdblock fby35.mtd
 ...
 user: root
 pass: 0penBmc
 ...
 root@bmc-oob:~# fruid-util bb
 FRU Information           : Baseboard
 ---------------           : ------------------
 Chassis Type              : Rack Mount Chassis
 Chassis Part Number       : N/A
 Chassis Serial Number     : N/A
 Board Mfg Date            : Fri Jan  7 10:30:00 2022
 Board Mfg                 : XXXXXX
 Board Product             : Management Board wBMC
 Board Serial              : XXXXXXXXXXXXX
 Board Part Number         : XXXXXXXXXXXXXX
 Board FRU ID              : 1.0
 Board Custom Data 1       : XXXXXXXXX
 Board Custom Data 2       : XXXXXXXXXXXXXXXXXX
 Product Manufacturer      : XXXXXX
 Product Name              : Yosemite V3.5 EVT2
 Product Part Number       : XXXXXXXXXXXXXX
 Product Version           : EVT2
 Product Serial            : XXXXXXXXXXXXX
 Product Asset Tag         : XXXXXXX
 Product FRU ID            : 1.0
 Product Custom Data 1     : XXXXXXXXX
 Product Custom Data 2     : N/A
 root@bmc-oob:~# fruid-util bmc
 FRU Information           : BMC
 ---------------           : ------------------
 Board Mfg Date            : Mon Jan 10 21:42:00 2022
 Board Mfg                 : XXXXXX
 Board Product             : BMC Storage Module
 Board Serial              : XXXXXXXXXXXXX
 Board Part Number         : XXXXXXXXXXXXXX
 Board FRU ID              : 1.0
 Board Custom Data 1       : XXXXXXXXX
 Board Custom Data 2       : XXXXXXXXXXXXXXXXXX
 Product Manufacturer      : XXXXXX
 Product Name              : Yosemite V3.5 EVT2
 Product Part Number       : XXXXXXXXXXXXXX
 Product Version           : EVT2
 Product Serial            : XXXXXXXXXXXXX
 Product Asset Tag         : XXXXXXX
 Product FRU ID            : 1.0
 Product Custom Data 1     : XXXXXXXXX
 Product Custom Data 2     : Config A
 root@bmc-oob:~# fruid-util nic
 FRU Information           : NIC
 ---------------           : ------------------
 Board Mfg Date            : Tue Nov  2 08:51:00 2021
 Board Mfg                 : XXXXXXXX
 Board Product             : Mellanox ConnectX-6 DX OCP3.0
 Board Serial              : XXXXXXXXXXXXXXXXXXXXXXXX
 Board Part Number         : XXXXXXXXXXXXXXXXXXXXX
 Board FRU ID              : FRU Ver 0.02
 Product Manufacturer      : XXXXXXXX
 Product Name              : Mellanox ConnectX-6 DX OCP3.0
 Product Part Number       : XXXXXXXXXXXXXXXXXXXXX
 Product Version           : A9
 Product Serial            : XXXXXXXXXXXXXXXXXXXXXXXX
 Product Custom Data 3     : ConnectX-6 DX
 Signed-off-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Corey Minyard <cminyard@mvista.com>
-Link: https://lore.kernel.org/r/20230128060543.95582-5-peter@pjd.dev
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_eeprom.h | 19 ++++++++++
+ hw/arm/aspeed_soc.c        |  96 -------------------------------
- hw/arm/aspeed.c        | 10 ++++--
+ hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
- hw/arm/aspeed_eeprom.c | 82 ++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/meson.build         |   1 +
- hw/arm/meson.build     |  1 +
+files changed, 115 insertions(+), 96 deletions(-)
-files changed, 109 insertions(+), 3 deletions(-)
+ create mode 100644 hw/arm/aspeed_soc_common.c
- create mode 100644 hw/arm/aspeed_eeprom.h
- create mode 100644 hw/arm/aspeed_eeprom.c
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+index XXXXXXX..XXXXXXX 100644
-diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
+--- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
  };
  type_init(aspeed_soc_register_types);
 -
 -qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
 -{
 -    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
 -}
 -
 -bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    SerialMM *smm;
 -
 -    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 -        smm = &s->uart[i];
 -
 -        /* Chardev property is set by the machine. */
 -        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 -        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 -        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 -        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 -        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 -            return false;
 -        }
 -
 -        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 -        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 -    }
 -
 -    return true;
 -}
 -
 -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    int i = dev - ASPEED_DEV_UART1;
 -
 -    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 -    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 -}
 -
 -/*
 - * SDMC should be realized first to get correct RAM size and max size
 - * values
 - */
 -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    ram_addr_t ram_size, max_ram_size;
 -
 -    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 -                                        &error_abort);
 -    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 -                                            &error_abort);
 -
 -    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 -                       max_ram_size);
 -    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 -
 -    /*
 -     * Add a memory region beyond the RAM region to let firmwares scan
 -     * the address space with load/store and guess how much RAM the
 -     * SoC has.
 -     */
 -    if (ram_size < max_ram_size) {
 -        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 -
 -        qdev_prop_set_string(dev, "name", "ram-empty");
 -        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 -        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 -            return false;
 -        }
 -
 -        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 -                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 -    }
 -
 -    memory_region_add_subregion(s->memory,
 -                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 -    return true;
 -}
 -
 -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 -{
 -    memory_region_add_subregion(s->memory, addr,
 -                                sysbus_mmio_get_region(dev, n));
 -}
 -
 -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 -                                   const char *name, hwaddr addr, uint64_t size)
 -{
 -    qdev_prop_set_string(DEVICE(dev), "name", name);
 -    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 -    sysbus_realize(dev, &error_abort);
 -
 -    memory_region_add_subregion_overlap(s->memory, addr,
 -                                        sysbus_mmio_get_region(dev, 0), -1000);
 -}
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/arm/aspeed_eeprom.h
++++ b/hw/arm/aspeed_soc_common.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Copyright (c) Meta Platforms, Inc. and affiliates.
++ * ASPEED SoC family
 + *
-+ * SPDX-License-Identifier: GPL-2.0-only
++ * Andrew Jeffery <andrew@aj.id.au>
 + * Jeremy Kerr <jk@ozlabs.org>
 + *
 + * Copyright 2016 IBM Corp.
 + *
 + * This code is licensed under the GPL version 2 or later.  See
 + * the COPYING file in the top-level directory.
 + */
 +
-+#ifndef ASPEED_EEPROM_H
-+#define ASPEED_EEPROM_H
-+
 +#include "qemu/osdep.h"
-+
++#include "qapi/error.h"
-+extern const uint8_t fby35_nic_fruid[];
++#include "hw/misc/unimp.h"
-+extern const uint8_t fby35_bb_fruid[];
++#include "hw/arm/aspeed_soc.h"
-+extern const uint8_t fby35_bmc_fruid[];
++#include "hw/char/serial.h"
-+extern const size_t fby35_nic_fruid_len;
++
-+extern const size_t fby35_bb_fruid_len;
++
-+extern const size_t fby35_bmc_fruid_len;
++qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-+
++{
-+#endif
++    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
++}
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/arm/aspeed.c
++bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-+++ b/hw/arm/aspeed.c
++{
-@@ -XXX,XX +XXX,XX @@
++    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- #include "hw/arm/boot.h"
++    SerialMM *smm;
- #include "hw/arm/aspeed.h"
++
- #include "hw/arm/aspeed_soc.h"
++    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-+#include "hw/arm/aspeed_eeprom.h"
++        smm = &s->uart[i];
- #include "hw/i2c/i2c_mux_pca954x.h"
++
- #include "hw/i2c/smbus_eeprom.h"
++        /* Chardev property is set by the machine. */
- #include "hw/misc/pca9552.h"
++        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
++        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
++        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
-     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
++        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
-     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
++        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
--    at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
++            return false;
--    at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
++        }
--    at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
++
-+    at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
++        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-+                          fby35_nic_fruid_len);
++        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-+    at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
++    }
-+                          fby35_bb_fruid_len);
++
-+    at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
++    return true;
-+                          fby35_bmc_fruid_len);
++}
++
-     /*
++void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
++{
-diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
++    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-new file mode 100644
++    int i = dev - ASPEED_DEV_UART1;
-index XXXXXXX..XXXXXXX
++
---- /dev/null
++    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
-+++ b/hw/arm/aspeed_eeprom.c
++    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-@@ -XXX,XX +XXX,XX @@
++}
 +
 +/*
-+ * Copyright (c) Meta Platforms, Inc. and affiliates.
++ * SDMC should be realized first to get correct RAM size and max size
-+ *
++ * values
 + * SPDX-License-Identifier: GPL-2.0-only
 + */
-+
++bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-+#include "aspeed_eeprom.h"
++{
-+
++    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-+const uint8_t fby35_nic_fruid[] = {
++    ram_addr_t ram_size, max_ram_size;
-+    0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
++
-+    0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
++    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-+    0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
++                                        &error_abort);
-+    0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
++    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-+    0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++                                            &error_abort);
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
++    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++                       max_ram_size);
-+    0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
++    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-+    0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
++
-+    0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++    /*
-+    0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
++     * Add a memory region beyond the RAM region to let firmwares scan
-+    0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
++     * the address space with load/store and guess how much RAM the
-+    0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
++     * SoC has.
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++     */
-+    0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
++    if (ram_size < max_ram_size) {
-+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
++        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-+    0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++        qdev_prop_set_string(dev, "name", "ram-empty");
-+    0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
++        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-+    0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
++        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-+    0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
++            return false;
-+    0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
++        }
-+    0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
++        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-+    0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
++                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-+};
++    }
 +
-+const uint8_t fby35_bb_fruid[] = {
++    memory_region_add_subregion(s->memory,
-+    0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
++                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-+    0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
++    return true;
-+    0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
++}
-+    0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
++
-+    0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
++void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++{
-+    0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++    memory_region_add_subregion(s->memory, addr,
-+    0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
++                                sysbus_mmio_get_region(dev, n));
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
++}
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++
-+    0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
++void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
++                                   const char *name, hwaddr addr, uint64_t size)
-+    0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
++{
-+    0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
++    qdev_prop_set_string(DEVICE(dev), "name", name);
-+    0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
++    qdev_prop_set_uint64(DEVICE(dev), "size", size);
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
++    sysbus_realize(dev, &error_abort);
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
++
-+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
++    memory_region_add_subregion_overlap(s->memory, addr,
-+    0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
++                                        sysbus_mmio_get_region(dev, 0), -1000);
-+};
++}
 +
 +const uint8_t fby35_bmc_fruid[] = {
 +    0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
 +    0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
 +    0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
 +    0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
 +    0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
 +    0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
 +    0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
 +    0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
 +    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
 +    0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
 +};
 +
 +const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
 +const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
 +const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
-@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
  arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
    'aspeed_soc.c',
    'aspeed.c',
++  'aspeed_soc_common.c',
    'aspeed_ast2600.c',
    'aspeed_ast10x0.c',
-+  'aspeed_eeprom.c',
+   'aspeed_eeprom.c',
    'fby35.c'))
  arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
  arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
 --
-.39.1
+.41.0

-[PULL 02/25] tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiB
+[PULL 03/12] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-The M2S-FG484 SOM uses a 16 MiB SPI flash (Spansion
-S25FL128SDPBHICO).  Since the test asset is bigger,
-truncate it to the correct size to avoid when running
-the test_arm_emcraft_sf2 test:
-  qemu-system-arm: device requires 16777216 bytes, block backend provides 67108864 bytes
-Add comment regarding the M2S-FG484 SOM hardware in
-hw/arm/msf2-som.c.
-Reported-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Tested-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/msf2-som.c                   | 5 ++++-
+ hw/arm/aspeed_soc.c | 6 +++---
- tests/avocado/boot_linux_console.py | 2 ++
+file changed, 3 insertions(+), 3 deletions(-)
 files changed, 6 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/msf2-som.c
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/arm/msf2-som.c
++++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
- /*
+     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
-  * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ }
-  *
-+ * M2S-FG484 SOM hardware architecture specification:
+-static void aspeed_soc_init(Object *obj)
-+ *   https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
++static void aspeed_ast2400_soc_init(Object *obj)
-+ *
+ {
-  * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+     AspeedSoCState *s = ASPEED_SOC(obj);
-  *
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-  * Permission is hereby granted, free of charge, to any person obtaining a copy
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
+ static const TypeInfo aspeed_soc_ast2400_type_info = {
+     .name           = "ast2400-a1",
-     /* Attach SPI flash to SPI0 controller */
+     .parent         = TYPE_ASPEED_SOC,
-     spi_bus = qdev_get_child_bus(dev, "spi0");
+-    .instance_init  = aspeed_soc_init,
--    spi_flash = qdev_new("s25sl12801");
++    .instance_init  = aspeed_ast2400_soc_init,
-+    spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */
+     .instance_size  = sizeof(AspeedSoCState),
-     qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
+     .class_init     = aspeed_soc_ast2400_class_init,
-     if (dinfo) {
+ };
-         qdev_prop_set_drive_err(spi_flash, "drive",
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
-diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
+ static const TypeInfo aspeed_soc_ast2500_type_info = {
-index XXXXXXX..XXXXXXX 100644
+     .name           = "ast2500-a1",
---- a/tests/avocado/boot_linux_console.py
+     .parent         = TYPE_ASPEED_SOC,
-+++ b/tests/avocado/boot_linux_console.py
+-    .instance_init  = aspeed_soc_init,
-@@ -XXX,XX +XXX,XX @@ def test_arm_emcraft_sf2(self):
++    .instance_init  = aspeed_ast2400_soc_init,
-         spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
+     .instance_size  = sizeof(AspeedSoCState),
-         spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
+     .class_init     = aspeed_soc_ast2500_class_init,
+ };
 +        file_truncate(spi_path, 16 << 20) # Spansion S25FL128SDPBHICO is 16 MiB
 +
          self.vm.set_console()
          kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE
          self.vm.add_args('-kernel', uboot_path,
 --
-.39.1
+.41.0

-[PULL 24/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
+[PULL 04/12] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Add a very quick test that runs some commands in a Zephyr shell:
+Keep aspeed_soc_class_init() generic, set the realize handler
+to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
   $ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
   (2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07:
   console: *** Booting Zephyr OS build v00.01.07  ***
   console: ast1030_evb demo
   console: SOC: AST1030-A1
   console: uart:~$ kernel stacks
   console: 0x36910 wdt_background (real size 1024):    unused 988    usage 36 / 1024 (3 %)
   console: 0x36ad8 shell_uart (real size 4096):    unused 3084    usage 1012 / 4096 (24 %)
   console: 0x2edb8 ADC0       (real size 400):    unused 260    usage 140 / 400 (35 %)
   console: 0x2f0f0 ADC1       (real size 400):    unused 260    usage 140 / 400 (35 %)
   console: 0x3b098 sysworkq   (real size 1024):    unused 860    usage 164 / 1024 (16 %)
   console: 0x36cc0 usbdworkq  (real size 1024):    unused 860    usage 164 / 1024 (16 %)
   console: 0x36bd8 usbworkq   (real size 1024):    unused 860    usage 164 / 1024 (16 %)
   console: 0x36a10 logging    (real size 768):    unused 548    usage 220 / 768 (28 %)
   console: 0x36ef8 idle 00    (real size 320):    unused 268    usage 52 / 320 (16 %)
   console: 0x47800 IRQ 00     (real size 2048):    unused 1504    usage 544 / 2048 (26 %)
   console: uart:~$ otp info scu
   console: SCU     BIT   reg_protect     Description
   console: ____________________________________________________________________
   console: 0x500   0x0   0x0             Disable ARM CM4 CPU boot (TXD5)
   console: 0x500   0x1   0x0            /Reserved
   console: 0x500   0x2   0x0            \ "
   console: 0x500   0x3   0x0             Address offset of single chip ABR mode
   console: 0x500   0x4   0x0            /Reserved
   console: 0x500   0x5   0x0            | "
   console: 0x500   0x6   0x0            | "
   console: 0x500   0x7   0x0            | "
   console: 0x500   0x8   0x0            | "
   console: 0x500   0x9   0x0            | "
   console: 0x500   0xA   0x0            | "
   console: 0x500   0xB   0x0            | "
   console: 0x500   0xC   0x0            | "
   console: 0x500   0xD   0x0            | "
   console: 0x500   0xE   0x0            | "
   console: 0x500   0xF   0x0            | "
   console: 0x500   0x10  0x0            \ "
   console: 0x500   0x11  0x0             Disabl3 ARM JTAG debug
   console: 0x500   0x12  0x0            /Reserved
   console: 0x500   0x13  0x0            | "
   console: 0x500   0x14  0x0            | "
   console: 0x500   0x15  0x0            | "
   console: 0x500   0x16  0x0            | "
   console: 0x500   0x17  0x0            | "
   console: 0x500   0x18  0x0            | "
   console: 0x500   0x19  0x0            | "
   console: 0x500   0x1A  0x0            | "
   console: 0x500   0x1B  0x0            | "
   console: 0x500   0x1C  0x0            | "
   console: 0x500   0x1D  0x0            | "
   console: 0x500   0x1E  0x0            | "
   console: 0x500   0x1F  0x0            \ "
   console: 0x510   0x0   0x0            /Reserved
   console: 0x510   0x1   0x0            | "
   console: 0x510   0x2   0x0            | "
   console: 0x510   0x3   0x0            \ "
   console: 0x510   0x4   0x0             Disable debug interfaces
   console: 0x510   0x5   0x0            /Reserved
   console: 0x510   0x6   0x0            | "
   console: 0x510   0x7   0x0            \ "
   console: 0x510   0x8   0x0             Enable boot from Uart5 by Pin Strap
   console: 0x510   0x9   0x0            /Reserved
   console: 0x510   0xA   0x0            \ "
   console: 0x510   0xB   0x0             Enable boot SPI ABR
   console: 0x510   0xC   0x0             Boot SPI ABR Mode
   console: 0x510   0xD   0x0            /Boot SPI flash size
   console: 0x510   0xE   0x0            | "
   console: 0x510   0xF   0x0            \ "
   console: 0x510   0x10  0x0            /Reserved
   console: 0x510   0x11  0x0            | "
   console: 0x510   0x12  0x0            | "
   console: 0x510   0x13  0x0            | "
   console: 0x510   0x14  0x0            | "
   console: 0x510   0x15  0x0            \ "
   console: 0x510   0x16  0x0             Enable boot SPI auxiliary control pins
   console: 0x510   0x19  0x0            /Reserved
   console: 0x510   0x1A  0x0            | "
   console: 0x510   0x1B  0x0            | "
   console: 0x510   0x1C  0x0            | "
   console: 0x510   0x1D  0x0            | "
   console: 0x510   0x1E  0x0            | "
   console: 0x510   0x1F  0x0            \ "
   console: 0x510   0x1E  0x0             Enable dedicate GPIO strap pins
   console: 0x510   0x1F  0x0             Enable Secure Boot by Pin Strap
   console: uart:~$ hwinfo devid
   console: Length: 8
   console: ID: 0x0000018000000180
   console: uart:~$ crypto aes256_cbc_vault
   console: aes256_cbc vault key 1
   console: Was waiting for:
   console: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
   console: ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
   console: 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
   console: f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
   console: But got:
   console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
   console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
   console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
   console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
   console: uart:~$ random get
   console: 0x862460d
   console: uart:~$ i2c scan I2C_0
   console: 0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
   console: 00:             -- -- -- -- -- -- -- -- -- -- -- --
   console: 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
   console: 70: -- -- -- -- -- -- -- --
   console: 1 devices found on I2C_0
   console: uart:~$ kernel uptime
   console: Uptime: 9897 ms
   console: uart:~$ kernel reboot warm
   console: *** Booting Zephyr OS build v00.01.07  ***
   PASS (1.08 s)
 Ref: https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.07/Aspeed_Zephy_SDK_User_Guide_v00.01.07.pdf
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- tests/avocado/machine_aspeed.py | 41 ++++++++++++++++++++++++++++++++-
+ hw/arm/aspeed_soc.c | 15 +++++++++++----
-file changed, 40 insertions(+), 1 deletion(-)
+file changed, 11 insertions(+), 4 deletions(-)
-diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/machine_aspeed.py
+--- a/hw/arm/aspeed_soc.c
-+++ b/tests/avocado/machine_aspeed.py
++++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@ class AST1030Machine(QemuSystemTest):
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
+     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
-     timeout = 10
+ }
--    def test_ast1030_zephyros(self):
+-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
-+    def test_ast1030_zephyros_1_04(self):
++static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-         """
+ {
-         :avocado: tags=arch:arm
+     int i;
-         :avocado: tags=machine:ast1030-evb
+     AspeedSoCState *s = ASPEED_SOC(dev);
-+        :avocado: tags=os:zephyr
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-         """
+ {
-         tar_url = ('https://github.com/AspeedTech-BMC'
+     DeviceClass *dc = DEVICE_CLASS(oc);
-                    '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
-@@ -XXX,XX +XXX,XX @@ def test_ast1030_zephyros(self):
+-    dc->realize = aspeed_soc_realize;
-         exec_command_and_wait_for_pattern(self, "help",
+-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-                                           "Available commands")
+-    dc->user_creatable = false;
+     device_class_set_props(dc, aspeed_soc_properties);
-+    def test_ast1030_zephyros_1_07(self):
+ }
-+        """
-+        :avocado: tags=arch:arm
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
-+        :avocado: tags=machine:ast1030-evb
+ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-+        :avocado: tags=os:zephyr
+ {
-+        """
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-+        tar_url = ('https://github.com/AspeedTech-BMC'
++    DeviceClass *dc = DEVICE_CLASS(oc);
 +                   '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip')
 +        tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2'
 +        tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
 +        archive.extract(tar_path, self.workdir)
 +        kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin"
 +        self.vm.set_console()
 +        self.vm.add_args('-kernel', kernel_file,
 +                         '-nographic')
 +        self.vm.launch()
 +        wait_for_console_pattern(self, "Booting Zephyr OS")
 +        for shell_cmd in [
 +                'kernel stacks',
 +                'otp info conf',
 +                'otp info scu',
 +                'hwinfo devid',
 +                'crypto aes256_cbc_vault',
 +                'random get',
 +                'jtag JTAG1 sw_xfer high TMS',
 +                'adc ADC0 resolution 12',
 +                'adc ADC0 read 42',
 +                'adc ADC1 read 69',
 +                'i2c scan I2C_0',
 +                'i3c attach I3C_0',
 +                'hash test',
 +                'kernel uptime',
 +                'kernel reboot warm',
 +                'kernel uptime',
 +                'kernel reboot cold',
 +                'kernel uptime',
 +        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
 +
- class AST2x00Machine(QemuSystemTest):
++    dc->realize = aspeed_ast2400_soc_realize;
++    /* Reason: Uses serial_hds and nd_table in realize() directly */
-     timeout = 90
++    dc->user_creatable = false;
      sc->name         = "ast2400-a1";
      sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = aspeed_ast2400_soc_realize;
 +    /* Reason: Uses serial_hds and nd_table in realize() directly */
 +    dc->user_creatable = false;
      sc->name         = "ast2500-a1";
      sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
 --
-.39.1
+.41.0

-[PULL 03/25] aspeed: Add Supermicro X11 SPI machine type
+[PULL 05/12] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
-From: Guenter Roeck <linux@roeck-us.net>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
+We want to derivate the big AspeedSoCState object in some more
-the Supermicro documentation for X11 BMCs, and it does not match the
+SoC-specific ones. Since the object size will vary, allocate it
-devicetree file in the Linux kernel.
+dynamically.
-As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-while others use AST2500.
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
 to match the devicetree description in the Linux kernel. Hardware
 configuration details for this machine type are guesswork and taken
 from defaults as well as from the Linux kernel devicetree file.
 The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts
 from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2.
 Linux booted successfully from initrd and from both SPI interfaces.
 Ethernet interfaces were confirmed to be operational.
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net
 [ clg: Renamed machine to 'supermicro-x11spi-bmc' ]
 Message-Id: <20221025165109.1226001-1-linux@roeck-us.net>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 33 +++++++++++++++++++++++++++++++++
+ hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
-file changed, 33 insertions(+)
+file changed, 52 insertions(+), 49 deletions(-)
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
 @@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
-         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
+     MachineState parent_obj;
-         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+     /* Public */
-+/* TODO: Find the actual hardware value */
+-    AspeedSoCState soc;
-+#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
++    AspeedSoCState *soc;
-+        AST2500_HW_STRAP1_DEFAULTS |                                    \
+     MemoryRegion boot_rom;
-+        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
+     bool mmio_exec;
-+        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
+     uint32_t uart_chosen;
-+        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
+@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
-+        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
+ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
-+        SCU_HW_STRAP_SPI_WIDTH |                                        \
+                                     uint64_t rom_size)
-+        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
+ {
-+
+-    AspeedSoCState *soc = &bmc->soc;
- /* AST2500 evb hardware value: 0xF100C2E6 */
++    AspeedSoCState *soc = bmc->soc;
- #define AST2500_EVB_HW_STRAP1 ((                                        \
-         AST2500_HW_STRAP1_DEFAULTS |                                    \
+     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
+                            &error_abort);
-     mc->default_ram_size = 256 * MiB;
+@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
  static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
  {
      AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
 -    AspeedSoCState *s = &bmc->soc;
 +    AspeedSoCState *s = bmc->soc;
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
      int i;
      NICInfo *nd = &nd_table[0];
 -    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 -
 -    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 +    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
 +    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
 +    object_unref(OBJECT(bmc->soc));
 +    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
      /*
       * This will error out if the RAM size is not supported by the
       * memory controller of the SoC.
       */
 -    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 +    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                               &error_fatal);
      for (i = 0; i < sc->macs_num; i++) {
          if ((amc->macs_mask & (1 << i)) && nd->used) {
              qemu_check_nic_model(nd, TYPE_FTGMAC100);
 -            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 +            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
              nd++;
          }
      }
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                              &error_abort);
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                              &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "memory",
 +    object_property_set_link(OBJECT(bmc->soc), "memory",
                               OBJECT(get_system_memory()), &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "dram",
 +    object_property_set_link(OBJECT(bmc->soc), "dram",
                               OBJECT(machine->ram), &error_abort);
      if (machine->kernel_filename) {
          /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
           * that runs to unlock the SCU. In this case set the default to
           * be unlocked as the kernel expects
           */
 -        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 +        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                  ASPEED_SCU_PROT_KEY, &error_abort);
      }
      connect_serial_hds_to_uarts(bmc);
 -    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 +    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
      if (defaults_enabled()) {
 -        aspeed_board_init_flashes(&bmc->soc.fmc,
 +        aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs, 0);
 -        aspeed_board_init_flashes(&bmc->soc.spi[0],
 +        aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
 , amc->num_cs);
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          amc->i2c_init(bmc);
      }
 -    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 -        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 +    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
 +        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                             drive_get(IF_SD, 0, i));
      }
 -    if (bmc->soc.emmc.num_slots) {
 -        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 -                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 +    if (bmc->soc->emmc.num_slots) {
 +        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
 +                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
      }
      if (!bmc->mmio_exec) {
 -        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
 +        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
          BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
          if (fmc0) {
 -            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 +            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
              aspeed_install_boot_rom(bmc, fmc0, rom_size);
          }
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
  static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /*
       * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
       * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
  static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* bus 2 : */
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
          {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
          {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
      };
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      DeviceState *dev;
      LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
  static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
  static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[144] = {};
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[13] = {};
      for (int i = 0; i < 13; i++) {
          if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  static void fby35_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[16];
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
  static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
  }
-+static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
+ static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
-+                                                            void *data)
+ {
-+{
+-    AspeedSoCState *soc = &bmc->soc;
-+    MachineClass *mc = MACHINE_CLASS(oc);
++    AspeedSoCState *soc = bmc->soc;
-+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+     I2CSlave *therm_mux, *cpuvr_mux;
-+
-+    mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
+     /* Create the generic DC-SCM hardware */
-+    amc->soc_name  = "ast2500-a1";
+@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
-+    amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
+ static void fby35_reset(MachineState *state, ShutdownCause reason)
-+    amc->fmc_model = "mx25l25635e";
+ {
-+    amc->spi_model = "mx25l25635e";
+     AspeedMachineState *bmc = ASPEED_MACHINE(state);
-+    amc->num_cs    = 1;
+-    AspeedGPIOState *gpio = &bmc->soc.gpio;
-+    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
++    AspeedGPIOState *gpio = &bmc->soc->gpio;
-+    amc->i2c_init  = palmetto_bmc_i2c_init;
-+    mc->default_ram_size = 512 * MiB;
+     qemu_devices_reset(reason);
-+    mc->default_cpus = mc->min_cpus = mc->max_cpus =
-+        aspeed_soc_num_cpus(amc->soc_name);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
-+}
+     sysclk = clock_new(OBJECT(machine), "SYSCLK");
-+
+     clock_set_hz(sysclk, SYSCLK_FRQ);
- static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
- {
+-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-     MachineClass *mc = MACHINE_CLASS(oc);
+-    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
++    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
-         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
++    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
-         .parent        = TYPE_ASPEED_MACHINE,
++    object_unref(OBJECT(bmc->soc));
-         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
++    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
-+    }, {
-+        .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
+-    object_property_set_link(OBJECT(&bmc->soc), "memory",
-+        .parent        = TYPE_ASPEED_MACHINE,
++    object_property_set_link(OBJECT(bmc->soc), "memory",
-+        .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
+                              OBJECT(get_system_memory()), &error_abort);
-     }, {
+     connect_serial_hds_to_uarts(bmc);
-         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
+-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
-         .parent        = TYPE_ASPEED_MACHINE,
++    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 -    aspeed_board_init_flashes(&bmc->soc.fmc,
 +    aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs,
 );
 -    aspeed_board_init_flashes(&bmc->soc.spi[0],
 +    aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, amc->num_cs);
 -    aspeed_board_init_flashes(&bmc->soc.spi[1],
 +    aspeed_board_init_flashes(&bmc->soc->spi[1],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, (amc->num_cs * 2));
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
  static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* U10 24C08 connects to SDA/SCL Group 1 by default */
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 --
-.39.1
+.41.0

-[PULL 04/25] hw/net: Fix read of uninitialized memory in ftgmac100
+Deleted patch
-From: Stephen Longfield <slongfield@google.com>
-With the `size += 4` before the call to `crc32`, the CRC calculation
-would overrun the buffer. Size is used in the while loop starting on
-line 1009 to determine how much data to write back, with the last
-four bytes coming from `crc_ptr`, so do need to increase it, but should
-do this after the computation.
-I'm unsure why this use of uninitialized memory in the CRC doesn't
-result in CRC errors, but it seems clear to me that it should not be
-included in the calculation.
-Signed-off-by: Stephen Longfield <slongfield@google.com>
-Reviewed-by: Hao Wu <wuhaotsh@google.com>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-Id: <20221220221437.3303721-1-slongfield@google.com>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/net/ftgmac100.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/net/ftgmac100.c
-+++ b/hw/net/ftgmac100.c
-@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
-         return size;
-     }
--    /* 4 bytes for the CRC.  */
--    size += 4;
-     crc = cpu_to_be32(crc32(~0, buf, size));
-+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
-+    size += 4;
-     crc_ptr = (uint8_t *) &crc;
-     /* Huge frames are truncated.  */
---
-.39.1

-[PULL 05/25] avocado/boot_linux_console.py: Update ast2600 test
+Deleted patch
-From: Joel Stanley <joel@jms.id.au>
-Update the test_arm_ast2600_debian test to
- - the latest Debian kernel
- - use the Rainier machine instead of Tacoma
-Both of which contains support for more hardware and thus exercises more
-of the hardware Qemu models.
-Signed-off-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- tests/avocado/boot_linux_console.py | 12 ++++++------
-file changed, 6 insertions(+), 6 deletions(-)
-diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/boot_linux_console.py
-+++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ def test_arm_vexpressa9(self):
-     def test_arm_ast2600_debian(self):
-         """
-         :avocado: tags=arch:arm
--        :avocado: tags=machine:tacoma-bmc
-+        :avocado: tags=machine:rainier-bmc
-         """
-         deb_url = ('http://snapshot.debian.org/archive/debian/'
--                   '20210302T203551Z/'
-+                   '20220606T211338Z/'
-                    'pool/main/l/linux/'
--                   'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
--        deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
-+                   'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
-+        deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
-         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
-                                     algorithm='sha256')
--        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
-+        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
-         dtb_path = self.extract_from_deb(deb_path,
--                '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
-+                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
-         self.vm.set_console()
-         self.vm.add_args('-kernel', kernel_path,
---
-.39.1

-[PULL 06/25] m25p80: Add the is25wp256 SFPD table
+Deleted patch
-From: Guenter Roeck <linux@roeck-us.net>
-Generated from hardware using the following command and then padding
-with 0xff to fill out a power-of-2:
-    xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
-Cc: Michael Walle <michael@walle.cc>
-Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-Id: <20221221122213.1458540-1-linux@roeck-us.net>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/block/m25p80_sfdp.h |  2 ++
- hw/block/m25p80.c      |  3 ++-
- hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
-files changed, 44 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
-+++ b/hw/block/m25p80_sfdp.h
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
- uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
-+uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
-+
- #endif
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
-     { INFO("is25wp032",   0x9d7016,      0,  64 << 10,  64, ER_4K) },
-     { INFO("is25wp064",   0x9d7017,      0,  64 << 10, 128, ER_4K) },
-     { INFO("is25wp128",   0x9d7018,      0,  64 << 10, 256, ER_4K) },
--    { INFO("is25wp256",   0x9d7019,      0,  64 << 10, 512, ER_4K) },
-+    { INFO("is25wp256",   0x9d7019,      0,  64 << 10, 512, ER_4K),
-+      .sfdp_read = m25p80_sfdp_is25wp256 },
-     /* Macronix */
-     { INFO("mx25l2005a",  0xc22012,      0,  64 << 10,   4, ER_4K) },
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.c
-+++ b/hw/block/m25p80_sfdp.c
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q01jvq[] = {
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- };
- define_sfdp_read(w25q01jvq);
-+
-+/*
-+ * Integrated Silicon Solution (ISSI)
-+ */
-+
-+static const uint8_t sfdp_is25wp256[] = {
-+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
-+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
-+    0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
-+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
-+    0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
-+    0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
-+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
-+    0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
-+    0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+};
-+define_sfdp_read(is25wp256);
---
-.39.1

-[PULL 07/25] tests/avocado/machine_aspeed.py: update buildroot tests
+Deleted patch
-Use buildroot 2022.11 based images plus some customization :
-  - Linux version is bumped to 6.0.9 and kernel is built with a custom
-    config similar to what OpenBMC provides.
-  - U-Boot is switched to the one provided by OpenBMC for better support.
-  - defconfigs includes more target tools for dev.
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-Id: <20230119123449.531826-7-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- tests/avocado/machine_aspeed.py | 8 ++++----
-file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/machine_aspeed.py
-+++ b/tests/avocado/machine_aspeed.py
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self):
-         """
-         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
--                     'images/ast2500-evb/buildroot-2022.05/flash.img')
--        image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
-+                     'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-+        image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
-         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
-                                       algorithm='sha256')
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
-         """
-         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
--                     'images/ast2600-evb/buildroot-2022.05/flash.img')
--        image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
-+                     'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
-+        image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
-         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
-                                       algorithm='sha256')
---
-.39.1

-[PULL 08/25] tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
+Deleted patch
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-Id: <20230119123449.531826-8-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- tests/avocado/machine_aspeed.py | 11 +++++++++--
-file changed, 9 insertions(+), 2 deletions(-)
-diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/machine_aspeed.py
-+++ b/tests/avocado/machine_aspeed.py
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
- class AST2x00MachineSDK(QemuSystemTest):
--    EXTRA_BOOTARGS = ' quiet'
-+    EXTRA_BOOTARGS = (
-+        'quiet '
-+        'systemd.mask=org.openbmc.HostIpmi.service '
-+        'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
-+        'systemd.mask=modprobe@fuse.service '
-+        'systemd.mask=rngd.service '
-+        'systemd.mask=obmc-console@ttyS2.service '
-+    )
-     # FIXME: Although these tests boot a whole distro they are still
-     # slower than comparable machine models. There may be some
-@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image):
-         interrupt_interactive_console_until_pattern(
-             self, 'Hit any key to stop autoboot:', 'ast#')
-         exec_command_and_wait_for_pattern(
--            self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
-+            self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
-         exec_command_and_wait_for_pattern(
-             self, 'boot', '## Loading kernel from FIT Image')
-         self.wait_for_console_pattern('Starting kernel ...')
---
-.39.1

-[PULL 09/25] hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
+Deleted patch
-These globals were moved to MachineClass by commit 71ae9e94d9 ("pc: Move
-option_rom_has_mr/rom_file_has_mr globals to MachineClass"). Finish cleanup.
-Cc: Eduardo Habkost <ehabkost@redhat.com>
-Cc: Marcel Apfelbaum <marcel@redhat.com>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- include/hw/loader.h | 3 ---
-file changed, 3 deletions(-)
-diff --git a/include/hw/loader.h b/include/hw/loader.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/loader.h
-+++ b/include/hw/loader.h
-@@ -XXX,XX +XXX,XX @@ void pstrcpy_targphys(const char *name,
-                       hwaddr dest, int buf_size,
-                       const char *source);
--extern bool option_rom_has_mr;
--extern bool rom_file_has_mr;
--
- ssize_t rom_add_file(const char *file, const char *fw_dir,
-                      hwaddr addr, int32_t bootindex,
-                      bool option_rom, MemoryRegion *mr, AddressSpace *as);
---
-.39.1

-[PULL 10/25] hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
+Deleted patch
-From: Peter Delevoryas <peter@pjd.dev>
-This helper is useful in board initialization because lets users initialize and
-realize an EEPROM on an I2C bus with a single function call.
-Signed-off-by: Peter Delevoryas <peter@pjd.dev>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Corey Minyard <cminyard@mvista.com>
-Link: https://lore.kernel.org/r/20230128060543.95582-2-peter@pjd.dev
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- include/hw/nvram/eeprom_at24c.h | 23 +++++++++++++++++++++++
- hw/arm/aspeed.c                 | 10 +---------
- hw/arm/npcm7xx_boards.c         | 20 +++++---------------
- hw/nvram/eeprom_at24c.c         | 12 ++++++++++++
-files changed, 41 insertions(+), 24 deletions(-)
- create mode 100644 include/hw/nvram/eeprom_at24c.h
-diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/include/hw/nvram/eeprom_at24c.h
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * Copyright (c) Meta Platforms, Inc. and affiliates.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0-only
-+ */
-+
-+#ifndef EEPROM_AT24C_H
-+#define EEPROM_AT24C_H
-+
-+#include "hw/i2c/i2c.h"
-+
-+/*
-+ * Create and realize an AT24C EEPROM device on the heap.
-+ * @bus: I2C bus to put it on
-+ * @address: I2C address of the EEPROM slave when put on a bus
-+ * @rom_size: size of the EEPROM
-+ *
-+ * Create the device state structure, initialize it, put it on the specified
-+ * @bus, and drop the reference to it (the device is realized).
-+ */
-+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
-+
-+#endif
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/i2c/i2c_mux_pca954x.h"
- #include "hw/i2c/smbus_eeprom.h"
- #include "hw/misc/pca9552.h"
-+#include "hw/nvram/eeprom_at24c.h"
- #include "hw/sensor/tmp105.h"
- #include "hw/misc/led.h"
- #include "hw/qdev-properties.h"
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
-     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
- }
--static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
--{
--    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
--    DeviceState *dev = DEVICE(i2c_dev);
--
--    qdev_prop_set_uint32(dev, "rom-size", rsize);
--    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
--}
--
- static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
- {
-     AspeedSoCState *soc = &bmc->soc;
-diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx_boards.c
-+++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/i2c/i2c_mux_pca954x.h"
- #include "hw/i2c/smbus_eeprom.h"
- #include "hw/loader.h"
-+#include "hw/nvram/eeprom_at24c.h"
- #include "hw/qdev-core.h"
- #include "hw/qdev-properties.h"
- #include "qapi/error.h"
-@@ -XXX,XX +XXX,XX @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
-     return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
- }
--static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
--                              uint32_t rsize)
--{
--    I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
--    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
--    DeviceState *dev = DEVICE(i2c_dev);
--
--    qdev_prop_set_uint32(dev, "rom-size", rsize);
--    i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
--}
--
- static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
-                                       NPCM7xxState *soc, const int *fan_counts)
- {
-@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
-     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
-     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
--    at24c_eeprom_init(soc, 9, 0x55, 8192);
--    at24c_eeprom_init(soc, 10, 0x55, 8192);
-+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
-+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
-     /*
-      * i2c-11:
-@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
-     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
--    at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
-+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
-     i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
-                                       TYPE_PCA9548, 0x77);
-@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
-     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
-     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
--    at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
-+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
-     /* TODO: Add remaining i2c devices. */
- }
-diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/nvram/eeprom_at24c.c
-+++ b/hw/nvram/eeprom_at24c.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "qemu/module.h"
- #include "hw/i2c/i2c.h"
-+#include "hw/nvram/eeprom_at24c.h"
- #include "hw/qdev-properties.h"
- #include "hw/qdev-properties-system.h"
- #include "sysemu/block-backend.h"
-@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
-     return 0;
- }
-+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
-+{
-+    I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
-+    DeviceState *dev = DEVICE(i2c_dev);
-+
-+    qdev_prop_set_uint32(dev, "rom-size", rom_size);
-+    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-+
-+    return i2c_dev;
-+}
-+
- static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
- {
-     EEPROMState *ee = AT24C_EE(dev);
---
-.39.1

-[PULL 11/25] hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
+Deleted patch
-From: Peter Delevoryas <peter@pjd.dev>
-aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.
-Signed-off-by: Peter Delevoryas <peter@pjd.dev>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Corey Minyard <cminyard@mvista.com>
-Link: https://lore.kernel.org/r/20230128060543.95582-3-peter@pjd.dev
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/arm/aspeed.c | 95 ++++++++++++++++++++++---------------------------
-file changed, 43 insertions(+), 52 deletions(-)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
-                           eeprom_buf);
- }
--static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
--{
--    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
--    DeviceState *dev = DEVICE(i2c_dev);
--
--    qdev_prop_set_uint32(dev, "rom-size", rsize);
--    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
--}
--
- static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
- {
-     AspeedSoCState *soc = &bmc->soc;
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     AspeedSoCState *soc = &bmc->soc;
-     I2CSlave *i2c_mux;
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
-     create_pca9552(soc, 3, 0x61);
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-x4a);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
-                                       "pca9546", 0x70);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
-     create_pca9552(soc, 4, 0x60);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     create_pca9552(soc, 5, 0x61);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
-                                       "pca9546", 0x70);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
-x48);
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-x4b);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
-                                       "pca9546", 0x70);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
-     create_pca9552(soc, 7, 0x30);
-     create_pca9552(soc, 7, 0x31);
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
-x48);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
-x48);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
-x4a);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
-     create_pca9552(soc, 8, 0x60);
-     create_pca9552(soc, 8, 0x61);
-     /* Bus 8: ucd90320@11 */
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
-     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
-x48);
-@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-x49);
-     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
-                                       "pca9546", 0x70);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
--    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-     create_pca9552(soc, 11, 0x60);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
-     create_pca9552(soc, 13, 0x60);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
-     create_pca9552(soc, 14, 0x60);
--    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
-+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
-     create_pca9552(soc, 15, 0x60);
- }
-@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
-     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
-     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
--    aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
--    aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
-+    at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
-+    at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
-     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
-     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
-     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
-     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
--    aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
-+    at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
-     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
-     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
--    aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
-     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
-     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
-     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
-     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
--    aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
-+    at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
-     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
-     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
--    aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
-+    at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
-     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
-     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
--    aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
--    aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
-+    at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
-+    at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
-     for (int i = 0; i < 8; i++) {
--        aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
-+        at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
-         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
-         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
-         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
-@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
-     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
-     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
--    aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
--    aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
--    aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
--    aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
--    aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
-+    at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
-+    at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
-+    at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
-+    at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
-+    at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
-     /*
-      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
---
-.39.1

-[PULL 12/25] hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
+Deleted patch
-From: Peter Delevoryas <peter@pjd.dev>
-Allows users to specify binary data to initialize an EEPROM, allowing users to
-emulate data programmed at manufacturing time.
-- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
-- Added at24c_eeprom_init_rom helper function to initialize attributes
-- If -drive property is provided, it overrides init_rom data
-Signed-off-by: Peter Delevoryas <peter@pjd.dev>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Corey Minyard <cminyard@mvista.com>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Tested-by: Ninad Palsule <ninadpalsule@us.ibm.com>
-Link: https://lore.kernel.org/r/20230128060543.95582-4-peter@pjd.dev
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- include/hw/nvram/eeprom_at24c.h | 16 +++++++++++++++
- hw/nvram/eeprom_at24c.c         | 36 ++++++++++++++++++++++++++++-----
-files changed, 47 insertions(+), 5 deletions(-)
-diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/nvram/eeprom_at24c.h
-+++ b/include/hw/nvram/eeprom_at24c.h
-@@ -XXX,XX +XXX,XX @@
-  */
- I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
-+
-+/*
-+ * Create and realize an AT24C EEPROM device on the heap with initial data.
-+ * @bus: I2C bus to put it on
-+ * @address: I2C address of the EEPROM slave when put on a bus
-+ * @rom_size: size of the EEPROM
-+ * @init_rom: Array of bytes to initialize EEPROM memory with
-+ * @init_rom_size: Size of @init_rom, must be less than or equal to @rom_size
-+ *
-+ * Create the device state structure, initialize it, put it on the specified
-+ * @bus, and drop the reference to it (the device is realized). Copies the data
-+ * from @init_rom to the beginning of the EEPROM memory buffer.
-+ */
-+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
-+                                const uint8_t *init_rom, uint32_t init_rom_size);
-+
- #endif
-diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/nvram/eeprom_at24c.c
-+++ b/hw/nvram/eeprom_at24c.c
-@@ -XXX,XX +XXX,XX @@ struct EEPROMState {
-     uint8_t *mem;
-     BlockBackend *blk;
-+
-+    const uint8_t *init_rom;
-+    uint32_t init_rom_size;
- };
- static
-@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
- I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
- {
--    I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
--    DeviceState *dev = DEVICE(i2c_dev);
-+    return at24c_eeprom_init_rom(bus, address, rom_size, NULL, 0);
-+}
-+
-+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
-+                                const uint8_t *init_rom, uint32_t init_rom_size)
-+{
-+    EEPROMState *s;
-+
-+    s = AT24C_EE(i2c_slave_new(TYPE_AT24C_EE, address));
-+
-+    qdev_prop_set_uint32(DEVICE(s), "rom-size", rom_size);
--    qdev_prop_set_uint32(dev, "rom-size", rom_size);
--    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-+    /* TODO: Model init_rom with QOM properties. */
-+    s->init_rom = init_rom;
-+    s->init_rom_size = init_rom_size;
--    return i2c_dev;
-+    i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);
-+
-+    return I2C_SLAVE(s);
- }
- static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
- {
-     EEPROMState *ee = AT24C_EE(dev);
-+    if (ee->init_rom_size > ee->rsize) {
-+        error_setg(errp, "%s: init rom is larger than rom: %u > %u",
-+                   TYPE_AT24C_EE, ee->init_rom_size, ee->rsize);
-+        return;
-+    }
-+
-     if (ee->blk) {
-         int64_t len = blk_getlength(ee->blk);
-@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
-     }
-     ee->mem = g_malloc0(ee->rsize);
-+
- }
- static
-@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
-     memset(ee->mem, 0, ee->rsize);
-+    if (ee->init_rom) {
-+        memcpy(ee->mem, ee->init_rom, MIN(ee->init_rom_size, ee->rsize));
-+    }
-+
-     if (ee->blk) {
-         int ret = blk_pread(ee->blk, 0, ee->rsize, ee->mem, 0);
---
-.39.1

-[PULL 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware
+Deleted patch
-From: Peter Delevoryas <peter@pjd.dev>
-EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
-I would expect the I2C state machine to be reset to default values, but I
-wouldn't really expect the memory to change at all.
-The current implementation of the at24c EEPROM resets its internal memory on
-reset. This matches the specification in docs/devel/reset.rst:
-  Cold reset is supported by every resettable object. In QEMU, it means we reset
-  to the initial state corresponding to the start of QEMU; this might differ
-  from what is a real hardware cold reset. It differs from other resets (like
-  warm or bus resets) which may keep certain parts untouched.
-But differs from my intuition. For example, if someone writes some information
-to an EEPROM, then AC power cycles their board, they would expect the EEPROM to
-retain that information. It's very useful to be able to test things like this
-in QEMU as well, to verify software instrumentation like determining the cause
-of a reboot.
-Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom")
-Signed-off-by: Peter Delevoryas <peter@pjd.dev>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Corey Minyard <cminyard@mvista.com>
-Link: https://lore.kernel.org/r/20230128060543.95582-6-peter@pjd.dev
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/nvram/eeprom_at24c.c | 22 ++++++++++------------
-file changed, 10 insertions(+), 12 deletions(-)
-diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/nvram/eeprom_at24c.c
-+++ b/hw/nvram/eeprom_at24c.c
-@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
-     }
-     ee->mem = g_malloc0(ee->rsize);
--
--}
--
--static
--void at24c_eeprom_reset(DeviceState *state)
--{
--    EEPROMState *ee = AT24C_EE(state);
--
--    ee->changed = false;
--    ee->cur = 0;
--    ee->haveaddr = 0;
--
-     memset(ee->mem, 0, ee->rsize);
-     if (ee->init_rom) {
-@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
-     }
- }
-+static
-+void at24c_eeprom_reset(DeviceState *state)
-+{
-+    EEPROMState *ee = AT24C_EE(state);
-+
-+    ee->changed = false;
-+    ee->cur = 0;
-+    ee->haveaddr = 0;
-+}
-+
- static Property at24c_eeprom_props[] = {
-     DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
-     DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
---
-.39.1

-[PULL 23/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
+[PULL 06/12] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-This SoC uses a Cortex-M4F. QEMU only implements a M4,
+TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
-which is good enough. Add a TODO note in case the M4F
+In few commits we'll add more fields, but to keep
-is added.
+review process simple, don't add any yet.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_ast10x0.c | 2 +-
+ include/hw/arm/aspeed_soc.h |  7 +++++++
-file changed, 1 insertion(+), 1 deletion(-)
+ hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
 files changed, 20 insertions(+), 13 deletions(-)
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/aspeed_soc.h
++++ b/include/hw/arm/aspeed_soc.h
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+ #define TYPE_ASPEED_SOC "aspeed-soc"
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
++struct Aspeed10x0SoCState {
++    AspeedSoCState parent;
++};
++
++#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
++
+ struct AspeedSoCClass {
+     DeviceClass parent_class;
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
 @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
-     dc->realize = aspeed_soc_ast1030_realize;
+     sc->get_irq = aspeed_soc_ast1030_get_irq;
+ }
-     sc->name = "ast1030-a1";
--    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+-static const TypeInfo aspeed_soc_ast1030_type_info = {
-+    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
+-    .name          = "ast1030-a1",
-     sc->silicon_rev = AST1030_A1_SILICON_REV;
+-    .parent        = TYPE_ASPEED_SOC,
-     sc->sram_size = 0xc0000;
+-    .instance_size = sizeof(AspeedSoCState),
-     sc->secsram_size = 0x40000; /* 256 * KiB */
+-    .instance_init = aspeed_soc_ast1030_init,
 -    .class_init    = aspeed_soc_ast1030_class_init,
 -    .class_size    = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast10x0_types[] = {
 +    {
 +        .name           = TYPE_ASPEED10X0_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed10x0SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast1030-a1",
 +        .parent         = TYPE_ASPEED10X0_SOC,
 +        .instance_init  = aspeed_soc_ast1030_init,
 +        .class_init     = aspeed_soc_ast1030_class_init,
 +    },
  };
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_ast1030_type_info);
 -}
 -
 -type_init(aspeed_soc_register_types)
 +DEFINE_TYPES(aspeed_soc_ast10x0_types)
 --
-.39.1
+.41.0

-[PULL 18/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed
+[PULL 07/12] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-address_space_map() can fail:
+TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
+In few commits we'll add more fields, but to keep
-  uart:~$ hash test
+review process simple, don't add any yet.
   sha256_test
   tv[0]:
   Segmentation fault: 11
   Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
   gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
       at ../hw/misc/aspeed_hace.c:171
 if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {
   (gdb) bt
   #0  gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
       at ../hw/misc/aspeed_hace.c:171
   #1  do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true)
       at ../hw/misc/aspeed_hace.c:224
   #2  0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>)
       at ../hw/misc/aspeed_hace.c:358
 This change doesn't fix much, but at least the guest
 can't crash QEMU anymore. Instead it is still usable:
   uart:~$ hash test
   sha256_test
   tv[0]:hash_final error
   sha384_test
   tv[0]:hash_final error
   sha512_test
   tv[0]:hash_final error
   [00:00:06.278,000] <err> hace_global: HACE poll timeout
   [00:00:09.324,000] <err> hace_global: HACE poll timeout
   [00:00:12.261,000] <err> hace_global: HACE poll timeout
   uart:~$
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/misc/aspeed_hace.c | 21 +++++++++++++++------
+ include/hw/arm/aspeed_soc.h |  7 +++++++
-file changed, 15 insertions(+), 6 deletions(-)
+ hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
 files changed, 20 insertions(+), 13 deletions(-)
-diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/aspeed_hace.c
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/misc/aspeed_hace.c
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
-     size_t digest_len = 0;
+ #define TYPE_ASPEED_SOC "aspeed-soc"
-     int niov = 0;
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
-     int i;
-+    void *haddr;
++struct Aspeed2600SoCState {
++    AspeedSoCState parent;
-     if (sg_mode) {
++};
-         uint32_t len = 0;
++
-@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
++#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
-             addr &= SG_LIST_ADDR_MASK;
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
++
-             plen = len & SG_LIST_LEN_MASK;
+ struct Aspeed10x0SoCState {
--            iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,
+     AspeedSoCState parent;
--                                                MEMTXATTRS_UNSPECIFIED);
+ };
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2600_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2600_type_info = {
 -    .name           = "ast2600-a3",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .instance_init  = aspeed_soc_ast2600_init,
 -    .class_init     = aspeed_soc_ast2600_class_init,
 -    .class_size     = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast2600_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2600_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed2600SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2600-a3",
 +        .parent         = TYPE_ASPEED2600_SOC,
 +        .instance_init  = aspeed_soc_ast2600_init,
 +        .class_init     = aspeed_soc_ast2600_class_init,
 +    },
  };
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_ast2600_type_info);
 -};
 -
-+            haddr = address_space_map(&s->dram_as, addr, &plen, false,
+-type_init(aspeed_soc_register_types)
-+                                      MEMTXATTRS_UNSPECIFIED);
++DEFINE_TYPES(aspeed_soc_ast2600_types)
 +            if (haddr == NULL) {
 +                qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
 +                return;
 +            }
 +            iov[i].iov_base = haddr;
              if (acc_mode) {
                  niov = gen_acc_mode_iov(s, iov, i, &plen);
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
      } else {
          hwaddr len = s->regs[R_HASH_SRC_LEN];
 +        haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
 +                                  &len, false, MEMTXATTRS_UNSPECIFIED);
 +        if (haddr == NULL) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
 +            return;
 +        }
 +        iov[0].iov_base = haddr;
          iov[0].iov_len = len;
 -        iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
 -                                            &len, false,
 -                                            MEMTXATTRS_UNSPECIFIED);
          i = 1;
          if (s->iov_count) {
 --
-.39.1
+.41.0

-[PULL 21/25] hw/arm/aspeed_ast10x0: Map the secure SRAM
+[PULL 08/12] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Some SRAM appears to be used by the Secure Boot unit and
+TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
-crypto accelerators. Name it 'secure sram'.
+In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
-Note, the SRAM base address was already present but unused
+TYPE_ASPEED_SOC is common to various Aspeed SoCs,
-(the 'SBC' index is used for the MMIO peripheral).
+define it in aspeed_soc_common.c.
 Interestingly using CFLAGS=-Winitializer-overrides reports:
   ../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
     [ASPEED_DEV_SBC]       = 0x7E6F2000,
                              ^~~~~~~~~~
   ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here
     [ASPEED_DEV_SBC]       = 0x79000000,
                              ^~~~~~~~~~
 This fixes with Zephyr:
   uart:~$ rsa test
   rsa test vector[0]:
   [00:00:26.156,000] <err> os: ***** BUS FAULT *****
   [00:00:26.157,000] <err> os:   Precise data bus error
   [00:00:26.157,000] <err> os:   BFAR Address: 0x79000000
   [00:00:26.158,000] <err> os: r0/a1:  0x79000000  r1/a2:  0x00000000  r2/a3:  0x00001800
   [00:00:26.158,000] <err> os: r3/a4:  0x79001800 r12/ip:  0x00000800 r14/lr:  0x0001098d
   [00:00:26.158,000] <err> os:  xpsr:  0x81000000
   [00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc
   [00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
   [00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart)
   [00:00:26.165,000] <err> os: Halting system
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: Fixed size of Secure Boot Controller Memory ]
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h |  3 +++
+ include/hw/arm/aspeed_soc.h |  7 +++++
- hw/arm/aspeed_ast10x0.c     | 11 ++++++++++-
+ hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
-files changed, 13 insertions(+), 1 deletion(-)
+ hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
 files changed, 53 insertions(+), 44 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
 @@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
-     AspeedSMCState spi[ASPEED_SPIS_NUM];
+ #define TYPE_ASPEED_SOC "aspeed-soc"
-     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
-     AspeedSBCState sbc;
-+    MemoryRegion secsram;
++struct Aspeed2400SoCState {
-     UnimplementedDeviceState sbc_unimplemented;
++    AspeedSoCState parent;
-     AspeedSDMCState sdmc;
++};
-     AspeedWDTState wdt[ASPEED_WDTS_NUM];
++
-@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
++#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
-     const char *cpu_type;
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
-     uint32_t silicon_rev;
++
-     uint64_t sram_size;
+ struct Aspeed2600SoCState {
-+    uint64_t secsram_size;
+     AspeedSoCState parent;
-     int spis_num;
+ };
-     int ehcis_num;
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
      int wdts_num;
@@ -XXX,XX +XXX,XX @@ enum {
      ASPEED_DEV_SCU,
      ASPEED_DEV_ADC,
      ASPEED_DEV_SBC,
 +    ASPEED_DEV_SECSRAM,
      ASPEED_DEV_EMMC_BC,
      ASPEED_DEV_VIDEO,
      ASPEED_DEV_SRAM,
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_ast10x0.c
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/arm/aspeed_ast10x0.c
++++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                         aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
  }
 -static Property aspeed_soc_properties[] = {
 -    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
 -static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 -{
 -    DeviceClass *dc = DEVICE_CLASS(oc);
 -
 -    device_class_set_props(dc, aspeed_soc_properties);
 -}
 -
 -static const TypeInfo aspeed_soc_type_info = {
 -    .name           = TYPE_ASPEED_SOC,
 -    .parent         = TYPE_DEVICE,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_size     = sizeof(AspeedSoCClass),
 -    .class_init     = aspeed_soc_class_init,
 -    .abstract       = true,
 -};
  static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
  {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2400_type_info = {
 -    .name           = "ast2400-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2400_class_init,
 -};
 -
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2500_type_info = {
 -    .name           = "ast2500-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2500_class_init,
 -};
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_type_info);
 -    type_register_static(&aspeed_soc_ast2400_type_info);
 -    type_register_static(&aspeed_soc_ast2500_type_info);
 +static const TypeInfo aspeed_soc_ast2400_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2400_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_init  = aspeed_ast2400_soc_init,
 +        .instance_size  = sizeof(Aspeed2400SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2400-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2400_class_init,
 +    }, {
 +        .name           = "ast2500-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2500_class_init,
 +    },
  };
 -type_init(aspeed_soc_register_types);
 +DEFINE_TYPES(aspeed_soc_ast2400_types)
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc_common.c
 +++ b/hw/arm/aspeed_soc_common.c
 @@ -XXX,XX +XXX,XX @@
- static const hwaddr aspeed_soc_ast1030_memmap[] = {
+ #include "qemu/osdep.h"
-     [ASPEED_DEV_SRAM]      = 0x00000000,
+ #include "qapi/error.h"
--    [ASPEED_DEV_SBC]       = 0x79000000,
++#include "hw/qdev-properties.h"
-+    [ASPEED_DEV_SECSRAM]   = 0x79000000,
+ #include "hw/misc/unimp.h"
-     [ASPEED_DEV_IOMEM]     = 0x7E600000,
+ #include "hw/arm/aspeed_soc.h"
-     [ASPEED_DEV_PWM]       = 0x7E610000,
+ #include "hw/char/serial.h"
-     [ASPEED_DEV_FMC]       = 0x7E620000,
+@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+     memory_region_add_subregion_overlap(s->memory, addr,
-     memory_region_add_subregion(s->memory,
+                                         sysbus_mmio_get_region(dev, 0), -1000);
-                                 sc->memmap[ASPEED_DEV_SRAM],
+ }
-                                 &s->sram);
++
-+    memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
++static Property aspeed_soc_properties[] = {
-+                           sc->secsram_size, &err);
++    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-+    if (err != NULL) {
++                     MemoryRegion *),
-+        error_propagate(errp, err);
++    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
-+        return;
++                     MemoryRegion *),
-+    }
++    DEFINE_PROP_END_OF_LIST(),
-+    memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
++};
-+                                &s->secsram);
++
++static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-     /* SCU */
++{
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
++    DeviceClass *dc = DEVICE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
++
-     sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
++    device_class_set_props(dc, aspeed_soc_properties);
-     sc->silicon_rev = AST1030_A1_SILICON_REV;
++}
-     sc->sram_size = 0xc0000;
++
-+    sc->secsram_size = 0x40000; /* 256 * KiB */
++static const TypeInfo aspeed_soc_types[] = {
-     sc->spis_num = 2;
++    {
-     sc->ehcis_num = 0;
++        .name           = TYPE_ASPEED_SOC,
-     sc->wdts_num = 4;
++        .parent         = TYPE_DEVICE,
 +        .instance_size  = sizeof(AspeedSoCState),
 +        .class_size     = sizeof(AspeedSoCClass),
 +        .class_init     = aspeed_soc_class_init,
 +        .abstract       = true,
 +    },
 +};
 +
 +DEFINE_TYPES(aspeed_soc_types)
 --
-.39.1
+.41.0

-[PULL 16/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
+[PULL 09/12] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-When booting the Zephyr demo in [1] we get:
-  aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <--
-  aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1)
-This corresponds to this Zephyr code [2]:
-  static int aspeed_wdt_init(const struct device *dev)
-  {
-    const struct aspeed_wdt_config *config = dev->config;
-    struct aspeed_wdt_data *const data = dev->data;
-    uint32_t reg_val;
-    /* disable WDT by default */
-    reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG);
-    reg_val &= ~WDT_CTRL_ENABLE;
-    sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG);
-    sys_write32(data->rst_mask1,
-                config->ctrl_base + WDT_SW_RESET_MASK1_REG);   <------
-    sys_write32(data->rst_mask2,
-                config->ctrl_base + WDT_SW_RESET_MASK2_REG);
-    return 0;
-  }
-The register definitions are [3]:
-  #define WDT_RELOAD_VAL_REG          0x0004
-  #define WDT_RESTART_REG             0x0008
-  #define WDT_CTRL_REG                0x000C
-  #define WDT_TIMEOUT_STATUS_REG      0x0010
-  #define WDT_TIMEOUT_STATUS_CLR_REG  0x0014
-  #define WDT_RESET_MASK1_REG         0x001C
-  #define WDT_RESET_MASK2_REG         0x0020
-  #define WDT_SW_RESET_MASK1_REG      0x0028   <------
-  #define WDT_SW_RESET_MASK2_REG      0x002C
-  #define WDT_SW_RESET_CTRL_REG       0x0024
-Currently QEMU only cover a MMIO region of size 0x20:
-  #define ASPEED_WDT_REGS_MAX        (0x20 / 4)
-Change to map the whole 'iosize' which might be bigger, covering
-the other registers. The MemoryRegionOps read/write handlers will
-report the accesses as out-of-bounds guest-errors, but the next
-commit will report them as unimplemented.
-[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
-[2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b
-[3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/watchdog/wdt_aspeed.c | 3 ++-
+ hw/arm/aspeed_soc_common.c | 11 +++++++++++
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 11 insertions(+)
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
+diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/wdt_aspeed.c
+--- a/hw/arm/aspeed_soc_common.c
-+++ b/hw/watchdog/wdt_aspeed.c
++++ b/hw/arm/aspeed_soc_common.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
                                          sysbus_mmio_get_region(dev, 0), -1000);
  }
 +static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 +{
 +    AspeedSoCState *s = ASPEED_SOC(dev);
 +
 +    if (!s->memory) {
 +        error_setg(errp, "'memory' link is not set");
 +        return;
 +    }
 +}
 +
  static Property aspeed_soc_properties[] = {
      DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                       MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
  {
-     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+     DeviceClass *dc = DEVICE_CLASS(oc);
-     AspeedWDTState *s = ASPEED_WDT(dev);
-+    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
++    dc->realize = aspeed_soc_realize;
+     device_class_set_props(dc, aspeed_soc_properties);
      assert(s->scu);
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
      s->pclk_freq = PCLK_HZ;
      memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
 -                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
 +                          TYPE_ASPEED_WDT, awc->iosize);
      sysbus_init_mmio(sbd, &s->iomem);
  }
 --
-.39.1
+.41.0

-[PULL 19/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
+[PULL 10/12] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Based on booting Zephyr demo from [1] running QEMU with
+The v7-M core is specific to the Aspeed 10x0 series,
-'-d unimp' and checking missing devices in [2].
+remove it from the common AspeedSoCState.
 [1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
 [2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/arm/aspeed_soc.h | 11 +++++++++++
+ include/hw/arm/aspeed_soc.h |  5 ++---
- hw/arm/aspeed_ast10x0.c     | 35 +++++++++++++++++++++++++++++++++++
+ hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
-files changed, 46 insertions(+)
+ hw/arm/fby35.c              | 13 ++++++++-----
 files changed, 25 insertions(+), 20 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
 @@ -XXX,XX +XXX,XX @@
- #define ASPEED_CPUS_NUM  2
+ #define ASPEED_JTAG_NUM  2
  #define ASPEED_MACS_NUM  4
  #define ASPEED_UARTS_NUM 13
 +#define ASPEED_JTAG_NUM  2
  struct AspeedSoCState {
-     /*< private >*/
+-    /*< private >*/
-@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
+     DeviceState parent;
-     UnimplementedDeviceState video;
-     UnimplementedDeviceState emmc_boot_controller;
+-    /*< public >*/
-     UnimplementedDeviceState dpmcu;
+     ARMCPU cpu[ASPEED_CPUS_NUM];
-+    UnimplementedDeviceState pwm;
+     A15MPPrivState     a7mpcore;
-+    UnimplementedDeviceState espi;
+-    ARMv7MState        armv7m;
-+    UnimplementedDeviceState udc;
+     MemoryRegion *memory;
-+    UnimplementedDeviceState sgpiom;
+     MemoryRegion *dram_mr;
-+    UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
+     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
 +
 +    ARMv7MState armv7m;
  };
- #define TYPE_ASPEED_SOC "aspeed-soc"
+ #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
@@ -XXX,XX +XXX,XX @@ enum {
      ASPEED_DEV_DPMCU,
      ASPEED_DEV_DP,
      ASPEED_DEV_I3C,
 +    ASPEED_DEV_ESPI,
 +    ASPEED_DEV_UDC,
 +    ASPEED_DEV_SGPIOM,
 +    ASPEED_DEV_JTAG0,
 +    ASPEED_DEV_JTAG1,
  };
  qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast10x0.c
 +++ b/hw/arm/aspeed_ast10x0.c
-@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
-     [ASPEED_DEV_FMC]       = 0x7E620000,
-     [ASPEED_DEV_SPI1]      = 0x7E630000,
-     [ASPEED_DEV_SPI2]      = 0x7E640000,
-+    [ASPEED_DEV_UDC]       = 0x7E6A2000,
-     [ASPEED_DEV_SCU]       = 0x7E6E2000,
-+    [ASPEED_DEV_JTAG0]     = 0x7E6E4000,
-+    [ASPEED_DEV_JTAG1]     = 0x7E6E4100,
-     [ASPEED_DEV_ADC]       = 0x7E6E9000,
-+    [ASPEED_DEV_ESPI]      = 0x7E6EE000,
-     [ASPEED_DEV_SBC]       = 0x7E6F2000,
-     [ASPEED_DEV_GPIO]      = 0x7E780000,
-+    [ASPEED_DEV_SGPIOM]    = 0x7E780500,
-     [ASPEED_DEV_TIMER1]    = 0x7E782000,
-     [ASPEED_DEV_UART1]     = 0x7E783000,
-     [ASPEED_DEV_UART2]     = 0x7E78D000,
 @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
-     [ASPEED_DEV_LPC]       = 35,
-     [ASPEED_DEV_PECI]      = 38,
+ static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
-     [ASPEED_DEV_FMC]       = 39,
+ {
-+    [ASPEED_DEV_ESPI]      = 42,
++    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
-     [ASPEED_DEV_PWM]       = 44,
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     [ASPEED_DEV_ADC]       = 46,
-     [ASPEED_DEV_SPI1]      = 65,
+-    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
-     [ASPEED_DEV_SPI2]      = 66,
++    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
-     [ASPEED_DEV_I2C]       = 110, /* 110 ~ 123 */
+ }
-     [ASPEED_DEV_KCS]       = 138, /* 138 -> 142 */
-+    [ASPEED_DEV_UDC]       = 9,
+ static void aspeed_soc_ast1030_init(Object *obj)
-+    [ASPEED_DEV_SGPIOM]    = 51,
+ {
-+    [ASPEED_DEV_JTAG0]     = 27,
++    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
-+    [ASPEED_DEV_JTAG1]     = 53,
+     AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
          g_assert_not_reached();
      }
 -    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
 +    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
      s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
  static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
      AspeedSoCState *s = ASPEED_SOC(dev_soc);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 x40000);
      /* AST1030 CPU Core */
 -    armv7m = DEVICE(&s->armv7m);
 +    armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
      qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 -    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +    object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
      /* Internal SRAM */
      sram_name = g_strdup_printf("aspeed.sram.%d",
 -                                CPU(s->armv7m.cpu)->cpu_index);
 +                                CPU(a->armv7m.cpu)->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err != NULL) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST1030 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST1030 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
       * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* UART */
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      Clock *bic_sysclk;
      AspeedSoCState bmc;
 -    AspeedSoCState bic;
 +    Aspeed10x0SoCState bic;
      bool mmio_exec;
  };
+@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
- static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
+ static void fby35_bic_init(Fby35State *s)
-     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
+ {
-     object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
++    AspeedSoCState *soc;
-                             TYPE_UNIMPLEMENTED_DEVICE);
++
-+    object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
+     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
-+    object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
+     clock_set_hz(s->bic_sysclk, 200000000ULL);
-+    object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
-+    object_initialize_child(obj, "sgpiom", &s->sgpiom,
+     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
-+                            TYPE_UNIMPLEMENTED_DEVICE);
++    soc = ASPEED_SOC(&s->bic);
-+    object_initialize_child(obj, "jtag[0]", &s->jtag[0],
-+                            TYPE_UNIMPLEMENTED_DEVICE);
+     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
-+    object_initialize_child(obj, "jtag[1]", &s->jtag[1],
+                        UINT64_MAX);
-+                            TYPE_UNIMPLEMENTED_DEVICE);
+@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
      qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
      object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                               &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
      qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
 -    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
 -    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
 +    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
 +    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
 +    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
  }
- static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+ static void fby35_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                      sc->memmap[ASPEED_DEV_GPIO]);
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                         aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
 +
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
 +                                  sc->memmap[ASPEED_DEV_PWM], 0x100);
 +
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
 +                                  sc->memmap[ASPEED_DEV_ESPI], 0x800);
 +
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
 +                                  sc->memmap[ASPEED_DEV_UDC], 0x1000);
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
 +                                  sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
 +
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
 +                                  sc->memmap[ASPEED_DEV_JTAG0], 0x20);
 +    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
 +                                  sc->memmap[ASPEED_DEV_JTAG1], 0x20);
  }
  static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
 --
-.39.1
+.41.0

-[PULL 15/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
+[PULL 11/12] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Avoid confusing two different things:
+The v7-A cluster is specific to the Aspeed 2600 series,
-- the WDT I/O region size ('iosize')
+remove it from the common AspeedSoCState.
-- at which offset the SoC map the WDT ('offset')
-While it is often the same, we can map smaller region sizes
+The ARM cores belong to the MP cluster, but the array
-at larger offsets.
+is currently used by TYPE_ASPEED2600_SOC. We'll clean
+that soon, but for now keep it in Aspeed2600SoCState.
-Here we are interested in the I/O region size, so rename as
 'iosize'.
 Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-[ clg: Introduced temporary wdt_offset variable ]
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/watchdog/wdt_aspeed.h | 2 +-
+ include/hw/arm/aspeed_soc.h |  4 ++-
- hw/arm/aspeed_ast10x0.c          | 4 ++--
+ hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
- hw/arm/aspeed_ast2600.c          | 4 ++--
+ hw/arm/fby35.c              | 14 ++++++-----
- hw/arm/aspeed_soc.c              | 4 ++--
+files changed, 37 insertions(+), 30 deletions(-)
- hw/watchdog/wdt_aspeed.c         | 8 ++++----
-files changed, 11 insertions(+), 11 deletions(-)
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/watchdog/wdt_aspeed.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/include/hw/watchdog/wdt_aspeed.h
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ struct AspeedWDTState {
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
- struct AspeedWDTClass {
+     DeviceState parent;
-     SysBusDeviceClass parent_class;
+     ARMCPU cpu[ASPEED_CPUS_NUM];
--    uint32_t offset;
+-    A15MPPrivState     a7mpcore;
-+    uint32_t iosize;
+     MemoryRegion *memory;
-     uint32_t ext_pulse_width_mask;
+     MemoryRegion *dram_mr;
-     uint32_t reset_ctrl_reg;
+     MemoryRegion dram_container;
-     void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
-diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
-index XXXXXXX..XXXXXXX 100644
+ struct Aspeed2600SoCState {
---- a/hw/arm/aspeed_ast10x0.c
+     AspeedSoCState parent;
-+++ b/hw/arm/aspeed_ast10x0.c
++
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
++    A15MPPrivState a7mpcore;
-     /* Watch dog */
++    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
-     for (i = 0; i < sc->wdts_num; i++) {
+ };
-         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
-+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
+ #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
          object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                   &error_abort);
          if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
              return;
          }
 -        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
 -                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
 +        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
      }
      /* GPIO */
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
-     /* Watch dog */
-     for (i = 0; i < sc->wdts_num; i++) {
+ static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
-         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+ {
-+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
++    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
-                                  &error_abort);
+-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
-         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
++    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
  }
  static void aspeed_soc_ast2600_init(Object *obj)
  {
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
 +        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                                "hw-prot-key");
 -    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
 +    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                              TYPE_A15MPCORE_PRIV);
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
  static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
          if (sc->num_cpus > 1) {
 -            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 +            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                      ASPEED_A7MPCORE_ADDR, &error_abort);
          }
 -        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
 +        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                  aspeed_calc_affinity(i), &error_abort);
 -        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
 +        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                  &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                  &error_abort);
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
--        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
+     }
--                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
-+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
+     /* A7MPCORE */
-     }
+-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
++    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
-     /* RAM */
+                             &error_abort);
-diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
+-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
 +    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                              ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                              &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
 -    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
 +    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
      for (i = 0; i < sc->num_cpus; i++) {
 -        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 -        DeviceState  *d   = DEVICE(&s->cpu[i]);
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
 +        DeviceState  *d   = DEVICE(&a->cpu[i]);
          irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
          sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      /* SRAM */
 -    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
 +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST2600 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
       * offset 0.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST2600 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_soc.c
+--- a/hw/arm/fby35.c
-+++ b/hw/arm/aspeed_soc.c
++++ b/hw/arm/fby35.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ struct Fby35State {
-     /* Watch dog */
+     MemoryRegion bic_memory;
-     for (i = 0; i < sc->wdts_num; i++) {
+     Clock *bic_sysclk;
-         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
-+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
+-    AspeedSoCState bmc;
++    Aspeed2600SoCState bmc;
-         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
+     Aspeed10x0SoCState bic;
-                                  &error_abort);
-         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
+     bool mmio_exec;
-             return;
+@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
-         }
--        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
+ static void fby35_bmc_init(Fby35State *s)
--                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+ {
-+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
++    AspeedSoCState *soc;
-     }
++
+     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
-     /* RAM  */
++    soc = ASPEED_SOC(&s->bmc);
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
-index XXXXXXX..XXXXXXX 100644
+     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
---- a/hw/watchdog/wdt_aspeed.c
+                        UINT64_MAX);
-+++ b/hw/watchdog/wdt_aspeed.c
+@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
+                             &error_abort);
-     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
+                             &error_abort);
-     dc->desc = "ASPEED 2400 Watchdog Controller";
+-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
--    awc->offset = 0x20;
++    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
-+    awc->iosize = 0x20;
+     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
-     awc->ext_pulse_width_mask = 0xff;
-     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
+-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
-     awc->wdt_reload = aspeed_wdt_reload;
++    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
-     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+     /* Install first FMC flash content as a boot rom. */
+     if (!s->mmio_exec) {
-     dc->desc = "ASPEED 2500 Watchdog Controller";
+         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
--    awc->offset = 0x20;
-+    awc->iosize = 0x20;
+         if (mtd0) {
-     awc->ext_pulse_width_mask = 0xfffff;
+-            AspeedSoCState *bmc = &s->bmc;
-     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
+-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
-     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
++            uint64_t rom_size = memory_region_size(&soc->spi_boot);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
-     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
+             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
+                                    rom_size, &error_abort);
-     dc->desc = "ASPEED 2600 Watchdog Controller";
+-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
--    awc->offset = 0x40;
++            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
-+    awc->iosize = 0x40;
+                                                 &s->bmc_boot_rom, 1);
-     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
-     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
+             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
      awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
@@ -XXX,XX +XXX,XX @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
      AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
      dc->desc = "ASPEED 1030 Watchdog Controller";
 -    awc->offset = 0x80;
 +    awc->iosize = 0x80;
      awc->ext_pulse_width_mask = 0xfffff; /* TODO */
      awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
      awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
 --
-.39.1
+.41.0

-[PULL 17/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
+Deleted patch
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Add more Aspeed watchdog registers from [*].
-Since guests can righteously access them, log the access at
-'unimplemented' level instead of 'guest-errors'.
-[*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- include/hw/watchdog/wdt_aspeed.h |  2 +-
- hw/watchdog/wdt_aspeed.c         | 13 +++++++++++++
-files changed, 14 insertions(+), 1 deletion(-)
-diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/watchdog/wdt_aspeed.h
-+++ b/include/hw/watchdog/wdt_aspeed.h
-@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
- #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
- #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
--#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
-+#define ASPEED_WDT_REGS_MAX        (0x30 / 4)
- struct AspeedWDTState {
-     /*< private >*/
-diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/watchdog/wdt_aspeed.c
-+++ b/hw/watchdog/wdt_aspeed.c
-@@ -XXX,XX +XXX,XX @@
- #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
- #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
- #define WDT_RESET_MASK1                 (0x1c / 4)
-+#define WDT_RESET_MASK2                 (0x20 / 4)
-+
-+#define WDT_SW_RESET_CTRL               (0x24 / 4)
-+#define WDT_SW_RESET_MASK1              (0x28 / 4)
-+#define WDT_SW_RESET_MASK2              (0x2c / 4)
- #define WDT_TIMEOUT_STATUS              (0x10 / 4)
- #define WDT_TIMEOUT_CLEAR               (0x14 / 4)
-@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
-         return s->regs[WDT_RESET_MASK1];
-     case WDT_TIMEOUT_STATUS:
-     case WDT_TIMEOUT_CLEAR:
-+    case WDT_RESET_MASK2:
-+    case WDT_SW_RESET_CTRL:
-+    case WDT_SW_RESET_MASK1:
-+    case WDT_SW_RESET_MASK2:
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
-                       __func__, offset);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
-     case WDT_TIMEOUT_STATUS:
-     case WDT_TIMEOUT_CLEAR:
-+    case WDT_RESET_MASK2:
-+    case WDT_SW_RESET_CTRL:
-+    case WDT_SW_RESET_MASK1:
-+    case WDT_SW_RESET_MASK2:
-         qemu_log_mask(LOG_UNIMP,
-                       "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
-                       __func__, offset);
---
-.39.1

-[PULL 20/25] hw/arm/aspeed_ast10x0: Map I3C peripheral
+[PULL 12/12] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Since I don't have access to the datasheet, the relevant
+The ARM array and VIC peripheral are only used by the
-values were found in:
+series, remove them from the common AspeedSoCState.
 https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++
+ include/hw/arm/aspeed_soc.h               |  5 +++--
-file changed, 16 insertions(+)
+ hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
  hw/arm/meson.build                        |  2 +-
 files changed, 19 insertions(+), 15 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
-diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_ast10x0.c
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/arm/aspeed_ast10x0.c
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
+@@ -XXX,XX +XXX,XX @@
-     [ASPEED_DEV_WDT]       = 0x7E785000,
+ struct AspeedSoCState {
-     [ASPEED_DEV_LPC]       = 0x7E789000,
+     DeviceState parent;
-     [ASPEED_DEV_PECI]      = 0x7E78B000,
-+    [ASPEED_DEV_I3C]       = 0x7E7A0000,
+-    ARMCPU cpu[ASPEED_CPUS_NUM];
-     [ASPEED_DEV_I2C]       = 0x7E7B0000,
+     MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
      MemoryRegion sram;
      MemoryRegion spi_boot_container;
      MemoryRegion spi_boot;
 -    AspeedVICState vic;
      AspeedRtcState rtc;
      AspeedTimerCtrlState timerctrl;
      AspeedI2CState i2c;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  struct Aspeed2400SoCState {
      AspeedSoCState parent;
 +
 +    ARMCPU cpu[ASPEED_CPUS_NUM];
 +    AspeedVICState vic;
  };
-@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
+ #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
-     [ASPEED_DEV_ADC]       = 46,
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
-     [ASPEED_DEV_SPI1]      = 65,
+similarity index 95%
-     [ASPEED_DEV_SPI2]      = 66,
+rename from hw/arm/aspeed_soc.c
-+    [ASPEED_DEV_I3C]       = 102, /* 102 -> 105 */
+rename to hw/arm/aspeed_ast2400.c
-     [ASPEED_DEV_I2C]       = 110, /* 110 ~ 123 */
+index XXXXXXX..XXXXXXX 100644
-     [ASPEED_DEV_KCS]       = 138, /* 138 -> 142 */
+--- a/hw/arm/aspeed_soc.c
-     [ASPEED_DEV_UDC]       = 9,
++++ b/hw/arm/aspeed_ast2400.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
-     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
-     object_initialize_child(obj, "i2c", &s->i2c, typename);
+ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
+ {
-+    object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
++    Aspeed2400SoCState *a = ASPEED2400_SOC(s);
-+
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
-     object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+-    return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
++    return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
+ }
-         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
  static void aspeed_ast2400_soc_init(Object *obj)
  {
 +    Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
      }
-+    /* I3C */
+     for (i = 0; i < sc->num_cpus; i++) {
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
+-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
-+        return;
++        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
-+    }
+     }
-+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
-+    for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
+     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
-+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
-+                                        sc->irqmap[ASPEED_DEV_I3C] + i);
+     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
-+        /* The AST1030 I3C controller has one IRQ per bus. */
+                               "hw-prot-key");
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
-+    }
+-    object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
-+
++    object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
-     /* PECI */
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
+     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
  static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
      }
      /* SRAM */
 -    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
 +    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
      /* VIC */
 -    if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
          return;
+     }
+-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
+-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
+-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
+-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
+-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
++                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
++    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
++                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
+     /* RTC */
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
+diff --git a/hw/arm/meson.build b/hw/arm/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/meson.build
++++ b/hw/arm/meson.build
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
+ arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
+ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
+ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+-  'aspeed_soc.c',
+   'aspeed.c',
+   'aspeed_soc_common.c',
++  'aspeed_ast2400.c',
+   'aspeed_ast2600.c',
+   'aspeed_ast10x0.c',
+   'aspeed_eeprom.c',
 --
-.39.1
+.41.0

-[PULL 22/25] hw/arm/aspeed_ast10x0: Map HACE peripheral
+Deleted patch
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Since I don't have access to the datasheet, the relevant
-values were found in:
-https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi
-Before on Zephyr:
-  uart:~$ hash test
-  sha256_test
-  tv[0]:hash_final error
-  sha384_test
-  tv[0]:hash_final error
-  sha512_test
-  tv[0]:hash_final error
-  [00:00:06.278,000] <err> hace_global: HACE poll timeout
-  [00:00:09.324,000] <err> hace_global: HACE poll timeout
-  [00:00:12.261,000] <err> hace_global: HACE poll timeout
-  uart:~$ crypto aes256_cbc_vault
-  aes256_cbc vault key 1
-  [00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup
-  [00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098
-  [00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340
-  [00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348
-  [00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300
-  [00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040
-  [00:00:06.699,000] <inf> hace_global: crypto_cmd_reg:  11c2098
-  [00:00:09.743,000] <inf> hace_global: HACE_STS: 0
-  [00:00:09.743,000] <err> hace_global: HACE poll timeout
-  [00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed
-  [00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free
-  uart:~$
-After:
-  uart:~$ hash test
-  sha256_test
-  tv[0]:PASS
-  tv[1]:PASS
-  tv[2]:PASS
-  tv[3]:PASS
-  tv[4]:PASS
-  sha384_test
-  tv[0]:PASS
-  tv[1]:PASS
-  tv[2]:PASS
-  tv[3]:PASS
-  tv[4]:PASS
-  tv[5]:PASS
-  sha512_test
-  tv[0]:PASS
-  tv[1]:PASS
-  tv[2]:PASS
-  tv[3]:PASS
-  tv[4]:PASS
-  tv[5]:PASS
-  uart:~$ crypto aes256_cbc_vault
-  aes256_cbc vault key 1
-  Was waiting for:
-b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
-  ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
-c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
-  f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
-   But got:
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-  [00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup
-  [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098
-  [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
-  [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
-  [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
-  [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
-  [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2098
-  [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
-  [00:00:05.772,000] <inf> crypto: Output length (encryption): 80
-  [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free
-  [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup
-  [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018
-  [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
-  [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
-  [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
-  [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
-  [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2018
-  [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
-  [00:00:05.772,000] <inf> crypto: Output length (decryption): 64
-  [00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text
-  [00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free
-  uart:~$
-Reviewed-by: Peter Delevoryas <peter@pjd.dev>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++
-file changed, 15 insertions(+)
-diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed_ast10x0.c
-+++ b/hw/arm/aspeed_ast10x0.c
-@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
-     [ASPEED_DEV_SPI1]      = 0x7E630000,
-     [ASPEED_DEV_SPI2]      = 0x7E640000,
-     [ASPEED_DEV_UDC]       = 0x7E6A2000,
-+    [ASPEED_DEV_HACE]      = 0x7E6D0000,
-     [ASPEED_DEV_SCU]       = 0x7E6E2000,
-     [ASPEED_DEV_JTAG0]     = 0x7E6E4000,
-     [ASPEED_DEV_JTAG1]     = 0x7E6E4100,
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
-     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
-     object_initialize_child(obj, "gpio", &s->gpio, typename);
-+    snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
-+    object_initialize_child(obj, "hace", &s->hace, typename);
-+
-     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
-     object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
-                             TYPE_UNIMPLEMENTED_DEVICE);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
-     }
-     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
-+    /* HACE */
-+    object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
-+                             &error_abort);
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
-+        return;
-+    }
-+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
-+                    sc->memmap[ASPEED_DEV_HACE]);
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
-+                       aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
-+
-     /* Watch dog */
-     for (i = 0; i < sc->wdts_num; i++) {
-         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
---
-.39.1

The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:

Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20230207

for you to fetch changes up to bf81b8f8acda4f1f774adc5f8e76225d472c6ae5:

aspeed/sdmc: Drop unnecessary scu include (2023-02-07 09:02:05 +0100)

----------------------------------------------------------------
aspeed queue:

* various small cleanups and fixes
* new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC
* at24c_eeprom extension to define eeprom contents with static arrays
* ast10x0 model and test improvements
* avocado update of images to use the latest

----------------------------------------------------------------
Cédric Le Goater (3):
      tests/avocado/machine_aspeed.py: update buildroot tests
      tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
      hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr

Guenter Roeck (2):
      aspeed: Add Supermicro X11 SPI machine type
      m25p80: Add the is25wp256 SFPD table

Joel Stanley (2):
      avocado/boot_linux_console.py: Update ast2600 test
      aspeed/sdmc: Drop unnecessary scu include

Peter Delevoryas (5):
      hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
      hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
      hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
      hw/arm/aspeed: Add aspeed_eeprom.c
      hw/nvram/eeprom_at24c: Make reset behavior more like hardware

Philippe Mathieu-Daudé (12):
      tests/avocado: Introduce file_truncate()
      tests/avocado: Truncate M2S-FG484 SOM SPI flash to 16MiB
      hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
      hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
      hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
      hw/misc/aspeed_hace: Do not crash if address_space_map() failed
      hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
      hw/arm/aspeed_ast10x0: Map I3C peripheral
      hw/arm/aspeed_ast10x0: Map the secure SRAM
      hw/arm/aspeed_ast10x0: Map HACE peripheral
      hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
      tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board

Stephen Longfield (1):
      hw/net: Fix read of uninitialized memory in ftgmac100

hw/arm/aspeed_eeprom.h              |  19 +++++
 hw/block/m25p80_sfdp.h              |   2 +
 include/hw/arm/aspeed_soc.h         |  14 ++++
 include/hw/loader.h                 |   3 -
 include/hw/nvram/eeprom_at24c.h     |  39 ++++++++++
 include/hw/watchdog/wdt_aspeed.h    |   4 +-
 hw/arm/aspeed.c                     | 142 ++++++++++++++++++++----------------
 hw/arm/aspeed_ast10x0.c             |  83 ++++++++++++++++++++-
 hw/arm/aspeed_ast2600.c             |   4 +-
 hw/arm/aspeed_eeprom.c              |  82 +++++++++++++++++++++
 hw/arm/aspeed_soc.c                 |   4 +-
 hw/arm/msf2-som.c                   |   5 +-
 hw/arm/npcm7xx_boards.c             |  20 ++---
 hw/block/m25p80.c                   |   3 +-
 hw/block/m25p80_sfdp.c              |  40 ++++++++++
 hw/misc/aspeed_hace.c               |  21 ++++--
 hw/misc/aspeed_sdmc.c               |   1 -
 hw/net/ftgmac100.c                  |   4 +-
 hw/nvram/eeprom_at24c.c             |  58 ++++++++++++---
 hw/watchdog/wdt_aspeed.c            |  24 ++++--
 hw/arm/meson.build                  |   1 +
 tests/avocado/boot_linux_console.py |  19 +++--
 tests/avocado/machine_aspeed.py     |  60 +++++++++++++--
 23 files changed, 523 insertions(+), 129 deletions(-)
 create mode 100644 hw/arm/aspeed_eeprom.h
 create mode 100644 include/hw/nvram/eeprom_at24c.h
 create mode 100644 hw/arm/aspeed_eeprom.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The M2S-FG484 SOM uses a 16 MiB SPI flash (Spansion
S25FL128SDPBHICO).  Since the test asset is bigger,
truncate it to the correct size to avoid when running
the test_arm_emcraft_sf2 test:

qemu-system-arm: device requires 16777216 bytes, block backend provides 67108864 bytes

Add comment regarding the M2S-FG484 SOM hardware in
hw/arm/msf2-som.c.

Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/msf2-som.c                   | 5 ++++-
 tests/avocado/boot_linux_console.py | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -XXX,XX +XXX,XX @@
 /*
  * SmartFusion2 SOM starter kit(from Emcraft) emulation.
  *
+ * M2S-FG484 SOM hardware architecture specification:
+ *   https://www.emcraft.com/jdownloads/som/m2s/m2s-som-ha.pdf
+ *
  * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
@@ -XXX,XX +XXX,XX @@ static void emcraft_sf2_s2s010_init(MachineState *machine)
 
     /* Attach SPI flash to SPI0 controller */
     spi_bus = qdev_get_child_bus(dev, "spi0");
-    spi_flash = qdev_new("s25sl12801");
+    spi_flash = qdev_new("s25sl12801"); /* Spansion S25FL128SDPBHICO */
     qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
     if (dinfo) {
         qdev_prop_set_drive_err(spi_flash, "drive",
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_emcraft_sf2(self):
         spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501'
         spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash)
 
+        file_truncate(spi_path, 16 << 20) # Spansion S25FL128SDPBHICO is 16 MiB
+
         self.vm.set_console()
         kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE
         self.vm.add_args('-kernel', uboot_path,
-- 
2.39.1

From: Guenter Roeck <linux@roeck-us.net>

supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
the Supermicro documentation for X11 BMCs, and it does not match the
devicetree file in the Linux kernel.

As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
while others use AST2500.

Introduce new machine type supermicrox11-spi-bmc with AST2500 SoC
to match the devicetree description in the Linux kernel. Hardware
configuration details for this machine type are guesswork and taken
from defaults as well as from the Linux kernel devicetree file.

The new machine type was tested with aspeed-bmc-supermicro-x11spi.dts
from the Linux kernel and with Linux versions 6.0.3 and 6.1-rc2.
Linux booted successfully from initrd and from both SPI interfaces.
Ethernet interfaces were confirmed to be operational.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20221025165109.1226001-1-linux@roeck-us.net
[ clg: Renamed machine to 'supermicro-x11spi-bmc' ]
Message-Id: <20221025165109.1226001-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
         SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) |                       \
         SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
 
+/* TODO: Find the actual hardware value */
+#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 (                               \
+        AST2500_HW_STRAP1_DEFAULTS |                                    \
+        SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE |                     \
+        SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE |                        \
+        SCU_AST2500_HW_STRAP_UART_DEBUG |                               \
+        SCU_AST2500_HW_STRAP_DDR4_ENABLE |                              \
+        SCU_HW_STRAP_SPI_WIDTH |                                        \
+        SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN))
+
 /* AST2500 evb hardware value: 0xF100C2E6 */
 #define AST2500_EVB_HW_STRAP1 ((                                        \
         AST2500_HW_STRAP1_DEFAULTS |                                    \
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
     mc->default_ram_size = 256 * MiB;
 }
 
+static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
+                                                            void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+    mc->desc       = "Supermicro X11 SPI BMC (ARM1176)";
+    amc->soc_name  = "ast2500-a1";
+    amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1;
+    amc->fmc_model = "mx25l25635e";
+    amc->spi_model = "mx25l25635e";
+    amc->num_cs    = 1;
+    amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+    amc->i2c_init  = palmetto_bmc_i2c_init;
+    mc->default_ram_size = 512 * MiB;
+    mc->default_cpus = mc->min_cpus = mc->max_cpus =
+        aspeed_soc_num_cpus(amc->soc_name);
+}
+
 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
+    }, {
+        .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
+        .parent        = TYPE_ASPEED_MACHINE,
+        .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
     }, {
         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
-- 
2.39.1

From: Stephen Longfield <slongfield@google.com>

With the `size += 4` before the call to `crc32`, the CRC calculation
would overrun the buffer. Size is used in the while loop starting on
line 1009 to determine how much data to write back, with the last
four bytes coming from `crc_ptr`, so do need to increase it, but should
do this after the computation.

I'm unsure why this use of uninitialized memory in the CRC doesn't
result in CRC errors, but it seems clear to me that it should not be
included in the calculation.

Signed-off-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20221220221437.3303721-1-slongfield@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/net/ftgmac100.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
         return size;
     }
 
-    /* 4 bytes for the CRC.  */
-    size += 4;
     crc = cpu_to_be32(crc32(~0, buf, size));
+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
+    size += 4;
     crc_ptr = (uint8_t *) &crc;
 
     /* Huge frames are truncated.  */
-- 
2.39.1

From: Joel Stanley <joel@jms.id.au>

Update the test_arm_ast2600_debian test to

- the latest Debian kernel
 - use the Rainier machine instead of Tacoma

Both of which contains support for more hardware and thus exercises more
of the hardware Qemu models.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220607011938.1676459-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/boot_linux_console.py | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_vexpressa9(self):
     def test_arm_ast2600_debian(self):
         """
         :avocado: tags=arch:arm
-        :avocado: tags=machine:tacoma-bmc
+        :avocado: tags=machine:rainier-bmc
         """
         deb_url = ('http://snapshot.debian.org/archive/debian/'
-                   '20210302T203551Z/'
+                   '20220606T211338Z/'
                    'pool/main/l/linux/'
-                   'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb')
-        deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e'
+                   'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
+        deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
         deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
                                     algorithm='sha256')
-        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp')
+        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
         dtb_path = self.extract_from_deb(deb_path,
-                '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb')
+                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
 
         self.vm.set_console()
         self.vm.add_args('-kernel', kernel_path,
-- 
2.39.1

From: Guenter Roeck <linux@roeck-us.net>

Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
	xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp

Cc: Michael Walle <michael@walle.cc>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20221221122213.1458540-1-linux@roeck-us.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
 uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
 
+uint8_t m25p80_sfdp_is25wp256(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("is25wp032",   0x9d7016,      0,  64 << 10,  64, ER_4K) },
     { INFO("is25wp064",   0x9d7017,      0,  64 << 10, 128, ER_4K) },
     { INFO("is25wp128",   0x9d7018,      0,  64 << 10, 256, ER_4K) },
-    { INFO("is25wp256",   0x9d7019,      0,  64 << 10, 512, ER_4K) },
+    { INFO("is25wp256",   0x9d7019,      0,  64 << 10, 512, ER_4K),
+      .sfdp_read = m25p80_sfdp_is25wp256 },
 
     /* Macronix */
     { INFO("mx25l2005a",  0xc22012,      0,  64 << 10,   4, ER_4K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q01jvq[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(w25q01jvq);
+
+/*
+ * Integrated Silicon Solution (ISSI)
+ */
+
+static const uint8_t sfdp_is25wp256[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
+    0x9d, 0x05, 0x01, 0x03, 0x80, 0x00, 0x00, 0x02,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf9, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x80, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0x23, 0x4a, 0xc9, 0x00,
+    0x82, 0xd8, 0x11, 0xce, 0xcc, 0xcd, 0x68, 0x46,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xae, 0xd5, 0x5c,
+    0x4a, 0x42, 0x2c, 0xff, 0xf0, 0x30, 0xfa, 0xa9,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x50, 0x19, 0x50, 0x16, 0x9f, 0xf9, 0xc0, 0x64,
+    0x8f, 0xef, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(is25wp256);
-- 
2.39.1

Use buildroot 2022.11 based images plus some customization :

- Linux version is bumped to 6.0.9 and kernel is built with a custom
    config similar to what OpenBMC provides.
  - U-Boot is switched to the one provided by OpenBMC for better support.
  - defconfigs includes more target tools for dev.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20230119123449.531826-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_buildroot(self):
         """
 
         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-                     'images/ast2500-evb/buildroot-2022.05/flash.img')
-        image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
+                     'images/ast2500-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
+        image_hash = ('f96d11db521fe7a2787745e9e391225deeeec3318ee0fc07c8b799b8833dd474')
         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
                                       algorithm='sha256')
 
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
         """
 
         image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-                     'images/ast2600-evb/buildroot-2022.05/flash.img')
-        image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
+                     'images/ast2600-evb/buildroot-2022.11-2-g15d3648df9/flash.img')
+        image_hash = ('e598d86e5ea79671ca8b59212a326c911bc8bea728dec1a1f5390d717a28bb8b')
         image_path = self.fetch_asset(image_url, asset_hash=image_hash,
                                       algorithm='sha256')
 
-- 
2.39.1

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20230119123449.531826-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_buildroot(self):
 
 class AST2x00MachineSDK(QemuSystemTest):
 
-    EXTRA_BOOTARGS = ' quiet'
+    EXTRA_BOOTARGS = (
+        'quiet '
+        'systemd.mask=org.openbmc.HostIpmi.service '
+        'systemd.mask=xyz.openbmc_project.Chassis.Control.Power@0.service '
+        'systemd.mask=modprobe@fuse.service '
+        'systemd.mask=rngd.service '
+        'systemd.mask=obmc-console@ttyS2.service '
+    )
 
     # FIXME: Although these tests boot a whole distro they are still
     # slower than comparable machine models. There may be some
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image):
         interrupt_interactive_console_until_pattern(
             self, 'Hit any key to stop autoboot:', 'ast#')
         exec_command_and_wait_for_pattern(
-            self, 'setenv bootargs ${bootargs}' + self.EXTRA_BOOTARGS, 'ast#')
+            self, 'setenv bootargs ${bootargs} ' + self.EXTRA_BOOTARGS, 'ast#')
         exec_command_and_wait_for_pattern(
             self, 'boot', '## Loading kernel from FIT Image')
         self.wait_for_console_pattern('Starting kernel ...')
-- 
2.39.1

These globals were moved to MachineClass by commit 71ae9e94d9 ("pc: Move
option_rom_has_mr/rom_file_has_mr globals to MachineClass"). Finish cleanup.

Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/loader.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -XXX,XX +XXX,XX @@ void pstrcpy_targphys(const char *name,
                       hwaddr dest, int buf_size,
                       const char *source);
 
-extern bool option_rom_has_mr;
-extern bool rom_file_has_mr;
-
 ssize_t rom_add_file(const char *file, const char *fw_dir,
                      hwaddr addr, int32_t bootindex,
                      bool option_rom, MemoryRegion *mr, AddressSpace *as);
-- 
2.39.1

From: Peter Delevoryas <peter@pjd.dev>

This helper is useful in board initialization because lets users initialize and
realize an EEPROM on an I2C bus with a single function call.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Link: https://lore.kernel.org/r/20230128060543.95582-2-peter@pjd.dev
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/nvram/eeprom_at24c.h | 23 +++++++++++++++++++++++
 hw/arm/aspeed.c                 | 10 +---------
 hw/arm/npcm7xx_boards.c         | 20 +++++---------------
 hw/nvram/eeprom_at24c.c         | 12 ++++++++++++
 4 files changed, 41 insertions(+), 24 deletions(-)
 create mode 100644 include/hw/nvram/eeprom_at24c.h

diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/nvram/eeprom_at24c.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#ifndef EEPROM_AT24C_H
+#define EEPROM_AT24C_H
+
+#include "hw/i2c/i2c.h"
+
+/*
+ * Create and realize an AT24C EEPROM device on the heap.
+ * @bus: I2C bus to put it on
+ * @address: I2C address of the EEPROM slave when put on a bus
+ * @rom_size: size of the EEPROM
+ *
+ * Create the device state structure, initialize it, put it on the specified
+ * @bus, and drop the reference to it (the device is realized).
+ */
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
+
+#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/i2c/i2c_mux_pca954x.h"
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/misc/pca9552.h"
+#include "hw/nvram/eeprom_at24c.h"
 #include "hw/sensor/tmp105.h"
 #include "hw/misc/led.h"
 #include "hw/qdev-properties.h"
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
 }
 
-static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
-{
-    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
-    DeviceState *dev = DEVICE(i2c_dev);
-
-    qdev_prop_set_uint32(dev, "rom-size", rsize);
-    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-}
-
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/i2c/i2c_mux_pca954x.h"
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/loader.h"
+#include "hw/nvram/eeprom_at24c.h"
 #include "hw/qdev-core.h"
 #include "hw/qdev-properties.h"
 #include "qapi/error.h"
@@ -XXX,XX +XXX,XX @@ static I2CBus *npcm7xx_i2c_get_bus(NPCM7xxState *soc, uint32_t num)
     return I2C_BUS(qdev_get_child_bus(DEVICE(&soc->smbus[num]), "i2c-bus"));
 }
 
-static void at24c_eeprom_init(NPCM7xxState *soc, int bus, uint8_t addr,
-                              uint32_t rsize)
-{
-    I2CBus *i2c_bus = npcm7xx_i2c_get_bus(soc, bus);
-    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
-    DeviceState *dev = DEVICE(i2c_dev);
-
-    qdev_prop_set_uint32(dev, "rom-size", rsize);
-    i2c_slave_realize_and_unref(i2c_dev, i2c_bus, &error_abort);
-}
-
 static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,
                                       NPCM7xxState *soc, const int *fan_counts)
 {
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc)
     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 3), "tmp105", 0x5c);
     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), "tmp105", 0x5c);
 
-    at24c_eeprom_init(soc, 9, 0x55, 8192);
-    at24c_eeprom_init(soc, 10, 0x55, 8192);
+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 9), 0x55, 8192);
+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 10), 0x55, 8192);
 
     /*
      * i2c-11:
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
 
     i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 4), TYPE_PCA9548, 0x77);
 
-    at24c_eeprom_init(soc, 4, 0x50, 8192); /* mbfru */
+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 4), 0x50, 8192); /* mbfru */
 
     i2c_mux = i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 13),
                                       TYPE_PCA9548, 0x77);
@@ -XXX,XX +XXX,XX @@ static void kudo_bmc_i2c_init(NPCM7xxState *soc)
     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 4), "tmp105", 0x48);
     i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), "tmp105", 0x49);
 
-    at24c_eeprom_init(soc, 14, 0x55, 8192); /* bmcfru */
+    at24c_eeprom_init(npcm7xx_i2c_get_bus(soc, 14), 0x55, 8192); /* bmcfru */
 
     /* TODO: Add remaining i2c devices. */
 }
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/module.h"
 #include "hw/i2c/i2c.h"
+#include "hw/nvram/eeprom_at24c.h"
 #include "hw/qdev-properties.h"
 #include "hw/qdev-properties-system.h"
 #include "sysemu/block-backend.h"
@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
     return 0;
 }
 
+I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
+{
+    I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
+    DeviceState *dev = DEVICE(i2c_dev);
+
+    qdev_prop_set_uint32(dev, "rom-size", rom_size);
+    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+
+    return i2c_dev;
+}
+
 static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
 {
     EEPROMState *ee = AT24C_EE(dev);
-- 
2.39.1

From: Peter Delevoryas <peter@pjd.dev>

aspeed_eeprom_init is an exact copy of at24c_eeprom_init, not needed.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Link: https://lore.kernel.org/r/20230128060543.95582-3-peter@pjd.dev
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 95 ++++++++++++++++++++++---------------------------
 1 file changed, 43 insertions(+), 52 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
                           eeprom_buf);
 }
 
-static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
-{
-    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
-    DeviceState *dev = DEVICE(i2c_dev);
-
-    qdev_prop_set_uint32(dev, "rom-size", rsize);
-    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
-}
-
 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = &bmc->soc;
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     AspeedSoCState *soc = &bmc->soc;
     I2CSlave *i2c_mux;
 
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
 
     create_pca9552(soc, 3, 0x61);
 
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                      0x4a);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
                                       "pca9546", 0x70);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
     create_pca9552(soc, 4, 0x60);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     create_pca9552(soc, 5, 0x61);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
                                       "pca9546", 0x70);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
                      0x48);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                      0x4b);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
                                       "pca9546", 0x70);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
 
     create_pca9552(soc, 7, 0x30);
     create_pca9552(soc, 7, 0x31);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
                      0x48);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
                      0x48);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
                      0x4a);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
     create_pca9552(soc, 8, 0x60);
     create_pca9552(soc, 8, 0x61);
     /* Bus 8: ucd90320@11 */
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
                      0x48);
@@ -XXX,XX +XXX,XX @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
                      0x49);
     i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
                                       "pca9546", 0x70);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
-    aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+    at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
     create_pca9552(soc, 11, 0x60);
 
 
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
     create_pca9552(soc, 13, 0x60);
 
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
     create_pca9552(soc, 14, 0x60);
 
-    aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
+    at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
     create_pca9552(soc, 15, 0x60);
 }
 
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
     i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
 
-    aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
-    aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
+    at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
+    at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
 
     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
     i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
     i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
 
-    aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
+    at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
     i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
 
     i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
-    aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
     i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
     i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
 
     i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
     i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
 
-    aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
+    at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
     i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
-    aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
 
-    aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
+    at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
     i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
-    aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
-    aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
+    at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
+    at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
 
     for (int i = 0; i < 8; i++) {
-        aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
+        at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
         i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
         i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
         i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
     i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
 
-    aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
-    aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
-    aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
-    aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
-    aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
+    at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
+    at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
+    at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
+    at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
+    at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
 
     /*
      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
-- 
2.39.1

From: Peter Delevoryas <peter@pjd.dev>

Allows users to specify binary data to initialize an EEPROM, allowing users to
emulate data programmed at manufacturing time.

- Added init_rom and init_rom_size attributes to TYPE_AT24C_EE
- Added at24c_eeprom_init_rom helper function to initialize attributes
- If -drive property is provided, it overrides init_rom data

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Ninad Palsule <ninadpalsule@us.ibm.com>
Link: https://lore.kernel.org/r/20230128060543.95582-4-peter@pjd.dev
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/nvram/eeprom_at24c.h | 16 +++++++++++++++
 hw/nvram/eeprom_at24c.c         | 36 ++++++++++++++++++++++++++++-----
 2 files changed, 47 insertions(+), 5 deletions(-)

diff --git a/include/hw/nvram/eeprom_at24c.h b/include/hw/nvram/eeprom_at24c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/nvram/eeprom_at24c.h
+++ b/include/hw/nvram/eeprom_at24c.h
@@ -XXX,XX +XXX,XX @@
  */
 I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size);
 
+
+/*
+ * Create and realize an AT24C EEPROM device on the heap with initial data.
+ * @bus: I2C bus to put it on
+ * @address: I2C address of the EEPROM slave when put on a bus
+ * @rom_size: size of the EEPROM
+ * @init_rom: Array of bytes to initialize EEPROM memory with
+ * @init_rom_size: Size of @init_rom, must be less than or equal to @rom_size
+ *
+ * Create the device state structure, initialize it, put it on the specified
+ * @bus, and drop the reference to it (the device is realized). Copies the data
+ * from @init_rom to the beginning of the EEPROM memory buffer.
+ */
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
+                                const uint8_t *init_rom, uint32_t init_rom_size);
+
 #endif
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -XXX,XX +XXX,XX @@ struct EEPROMState {
     uint8_t *mem;
 
     BlockBackend *blk;
+
+    const uint8_t *init_rom;
+    uint32_t init_rom_size;
 };
 
 static
@@ -XXX,XX +XXX,XX @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
 
 I2CSlave *at24c_eeprom_init(I2CBus *bus, uint8_t address, uint32_t rom_size)
 {
-    I2CSlave *i2c_dev = i2c_slave_new(TYPE_AT24C_EE, address);
-    DeviceState *dev = DEVICE(i2c_dev);
+    return at24c_eeprom_init_rom(bus, address, rom_size, NULL, 0);
+}
+
+I2CSlave *at24c_eeprom_init_rom(I2CBus *bus, uint8_t address, uint32_t rom_size,
+                                const uint8_t *init_rom, uint32_t init_rom_size)
+{
+    EEPROMState *s;
+
+    s = AT24C_EE(i2c_slave_new(TYPE_AT24C_EE, address));
+
+    qdev_prop_set_uint32(DEVICE(s), "rom-size", rom_size);
 
-    qdev_prop_set_uint32(dev, "rom-size", rom_size);
-    i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
+    /* TODO: Model init_rom with QOM properties. */
+    s->init_rom = init_rom;
+    s->init_rom_size = init_rom_size;
 
-    return i2c_dev;
+    i2c_slave_realize_and_unref(I2C_SLAVE(s), bus, &error_abort);
+
+    return I2C_SLAVE(s);
 }
 
 static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
 {
     EEPROMState *ee = AT24C_EE(dev);
 
+    if (ee->init_rom_size > ee->rsize) {
+        error_setg(errp, "%s: init rom is larger than rom: %u > %u",
+                   TYPE_AT24C_EE, ee->init_rom_size, ee->rsize);
+        return;
+    }
+
     if (ee->blk) {
         int64_t len = blk_getlength(ee->blk);
 
@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
     }
 
     ee->mem = g_malloc0(ee->rsize);
+
 }
 
 static
@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
 
     memset(ee->mem, 0, ee->rsize);
 
+    if (ee->init_rom) {
+        memcpy(ee->mem, ee->init_rom, MIN(ee->init_rom_size, ee->rsize));
+    }
+
     if (ee->blk) {
         int ret = blk_pread(ee->blk, 0, ee->rsize, ee->mem, 0);
 
-- 
2.39.1

From: Peter Delevoryas <peter@pjd.dev>

- Create aspeed_eeprom.c and aspeed_eeprom.h
- Include aspeed_eeprom.c in CONFIG_ASPEED meson source files
- Include aspeed_eeprom.h in aspeed.c
- Add fby35_bmc_fruid data
- Use new at24c_eeprom_init_rom helper to initialize BMC FRUID EEPROM with data
  from aspeed_eeprom.c

wget https://github.com/facebook/openbmc/releases/download/openbmc-e2294ff5d31d/fby35.mtd
qemu-system-aarch64 -machine fby35-bmc -nographic -mtdblock fby35.mtd
...
user: root
pass: 0penBmc
...
root@bmc-oob:~# fruid-util bb

FRU Information           : Baseboard
---------------           : ------------------
Chassis Type              : Rack Mount Chassis
Chassis Part Number       : N/A
Chassis Serial Number     : N/A
Board Mfg Date            : Fri Jan  7 10:30:00 2022
Board Mfg                 : XXXXXX
Board Product             : Management Board wBMC
Board Serial              : XXXXXXXXXXXXX
Board Part Number         : XXXXXXXXXXXXXX
Board FRU ID              : 1.0
Board Custom Data 1       : XXXXXXXXX
Board Custom Data 2       : XXXXXXXXXXXXXXXXXX
Product Manufacturer      : XXXXXX
Product Name              : Yosemite V3.5 EVT2
Product Part Number       : XXXXXXXXXXXXXX
Product Version           : EVT2
Product Serial            : XXXXXXXXXXXXX
Product Asset Tag         : XXXXXXX
Product FRU ID            : 1.0
Product Custom Data 1     : XXXXXXXXX
Product Custom Data 2     : N/A
root@bmc-oob:~# fruid-util bmc

FRU Information           : BMC
---------------           : ------------------
Board Mfg Date            : Mon Jan 10 21:42:00 2022
Board Mfg                 : XXXXXX
Board Product             : BMC Storage Module
Board Serial              : XXXXXXXXXXXXX
Board Part Number         : XXXXXXXXXXXXXX
Board FRU ID              : 1.0
Board Custom Data 1       : XXXXXXXXX
Board Custom Data 2       : XXXXXXXXXXXXXXXXXX
Product Manufacturer      : XXXXXX
Product Name              : Yosemite V3.5 EVT2
Product Part Number       : XXXXXXXXXXXXXX
Product Version           : EVT2
Product Serial            : XXXXXXXXXXXXX
Product Asset Tag         : XXXXXXX
Product FRU ID            : 1.0
Product Custom Data 1     : XXXXXXXXX
Product Custom Data 2     : Config A
root@bmc-oob:~# fruid-util nic

FRU Information           : NIC
---------------           : ------------------
Board Mfg Date            : Tue Nov  2 08:51:00 2021
Board Mfg                 : XXXXXXXX
Board Product             : Mellanox ConnectX-6 DX OCP3.0
Board Serial              : XXXXXXXXXXXXXXXXXXXXXXXX
Board Part Number         : XXXXXXXXXXXXXXXXXXXXX
Board FRU ID              : FRU Ver 0.02
Product Manufacturer      : XXXXXXXX
Product Name              : Mellanox ConnectX-6 DX OCP3.0
Product Part Number       : XXXXXXXXXXXXXXXXXXXXX
Product Version           : A9
Product Serial            : XXXXXXXXXXXXXXXXXXXXXXXX
Product Custom Data 3     : ConnectX-6 DX

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Link: https://lore.kernel.org/r/20230128060543.95582-5-peter@pjd.dev
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_eeprom.h | 19 ++++++++++
 hw/arm/aspeed.c        | 10 ++++--
 hw/arm/aspeed_eeprom.c | 82 ++++++++++++++++++++++++++++++++++++++++++
 hw/arm/meson.build     |  1 +
 4 files changed, 109 insertions(+), 3 deletions(-)
 create mode 100644 hw/arm/aspeed_eeprom.h
 create mode 100644 hw/arm/aspeed_eeprom.c

diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_eeprom.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#ifndef ASPEED_EEPROM_H
+#define ASPEED_EEPROM_H
+
+#include "qemu/osdep.h"
+
+extern const uint8_t fby35_nic_fruid[];
+extern const uint8_t fby35_bb_fruid[];
+extern const uint8_t fby35_bmc_fruid[];
+extern const size_t fby35_nic_fruid_len;
+extern const size_t fby35_bb_fruid_len;
+extern const size_t fby35_bmc_fruid_len;
+
+#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/boot.h"
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
+#include "hw/arm/aspeed_eeprom.h"
 #include "hw/i2c/i2c_mux_pca954x.h"
 #include "hw/i2c/smbus_eeprom.h"
 #include "hw/misc/pca9552.h"
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
 
     at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
     at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
-    at24c_eeprom_init(i2c[8], 0x50, 32 * KiB);
-    at24c_eeprom_init(i2c[11], 0x51, 128 * KiB);
-    at24c_eeprom_init(i2c[11], 0x54, 128 * KiB);
+    at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
+                          fby35_nic_fruid_len);
+    at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
+                          fby35_bb_fruid_len);
+    at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
+                          fby35_bmc_fruid_len);
 
     /*
      * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_eeprom.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) Meta Platforms, Inc. and affiliates.
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+#include "aspeed_eeprom.h"
+
+const uint8_t fby35_nic_fruid[] = {
+    0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
+    0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
+    0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
+    0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
+    0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
+    0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
+    0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
+    0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
+    0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+    0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
+    0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
+    0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
+    0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
+    0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
+};
+
+const uint8_t fby35_bb_fruid[] = {
+    0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
+    0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
+    0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
+    0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+    0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+    0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
+    0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
+};
+
+const uint8_t fby35_bmc_fruid[] = {
+    0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
+    0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
+    0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
+    0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
+    0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+    0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+    0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+    0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
+    0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
+};
+
+const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
+const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
+const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
+  'aspeed_eeprom.c',
   'fby35.c'))
 arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
 arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
-- 
2.39.1

From: Peter Delevoryas <peter@pjd.dev>

EEPROM's are a form of non-volatile memory. After power-cycling an EEPROM,
I would expect the I2C state machine to be reset to default values, but I
wouldn't really expect the memory to change at all.

The current implementation of the at24c EEPROM resets its internal memory on
reset. This matches the specification in docs/devel/reset.rst:

Cold reset is supported by every resettable object. In QEMU, it means we reset
  to the initial state corresponding to the start of QEMU; this might differ
  from what is a real hardware cold reset. It differs from other resets (like
  warm or bus resets) which may keep certain parts untouched.

But differs from my intuition. For example, if someone writes some information
to an EEPROM, then AC power cycles their board, they would expect the EEPROM to
retain that information. It's very useful to be able to test things like this
in QEMU as well, to verify software instrumentation like determining the cause
of a reboot.

Fixes: 5d8424dbd3e8 ("nvram: add AT24Cx i2c eeprom")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Link: https://lore.kernel.org/r/20230128060543.95582-6-peter@pjd.dev
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/nvram/eeprom_at24c.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -XXX,XX +XXX,XX @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
     }
 
     ee->mem = g_malloc0(ee->rsize);
-
-}
-
-static
-void at24c_eeprom_reset(DeviceState *state)
-{
-    EEPROMState *ee = AT24C_EE(state);
-
-    ee->changed = false;
-    ee->cur = 0;
-    ee->haveaddr = 0;
-
     memset(ee->mem, 0, ee->rsize);
 
     if (ee->init_rom) {
@@ -XXX,XX +XXX,XX @@ void at24c_eeprom_reset(DeviceState *state)
     }
 }
 
+static
+void at24c_eeprom_reset(DeviceState *state)
+{
+    EEPROMState *ee = AT24C_EE(state);
+
+    ee->changed = false;
+    ee->cur = 0;
+    ee->haveaddr = 0;
+}
+
 static Property at24c_eeprom_props[] = {
     DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
     DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Avoid confusing two different things:
- the WDT I/O region size ('iosize')
- at which offset the SoC map the WDT ('offset')
While it is often the same, we can map smaller region sizes
at larger offsets.

Here we are interested in the I/O region size, so rename as
'iosize'.

Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[ clg: Introduced temporary wdt_offset variable ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/watchdog/wdt_aspeed.h | 2 +-
 hw/arm/aspeed_ast10x0.c          | 4 ++--
 hw/arm/aspeed_ast2600.c          | 4 ++--
 hw/arm/aspeed_soc.c              | 4 ++--
 hw/watchdog/wdt_aspeed.c         | 8 ++++----
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -XXX,XX +XXX,XX @@ struct AspeedWDTState {
 struct AspeedWDTClass {
     SysBusDeviceClass parent_class;
 
-    uint32_t offset;
+    uint32_t iosize;
     uint32_t ext_pulse_width_mask;
     uint32_t reset_ctrl_reg;
     void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     /* Watch dog */
     for (i = 0; i < sc->wdts_num; i++) {
         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
 
         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                  &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
             return;
         }
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
-                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
     }
 
     /* GPIO */
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     /* Watch dog */
     for (i = 0; i < sc->wdts_num; i++) {
         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
 
         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                  &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
             return;
         }
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
-                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
     }
 
     /* RAM */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
     /* Watch dog */
     for (i = 0; i < sc->wdts_num; i++) {
         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
+        hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize;
 
         object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
                                  &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
             return;
         }
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
-                        sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset);
     }
 
     /* RAM  */
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 
     dc->desc = "ASPEED 2400 Watchdog Controller";
-    awc->offset = 0x20;
+    awc->iosize = 0x20;
     awc->ext_pulse_width_mask = 0xff;
     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
     awc->wdt_reload = aspeed_wdt_reload;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 
     dc->desc = "ASPEED 2500 Watchdog Controller";
-    awc->offset = 0x20;
+    awc->iosize = 0x20;
     awc->ext_pulse_width_mask = 0xfffff;
     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 
     dc->desc = "ASPEED 2600 Watchdog Controller";
-    awc->offset = 0x40;
+    awc->iosize = 0x40;
     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
@@ -XXX,XX +XXX,XX @@ static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 
     dc->desc = "ASPEED 1030 Watchdog Controller";
-    awc->offset = 0x80;
+    awc->iosize = 0x80;
     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

When booting the Zephyr demo in [1] we get:

aspeed.io: unimplemented device write (size 4, offset 0x185128, value 0x030f1ff1) <--
  aspeed.io: unimplemented device write (size 4, offset 0x18512c, value 0x03fffff1)

This corresponds to this Zephyr code [2]:

static int aspeed_wdt_init(const struct device *dev)
  {
    const struct aspeed_wdt_config *config = dev->config;
    struct aspeed_wdt_data *const data = dev->data;
    uint32_t reg_val;

/* disable WDT by default */
    reg_val = sys_read32(config->ctrl_base + WDT_CTRL_REG);
    reg_val &= ~WDT_CTRL_ENABLE;
    sys_write32(reg_val, config->ctrl_base + WDT_CTRL_REG);

sys_write32(data->rst_mask1,
                config->ctrl_base + WDT_SW_RESET_MASK1_REG);   <------
    sys_write32(data->rst_mask2,
                config->ctrl_base + WDT_SW_RESET_MASK2_REG);

return 0;
  }

The register definitions are [3]:

#define WDT_RELOAD_VAL_REG          0x0004
  #define WDT_RESTART_REG             0x0008
  #define WDT_CTRL_REG                0x000C
  #define WDT_TIMEOUT_STATUS_REG      0x0010
  #define WDT_TIMEOUT_STATUS_CLR_REG  0x0014
  #define WDT_RESET_MASK1_REG         0x001C
  #define WDT_RESET_MASK2_REG         0x0020
  #define WDT_SW_RESET_MASK1_REG      0x0028   <------
  #define WDT_SW_RESET_MASK2_REG      0x002C
  #define WDT_SW_RESET_CTRL_REG       0x0024

Currently QEMU only cover a MMIO region of size 0x20:

#define ASPEED_WDT_REGS_MAX        (0x20 / 4)

Change to map the whole 'iosize' which might be bigger, covering
the other registers. The MemoryRegionOps read/write handlers will
report the accesses as out-of-bounds guest-errors, but the next
commit will report them as unimplemented.

[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
[2] https://github.com/AspeedTech-BMC/zephyr/commit/2e99f10ac27b
[3] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31

Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/watchdog/wdt_aspeed.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     AspeedWDTState *s = ASPEED_WDT(dev);
+    AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(dev);
 
     assert(s->scu);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
     s->pclk_freq = PCLK_HZ;
 
     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
-                          TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
+                          TYPE_ASPEED_WDT, awc->iosize);
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Add more Aspeed watchdog registers from [*].

Since guests can righteously access them, log the access at
'unimplemented' level instead of 'guest-errors'.

[*] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/drivers/watchdog/wdt_aspeed.c#L31

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/watchdog/wdt_aspeed.h |  2 +-
 hw/watchdog/wdt_aspeed.c         | 13 +++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_aspeed.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/watchdog/wdt_aspeed.h
+++ b/include/hw/watchdog/wdt_aspeed.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedWDTState, AspeedWDTClass, ASPEED_WDT)
 #define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
 #define TYPE_ASPEED_1030_WDT TYPE_ASPEED_WDT "-ast1030"
 
-#define ASPEED_WDT_REGS_MAX        (0x20 / 4)
+#define ASPEED_WDT_REGS_MAX        (0x30 / 4)
 
 struct AspeedWDTState {
     /*< private >*/
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -XXX,XX +XXX,XX @@
 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
 #define WDT_RESET_MASK1                 (0x1c / 4)
+#define WDT_RESET_MASK2                 (0x20 / 4)
+
+#define WDT_SW_RESET_CTRL               (0x24 / 4)
+#define WDT_SW_RESET_MASK1              (0x28 / 4)
+#define WDT_SW_RESET_MASK2              (0x2c / 4)
 
 #define WDT_TIMEOUT_STATUS              (0x10 / 4)
 #define WDT_TIMEOUT_CLEAR               (0x14 / 4)
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
         return s->regs[WDT_RESET_MASK1];
     case WDT_TIMEOUT_STATUS:
     case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_MASK2:
+    case WDT_SW_RESET_CTRL:
+    case WDT_SW_RESET_MASK1:
+    case WDT_SW_RESET_MASK2:
         qemu_log_mask(LOG_UNIMP,
                       "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
                       __func__, offset);
@@ -XXX,XX +XXX,XX @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
 
     case WDT_TIMEOUT_STATUS:
     case WDT_TIMEOUT_CLEAR:
+    case WDT_RESET_MASK2:
+    case WDT_SW_RESET_CTRL:
+    case WDT_SW_RESET_MASK1:
+    case WDT_SW_RESET_MASK2:
         qemu_log_mask(LOG_UNIMP,
                       "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
                       __func__, offset);
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

address_space_map() can fail:

uart:~$ hash test
  sha256_test
  tv[0]:
  Segmentation fault: 11
  Thread 3 "qemu-system-arm" received signal SIGSEGV, Segmentation fault.
  gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
      at ../hw/misc/aspeed_hace.c:171
  171         if (has_padding(s, &iov[id], *req_len, &total_msg_len, &pad_offset)) {
  (gdb) bt
  #0  gen_acc_mode_iov (req_len=0x7ffff18b7778, id=<optimized out>, iov=0x7ffff18b7780, s=0x555556ce0bd0)
      at ../hw/misc/aspeed_hace.c:171
  #1  do_hash_operation (s=s@entry=0x555556ce0bd0, algo=3, sg_mode=sg_mode@entry=true, acc_mode=acc_mode@entry=true)
      at ../hw/misc/aspeed_hace.c:224
  #2  0x00005555559bdbb8 in aspeed_hace_write (opaque=<optimized out>, addr=12, data=262488, size=<optimized out>)
      at ../hw/misc/aspeed_hace.c:358

This change doesn't fix much, but at least the guest
can't crash QEMU anymore. Instead it is still usable:

uart:~$ hash test
  sha256_test
  tv[0]:hash_final error
  sha384_test
  tv[0]:hash_final error
  sha512_test
  tv[0]:hash_final error
  [00:00:06.278,000] <err> hace_global: HACE poll timeout
  [00:00:09.324,000] <err> hace_global: HACE poll timeout
  [00:00:12.261,000] <err> hace_global: HACE poll timeout
  uart:~$

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/misc/aspeed_hace.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/aspeed_hace.c
+++ b/hw/misc/aspeed_hace.c
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
     size_t digest_len = 0;
     int niov = 0;
     int i;
+    void *haddr;
 
     if (sg_mode) {
         uint32_t len = 0;
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
             addr &= SG_LIST_ADDR_MASK;
 
             plen = len & SG_LIST_LEN_MASK;
-            iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false,
-                                                MEMTXATTRS_UNSPECIFIED);
-
+            haddr = address_space_map(&s->dram_as, addr, &plen, false,
+                                      MEMTXATTRS_UNSPECIFIED);
+            if (haddr == NULL) {
+                qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
+                return;
+            }
+            iov[i].iov_base = haddr;
             if (acc_mode) {
                 niov = gen_acc_mode_iov(s, iov, i, &plen);
 
@@ -XXX,XX +XXX,XX @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode,
     } else {
         hwaddr len = s->regs[R_HASH_SRC_LEN];
 
+        haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
+                                  &len, false, MEMTXATTRS_UNSPECIFIED);
+        if (haddr == NULL) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__);
+            return;
+        }
+        iov[0].iov_base = haddr;
         iov[0].iov_len = len;
-        iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC],
-                                            &len, false,
-                                            MEMTXATTRS_UNSPECIFIED);
         i = 1;
 
         if (s->iov_count) {
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Based on booting Zephyr demo from [1] running QEMU with
'-d unimp' and checking missing devices in [2].

[1] https://github.com/AspeedTech-BMC/zephyr/releases/tag/v00.01.07
[2] https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h | 11 +++++++++++
 hw/arm/aspeed_ast10x0.c     | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_CPUS_NUM  2
 #define ASPEED_MACS_NUM  4
 #define ASPEED_UARTS_NUM 13
+#define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     UnimplementedDeviceState video;
     UnimplementedDeviceState emmc_boot_controller;
     UnimplementedDeviceState dpmcu;
+    UnimplementedDeviceState pwm;
+    UnimplementedDeviceState espi;
+    UnimplementedDeviceState udc;
+    UnimplementedDeviceState sgpiom;
+    UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
 };
 
 #define TYPE_ASPEED_SOC "aspeed-soc"
@@ -XXX,XX +XXX,XX @@ enum {
     ASPEED_DEV_DPMCU,
     ASPEED_DEV_DP,
     ASPEED_DEV_I3C,
+    ASPEED_DEV_ESPI,
+    ASPEED_DEV_UDC,
+    ASPEED_DEV_SGPIOM,
+    ASPEED_DEV_JTAG0,
+    ASPEED_DEV_JTAG1,
 };
 
 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
     [ASPEED_DEV_FMC]       = 0x7E620000,
     [ASPEED_DEV_SPI1]      = 0x7E630000,
     [ASPEED_DEV_SPI2]      = 0x7E640000,
+    [ASPEED_DEV_UDC]       = 0x7E6A2000,
     [ASPEED_DEV_SCU]       = 0x7E6E2000,
+    [ASPEED_DEV_JTAG0]     = 0x7E6E4000,
+    [ASPEED_DEV_JTAG1]     = 0x7E6E4100,
     [ASPEED_DEV_ADC]       = 0x7E6E9000,
+    [ASPEED_DEV_ESPI]      = 0x7E6EE000,
     [ASPEED_DEV_SBC]       = 0x7E6F2000,
     [ASPEED_DEV_GPIO]      = 0x7E780000,
+    [ASPEED_DEV_SGPIOM]    = 0x7E780500,
     [ASPEED_DEV_TIMER1]    = 0x7E782000,
     [ASPEED_DEV_UART1]     = 0x7E783000,
     [ASPEED_DEV_UART2]     = 0x7E78D000,
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
     [ASPEED_DEV_LPC]       = 35,
     [ASPEED_DEV_PECI]      = 38,
     [ASPEED_DEV_FMC]       = 39,
+    [ASPEED_DEV_ESPI]      = 42,
     [ASPEED_DEV_PWM]       = 44,
     [ASPEED_DEV_ADC]       = 46,
     [ASPEED_DEV_SPI1]      = 65,
     [ASPEED_DEV_SPI2]      = 66,
     [ASPEED_DEV_I2C]       = 110, /* 110 ~ 123 */
     [ASPEED_DEV_KCS]       = 138, /* 138 -> 142 */
+    [ASPEED_DEV_UDC]       = 9,
+    [ASPEED_DEV_SGPIOM]    = 51,
+    [ASPEED_DEV_JTAG0]     = 27,
+    [ASPEED_DEV_JTAG1]     = 53,
 };
 
 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "udc", &s->udc, TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "sgpiom", &s->sgpiom,
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "jtag[0]", &s->jtag[0],
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "jtag[1]", &s->jtag[1],
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                     sc->memmap[ASPEED_DEV_GPIO]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
+
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm",
+                                  sc->memmap[ASPEED_DEV_PWM], 0x100);
+
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->espi), "aspeed.espi",
+                                  sc->memmap[ASPEED_DEV_ESPI], 0x800);
+
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->udc), "aspeed.udc",
+                                  sc->memmap[ASPEED_DEV_UDC], 0x1000);
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sgpiom), "aspeed.sgpiom",
+                                  sc->memmap[ASPEED_DEV_SGPIOM], 0x100);
+
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[0]), "aspeed.jtag",
+                                  sc->memmap[ASPEED_DEV_JTAG0], 0x20);
+    aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag",
+                                  sc->memmap[ASPEED_DEV_JTAG1], 0x20);
 }
 
 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi

Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast10x0.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
     [ASPEED_DEV_WDT]       = 0x7E785000,
     [ASPEED_DEV_LPC]       = 0x7E789000,
     [ASPEED_DEV_PECI]      = 0x7E78B000,
+    [ASPEED_DEV_I3C]       = 0x7E7A0000,
     [ASPEED_DEV_I2C]       = 0x7E7B0000,
 };
 
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
     [ASPEED_DEV_ADC]       = 46,
     [ASPEED_DEV_SPI1]      = 65,
     [ASPEED_DEV_SPI2]      = 66,
+    [ASPEED_DEV_I3C]       = 102, /* 102 -> 105 */
     [ASPEED_DEV_I2C]       = 110, /* 110 ~ 123 */
     [ASPEED_DEV_KCS]       = 138, /* 138 -> 142 */
     [ASPEED_DEV_UDC]       = 9,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
     object_initialize_child(obj, "i2c", &s->i2c, typename);
 
+    object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
+
     snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
     object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
     }
 
+    /* I3C */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
+    for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+                                        sc->irqmap[ASPEED_DEV_I3C] + i);
+        /* The AST1030 I3C controller has one IRQ per bus. */
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
+    }
+
     /* PECI */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
         return;
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Some SRAM appears to be used by the Secure Boot unit and
crypto accelerators. Name it 'secure sram'.

Note, the SRAM base address was already present but unused
(the 'SBC' index is used for the MMIO peripheral).

Interestingly using CFLAGS=-Winitializer-overrides reports:

../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
    [ASPEED_DEV_SBC]       = 0x7E6F2000,
                             ^~~~~~~~~~
  ../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here
    [ASPEED_DEV_SBC]       = 0x79000000,
                             ^~~~~~~~~~
This fixes with Zephyr:

uart:~$ rsa test
  rsa test vector[0]:
  [00:00:26.156,000] <err> os: ***** BUS FAULT *****
  [00:00:26.157,000] <err> os:   Precise data bus error
  [00:00:26.157,000] <err> os:   BFAR Address: 0x79000000
  [00:00:26.158,000] <err> os: r0/a1:  0x79000000  r1/a2:  0x00000000  r2/a3:  0x00001800
  [00:00:26.158,000] <err> os: r3/a4:  0x79001800 r12/ip:  0x00000800 r14/lr:  0x0001098d
  [00:00:26.158,000] <err> os:  xpsr:  0x81000000
  [00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc
  [00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
  [00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart)
  [00:00:26.165,000] <err> os: Halting system

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
[ clg: Fixed size of Secure Boot Controller Memory ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  3 +++
 hw/arm/aspeed_ast10x0.c     | 11 ++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     AspeedSMCState spi[ASPEED_SPIS_NUM];
     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
     AspeedSBCState sbc;
+    MemoryRegion secsram;
     UnimplementedDeviceState sbc_unimplemented;
     AspeedSDMCState sdmc;
     AspeedWDTState wdt[ASPEED_WDTS_NUM];
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCClass {
     const char *cpu_type;
     uint32_t silicon_rev;
     uint64_t sram_size;
+    uint64_t secsram_size;
     int spis_num;
     int ehcis_num;
     int wdts_num;
@@ -XXX,XX +XXX,XX @@ enum {
     ASPEED_DEV_SCU,
     ASPEED_DEV_ADC,
     ASPEED_DEV_SBC,
+    ASPEED_DEV_SECSRAM,
     ASPEED_DEV_EMMC_BC,
     ASPEED_DEV_VIDEO,
     ASPEED_DEV_SRAM,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@
 
 static const hwaddr aspeed_soc_ast1030_memmap[] = {
     [ASPEED_DEV_SRAM]      = 0x00000000,
-    [ASPEED_DEV_SBC]       = 0x79000000,
+    [ASPEED_DEV_SECSRAM]   = 0x79000000,
     [ASPEED_DEV_IOMEM]     = 0x7E600000,
     [ASPEED_DEV_PWM]       = 0x7E610000,
     [ASPEED_DEV_FMC]       = 0x7E620000,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     memory_region_add_subregion(s->memory,
                                 sc->memmap[ASPEED_DEV_SRAM],
                                 &s->sram);
+    memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
+                           sc->secsram_size, &err);
+    if (err != NULL) {
+        error_propagate(errp, err);
+        return;
+    }
+    memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
+                                &s->secsram);
 
     /* SCU */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
     sc->silicon_rev = AST1030_A1_SILICON_REV;
     sc->sram_size = 0xc0000;
+    sc->secsram_size = 0x40000; /* 256 * KiB */
     sc->spis_num = 2;
     sc->ehcis_num = 0;
     sc->wdts_num = 4;
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since I don't have access to the datasheet, the relevant
values were found in:
https://github.com/AspeedTech-BMC/zephyr/blob/v00.01.08/dts/arm/aspeed/ast10x0.dtsi

Before on Zephyr:

uart:~$ crypto aes256_cbc_vault
  aes256_cbc vault key 1
  [00:00:06.699,000] <inf> hace_global: aspeed_crypto_session_setup
  [00:00:06.699,000] <inf> hace_global: data->cmd: 1c2098
  [00:00:06.699,000] <inf> hace_global: crypto_data_src: 93340
  [00:00:06.699,000] <inf> hace_global: crypto_data_dst: 93348
  [00:00:06.699,000] <inf> hace_global: crypto_ctx_base: 93300
  [00:00:06.699,000] <inf> hace_global: crypto_data_len: 80000040
  [00:00:06.699,000] <inf> hace_global: crypto_cmd_reg:  11c2098
  [00:00:09.743,000] <inf> hace_global: HACE_STS: 0
  [00:00:09.743,000] <err> hace_global: HACE poll timeout
  [00:00:09.743,000] <err> crypto: CBC mode ENCRYPT - Failed
  [00:00:09.743,000] <inf> hace_global: aspeed_crypto_session_free
  uart:~$

After:

uart:~$ hash test
  sha256_test
  tv[0]:PASS
  tv[1]:PASS
  tv[2]:PASS
  tv[3]:PASS
  tv[4]:PASS
  sha384_test
  tv[0]:PASS
  tv[1]:PASS
  tv[2]:PASS
  tv[3]:PASS
  tv[4]:PASS
  tv[5]:PASS
  sha512_test
  tv[0]:PASS
  tv[1]:PASS
  tv[2]:PASS
  tv[3]:PASS
  tv[4]:PASS
  tv[5]:PASS

uart:~$ crypto aes256_cbc_vault
  aes256_cbc vault key 1
  Was waiting for:
  6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
  ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
  30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
  f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10

But got:
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

[00:00:05.771,000] <inf> hace_global: aspeed_crypto_session_setup
  [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2098
  [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
  [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
  [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
  [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
  [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2098
  [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
  [00:00:05.772,000] <inf> crypto: Output length (encryption): 80
  [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_free
  [00:00:05.772,000] <inf> hace_global: aspeed_crypto_session_setup
  [00:00:05.772,000] <inf> hace_global: data->cmd: 1c2018
  [00:00:05.772,000] <inf> hace_global: crypto_data_src: 93340
  [00:00:05.772,000] <inf> hace_global: crypto_data_dst: 93348
  [00:00:05.772,000] <inf> hace_global: crypto_ctx_base: 93300
  [00:00:05.772,000] <inf> hace_global: crypto_data_len: 80000040
  [00:00:05.772,000] <inf> hace_global: crypto_cmd_reg:  11c2018
  [00:00:05.772,000] <inf> hace_global: HACE_STS: 1000
  [00:00:05.772,000] <inf> crypto: Output length (decryption): 64
  [00:00:05.772,000] <err> crypto: CBC mode DECRYPT - Mismatch between plaintext and decrypted cipher text
  [00:00:05.774,000] <inf> hace_global: aspeed_crypto_session_free
  uart:~$

Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast10x0.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
     [ASPEED_DEV_SPI1]      = 0x7E630000,
     [ASPEED_DEV_SPI2]      = 0x7E640000,
     [ASPEED_DEV_UDC]       = 0x7E6A2000,
+    [ASPEED_DEV_HACE]      = 0x7E6D0000,
     [ASPEED_DEV_SCU]       = 0x7E6E2000,
     [ASPEED_DEV_JTAG0]     = 0x7E6E4000,
     [ASPEED_DEV_JTAG1]     = 0x7E6E4100,
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
     object_initialize_child(obj, "gpio", &s->gpio, typename);
 
+    snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+    object_initialize_child(obj, "hace", &s->hace, typename);
+
     object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
                             TYPE_UNIMPLEMENTED_DEVICE);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
 
+    /* HACE */
+    object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram),
+                             &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+                    sc->memmap[ASPEED_DEV_HACE]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+                       aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
     /* Watch dog */
     for (i = 0; i < sc->wdts_num; i++) {
         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This SoC uses a Cortex-M4F. QEMU only implements a M4,
which is good enough. Add a TODO note in case the M4F
is added.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast10x0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     dc->realize = aspeed_soc_ast1030_realize;
 
     sc->name = "ast1030-a1";
-    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+    sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */
     sc->silicon_rev = AST1030_A1_SILICON_REV;
     sc->sram_size = 0xc0000;
     sc->secsram_size = 0x40000; /* 256 * KiB */
-- 
2.39.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Add a very quick test that runs some commands in a Zephyr shell:

$ tests/venv/bin/avocado --show=app,console run -t os:zephyr tests/avocado
  (2/2) tests/avocado/machine_aspeed.py:AST1030Machine.test_ast1030_zephyros_1_07:
  console: *** Booting Zephyr OS build v00.01.07  ***
  console: ast1030_evb demo
  console: SOC: AST1030-A1
  console: uart:~$ kernel stacks
  console: 0x36910 wdt_background (real size 1024):	unused 988	usage 36 / 1024 (3 %)
  console: 0x36ad8 shell_uart (real size 4096):	unused 3084	usage 1012 / 4096 (24 %)
  console: 0x2edb8 ADC0       (real size 400):	unused 260	usage 140 / 400 (35 %)
  console: 0x2f0f0 ADC1       (real size 400):	unused 260	usage 140 / 400 (35 %)
  console: 0x3b098 sysworkq   (real size 1024):	unused 860	usage 164 / 1024 (16 %)
  console: 0x36cc0 usbdworkq  (real size 1024):	unused 860	usage 164 / 1024 (16 %)
  console: 0x36bd8 usbworkq   (real size 1024):	unused 860	usage 164 / 1024 (16 %)
  console: 0x36a10 logging    (real size 768):	unused 548	usage 220 / 768 (28 %)
  console: 0x36ef8 idle 00    (real size 320):	unused 268	usage 52 / 320 (16 %)
  console: 0x47800 IRQ 00     (real size 2048):	unused 1504	usage 544 / 2048 (26 %)
  console: uart:~$ otp info scu
  console: SCU     BIT   reg_protect     Description
  console: ____________________________________________________________________
  console: 0x500   0x0   0x0             Disable ARM CM4 CPU boot (TXD5)
  console: 0x500   0x1   0x0            /Reserved
  console: 0x500   0x2   0x0            \ "
  console: 0x500   0x3   0x0             Address offset of single chip ABR mode
  console: 0x500   0x4   0x0            /Reserved
  console: 0x500   0x5   0x0            | "
  console: 0x500   0x6   0x0            | "
  console: 0x500   0x7   0x0            | "
  console: 0x500   0x8   0x0            | "
  console: 0x500   0x9   0x0            | "
  console: 0x500   0xA   0x0            | "
  console: 0x500   0xB   0x0            | "
  console: 0x500   0xC   0x0            | "
  console: 0x500   0xD   0x0            | "
  console: 0x500   0xE   0x0            | "
  console: 0x500   0xF   0x0            | "
  console: 0x500   0x10  0x0            \ "
  console: 0x500   0x11  0x0             Disabl3 ARM JTAG debug
  console: 0x500   0x12  0x0            /Reserved
  console: 0x500   0x13  0x0            | "
  console: 0x500   0x14  0x0            | "
  console: 0x500   0x15  0x0            | "
  console: 0x500   0x16  0x0            | "
  console: 0x500   0x17  0x0            | "
  console: 0x500   0x18  0x0            | "
  console: 0x500   0x19  0x0            | "
  console: 0x500   0x1A  0x0            | "
  console: 0x500   0x1B  0x0            | "
  console: 0x500   0x1C  0x0            | "
  console: 0x500   0x1D  0x0            | "
  console: 0x500   0x1E  0x0            | "
  console: 0x500   0x1F  0x0            \ "
  console: 0x510   0x0   0x0            /Reserved
  console: 0x510   0x1   0x0            | "
  console: 0x510   0x2   0x0            | "
  console: 0x510   0x3   0x0            \ "
  console: 0x510   0x4   0x0             Disable debug interfaces
  console: 0x510   0x5   0x0            /Reserved
  console: 0x510   0x6   0x0            | "
  console: 0x510   0x7   0x0            \ "
  console: 0x510   0x8   0x0             Enable boot from Uart5 by Pin Strap
  console: 0x510   0x9   0x0            /Reserved
  console: 0x510   0xA   0x0            \ "
  console: 0x510   0xB   0x0             Enable boot SPI ABR
  console: 0x510   0xC   0x0             Boot SPI ABR Mode
  console: 0x510   0xD   0x0            /Boot SPI flash size
  console: 0x510   0xE   0x0            | "
  console: 0x510   0xF   0x0            \ "
  console: 0x510   0x10  0x0            /Reserved
  console: 0x510   0x11  0x0            | "
  console: 0x510   0x12  0x0            | "
  console: 0x510   0x13  0x0            | "
  console: 0x510   0x14  0x0            | "
  console: 0x510   0x15  0x0            \ "
  console: 0x510   0x16  0x0             Enable boot SPI auxiliary control pins
  console: 0x510   0x19  0x0            /Reserved
  console: 0x510   0x1A  0x0            | "
  console: 0x510   0x1B  0x0            | "
  console: 0x510   0x1C  0x0            | "
  console: 0x510   0x1D  0x0            | "
  console: 0x510   0x1E  0x0            | "
  console: 0x510   0x1F  0x0            \ "
  console: 0x510   0x1E  0x0             Enable dedicate GPIO strap pins
  console: 0x510   0x1F  0x0             Enable Secure Boot by Pin Strap
  console: uart:~$ hwinfo devid
  console: Length: 8
  console: ID: 0x0000018000000180
  console: uart:~$ crypto aes256_cbc_vault
  console: aes256_cbc vault key 1
  console: Was waiting for:
  console: 6b c1 be e2 2e 40 9f 96 e9 3d 7e 11 73 93 17 2a
  console: ae 2d 8a 57 1e 03 ac 9c 9e b7 6f ac 45 af 8e 51
  console: 30 c8 1c 46 a3 5c e4 11 e5 fb c1 19 1a 0a 52 ef
  console: f6 9f 24 45 df 4f 9b 17 ad 2b 41 7b e6 6c 37 10
  console: But got:
  console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  console: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  console: uart:~$ random get
  console: 0x862460d
  console: uart:~$ i2c scan I2C_0
  console: 0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
  console: 00:             -- -- -- -- -- -- -- -- -- -- -- --
  console: 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
  console: 70: -- -- -- -- -- -- -- --
  console: 1 devices found on I2C_0
  console: uart:~$ kernel uptime
  console: Uptime: 9897 ms
  console: uart:~$ kernel reboot warm
  console: *** Booting Zephyr OS build v00.01.07  ***
  PASS (1.08 s)

Ref: https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.07/Aspeed_Zephy_SDK_User_Guide_v00.01.07.pdf

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 41 ++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ class AST1030Machine(QemuSystemTest):
 
     timeout = 10
 
-    def test_ast1030_zephyros(self):
+    def test_ast1030_zephyros_1_04(self):
         """
         :avocado: tags=arch:arm
         :avocado: tags=machine:ast1030-evb
+        :avocado: tags=os:zephyr
         """
         tar_url = ('https://github.com/AspeedTech-BMC'
                    '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip')
@@ -XXX,XX +XXX,XX @@ def test_ast1030_zephyros(self):
         exec_command_and_wait_for_pattern(self, "help",
                                           "Available commands")
 
+    def test_ast1030_zephyros_1_07(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:ast1030-evb
+        :avocado: tags=os:zephyr
+        """
+        tar_url = ('https://github.com/AspeedTech-BMC'
+                   '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip')
+        tar_hash = '40ac87eabdcd3b3454ce5aad11fedc72a33ecda2'
+        tar_path = self.fetch_asset(tar_url, asset_hash=tar_hash)
+        archive.extract(tar_path, self.workdir)
+        kernel_file = self.workdir + "/ast1030-evb-demo/zephyr.bin"
+        self.vm.set_console()
+        self.vm.add_args('-kernel', kernel_file,
+                         '-nographic')
+        self.vm.launch()
+        wait_for_console_pattern(self, "Booting Zephyr OS")
+        for shell_cmd in [
+                'kernel stacks',
+                'otp info conf',
+                'otp info scu',
+                'hwinfo devid',
+                'crypto aes256_cbc_vault',
+                'random get',
+                'jtag JTAG1 sw_xfer high TMS',
+                'adc ADC0 resolution 12',
+                'adc ADC0 read 42',
+                'adc ADC1 read 69',
+                'i2c scan I2C_0',
+                'i3c attach I3C_0',
+                'hash test',
+                'kernel uptime',
+                'kernel reboot warm',
+                'kernel uptime',
+                'kernel reboot cold',
+                'kernel uptime',
+        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
+
 class AST2x00Machine(QemuSystemTest):
 
     timeout = 90
-- 
2.39.1

The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20231025

for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)

----------------------------------------------------------------
aspeed queue:

* Update of Andrew's email
* Split of AspeedSoCState per 2400/2600/10x0

----------------------------------------------------------------
Andrew Jeffery (1):
      MAINTAINERS: aspeed: Update Andrew's email address

Philippe Mathieu-Daudé (11):
      hw/arm/aspeed: Extract code common to all boards to a common file
      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState

MAINTAINERS                               |   2 +-
 include/hw/arm/aspeed_soc.h               |  35 +++++-
 hw/arm/aspeed.c                           | 101 +++++++--------
 hw/arm/aspeed_ast10x0.c                   |  53 ++++----
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
 hw/arm/aspeed_ast2600.c                   |  75 ++++++------
 hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
 hw/arm/fby35.c                            |  27 ++--
 hw/arm/meson.build                        |   3 +-
 9 files changed, 363 insertions(+), 284 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
 create mode 100644 hw/arm/aspeed_soc_common.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

aspeed_soc.c contains definitions specific to the AST2400
and AST2500 SoCs, but also some definitions for other AST
SoCs: move them to a common file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_soc.c        |  96 -------------------------------
 hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
 hw/arm/meson.build         |   1 +
 3 files changed, 115 insertions(+), 96 deletions(-)
 create mode 100644 hw/arm/aspeed_soc_common.c

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
 };
 
 type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
-    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    SerialMM *smm;
-
-    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-        smm = &s->uart[i];
-
-        /* Chardev property is set by the machine. */
-        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
-        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
-        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
-        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
-            return false;
-        }
-
-        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-    }
-
-    return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    int i = dev - ASPEED_DEV_UART1;
-
-    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
-    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    ram_addr_t ram_size, max_ram_size;
-
-    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-                                        &error_abort);
-    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-                                            &error_abort);
-
-    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-                       max_ram_size);
-    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
-    /*
-     * Add a memory region beyond the RAM region to let firmwares scan
-     * the address space with load/store and guess how much RAM the
-     * SoC has.
-     */
-    if (ram_size < max_ram_size) {
-        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
-        qdev_prop_set_string(dev, "name", "ram-empty");
-        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-            return false;
-        }
-
-        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-    }
-
-    memory_region_add_subregion(s->memory,
-                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-    return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
-    memory_region_add_subregion(s->memory, addr,
-                                sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-                                   const char *name, hwaddr addr, uint64_t size)
-{
-    qdev_prop_set_string(DEVICE(dev), "name", name);
-    qdev_prop_set_uint64(DEVICE(dev), "size", size);
-    sysbus_realize(dev, &error_abort);
-
-    memory_region_add_subregion_overlap(s->memory, addr,
-                                        sysbus_mmio_get_region(dev, 0), -1000);
-}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    SerialMM *smm;
+
+    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+        smm = &s->uart[i];
+
+        /* Chardev property is set by the machine. */
+        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+            return false;
+        }
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+    }
+
+    return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    int i = dev - ASPEED_DEV_UART1;
+
+    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    ram_addr_t ram_size, max_ram_size;
+
+    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+                                        &error_abort);
+    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+                                            &error_abort);
+
+    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+                       max_ram_size);
+    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+    /*
+     * Add a memory region beyond the RAM region to let firmwares scan
+     * the address space with load/store and guess how much RAM the
+     * SoC has.
+     */
+    if (ram_size < max_ram_size) {
+        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+        qdev_prop_set_string(dev, "name", "ram-empty");
+        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
+        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+            return false;
+        }
+
+        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+    }
+
+    memory_region_add_subregion(s->memory,
+                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+    return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+    memory_region_add_subregion(s->memory, addr,
+                                sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+                                   const char *name, hwaddr addr, uint64_t size)
+{
+    qdev_prop_set_string(DEVICE(dev), "name", name);
+    qdev_prop_set_uint64(DEVICE(dev), "size", size);
+    sysbus_realize(dev, &error_abort);
+
+    memory_region_add_subregion_overlap(s->memory, addr,
+                                        sysbus_mmio_get_region(dev, 0), -1000);
+}
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
   'aspeed.c',
+  'aspeed_soc_common.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'aspeed_eeprom.c',
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
 }
 
-static void aspeed_soc_init(Object *obj)
+static void aspeed_ast2400_soc_init(Object *obj)
 {
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2400_type_info = {
     .name           = "ast2400-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2400_class_init,
 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2500_type_info = {
     .name           = "ast2500-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2500_class_init,
 };
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Keep aspeed_soc_class_init() generic, set the realize handler
to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
 }
 
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
 {
     int i;
     AspeedSoCState *s = ASPEED_SOC(dev);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->realize = aspeed_soc_realize;
-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-    dc->user_creatable = false;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2400-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2500-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

We want to derivate the big AspeedSoCState object in some more
SoC-specific ones. Since the object size will vary, allocate it
dynamically.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
     MachineState parent_obj;
     /* Public */
 
-    AspeedSoCState soc;
+    AspeedSoCState *soc;
     MemoryRegion boot_rom;
     bool mmio_exec;
     uint32_t uart_chosen;
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                     uint64_t rom_size)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
                            &error_abort);
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 {
     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
-    AspeedSoCState *s = &bmc->soc;
+    AspeedSoCState *s = bmc->soc;
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     int i;
     NICInfo *nd = &nd_table[0];
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
-    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
 
     /*
      * This will error out if the RAM size is not supported by the
      * memory controller of the SoC.
      */
-    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                              &error_fatal);
 
     for (i = 0; i < sc->macs_num; i++) {
         if ((amc->macs_mask & (1 << i)) && nd->used) {
             qemu_check_nic_model(nd, TYPE_FTGMAC100);
-            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
             nd++;
         }
     }
 
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                             &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                             &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "dram",
+    object_property_set_link(OBJECT(bmc->soc), "dram",
                              OBJECT(machine->ram), &error_abort);
     if (machine->kernel_filename) {
         /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          * that runs to unlock the SCU. In this case set the default to
          * be unlocked as the kernel expects
          */
-        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                 ASPEED_SCU_PROT_KEY, &error_abort);
     }
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
     if (defaults_enabled()) {
-        aspeed_board_init_flashes(&bmc->soc.fmc,
+        aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs, 0);
-        aspeed_board_init_flashes(&bmc->soc.spi[0],
+        aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               1, amc->num_cs);
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
         amc->i2c_init(bmc);
     }
 
-    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
-        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                            drive_get(IF_SD, 0, i));
     }
 
-    if (bmc->soc.emmc.num_slots) {
-        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
-                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+    if (bmc->soc->emmc.num_slots) {
+        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
     }
 
     if (!bmc->mmio_exec) {
-        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
 
         if (fmc0) {
-            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
             aspeed_install_boot_rom(bmc, fmc0, rom_size);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
 
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /*
      * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 
 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 
 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
      * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* bus 2 : */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
     };
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
     DeviceState *dev;
     LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
 
     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 
 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[144] = {};
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[13] = {};
     for (int i = 0; i < 13; i++) {
         if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fby35_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[16];
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
 
 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 }
 
 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *therm_mux, *cpuvr_mux;
 
     /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 static void fby35_reset(MachineState *state, ShutdownCause reason)
 {
     AspeedMachineState *bmc = ASPEED_MACHINE(state);
-    AspeedGPIOState *gpio = &bmc->soc.gpio;
+    AspeedGPIOState *gpio = &bmc->soc->gpio;
 
     qemu_devices_reset(reason);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
     clock_set_hz(sysclk, SYSCLK_FRQ);
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&bmc->soc.fmc,
+    aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs,
                               0);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[0],
+    aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, amc->num_cs);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[1],
+    aspeed_board_init_flashes(&bmc->soc->spi[1],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, (amc->num_cs * 2));
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
 
 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* U10 24C08 connects to SDA/SCL Group 1 by default */
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed10x0SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
 struct AspeedSoCClass {
     DeviceClass parent_class;
 
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     sc->get_irq = aspeed_soc_ast1030_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast1030_type_info = {
-    .name          = "ast1030-a1",
-    .parent        = TYPE_ASPEED_SOC,
-    .instance_size = sizeof(AspeedSoCState),
-    .instance_init = aspeed_soc_ast1030_init,
-    .class_init    = aspeed_soc_ast1030_class_init,
-    .class_size    = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+    {
+        .name           = TYPE_ASPEED10X0_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed10x0SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast1030-a1",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1030_init,
+        .class_init     = aspeed_soc_ast1030_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2600SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2600_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2600_type_info = {
-    .name           = "ast2600-a3",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_size  = sizeof(AspeedSoCState),
-    .instance_init  = aspeed_soc_ast2600_init,
-    .class_init     = aspeed_soc_ast2600_class_init,
-    .class_size     = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+    {
+        .name           = TYPE_ASPEED2600_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed2600SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2600-a3",
+        .parent         = TYPE_ASPEED2600_SOC,
+        .instance_init  = aspeed_soc_ast2600_init,
+        .class_init     = aspeed_soc_ast2600_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++
 hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
 hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
 3 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2400SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
 }
-static Property aspeed_soc_properties[] = {
-    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(oc);
-
-    device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
-    .name           = TYPE_ASPEED_SOC,
-    .parent         = TYPE_DEVICE,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_size     = sizeof(AspeedSoCClass),
-    .class_init     = aspeed_soc_class_init,
-    .abstract       = true,
-};
 
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2400_type_info = {
-    .name           = "ast2400-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2400_class_init,
-};
-
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2500_type_info = {
-    .name           = "ast2500-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_type_info);
-    type_register_static(&aspeed_soc_ast2400_type_info);
-    type_register_static(&aspeed_soc_ast2500_type_info);
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+    {
+        .name           = TYPE_ASPEED2400_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_init  = aspeed_ast2400_soc_init,
+        .instance_size  = sizeof(Aspeed2400SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2400-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2400_class_init,
+    }, {
+        .name           = "ast2500-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2500_class_init,
+    },
 };
 
-type_init(aspeed_soc_register_types);
+DEFINE_TYPES(aspeed_soc_ast2400_types)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/qdev-properties.h"
 #include "hw/misc/unimp.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
     memory_region_add_subregion_overlap(s->memory, addr,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
+
+static Property aspeed_soc_properties[] = {
+    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+    {
+        .name           = TYPE_ASPEED_SOC,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(AspeedSoCState),
+        .class_size     = sizeof(AspeedSoCClass),
+        .class_init     = aspeed_soc_class_init,
+        .abstract       = true,
+    },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
 
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+    AspeedSoCState *s = ASPEED_SOC(dev);
+
+    if (!s->memory) {
+        error_setg(errp, "'memory' link is not set");
+        return;
+    }
+}
+
 static Property aspeed_soc_properties[] = {
     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                      MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    dc->realize = aspeed_soc_realize;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  5 ++---
 hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
 hw/arm/fby35.c              | 13 ++++++++-----
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
-    /*< private >*/
     DeviceState parent;
 
-    /*< public >*/
     ARMCPU cpu[ASPEED_CPUS_NUM];
     A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
+
+    ARMv7MState armv7m;
 };
 
 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast1030_init(Object *obj)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
         g_assert_not_reached();
     }
 
-    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
 
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
     AspeedSoCState *s = ASPEED_SOC(dev_soc);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                                   0x40000);
 
     /* AST1030 CPU Core */
-    armv7m = DEVICE(&s->armv7m);
+    armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
     qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
-    object_property_set_link(OBJECT(&s->armv7m), "memory",
+    object_property_set_link(OBJECT(&a->armv7m), "memory",
                              OBJECT(s->memory), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
     /* Internal SRAM */
     sram_name = g_strdup_printf("aspeed.sram.%d",
-                                CPU(s->armv7m.cpu)->cpu_index);
+                                CPU(a->armv7m.cpu)->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err != NULL) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST1030 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST1030 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     Clock *bic_sysclk;
 
     AspeedSoCState bmc;
-    AspeedSoCState bic;
+    Aspeed10x0SoCState bic;
 
     bool mmio_exec;
 };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
 
 static void fby35_bic_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
     clock_set_hz(s->bic_sysclk, 200000000ULL);
 
     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+    soc = ASPEED_SOC(&s->bic);
 
     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                              &error_abort);
-    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
     qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
-    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
-    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
 }
 
 static void fby35_init(MachineState *machine)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-A cluster is specific to the Aspeed 2600 series,
remove it from the common AspeedSoCState.

The ARM cores belong to the MP cluster, but the array
is currently used by TYPE_ASPEED2600_SOC. We'll clean
that soon, but for now keep it in Aspeed2600SoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  4 ++-
 hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
 hw/arm/fby35.c              | 14 ++++++-----
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     DeviceState parent;
 
     ARMCPU cpu[ASPEED_CPUS_NUM];
-    A15MPPrivState     a7mpcore;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
+
+    A15MPPrivState a7mpcore;
+    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 };
 
 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast2600_init(Object *obj)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                               "hw-prot-key");
 
-    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                             TYPE_A15MPCORE_PRIV);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     /* CPU */
     for (i = 0; i < sc->num_cpus; i++) {
         if (sc->num_cpus > 1) {
-            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                     ASPEED_A7MPCORE_ADDR, &error_abort);
         }
-        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                 aspeed_calc_affinity(i), &error_abort);
 
-        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                 &error_abort);
-        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
             return;
         }
     }
 
     /* A7MPCORE */
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                             &error_abort);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 
     for (i = 0; i < sc->num_cpus; i++) {
-        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
-        DeviceState  *d   = DEVICE(&s->cpu[i]);
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+        DeviceState  *d   = DEVICE(&a->cpu[i]);
 
         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
         sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
 
     /* SRAM */
-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST2600 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      * offset 0.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST2600 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     MemoryRegion bic_memory;
     Clock *bic_sysclk;
 
-    AspeedSoCState bmc;
+    Aspeed2600SoCState bmc;
     Aspeed10x0SoCState bic;
 
     bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
 
 static void fby35_bmc_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+    soc = ASPEED_SOC(&s->bmc);
 
     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                             &error_abort);
     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                             &error_abort);
-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
 
     /* Install first FMC flash content as a boot rom. */
     if (!s->mmio_exec) {
         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 
         if (mtd0) {
-            AspeedSoCState *bmc = &s->bmc;
-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+            uint64_t rom_size = memory_region_size(&soc->spi_boot);
 
             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                    rom_size, &error_abort);
-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                 &s->bmc_boot_rom, 1);
 
             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARM array and VIC peripheral are only used by the
2400 series, remove them from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h               |  5 +++--
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
 hw/arm/meson.build                        |  2 +-
 3 files changed, 19 insertions(+), 15 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)