Series comparison

-[PULL 00/32] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Third RISC-V PR for QEMU 8.0
+RISC-V PR for 9.1
-* Update disas for xnor/orn/andn and slli.uw
+* APLICs add child earlier than realize
-* Update opentitan IRQs
+* Fix exposure of Zkr
-* Fix rom code when Zicsr is disabled
+* Raise exceptions on wrs.nto
-* Update VS timer whenever htimedelta changes
+* Implement SBI debug console (DBCN) calls for KVM
-* A collection of fixes for virtulisation
+* Support 64-bit addresses for initrd
-* Set tval for triggered watchpoints
+* Change RISCV_EXCP_SEMIHOST exception number to 63
-* Cleanups for board and FDT creation
+* Tolerate KVM disable ext errors
-* Add support for the T-Head vendor extensions
+* Set tval in breakpoints
-* A fix for virtual instr exception
+* Add support for Zve32x extension
-* Fix ctzw behavior
+* Add support for Zve64x extension
-* Fix SBI getchar handler for KVM
+* Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alistair Francis (1):
+Alexei Filippov (1):
-      hw/riscv: boot: Don't use CSRs if they are disabled
+      target/riscv: do not set mtval2 for non guest-page faults
-Anup Patel (4):
+Alistair Francis (2):
-      target/riscv: Update VS timer whenever htimedelta changes
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
       target/riscv: Ensure opcode is saved for all relevant instructions
-Bin Meng (1):
+Andrew Jones (2):
-      hw/riscv: virt: Simplify virt_{get,set}_aclint()
+      target/riscv/kvm: Fix exposure of Zkr
       target/riscv: Raise exceptions on wrs.nto
-Christoph Müllner (14):
+Cheng Yang (1):
-      RISC-V: Adding XTheadCmo ISA extension
+      hw/riscv/boot.c: Support 64-bit address for initrd
-      RISC-V: Adding XTheadSync ISA extension
-      RISC-V: Adding XTheadBa ISA extension
+Christoph Müllner (1):
-      RISC-V: Adding XTheadBb ISA extension
+      riscv: thead: Add th.sxstatus CSR emulation
-      RISC-V: Adding XTheadBs ISA extension
-      RISC-V: Adding XTheadCondMov ISA extension
+Clément Léger (1):
-      RISC-V: Adding T-Head multiply-accumulate instructions
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
       RISC-V: Adding T-Head MemPair extension
       RISC-V: Adding T-Head MemIdx extension
       RISC-V: Adding T-Head FMemIdx extension
       RISC-V: Set minimum priv version for Zfh to 1.11
       RISC-V: Add initial support for T-Head C906
       RISC-V: Adding XTheadFmv ISA extension
       target/riscv: add a MAINTAINERS entry for XThead* extension support
 Daniel Henrique Barboza (6):
-      hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
-      hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
+      target/riscv/kvm: tolerate KVM disable ext errors
-      hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
+      target/riscv/debug: set tval=pc in breakpoint exceptions
-      hw/riscv/boot.c: calculate fdt size after fdt_pack()
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
-      hw/riscv: split fdt address calculation from fdt load
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
-      hw/riscv: change riscv_compute_fdt_addr() semantics
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-Deepak Gupta (1):
+Huang Tao (2):
-      target/riscv: fix for virtual instr exception
+      target/riscv: Fix the element agnostic function problem
       target/riscv: Implement dynamic establishment of custom decoder
-Philipp Tomsich (1):
+Jason Chien (3):
-      target/riscv: update disas.c for xnor/orn/andn and slli.uw
+      target/riscv: Add support for Zve32x extension
       target/riscv: Add support for Zve64x extension
       target/riscv: Relax vector register check in RISCV gdbstub
-Sergey Matyukevich (1):
+Max Chou (4):
-      target/riscv: set tval for triggered watchpoints
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
       target/riscv: rvv: Check single width operator for vector fp widen instructions
       target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
       target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-Vladimir Isaev (2):
+Rob Bradford (1):
-      target/riscv: fix ctzw behavior
+      target/riscv: Remove experimental prefix from "B" extension
       target/riscv: fix SBI getchar handler for KVM
-Wilfred Mallawa (1):
+Yangyu Chen (1):
-      include/hw/riscv/opentitan: update opentitan IRQs
+      target/riscv/cpu.c: fix Zvkb extension config
- MAINTAINERS                                 |    8 +
+Yong-Xuan Wang (1):
- include/hw/riscv/boot.h                     |    4 +-
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
- include/hw/riscv/opentitan.h                |   14 +-
- target/riscv/cpu.h                          |   12 +
+Yu-Ming Chang (1):
- target/riscv/cpu_vendorid.h                 |    6 +
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
- target/riscv/helper.h                       |    1 +
- target/riscv/xthead.decode                  |  185 +++++
+yang.zhang (1):
- disas/riscv.c                               |    8 +-
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
- hw/riscv/boot.c                             |   62 +-
- hw/riscv/microchip_pfsoc.c                  |    7 +-
+ MAINTAINERS                                    |   1 +
- hw/riscv/opentitan.c                        |   80 +-
+ target/riscv/cpu.h                             |  11 ++
- hw/riscv/sifive_u.c                         |    8 +-
+ target/riscv/cpu_bits.h                        |   2 +-
- hw/riscv/spike.c                            |   25 +-
+ target/riscv/cpu_cfg.h                         |   2 +
- hw/riscv/virt.c                             |  476 ++++++------
+ target/riscv/helper.h                          |   1 +
- target/riscv/cpu.c                          |   55 +-
+ target/riscv/sbi_ecall_interface.h             |  17 +++
- target/riscv/cpu_helper.c                   |    8 +-
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
- target/riscv/csr.c                          |   16 +
+ disas/riscv.c                                  |  65 +++++++++-
- target/riscv/debug.c                        |    1 -
+ hw/intc/riscv_aplic.c                          |   8 +-
- target/riscv/kvm.c                          |    5 +-
+ hw/riscv/boot.c                                |   4 +-
- target/riscv/op_helper.c                    |    6 +
+ target/riscv/cpu.c                             |  10 +-
- target/riscv/time_helper.c                  |   36 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
- target/riscv/translate.c                    |   32 +
+ target/riscv/csr.c                             |  71 +++++++++--
- target/riscv/insn_trans/trans_rva.c.inc     |   10 +-
+ target/riscv/debug.c                           |   3 +
- target/riscv/insn_trans/trans_rvb.c.inc     |    1 +
+ target/riscv/gdbstub.c                         |   8 +-
- target/riscv/insn_trans/trans_rvd.c.inc     |    2 +
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
- target/riscv/insn_trans/trans_rvf.c.inc     |    2 +
+ target/riscv/op_helper.c                       |  17 ++-
- target/riscv/insn_trans/trans_rvh.c.inc     |    3 +
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
- target/riscv/insn_trans/trans_rvi.c.inc     |    2 +
+ target/riscv/th_csr.c                          |  79 +++++++++++++
- target/riscv/insn_trans/trans_rvzfh.c.inc   |    2 +
+ target/riscv/translate.c                       |  31 +++--
- target/riscv/insn_trans/trans_svinval.c.inc |    3 +
+ target/riscv/vector_internals.c                |  22 ++++
- target/riscv/insn_trans/trans_xthead.c.inc  | 1094 +++++++++++++++++++++++++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
- target/riscv/meson.build                    |    1 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
-files changed, 1847 insertions(+), 328 deletions(-)
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
- create mode 100644 target/riscv/cpu_vendorid.h
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
- create mode 100644 target/riscv/xthead.decode
+ target/riscv/meson.build                       |   1 +
- create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc
+files changed, 596 insertions(+), 109 deletions(-)
  create mode 100644 target/riscv/th_csr.c

-[PULL 24/32] RISC-V: Adding T-Head FMemIdx extension
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-This patch adds support for the T-Head FMemIdx instructions.
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-The patch uses the T-Head specific decoder and translation.
+be initialized first.
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
-Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |   1 +
+ hw/intc/riscv_aplic.c | 8 ++++----
- target/riscv/xthead.decode                 |  10 ++
+file changed, 4 insertions(+), 4 deletions(-)
  target/riscv/cpu.c                         |   2 +
  target/riscv/translate.c                   |   3 +-
  target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++
 files changed, 123 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/hw/intc/riscv_aplic.c
-+++ b/target/riscv/cpu.h
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
-     bool ext_xtheadbs;
+     qdev_prop_set_bit(dev, "msimode", msimode);
-     bool ext_xtheadcmo;
+     qdev_prop_set_bit(dev, "mmode", mmode);
-     bool ext_xtheadcondmov;
-+    bool ext_xtheadfmemidx;
++    if (parent) {
-     bool ext_xtheadmac;
++        riscv_aplic_add_child(parent, dev);
      bool ext_xtheadmemidx;
      bool ext_xtheadmempair;
 diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/xthead.decode
 +++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@ th_l2cache_iall  0000000 10110 00000 000 00000 0001011
  th_mveqz         0100000 ..... .....  001 ..... 0001011 @r
  th_mvnez         0100001 ..... .....  001 ..... 0001011 @r
 +# XTheadFMemIdx
 +th_flrd          01100 .. ..... ..... 110 ..... 0001011 @th_memidx
 +th_flrw          01000 .. ..... ..... 110 ..... 0001011 @th_memidx
 +th_flurd         01110 .. ..... ..... 110 ..... 0001011 @th_memidx
 +th_flurw         01010 .. ..... ..... 110 ..... 0001011 @th_memidx
 +th_fsrd          01100 .. ..... ..... 111 ..... 0001011 @th_memidx
 +th_fsrw          01000 .. ..... ..... 111 ..... 0001011 @th_memidx
 +th_fsurd         01110 .. ..... ..... 111 ..... 0001011 @th_memidx
 +th_fsurw         01010 .. ..... ..... 111 ..... 0001011 @th_memidx
 +
  # XTheadMac
  th_mula          00100 00 ..... ..... 001 ..... 0001011 @r
  th_mulah         00101 00 ..... ..... 001 ..... 0001011 @r
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
      ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
 +    ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
      ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
      ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
      ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
 +    DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
      DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
      DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
      DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
  {
      return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
             ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
 -           ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
 +           ctx->cfg_ptr->ext_xtheadcondmov ||
 +           ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac ||
             ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
             ctx->cfg_ptr->ext_xtheadsync;
  }
 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_xthead.c.inc
 +++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADFMEMIDX(ctx) do {          \
 +    if (!ctx->cfg_ptr->ext_xtheadfmemidx) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADMAC(ctx) do {              \
      if (!ctx->cfg_ptr->ext_xtheadmac) {          \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
      return gen_th_condmove(ctx, a, TCG_COND_NE);
  }
 +/* XTheadFMem */
 +
 +/*
 + * Load 64-bit float from indexed address.
 + * If !zext_offs, then address is rs1 + (rs2 << imm2).
 + * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
 + */
 +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
 +                          bool zext_offs)
 +{
 +    TCGv_i64 rd = cpu_fpr[a->rd];
 +    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
 +
 +    tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
 +    if ((memop & MO_SIZE) == MO_32) {
 +        gen_nanbox_s(rd, rd);
 +    }
 +
-+    mark_fs_dirty(ctx);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-+    return true;
-+}
+     if (!is_kvm_aia(msimode)) {
-+
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-+/*
+     }
-+ * Store 64-bit float to indexed address.
-+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+-    if (parent) {
-+ * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+-        riscv_aplic_add_child(parent, dev);
-+ */
+-    }
-+static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+-
-+                           bool zext_offs)
+     if (!msimode) {
-+{
+         for (i = 0; i < num_harts; i++) {
-+    TCGv_i64 rd = cpu_fpr[a->rd];
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
 +    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
 +
 +    tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
 +
 +    return true;
 +}
 +
 +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +    return gen_fload_idx(ctx, a, MO_TEUQ, false);
 +}
 +
 +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVF);
 +    return gen_fload_idx(ctx, a, MO_TEUL, false);
 +}
 +
 +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +    return gen_fload_idx(ctx, a, MO_TEUQ, true);
 +}
 +
 +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVF);
 +    return gen_fload_idx(ctx, a, MO_TEUL, true);
 +}
 +
 +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +    return gen_fstore_idx(ctx, a, MO_TEUQ, false);
 +}
 +
 +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVF);
 +    return gen_fstore_idx(ctx, a, MO_TEUL, false);
 +}
 +
 +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +    return gen_fstore_idx(ctx, a, MO_TEUQ, true);
 +}
 +
 +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADFMEMIDX(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVF);
 +    return gen_fstore_idx(ctx, a, MO_TEUL, true);
 +}
 +
  /* XTheadMac */
  static bool gen_th_mac(DisasContext *ctx, arg_r *a,
 --
-.39.1
+.45.1

-[PULL 23/32] RISC-V: Adding T-Head MemIdx extension
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Andrew Jones <ajones@ventanamicro.com>
-This patch adds support for the T-Head MemIdx instructions.
+The Zkr extension may only be exposed to KVM guests if the VMM
-The patch uses the T-Head specific decoder and translation.
+implements the SEED CSR. Use the same implementation as TCG.
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Without this patch, running with a KVM which does not forward the
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+SEED CSR access to QEMU will result in an ILL exception being
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+injected into the guest (this results in Linux guests crashing on
-Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu>
+boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
 Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
 Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |   1 +
+ target/riscv/cpu.h         |  3 +++
- target/riscv/xthead.decode                 |  54 +++
+ target/riscv/csr.c         | 18 ++++++++++++++----
- target/riscv/cpu.c                         |   2 +
+ target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
- target/riscv/translate.c                   |  21 +-
+files changed, 42 insertions(+), 4 deletions(-)
  target/riscv/insn_trans/trans_xthead.c.inc | 387 +++++++++++++++++++++
 files changed, 464 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
-     bool ext_xtheadcmo;
-     bool ext_xtheadcondmov;
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
-     bool ext_xtheadmac;
-+    bool ext_xtheadmemidx;
++target_ulong riscv_new_csr_seed(target_ulong new_value,
-     bool ext_xtheadmempair;
++                                target_ulong write_mask);
-     bool ext_xtheadsync;
++
-     bool ext_XVentanaCondOps;
+ uint8_t satp_mode_max_from_map(uint32_t map);
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
+--- a/target/riscv/csr.c
-+++ b/target/riscv/xthead.decode
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
- %rd2       20:5
+ #endif
- %rs2       20:5
- %sh5       20:5
+ /* Crypto Extension */
-+%imm5      20:s5
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- %sh6       20:6
+-                               target_ulong *ret_value,
- %sh2       25:2
+-                               target_ulong new_value,
-+%imm2      25:2
+-                               target_ulong write_mask)
++target_ulong riscv_new_csr_seed(target_ulong new_value,
- # Argument sets
++                                target_ulong write_mask)
- &r         rd rs1 rs2                               !extern
+ {
-@@ -XXX,XX +XXX,XX @@
+     uint16_t random_v;
- &shift     shamt rs1 rd                             !extern
+     Error *random_e = NULL;
- &th_bfext  msb lsb rs1 rd
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- &th_pair   rd1 rs rd2 sh2
+         rval = random_v | SEED_OPST_ES16;
-+&th_memidx rd rs1 rs2 imm2
+     }
-+&th_meminc rd rs1 imm5 imm2
++    return rval;
  # Formats
  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
@@ -XXX,XX +XXX,XX @@
  @sh5        ....... ..... .....  ... ..... .......  &shift  shamt=%sh5      %rs1 %rd
  @sh6        ...... ...... .....  ... ..... .......  &shift shamt=%sh6 %rs1 %rd
  @th_pair    ..... .. ..... ..... ... ..... .......  &th_pair %rd1 %rs %rd2 %sh2
 +@th_memidx  ..... .. ..... ..... ... ..... .......  &th_memidx %rd %rs1 %rs2 %imm2
 +@th_meminc  ..... .. ..... ..... ... ..... .......  &th_meminc %rd %rs1 %imm5 %imm2
  # XTheadBa
  # Instead of defining a new encoding, we simply use the decoder to
@@ -XXX,XX +XXX,XX @@ th_muls          00100 01 ..... ..... 001 ..... 0001011 @r
  th_mulsh         00101 01 ..... ..... 001 ..... 0001011 @r
  th_mulsw         00100 11 ..... ..... 001 ..... 0001011 @r
 +# XTheadMemIdx
 +th_ldia          01111 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_ldib          01101 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lwia          01011 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lwib          01001 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lwuia         11011 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lwuib         11001 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lhia          00111 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lhib          00101 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lhuia         10111 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lhuib         10101 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lbia          00011 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lbib          00001 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lbuia         10011 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_lbuib         10001 .. ..... ..... 100 ..... 0001011 @th_meminc
 +th_sdia          01111 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_sdib          01101 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_swia          01011 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_swib          01001 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_shia          00111 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_shib          00101 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_sbia          00011 .. ..... ..... 101 ..... 0001011 @th_meminc
 +th_sbib          00001 .. ..... ..... 101 ..... 0001011 @th_meminc
 +
 +th_lrd           01100 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrw           01000 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrwu          11000 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrh           00100 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrhu          10100 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrb           00000 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lrbu          10000 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_srd           01100 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_srw           01000 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_srh           00100 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_srb           00000 .. ..... ..... 101 ..... 0001011 @th_memidx
 +
 +th_lurd          01110 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurw          01010 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurwu         11010 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurh          00110 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurhu         10110 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurb          00010 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_lurbu         10010 .. ..... ..... 100 ..... 0001011 @th_memidx
 +th_surd          01110 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_surw          01010 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_surh          00110 .. ..... ..... 101 ..... 0001011 @th_memidx
 +th_surb          00010 .. ..... ..... 101 ..... 0001011 @th_memidx
 +
  # XTheadMemPair
  th_ldd           11111 .. ..... ..... 100 ..... 0001011 @th_pair
  th_lwd           11100 .. ..... ..... 100 ..... 0001011 @th_pair
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
      ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
      ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
 +    ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
      ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
      ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
      DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
 +    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
      DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
      DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
      return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
             ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
             ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
 -           ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
 +           ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
 +           ctx->cfg_ptr->ext_xtheadsync;
  }
  #define MATERIALISE_EXT_PREDICATE(ext)  \
@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
      return addr;
  }
 +/* Compute a canonical address from a register plus reg offset. */
 +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
 +{
 +    TCGv addr = temp_new(ctx);
 +    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 +
 +    tcg_gen_add_tl(addr, src1, offs);
 +    if (ctx->pm_mask_enabled) {
 +        tcg_gen_andc_tl(addr, addr, pm_mask);
 +    } else if (get_xl(ctx) == MXL_RV32) {
 +        tcg_gen_ext32u_tl(addr, addr);
 +    }
 +    if (ctx->pm_base_enabled) {
 +        tcg_gen_or_tl(addr, addr, pm_base);
 +    }
 +    return addr;
 +}
 +
- #ifndef CONFIG_USER_ONLY
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- /* The states of mstatus_fs are:
++                               target_ulong *ret_value,
-  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
++                               target_ulong new_value,
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
++                               target_ulong write_mask)
 +{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_xthead.c.inc
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
-     }                                            \
+     return ret;
- } while (0)
+ }
-+#define REQUIRE_XTHEADMEMIDX(ctx) do {           \
++static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
-+    if (!ctx->cfg_ptr->ext_xtheadmemidx) {       \
++{
-+        return false;                            \
++    target_ulong csr_num = run->riscv_csr.csr_num;
-+    }                                            \
++    target_ulong new_value = run->riscv_csr.new_value;
-+} while (0)
++    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
- #define REQUIRE_XTHEADMEMPAIR(ctx) do {          \
++    switch (csr_num) {
-     if (!ctx->cfg_ptr->ext_xtheadmempair) {      \
++    case CSR_SEED:
-         return false;                            \
++        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
-@@ -XXX,XX +XXX,XX @@
++        break;
-     }                                            \
++    default:
- } while (0)
++        qemu_log_mask(LOG_UNIMP,
++                      "%s: un-handled CSR EXIT for CSR %lx\n",
-+/*
++                      __func__, csr_num);
-+ * Calculate and return the address for indexed mem operations:
++        ret = -1;
-+ * If !zext_offs, then the address is rs1 + (rs2 << imm2).
++        break;
 + * If  zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
 + */
 +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
 +                                   int imm2, bool zext_offs)
 +{
 +    TCGv src2 = get_gpr(ctx, rs2, EXT_NONE);
 +    TCGv offs = tcg_temp_new();
 +
 +    if (zext_offs) {
 +        tcg_gen_extract_tl(offs, src2, 0, 32);
 +        tcg_gen_shli_tl(offs, offs, imm2);
 +    } else {
 +        tcg_gen_shli_tl(offs, src2, imm2);
 +    }
 +
-+    TCGv addr = get_address_indexed(ctx, rs1, offs);
++    return ret;
 +
 +    tcg_temp_free(offs);
 +    return addr;
 +}
 +
- /* XTheadBa */
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+ {
- /*
+     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
-     return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
+     case KVM_EXIT_RISCV_SBI:
- }
+         ret = kvm_riscv_handle_sbi(cs, run);
+         break;
-+/* XTheadMemIdx */
++    case KVM_EXIT_RISCV_CSR:
-+
++        ret = kvm_riscv_handle_csr(cs, run);
-+/*
++        break;
-+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+     default:
-+ * If !preinc, then the load address is rs1.
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
-+ * If  preinc, then the load address is rs1 + (imm5) << imm2).
+                       __func__, run->exit_reason);
 + */
 +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
 +                         bool preinc)
 +{
 +    if (a->rs1 == a->rd) {
 +        return false;
 +    }
 +
 +    int imm = a->imm5 << a->imm2;
 +    TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
 +    TCGv rd = dest_gpr(ctx, a->rd);
 +    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +
 +    tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
 +    tcg_gen_addi_tl(rs1, rs1, imm);
 +    gen_set_gpr(ctx, a->rd, rd);
 +    gen_set_gpr(ctx, a->rs1, rs1);
 +
 +    tcg_temp_free(addr);
 +    return true;
 +}
 +
 +/*
 + * Store with memop to indexed address and add (imm5 << imm2) to rs1.
 + * If !preinc, then the store address is rs1.
 + * If  preinc, then the store address is rs1 + (imm5) << imm2).
 + */
 +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
 +                          bool preinc)
 +{
 +    int imm = a->imm5 << a->imm2;
 +    TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
 +    TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
 +    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
 +
 +    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
 +    tcg_gen_addi_tl(rs1, rs1, imm);
 +    gen_set_gpr(ctx, a->rs1, rs1);
 +
 +    tcg_temp_free(addr);
 +    return true;
 +}
 +
 +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_inc(ctx, a, MO_TESQ, false);
 +}
 +
 +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_inc(ctx, a, MO_TESQ, true);
 +}
 +
 +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TESL, false);
 +}
 +
 +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TESL, true);
 +}
 +
 +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_inc(ctx, a, MO_TEUL, false);
 +}
 +
 +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_inc(ctx, a, MO_TEUL, true);
 +}
 +
 +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TESW, false);
 +}
 +
 +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TESW, true);
 +}
 +
 +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TEUW, false);
 +}
 +
 +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_TEUW, true);
 +}
 +
 +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_SB, false);
 +}
 +
 +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_SB, true);
 +}
 +
 +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_UB, false);
 +}
 +
 +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_inc(ctx, a, MO_UB, true);
 +}
 +
 +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_store_inc(ctx, a, MO_TESQ, false);
 +}
 +
 +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_store_inc(ctx, a, MO_TESQ, true);
 +}
 +
 +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_TESL, false);
 +}
 +
 +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_TESL, true);
 +}
 +
 +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_TESW, false);
 +}
 +
 +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_TESW, true);
 +}
 +
 +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_SB, false);
 +}
 +
 +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_inc(ctx, a, MO_SB, true);
 +}
 +
 +/*
 + * Load with memop from indexed address.
 + * If !zext_offs, then address is rs1 + (rs2 << imm2).
 + * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
 + */
 +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
 +                         bool zext_offs)
 +{
 +    TCGv rd = dest_gpr(ctx, a->rd);
 +    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
 +
 +    tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
 +    gen_set_gpr(ctx, a->rd, rd);
 +
 +    return true;
 +}
 +
 +/*
 + * Store with memop to indexed address.
 + * If !zext_offs, then address is rs1 + (rs2 << imm2).
 + * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
 + */
 +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
 +                          bool zext_offs)
 +{
 +    TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
 +    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
 +
 +    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
 +
 +    return true;
 +}
 +
 +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_idx(ctx, a, MO_TESQ, false);
 +}
 +
 +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TESL, false);
 +}
 +
 +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_idx(ctx, a, MO_TEUL, false);
 +}
 +
 +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TESW, false);
 +}
 +
 +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TEUW, false);
 +}
 +
 +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_SB, false);
 +}
 +
 +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_UB, false);
 +}
 +
 +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_store_idx(ctx, a, MO_TESQ, false);
 +}
 +
 +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_TESL, false);
 +}
 +
 +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_TESW, false);
 +}
 +
 +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_SB, false);
 +}
 +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_idx(ctx, a, MO_TESQ, true);
 +}
 +
 +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TESL, true);
 +}
 +
 +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_load_idx(ctx, a, MO_TEUL, true);
 +}
 +
 +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TESW, true);
 +}
 +
 +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_TEUW, true);
 +}
 +
 +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_SB, true);
 +}
 +
 +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_load_idx(ctx, a, MO_UB, true);
 +}
 +
 +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_store_idx(ctx, a, MO_TESQ, true);
 +}
 +
 +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_TESL, true);
 +}
 +
 +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_TESW, true);
 +}
 +
 +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a)
 +{
 +    REQUIRE_XTHEADMEMIDX(ctx);
 +    return gen_store_idx(ctx, a, MO_SB, true);
 +}
 +
  /* XTheadMemPair */
  static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
 --
-.39.1
+.45.1

-[PULL 16/32] RISC-V: Adding XTheadSync ISA extension
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Andrew Jones <ajones@ventanamicro.com>
-This patch adds support for the XTheadSync ISA extension.
+Implementing wrs.nto to always just return is consistent with the
-The patch uses the T-Head specific decoder and translation.
+specification, as the instruction is permitted to terminate the
 stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-The implementation introduces a helper to execute synchronization tasks:
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
-helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/helper.h                       |  1 +
- target/riscv/helper.h                      |  1 +
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/xthead.decode                 |  9 +++
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
- target/riscv/cpu.c                         |  2 +
+files changed, 32 insertions(+), 9 deletions(-)
  target/riscv/op_helper.c                   |  6 ++
  target/riscv/translate.c                   |  2 +-
  target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++
 files changed, 105 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     /* Vendor-specific custom extensions */
-     bool ext_xtheadcmo;
-+    bool ext_xtheadsync;
-     bool ext_XVentanaCondOps;
-     uint8_t pmu_num;
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(sret, tl, env)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
  DEF_HELPER_1(sret, tl, env)
  DEF_HELPER_1(mret, tl, env)
  DEF_HELPER_1(wfi, void, env)
++DEF_HELPER_1(wrs_nto, void, env)
  DEF_HELPER_1(tlb_flush, void, env)
-+DEF_HELPER_1(tlb_flush_all, void, env)
+ DEF_HELPER_1(tlb_flush_all, void, env)
  /* Native Debug */
- DEF_HELPER_1(itrigger_match, void, env)
- #endif
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
-+++ b/target/riscv/xthead.decode
-@@ -XXX,XX +XXX,XX @@
- # Fields:
- %rs1       15:5
-+%rs2       20:5
- # Formats
- @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
-+@rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
- # XTheadCmo
- th_dcache_call   0000000 00001 00000 000 00000 0001011
-@@ -XXX,XX +XXX,XX @@ th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
- th_l2cache_call  0000000 10101 00000 000 00000 0001011
- th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
- th_l2cache_iall  0000000 10110 00000 000 00000 0001011
-+
-+# XTheadSync
-+th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
-+th_sync          0000000 11000 00000 000 00000 0001011
-+th_sync_i        0000000 11010 00000 000 00000 0001011
-+th_sync_is       0000000 11011 00000 000 00000 0001011
-+th_sync_s        0000000 11001 00000 000 00000 0001011
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
-     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
-     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
-+    ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
-     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
- };
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     /* Vendor-specific custom extensions */
-     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
-+    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
-     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
-     /* These are experimental so mark with 'x-' */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
      }
  }
-+void helper_tlb_flush_all(CPURISCVState *env)
++void helper_wrs_nto(CPURISCVState *env)
 +{
-+    CPUState *cs = env_cpu(env);
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
-+    tlb_flush_all_cpus_synced(cs);
++        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
- void helper_hyp_tlb_flush(CPURISCVState *env)
+ void helper_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
+@@ -XXX,XX +XXX,XX @@
+  * this program.  If not, see <http://www.gnu.org/licenses/>.
- static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
+  */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
--    return ctx->cfg_ptr->ext_xtheadcmo;
+     if (!ctx->cfg_ptr->ext_zawrs) {
-+    return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
+-#define GEN_TRANS_WRS(insn)                                     \
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
+-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-index XXXXXXX..XXXXXXX 100644
+-{                                                               \
---- a/target/riscv/insn_trans/trans_xthead.c.inc
+-    (void)a;                                                    \
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
+-    return trans_wrs(ctx);                                      \
-@@ -XXX,XX +XXX,XX @@
+-}
-     }                                            \
++static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
  } while (0)
 +#define REQUIRE_XTHEADSYNC(ctx) do {             \
 +    if (!ctx->cfg_ptr->ext_xtheadsync) {         \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  /* XTheadCmo */
  static inline int priv_level(DisasContext *ctx)
@@ -XXX,XX +XXX,XX @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
  NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
  NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
  NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +
 +/* XTheadSync */
 +
 +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
 +{
-+    (void) a;
++    if (!ctx->cfg_ptr->ext_zawrs) {
-+    REQUIRE_XTHEADSYNC(ctx);
++        return false;
-+
++    }
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
-+    REQUIRE_PRIV_MS(ctx);
++    gen_helper_wrs_nto(tcg_env);
 +    gen_helper_tlb_flush_all(cpu_env);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +#ifndef CONFIG_USER_ONLY
 +static void gen_th_sync_local(DisasContext *ctx)
 +{
 +    /*
 +     * Emulate out-of-order barriers with pipeline flush
 +     * by exiting the translation block.
 +     */
 +    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
 +    tcg_gen_exit_tb(NULL, 0);
 +    ctx->base.is_jmp = DISAS_NORETURN;
 +}
 +#endif
 +
-+static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a)
++    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
-+{
++    return trans_wrs_sto(ctx, NULL);
 +    (void) a;
 +    REQUIRE_XTHEADSYNC(ctx);
 +
 +#ifndef CONFIG_USER_ONLY
 +    REQUIRE_PRIV_MSU(ctx);
 +
 +    /*
 +     * th.sync is an out-of-order barrier.
 +     */
 +    gen_th_sync_local(ctx);
 +
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a)
 +{
 +    (void) a;
 +    REQUIRE_XTHEADSYNC(ctx);
 +
 +#ifndef CONFIG_USER_ONLY
 +    REQUIRE_PRIV_MSU(ctx);
 +
 +    /*
 +     * th.sync.i is th.sync plus pipeline flush.
 +     */
 +    gen_th_sync_local(ctx);
 +
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a)
 +{
 +    /* This instruction has the same behaviour like th.sync.i. */
 +    return trans_th_sync_i(ctx, a);
 +}
 +
 +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a)
 +{
 +    /* This instruction has the same behaviour like th.sync. */
 +    return trans_th_sync(ctx, a);
 +}
 --
-.39.1
+.45.1

-[PULL 20/32] RISC-V: Adding XTheadCondMov ISA extension
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This patch adds support for the XTheadCondMov ISA extension.
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-The patch uses the T-Head specific decoder and translation.
+the legacy console putchar and getchar SBI extensions.
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+The appeal of the DBCN extension is that it allows multiple bytes to be
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+read/written in the SBI console in a single SBI call.
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
 module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/xthead.decode                 |  4 +++
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
- target/riscv/cpu.c                         |  2 ++
+files changed, 128 insertions(+)
- target/riscv/translate.c                   |  2 +-
- target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 files changed, 43 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@
-     bool ext_xtheadbb;
-     bool ext_xtheadbs;
+ /* clang-format off */
-     bool ext_xtheadcmo;
-+    bool ext_xtheadcondmov;
++#define SBI_SUCCESS                      0
-     bool ext_xtheadsync;
++#define SBI_ERR_FAILED                  -1
-     bool ext_XVentanaCondOps;
++#define SBI_ERR_NOT_SUPPORTED           -2
++#define SBI_ERR_INVALID_PARAM           -3
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
++#define SBI_ERR_DENIED                  -4
 +#define SBI_ERR_INVALID_ADDRESS         -5
 +#define SBI_ERR_ALREADY_AVAILABLE       -6
 +#define SBI_ERR_ALREADY_STARTED         -7
 +#define SBI_ERR_ALREADY_STOPPED         -8
 +#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/xthead.decode
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ th_l2cache_call  0000000 10101 00000 000 00000 0001011
+@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
- th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
+                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  th_l2cache_iall  0000000 10110 00000 000 00000 0001011
 +# XTheadCondMov
 +th_mveqz         0100000 ..... .....  001 ..... 0001011 @r
 +th_mvnez         0100001 ..... .....  001 ..... 0001011 @r
 +
  # XTheadSync
  th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
  th_sync          0000000 11000 00000 000 00000 0001011
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
      ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
 +    ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
      ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
  };
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
++static KVMCPUConfig kvm_sbi_dbcn = {
-     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
++    .name = "sbi_dbcn",
-     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
++    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
-+    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
++                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
-     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
++};
-     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
++
+ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+ {
-index XXXXXXX..XXXXXXX 100644
+     CPURISCVState *env = &cpu->env;
---- a/target/riscv/translate.c
+@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
-+++ b/target/riscv/translate.c
+     return 0;
-@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
+ }
- {
-     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
++static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
-            ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
++                                             KVMScratchCPU *kvmcpu,
--           ctx->cfg_ptr->ext_xtheadsync;
++                                             struct kvm_reg_list *reglist)
 +           ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync;
  }
  #define MATERIALISE_EXT_PREDICATE(ext)  \
 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_xthead.c.inc
 +++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADCONDMOV(ctx) do {          \
 +    if (!ctx->cfg_ptr->ext_xtheadcondmov) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADSYNC(ctx) do {             \
      if (!ctx->cfg_ptr->ext_xtheadsync) {         \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
  NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
  NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +/* XTheadCondMov */
 +
 +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
 +{
-+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
++    struct kvm_reg_list *reg_search;
-+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
++
-+    TCGv old = get_gpr(ctx, a->rd, EXT_NONE);
++    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
-+    TCGv dest = dest_gpr(ctx, a->rd);
++                         sizeof(uint64_t), uint64_cmp);
 +
-+    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old);
++    if (reg_search) {
-+
++        kvm_sbi_dbcn.supported = true;
-+    gen_set_gpr(ctx, a->rd, dest);
++    }
 +    return true;
 +}
 +
-+/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
-+static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
+                                  struct kvm_reg_list *reglist)
  {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
      if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
 +static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
 +{
-+    REQUIRE_XTHEADCONDMOV(ctx);
++    target_ulong reg = 1;
-+    return gen_th_condmove(ctx, a, TCG_COND_EQ);
++
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
-+/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
+ int kvm_arch_init_vcpu(CPUState *cs)
-+static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
+ {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
-+    REQUIRE_XTHEADCONDMOV(ctx);
++    g_autofree uint8_t *buf = NULL;
-+    return gen_th_condmove(ctx, a, TCG_COND_NE);
++    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
- /* XTheadSync */
+ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+ {
- static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
+     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP,
                        "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 --
-.39.1
+.45.1

-[PULL 12/32] hw/riscv/boot.c: calculate fdt size after fdt_pack()
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-fdt_pack() can change the fdt size, meaning that fdt_totalsize() can
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
-contain a now deprecated (bigger) value.
+to set the address of initrd in FDT to support 64-bit address.
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Message-Id: <20230201171212.1219375-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/boot.c | 10 ++++++----
+ hw/riscv/boot.c | 4 ++--
-file changed, 6 insertions(+), 4 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
- {
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-     uint64_t temp, fdt_addr;
+     if (fdt) {
-     hwaddr dram_end = dram_base + mem_size;
+         end = start + size;
--    int ret, fdtsize = fdt_totalsize(fdt);
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-+    int ret = fdt_pack(fdt);
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-+    int fdtsize;
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
-+    /* Should only fail if we've built a corrupted tree */
+     }
-+    g_assert(ret == 0);
+ }
 +
 +    fdtsize = fdt_totalsize(fdt);
      if (fdtsize <= 0) {
          error_report("invalid device-tree");
          exit(1);
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
      temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
      fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 -    ret = fdt_pack(fdt);
 -    /* Should only fail if we've built a corrupted tree */
 -    g_assert(ret == 0);
      /* copy in the device tree */
      qemu_fdt_dumpdtb(fdt, fdtsize);
 --
-.39.1
+.45.1

-[PULL 31/32] target/riscv: fix SBI getchar handler for KVM
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Vladimir Isaev <vladimir.isaev@syntacore.com>
+From: Clément Léger <cleger@rivosinc.com>
-Character must be returned via ret[0] field (copied to a0 by KVM).
+The current semihost exception number (16) is a reserved number (range
 [16-17]). The upcoming double trap specification uses that number for
 the double trap exception. Since the privileged spec (Table 22) defines
 ranges for custom uses change the semihosting exception number to 63
 which belongs to the range [48-63] in order to avoid any future
 collisions with reserved exception.
-Return value should be set to 0 to indicate successful processing.
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
-Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230203135155.12449-1-vladimir.isaev@syntacore.com>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/kvm.c | 5 +++--
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/kvm.c
+--- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/kvm.c
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
-     case SBI_EXT_0_1_CONSOLE_GETCHAR:
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
-         ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-         if (ret == sizeof(ch)) {
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--            run->riscv_sbi.args[0] = ch;
+-    RISCV_EXCP_SEMIHOST = 0x10,
-+            run->riscv_sbi.ret[0] = ch;
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
-         } else {
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
--            run->riscv_sbi.args[0] = -1;
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
-+            run->riscv_sbi.ret[0] = -1;
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
-         }
++    RISCV_EXCP_SEMIHOST = 0x3f,
-+        ret = 0;
+ } RISCVException;
-         break;
-     default:
+ #define RISCV_EXCP_INT_FLAG                0x80000000
          qemu_log_mask(LOG_UNIMP,
 --
-.39.1
+.45.1

-[PULL 09/32] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We have a convention in other QEMU boards/archs to name MachineState
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-pointers as either 'machine' or 'ms'. MachineClass pointers are usually
+enabled, will fail with a kernel oops SIGILL right at the start. The
-called 'mc'.
+reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
-The 'virt' RISC-V machine has a lot of instances where MachineState
+In hindsight this is too strict. If we keep proceeding, despite not
-pointers are named 'mc'. There is nothing wrong with that, but we gain
+disabling the extension in the KVM vcpu, we'll not add the extension in
-more compatibility with the rest of the QEMU code base, and easier
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
-reviews, if we follow QEMU conventions.
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
 it's ok to keep booting in this case.
-Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious
+Change our current logic to not error out if we fail to disable an
-and mechanical patch that was produced by doing the following:
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
 is important to throw a warning because we must make the user aware that
 the extension is still available in the vcpu, meaning that an
 ill-behaved guest can ignore the riscv,isa settings and  use the
 extension.
-- find/replace all 'MachineState *mc' to 'MachineState *ms';
+The case we're handling happens with an EINVAL error code. If we fail to
-- find/replace all 'mc->fdt' to 'ms->fdt';
+disable the extension in KVM for any other reason, error out.
 - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus';
 - replace any remaining occurrences of 'mc' that the compiler complained
 about.
-Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+We'll also keep erroring out when we fail to enable an extension in KVM,
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+since adding the extension in riscv,isa at this point will cause a guest
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+malfunction because the extension isn't enabled in the vcpu.
 Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-Id: <20230124212234.412630-3-dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
-file changed, 217 insertions(+), 217 deletions(-)
+file changed, 8 insertions(+), 4 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
- {
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
-     int cpu;
+         ret = kvm_set_one_reg(cs, id, &reg);
-     uint32_t cpu_phandle;
+         if (ret != 0) {
--    MachineState *mc = MACHINE(s);
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+    MachineState *ms = MACHINE(s);
+-                         reg ? "enable" : "disable",
-     char *name, *cpu_name, *core_name, *intc_name;
+-                         multi_ext_cfg->name, ret);
-     bool is_32_bit = riscv_is_32bit(&s->soc[0]);
+-            exit(EXIT_FAILURE);
++            if (!reg && ret == -EINVAL) {
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
++                warn_report("KVM cannot disable extension %s",
++                            multi_ext_cfg->name);
-         cpu_name = g_strdup_printf("/cpus/cpu@%d",
++            } else {
-             s->soc[socket].hartid_base + cpu);
++                error_report("Unable to enable extension %s in KVM, error %d",
--        qemu_fdt_add_subnode(mc->fdt, cpu_name);
++                             multi_ext_cfg->name, ret);
-+        qemu_fdt_add_subnode(ms->fdt, cpu_name);
++                exit(EXIT_FAILURE);
-         if (riscv_feature(&s->soc[socket].harts[cpu].env,
++            }
                            RISCV_FEATURE_MMU)) {
 -            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
 +            qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                      (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
          } else {
 -            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
 +            qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                      "riscv,none");
          }
          name = riscv_isa_string(&s->soc[socket].harts[cpu]);
 -        qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
 +        qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
          g_free(name);
 -        qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
 -        qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
 -        qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
 +        qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
 +        qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
 +        qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
              s->soc[socket].hartid_base + cpu);
 -        qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
 -        riscv_socket_fdt_write_id(mc, cpu_name, socket);
 -        qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
 +        qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
 +        riscv_socket_fdt_write_id(ms, cpu_name, socket);
 +        qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
          intc_phandles[cpu] = (*phandle)++;
          intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
 -        qemu_fdt_add_subnode(mc->fdt, intc_name);
 -        qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
 +        qemu_fdt_add_subnode(ms->fdt, intc_name);
 +        qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
              intc_phandles[cpu]);
 -        qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
 +        qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
              "riscv,cpu-intc");
 -        qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
 -        qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
 +        qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
 +        qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
          core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
 -        qemu_fdt_add_subnode(mc->fdt, core_name);
 -        qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
 +        qemu_fdt_add_subnode(ms->fdt, core_name);
 +        qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
          g_free(core_name);
          g_free(intc_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_memory(RISCVVirtState *s,
  {
      char *mem_name;
      uint64_t addr, size;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
 -    addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
 -    size = riscv_socket_mem_size(mc, socket);
 +    addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
 +    size = riscv_socket_mem_size(ms, socket);
      mem_name = g_strdup_printf("/memory@%lx", (long)addr);
 -    qemu_fdt_add_subnode(mc->fdt, mem_name);
 -    qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
 +    qemu_fdt_add_subnode(ms->fdt, mem_name);
 +    qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
          addr >> 32, addr, size >> 32, size);
 -    qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
 -    riscv_socket_fdt_write_id(mc, mem_name, socket);
 +    qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
 +    riscv_socket_fdt_write_id(ms, mem_name, socket);
      g_free(mem_name);
  }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
      char *clint_name;
      uint32_t *clint_cells;
      unsigned long clint_addr;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      static const char * const clint_compat[2] = {
          "sifive,clint0", "riscv,clint0"
      };
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
      clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
      clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
 -    qemu_fdt_add_subnode(mc->fdt, clint_name);
 -    qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
 +    qemu_fdt_add_subnode(ms->fdt, clint_name);
 +    qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
                                    (char **)&clint_compat,
                                    ARRAY_SIZE(clint_compat));
 -    qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
 +    qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
 x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
 -    qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
 +    qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
          clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 -    riscv_socket_fdt_write_id(mc, clint_name, socket);
 +    riscv_socket_fdt_write_id(ms, clint_name, socket);
      g_free(clint_name);
      g_free(clint_cells);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
      uint32_t *aclint_mswi_cells;
      uint32_t *aclint_sswi_cells;
      uint32_t *aclint_mtimer_cells;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
      aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
      if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
          addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
          name = g_strdup_printf("/soc/mswi@%lx", addr);
 -        qemu_fdt_add_subnode(mc->fdt, name);
 -        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
 +        qemu_fdt_add_subnode(ms->fdt, name);
 +        qemu_fdt_setprop_string(ms->fdt, name, "compatible",
              "riscv,aclint-mswi");
 -        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
 +        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
 x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
 -        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
 +        qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
              aclint_mswi_cells, aclint_cells_size);
 -        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
 -        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
 -        riscv_socket_fdt_write_id(mc, name, socket);
 +        qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
 +        qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
 +        riscv_socket_fdt_write_id(ms, name, socket);
          g_free(name);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
          size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
      }
      name = g_strdup_printf("/soc/mtimer@%lx", addr);
 -    qemu_fdt_add_subnode(mc->fdt, name);
 -    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
 +    qemu_fdt_add_subnode(ms->fdt, name);
 +    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
          "riscv,aclint-mtimer");
 -    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
 +    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
 x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
 x0, size - RISCV_ACLINT_DEFAULT_MTIME,
 x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
 x0, RISCV_ACLINT_DEFAULT_MTIME);
 -    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
 +    qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
          aclint_mtimer_cells, aclint_cells_size);
 -    riscv_socket_fdt_write_id(mc, name, socket);
 +    riscv_socket_fdt_write_id(ms, name, socket);
      g_free(name);
      if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
          addr = memmap[VIRT_ACLINT_SSWI].base +
              (memmap[VIRT_ACLINT_SSWI].size * socket);
          name = g_strdup_printf("/soc/sswi@%lx", addr);
 -        qemu_fdt_add_subnode(mc->fdt, name);
 -        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
 +        qemu_fdt_add_subnode(ms->fdt, name);
 +        qemu_fdt_setprop_string(ms->fdt, name, "compatible",
              "riscv,aclint-sswi");
 -        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
 +        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
 x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
 -        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
 +        qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
              aclint_sswi_cells, aclint_cells_size);
 -        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
 -        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
 -        riscv_socket_fdt_write_id(mc, name, socket);
 +        qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
 +        qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
 +        riscv_socket_fdt_write_id(ms, name, socket);
          g_free(name);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
      char *plic_name;
      uint32_t *plic_cells;
      unsigned long plic_addr;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      static const char * const plic_compat[2] = {
          "sifive,plic-1.0.0", "riscv,plic0"
      };
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
      plic_phandles[socket] = (*phandle)++;
      plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
      plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
 -    qemu_fdt_add_subnode(mc->fdt, plic_name);
 -    qemu_fdt_setprop_cell(mc->fdt, plic_name,
 +    qemu_fdt_add_subnode(ms->fdt, plic_name);
 +    qemu_fdt_setprop_cell(ms->fdt, plic_name,
          "#interrupt-cells", FDT_PLIC_INT_CELLS);
 -    qemu_fdt_setprop_cell(mc->fdt, plic_name,
 +    qemu_fdt_setprop_cell(ms->fdt, plic_name,
          "#address-cells", FDT_PLIC_ADDR_CELLS);
 -    qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
 +    qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
                                    (char **)&plic_compat,
                                    ARRAY_SIZE(plic_compat));
 -    qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
 -    qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
 +    qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
          plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 -    qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
 +    qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
 x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
 -    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
 +    qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
                            VIRT_IRQCHIP_NUM_SOURCES - 1);
 -    riscv_socket_fdt_write_id(mc, plic_name, socket);
 -    qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
 +    riscv_socket_fdt_write_id(ms, plic_name, socket);
 +    qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
          plic_phandles[socket]);
      if (!socket) {
 -        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
 +        platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
                                         memmap[VIRT_PLATFORM_BUS].base,
                                         memmap[VIRT_PLATFORM_BUS].size,
                                         VIRT_PLATFORM_BUS_IRQ);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
  {
      int cpu, socket;
      char *imsic_name;
 -    MachineState *mc = MACHINE(s);
 -    int socket_count = riscv_socket_count(mc);
 +    MachineState *ms = MACHINE(s);
 +    int socket_count = riscv_socket_count(ms);
      uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
      uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
      *msi_m_phandle = (*phandle)++;
      *msi_s_phandle = (*phandle)++;
 -    imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
 +    imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
      imsic_regs = g_new0(uint32_t, socket_count * 4);
      /* M-level IMSIC node */
 -    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
 +    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
          imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
          imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
      }
      imsic_name = g_strdup_printf("/soc/imsics@%lx",
          (unsigned long)memmap[VIRT_IMSIC_M].base);
 -    qemu_fdt_add_subnode(mc->fdt, imsic_name);
 -    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
 +    qemu_fdt_add_subnode(ms->fdt, imsic_name);
 +    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
          "riscv,imsics");
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
          FDT_IMSIC_INT_CELLS);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
          NULL, 0);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
          NULL, 0);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
 -        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
 +        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
          socket_count * sizeof(uint32_t) * 4);
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
          VIRT_IRQCHIP_NUM_MSIS);
      if (socket_count > 1) {
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
              imsic_num_bits(imsic_max_hart_per_socket));
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
              imsic_num_bits(socket_count));
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
              IMSIC_MMIO_GROUP_MIN_SHIFT);
      }
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
      g_free(imsic_name);
      /* S-level IMSIC node */
 -    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
 +    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
          imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
          imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
      }
      imsic_name = g_strdup_printf("/soc/imsics@%lx",
          (unsigned long)memmap[VIRT_IMSIC_S].base);
 -    qemu_fdt_add_subnode(mc->fdt, imsic_name);
 -    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
 +    qemu_fdt_add_subnode(ms->fdt, imsic_name);
 +    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
          "riscv,imsics");
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
          FDT_IMSIC_INT_CELLS);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
          NULL, 0);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
          NULL, 0);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
 -        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
 -    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
 +        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
 +    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
          socket_count * sizeof(uint32_t) * 4);
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
          VIRT_IRQCHIP_NUM_MSIS);
      if (imsic_guest_bits) {
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
              imsic_guest_bits);
      }
      if (socket_count > 1) {
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
              imsic_num_bits(imsic_max_hart_per_socket));
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
              imsic_num_bits(socket_count));
 -        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
 +        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
              IMSIC_MMIO_GROUP_MIN_SHIFT);
      }
 -    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
 +    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
      g_free(imsic_name);
      g_free(imsic_regs);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
      char *aplic_name;
      uint32_t *aplic_cells;
      unsigned long aplic_addr;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      uint32_t aplic_m_phandle, aplic_s_phandle;
      aplic_m_phandle = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
      aplic_addr = memmap[VIRT_APLIC_M].base +
                   (memmap[VIRT_APLIC_M].size * socket);
      aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
 -    qemu_fdt_add_subnode(mc->fdt, aplic_name);
 -    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
 +    qemu_fdt_add_subnode(ms->fdt, aplic_name);
 +    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
          "#interrupt-cells", FDT_APLIC_INT_CELLS);
 -    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
      if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
 -        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
 +        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
              aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
      } else {
 -        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
 +        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
              msi_m_phandle);
      }
 -    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
 +    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
 x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
          VIRT_IRQCHIP_NUM_SOURCES);
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
          aplic_s_phandle);
 -    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
 +    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
          aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
 -    riscv_socket_fdt_write_id(mc, aplic_name, socket);
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
 +    riscv_socket_fdt_write_id(ms, aplic_name, socket);
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
      g_free(aplic_name);
      /* S-level APLIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
      aplic_addr = memmap[VIRT_APLIC_S].base +
                   (memmap[VIRT_APLIC_S].size * socket);
      aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
 -    qemu_fdt_add_subnode(mc->fdt, aplic_name);
 -    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
 +    qemu_fdt_add_subnode(ms->fdt, aplic_name);
 +    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
          "#interrupt-cells", FDT_APLIC_INT_CELLS);
 -    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
 +    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
      if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
 -        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
 +        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
              aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
      } else {
 -        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
 +        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
              msi_s_phandle);
      }
 -    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
 +    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
 x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
          VIRT_IRQCHIP_NUM_SOURCES);
 -    riscv_socket_fdt_write_id(mc, aplic_name, socket);
 -    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 +    riscv_socket_fdt_write_id(ms, aplic_name, socket);
 +    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
      if (!socket) {
 -        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
 +        platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
                                         memmap[VIRT_PLATFORM_BUS].base,
                                         memmap[VIRT_PLATFORM_BUS].size,
                                         VIRT_PLATFORM_BUS_IRQ);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
  static void create_fdt_pmu(RISCVVirtState *s)
  {
      char *pmu_name;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      RISCVCPU hart = s->soc[0].harts[0];
      pmu_name = g_strdup_printf("/soc/pmu");
 -    qemu_fdt_add_subnode(mc->fdt, pmu_name);
 -    qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
 -    riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
 +    qemu_fdt_add_subnode(ms->fdt, pmu_name);
 +    qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
 +    riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
      g_free(pmu_name);
  }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
  {
      char *clust_name;
      int socket, phandle_pos;
 -    MachineState *mc = MACHINE(s);
 +    MachineState *ms = MACHINE(s);
      uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
      uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
 -    int socket_count = riscv_socket_count(mc);
 +    int socket_count = riscv_socket_count(ms);
 -    qemu_fdt_add_subnode(mc->fdt, "/cpus");
 -    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
 +    qemu_fdt_add_subnode(ms->fdt, "/cpus");
 +    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
                            RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
 -    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
 -    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
 -    qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
 +    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
 +    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
 +    qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
 -    intc_phandles = g_new0(uint32_t, mc->smp.cpus);
 +    intc_phandles = g_new0(uint32_t, ms->smp.cpus);
 -    phandle_pos = mc->smp.cpus;
 +    phandle_pos = ms->smp.cpus;
      for (socket = (socket_count - 1); socket >= 0; socket--) {
          phandle_pos -= s->soc[socket].num_harts;
          clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
 -        qemu_fdt_add_subnode(mc->fdt, clust_name);
 +        qemu_fdt_add_subnode(ms->fdt, clust_name);
          create_fdt_socket_cpus(s, socket, clust_name, phandle,
                                 &intc_phandles[phandle_pos]);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          *msi_pcie_phandle = msi_s_phandle;
      }
 -    phandle_pos = mc->smp.cpus;
 +    phandle_pos = ms->smp.cpus;
      for (socket = (socket_count - 1); socket >= 0; socket--) {
          phandle_pos -= s->soc[socket].num_harts;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          }
      }
--    riscv_socket_fdt_write_distance_matrix(mc);
-+    riscv_socket_fdt_write_distance_matrix(ms);
- }
- static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
- {
-     int i;
-     char *name;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     for (i = 0; i < VIRTIO_COUNT; i++) {
-         name = g_strdup_printf("/soc/virtio_mmio@%lx",
-             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
--        qemu_fdt_add_subnode(mc->fdt, name);
--        qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
--        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-+        qemu_fdt_add_subnode(ms->fdt, name);
-+        qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
-+        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
-x0, memmap[VIRT_VIRTIO].size);
--        qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
-+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
-             irq_virtio_phandle);
-         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
--            qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
-+            qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
-                                   VIRTIO_IRQ + i);
-         } else {
--            qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
-+            qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
-                                    VIRTIO_IRQ + i, 0x4);
-         }
-         g_free(name);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
-                             uint32_t msi_pcie_phandle)
- {
-     char *name;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     name = g_strdup_printf("/soc/pci@%lx",
-         (long) memmap[VIRT_PCIE_ECAM].base);
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
-         FDT_PCI_ADDR_CELLS);
--    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
-+    qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
-         FDT_PCI_INT_CELLS);
--    qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
-+    qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
-         "pci-host-ecam-generic");
--    qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
--    qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
--    qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
-+    qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
-+    qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
-+    qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
-         memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
--    qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
-+    qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
-     if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
--        qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
-+        qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
-     }
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
-+    qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
-         memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
--    qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
-+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
-, FDT_PCI_RANGE_IOPORT, 2, 0,
-, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
-, FDT_PCI_RANGE_MMIO,
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
-, virt_high_pcie_memmap.base,
-, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
--    create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
-+    create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
-     g_free(name);
- }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
- {
-     char *name;
-     uint32_t test_phandle;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     test_phandle = (*phandle)++;
-     name = g_strdup_printf("/soc/test@%lx",
-         (long)memmap[VIRT_TEST].base);
--    qemu_fdt_add_subnode(mc->fdt, name);
-+    qemu_fdt_add_subnode(ms->fdt, name);
-     {
-         static const char * const compat[3] = {
-             "sifive,test1", "sifive,test0", "syscon"
-         };
--        qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
-+        qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
-                                       (char **)&compat, ARRAY_SIZE(compat));
-     }
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
--    qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
--    test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
-+    test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
-     g_free(name);
-     name = g_strdup_printf("/reboot");
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
--    qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
--    qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
--    qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
-+    qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
-     g_free(name);
-     name = g_strdup_printf("/poweroff");
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
--    qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
--    qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
--    qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
-+    qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
-     g_free(name);
- }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
-                             uint32_t irq_mmio_phandle)
- {
-     char *name;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
-+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-x0, memmap[VIRT_UART0].base,
-x0, memmap[VIRT_UART0].size);
--    qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
--    qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
-     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
--        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
-+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
-     } else {
--        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
-+        qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
-     }
--    qemu_fdt_add_subnode(mc->fdt, "/chosen");
--    qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
-+    qemu_fdt_add_subnode(ms->fdt, "/chosen");
-+    qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
-     g_free(name);
- }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
-                            uint32_t irq_mmio_phandle)
- {
-     char *name;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
-         "google,goldfish-rtc");
--    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
-+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
-x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
--    qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
-+    qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
-         irq_mmio_phandle);
-     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
--        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
-+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
-     } else {
--        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
-+        qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
-     }
-     g_free(name);
- }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
- static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
- {
-     char *name;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
-     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
-     name = g_strdup_printf("/flash@%" PRIx64, flashbase);
--    qemu_fdt_add_subnode(mc->fdt, name);
--    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
--    qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
-+    qemu_fdt_add_subnode(ms->fdt, name);
-+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
-+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
-, flashbase, 2, flashsize,
-, flashbase + flashsize, 2, flashsize);
--    qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
-+    qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
-     g_free(name);
- }
- static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
- {
-     char *nodename;
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     hwaddr base = memmap[VIRT_FW_CFG].base;
-     hwaddr size = memmap[VIRT_FW_CFG].size;
-     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
--    qemu_fdt_add_subnode(mc->fdt, nodename);
--    qemu_fdt_setprop_string(mc->fdt, nodename,
-+    qemu_fdt_add_subnode(ms->fdt, nodename);
-+    qemu_fdt_setprop_string(ms->fdt, nodename,
-                             "compatible", "qemu,fw-cfg-mmio");
--    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
-+    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
-, base, 2, size);
--    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
-+    qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
-     g_free(nodename);
- }
- static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
- {
--    MachineState *mc = MACHINE(s);
-+    MachineState *ms = MACHINE(s);
-     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
-     uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
-     uint8_t rng_seed[32];
--    if (mc->dtb) {
--        mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
--        if (!mc->fdt) {
-+    if (ms->dtb) {
-+        ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
-+        if (!ms->fdt) {
-             error_report("load_device_tree() failed");
-             exit(1);
-         }
-     } else {
--        mc->fdt = create_device_tree(&s->fdt_size);
--        if (!mc->fdt) {
-+        ms->fdt = create_device_tree(&s->fdt_size);
-+        if (!ms->fdt) {
-             error_report("create_device_tree() failed");
-             exit(1);
-         }
-     }
--    qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
--    qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
--    qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
--    qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
-+    qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
-+    qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
-+    qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
-+    qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
--    qemu_fdt_add_subnode(mc->fdt, "/soc");
--    qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
--    qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
--    qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
--    qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
-+    qemu_fdt_add_subnode(ms->fdt, "/soc");
-+    qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
-+    qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
-+    qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
-+    qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
-     create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
-                        &irq_pcie_phandle, &irq_virtio_phandle,
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
-     /* Pass seed to RNG */
-     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
--    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed",
-+    qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
-                      rng_seed, sizeof(rng_seed));
- }
-@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
-     return dev;
- }
--static FWCfgState *create_fw_cfg(const MachineState *mc)
-+static FWCfgState *create_fw_cfg(const MachineState *ms)
- {
-     hwaddr base = virt_memmap[VIRT_FW_CFG].base;
-     FWCfgState *fw_cfg;
-     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
-                                   &address_space_memory);
--    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
-+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
-     return fw_cfg;
  }
 --
-.39.1
+.45.1

-[PULL 11/32] target/riscv: set tval for triggered watchpoints
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
-From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-According to privileged spec, if [sm]tval is written with a nonzero
+We're not setting (s/m)tval when triggering breakpoints of type 2
-value when a breakpoint exception occurs, then [sm]tval will contain
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
-the faulting virtual address. Set tval to hit address when breakpoint
+.7.12, "Match Control Type 6":
 exception is triggered by hardware watchpoint.
-Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
+"The Privileged Spec says that breakpoint exceptions that occur on
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 6 ++++++
+ target/riscv/cpu_helper.c | 1 +
- target/riscv/debug.c      | 1 -
+ target/riscv/debug.c      | 3 +++
-files changed, 6 insertions(+), 1 deletion(-)
+files changed, 4 insertions(+)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
 @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
-         case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
              tval = env->bins;
              break;
-+        case RISCV_EXCP_BREAKPOINT:
+         case RISCV_EXCP_BREAKPOINT:
-+            if (cs->watchpoint_hit) {
++            tval = env->badaddr;
-+                tval = cs->watchpoint_hit->hitaddr;
+             if (cs->watchpoint_hit) {
-+                cs->watchpoint_hit = NULL;
+                 tval = cs->watchpoint_hit->hitaddr;
-+            }
+                 cs->watchpoint_hit = NULL;
 +            break;
          default:
              break;
          }
 diff --git a/target/riscv/debug.c b/target/riscv/debug.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/debug.c
 +++ b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-     if (cs->watchpoint_hit) {
+                     /* check U/S/M bit against current privilege level */
-         if (cs->watchpoint_hit->flags & BP_CPU) {
+                     if ((ctrl >> 3) & BIT(env->priv)) {
--            cs->watchpoint_hit = NULL;
++                        env->badaddr = pc;
-             do_trigger_action(env, DBG_ACTION_BP);
+                         return true;
-         }
+                     }
-     } else {
+                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                      if (env->virt_enabled) {
                          /* check VU/VS bit against current privilege level */
                          if ((ctrl >> 23) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      } else {
                          /* check U/S/M bit against current privilege level */
                          if ((ctrl >> 3) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      }
 --
-.39.1
+.45.1

-[PULL 14/32] hw/riscv: change riscv_compute_fdt_addr() semantics
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
+Privileged spec section 4.1.9 mentions:
 mem_size (which is defaulted to MachineState::ram_size in all boards)
 and the FDT pointer. And it makes a very important assumption: the DRAM
 interval dram_base + mem_size is contiguous. This is indeed the case for
 most boards that use a FDT.
-The Icicle Kit board works with 2 distinct RAM banks that are separated
+"When a trap is taken into S-mode, stval is written with
-by a gap. We have a lower bank with 1GiB size, a gap follows, then at
+exception-specific information to assist software in handling the trap.
-GiB the high memory starts. MachineClass::default_ram_size for this
+(...)
 board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM
 size, meaning that there we'll always have at least 512 MiB in the Hi
 RAM area.
-Using riscv_compute_fdt_addr() in this board is weird because not only
+If stval is written with a nonzero value when a breakpoint,
-the board has sparse RAM, and it's calling it using the base address of
+address-misaligned, access-fault, or page-fault exception occurs on an
-the Lo RAM area, but it's also using a mem_size that we have guarantees
+instruction fetch, load, or store, then stval will contain the faulting
-that it will go up to the Hi RAM. All the function assumptions doesn't
+virtual address."
 work for this board.
-In fact, what makes the function works at all in this case is a
+A similar text is found for mtval in section 3.1.16.
 coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT,
 down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For
 the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000
 (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put
 the FDT under a 3Gb address, which happens to be exactly at the end of
 DRAM_LO. If the base address of the Lo area started later than 3Gb this
 function would be unusable by the board. Changing any assumptions inside
 riscv_compute_fdt_addr() can also break it by accident as well.
-Let's change riscv_compute_fdt_addr() semantics to be appropriate to the
+Setting mtval/stval in this scenario is optional, but some softwares read
-Icicle Kit board and for future boards that might have sparse RAM
+these regs when handling ebreaks.
 topologies to worry about:
-- relieve the condition that the dram_base + mem_size area is contiguous,
+Write 'badaddr' in all ebreak breakpoints to write the appropriate
-since this is already not the case today;
+'tval' during riscv_do_cpu_interrrupt().
 - receive an extra 'dram_size' size attribute that refers to a contiguous
 RAM block that the board wants the FDT to reside on.
 Together with 'mem_size' and 'fdt', which are now now being consumed by a
 MachineState pointer, we're able to make clear assumptions based on the
 DRAM block and total mem_size available to ensure that the FDT will be put
 in a valid RAM address.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230201171212.1219375-4-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h    |  2 +-
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
- hw/riscv/boot.c            | 35 +++++++++++++++++++++++------------
+file changed, 2 insertions(+)
  hw/riscv/microchip_pfsoc.c |  3 ++-
  hw/riscv/sifive_u.c        |  3 ++-
  hw/riscv/spike.c           |  3 ++-
  hw/riscv/virt.c            |  3 ++-
 files changed, 32 insertions(+), 17 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
-                                symbol_fn_t sym_cb);
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
- void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
- uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
+     } else {
--                                void *fdt);
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
-+                                MachineState *ms);
++                      offsetof(CPURISCVState, badaddr));
- void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
  void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                 hwaddr saddr,
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
  }
  /*
 - * The FDT should be put at the farthest point possible to
 - * avoid overwriting it with the kernel/initrd.
 + * This function makes an assumption that the DRAM interval
 + * 'dram_base' + 'dram_size' is contiguous.
   *
 - * This function makes an assumption that the DRAM is
 - * contiguous. It also cares about 32-bit systems and
 - * will limit fdt_addr to be addressable by them even for
 - * 64-bit CPUs.
 + * Considering that 'dram_end' is the lowest value between
 + * the end of the DRAM block and MachineState->ram_size, the
 + * FDT location will vary according to 'dram_base':
 + *
 + * - if 'dram_base' is less that 3072 MiB, the FDT will be
 + * put at the lowest value between 3072 MiB and 'dram_end';
 + *
 + * - if 'dram_base' is higher than 3072 MiB, the FDT will be
 + * put at 'dram_end'.
   *
   * The FDT is fdt_packed() during the calculation.
   */
 -uint64_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size,
 -                                void *fdt)
 +uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
 +                                MachineState *ms)
  {
 -    uint64_t temp;
 -    hwaddr dram_end = dram_base + mem_size;
 -    int ret = fdt_pack(fdt);
 +    int ret = fdt_pack(ms->fdt);
 +    hwaddr dram_end, temp;
      int fdtsize;
      /* Should only fail if we've built a corrupted tree */
      g_assert(ret == 0);
 -    fdtsize = fdt_totalsize(fdt);
 +    fdtsize = fdt_totalsize(ms->fdt);
      if (fdtsize <= 0) {
          error_report("invalid device-tree");
          exit(1);
      }
+     return true;
 +    /*
 +     * A dram_size == 0, usually from a MemMapEntry[].size element,
 +     * means that the DRAM block goes all the way to ms->ram_size.
 +     */
 +    dram_end = dram_base;
 +    dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size;
 +
      /*
       * We should put fdt as far as possible to avoid kernel/initrd overwriting
       * its content. But it should be addressable by 32 bit system as well.
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
          /* Compute the fdt load address in dram */
          fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 -                                               machine->ram_size, machine->fdt);
 +                                               memmap[MICROCHIP_PFSOC_DRAM_LO].size,
 +                                               machine);
          riscv_load_fdt(fdt_load_addr, machine->fdt);
          /* Load the reset vector */
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      }
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
 -                                           machine->ram_size, machine->fdt);
 +                                           memmap[SIFIVE_U_DEV_DRAM].size,
 +                                           machine);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      if (!riscv_is_32bit(&s->soc.u_cpus)) {
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      }
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
 -                                           machine->ram_size, machine->fdt);
 +                                           memmap[SPIKE_DRAM].size,
 +                                           machine);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      /* load the reset vector */
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
      }
      fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
 -                                           machine->ram_size, machine->fdt);
 +                                           memmap[VIRT_DRAM].size,
 +                                           machine);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      /* load the reset vector */
 --
-.39.1
+.45.1

-[PULL 04/32] target/riscv: Update VS timer whenever htimedelta changes
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Anup Patel <apatel@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-The htimedelta[h] CSR has impact on the VS timer comparison so we
+Add support for Zve32x extension and replace some checks for Zve32f with
-should call riscv_timer_write_timecmp() whenever htimedelta changes.
+Zve32x, since Zve32f depends on Zve32x.
-Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 16 ++++++++++++++++
+ target/riscv/cpu_cfg.h                  |  1 +
-file changed, 16 insertions(+)
+ target/riscv/cpu.c                      |  2 ++
  target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zhinx;
+     bool ext_zhinxmin;
+     bool ext_zve32f;
++    bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
+     bool ext_zvbb;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
+     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
++    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+     *cs_base = 0;
+-    if (cpu->cfg.ext_zve32f) {
++    if (cpu->cfg.ext_zve32x) {
+         /*
+          * If env->vl equals to VLMAX, we can use generic vector operation
+          * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
- static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
-                                        target_ulong val)
+ static RISCVException vs(CPURISCVState *env, int csrno)
  {
-+    RISCVCPU *cpu = env_archcpu(env);
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
-+
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
-     if (!env->rdtime_fn) {
+ #if !defined(CONFIG_USER_ONLY)
-         return RISCV_EXCP_ILLEGAL_INST;
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
-     } else {
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-         env->htimedelta = val;
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 -        return;
 +    /* The Zve32f extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
-+
-+    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+     if (cpu->cfg.ext_zvfh) {
-+        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+                                  env->htimedelta, MIP_VSTIP);
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
-+    }
+     }
-+
-     return RISCV_EXCP_NONE;
+-    /*
- }
+-     * In principle Zve*x would also suffice here, were they supported
+-     * in qemu
-@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
+-     */
- static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
+     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
-                                         target_ulong val)
+          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
-+    RISCVCPU *cpu = env_archcpu(env);
+     TCGv s1, dst;
-+
-     if (!env->rdtime_fn) {
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
-         return RISCV_EXCP_ILLEGAL_INST;
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
-     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
-+
+ {
-+    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+     TCGv dst;
-+        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
-+                                  env->htimedelta, MIP_VSTIP);
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
-+    }
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
-+
+         return false;
-     return RISCV_EXCP_NONE;
+     }
  }
 --
-.39.1
+.45.1

-[PULL 26/32] RISC-V: Add initial support for T-Head C906
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Jason Chien <jason.chien@sifive.com>
-This patch adds the T-Head C906 to the list of known CPUs.
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-Selecting this CPUs will automatically enable the available
+enabling Zve64x enables Zve32x according to their dependency.
 ISA extensions of the CPUs (incl. vendor extensions).
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu>
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h          |  1 +
+ target/riscv/cpu_cfg.h     |  1 +
- target/riscv/cpu_vendorid.h |  6 ++++++
+ target/riscv/cpu.c         |  2 ++
- target/riscv/cpu.c          | 31 +++++++++++++++++++++++++++++++
+ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
-files changed, 38 insertions(+)
+files changed, 14 insertions(+), 6 deletions(-)
  create mode 100644 target/riscv/cpu_vendorid.h
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
+     bool ext_zve32x;
- #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
+     bool ext_zve64f;
- #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+     bool ext_zve64d;
-+#define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
++    bool ext_zve64x;
- #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
+     bool ext_zvbb;
+     bool ext_zvbc;
- #if defined(TARGET_RISCV32)
+     bool ext_zvkb;
 diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/cpu_vendorid.h
@@ -XXX,XX +XXX,XX @@
 +#ifndef TARGET_RISCV_CPU_VENDORID_H
 +#define TARGET_RISCV_CPU_VENDORID_H
 +
 +#define THEAD_VENDOR_ID         0x5b7
 +
 +#endif /*  TARGET_RISCV_CPU_VENDORID_H */
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- #include "qemu/ctype.h"
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
- #include "qemu/log.h"
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
- #include "cpu.h"
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+#include "cpu_vendorid.h"
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
- #include "pmu.h"
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
- #include "internals.h"
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
- #include "time_helper.h"
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     cpu->cfg.mmu = false;
+     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
- }
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
-+static void rv64_thead_c906_cpu_init(Object *obj)
++    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
-+{
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
-+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+     MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
-+    RISCVCPU *cpu = RISCV_CPU(obj);
+     MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
-+
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+index XXXXXXX..XXXXXXX 100644
-+    set_priv_version(env, PRIV_VERSION_1_11_0);
+--- a/target/riscv/tcg/tcg-cpu.c
-+
++++ b/target/riscv/tcg/tcg-cpu.c
-+    cpu->cfg.ext_g = true;
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+    cpu->cfg.ext_c = true;
-+    cpu->cfg.ext_u = true;
+     /* The Zve64d extension depends on the Zve64f extension */
-+    cpu->cfg.ext_s = true;
+     if (cpu->cfg.ext_zve64d) {
-+    cpu->cfg.ext_icsr = true;
++        if (!riscv_has_ext(env, RVD)) {
-+    cpu->cfg.ext_zfh = true;
++            error_setg(errp, "Zve64d/V extensions require D extension");
-+    cpu->cfg.mmu = true;
++            return;
-+    cpu->cfg.ext_xtheadba = true;
++        }
-+    cpu->cfg.ext_xtheadbb = true;
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
-+    cpu->cfg.ext_xtheadbs = true;
+     }
-+    cpu->cfg.ext_xtheadcmo = true;
-+    cpu->cfg.ext_xtheadcondmov = true;
+-    /* The Zve64f extension depends on the Zve32f extension */
-+    cpu->cfg.ext_xtheadfmemidx = true;
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
-+    cpu->cfg.ext_xtheadmac = true;
+     if (cpu->cfg.ext_zve64f) {
-+    cpu->cfg.ext_xtheadmemidx = true;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
-+    cpu->cfg.ext_xtheadmempair = true;
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
-+    cpu->cfg.ext_xtheadsync = true;
+     }
-+
-+    cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-+}
+-        error_setg(errp, "Zve64d/V extensions require D extension");
-+
+-        return;
- static void rv128_base_cpu_init(Object *obj)
++    /* The Zve64x extension depends on the Zve32x extension */
- {
++    if (cpu->cfg.ext_zve64x) {
-     if (qemu_tcg_mttcg_enabled()) {
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
+     }
-     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
-     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
+     /* The Zve32f extension depends on the Zve32x extension */
-     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+    DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,       rv64_thead_c906_cpu_init),
+         return;
-     DEFINE_CPU(TYPE_RISCV_CPU_BASE128,          rv128_base_cpu_init),
+     }
- #endif
- };
+-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.39.1
+.45.1

-[PULL 28/32] target/riscv: add a MAINTAINERS entry for XThead* extension support
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Jason Chien <jason.chien@sifive.com>
-The XThead* extensions are maintained by T-Head and VRULL.
+In current implementation, the gdbstub allows reading vector registers
-Adding a point of contact from both companies.
+only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Message-Id: <20230131202013.2541053-15-christoph.muellner@vrull.eu>
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- MAINTAINERS | 8 ++++++++
+ target/riscv/gdbstub.c | 2 +-
-file changed, 8 insertions(+)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/target/riscv/gdbstub.c
-+++ b/MAINTAINERS
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
- F: linux-user/host/riscv32/
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
- F: linux-user/host/riscv64/
+);
+     }
-+RISC-V XThead* extensions
+-    if (env->misa_ext & RVV) {
-+M: Christoph Muellner <christoph.muellner@vrull.eu>
++    if (cpu->cfg.ext_zve32x) {
-+M: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
-+L: qemu-riscv@nongnu.org
+                                  riscv_gdb_set_vector,
-+S: Supported
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 +F: target/riscv/insn_trans/trans_xthead.c.inc
 +F: target/riscv/xthead*.decode
 +
  RISC-V XVentanaCondOps extension
  M: Philipp Tomsich <philipp.tomsich@vrull.eu>
  L: qemu-riscv@nongnu.org
 --
-.39.1
+.45.1

-[PULL 30/32] target/riscv: fix ctzw behavior
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Vladimir Isaev <vladimir.isaev@syntacore.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-According to spec, ctzw should work with 32-bit register, not 64.
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
 using vext_set_elems_1s function if the vma/vta bit is set. It is the element
 agnostic policy.
-For example, previous implementation returns 33 for (1<<33) input
+However, this function can't deal the big endian situation. This patch fixes
-when the new one returns 32.
+the problem by adding handling of such case.
-Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20230204082312.43557-1-vladimir.isaev@syntacore.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/insn_trans/trans_rvb.c.inc | 1 +
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
-file changed, 1 insertion(+)
+file changed, 22 insertions(+)
-diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvb.c.inc
+--- a/target/riscv/vector_internals.c
-+++ b/target/riscv/insn_trans/trans_rvb.c.inc
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
- {
+     if (tot - cnt == 0) {
-     REQUIRE_64BIT(ctx);
+         return ;
-     REQUIRE_ZBB(ctx);
+     }
-+    ctx->ol = MXL_RV32;
++
-     return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
++    if (HOST_BIG_ENDIAN) {
 +        /*
 +         * Deal the situation when the elements are insdie
 +         * only one uint64 block including setting the
 +         * masked-off element.
 +         */
 +        if (((tot - 1) ^ cnt) < 8) {
 +            memset(base + H1(tot - 1), -1, tot - cnt);
 +            return;
 +        }
 +        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
 --
-.39.1
+.45.1

-[PULL 25/32] RISC-V: Set minimum priv version for Zfh to 1.11
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Yangyu Chen <cyy@cyyself.name>
-There are no differences for floating point instructions in priv version 1.11
+This code has a typo that writes zvkb to zvkg, causing users can't
-and 1.12. There is also no dependency for Zfh to priv version 1.12.
+enable zvkb through the config. This patch gets this fixed.
 Therefore allow Zfh to be enabled for priv version 1.11.
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
-Message-Id: <20230131202013.2541053-12-christoph.muellner@vrull.eu>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
+     /* Vector cryptography extensions */
-     ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
-     ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--    ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-+    ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
-     ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
-     ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
-     ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 --
-.39.1
+.45.1

-[PULL 27/32] RISC-V: Adding XTheadFmv ISA extension
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-This patch adds support for the XTheadFmv ISA extension.
+In this patch, we modify the decoder to be a freely composable data
-The patch uses the T-Head specific decoder and translation.
+structure instead of a hardcoded one. It can be dynamically builded up
 according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
 Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
 Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/cpu.h         |  1 +
- target/riscv/xthead.decode                 |  4 ++
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
- target/riscv/cpu.c                         |  2 +
+ target/riscv/cpu.c         |  1 +
- target/riscv/translate.c                   |  6 +--
+ target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
- target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++
+ target/riscv/translate.c   | 31 +++++++++++++++----------------
-files changed, 55 insertions(+), 3 deletions(-)
+files changed, 47 insertions(+), 16 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-     bool ext_xtheadcmo;
+     uint32_t pmu_avail_ctrs;
-     bool ext_xtheadcondmov;
+     /* Mapping of events to counters */
-     bool ext_xtheadfmemidx;
+     GHashTable *pmu_event_ctr_map;
-+    bool ext_xtheadfmv;
++    const GPtrArray *decoders;
-     bool ext_xtheadmac;
+ };
-     bool ext_xtheadmemidx;
-     bool ext_xtheadmempair;
+ /**
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
+--- a/target/riscv/tcg/tcg-cpu.h
-+++ b/target/riscv/xthead.decode
++++ b/target/riscv/tcg/tcg-cpu.h
-@@ -XXX,XX +XXX,XX @@ th_fsrw          01000 .. ..... ..... 111 ..... 0001011 @th_memidx
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
- th_fsurd         01110 .. ..... ..... 111 ..... 0001011 @th_memidx
+ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
- th_fsurw         01010 .. ..... ..... 111 ..... 0001011 @th_memidx
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
-+# XTheadFmv
++struct DisasContext;
-+th_fmv_hw_x      1010000  00000 ..... 001 ..... 0001011 @r2
++struct RISCVCPUConfig;
-+th_fmv_x_hw      1100000  00000 ..... 001 ..... 0001011 @r2
++typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
- # XTheadMac
++typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
- th_mula          00100 00 ..... ..... 001 ..... 0001011 @r
++
- th_mulah         00101 00 ..... ..... 001 ..... 0001011 @r
++extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
-     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+             error_propagate(errp, local_err);
-     ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
+             return;
-     ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
+         }
-+    ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv),
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
-     ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
+     } else if (kvm_enabled()) {
-     ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
-     ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
+         if (local_err != NULL) {
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+index XXXXXXX..XXXXXXX 100644
-     DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
+--- a/target/riscv/tcg/tcg-cpu.c
-     DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
++++ b/target/riscv/tcg/tcg-cpu.c
-+    DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
+@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
-     DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
+     }
-     DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
+ }
-     DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
 +{
 +    GPtrArray *dynamic_decoders;
 +    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
 +    for (size_t i = 0; i < decoder_table_size; ++i) {
 +        if (decoder_table[i].guard_func &&
 +            decoder_table[i].guard_func(&cpu->cfg)) {
 +            g_ptr_array_add(dynamic_decoders,
 +                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
 +        }
 +    }
 +
 +    cpu->decoders = dynamic_decoders;
 +}
 +
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
  {
      return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
+@@ -XXX,XX +XXX,XX @@
-     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
+ #include "exec/helper-info.c.inc"
-            ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
+ #undef  HELPER_H
-            ctx->cfg_ptr->ext_xtheadcondmov ||
--           ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac ||
++#include "tcg/tcg-cpu.h"
--           ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
++
--           ctx->cfg_ptr->ext_xtheadsync;
+ /* global register indices */
-+           ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
+ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
-+           ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
+ static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
-+           ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* FRM is known to contain a valid value. */
      bool frm_valid;
      bool insn_start_updated;
 +    const GPtrArray *decoders;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
      return (first_word & 3) == 3 ? 4 : 2;
  }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
++const RISCVDecoder decoder_table[] = {
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
++    { always_true_p, decode_insn32 },
-index XXXXXXX..XXXXXXX 100644
++    { has_xthead_p, decode_xthead},
---- a/target/riscv/insn_trans/trans_xthead.c.inc
++    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
++};
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADFMV(ctx) do {              \
 +    if (!ctx->cfg_ptr->ext_xtheadfmv) {          \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
- #define REQUIRE_XTHEADMAC(ctx) do {              \
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
-     if (!ctx->cfg_ptr->ext_xtheadmac) {          \
++
-         return false;                            \
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
-@@ -XXX,XX +XXX,XX @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
+ {
-     return gen_fstore_idx(ctx, a, MO_TEUL, true);
+-    /*
 -     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
      ctx->virt_inst_excp = false;
      ctx->cur_insn_len = insn_len(opcode);
      /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                               ctx->base.pc_next + 2));
          ctx->opcode = opcode32;
 -        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
 -            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
      ctx->virt_inst_excp = false;
 +    ctx->decoders = cpu->decoders;
  }
-+/* XTheadFmv */
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 +
 +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a)
 +{
 +    REQUIRE_XTHEADFMV(ctx);
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +
 +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
 +    TCGv_i64 t1 = tcg_temp_new_i64();
 +
 +    tcg_gen_extu_tl_i64(t1, src1);
 +    tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32);
 +    tcg_temp_free_i64(t1);
 +    mark_fs_dirty(ctx);
 +    return true;
 +}
 +
 +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a)
 +{
 +    REQUIRE_XTHEADFMV(ctx);
 +    REQUIRE_32BIT(ctx);
 +    REQUIRE_FPU;
 +    REQUIRE_EXT(ctx, RVD);
 +    TCGv dst;
 +    TCGv_i64 t1;
 +
 +    dst = dest_gpr(ctx, a->rd);
 +    t1 = tcg_temp_new_i64();
 +
 +    tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
 +    tcg_gen_trunc_i64_tl(dst, t1);
 +    gen_set_gpr(ctx, a->rd, dst);
 +    tcg_temp_free_i64(t1);
 +    mark_fs_dirty(ctx);
 +    return true;
 +}
 +
  /* XTheadMac */
  static bool gen_th_mac(DisasContext *ctx, arg_r *a,
 --
-.39.1
+.45.1

-[PULL 15/32] RISC-V: Adding XTheadCmo ISA extension
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
 From: Christoph Müllner <christoph.muellner@vrull.eu>
-This patch adds support for the XTheadCmo ISA extension.
+The th.sxstatus CSR can be used to identify available custom extension
-To avoid interfering with standard extensions, decoder and translation
+on T-Head CPUs. The CSR is documented here:
-are in its own xthead* specific files.
+  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
 Future patches should be able to easily add additional T-Head extension.
-The implementation does not have much functionality (besides accepting
+An important property of this patch is, that the th.sxstatus MAEE field
-the instructions and not qualifying them as illegal instructions if
+is not set (indicating that XTheadMae is not available).
-the hart executes in the required privilege level for the instruction),
+XTheadMae is a memory attribute extension (similar to Svpbmt) which is
-as QEMU does not model CPU caches and instructions are documented
+implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
-to not raise any exceptions.
+in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Further context can be found on the list:
 https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ MAINTAINERS              |  1 +
- target/riscv/xthead.decode                 | 38 ++++++++++
+ target/riscv/cpu.h       |  3 ++
- target/riscv/cpu.c                         |  2 +
+ target/riscv/cpu.c       |  1 +
- target/riscv/translate.c                   |  8 +++
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++
+ target/riscv/meson.build |  1 +
- target/riscv/meson.build                   |  1 +
+files changed, 85 insertions(+)
-files changed, 131 insertions(+)
+ create mode 100644 target/riscv/th_csr.c
  create mode 100644 target/riscv/xthead.decode
  create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
-     uint64_t mimpid;
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-     /* Vendor-specific custom extensions */
-+    bool ext_xtheadcmo;
++/* Implemented in th_csr.c */
-     bool ext_XVentanaCondOps;
++void th_register_custom_csrs(RISCVCPU *cpu);
      uint8_t pmu_num;
 diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
 +#
 +# Translation routines for the instructions of the XThead* ISA extensions
 +#
 +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
 +#
 +# SPDX-License-Identifier: LGPL-2.1-or-later
 +#
 +# The documentation of the ISA extensions can be found here:
 +#   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
 +
-+# Fields:
+ #endif /* RISCV_CPU_H */
 +%rs1       15:5
 +
 +# Formats
 +@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 +
 +# XTheadCmo
 +th_dcache_call   0000000 00001 00000 000 00000 0001011
 +th_dcache_ciall  0000000 00011 00000 000 00000 0001011
 +th_dcache_iall   0000000 00010 00000 000 00000 0001011
 +th_dcache_cpa    0000001 01001 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_cipa   0000001 01011 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_ipa    0000001 01010 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_cva    0000001 00101 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_civa   0000001 00111 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_iva    0000001 00110 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_csw    0000001 00001 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_cisw   0000001 00011 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_isw    0000001 00010 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_cpal1  0000001 01000 ..... 000 00000 0001011 @sfence_vm
 +th_dcache_cval1  0000001 00100 ..... 000 00000 0001011 @sfence_vm
 +th_icache_iall   0000000 10000 00000 000 00000 0001011
 +th_icache_ialls  0000000 10001 00000 000 00000 0001011
 +th_icache_ipa    0000001 11000 ..... 000 00000 0001011 @sfence_vm
 +th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
 +th_l2cache_call  0000000 10101 00000 000 00000 0001011
 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
 +th_l2cache_iall  0000000 10110 00000 000 00000 0001011
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
-     ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
+ #ifndef CONFIG_USER_ONLY
-     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-+    ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
++    th_register_custom_csrs(cpu);
-     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
+ #endif
- };
+     /* inherited from parent obj via riscv_cpu_init() */
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
      DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
      /* Vendor-specific custom extensions */
 +    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
      /* These are experimental so mark with 'x-' */
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
      return true;
  }
 +static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
 +{
 +    return ctx->cfg_ptr->ext_xtheadcmo;
 +}
 +
  #define MATERIALISE_EXT_PREDICATE(ext)  \
      static bool has_ ## ext ## _p(DisasContext *ctx)    \
      { \
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  #include "insn_trans/trans_rvk.c.inc"
  #include "insn_trans/trans_privileged.c.inc"
  #include "insn_trans/trans_svinval.c.inc"
 +#include "decode-xthead.c.inc"
 +#include "insn_trans/trans_xthead.c.inc"
  #include "insn_trans/trans_xventanacondops.c.inc"
  /* Include the auto-generated decoder for 16 bit insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
          bool (*decode_func)(DisasContext *, uint32_t);
      } decoders[] = {
          { always_true_p,  decode_insn32 },
 +        { has_xthead_p, decode_xthead },
          { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
      };
 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
++++ b/target/riscv/th_csr.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * RISC-V translation routines for the T-Head vendor extensions (xthead*).
++ * T-Head-specific CSRs.
 + *
-+ * Copyright (c) 2022 VRULL GmbH.
++ * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#define REQUIRE_XTHEADCMO(ctx) do {              \
++#include "qemu/osdep.h"
-+    if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
++#include "cpu.h"
-+        return false;                            \
++#include "cpu_vendorid.h"
 +    }                                            \
 +} while (0)
 +
-+/* XTheadCmo */
++#define CSR_TH_SXSTATUS 0x5c0
 +
-+static inline int priv_level(DisasContext *ctx)
++/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
-+#ifdef CONFIG_USER_ONLY
++    if (riscv_has_ext(env, RVS)) {
-+    return PRV_U;
++        return RISCV_EXCP_NONE;
-+#else
++    }
-+     /* Priv level is part of mem_idx. */
++
-+    return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
++    return RISCV_EXCP_ILLEGAL_INST;
 +#endif
 +}
 +
-+/* Test if priv level is M, S, or U (cannot fail). */
++static int test_thead_mvendorid(RISCVCPU *cpu)
-+#define REQUIRE_PRIV_MSU(ctx)
++{
 +    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
 +        return -1;
 +    }
 +
-+/* Test if priv level is M or S. */
++    return 0;
 +#define REQUIRE_PRIV_MS(ctx)                                    \
 +do {                                                            \
 +    int priv = priv_level(ctx);                                 \
 +    if (!(priv == PRV_M ||                                      \
 +          priv == PRV_S)) {                                     \
 +        return false;                                           \
 +    }                                                           \
 +} while (0)
 +
 +#define NOP_PRIVCHECK(insn, extcheck, privcheck)                \
 +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \
 +{                                                               \
 +    (void) a;                                                   \
 +    extcheck(ctx);                                              \
 +    privcheck(ctx);                                             \
 +    return true;                                                \
 +}
 +
-+NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
-+NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++                                       target_ulong *val)
-+NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++{
-+NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
-+NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
-+NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++    return RISCV_EXCP_NONE;
-+NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
++}
 +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
 +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
 +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 +
-+NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++static riscv_csr th_csr_list[] = {
-+NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++    {
-+NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++        .csrno = CSR_TH_SXSTATUS,
-+NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
++        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
-+NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++void th_register_custom_csrs(RISCVCPU *cpu)
-+NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++{
-+NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
++    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
- gen = [
+   'monitor.c',
-   decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
+   'machine.c',
-   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+   'pmu.c',
-+  decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
++  'th_csr.c',
-   decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
+   'time_helper.c',
- ]
+   'riscv-qmp-cmds.c',
+ ))
 --
-.39.1
+.45.1

-[PULL 22/32] RISC-V: Adding T-Head MemPair extension
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Max Chou <max.chou@sifive.com>
-This patch adds support for the T-Head MemPair instructions.
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-The patch uses the T-Head specific decoder and translation.
+instructions will be affected by Zvfhmin extension.
 And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+* From 1*SEW(16/32) to 2*SEW(32/64)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+* From 2*SEW(32/64) to 1*SEW(16/32)
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
- target/riscv/xthead.decode                 | 13 +++
+file changed, 18 insertions(+), 2 deletions(-)
  target/riscv/cpu.c                         |  2 +
  target/riscv/translate.c                   |  2 +-
  target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++
 files changed, 109 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
-     bool ext_xtheadcmo;
+     }
      bool ext_xtheadcondmov;
      bool ext_xtheadmac;
 +    bool ext_xtheadmempair;
      bool ext_xtheadsync;
      bool ext_XVentanaCondOps;
 diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/xthead.decode
 +++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
  # Fields:
  %rd        7:5
 +%rd1       7:5
 +%rs        15:5
  %rs1       15:5
 +%rd2       20:5
  %rs2       20:5
  %sh5       20:5
  %sh6       20:6
 +%sh2       25:2
  # Argument sets
  &r         rd rs1 rs2                               !extern
  &r2        rd rs1                                   !extern
  &shift     shamt rs1 rd                             !extern
  &th_bfext  msb lsb rs1 rd
 +&th_pair   rd1 rs rd2 sh2
  # Formats
  @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
@@ -XXX,XX +XXX,XX @@
  @th_bfext   msb:6  lsb:6  .....  ... ..... .......  &th_bfext %rs1 %rd
  @sh5        ....... ..... .....  ... ..... .......  &shift  shamt=%sh5      %rs1 %rd
  @sh6        ...... ...... .....  ... ..... .......  &shift shamt=%sh6 %rs1 %rd
 +@th_pair    ..... .. ..... ..... ... ..... .......  &th_pair %rd1 %rs %rd2 %sh2
  # XTheadBa
  # Instead of defining a new encoding, we simply use the decoder to
@@ -XXX,XX +XXX,XX @@ th_muls          00100 01 ..... ..... 001 ..... 0001011 @r
  th_mulsh         00101 01 ..... ..... 001 ..... 0001011 @r
  th_mulsw         00100 11 ..... ..... 001 ..... 0001011 @r
 +# XTheadMemPair
 +th_ldd           11111 .. ..... ..... 100 ..... 0001011 @th_pair
 +th_lwd           11100 .. ..... ..... 100 ..... 0001011 @th_pair
 +th_lwud          11110 .. ..... ..... 100 ..... 0001011 @th_pair
 +th_sdd           11111 .. ..... ..... 101 ..... 0001011 @th_pair
 +th_swd           11100 .. ..... ..... 101 ..... 0001011 @th_pair
 +
  # XTheadSync
  th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
  th_sync          0000000 11000 00000 000 00000 0001011
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
      ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
      ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
 +    ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
      ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
  };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
      DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
 +    DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
      DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
      return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
             ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
             ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
 -           ctx->cfg_ptr->ext_xtheadsync;
 +           ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
  }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
++static bool require_rvfmin(DisasContext *s)
 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_xthead.c.inc
 +++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADMEMPAIR(ctx) do {          \
 +    if (!ctx->cfg_ptr->ext_xtheadmempair) {      \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADSYNC(ctx) do {             \
      if (!ctx->cfg_ptr->ext_xtheadsync) {         \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
      return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
  }
 +/* XTheadMemPair */
 +
 +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
 +                            int shamt)
 +{
-+    if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
 +        return false;
 +    }
 +
-+    TCGv t1 = tcg_temp_new();
++    switch (s->sew) {
-+    TCGv t2 = tcg_temp_new();
++    case MO_16:
-+    TCGv addr1 = tcg_temp_new();
++        return s->cfg_ptr->ext_zvfhmin;
-+    TCGv addr2 = tcg_temp_new();
++    case MO_32:
-+    int imm = a->sh2 << shamt;
++        return s->cfg_ptr->ext_zve32f;
-+
++    default:
-+    addr1 = get_address(ctx, a->rs, imm);
++        return false;
-+    addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
++    }
 +
 +    tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop);
 +    tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop);
 +    gen_set_gpr(ctx, a->rd1, t1);
 +    gen_set_gpr(ctx, a->rd2, t2);
 +
 +    tcg_temp_free(t1);
 +    tcg_temp_free(t2);
 +    tcg_temp_free(addr1);
 +    tcg_temp_free(addr2);
 +    return true;
 +}
 +
-+static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a)
+ static bool require_scale_rvf(DisasContext *s)
-+{
+ {
-+    REQUIRE_XTHEADMEMPAIR(ctx);
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+    REQUIRE_64BIT(ctx);
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
-+    return gen_loadpair_tl(ctx, a, MO_TESQ, 4);
+     }
-+}
-+
+     switch (s->sew) {
-+static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a)
+-    case MO_8:
-+{
+-        return s->cfg_ptr->ext_zvfhmin;
-+    REQUIRE_XTHEADMEMPAIR(ctx);
+     case MO_16:
-+    return gen_loadpair_tl(ctx, a, MO_TESL, 3);
+         return s->cfg_ptr->ext_zve32f;
-+}
+     case MO_32:
-+
+@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
-+static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a)
+ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
-+{
+ {
-+    REQUIRE_XTHEADMEMPAIR(ctx);
+     return opfv_widen_check(s, a) &&
-+    return gen_loadpair_tl(ctx, a, MO_TEUL, 3);
++           require_rvfmin(s) &&
-+}
+            require_scale_rvfmin(s) &&
-+
+            (s->sew != MO_8);
-+static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
+ }
-+                             int shamt)
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
-+{
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-+    if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
+ {
-+        return false;
+     return opfv_narrow_check(s, a) &&
-+    }
++           require_rvfmin(s) &&
-+
+            require_scale_rvfmin(s) &&
-+    TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
+            (s->sew != MO_8);
-+    TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
+ }
 +    TCGv addr1 = tcg_temp_new();
 +    TCGv addr2 = tcg_temp_new();
 +    int imm = a->sh2 << shamt;
 +
 +    addr1 = get_address(ctx, a->rs, imm);
 +    addr2 = get_address(ctx, a->rs, memop_size(memop) + imm);
 +
 +    tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop);
 +    tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop);
 +
 +    tcg_temp_free(addr1);
 +    tcg_temp_free(addr2);
 +    return true;
 +}
 +
 +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a)
 +{
 +    REQUIRE_XTHEADMEMPAIR(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_storepair_tl(ctx, a, MO_TESQ, 4);
 +}
 +
 +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a)
 +{
 +    REQUIRE_XTHEADMEMPAIR(ctx);
 +    return gen_storepair_tl(ctx, a, MO_TESL, 3);
 +}
 +
  /* XTheadSync */
  static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
 --
-.39.1
+.45.1

-[PULL 32/32] hw/riscv: virt: Simplify virt_{get,set}_aclint()
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Bin Meng <bmeng@tinylab.org>
+From: Max Chou <max.chou@sifive.com>
-There is no need to declare an intermediate "MachineState *ms".
+The require_scale_rvf function only checks the double width operator for
 the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+integer to double width float, so the opfxv_widen_check function doesn’t
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+need require_rvf for the single width operator(integer).
-Message-Id: <20230206085007.3618715-1-bmeng@tinylab.org>
 Signed-off-by: Max Chou <max.chou@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 6 ++----
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
-file changed, 2 insertions(+), 4 deletions(-)
+file changed, 5 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
  static bool virt_get_aclint(Object *obj, Error **errp)
  {
--    MachineState *ms = MACHINE(obj);
+     return require_rvv(s) &&
--    RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
++           require_rvf(s) &&
-+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
-     return s->have_aclint;
+            vext_check_isa_ill(s) &&
- }
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
+ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  static void virt_set_aclint(Object *obj, bool value, Error **errp)
  {
--    MachineState *ms = MACHINE(obj);
+     return require_rvv(s) &&
--    RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
++           require_rvf(s) &&
-+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+            require_scale_rvf(s) &&
+            (s->sew != MO_8) &&
-     s->have_aclint = value;
+            vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.39.1
+.45.1

-[PULL 29/32] target/riscv: fix for virtual instr exception
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Deepak Gupta <debug@rivosinc.com>
+From: Max Chou <max.chou@sifive.com>
-commit fb3f3730e4 added mechanism to generate virtual instruction
+The opfv_narrow_check needs to check the single width float operator by
-exception during instruction decode when virt is enabled.
+require_rvf.
-However in some situations, illegal instruction exception can be raised
+Signed-off-by: Max Chou <max.chou@sifive.com>
-due to state of CPU. One such situation is implementing branch tracking.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-[1] An indirect branch if doesn't land on a landing pad instruction, then
+Cc: qemu-stable <qemu-stable@nongnu.org>
-cpu must raise an illegal instruction exception.
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Implementation would raise such expcetion due to missing landing pad inst
 and not due to decode. Thus DisasContext must have `virt_inst_excp`
 initialized to false during DisasContxt initialization for TB.
 [1] - https://github.com/riscv/riscv-cfi
 Signed-off-by: Deepak Gupta <debug@rivosinc.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20230127191758.755844-1-debug@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/translate.c | 1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 file changed, 1 insertion(+)
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/translate.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
-     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
+ {
-     ctx->zero = tcg_constant_tl(0);
+     return opfv_narrow_check(s, a) &&
-+    ctx->virt_inst_excp = false;
++           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
- static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.39.1
+.45.1

-[PULL 19/32] RISC-V: Adding XTheadBs ISA extension
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Max Chou <max.chou@sifive.com>
-This patch adds support for the XTheadBs ISA extension.
+If the checking functions check both the single and double width
-The patch uses the T-Head specific decoder and translation.
+operators at the same time, then the single width operator checking
 functions (require_rvf[min]) will check whether the SEW is 8.
-Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
- target/riscv/xthead.decode                 |  3 +++
+file changed, 4 insertions(+), 12 deletions(-)
  target/riscv/cpu.c                         |  2 ++
  target/riscv/translate.c                   |  3 ++-
  target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++
 files changed, 23 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-     /* Vendor-specific custom extensions */
+     return require_rvv(s) &&
-     bool ext_xtheadba;
+            require_rvf(s) &&
-     bool ext_xtheadbb;
+            require_scale_rvf(s) &&
-+    bool ext_xtheadbs;
+-           (s->sew != MO_8) &&
-     bool ext_xtheadcmo;
+            vext_check_isa_ill(s) &&
-     bool ext_xtheadsync;
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
-     bool ext_XVentanaCondOps;
+ }
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-index XXXXXXX..XXXXXXX 100644
+     return require_rvv(s) &&
---- a/target/riscv/xthead.decode
+            require_rvf(s) &&
-+++ b/target/riscv/xthead.decode
+            require_scale_rvf(s) &&
-@@ -XXX,XX +XXX,XX @@ th_rev           1000001 00000 ..... 001 ..... 0001011 @r2
+-           (s->sew != MO_8) &&
- th_revw          1001000 00000 ..... 001 ..... 0001011 @r2
+            vext_check_isa_ill(s) &&
- th_tstnbz        1000000 00000 ..... 001 ..... 0001011 @r2
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
+ }
-+# XTheadBs
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-+th_tst           100010 ...... ..... 001 ..... 0001011 @sh6
+     return require_rvv(s) &&
-+
+            require_rvf(s) &&
- # XTheadCmo
+            require_scale_rvf(s) &&
- th_dcache_call   0000000 00001 00000 000 00000 0001011
+-           (s->sew != MO_8) &&
- th_dcache_ciall  0000000 00011 00000 000 00000 0001011
+            vext_check_isa_ill(s) &&
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
-index XXXXXXX..XXXXXXX 100644
+ }
---- a/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
-+++ b/target/riscv/cpu.c
+     return require_rvv(s) &&
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+            require_rvf(s) &&
-     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+            require_scale_rvf(s) &&
-     ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
+-           (s->sew != MO_8) &&
-     ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
+            vext_check_isa_ill(s) &&
-+    ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
+            vext_check_dd(s, a->rd, a->rs2, a->vm);
-     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+ }
-     ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
+@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      /* Vendor-specific custom extensions */
      DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
      DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
 +    DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
  static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
  {
-     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
+     return opfv_widen_check(s, a) &&
--           ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+            require_rvfmin(s) &&
-+           ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
+-           require_scale_rvfmin(s) &&
-+           ctx->cfg_ptr->ext_xtheadsync;
+-           (s->sew != MO_8);
 +           require_scale_rvfmin(s);
  }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/target/riscv/insn_trans/trans_xthead.c.inc
+     return opfv_narrow_check(s, a) &&
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
+            require_rvfmin(s) &&
-@@ -XXX,XX +XXX,XX @@
+-           require_scale_rvfmin(s) &&
-     }                                            \
+-           (s->sew != MO_8);
- } while (0)
++           require_scale_rvfmin(s);
 +#define REQUIRE_XTHEADBS(ctx) do {               \
 +    if (!ctx->cfg_ptr->ext_xtheadbs) {           \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADCMO(ctx) do {              \
      if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a)
      return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz);
  }
-+/* XTheadBs */
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
-+
+ {
-+/* th.tst is an alternate encoding for bexti (from Zbs) */
+     return opfv_narrow_check(s, a) &&
-+static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
+            require_rvf(s) &&
-+{
+-           require_scale_rvf(s) &&
-+    REQUIRE_XTHEADBS(ctx);
+-           (s->sew != MO_8);
-+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
++           require_scale_rvf(s);
-+}
+ }
-+
- /* XTheadCmo */
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
- static inline int priv_level(DisasContext *ctx)
+ {
      return reduction_widen_check(s, a) &&
             require_rvf(s) &&
 -           require_scale_rvf(s) &&
 -           (s->sew != MO_8);
 +           require_scale_rvf(s);
  }
  GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.39.1
+.45.1

-[PULL 08/32] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-riscv_socket_count() returns either ms->numa_state->num_nodes or 1
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
-depending on NUMA support. In any case the value can be retrieved only
+checking first if virt_enabled && !first_stage, and then considering the
-once and used in the rest of the function.
+regular inst/load/store faults.
-This will also alleviate the rename we're going to do next by reducing
+There's no mention in the spec about guest page fault being a higher
-the instances of MachineState 'mc' inside hw/riscv/virt.c.
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+"Attempting to fetch an instruction from a PMP region that does not have
 execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
 So, in fact, we're doing it wrong - PMP faults should always be thrown,
 regardless of also being a first or second stage fault.
 The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
-Message-Id: <20230124212234.412630-2-dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 34 +++++++++++++++++++---------------
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 19 insertions(+), 15 deletions(-)
+file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     int cpu, socket;
-     char *imsic_name;
+     switch (access_type) {
-     MachineState *mc = MACHINE(s);
+     case MMU_INST_FETCH:
-+    int socket_count = riscv_socket_count(mc);
+-        if (env->virt_enabled && !first_stage) {
-     uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
++        if (pmp_violation) {
-     uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
++        } else if (env->virt_enabled && !first_stage) {
-     *msi_m_phandle = (*phandle)++;
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
-     *msi_s_phandle = (*phandle)++;
+         } else {
-     imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
+-            cs->exception_index = pmp_violation ?
--    imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-+    imsic_regs = g_new0(uint32_t, socket_count * 4);
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
+         }
-     /* M-level IMSIC node */
+         break;
-     for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+     case MMU_DATA_LOAD:
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+-        if (two_stage && !first_stage) {
-         imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
++        if (pmp_violation) {
-     }
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-     imsic_max_hart_per_socket = 0;
++        } else if (two_stage && !first_stage) {
--    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
-+    for (socket = 0; socket < socket_count; socket++) {
+         } else {
-         imsic_addr = memmap[VIRT_IMSIC_M].base +
+-            cs->exception_index = pmp_violation ?
-                      socket * VIRT_IMSIC_GROUP_MAX_SIZE;
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
-         imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
+         }
-     qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
+         break;
-         imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
+     case MMU_DATA_STORE:
-     qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+-        if (two_stage && !first_stage) {
--        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
++        if (pmp_violation) {
-+        socket_count * sizeof(uint32_t) * 4);
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
-     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
++        } else if (two_stage && !first_stage) {
-         VIRT_IRQCHIP_NUM_MSIS);
+             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
--    if (riscv_socket_count(mc) > 1) {
+         } else {
-+    if (socket_count > 1) {
+-            cs->exception_index = pmp_violation ?
-         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-             imsic_num_bits(imsic_max_hart_per_socket));
+-                RISCV_EXCP_STORE_PAGE_FAULT;
-         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
++            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
--            imsic_num_bits(riscv_socket_count(mc)));
+         }
-+            imsic_num_bits(socket_count));
+         break;
-         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+     default:
              IMSIC_MMIO_GROUP_MIN_SHIFT);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
      }
      imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
      imsic_max_hart_per_socket = 0;
 -    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
 +    for (socket = 0; socket < socket_count; socket++) {
          imsic_addr = memmap[VIRT_IMSIC_S].base +
                       socket * VIRT_IMSIC_GROUP_MAX_SIZE;
          imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
      qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
          imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
      qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
 -        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
 +        socket_count * sizeof(uint32_t) * 4);
      qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
          VIRT_IRQCHIP_NUM_MSIS);
      if (imsic_guest_bits) {
          qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
              imsic_guest_bits);
      }
 -    if (riscv_socket_count(mc) > 1) {
 +    if (socket_count > 1) {
          qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
              imsic_num_bits(imsic_max_hart_per_socket));
          qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
 -            imsic_num_bits(riscv_socket_count(mc)));
 +            imsic_num_bits(socket_count));
          qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
              IMSIC_MMIO_GROUP_MIN_SHIFT);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
      MachineState *mc = MACHINE(s);
      uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
      uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
 +    int socket_count = riscv_socket_count(mc);
      qemu_fdt_add_subnode(mc->fdt, "/cpus");
      qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
      intc_phandles = g_new0(uint32_t, mc->smp.cpus);
      phandle_pos = mc->smp.cpus;
 -    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
 +    for (socket = (socket_count - 1); socket >= 0; socket--) {
          phandle_pos -= s->soc[socket].num_harts;
          clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
      }
      phandle_pos = mc->smp.cpus;
 -    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
 +    for (socket = (socket_count - 1); socket >= 0; socket--) {
          phandle_pos -= s->soc[socket].num_harts;
          if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
      g_free(intc_phandles);
 -    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
 +    for (socket = 0; socket < socket_count; socket++) {
          if (socket == 0) {
              *irq_mmio_phandle = xplic_phandles[socket];
              *irq_virtio_phandle = xplic_phandles[socket];
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
      /* Pass seed to RNG */
      qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
 -    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
 +    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed",
 +                     rng_seed, sizeof(rng_seed));
  }
  static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      char *soc_name;
      DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
      int i, base_hartid, hart_count;
 +    int socket_count = riscv_socket_count(machine);
      /* Check socket count limit */
 -    if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
 +    if (VIRT_SOCKETS_MAX < socket_count) {
          error_report("number of sockets/nodes should be less than %d",
              VIRT_SOCKETS_MAX);
          exit(1);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      /* Initialize sockets */
      mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
 -    for (i = 0; i < riscv_socket_count(machine); i++) {
 +    for (i = 0; i < socket_count; i++) {
          if (!riscv_socket_check_hartids(machine, i)) {
              error_report("discontinuous hartids in socket%d", i);
              exit(1);
 --
-.39.1
+.45.1

-[PULL 05/32] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: Anup Patel <apatel@ventanamicro.com>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
-should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
-for VSTIP.
+translation part, mtval2 will be set in case of successes 2 stage translation but
 failed pmp check.
-Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
 Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c  |  2 --
+ target/riscv/cpu_helper.c | 12 ++++++------
- target/riscv/time_helper.c | 12 ++++++++----
+file changed, 6 insertions(+), 6 deletions(-)
 files changed, 8 insertions(+), 6 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-         vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
+                               __func__, pa, ret, prot_pmp, tlb_size);
-     }
+                 prot &= prot_pmp;
--    /* No need to update mip for VSTIP */
+-            }
--    mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
+-
-     vstip = env->vstime_irq ? MIP_VSTIP : 0;
+-            if (ret != TRANSLATE_SUCCESS) {
++            } else {
-     QEMU_IOTHREAD_LOCK_GUARD();
+                 /*
-diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
+                  * Guest physical address translation failed, this is a HS
-index XXXXXXX..XXXXXXX 100644
+                  * level exception
---- a/target/riscv/time_helper.c
+                  */
-+++ b/target/riscv/time_helper.c
+                 first_stage_error = false;
-@@ -XXX,XX +XXX,XX @@ static void riscv_vstimer_cb(void *opaque)
+-                env->guest_phys_fault_addr = (im_address |
-     RISCVCPU *cpu = opaque;
+-                                              (address &
-     CPURISCVState *env = &cpu->env;
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
-     env->vstime_irq = 1;
++                if (ret != TRANSLATE_PMP_FAIL) {
--    riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
++                    env->guest_phys_fault_addr = (im_address |
-+    riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
++                                                  (address &
- }
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
++                }
- static void riscv_stimer_cb(void *opaque)
+             }
@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
           */
          if (timer_irq == MIP_VSTIP) {
              env->vstime_irq = 1;
 +            riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
 +        } else {
 +            riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
          }
--        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
+     } else {
          return;
      }
 +    /* Clear the [VS|S]TIP bit in mip */
      if (timer_irq == MIP_VSTIP) {
          env->vstime_irq = 0;
 +        riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
 +    } else {
 +        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
      }
 -    /* Clear the [V]STIP bit in mip */
 -    riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
      /* otherwise, set up the future timer interrupt */
      diff = timecmp - rtc_r;
 --
-.39.1
+.45.1

-[PULL 18/32] RISC-V: Adding XTheadBb ISA extension
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Rob Bradford <rbradford@rivosinc.com>
-This patch adds support for the XTheadBb ISA extension.
+This extension has now been ratified:
-The patch uses the T-Head specific decoder and translation.
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
-Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Since this is now a ratified extension add it to the list of extensions
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+included in the "max" CPU variant.
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |   1 +
+ target/riscv/cpu.c         | 2 +-
- target/riscv/xthead.decode                 |  20 ++++
+ target/riscv/tcg/tcg-cpu.c | 2 +-
- target/riscv/cpu.c                         |   2 +
+files changed, 2 insertions(+), 2 deletions(-)
  target/riscv/translate.c                   |   4 +-
  target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++
 files changed, 149 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     /* Vendor-specific custom extensions */
-     bool ext_xtheadba;
-+    bool ext_xtheadbb;
-     bool ext_xtheadcmo;
-     bool ext_xtheadsync;
-     bool ext_XVentanaCondOps;
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
-+++ b/target/riscv/xthead.decode
-@@ -XXX,XX +XXX,XX @@
- %rd        7:5
- %rs1       15:5
- %rs2       20:5
-+%sh5       20:5
-+%sh6       20:6
- # Argument sets
- &r         rd rs1 rs2                               !extern
-+&r2        rd rs1                                   !extern
-+&shift     shamt rs1 rd                             !extern
-+&th_bfext  msb lsb rs1 rd
- # Formats
- @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
- @rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
- @r          ....... ..... .....  ... ..... .......  &r %rs2 %rs1 %rd
-+@r2         ....... ..... .....  ... ..... .......  &r2 %rs1 %rd
-+@th_bfext   msb:6  lsb:6  .....  ... ..... .......  &th_bfext %rs1 %rd
-+@sh5        ....... ..... .....  ... ..... .......  &shift  shamt=%sh5      %rs1 %rd
-+@sh6        ...... ...... .....  ... ..... .......  &shift shamt=%sh6 %rs1 %rd
- # XTheadBa
- # Instead of defining a new encoding, we simply use the decoder to
-@@ -XXX,XX +XXX,XX @@ th_addsl1        0000001 ..... ..... 001 ..... 0001011 @r
- th_addsl2        0000010 ..... ..... 001 ..... 0001011 @r
- th_addsl3        0000011 ..... ..... 001 ..... 0001011 @r
-+# XTheadBb
-+th_ext           ...... ...... ..... 010 ..... 0001011 @th_bfext
-+th_extu          ...... ...... ..... 011 ..... 0001011 @th_bfext
-+th_ff0           1000010 00000 ..... 001 ..... 0001011 @r2
-+th_ff1           1000011 00000 ..... 001 ..... 0001011 @r2
-+th_srri          000100 ...... ..... 001 ..... 0001011 @sh6
-+th_srriw         0001010 ..... ..... 001 ..... 0001011 @sh5
-+th_rev           1000001 00000 ..... 001 ..... 0001011 @r2
-+th_revw          1001000 00000 ..... 001 ..... 0001011 @r2
-+th_tstnbz        1000000 00000 ..... 001 ..... 0001011 @r2
-+
- # XTheadCmo
- th_dcache_call   0000000 00001 00000 000 00000 0001011
- th_dcache_ciall  0000000 00011 00000 000 00000 0001011
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
-     ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-+    ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb),
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
-     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
-     ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
+ };
-     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
      /* Vendor-specific custom extensions */
      DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
 +    DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/translate.c
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+     const RISCVCPUMultiExtConfig *prop;
- static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
- {
+     /* Enable RVG, RVJ and RVV that are disabled by default */
--    return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
--           ctx->cfg_ptr->ext_xtheadsync;
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
-+    return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
-+           ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
- }
+         isa_ext_update_enabled(cpu, prop->offset, true);
  #define MATERIALISE_EXT_PREDICATE(ext)  \
 diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_xthead.c.inc
 +++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADBB(ctx) do {               \
 +    if (!ctx->cfg_ptr->ext_xtheadbb) {           \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADCMO(ctx) do {              \
      if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ GEN_TRANS_TH_ADDSL(1)
  GEN_TRANS_TH_ADDSL(2)
  GEN_TRANS_TH_ADDSL(3)
 +/* XTheadBb */
 +
 +/* th.srri is an alternate encoding for rori (from Zbb) */
 +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
 +                                   tcg_gen_rotri_tl, gen_roriw, NULL);
 +}
 +
 +/* th.srriw is an alternate encoding for roriw (from Zbb) */
 +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    REQUIRE_64BIT(ctx);
 +    ctx->ol = MXL_RV32;
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
 +}
 +
 +/* th.ext and th.extu perform signed/unsigned bitfield extraction */
 +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a,
 +                             void (*f)(TCGv, TCGv, unsigned int, unsigned int))
 +{
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO);
 +
 +    if (a->lsb <= a->msb) {
 +        f(dest, source, a->lsb, a->msb - a->lsb + 1);
 +        gen_set_gpr(ctx, a->rd, dest);
 +    }
 +    return true;
 +}
 +
 +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl);
 +}
 +
 +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_th_bfextract(ctx, a, tcg_gen_extract_tl);
 +}
 +
 +/* th.ff0: find first zero (clz on an inverted input) */
 +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext)
 +{
 +    TCGv dest = dest_gpr(ctx, a->rd);
 +    TCGv src1 = get_gpr(ctx, a->rs1, ext);
 +
 +    int olen = get_olen(ctx);
 +    TCGv t = tcg_temp_new();
 +
 +    tcg_gen_not_tl(t, src1);
 +    if (olen != TARGET_LONG_BITS) {
 +        if (olen == 32) {
 +            gen_clzw(dest, t);
 +        } else {
 +            g_assert_not_reached();
 +        }
 +    } else {
 +        gen_clz(dest, t);
 +    }
 +
 +    tcg_temp_free(t);
 +    gen_set_gpr(ctx, a->rd, dest);
 +
 +    return true;
 +}
 +
 +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_th_ff0(ctx, a, EXT_NONE);
 +}
 +
 +/* th.ff1 is an alternate encoding for clz (from Zbb) */
 +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
 +}
 +
 +static void gen_th_revw(TCGv ret, TCGv arg1)
 +{
 +    tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS);
 +}
 +
 +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */
 +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +
 +    return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw);
 +}
 +
 +/* th.revw is a sign-extended byte-swap of the lower word */
 +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    REQUIRE_64BIT(ctx);
 +    return gen_unary(ctx, a, EXT_NONE, gen_th_revw);
 +}
 +
 +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */
 +static void gen_th_tstnbz(TCGv ret, TCGv source1)
 +{
 +    gen_orc_b(ret, source1);
 +    tcg_gen_not_tl(ret, ret);
 +}
 +
 +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a)
 +{
 +    REQUIRE_XTHEADBB(ctx);
 +    return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz);
 +}
 +
  /* XTheadCmo */
  static inline int priv_level(DisasContext *ctx)
 --
-.39.1
+.45.1

-[PULL 13/32] hw/riscv: split fdt address calculation from fdt load
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Alistair Francis <alistair23@gmail.com>
-A common trend in other archs is to calculate the fdt address, which is
+When running the instruction
 usually straightforward, and then calling a function that loads the
 fdt/dtb by using that address.
-riscv_load_fdt() is doing a bit too much in comparison. It's calculating
+```
-the fdt address via an elaborated heuristic to put the FDT at the bottom
+    cbo.flush 0(x0)
-of DRAM, and "bottom of DRAM" will vary across boards and
+```
 configurations, then it's actually loading the fdt, and finally it's
 returning the fdt address used to the caller.
-Reduce the existing complexity of riscv_load_fdt() by splitting its code
+QEMU would segfault.
 into a new function, riscv_compute_fdt_addr(), that will take care of
 all fdt address logic. riscv_load_fdt() can then be a simple function
 that just loads a fdt at the given fdt address.
-We're also taken the opportunity to clarify the intentions and
+The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
-assumptions made by these functions. riscv_load_fdt() is now receiving a
+allocated.
 hwaddr as fdt_addr because there is no restriction of having to load the
 fdt in higher addresses that doesn't fit in an uint32_t.
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+In order to fix this let's use the existing get_address()
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+helper. This also has the benefit of performing pointer mask
-Message-Id: <20230201171212.1219375-3-dbarboza@ventanamicro.com>
+calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h    |  4 +++-
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- hw/riscv/boot.c            | 30 +++++++++++++++++++++++++-----
+file changed, 12 insertions(+), 4 deletions(-)
  hw/riscv/microchip_pfsoc.c |  6 ++++--
  hw/riscv/sifive_u.c        |  7 ++++---
  hw/riscv/spike.c           |  6 +++---
  hw/riscv/virt.c            |  7 ++++---
 files changed, 43 insertions(+), 17 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
+@@ -XXX,XX +XXX,XX @@
-                                target_ulong firmware_end_addr,
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
-                                symbol_fn_t sym_cb);
+ {
- void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
+     REQUIRE_ZICBOM(ctx);
--uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-+uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
++    TCGv src = get_address(ctx, a->rs1, 0);
-+                                void *fdt);
++
-+void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
++    gen_helper_cbo_clean_flush(tcg_env, src);
- void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
+     return true;
                                 hwaddr saddr,
                                 hwaddr rom_base, hwaddr rom_size,
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
      }
  }
--uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 +/*
 + * The FDT should be put at the farthest point possible to
 + * avoid overwriting it with the kernel/initrd.
 + *
 + * This function makes an assumption that the DRAM is
 + * contiguous. It also cares about 32-bit systems and
 + * will limit fdt_addr to be addressable by them even for
 + * 64-bit CPUs.
 + *
 + * The FDT is fdt_packed() during the calculation.
 + */
 +uint64_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size,
 +                                void *fdt)
  {
--    uint64_t temp, fdt_addr;
+     REQUIRE_ZICBOM(ctx);
-+    uint64_t temp;
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-     hwaddr dram_end = dram_base + mem_size;
++    TCGv src = get_address(ctx, a->rs1, 0);
      int ret = fdt_pack(fdt);
      int fdtsize;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
       * end of dram or 3GB whichever is lesser.
       */
      temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
 -    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 +
-+    return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
++    gen_helper_cbo_clean_flush(tcg_env, src);
-+}
+     return true;
  }
  static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
  {
      REQUIRE_ZICBOM(ctx);
 -    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
 +    TCGv src = get_address(ctx, a->rs1, 0);
 +
-+/*
++    gen_helper_cbo_inval(tcg_env, src);
-+ * 'fdt_addr' is received as hwaddr because boards might put
+     return true;
 + * the FDT beyond 32-bit addressing boundary.
 + */
 +void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
 +{
 +    uint32_t fdtsize = fdt_totalsize(fdt);
      /* copy in the device tree */
      qemu_fdt_dumpdtb(fdt, fdtsize);
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
                            &address_space_memory);
      qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
                          rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
 -
 -    return fdt_addr;
  }
- void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+ {
-index XXXXXXX..XXXXXXX 100644
+     REQUIRE_ZICBOZ(ctx);
---- a/hw/riscv/microchip_pfsoc.c
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
-+++ b/hw/riscv/microchip_pfsoc.c
++    TCGv src = get_address(ctx, a->rs1, 0);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
          }
          /* Compute the fdt load address in dram */
 -        fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 -                                       machine->ram_size, machine->fdt);
 +        fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 +                                               machine->ram_size, machine->fdt);
 +        riscv_load_fdt(fdt_load_addr, machine->fdt);
 +
-         /* Load the reset vector */
++    gen_helper_cbo_zero(tcg_env, src);
-         riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
+     return true;
-                                   memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
+ }
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
          kernel_entry = 0;
      }
 -    /* Compute the fdt load address in dram */
 -    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
 -                                   machine->ram_size, machine->fdt);
 +    fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
 +                                           machine->ram_size, machine->fdt);
 +    riscv_load_fdt(fdt_load_addr, machine->fdt);
 +
      if (!riscv_is_32bit(&s->soc.u_cpus)) {
          start_addr_hi32 = (uint64_t)start_addr >> 32;
      }
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          kernel_entry = 0;
      }
 -    /* Compute the fdt load address in dram */
 -    fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
 -                                   machine->ram_size, machine->fdt);
 +    fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
 +                                           machine->ram_size, machine->fdt);
 +    riscv_load_fdt(fdt_load_addr, machine->fdt);
      /* load the reset vector */
      riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
          start_addr = virt_memmap[VIRT_FLASH].base;
      }
 -    /* Compute the fdt load address in dram */
 -    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
 -                                   machine->ram_size, machine->fdt);
 +    fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
 +                                           machine->ram_size, machine->fdt);
 +    riscv_load_fdt(fdt_load_addr, machine->fdt);
 +
      /* load the reset vector */
      riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
                                virt_memmap[VIRT_MROM].base,
 --
-.39.1
+.45.1

-[PULL 06/32] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Anup Patel <apatel@ventanamicro.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-The time CSR will wrap-around immediately after reaching UINT64_MAX
+In AIA spec, each hart (or each hart within a group) has a unique hart
-so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
+number to locate the memory pages of interrupt files in the address
-in riscv_timer_write_timecmp().
+space. The number of bits required to represent any hart number is equal
 to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
+However, if the largest hart number among groups is a power of 2, QEMU
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-Message-Id: <20230120125950.2246378-4-apatel@ventanamicro.com>
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
 to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
 Additionally, a Linux patch[1] is necessary to correctly recover the hart
 index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 [1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
 Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/time_helper.c | 24 ++++++++++++++++++++++++
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
-file changed, 24 insertions(+)
+file changed, 8 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/time_helper.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/time_helper.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
-         riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
+         }
      }
-+    /*
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+     * Sstc specification says the following about timer interrupt:
++
-+     * "A supervisor timer interrupt becomes pending - as reflected in
++    if (max_hart_per_socket > 1) {
-+     * the STIP bit in the mip and sip registers - whenever time contains
++        max_hart_per_socket--;
-+     * a value greater than or equal to stimecmp, treating the values
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+     * as unsigned integers. Writes to stimecmp are guaranteed to be
++    } else {
-+     * reflected in STIP eventually, but not necessarily immediately.
++        hart_bits = 0;
 +     * The interrupt remains posted until stimecmp becomes greater
 +     * than time - typically as a result of writing stimecmp."
 +     *
 +     * When timecmp = UINT64_MAX, the time CSR will eventually reach
 +     * timecmp value but on next timer tick the time CSR will wrap-around
 +     * and become zero which is less than UINT64_MAX. Now, the timer
 +     * interrupt behaves like a level triggered interrupt so it will
 +     * become 1 when time = timecmp = UINT64_MAX and next timer tick
 +     * it will become 0 again because time = 0 < timecmp = UINT64_MAX.
 +     *
 +     * Based on above, we don't re-start the QEMU timer when timecmp
 +     * equals UINT64_MAX.
 +     */
 +    if (timecmp == UINT64_MAX) {
 +        return;
 +    }
 +
-     /* otherwise, set up the future timer interrupt */
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-     diff = timecmp - rtc_r;
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-     /* back to ns (note args switched in muldiv64) */
+                             &hart_bits, true, NULL);
 --
-.39.1
+.45.1

-[PULL 10/32] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Follow the QEMU convention of naming MachineState pointers as 'ms' by
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-renaming the instances where we're calling it 'mc'.
+in bytes, when in this context we want 'reg_width' as the length in
 bits.
-Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com>
+Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/spike.c | 18 +++++++++---------
+ target/riscv/gdbstub.c | 6 +++---
-file changed, 9 insertions(+), 9 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/target/riscv/gdbstub.c
-+++ b/hw/riscv/spike.c
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
-     uint64_t addr, size;
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     unsigned long clint_addr;
+ {
-     int cpu, socket;
+     RISCVCPU *cpu = RISCV_CPU(cs);
--    MachineState *mc = MACHINE(s);
+-    int reg_width = cpu->cfg.vlenb;
-+    MachineState *ms = MACHINE(s);
++    int bitsize = cpu->cfg.vlenb << 3;
-     uint32_t *clint_cells;
+     GDBFeatureBuilder builder;
-     uint32_t cpu_phandle, intc_phandle, phandle = 1;
+     int i;
-     char *name, *mem_name, *clint_name, *clust_name;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-         "sifive,clint0", "riscv,clint0"
-     };
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
--    fdt = mc->fdt = create_device_tree(&fdt_size);
+-        int count = reg_width / vec_lanes[i].size;
-+    fdt = ms->fdt = create_device_tree(&fdt_size);
++        int count = bitsize / vec_lanes[i].size;
-     if (!fdt) {
+         gdb_feature_builder_append_tag(
-         error_report("create_device_tree() failed");
+             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-         exit(1);
+             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+     /* Define vector registers */
-     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+     for (i = 0; i < 32; i++) {
+         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
--    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+-                                       reg_width, i, "riscv_vector", "vector");
-+    for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
++                                       bitsize, i, "riscv_vector", "vector");
          clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
          qemu_fdt_add_subnode(fdt, clust_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
              qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
                  s->soc[socket].hartid_base + cpu);
              qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 -            riscv_socket_fdt_write_id(mc, cpu_name, socket);
 +            riscv_socket_fdt_write_id(ms, cpu_name, socket);
              qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
              intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
              g_free(cpu_name);
          }
 -        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
 -        size = riscv_socket_mem_size(mc, socket);
 +        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
 +        size = riscv_socket_mem_size(ms, socket);
          mem_name = g_strdup_printf("/memory@%lx", (long)addr);
          qemu_fdt_add_subnode(fdt, mem_name);
          qemu_fdt_setprop_cells(fdt, mem_name, "reg",
              addr >> 32, addr, size >> 32, size);
          qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
 -        riscv_socket_fdt_write_id(mc, mem_name, socket);
 +        riscv_socket_fdt_write_id(ms, mem_name, socket);
          g_free(mem_name);
          clint_addr = memmap[SPIKE_CLINT].base +
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
          qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
              clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 -        riscv_socket_fdt_write_id(mc, clint_name, socket);
 +        riscv_socket_fdt_write_id(ms, clint_name, socket);
          g_free(clint_name);
          g_free(clint_cells);
          g_free(clust_name);
      }
--    riscv_socket_fdt_write_distance_matrix(mc);
+     gdb_feature_builder_end(&builder);
 +    riscv_socket_fdt_write_distance_matrix(ms);
      qemu_fdt_add_subnode(fdt, "/chosen");
      qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
 --
-.39.1
+.45.1

-[PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Philipp Tomsich <philipp.tomsich@vrull.eu>
+From: Alistair Francis <alistair23@gmail.com>
-The decoding of the following instructions from Zb[abcs] currently
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
-contains decoding/printing errors:
+CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
- * xnor,orn,andn: the rs2 operand is not being printed
+CSRs are part of the disassembly.
  * slli.uw: decodes and prints the immediate shift-amount as a
             register (e.g. 'shift-by-2' becomes 'sp') instead of
         interpreting this as an immediate
-This commit updates the instruction descriptions to use the
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-appropriate decoding/printing formats.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Fixes: ea10325917 ("RISC-V Disassembler")
-Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
+Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- disas/riscv.c | 8 ++++----
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
-file changed, 4 insertions(+), 4 deletions(-)
+file changed, 64 insertions(+), 1 deletion(-)
 diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
 --- a/disas/riscv.c
 +++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+     case 0x0383: return "mibound";
-     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+     case 0x0384: return "mdbase";
-     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+     case 0x0385: return "mdbound";
--    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+-    case 0x03a0: return "pmpcfg3";
--    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03a0: return "pmpcfg0";
--    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03a1: return "pmpcfg1";
-+    { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a2: return "pmpcfg2";
-+    { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a3: return "pmpcfg3";
-+    { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a4: return "pmpcfg4";
-     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a5: return "pmpcfg5";
-     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a6: return "pmpcfg6";
-     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03a7: return "pmpcfg7";
-@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
++    case 0x03a8: return "pmpcfg8";
-     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03a9: return "pmpcfg9";
-     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03aa: return "pmpcfg10";
-     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
++    case 0x03ab: return "pmpcfg11";
--    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ac: return "pmpcfg12";
-+    { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
++    case 0x03ad: return "pmpcfg13";
-     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03ae: return "pmpcfg14";
-     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
++    case 0x03af: return "pmpcfg15";
-     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+     case 0x03b0: return "pmpaddr0";
      case 0x03b1: return "pmpaddr1";
      case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
      case 0x03bd: return "pmpaddr13";
      case 0x03be: return "pmpaddr14";
      case 0x03bf: return "pmpaddr15";
 +    case 0x03c0: return "pmpaddr16";
 +    case 0x03c1: return "pmpaddr17";
 +    case 0x03c2: return "pmpaddr18";
 +    case 0x03c3: return "pmpaddr19";
 +    case 0x03c4: return "pmpaddr20";
 +    case 0x03c5: return "pmpaddr21";
 +    case 0x03c6: return "pmpaddr22";
 +    case 0x03c7: return "pmpaddr23";
 +    case 0x03c8: return "pmpaddr24";
 +    case 0x03c9: return "pmpaddr25";
 +    case 0x03ca: return "pmpaddr26";
 +    case 0x03cb: return "pmpaddr27";
 +    case 0x03cc: return "pmpaddr28";
 +    case 0x03cd: return "pmpaddr29";
 +    case 0x03ce: return "pmpaddr30";
 +    case 0x03cf: return "pmpaddr31";
 +    case 0x03d0: return "pmpaddr32";
 +    case 0x03d1: return "pmpaddr33";
 +    case 0x03d2: return "pmpaddr34";
 +    case 0x03d3: return "pmpaddr35";
 +    case 0x03d4: return "pmpaddr36";
 +    case 0x03d5: return "pmpaddr37";
 +    case 0x03d6: return "pmpaddr38";
 +    case 0x03d7: return "pmpaddr39";
 +    case 0x03d8: return "pmpaddr40";
 +    case 0x03d9: return "pmpaddr41";
 +    case 0x03da: return "pmpaddr42";
 +    case 0x03db: return "pmpaddr43";
 +    case 0x03dc: return "pmpaddr44";
 +    case 0x03dd: return "pmpaddr45";
 +    case 0x03de: return "pmpaddr46";
 +    case 0x03df: return "pmpaddr47";
 +    case 0x03e0: return "pmpaddr48";
 +    case 0x03e1: return "pmpaddr49";
 +    case 0x03e2: return "pmpaddr50";
 +    case 0x03e3: return "pmpaddr51";
 +    case 0x03e4: return "pmpaddr52";
 +    case 0x03e5: return "pmpaddr53";
 +    case 0x03e6: return "pmpaddr54";
 +    case 0x03e7: return "pmpaddr55";
 +    case 0x03e8: return "pmpaddr56";
 +    case 0x03e9: return "pmpaddr57";
 +    case 0x03ea: return "pmpaddr58";
 +    case 0x03eb: return "pmpaddr59";
 +    case 0x03ec: return "pmpaddr60";
 +    case 0x03ed: return "pmpaddr61";
 +    case 0x03ee: return "pmpaddr62";
 +    case 0x03ef: return "pmpaddr63";
      case 0x0780: return "mtohost";
      case 0x0781: return "mfromhost";
      case 0x0782: return "mreset";
 --
-.39.1
+.45.1

-[PULL 02/32] include/hw/riscv/opentitan: update opentitan IRQs
+Deleted patch
-From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Updates the opentitan IRQs to match the latest supported commit of
-Opentitan from TockOS.
-OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
-Memory layout as per [1]
-[1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
-Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/opentitan.h | 14 +++----
- hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
-files changed, 47 insertions(+), 47 deletions(-)
-diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/opentitan.h
-+++ b/include/hw/riscv/opentitan.h
-@@ -XXX,XX +XXX,XX @@ enum {
-     IBEX_DEV_EDNO,
-     IBEX_DEV_EDN1,
-     IBEX_DEV_ALERT_HANDLER,
--    IBEX_DEV_NMI_GEN,
-+    IBEX_DEV_SRAM_CTRL,
-     IBEX_DEV_OTBN,
--    IBEX_DEV_PERI,
-+    IBEX_DEV_IBEX_CFG,
- };
- enum {
-@@ -XXX,XX +XXX,XX @@ enum {
-     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
-     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
-     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
--    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
--    IBEX_SPI_HOST0_ERR_IRQ        = 134,
--    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
--    IBEX_SPI_HOST1_ERR_IRQ        = 136,
--    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
-+    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
-+    IBEX_SPI_HOST0_ERR_IRQ        = 131,
-+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
-+    IBEX_SPI_HOST1_ERR_IRQ        = 133,
-+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
- };
- #endif
-diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/opentitan.c
-+++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@
- /*
-  * This version of the OpenTitan machine currently supports
-  * OpenTitan RTL version:
-- * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
-+ * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
-  *
-  * MMIO mapping as per (specified commit):
-  * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
-  */
- static const MemMapEntry ibex_memmap[] = {
--    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
--    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
--    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
--    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
--    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
--    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
--    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
--    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
--    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
--    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
--    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
--    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
--    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
--    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
--    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
--    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
--    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
--    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
--    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
--    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
--    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
--    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
--    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
--    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
--    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
--    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
--    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
--    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
--    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
--    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
--    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
--    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
--    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
--    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
--    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
-+    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000      },
-+    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000     },
-+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000    },
-+    [IBEX_DEV_UART] =           {  0x40000000,  0x40        },
-+    [IBEX_DEV_GPIO] =           {  0x40040000,  0x40        },
-+    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x2000      },
-+    [IBEX_DEV_I2C] =            {  0x40080000,  0x80        },
-+    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x40        },
-+    [IBEX_DEV_TIMER] =          {  0x40100000,  0x200       },
-+    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x2000      },
-+    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x100       },
-+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x800       },
-+    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x40        },
-+    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x40        },
-+    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000      },
-+    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x80        },
-+    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x80        },
-+    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x80        },
-+    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000      },
-+    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x40        },
-+    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x40        },
-+    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x200       },
-+    [IBEX_DEV_AES] =            {  0x41100000,  0x100       },
-+    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000      },
-+    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000      },
-+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000     },
-+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x100       },
-+    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x80        },
-+    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x100       },
-+    [IBEX_DEV_EDNO] =           {  0x41170000,  0x80        },
-+    [IBEX_DEV_EDN1] =           {  0x41180000,  0x80        },
-+    [IBEX_DEV_SRAM_CTRL] =      {  0x411c0000,  0x20        },
-+    [IBEX_DEV_IBEX_CFG] =       {  0x411f0000,  0x100       },
-+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x8000000   },
-+    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000     },
- };
- static void opentitan_board_init(MachineState *machine)
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
-     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
-         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
--    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
--        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
-+    create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
-+        memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
-     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
-         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
--    create_unimplemented_device("riscv.lowrisc.ibex.peri",
--        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
-+    create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
-+        memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
- }
- static Property lowrisc_ibex_soc_props[] = {
---
-.39.1

-[PULL 03/32] hw/riscv: boot: Don't use CSRs if they are disabled
+Deleted patch
-From: Alistair Francis <alistair.francis@wdc.com>
-If the CSRs and CSR instructions are disabled because the Zicsr
-extension isn't enabled then we want to make sure we don't run any CSR
-instructions in the boot ROM.
-This patches removes the CSR instructions from the reset-vec if the
-extension isn't enabled. We replace the instruction with a NOP instead.
-Note that we don't do this for the SiFive U machine, as we are modelling
-the hardware in that case.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/boot.c | 9 +++++++++
-file changed, 9 insertions(+)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
-         reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
-     }
-+    if (!harts->harts[0].cfg.ext_icsr) {
-+        /*
-+         * The Zicsr extension has been disabled, so let's ensure we don't
-+         * run the CSR instruction. Let's fill the address with a non
-+         * compressed nop.
-+         */
-+        reset_vec[2] = 0x00000013;   /*     addi   x0, x0, 0 */
-+    }
-+
-     /* copy in the reset vector in little_endian byte order */
-     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
-         reset_vec[i] = cpu_to_le32(reset_vec[i]);
---
-.39.1

-[PULL 07/32] target/riscv: Ensure opcode is saved for all relevant instructions
+Deleted patch
-From: Anup Patel <apatel@ventanamicro.com>
-We should call decode_save_opc() for all relevant instructions which
-can potentially generate a virtual instruction fault or a guest page
-fault because generating transformed instruction upon guest page fault
-expects opcode to be available. Without this, hypervisor will see
-transformed instruction as zero in htinst CSR for guest MMIO emulation
-which makes MMIO emulation in hypervisor slow and also breaks nested
-virtualization.
-Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
-Signed-off-by: Anup Patel <apatel@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/insn_trans/trans_rva.c.inc     | 10 +++++++---
- target/riscv/insn_trans/trans_rvd.c.inc     |  2 ++
- target/riscv/insn_trans/trans_rvf.c.inc     |  2 ++
- target/riscv/insn_trans/trans_rvh.c.inc     |  3 +++
- target/riscv/insn_trans/trans_rvi.c.inc     |  2 ++
- target/riscv/insn_trans/trans_rvzfh.c.inc   |  2 ++
- target/riscv/insn_trans/trans_svinval.c.inc |  3 +++
-files changed, 21 insertions(+), 3 deletions(-)
-diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rva.c.inc
-+++ b/target/riscv/insn_trans/trans_rva.c.inc
-@@ -XXX,XX +XXX,XX @@
- static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
- {
--    TCGv src1 = get_address(ctx, a->rs1, 0);
-+    TCGv src1;
-+    decode_save_opc(ctx);
-+    src1 = get_address(ctx, a->rs1, 0);
-     if (a->rl) {
-         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
-     TCGLabel *l1 = gen_new_label();
-     TCGLabel *l2 = gen_new_label();
-+    decode_save_opc(ctx);
-     src1 = get_address(ctx, a->rs1, 0);
-     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
-                     MemOp mop)
- {
-     TCGv dest = dest_gpr(ctx, a->rd);
--    TCGv src1 = get_address(ctx, a->rs1, 0);
--    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-+    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-+    decode_save_opc(ctx);
-+    src1 = get_address(ctx, a->rs1, 0);
-     func(dest, src1, src2, ctx->mem_idx, mop);
-     gen_set_gpr(ctx, a->rd, dest);
-diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvd.c.inc
-+++ b/target/riscv/insn_trans/trans_rvd.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVD);
-+    decode_save_opc(ctx);
-     addr = get_address(ctx, a->rs1, a->imm);
-     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVD);
-+    decode_save_opc(ctx);
-     addr = get_address(ctx, a->rs1, a->imm);
-     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
-     return true;
-diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvf.c.inc
-+++ b/target/riscv/insn_trans/trans_rvf.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVF);
-+    decode_save_opc(ctx);
-     addr = get_address(ctx, a->rs1, a->imm);
-     dest = cpu_fpr[a->rd];
-     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
-     REQUIRE_FPU;
-     REQUIRE_EXT(ctx, RVF);
-+    decode_save_opc(ctx);
-     addr = get_address(ctx, a->rs1, a->imm);
-     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
-     return true;
-diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvh.c.inc
-+++ b/target/riscv/insn_trans/trans_rvh.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
- #ifdef CONFIG_USER_ONLY
-     return false;
- #else
-+    decode_save_opc(ctx);
-     if (check_access(ctx)) {
-         TCGv dest = dest_gpr(ctx, a->rd);
-         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-@@ -XXX,XX +XXX,XX @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
- #ifdef CONFIG_USER_ONLY
-     return false;
- #else
-+    decode_save_opc(ctx);
-     if (check_access(ctx)) {
-         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-         TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
-@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
- static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
-                     void (*func)(TCGv, TCGv_env, TCGv))
- {
-+    decode_save_opc(ctx);
-     if (check_access(ctx)) {
-         TCGv dest = dest_gpr(ctx, a->rd);
-         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
-diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvi.c.inc
-+++ b/target/riscv/insn_trans/trans_rvi.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
- static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
- {
-+    decode_save_opc(ctx);
-     if (get_xl(ctx) == MXL_RV128) {
-         return gen_load_i128(ctx, a, memop);
-     } else {
-@@ -XXX,XX +XXX,XX @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
- static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
- {
-+    decode_save_opc(ctx);
-     if (get_xl(ctx) == MXL_RV128) {
-         return gen_store_i128(ctx, a, memop);
-     } else {
-diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvzfh.c.inc
-+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
-     REQUIRE_FPU;
-     REQUIRE_ZFH_OR_ZFHMIN(ctx);
-+    decode_save_opc(ctx);
-     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
-     if (a->imm) {
-         TCGv temp = temp_new(ctx);
-@@ -XXX,XX +XXX,XX @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
-     REQUIRE_FPU;
-     REQUIRE_ZFH_OR_ZFHMIN(ctx);
-+    decode_save_opc(ctx);
-     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
-     if (a->imm) {
-         TCGv temp = tcg_temp_new();
-diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_svinval.c.inc
-+++ b/target/riscv/insn_trans/trans_svinval.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
-     /* Do the same as sfence.vma currently */
-     REQUIRE_EXT(ctx, RVS);
- #ifndef CONFIG_USER_ONLY
-+    decode_save_opc(ctx);
-     gen_helper_tlb_flush(cpu_env);
-     return true;
- #endif
-@@ -XXX,XX +XXX,XX @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
-     /* Do the same as hfence.vvma currently */
-     REQUIRE_EXT(ctx, RVH);
- #ifndef CONFIG_USER_ONLY
-+    decode_save_opc(ctx);
-     gen_helper_hyp_tlb_flush(cpu_env);
-     return true;
- #endif
-@@ -XXX,XX +XXX,XX @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
-     /* Do the same as hfence.gvma currently */
-     REQUIRE_EXT(ctx, RVH);
- #ifndef CONFIG_USER_ONLY
-+    decode_save_opc(ctx);
-     gen_helper_hyp_gvma_tlb_flush(cpu_env);
-     return true;
- #endif
---
-.39.1

-[PULL 17/32] RISC-V: Adding XTheadBa ISA extension
+Deleted patch
-From: Christoph Müllner <christoph.muellner@vrull.eu>
-This patch adds support for the XTheadBa ISA extension.
-The patch uses the T-Head specific decoder and translation.
-Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
-Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- target/riscv/cpu.h                         |  1 +
- target/riscv/xthead.decode                 | 22 ++++++++++++
- target/riscv/cpu.c                         |  2 ++
- target/riscv/translate.c                   |  3 +-
- target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++
-files changed, 66 insertions(+), 1 deletion(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     uint64_t mimpid;
-     /* Vendor-specific custom extensions */
-+    bool ext_xtheadba;
-     bool ext_xtheadcmo;
-     bool ext_xtheadsync;
-     bool ext_XVentanaCondOps;
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
-+++ b/target/riscv/xthead.decode
-@@ -XXX,XX +XXX,XX @@
- # Translation routines for the instructions of the XThead* ISA extensions
- #
- # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
-+#                    Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
- #
- # SPDX-License-Identifier: LGPL-2.1-or-later
- #
-@@ -XXX,XX +XXX,XX @@
- #   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
- # Fields:
-+%rd        7:5
- %rs1       15:5
- %rs2       20:5
-+# Argument sets
-+&r         rd rs1 rs2                               !extern
-+
- # Formats
- @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
- @rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
-+@r          ....... ..... .....  ... ..... .......  &r %rs2 %rs1 %rd
-+
-+# XTheadBa
-+# Instead of defining a new encoding, we simply use the decoder to
-+# extract the imm[0:1] field and dispatch to separate translation
-+# functions (mirroring the `sh[123]add` instructions from Zba and
-+# the regular RVI `add` instruction.
-+#
-+# The only difference between sh[123]add and addsl is that the shift
-+# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
-+#
-+# Note that shift-by-0 is a valid operation according to the manual.
-+# This will be equivalent to a regular add.
-+add              0000000 ..... ..... 001 ..... 0001011 @r
-+th_addsl1        0000001 ..... ..... 001 ..... 0001011 @r
-+th_addsl2        0000010 ..... ..... 001 ..... 0001011 @r
-+th_addsl3        0000011 ..... ..... 001 ..... 0001011 @r
- # XTheadCmo
- th_dcache_call   0000000 00001 00000 000 00000 0001011
-diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.c
-+++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
-     ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
-     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
-     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
-+    ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
-     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
-     ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
-     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
-     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
-     /* Vendor-specific custom extensions */
-+    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
-     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
-     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
-     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
- static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
- {
--    return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
-+    return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
-+           ctx->cfg_ptr->ext_xtheadsync;
- }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_xthead.c.inc
-+++ b/target/riscv/insn_trans/trans_xthead.c.inc
-@@ -XXX,XX +XXX,XX @@
-  * this program.  If not, see <http://www.gnu.org/licenses/>.
-  */
-+#define REQUIRE_XTHEADBA(ctx) do {               \
-+    if (!ctx->cfg_ptr->ext_xtheadba) {           \
-+        return false;                            \
-+    }                                            \
-+} while (0)
-+
- #define REQUIRE_XTHEADCMO(ctx) do {              \
-     if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
-         return false;                            \
-@@ -XXX,XX +XXX,XX @@
-     }                                            \
- } while (0)
-+/* XTheadBa */
-+
-+/*
-+ * th.addsl is similar to sh[123]add (from Zba), but not an
-+ * alternative encoding: while sh[123] applies the shift to rs1,
-+ * th.addsl shifts rs2.
-+ */
-+
-+#define GEN_TH_ADDSL(SHAMT)                                     \
-+static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
-+{                                                               \
-+    TCGv t = tcg_temp_new();                                    \
-+    tcg_gen_shli_tl(t, arg2, SHAMT);                            \
-+    tcg_gen_add_tl(ret, t, arg1);                               \
-+    tcg_temp_free(t);                                           \
-+}
-+
-+GEN_TH_ADDSL(1)
-+GEN_TH_ADDSL(2)
-+GEN_TH_ADDSL(3)
-+
-+#define GEN_TRANS_TH_ADDSL(SHAMT)                                       \
-+static bool trans_th_addsl##SHAMT(DisasContext *ctx,                    \
-+                                  arg_th_addsl##SHAMT * a)              \
-+{                                                                       \
-+    REQUIRE_XTHEADBA(ctx);                                              \
-+    return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL);      \
-+}
-+
-+GEN_TRANS_TH_ADDSL(1)
-+GEN_TRANS_TH_ADDSL(2)
-+GEN_TRANS_TH_ADDSL(3)
-+
- /* XTheadCmo */
- static inline int priv_level(DisasContext *ctx)
---
-.39.1

-[PULL 21/32] RISC-V: Adding T-Head multiply-accumulate instructions
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Christoph Müllner <christoph.muellner@vrull.eu>
+From: Yu-Ming Chang <yumin686@andestech.com>
-This patch adds support for the T-Head MAC instructions.
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-The patch uses the T-Head specific decoder and translation.
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
 holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
 a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h                         |  1 +
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/xthead.decode                 |  8 +++
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- target/riscv/cpu.c                         |  2 +
+ target/riscv/op_helper.c |  6 ++---
- target/riscv/translate.c                   |  3 +-
+files changed, 53 insertions(+), 8 deletions(-)
  target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++
 files changed, 96 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-     bool ext_xtheadbs;
+ void riscv_cpu_update_mask(CPURISCVState *env);
-     bool ext_xtheadcmo;
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
-     bool ext_xtheadcondmov;
-+    bool ext_xtheadmac;
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-     bool ext_xtheadsync;
++                          target_ulong *ret_value);
-     bool ext_XVentanaCondOps;
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+                            target_ulong *ret_value,
-diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
+                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                            target_ulong new_value,
                                            target_ulong write_mask);
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value);
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/xthead.decode
+--- a/target/riscv/csr.c
-+++ b/target/riscv/xthead.decode
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ th_l2cache_iall  0000000 10110 00000 000 00000 0001011
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
- th_mveqz         0100000 ..... .....  001 ..... 0001011 @r
- th_mvnez         0100001 ..... .....  001 ..... 0001011 @r
+ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+                                                int csrno,
-+# XTheadMac
+-                                               bool write_mask)
-+th_mula          00100 00 ..... ..... 001 ..... 0001011 @r
++                                               bool write)
 +th_mulah         00101 00 ..... ..... 001 ..... 0001011 @r
 +th_mulaw         00100 10 ..... ..... 001 ..... 0001011 @r
 +th_muls          00100 01 ..... ..... 001 ..... 0001011 @r
 +th_mulsh         00101 01 ..... ..... 001 ..... 0001011 @r
 +th_mulsw         00100 11 ..... ..... 001 ..... 0001011 @r
 +
  # XTheadSync
  th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
  th_sync          0000000 11000 00000 000 00000 0001011
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
      ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
      ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
      ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
 +    ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
      ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
      ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
  };
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
      DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
      DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
 +    DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
      DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
      DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
  {
-     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
+     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
-            ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
+     bool read_only = get_field(csrno, 0xC00) == 3;
--           ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync;
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
-+           ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
+     }
-+           ctx->cfg_ptr->ext_xtheadsync;
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
- #define MATERIALISE_EXT_PREDICATE(ext)  \
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
++                           target_ulong *ret_value)
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_xthead.c.inc
 +++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
      }                                            \
  } while (0)
 +#define REQUIRE_XTHEADMAC(ctx) do {              \
 +    if (!ctx->cfg_ptr->ext_xtheadmac) {          \
 +        return false;                            \
 +    }                                            \
 +} while (0)
 +
  #define REQUIRE_XTHEADSYNC(ctx) do {             \
      if (!ctx->cfg_ptr->ext_xtheadsync) {         \
          return false;                            \
@@ -XXX,XX +XXX,XX @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
      return gen_th_condmove(ctx, a, TCG_COND_NE);
  }
 +/* XTheadMac */
 +
 +static bool gen_th_mac(DisasContext *ctx, arg_r *a,
 +                       void (*accumulate_func)(TCGv, TCGv, TCGv),
 +                       void (*extend_operand_func)(TCGv, TCGv))
 +{
-+    TCGv dest = dest_gpr(ctx, a->rd);
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-+    TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE);
++    if (ret != RISCV_EXCP_NONE) {
-+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
++        return ret;
 +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 +    TCGv tmp = tcg_temp_new();
 +
 +    if (extend_operand_func) {
 +        TCGv tmp2 = tcg_temp_new();
 +        extend_operand_func(tmp, src1);
 +        extend_operand_func(tmp2, src2);
 +        tcg_gen_mul_tl(tmp, tmp, tmp2);
 +        tcg_temp_free(tmp2);
 +    } else {
 +        tcg_gen_mul_tl(tmp, src1, src2);
 +    }
 +
-+    accumulate_func(dest, src0, tmp);
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
 +    gen_set_gpr(ctx, a->rd, dest);
 +    tcg_temp_free(tmp);
 +
 +    return true;
 +}
 +
-+/* th.mula: "rd = rd + rs1 * rs2" */
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-+static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a)
+                            target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
-+    REQUIRE_XTHEADMAC(ctx);
++    RISCVException ret;
-+    return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
++
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
 +    if (csr_ops[csrno].read128) {
 +        return riscv_csrrw_do128(env, csrno, ret_value,
 +                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
-+/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
-+static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a)
+                                 Int128 *ret_value,
-+{
+                                 Int128 new_value, Int128 write_mask)
-+    REQUIRE_XTHEADMAC(ctx);
+ {
-+    ctx->ol = MXL_RV32;
+     RISCVException ret;
-+    return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl);
-+}
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
-+
++    ret = riscv_csrrw_check(env, csrno, true);
-+/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */
+     if (ret != RISCV_EXCP_NONE) {
-+static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a)
+         return ret;
-+{
+     }
-+    REQUIRE_XTHEADMAC(ctx);
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-+    REQUIRE_64BIT(ctx);
+index XXXXXXX..XXXXXXX 100644
-+    ctx->ol = MXL_RV32;
+--- a/target/riscv/op_helper.c
-+    return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL);
++++ b/target/riscv/op_helper.c
-+}
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
-+
+     }
-+/* th.muls: "rd = rd - rs1 * rs2" */
-+static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a)
+     target_ulong val = 0;
-+{
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
-+    REQUIRE_XTHEADMAC(ctx);
++    RISCVException ret = riscv_csrr(env, csr, &val);
-+    return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
-+}
+     if (ret != RISCV_EXCP_NONE) {
-+
+         riscv_raise_exception(env, ret, GETPC());
-+/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
-+static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a)
+ target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
-+{
+ {
-+    REQUIRE_XTHEADMAC(ctx);
+     Int128 rv = int128_zero();
-+    ctx->ol = MXL_RV32;
+-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-+    return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl);
+-                                          int128_zero(),
-+}
+-                                          int128_zero());
-+
++    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
-+/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */
-+static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
+     if (ret != RISCV_EXCP_NONE) {
-+{
+         riscv_raise_exception(env, ret, GETPC());
 +    REQUIRE_XTHEADMAC(ctx);
 +    REQUIRE_64BIT(ctx);
 +    ctx->ol = MXL_RV32;
 +    return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
 +}
 +
  /* XTheadSync */
  static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
 --
-.39.1
+.45.1

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:

Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207

for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c:

hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: boot: Don't use CSRs if they are disabled

Anup Patel (4):
      target/riscv: Update VS timer whenever htimedelta changes
      target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
      target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
      target/riscv: Ensure opcode is saved for all relevant instructions

Bin Meng (1):
      hw/riscv: virt: Simplify virt_{get,set}_aclint()

Christoph Müllner (14):
      RISC-V: Adding XTheadCmo ISA extension
      RISC-V: Adding XTheadSync ISA extension
      RISC-V: Adding XTheadBa ISA extension
      RISC-V: Adding XTheadBb ISA extension
      RISC-V: Adding XTheadBs ISA extension
      RISC-V: Adding XTheadCondMov ISA extension
      RISC-V: Adding T-Head multiply-accumulate instructions
      RISC-V: Adding T-Head MemPair extension
      RISC-V: Adding T-Head MemIdx extension
      RISC-V: Adding T-Head FMemIdx extension
      RISC-V: Set minimum priv version for Zfh to 1.11
      RISC-V: Add initial support for T-Head C906
      RISC-V: Adding XTheadFmv ISA extension
      target/riscv: add a MAINTAINERS entry for XThead* extension support

Daniel Henrique Barboza (6):
      hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
      hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
      hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
      hw/riscv/boot.c: calculate fdt size after fdt_pack()
      hw/riscv: split fdt address calculation from fdt load
      hw/riscv: change riscv_compute_fdt_addr() semantics

Deepak Gupta (1):
      target/riscv: fix for virtual instr exception

Philipp Tomsich (1):
      target/riscv: update disas.c for xnor/orn/andn and slli.uw

Sergey Matyukevich (1):
      target/riscv: set tval for triggered watchpoints

Vladimir Isaev (2):
      target/riscv: fix ctzw behavior
      target/riscv: fix SBI getchar handler for KVM

Wilfred Mallawa (1):
      include/hw/riscv/opentitan: update opentitan IRQs

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The decoding of the following instructions from Zb[abcs] currently
contains decoding/printing errors:
 * xnor,orn,andn: the rs2 operand is not being printed
 * slli.uw: decodes and prints the immediate shift-amount as a
            register (e.g. 'shift-by-2' becomes 'sp') instead of
	    interpreting this as an immediate

This commit updates the instruction descriptions to use the
appropriate decoding/printing formats.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "cpop", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "sext.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "sext.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "xnor", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "orn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "andn", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+    { "xnor", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "orn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "andn", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rol", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "ror", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "sh1add", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
     { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
-    { "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
     { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
     { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
-- 
2.39.1

From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.

OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47

Memory layout as per [1]

[1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/opentitan.h | 14 +++----
 hw/riscv/opentitan.c         | 80 ++++++++++++++++++------------------
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_DEV_EDNO,
     IBEX_DEV_EDN1,
     IBEX_DEV_ALERT_HANDLER,
-    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_SRAM_CTRL,
     IBEX_DEV_OTBN,
-    IBEX_DEV_PERI,
+    IBEX_DEV_IBEX_CFG,
 };
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
-    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
-    IBEX_SPI_HOST0_ERR_IRQ        = 134,
-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 135,
-    IBEX_SPI_HOST1_ERR_IRQ        = 136,
-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 137,
+    IBEX_TIMER_TIMEREXPIRED0_0    = 124,
+    IBEX_SPI_HOST0_ERR_IRQ        = 131,
+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 132,
+    IBEX_SPI_HOST1_ERR_IRQ        = 133,
+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 134,
 };
 
 #endif
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@
 /*
  * This version of the OpenTitan machine currently supports
  * OpenTitan RTL version:
- * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
+ * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
  *
  * MMIO mapping as per (specified commit):
  * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
  */
 static const MemMapEntry ibex_memmap[] = {
-    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
-    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
-    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
-    [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
-    [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
-    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
-    [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
-    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
-    [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
-    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
-    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
-    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
-    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
-    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
-    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
-    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
-    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
-    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
-    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
-    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
-    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
-    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
-    [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
-    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
-    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
-    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
-    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
-    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
-    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
-    [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
-    [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
-    [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-    [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
-    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
-    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
+    [IBEX_DEV_ROM] =            {  0x00008000,  0x8000      },
+    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000     },
+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000    },
+    [IBEX_DEV_UART] =           {  0x40000000,  0x40        },
+    [IBEX_DEV_GPIO] =           {  0x40040000,  0x40        },
+    [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x2000      },
+    [IBEX_DEV_I2C] =            {  0x40080000,  0x80        },
+    [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x40        },
+    [IBEX_DEV_TIMER] =          {  0x40100000,  0x200       },
+    [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x2000      },
+    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x100       },
+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x800       },
+    [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x40        },
+    [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x40        },
+    [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000      },
+    [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x80        },
+    [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x80        },
+    [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x80        },
+    [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000      },
+    [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x40        },
+    [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x40        },
+    [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x200       },
+    [IBEX_DEV_AES] =            {  0x41100000,  0x100       },
+    [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000      },
+    [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000      },
+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000     },
+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x100       },
+    [IBEX_DEV_CSRNG] =          {  0x41150000,  0x80        },
+    [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x100       },
+    [IBEX_DEV_EDNO] =           {  0x41170000,  0x80        },
+    [IBEX_DEV_EDN1] =           {  0x41180000,  0x80        },
+    [IBEX_DEV_SRAM_CTRL] =      {  0x411c0000,  0x20        },
+    [IBEX_DEV_IBEX_CFG] =       {  0x411f0000,  0x100       },
+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x8000000   },
+    [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000     },
 };
 
 static void opentitan_board_init(MachineState *machine)
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
-        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
+        memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
-    create_unimplemented_device("riscv.lowrisc.ibex.peri",
-        memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
+        memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
 }
 
 static Property lowrisc_ibex_soc_props[] = {
-- 
2.39.1

From: Alistair Francis <alistair.francis@wdc.com>

If the CSRs and CSR instructions are disabled because the Zicsr
extension isn't enabled then we want to make sure we don't run any CSR
instructions in the boot ROM.

This patches removes the CSR instructions from the reset-vec if the
extension isn't enabled. We replace the instruction with a NOP instead.

Note that we don't do this for the SiFive U machine, as we are modelling
the hardware in that case.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
         reset_vec[4] = 0x0182b283;   /*     ld     t0, 24(t0) */
     }
 
+    if (!harts->harts[0].cfg.ext_icsr) {
+        /*
+         * The Zicsr extension has been disabled, so let's ensure we don't
+         * run the CSR instruction. Let's fill the address with a non
+         * compressed nop.
+         */
+        reset_vec[2] = 0x00000013;   /*     addi   x0, x0, 0 */
+    }
+
     /* copy in the reset vector in little_endian byte order */
     for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
         reset_vec[i] = cpu_to_le32(reset_vec[i]);
-- 
2.39.1

From: Anup Patel <apatel@ventanamicro.com>

The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
                                        target_ulong val)
 {
+    RISCVCPU *cpu = env_archcpu(env);
+
     if (!env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
     } else {
         env->htimedelta = val;
     }
+
+    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+                                  env->htimedelta, MIP_VSTIP);
+    }
+
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
                                         target_ulong val)
 {
+    RISCVCPU *cpu = env_archcpu(env);
+
     if (!env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+
+    if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+        riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+                                  env->htimedelta, MIP_VSTIP);
+    }
+
     return RISCV_EXCP_NONE;
 }
 
-- 
2.39.1

From: Anup Patel <apatel@ventanamicro.com>

Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c  |  2 --
 target/riscv/time_helper.c | 12 ++++++++----
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
         vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
     }
 
-    /* No need to update mip for VSTIP */
-    mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask;
     vstip = env->vstime_irq ? MIP_VSTIP : 0;
 
     QEMU_IOTHREAD_LOCK_GUARD();
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -XXX,XX +XXX,XX @@ static void riscv_vstimer_cb(void *opaque)
     RISCVCPU *cpu = opaque;
     CPURISCVState *env = &cpu->env;
     env->vstime_irq = 1;
-    riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1));
+    riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
 }
 
 static void riscv_stimer_cb(void *opaque)
@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
          */
         if (timer_irq == MIP_VSTIP) {
             env->vstime_irq = 1;
+            riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1));
+        } else {
+            riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1));
         }
-        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1));
         return;
     }
 
+    /* Clear the [VS|S]TIP bit in mip */
     if (timer_irq == MIP_VSTIP) {
         env->vstime_irq = 0;
+        riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0));
+    } else {
+        riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
     }
-    /* Clear the [V]STIP bit in mip */
-    riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
 
     /* otherwise, set up the future timer interrupt */
     diff = timecmp - rtc_r;
-- 
2.39.1

From: Anup Patel <apatel@ventanamicro.com>

The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-4-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/time_helper.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer,
         riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0));
     }
 
+    /*
+     * Sstc specification says the following about timer interrupt:
+     * "A supervisor timer interrupt becomes pending - as reflected in
+     * the STIP bit in the mip and sip registers - whenever time contains
+     * a value greater than or equal to stimecmp, treating the values
+     * as unsigned integers. Writes to stimecmp are guaranteed to be
+     * reflected in STIP eventually, but not necessarily immediately.
+     * The interrupt remains posted until stimecmp becomes greater
+     * than time - typically as a result of writing stimecmp."
+     *
+     * When timecmp = UINT64_MAX, the time CSR will eventually reach
+     * timecmp value but on next timer tick the time CSR will wrap-around
+     * and become zero which is less than UINT64_MAX. Now, the timer
+     * interrupt behaves like a level triggered interrupt so it will
+     * become 1 when time = timecmp = UINT64_MAX and next timer tick
+     * it will become 0 again because time = 0 < timecmp = UINT64_MAX.
+     *
+     * Based on above, we don't re-start the QEMU timer when timecmp
+     * equals UINT64_MAX.
+     */
+    if (timecmp == UINT64_MAX) {
+        return;
+    }
+
     /* otherwise, set up the future timer interrupt */
     diff = timecmp - rtc_r;
     /* back to ns (note args switched in muldiv64) */
-- 
2.39.1

From: Anup Patel <apatel@ventanamicro.com>

We should call decode_save_opc() for all relevant instructions which
can potentially generate a virtual instruction fault or a guest page
fault because generating transformed instruction upon guest page fault
expects opcode to be available. Without this, hypervisor will see
transformed instruction as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.

Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rva.c.inc     | 10 +++++++---
 target/riscv/insn_trans/trans_rvd.c.inc     |  2 ++
 target/riscv/insn_trans/trans_rvf.c.inc     |  2 ++
 target/riscv/insn_trans/trans_rvh.c.inc     |  3 +++
 target/riscv/insn_trans/trans_rvi.c.inc     |  2 ++
 target/riscv/insn_trans/trans_rvzfh.c.inc   |  2 ++
 target/riscv/insn_trans/trans_svinval.c.inc |  3 +++
 7 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -XXX,XX +XXX,XX @@
 
 static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
 {
-    TCGv src1 = get_address(ctx, a->rs1, 0);
+    TCGv src1;
 
+    decode_save_opc(ctx);
+    src1 = get_address(ctx, a->rs1, 0);
     if (a->rl) {
         tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
     }
@@ -XXX,XX +XXX,XX @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
     TCGLabel *l1 = gen_new_label();
     TCGLabel *l2 = gen_new_label();
 
+    decode_save_opc(ctx);
     src1 = get_address(ctx, a->rs1, 0);
     tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
 
@@ -XXX,XX +XXX,XX @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
                     MemOp mop)
 {
     TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv src1 = get_address(ctx, a->rs1, 0);
-    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+    TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE);
 
+    decode_save_opc(ctx);
+    src1 = get_address(ctx, a->rs1, 0);
     func(dest, src1, src2, ctx->mem_idx, mop);
 
     gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+    decode_save_opc(ctx);
     addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
+    decode_save_opc(ctx);
     addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
     return true;
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
+    decode_save_opc(ctx);
     addr = get_address(ctx, a->rs1, a->imm);
     dest = cpu_fpr[a->rd];
     tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
+    decode_save_opc(ctx);
     addr = get_address(ctx, a->rs1, a->imm);
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
     return true;
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop)
 #ifdef CONFIG_USER_ONLY
     return false;
 #else
+    decode_save_opc(ctx);
     if (check_access(ctx)) {
         TCGv dest = dest_gpr(ctx, a->rd);
         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop)
 #ifdef CONFIG_USER_ONLY
     return false;
 #else
+    decode_save_opc(ctx);
     if (check_access(ctx)) {
         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
         TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 static bool do_hlvx(DisasContext *ctx, arg_r2 *a,
                     void (*func)(TCGv, TCGv_env, TCGv))
 {
+    decode_save_opc(ctx);
     if (check_access(ctx)) {
         TCGv dest = dest_gpr(ctx, a->rd);
         TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
 
 static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
 {
+    decode_save_opc(ctx);
     if (get_xl(ctx) == MXL_RV128) {
         return gen_load_i128(ctx, a, memop);
     } else {
@@ -XXX,XX +XXX,XX @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
 
 static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
 {
+    decode_save_opc(ctx);
     if (get_xl(ctx) == MXL_RV128) {
         return gen_store_i128(ctx, a, memop);
     } else {
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
     REQUIRE_FPU;
     REQUIRE_ZFH_OR_ZFHMIN(ctx);
 
+    decode_save_opc(ctx);
     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
     if (a->imm) {
         TCGv temp = temp_new(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
     REQUIRE_FPU;
     REQUIRE_ZFH_OR_ZFHMIN(ctx);
 
+    decode_save_opc(ctx);
     t0 = get_gpr(ctx, a->rs1, EXT_NONE);
     if (a->imm) {
         TCGv temp = tcg_temp_new();
diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_svinval.c.inc
+++ b/target/riscv/insn_trans/trans_svinval.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a)
     /* Do the same as sfence.vma currently */
     REQUIRE_EXT(ctx, RVS);
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_tlb_flush(cpu_env);
     return true;
 #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a)
     /* Do the same as hfence.vvma currently */
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_hyp_tlb_flush(cpu_env);
     return true;
 #endif
@@ -XXX,XX +XXX,XX @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a)
     /* Do the same as hfence.gvma currently */
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
+    decode_save_opc(ctx);
     gen_helper_hyp_gvma_tlb_flush(cpu_env);
     return true;
 #endif
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_socket_count() returns either ms->numa_state->num_nodes or 1
depending on NUMA support. In any case the value can be retrieved only
once and used in the rest of the function.

This will also alleviate the rename we're going to do next by reducing
the instances of MachineState 'mc' inside hw/riscv/virt.c.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     int cpu, socket;
     char *imsic_name;
     MachineState *mc = MACHINE(s);
+    int socket_count = riscv_socket_count(mc);
     uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
     uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
 
     *msi_m_phandle = (*phandle)++;
     *msi_s_phandle = (*phandle)++;
     imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
-    imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
+    imsic_regs = g_new0(uint32_t, socket_count * 4);
 
     /* M-level IMSIC node */
     for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
         imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
     }
     imsic_max_hart_per_socket = 0;
-    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+    for (socket = 0; socket < socket_count; socket++) {
         imsic_addr = memmap[VIRT_IMSIC_M].base +
                      socket * VIRT_IMSIC_GROUP_MAX_SIZE;
         imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
         imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
     qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
-        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+        socket_count * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
-    if (riscv_socket_count(mc) > 1) {
+    if (socket_count > 1) {
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
             imsic_num_bits(imsic_max_hart_per_socket));
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
-            imsic_num_bits(riscv_socket_count(mc)));
+            imsic_num_bits(socket_count));
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
             IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     }
     imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
     imsic_max_hart_per_socket = 0;
-    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+    for (socket = 0; socket < socket_count; socket++) {
         imsic_addr = memmap[VIRT_IMSIC_S].base +
                      socket * VIRT_IMSIC_GROUP_MAX_SIZE;
         imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
         imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
     qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
-        riscv_socket_count(mc) * sizeof(uint32_t) * 4);
+        socket_count * sizeof(uint32_t) * 4);
     qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
     if (imsic_guest_bits) {
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
             imsic_guest_bits);
     }
-    if (riscv_socket_count(mc) > 1) {
+    if (socket_count > 1) {
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
             imsic_num_bits(imsic_max_hart_per_socket));
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
-            imsic_num_bits(riscv_socket_count(mc)));
+            imsic_num_bits(socket_count));
         qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
             IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
     MachineState *mc = MACHINE(s);
     uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
     uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
+    int socket_count = riscv_socket_count(mc);
 
     qemu_fdt_add_subnode(mc->fdt, "/cpus");
     qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
     intc_phandles = g_new0(uint32_t, mc->smp.cpus);
 
     phandle_pos = mc->smp.cpus;
-    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+    for (socket = (socket_count - 1); socket >= 0; socket--) {
         phandle_pos -= s->soc[socket].num_harts;
 
         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
     }
 
     phandle_pos = mc->smp.cpus;
-    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+    for (socket = (socket_count - 1); socket >= 0; socket--) {
         phandle_pos -= s->soc[socket].num_harts;
 
         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 
     g_free(intc_phandles);
 
-    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+    for (socket = 0; socket < socket_count; socket++) {
         if (socket == 0) {
             *irq_mmio_phandle = xplic_phandles[socket];
             *irq_virtio_phandle = xplic_phandles[socket];
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
 
     /* Pass seed to RNG */
     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
-    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed",
+                     rng_seed, sizeof(rng_seed));
 }
 
 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     char *soc_name;
     DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
     int i, base_hartid, hart_count;
+    int socket_count = riscv_socket_count(machine);
 
     /* Check socket count limit */
-    if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
+    if (VIRT_SOCKETS_MAX < socket_count) {
         error_report("number of sockets/nodes should be less than %d",
             VIRT_SOCKETS_MAX);
         exit(1);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
 
     /* Initialize sockets */
     mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
-    for (i = 0; i < riscv_socket_count(machine); i++) {
+    for (i = 0; i < socket_count; i++) {
         if (!riscv_socket_check_hartids(machine, i)) {
             error_report("discontinuous hartids in socket%d", i);
             exit(1);
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We have a convention in other QEMU boards/archs to name MachineState
pointers as either 'machine' or 'ms'. MachineClass pointers are usually
called 'mc'.

The 'virt' RISC-V machine has a lot of instances where MachineState
pointers are named 'mc'. There is nothing wrong with that, but we gain
more compatibility with the rest of the QEMU code base, and easier
reviews, if we follow QEMU conventions.

Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious
and mechanical patch that was produced by doing the following:

- find/replace all 'MachineState *mc' to 'MachineState *ms';
- find/replace all 'mc->fdt' to 'ms->fdt';
- find/replace all 'mc->smp.cpus' to 'ms->smp.cpus';
- replace any remaining occurrences of 'mc' that the compiler complained
about.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------
 1 file changed, 217 insertions(+), 217 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
 {
     int cpu;
     uint32_t cpu_phandle;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     char *name, *cpu_name, *core_name, *intc_name;
     bool is_32_bit = riscv_is_32bit(&s->soc[0]);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
 
         cpu_name = g_strdup_printf("/cpus/cpu@%d",
             s->soc[socket].hartid_base + cpu);
-        qemu_fdt_add_subnode(mc->fdt, cpu_name);
+        qemu_fdt_add_subnode(ms->fdt, cpu_name);
         if (riscv_feature(&s->soc[socket].harts[cpu].env,
                           RISCV_FEATURE_MMU)) {
-            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+            qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
         } else {
-            qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
+            qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     "riscv,none");
         }
         name = riscv_isa_string(&s->soc[socket].harts[cpu]);
-        qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
+        qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
         g_free(name);
-        qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
-        qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
-        qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
+        qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
+        qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay");
+        qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg",
             s->soc[socket].hartid_base + cpu);
-        qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
-        riscv_socket_fdt_write_id(mc, cpu_name, socket);
-        qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
+        qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu");
+        riscv_socket_fdt_write_id(ms, cpu_name, socket);
+        qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle);
 
         intc_phandles[cpu] = (*phandle)++;
 
         intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
-        qemu_fdt_add_subnode(mc->fdt, intc_name);
-        qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
+        qemu_fdt_add_subnode(ms->fdt, intc_name);
+        qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle",
             intc_phandles[cpu]);
-        qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+        qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible",
             "riscv,cpu-intc");
-        qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
-        qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
+        qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1);
 
         core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
-        qemu_fdt_add_subnode(mc->fdt, core_name);
-        qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
+        qemu_fdt_add_subnode(ms->fdt, core_name);
+        qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle);
 
         g_free(core_name);
         g_free(intc_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_memory(RISCVVirtState *s,
 {
     char *mem_name;
     uint64_t addr, size;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
-    addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
-    size = riscv_socket_mem_size(mc, socket);
+    addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket);
+    size = riscv_socket_mem_size(ms, socket);
     mem_name = g_strdup_printf("/memory@%lx", (long)addr);
-    qemu_fdt_add_subnode(mc->fdt, mem_name);
-    qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
+    qemu_fdt_add_subnode(ms->fdt, mem_name);
+    qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
         addr >> 32, addr, size >> 32, size);
-    qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
-    riscv_socket_fdt_write_id(mc, mem_name, socket);
+    qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
+    riscv_socket_fdt_write_id(ms, mem_name, socket);
     g_free(mem_name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
     char *clint_name;
     uint32_t *clint_cells;
     unsigned long clint_addr;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     static const char * const clint_compat[2] = {
         "sifive,clint0", "riscv,clint0"
     };
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
 
     clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
     clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
-    qemu_fdt_add_subnode(mc->fdt, clint_name);
-    qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
+    qemu_fdt_add_subnode(ms->fdt, clint_name);
+    qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
                                   (char **)&clint_compat,
                                   ARRAY_SIZE(clint_compat));
-    qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
         0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
-    qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+    qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
         clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-    riscv_socket_fdt_write_id(mc, clint_name, socket);
+    riscv_socket_fdt_write_id(ms, clint_name, socket);
     g_free(clint_name);
 
     g_free(clint_cells);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
     uint32_t *aclint_mswi_cells;
     uint32_t *aclint_sswi_cells;
     uint32_t *aclint_mtimer_cells;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
     aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
     if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
         addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
         name = g_strdup_printf("/soc/mswi@%lx", addr);
-        qemu_fdt_add_subnode(mc->fdt, name);
-        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+        qemu_fdt_add_subnode(ms->fdt, name);
+        qemu_fdt_setprop_string(ms->fdt, name, "compatible",
             "riscv,aclint-mswi");
-        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
             0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
-        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+        qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
             aclint_mswi_cells, aclint_cells_size);
-        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
-        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-        riscv_socket_fdt_write_id(mc, name, socket);
+        qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+        riscv_socket_fdt_write_id(ms, name, socket);
         g_free(name);
     }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
         size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
     }
     name = g_strdup_printf("/soc/mtimer@%lx", addr);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
         "riscv,aclint-mtimer");
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
         0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
         0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
         0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
         0x0, RISCV_ACLINT_DEFAULT_MTIME);
-    qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+    qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
         aclint_mtimer_cells, aclint_cells_size);
-    riscv_socket_fdt_write_id(mc, name, socket);
+    riscv_socket_fdt_write_id(ms, name, socket);
     g_free(name);
 
     if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
         addr = memmap[VIRT_ACLINT_SSWI].base +
             (memmap[VIRT_ACLINT_SSWI].size * socket);
         name = g_strdup_printf("/soc/sswi@%lx", addr);
-        qemu_fdt_add_subnode(mc->fdt, name);
-        qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+        qemu_fdt_add_subnode(ms->fdt, name);
+        qemu_fdt_setprop_string(ms->fdt, name, "compatible",
             "riscv,aclint-sswi");
-        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
             0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
-        qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
+        qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
             aclint_sswi_cells, aclint_cells_size);
-        qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
-        qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-        riscv_socket_fdt_write_id(mc, name, socket);
+        qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0);
+        riscv_socket_fdt_write_id(ms, name, socket);
         g_free(name);
     }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     char *plic_name;
     uint32_t *plic_cells;
     unsigned long plic_addr;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     static const char * const plic_compat[2] = {
         "sifive,plic-1.0.0", "riscv,plic0"
     };
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
     plic_phandles[socket] = (*phandle)++;
     plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
     plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
-    qemu_fdt_add_subnode(mc->fdt, plic_name);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name,
+    qemu_fdt_add_subnode(ms->fdt, plic_name);
+    qemu_fdt_setprop_cell(ms->fdt, plic_name,
         "#interrupt-cells", FDT_PLIC_INT_CELLS);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name,
+    qemu_fdt_setprop_cell(ms->fdt, plic_name,
         "#address-cells", FDT_PLIC_ADDR_CELLS);
-    qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
+    qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible",
                                   (char **)&plic_compat,
                                   ARRAY_SIZE(plic_compat));
-    qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
+    qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended",
         plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-    qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
         0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+    qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
                           VIRT_IRQCHIP_NUM_SOURCES - 1);
-    riscv_socket_fdt_write_id(mc, plic_name, socket);
-    qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
+    riscv_socket_fdt_write_id(ms, plic_name, socket);
+    qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle",
         plic_phandles[socket]);
 
     if (!socket) {
-        platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
+        platform_bus_add_all_fdt_nodes(ms->fdt, plic_name,
                                        memmap[VIRT_PLATFORM_BUS].base,
                                        memmap[VIRT_PLATFORM_BUS].size,
                                        VIRT_PLATFORM_BUS_IRQ);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
 {
     int cpu, socket;
     char *imsic_name;
-    MachineState *mc = MACHINE(s);
-    int socket_count = riscv_socket_count(mc);
+    MachineState *ms = MACHINE(s);
+    int socket_count = riscv_socket_count(ms);
     uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
     uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
 
     *msi_m_phandle = (*phandle)++;
     *msi_s_phandle = (*phandle)++;
-    imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
+    imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
     imsic_regs = g_new0(uint32_t, socket_count * 4);
 
     /* M-level IMSIC node */
-    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
         imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     }
     imsic_name = g_strdup_printf("/soc/imsics@%lx",
         (unsigned long)memmap[VIRT_IMSIC_M].base);
-    qemu_fdt_add_subnode(mc->fdt, imsic_name);
-    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+    qemu_fdt_add_subnode(ms->fdt, imsic_name);
+    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
         "riscv,imsics");
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
         FDT_IMSIC_INT_CELLS);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
         NULL, 0);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
         NULL, 0);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
-        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
         socket_count * sizeof(uint32_t) * 4);
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
     if (socket_count > 1) {
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
             imsic_num_bits(imsic_max_hart_per_socket));
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
             imsic_num_bits(socket_count));
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
             IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle);
 
     g_free(imsic_name);
 
     /* S-level IMSIC node */
-    for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
+    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
         imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
         imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
     }
     imsic_name = g_strdup_printf("/soc/imsics@%lx",
         (unsigned long)memmap[VIRT_IMSIC_S].base);
-    qemu_fdt_add_subnode(mc->fdt, imsic_name);
-    qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
+    qemu_fdt_add_subnode(ms->fdt, imsic_name);
+    qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible",
         "riscv,imsics");
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells",
         FDT_IMSIC_INT_CELLS);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
+    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller",
         NULL, 0);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
+    qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
         NULL, 0);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
-        imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
-    qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
+    qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
+        imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
+    qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
         socket_count * sizeof(uint32_t) * 4);
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
         VIRT_IRQCHIP_NUM_MSIS);
     if (imsic_guest_bits) {
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits",
             imsic_guest_bits);
     }
     if (socket_count > 1) {
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits",
             imsic_num_bits(imsic_max_hart_per_socket));
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits",
             imsic_num_bits(socket_count));
-        qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
+        qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift",
             IMSIC_MMIO_GROUP_MIN_SHIFT);
     }
-    qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle);
     g_free(imsic_name);
 
     g_free(imsic_regs);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     char *aplic_name;
     uint32_t *aplic_cells;
     unsigned long aplic_addr;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     uint32_t aplic_m_phandle, aplic_s_phandle;
 
     aplic_m_phandle = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     aplic_addr = memmap[VIRT_APLIC_M].base +
                  (memmap[VIRT_APLIC_M].size * socket);
     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
-    qemu_fdt_add_subnode(mc->fdt, aplic_name);
-    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+    qemu_fdt_add_subnode(ms->fdt, aplic_name);
+    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
         "#interrupt-cells", FDT_APLIC_INT_CELLS);
-    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
     if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
-        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
             aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
     } else {
-        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
             msi_m_phandle);
     }
-    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
         0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
         VIRT_IRQCHIP_NUM_SOURCES);
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children",
         aplic_s_phandle);
-    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
+    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate",
         aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
-    riscv_socket_fdt_write_id(mc, aplic_name, socket);
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
+    riscv_socket_fdt_write_id(ms, aplic_name, socket);
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle);
     g_free(aplic_name);
 
     /* S-level APLIC node */
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
     aplic_addr = memmap[VIRT_APLIC_S].base +
                  (memmap[VIRT_APLIC_S].size * socket);
     aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
-    qemu_fdt_add_subnode(mc->fdt, aplic_name);
-    qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name,
+    qemu_fdt_add_subnode(ms->fdt, aplic_name);
+    qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic");
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name,
         "#interrupt-cells", FDT_APLIC_INT_CELLS);
-    qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0);
     if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
-        qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
+        qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended",
             aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
     } else {
-        qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
+        qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent",
             msi_s_phandle);
     }
-    qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
         0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
         VIRT_IRQCHIP_NUM_SOURCES);
-    riscv_socket_fdt_write_id(mc, aplic_name, socket);
-    qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
+    riscv_socket_fdt_write_id(ms, aplic_name, socket);
+    qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle);
 
     if (!socket) {
-        platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
+        platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name,
                                        memmap[VIRT_PLATFORM_BUS].base,
                                        memmap[VIRT_PLATFORM_BUS].size,
                                        VIRT_PLATFORM_BUS_IRQ);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
 static void create_fdt_pmu(RISCVVirtState *s)
 {
     char *pmu_name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     RISCVCPU hart = s->soc[0].harts[0];
 
     pmu_name = g_strdup_printf("/soc/pmu");
-    qemu_fdt_add_subnode(mc->fdt, pmu_name);
-    qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
-    riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
+    qemu_fdt_add_subnode(ms->fdt, pmu_name);
+    qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu");
+    riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name);
 
     g_free(pmu_name);
 }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 {
     char *clust_name;
     int socket, phandle_pos;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
     uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
-    int socket_count = riscv_socket_count(mc);
+    int socket_count = riscv_socket_count(ms);
 
-    qemu_fdt_add_subnode(mc->fdt, "/cpus");
-    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
+    qemu_fdt_add_subnode(ms->fdt, "/cpus");
+    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency",
                           RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
-    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
-    qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
-    qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
+    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
+    qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
 
-    intc_phandles = g_new0(uint32_t, mc->smp.cpus);
+    intc_phandles = g_new0(uint32_t, ms->smp.cpus);
 
-    phandle_pos = mc->smp.cpus;
+    phandle_pos = ms->smp.cpus;
     for (socket = (socket_count - 1); socket >= 0; socket--) {
         phandle_pos -= s->soc[socket].num_harts;
 
         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
-        qemu_fdt_add_subnode(mc->fdt, clust_name);
+        qemu_fdt_add_subnode(ms->fdt, clust_name);
 
         create_fdt_socket_cpus(s, socket, clust_name, phandle,
                                &intc_phandles[phandle_pos]);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         *msi_pcie_phandle = msi_s_phandle;
     }
 
-    phandle_pos = mc->smp.cpus;
+    phandle_pos = ms->smp.cpus;
     for (socket = (socket_count - 1); socket >= 0; socket--) {
         phandle_pos -= s->soc[socket].num_harts;
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         }
     }
 
-    riscv_socket_fdt_write_distance_matrix(mc);
+    riscv_socket_fdt_write_distance_matrix(ms);
 }
 
 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
 {
     int i;
     char *name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     for (i = 0; i < VIRTIO_COUNT; i++) {
         name = g_strdup_printf("/soc/virtio_mmio@%lx",
             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
-        qemu_fdt_add_subnode(mc->fdt, name);
-        qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
-        qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+        qemu_fdt_add_subnode(ms->fdt, name);
+        qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
+        qemu_fdt_setprop_cells(ms->fdt, name, "reg",
             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
             0x0, memmap[VIRT_VIRTIO].size);
-        qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
             irq_virtio_phandle);
         if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-            qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
+            qemu_fdt_setprop_cell(ms->fdt, name, "interrupts",
                                   VIRTIO_IRQ + i);
         } else {
-            qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
+            qemu_fdt_setprop_cells(ms->fdt, name, "interrupts",
                                    VIRTIO_IRQ + i, 0x4);
         }
         g_free(name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
                             uint32_t msi_pcie_phandle)
 {
     char *name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     name = g_strdup_printf("/soc/pci@%lx",
         (long) memmap[VIRT_PCIE_ECAM].base);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells",
         FDT_PCI_ADDR_CELLS);
-    qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
+    qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells",
         FDT_PCI_INT_CELLS);
-    qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+    qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
         "pci-host-ecam-generic");
-    qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
-    qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
-    qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
+    qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci");
+    qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0);
+    qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0,
         memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
-    qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0);
     if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
-        qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
+        qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
     }
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
+    qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
         memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
-    qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
         1, FDT_PCI_RANGE_IOPORT, 2, 0,
         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
         1, FDT_PCI_RANGE_MMIO,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
         2, virt_high_pcie_memmap.base,
         2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
 
-    create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
+    create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
     g_free(name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
 {
     char *name;
     uint32_t test_phandle;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     test_phandle = (*phandle)++;
     name = g_strdup_printf("/soc/test@%lx",
         (long)memmap[VIRT_TEST].base);
-    qemu_fdt_add_subnode(mc->fdt, name);
+    qemu_fdt_add_subnode(ms->fdt, name);
     {
         static const char * const compat[3] = {
             "sifive,test1", "sifive,test0", "syscon"
         };
-        qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
+        qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
                                       (char **)&compat, ARRAY_SIZE(compat));
     }
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
         0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
-    qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
-    test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
+    qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
+    test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
     g_free(name);
 
     name = g_strdup_printf("/reboot");
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
-    qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
-    qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
-    qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot");
+    qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+    qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET);
     g_free(name);
 
     name = g_strdup_printf("/poweroff");
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
-    qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
-    qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
-    qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff");
+    qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0);
+    qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS);
     g_free(name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
                             uint32_t irq_mmio_phandle)
 {
     char *name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
         0x0, memmap[VIRT_UART0].base,
         0x0, memmap[VIRT_UART0].size);
-    qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
-    qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
+    qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
+    qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ);
     } else {
-        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
+        qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4);
     }
 
-    qemu_fdt_add_subnode(mc->fdt, "/chosen");
-    qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
+    qemu_fdt_add_subnode(ms->fdt, "/chosen");
+    qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name);
     g_free(name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
                            uint32_t irq_mmio_phandle)
 {
     char *name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
 
     name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible",
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible",
         "google,goldfish-rtc");
-    qemu_fdt_setprop_cells(mc->fdt, name, "reg",
+    qemu_fdt_setprop_cells(ms->fdt, name, "reg",
         0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
-    qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
+    qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
         irq_mmio_phandle);
     if (s->aia_type == VIRT_AIA_TYPE_NONE) {
-        qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
+        qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ);
     } else {
-        qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
+        qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4);
     }
     g_free(name);
 }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
 {
     char *name;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 
     name = g_strdup_printf("/flash@%" PRIx64, flashbase);
-    qemu_fdt_add_subnode(mc->fdt, name);
-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
-    qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
+    qemu_fdt_add_subnode(ms->fdt, name);
+    qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash");
+    qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
                                  2, flashbase, 2, flashsize,
                                  2, flashbase + flashsize, 2, flashsize);
-    qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
+    qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4);
     g_free(name);
 }
 
 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
 {
     char *nodename;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     hwaddr base = memmap[VIRT_FW_CFG].base;
     hwaddr size = memmap[VIRT_FW_CFG].size;
 
     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
-    qemu_fdt_add_subnode(mc->fdt, nodename);
-    qemu_fdt_setprop_string(mc->fdt, nodename,
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_string(ms->fdt, nodename,
                             "compatible", "qemu,fw-cfg-mmio");
-    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
                                  2, base, 2, size);
-    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
     g_free(nodename);
 }
 
 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
 {
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
     uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
     uint8_t rng_seed[32];
 
-    if (mc->dtb) {
-        mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
-        if (!mc->fdt) {
+    if (ms->dtb) {
+        ms->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+        if (!ms->fdt) {
             error_report("load_device_tree() failed");
             exit(1);
         }
     } else {
-        mc->fdt = create_device_tree(&s->fdt_size);
-        if (!mc->fdt) {
+        ms->fdt = create_device_tree(&s->fdt_size);
+        if (!ms->fdt) {
             error_report("create_device_tree() failed");
             exit(1);
         }
     }
 
-    qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
-    qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
-    qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
-    qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
+    qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu");
+    qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio");
+    qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
+    qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
 
-    qemu_fdt_add_subnode(mc->fdt, "/soc");
-    qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
-    qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
-    qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
-    qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
+    qemu_fdt_add_subnode(ms->fdt, "/soc");
+    qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0);
+    qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus");
+    qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2);
+    qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2);
 
     create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
                        &irq_pcie_phandle, &irq_virtio_phandle,
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
 
     /* Pass seed to RNG */
     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
-    qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed",
+    qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed",
                      rng_seed, sizeof(rng_seed));
 }
 
@@ -XXX,XX +XXX,XX @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
-static FWCfgState *create_fw_cfg(const MachineState *mc)
+static FWCfgState *create_fw_cfg(const MachineState *ms)
 {
     hwaddr base = virt_memmap[VIRT_FW_CFG].base;
     FWCfgState *fw_cfg;
 
     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
                                   &address_space_memory);
-    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
 
     return fw_cfg;
 }
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instances where we're calling it 'mc'.

Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     uint64_t addr, size;
     unsigned long clint_addr;
     int cpu, socket;
-    MachineState *mc = MACHINE(s);
+    MachineState *ms = MACHINE(s);
     uint32_t *clint_cells;
     uint32_t cpu_phandle, intc_phandle, phandle = 1;
     char *name, *mem_name, *clint_name, *clust_name;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
         "sifive,clint0", "riscv,clint0"
     };
 
-    fdt = mc->fdt = create_device_tree(&fdt_size);
+    fdt = ms->fdt = create_device_tree(&fdt_size);
     if (!fdt) {
         error_report("create_device_tree() failed");
         exit(1);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 
-    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+    for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) {
         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
         qemu_fdt_add_subnode(fdt, clust_name);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
                 s->soc[socket].hartid_base + cpu);
             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
-            riscv_socket_fdt_write_id(mc, cpu_name, socket);
+            riscv_socket_fdt_write_id(ms, cpu_name, socket);
             qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 
             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             g_free(cpu_name);
         }
 
-        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
-        size = riscv_socket_mem_size(mc, socket);
+        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket);
+        size = riscv_socket_mem_size(ms, socket);
         mem_name = g_strdup_printf("/memory@%lx", (long)addr);
         qemu_fdt_add_subnode(fdt, mem_name);
         qemu_fdt_setprop_cells(fdt, mem_name, "reg",
             addr >> 32, addr, size >> 32, size);
         qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
-        riscv_socket_fdt_write_id(mc, mem_name, socket);
+        riscv_socket_fdt_write_id(ms, mem_name, socket);
         g_free(mem_name);
 
         clint_addr = memmap[SPIKE_CLINT].base +
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-        riscv_socket_fdt_write_id(mc, clint_name, socket);
+        riscv_socket_fdt_write_id(ms, clint_name, socket);
 
         g_free(clint_name);
         g_free(clint_cells);
         g_free(clust_name);
     }
 
-    riscv_socket_fdt_write_distance_matrix(mc);
+    riscv_socket_fdt_write_distance_matrix(ms);
 
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-- 
2.39.1

From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 6 ++++++
 target/riscv/debug.c      | 1 -
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
             tval = env->bins;
             break;
+        case RISCV_EXCP_BREAKPOINT:
+            if (cs->watchpoint_hit) {
+                tval = cs->watchpoint_hit->hitaddr;
+                cs->watchpoint_hit = NULL;
+            }
+            break;
         default:
             break;
         }
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs)
 
     if (cs->watchpoint_hit) {
         if (cs->watchpoint_hit->flags & BP_CPU) {
-            cs->watchpoint_hit = NULL;
             do_trigger_action(env, DBG_ACTION_BP);
         }
     } else {
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

fdt_pack() can change the fdt size, meaning that fdt_totalsize() can
contain a now deprecated (bigger) value.

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
 {
     uint64_t temp, fdt_addr;
     hwaddr dram_end = dram_base + mem_size;
-    int ret, fdtsize = fdt_totalsize(fdt);
+    int ret = fdt_pack(fdt);
+    int fdtsize;
 
+    /* Should only fail if we've built a corrupted tree */
+    g_assert(ret == 0);
+
+    fdtsize = fdt_totalsize(fdt);
     if (fdtsize <= 0) {
         error_report("invalid device-tree");
         exit(1);
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
     temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
     fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 
-    ret = fdt_pack(fdt);
-    /* Should only fail if we've built a corrupted tree */
-    g_assert(ret == 0);
     /* copy in the device tree */
     qemu_fdt_dumpdtb(fdt, fdtsize);
 
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

A common trend in other archs is to calculate the fdt address, which is
usually straightforward, and then calling a function that loads the
fdt/dtb by using that address.

riscv_load_fdt() is doing a bit too much in comparison. It's calculating
the fdt address via an elaborated heuristic to put the FDT at the bottom
of DRAM, and "bottom of DRAM" will vary across boards and
configurations, then it's actually loading the fdt, and finally it's
returning the fdt address used to the caller.

Reduce the existing complexity of riscv_load_fdt() by splitting its code
into a new function, riscv_compute_fdt_addr(), that will take care of
all fdt address logic. riscv_load_fdt() can then be a simple function
that just loads a fdt at the given fdt address.

We're also taken the opportunity to clarify the intentions and
assumptions made by these functions. riscv_load_fdt() is now receiving a
hwaddr as fdt_addr because there is no restriction of having to load the
fdt in higher addresses that doesn't fit in an uint32_t.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230201171212.1219375-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    |  4 +++-
 hw/riscv/boot.c            | 30 +++++++++++++++++++++++++-----
 hw/riscv/microchip_pfsoc.c |  6 ++++--
 hw/riscv/sifive_u.c        |  7 ++++---
 hw/riscv/spike.c           |  6 +++---
 hw/riscv/virt.c            |  7 ++++---
 6 files changed, 43 insertions(+), 17 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
                                target_ulong firmware_end_addr,
                                symbol_fn_t sym_cb);
 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
-uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
+uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
+                                void *fdt);
+void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                hwaddr saddr,
                                hwaddr rom_base, hwaddr rom_size,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     }
 }
 
-uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+/*
+ * The FDT should be put at the farthest point possible to
+ * avoid overwriting it with the kernel/initrd.
+ *
+ * This function makes an assumption that the DRAM is
+ * contiguous. It also cares about 32-bit systems and
+ * will limit fdt_addr to be addressable by them even for
+ * 64-bit CPUs.
+ *
+ * The FDT is fdt_packed() during the calculation.
+ */
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size,
+                                void *fdt)
 {
-    uint64_t temp, fdt_addr;
+    uint64_t temp;
     hwaddr dram_end = dram_base + mem_size;
     int ret = fdt_pack(fdt);
     int fdtsize;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
      * end of dram or 3GB whichever is lesser.
      */
     temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
-    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+
+    return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+}
+
+/*
+ * 'fdt_addr' is received as hwaddr because boards might put
+ * the FDT beyond 32-bit addressing boundary.
+ */
+void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
+{
+    uint32_t fdtsize = fdt_totalsize(fdt);
 
     /* copy in the device tree */
     qemu_fdt_dumpdtb(fdt, fdtsize);
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
                           &address_space_memory);
     qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
                         rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
-
-    return fdt_addr;
 }
 
 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
         }
 
         /* Compute the fdt load address in dram */
-        fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-                                       machine->ram_size, machine->fdt);
+        fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+                                               machine->ram_size, machine->fdt);
+        riscv_load_fdt(fdt_load_addr, machine->fdt);
+
         /* Load the reset vector */
         riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
                                   memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         kernel_entry = 0;
     }
 
-    /* Compute the fdt load address in dram */
-    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
-                                   machine->ram_size, machine->fdt);
+    fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
+                                           machine->ram_size, machine->fdt);
+    riscv_load_fdt(fdt_load_addr, machine->fdt);
+
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
         start_addr_hi32 = (uint64_t)start_addr >> 32;
     }
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = 0;
     }
 
-    /* Compute the fdt load address in dram */
-    fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
-                                   machine->ram_size, machine->fdt);
+    fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
+                                           machine->ram_size, machine->fdt);
+    riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
     riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
-    /* Compute the fdt load address in dram */
-    fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
-                                   machine->ram_size, machine->fdt);
+    fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
+                                           machine->ram_size, machine->fdt);
+    riscv_load_fdt(fdt_load_addr, machine->fdt);
+
     /* load the reset vector */
     riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
                               virt_memmap[VIRT_MROM].base,
-- 
2.39.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and the FDT pointer. And it makes a very important assumption: the DRAM
interval dram_base + mem_size is contiguous. This is indeed the case for
most boards that use a FDT.

The Icicle Kit board works with 2 distinct RAM banks that are separated
by a gap. We have a lower bank with 1GiB size, a gap follows, then at
64GiB the high memory starts. MachineClass::default_ram_size for this
board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM
size, meaning that there we'll always have at least 512 MiB in the Hi
RAM area.

Using riscv_compute_fdt_addr() in this board is weird because not only
the board has sparse RAM, and it's calling it using the base address of
the Lo RAM area, but it's also using a mem_size that we have guarantees
that it will go up to the Hi RAM. All the function assumptions doesn't
work for this board.

In fact, what makes the function works at all in this case is a
coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT,
down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For
the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000
(2 Gb) and it has a 1Gb size, so it will fall in the conditions to put
the FDT under a 3Gb address, which happens to be exactly at the end of
DRAM_LO. If the base address of the Lo area started later than 3Gb this
function would be unusable by the board. Changing any assumptions inside
riscv_compute_fdt_addr() can also break it by accident as well.

Let's change riscv_compute_fdt_addr() semantics to be appropriate to the
Icicle Kit board and for future boards that might have sparse RAM
topologies to worry about:

- relieve the condition that the dram_base + mem_size area is contiguous,
since this is already not the case today;

- receive an extra 'dram_size' size attribute that refers to a contiguous
RAM block that the board wants the FDT to reside on.

Together with 'mem_size' and 'fdt', which are now now being consumed by a
MachineState pointer, we're able to make clear assumptions based on the
DRAM block and total mem_size available to ensure that the FDT will be put
in a valid RAM address.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230201171212.1219375-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    |  2 +-
 hw/riscv/boot.c            | 35 +++++++++++++++++++++++------------
 hw/riscv/microchip_pfsoc.c |  3 ++-
 hw/riscv/sifive_u.c        |  3 ++-
 hw/riscv/spike.c           |  3 ++-
 hw/riscv/virt.c            |  3 ++-
 6 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
                                symbol_fn_t sym_cb);
 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
 uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
-                                void *fdt);
+                                MachineState *ms);
 void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
 }
 
 /*
- * The FDT should be put at the farthest point possible to
- * avoid overwriting it with the kernel/initrd.
+ * This function makes an assumption that the DRAM interval
+ * 'dram_base' + 'dram_size' is contiguous.
  *
- * This function makes an assumption that the DRAM is
- * contiguous. It also cares about 32-bit systems and
- * will limit fdt_addr to be addressable by them even for
- * 64-bit CPUs.
+ * Considering that 'dram_end' is the lowest value between
+ * the end of the DRAM block and MachineState->ram_size, the
+ * FDT location will vary according to 'dram_base':
+ *
+ * - if 'dram_base' is less that 3072 MiB, the FDT will be
+ * put at the lowest value between 3072 MiB and 'dram_end';
+ *
+ * - if 'dram_base' is higher than 3072 MiB, the FDT will be
+ * put at 'dram_end'.
  *
  * The FDT is fdt_packed() during the calculation.
  */
-uint64_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size,
-                                void *fdt)
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
+                                MachineState *ms)
 {
-    uint64_t temp;
-    hwaddr dram_end = dram_base + mem_size;
-    int ret = fdt_pack(fdt);
+    int ret = fdt_pack(ms->fdt);
+    hwaddr dram_end, temp;
     int fdtsize;
 
     /* Should only fail if we've built a corrupted tree */
     g_assert(ret == 0);
 
-    fdtsize = fdt_totalsize(fdt);
+    fdtsize = fdt_totalsize(ms->fdt);
     if (fdtsize <= 0) {
         error_report("invalid device-tree");
         exit(1);
     }
 
+    /*
+     * A dram_size == 0, usually from a MemMapEntry[].size element,
+     * means that the DRAM block goes all the way to ms->ram_size.
+     */
+    dram_end = dram_base;
+    dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size;
+
     /*
      * We should put fdt as far as possible to avoid kernel/initrd overwriting
      * its content. But it should be addressable by 32 bit system as well.
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
 
         /* Compute the fdt load address in dram */
         fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-                                               machine->ram_size, machine->fdt);
+                                               memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+                                               machine);
         riscv_load_fdt(fdt_load_addr, machine->fdt);
 
         /* Load the reset vector */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     }
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
-                                           machine->ram_size, machine->fdt);
+                                           memmap[SIFIVE_U_DEV_DRAM].size,
+                                           machine);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     }
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
-                                           machine->ram_size, machine->fdt);
+                                           memmap[SPIKE_DRAM].size,
+                                           machine);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
     }
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
-                                           machine->ram_size, machine->fdt);
+                                           memmap[VIRT_DRAM].size,
+                                           machine);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.

The implementation does not have much functionality (besides accepting
the instructions and not qualifying them as illegal instructions if
the hart executes in the required privilege level for the instruction),
as QEMU does not model CPU caches and instructions are documented
to not raise any exceptions.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 | 38 ++++++++++
 target/riscv/cpu.c                         |  2 +
 target/riscv/translate.c                   |  8 +++
 target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++
 target/riscv/meson.build                   |  1 +
 6 files changed, 131 insertions(+)
 create mode 100644 target/riscv/xthead.decode
 create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     uint64_t mimpid;
 
     /* Vendor-specific custom extensions */
+    bool ext_xtheadcmo;
     bool ext_XVentanaCondOps;
 
     uint8_t pmu_num;
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
+#
+# Translation routines for the instructions of the XThead* ISA extensions
+#
+# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# The documentation of the ISA extensions can be found here:
+#   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
+
+# Fields:
+%rs1       15:5
+
+# Formats
+@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
+
+# XTheadCmo
+th_dcache_call   0000000 00001 00000 000 00000 0001011
+th_dcache_ciall  0000000 00011 00000 000 00000 0001011
+th_dcache_iall   0000000 00010 00000 000 00000 0001011
+th_dcache_cpa    0000001 01001 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cipa   0000001 01011 ..... 000 00000 0001011 @sfence_vm
+th_dcache_ipa    0000001 01010 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cva    0000001 00101 ..... 000 00000 0001011 @sfence_vm
+th_dcache_civa   0000001 00111 ..... 000 00000 0001011 @sfence_vm
+th_dcache_iva    0000001 00110 ..... 000 00000 0001011 @sfence_vm
+th_dcache_csw    0000001 00001 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cisw   0000001 00011 ..... 000 00000 0001011 @sfence_vm
+th_dcache_isw    0000001 00010 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cpal1  0000001 01000 ..... 000 00000 0001011 @sfence_vm
+th_dcache_cval1  0000001 00100 ..... 000 00000 0001011 @sfence_vm
+th_icache_iall   0000000 10000 00000 000 00000 0001011
+th_icache_ialls  0000000 10001 00000 000 00000 0001011
+th_icache_ipa    0000001 11000 ..... 000 00000 0001011 @sfence_vm
+th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
+th_l2cache_call  0000000 10101 00000 000 00000 0001011
+th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
+th_l2cache_iall  0000000 10110 00000 000 00000 0001011
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+    ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 
     /* Vendor-specific custom extensions */
+    DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
     /* These are experimental so mark with 'x-' */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
     return true;
 }
 
+static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
+{
+    return ctx->cfg_ptr->ext_xtheadcmo;
+}
+
 #define MATERIALISE_EXT_PREDICATE(ext)  \
     static bool has_ ## ext ## _p(DisasContext *ctx)    \
     { \
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 #include "insn_trans/trans_rvk.c.inc"
 #include "insn_trans/trans_privileged.c.inc"
 #include "insn_trans/trans_svinval.c.inc"
+#include "decode-xthead.c.inc"
+#include "insn_trans/trans_xthead.c.inc"
 #include "insn_trans/trans_xventanacondops.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         bool (*decode_func)(DisasContext *, uint32_t);
     } decoders[] = {
         { always_true_p,  decode_insn32 },
+        { has_xthead_p, decode_xthead },
         { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
     };
 
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
+/*
+ * RISC-V translation routines for the T-Head vendor extensions (xthead*).
+ *
+ * Copyright (c) 2022 VRULL GmbH.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_XTHEADCMO(ctx) do {              \
+    if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
+        return false;                            \
+    }                                            \
+} while (0)
+
+/* XTheadCmo */
+
+static inline int priv_level(DisasContext *ctx)
+{
+#ifdef CONFIG_USER_ONLY
+    return PRV_U;
+#else
+     /* Priv level is part of mem_idx. */
+    return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK;
+#endif
+}
+
+/* Test if priv level is M, S, or U (cannot fail). */
+#define REQUIRE_PRIV_MSU(ctx)
+
+/* Test if priv level is M or S. */
+#define REQUIRE_PRIV_MS(ctx)                                    \
+do {                                                            \
+    int priv = priv_level(ctx);                                 \
+    if (!(priv == PRV_M ||                                      \
+          priv == PRV_S)) {                                     \
+        return false;                                           \
+    }                                                           \
+} while (0)
+
+#define NOP_PRIVCHECK(insn, extcheck, privcheck)                \
+static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \
+{                                                               \
+    (void) a;                                                   \
+    extcheck(ctx);                                              \
+    privcheck(ctx);                                             \
+    return true;                                                \
+}
+
+NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+
+NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
+
+NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 gen = [
   decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
   decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
+  decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),
   decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
 ]
 
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.

The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/helper.h                      |  1 +
 target/riscv/xthead.decode                 |  9 +++
 target/riscv/cpu.c                         |  2 +
 target/riscv/op_helper.c                   |  6 ++
 target/riscv/translate.c                   |  2 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++
 7 files changed, 105 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
 
     /* Vendor-specific custom extensions */
     bool ext_xtheadcmo;
+    bool ext_xtheadsync;
     bool ext_XVentanaCondOps;
 
     uint8_t pmu_num;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
+DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
 DEF_HELPER_1(itrigger_match, void, env)
 #endif
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
 
 # Fields:
 %rs1       15:5
+%rs2       20:5
 
 # Formats
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
+@rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
 
 # XTheadCmo
 th_dcache_call   0000000 00001 00000 000 00000 0001011
@@ -XXX,XX +XXX,XX @@ th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
 th_l2cache_call  0000000 10101 00000 000 00000 0001011
 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
 th_l2cache_iall  0000000 10110 00000 000 00000 0001011
+
+# XTheadSync
+th_sfence_vmas   0000010 ..... ..... 000 00000 0001011 @rs2_s
+th_sync          0000000 11000 00000 000 00000 0001011
+th_sync_i        0000000 11010 00000 000 00000 0001011
+th_sync_is       0000000 11011 00000 000 00000 0001011
+th_sync_s        0000000 11001 00000 000 00000 0001011
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
+    ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
 };
 
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
 
     /* Vendor-specific custom extensions */
     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+    DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
     /* These are experimental so mark with 'x-' */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
     }
 }
 
+void helper_tlb_flush_all(CPURISCVState *env)
+{
+    CPUState *cs = env_cpu(env);
+    tlb_flush_all_cpus_synced(cs);
+}
+
 void helper_hyp_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
 
 static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
 {
-    return ctx->cfg_ptr->ext_xtheadcmo;
+    return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
 }
 
 #define MATERIALISE_EXT_PREDICATE(ext)  \
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_XTHEADSYNC(ctx) do {             \
+    if (!ctx->cfg_ptr->ext_xtheadsync) {         \
+        return false;                            \
+    }                                            \
+} while (0)
+
 /* XTheadCmo */
 
 static inline int priv_level(DisasContext *ctx)
@@ -XXX,XX +XXX,XX @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU)
 NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
 NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS)
+
+/* XTheadSync */
+
+static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a)
+{
+    (void) a;
+    REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+    REQUIRE_PRIV_MS(ctx);
+    gen_helper_tlb_flush_all(cpu_env);
+    return true;
+#else
+    return false;
+#endif
+}
+
+#ifndef CONFIG_USER_ONLY
+static void gen_th_sync_local(DisasContext *ctx)
+{
+    /*
+     * Emulate out-of-order barriers with pipeline flush
+     * by exiting the translation block.
+     */
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    tcg_gen_exit_tb(NULL, 0);
+    ctx->base.is_jmp = DISAS_NORETURN;
+}
+#endif
+
+static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a)
+{
+    (void) a;
+    REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+    REQUIRE_PRIV_MSU(ctx);
+
+    /*
+     * th.sync is an out-of-order barrier.
+     */
+    gen_th_sync_local(ctx);
+
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a)
+{
+    (void) a;
+    REQUIRE_XTHEADSYNC(ctx);
+
+#ifndef CONFIG_USER_ONLY
+    REQUIRE_PRIV_MSU(ctx);
+
+    /*
+     * th.sync.i is th.sync plus pipeline flush.
+     */
+    gen_th_sync_local(ctx);
+
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a)
+{
+    /* This instruction has the same behaviour like th.sync.i. */
+    return trans_th_sync_i(ctx, a);
+}
+
+static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a)
+{
+    /* This instruction has the same behaviour like th.sync. */
+    return trans_th_sync(ctx, a);
+}
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 | 22 ++++++++++++
 target/riscv/cpu.c                         |  2 ++
 target/riscv/translate.c                   |  3 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++
 5 files changed, 66 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     uint64_t mimpid;
 
     /* Vendor-specific custom extensions */
+    bool ext_xtheadba;
     bool ext_xtheadcmo;
     bool ext_xtheadsync;
     bool ext_XVentanaCondOps;
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
 # Translation routines for the instructions of the XThead* ISA extensions
 #
 # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
+#                    Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
 #
 # SPDX-License-Identifier: LGPL-2.1-or-later
 #
@@ -XXX,XX +XXX,XX @@
 #   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
 
 # Fields:
+%rd        7:5
 %rs1       15:5
 %rs2       20:5
 
+# Argument sets
+&r         rd rs1 rs2                               !extern
+
 # Formats
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
 @rs2_s      ....... ..... ..... ... ..... .......   %rs2 %rs1
+@r          ....... ..... .....  ... ..... .......  &r %rs2 %rs1 %rd
+
+# XTheadBa
+# Instead of defining a new encoding, we simply use the decoder to
+# extract the imm[0:1] field and dispatch to separate translation
+# functions (mirroring the `sh[123]add` instructions from Zba and
+# the regular RVI `add` instruction.
+#
+# The only difference between sh[123]add and addsl is that the shift
+# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
+#
+# Note that shift-by-0 is a valid operation according to the manual.
+# This will be equivalent to a regular add.
+add              0000000 ..... ..... 001 ..... 0001011 @r
+th_addsl1        0000001 ..... ..... 001 ..... 0001011 @r
+th_addsl2        0000010 ..... ..... 001 ..... 0001011 @r
+th_addsl3        0000011 ..... ..... 001 ..... 0001011 @r
 
 # XTheadCmo
 th_dcache_call   0000000 00001 00000 000 00000 0001011
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
     ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
     ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+    ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
     ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
 
     /* Vendor-specific custom extensions */
+    DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
 
 static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
 {
-    return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+    return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
+           ctx->cfg_ptr->ext_xtheadsync;
 }
 
 #define MATERIALISE_EXT_PREDICATE(ext)  \
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#define REQUIRE_XTHEADBA(ctx) do {               \
+    if (!ctx->cfg_ptr->ext_xtheadba) {           \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_XTHEADCMO(ctx) do {              \
     if (!ctx->cfg_ptr->ext_xtheadcmo) {          \
         return false;                            \
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+/* XTheadBa */
+
+/*
+ * th.addsl is similar to sh[123]add (from Zba), but not an
+ * alternative encoding: while sh[123] applies the shift to rs1,
+ * th.addsl shifts rs2.
+ */
+
+#define GEN_TH_ADDSL(SHAMT)                                     \
+static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
+{                                                               \
+    TCGv t = tcg_temp_new();                                    \
+    tcg_gen_shli_tl(t, arg2, SHAMT);                            \
+    tcg_gen_add_tl(ret, t, arg1);                               \
+    tcg_temp_free(t);                                           \
+}
+
+GEN_TH_ADDSL(1)
+GEN_TH_ADDSL(2)
+GEN_TH_ADDSL(3)
+
+#define GEN_TRANS_TH_ADDSL(SHAMT)                                       \
+static bool trans_th_addsl##SHAMT(DisasContext *ctx,                    \
+                                  arg_th_addsl##SHAMT * a)              \
+{                                                                       \
+    REQUIRE_XTHEADBA(ctx);                                              \
+    return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL);      \
+}
+
+GEN_TRANS_TH_ADDSL(1)
+GEN_TRANS_TH_ADDSL(2)
+GEN_TRANS_TH_ADDSL(3)
+
 /* XTheadCmo */
 
 static inline int priv_level(DisasContext *ctx)
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBb ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |   1 +
 target/riscv/xthead.decode                 |  20 ++++
 target/riscv/cpu.c                         |   2 +
 target/riscv/translate.c                   |   4 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++
 5 files changed, 149 insertions(+), 2 deletions(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 |  3 +++
 target/riscv/cpu.c                         |  2 ++
 target/riscv/translate.c                   |  3 ++-
 target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++
 5 files changed, 23 insertions(+), 1 deletion(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 |  4 +++
 target/riscv/cpu.c                         |  2 ++
 target/riscv/translate.c                   |  2 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++
 5 files changed, 43 insertions(+), 1 deletion(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 |  8 +++
 target/riscv/cpu.c                         |  2 +
 target/riscv/translate.c                   |  3 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++
 5 files changed, 96 insertions(+), 1 deletion(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 | 13 +++
 target/riscv/cpu.c                         |  2 +
 target/riscv/translate.c                   |  2 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++
 5 files changed, 109 insertions(+), 1 deletion(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |   1 +
 target/riscv/xthead.decode                 |  54 +++
 target/riscv/cpu.c                         |   2 +
 target/riscv/translate.c                   |  21 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 387 +++++++++++++++++++++
 5 files changed, 464 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_xtheadcmo;
     bool ext_xtheadcondmov;
     bool ext_xtheadmac;
+    bool ext_xtheadmemidx;
     bool ext_xtheadmempair;
     bool ext_xtheadsync;
     bool ext_XVentanaCondOps;
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -XXX,XX +XXX,XX @@
 %rd2       20:5
 %rs2       20:5
 %sh5       20:5
+%imm5      20:s5
 %sh6       20:6
 %sh2       25:2
+%imm2      25:2
 
 # Argument sets
 &r         rd rs1 rs2                               !extern
@@ -XXX,XX +XXX,XX @@
 &shift     shamt rs1 rd                             !extern
 &th_bfext  msb lsb rs1 rd
 &th_pair   rd1 rs rd2 sh2
+&th_memidx rd rs1 rs2 imm2
+&th_meminc rd rs1 imm5 imm2
 
 # Formats
 @sfence_vm  ....... ..... .....   ... ..... ....... %rs1
@@ -XXX,XX +XXX,XX @@
 @sh5        ....... ..... .....  ... ..... .......  &shift  shamt=%sh5      %rs1 %rd
 @sh6        ...... ...... .....  ... ..... .......  &shift shamt=%sh6 %rs1 %rd
 @th_pair    ..... .. ..... ..... ... ..... .......  &th_pair %rd1 %rs %rd2 %sh2
+@th_memidx  ..... .. ..... ..... ... ..... .......  &th_memidx %rd %rs1 %rs2 %imm2
+@th_meminc  ..... .. ..... ..... ... ..... .......  &th_meminc %rd %rs1 %imm5 %imm2
 
 # XTheadBa
 # Instead of defining a new encoding, we simply use the decoder to
@@ -XXX,XX +XXX,XX @@ th_muls          00100 01 ..... ..... 001 ..... 0001011 @r
 th_mulsh         00101 01 ..... ..... 001 ..... 0001011 @r
 th_mulsw         00100 11 ..... ..... 001 ..... 0001011 @r
 
+# XTheadMemIdx
+th_ldia          01111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_ldib          01101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwia          01011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwib          01001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwuia         11011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lwuib         11001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhia          00111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhib          00101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhuia         10111 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lhuib         10101 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbia          00011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbib          00001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbuia         10011 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_lbuib         10001 .. ..... ..... 100 ..... 0001011 @th_meminc
+th_sdia          01111 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sdib          01101 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_swia          01011 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_swib          01001 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_shia          00111 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_shib          00101 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sbia          00011 .. ..... ..... 101 ..... 0001011 @th_meminc
+th_sbib          00001 .. ..... ..... 101 ..... 0001011 @th_meminc
+
+th_lrd           01100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrw           01000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrwu          11000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrh           00100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrhu          10100 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrb           00000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lrbu          10000 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_srd           01100 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srw           01000 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srh           00100 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_srb           00000 .. ..... ..... 101 ..... 0001011 @th_memidx
+
+th_lurd          01110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurw          01010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurwu         11010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurh          00110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurhu         10110 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurb          00010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_lurbu         10010 .. ..... ..... 100 ..... 0001011 @th_memidx
+th_surd          01110 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surw          01010 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surh          00110 .. ..... ..... 101 ..... 0001011 @th_memidx
+th_surb          00010 .. ..... ..... 101 ..... 0001011 @th_memidx
+
 # XTheadMemPair
 th_ldd           11111 .. ..... ..... 100 ..... 0001011 @th_pair
 th_lwd           11100 .. ..... ..... 100 ..... 0001011 @th_pair
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
     ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
     ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
+    ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
     ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
     ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
     ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
     DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
     DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
+    DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
     DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
            ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
            ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
-           ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
+           ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
+           ctx->cfg_ptr->ext_xtheadsync;
 }
 
 #define MATERIALISE_EXT_PREDICATE(ext)  \
@@ -XXX,XX +XXX,XX @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     return addr;
 }
 
+/* Compute a canonical address from a register plus reg offset. */
+static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
+{
+    TCGv addr = temp_new(ctx);
+    TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
+
+    tcg_gen_add_tl(addr, src1, offs);
+    if (ctx->pm_mask_enabled) {
+        tcg_gen_andc_tl(addr, addr, pm_mask);
+    } else if (get_xl(ctx) == MXL_RV32) {
+        tcg_gen_ext32u_tl(addr, addr);
+    }
+    if (ctx->pm_base_enabled) {
+        tcg_gen_or_tl(addr, addr, pm_base);
+    }
+    return addr;
+}
+
 #ifndef CONFIG_USER_ONLY
 /* The states of mstatus_fs are:
  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+#define REQUIRE_XTHEADMEMIDX(ctx) do {           \
+    if (!ctx->cfg_ptr->ext_xtheadmemidx) {       \
+        return false;                            \
+    }                                            \
+} while (0)
+
 #define REQUIRE_XTHEADMEMPAIR(ctx) do {          \
     if (!ctx->cfg_ptr->ext_xtheadmempair) {      \
         return false;                            \
@@ -XXX,XX +XXX,XX @@
     }                                            \
 } while (0)
 
+/*
+ * Calculate and return the address for indexed mem operations:
+ * If !zext_offs, then the address is rs1 + (rs2 << imm2).
+ * If  zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2,
+                                   int imm2, bool zext_offs)
+{
+    TCGv src2 = get_gpr(ctx, rs2, EXT_NONE);
+    TCGv offs = tcg_temp_new();
+
+    if (zext_offs) {
+        tcg_gen_extract_tl(offs, src2, 0, 32);
+        tcg_gen_shli_tl(offs, offs, imm2);
+    } else {
+        tcg_gen_shli_tl(offs, src2, imm2);
+    }
+
+    TCGv addr = get_address_indexed(ctx, rs1, offs);
+
+    tcg_temp_free(offs);
+    return addr;
+}
+
 /* XTheadBa */
 
 /*
@@ -XXX,XX +XXX,XX @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a)
     return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL);
 }
 
+/* XTheadMemIdx */
+
+/*
+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the load address is rs1.
+ * If  preinc, then the load address is rs1 + (imm5) << imm2).
+ */
+static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
+                         bool preinc)
+{
+    if (a->rs1 == a->rd) {
+        return false;
+    }
+
+    int imm = a->imm5 << a->imm2;
+    TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
+    TCGv rd = dest_gpr(ctx, a->rd);
+    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
+    tcg_gen_addi_tl(rs1, rs1, imm);
+    gen_set_gpr(ctx, a->rd, rd);
+    gen_set_gpr(ctx, a->rs1, rs1);
+
+    tcg_temp_free(addr);
+    return true;
+}
+
+/*
+ * Store with memop to indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the store address is rs1.
+ * If  preinc, then the store address is rs1 + (imm5) << imm2).
+ */
+static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop,
+                          bool preinc)
+{
+    int imm = a->imm5 << a->imm2;
+    TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0);
+    TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
+    TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+    tcg_gen_addi_tl(rs1, rs1, imm);
+    gen_set_gpr(ctx, a->rs1, rs1);
+
+    tcg_temp_free(addr);
+    return true;
+}
+
+static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_inc(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_inc(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_inc(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_inc(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TEUW, false);
+}
+
+static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_TEUW, true);
+}
+
+static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_SB, true);
+}
+
+static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_UB, false);
+}
+
+static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_inc(ctx, a, MO_UB, true);
+}
+
+static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_store_inc(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_store_inc(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_inc(ctx, a, MO_SB, true);
+}
+
+/*
+ * Load with memop from indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+                         bool zext_offs)
+{
+    TCGv rd = dest_gpr(ctx, a->rd);
+    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+    tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop);
+    gen_set_gpr(ctx, a->rd, rd);
+
+    return true;
+}
+
+/*
+ * Store with memop to indexed address.
+ * If !zext_offs, then address is rs1 + (rs2 << imm2).
+ * If  zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
+ */
+static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
+                          bool zext_offs)
+{
+    TCGv data = get_gpr(ctx, a->rd, EXT_NONE);
+    TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
+
+    tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
+
+    return true;
+}
+
+static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_idx(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_idx(ctx, a, MO_TEUL, false);
+}
+
+static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TEUW, false);
+}
+
+static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_SB, false);
+}
+
+static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_UB, false);
+}
+
+static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_store_idx(ctx, a, MO_TESQ, false);
+}
+
+static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_TESL, false);
+}
+
+static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_TESW, false);
+}
+
+static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_SB, false);
+}
+static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_idx(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_load_idx(ctx, a, MO_TEUL, true);
+}
+
+static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_TEUW, true);
+}
+
+static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_SB, true);
+}
+
+static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_load_idx(ctx, a, MO_UB, true);
+}
+
+static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    REQUIRE_64BIT(ctx);
+    return gen_store_idx(ctx, a, MO_TESQ, true);
+}
+
+static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_TESL, true);
+}
+
+static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_TESW, true);
+}
+
+static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a)
+{
+    REQUIRE_XTHEADMEMIDX(ctx);
+    return gen_store_idx(ctx, a, MO_SB, true);
+}
+
 /* XTheadMemPair */
 
 static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |   1 +
 target/riscv/xthead.decode                 |  10 ++
 target/riscv/cpu.c                         |   2 +
 target/riscv/translate.c                   |   3 +-
 target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++
 5 files changed, 123 insertions(+), 1 deletion(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

There are no differences for floating point instructions in priv version 1.11
and 1.12. There is also no dependency for Zfh to priv version 1.12.
Therefore allow Zfh to be enabled for priv version 1.11.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-12-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei),
     ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause),
     ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs),
-    ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh),
+    ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh),
     ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
     ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
     ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds the T-Head C906 to the list of known CPUs.
Selecting this CPUs will automatically enable the available
ISA extensions of the CPUs (incl. vendor extensions).

Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h          |  1 +
 target/riscv/cpu_vendorid.h |  6 ++++++
 target/riscv/cpu.c          | 31 +++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+)
 create mode 100644 target/riscv/cpu_vendorid.h

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+#define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 #if defined(TARGET_RISCV32)
diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/cpu_vendorid.h
@@ -XXX,XX +XXX,XX @@
+#ifndef TARGET_RISCV_CPU_VENDORID_H
+#define TARGET_RISCV_CPU_VENDORID_H
+
+#define THEAD_VENDOR_ID         0x5b7
+
+#endif /*  TARGET_RISCV_CPU_VENDORID_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/ctype.h"
 #include "qemu/log.h"
 #include "cpu.h"
+#include "cpu_vendorid.h"
 #include "pmu.h"
 #include "internals.h"
 #include "time_helper.h"
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
     cpu->cfg.mmu = false;
 }
 
+static void rv64_thead_c906_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_priv_version(env, PRIV_VERSION_1_11_0);
+
+    cpu->cfg.ext_g = true;
+    cpu->cfg.ext_c = true;
+    cpu->cfg.ext_u = true;
+    cpu->cfg.ext_s = true;
+    cpu->cfg.ext_icsr = true;
+    cpu->cfg.ext_zfh = true;
+    cpu->cfg.mmu = true;
+    cpu->cfg.ext_xtheadba = true;
+    cpu->cfg.ext_xtheadbb = true;
+    cpu->cfg.ext_xtheadbs = true;
+    cpu->cfg.ext_xtheadcmo = true;
+    cpu->cfg.ext_xtheadcondmov = true;
+    cpu->cfg.ext_xtheadfmemidx = true;
+    cpu->cfg.ext_xtheadmac = true;
+    cpu->cfg.ext_xtheadmemidx = true;
+    cpu->cfg.ext_xtheadmempair = true;
+    cpu->cfg.ext_xtheadsync = true;
+
+    cpu->cfg.mvendorid = THEAD_VENDOR_ID;
+}
+
 static void rv128_base_cpu_init(Object *obj)
 {
     if (qemu_tcg_mttcg_enabled()) {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,       rv64_thead_c906_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_BASE128,          rv128_base_cpu_init),
 #endif
 };
-- 
2.39.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h                         |  1 +
 target/riscv/xthead.decode                 |  4 ++
 target/riscv/cpu.c                         |  2 +
 target/riscv/translate.c                   |  6 +--
 target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++
 5 files changed, 55 insertions(+), 3 deletions(-)

From: Christoph Müllner <christoph.muellner@vrull.eu>

The XThead* extensions are maintained by T-Head and VRULL.
Adding a point of contact from both companies.

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/
 
+RISC-V XThead* extensions
+M: Christoph Muellner <christoph.muellner@vrull.eu>
+M: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/insn_trans/trans_xthead.c.inc
+F: target/riscv/xthead*.decode
+
 RISC-V XVentanaCondOps extension
 M: Philipp Tomsich <philipp.tomsich@vrull.eu>
 L: qemu-riscv@nongnu.org
-- 
2.39.1

From: Deepak Gupta <debug@rivosinc.com>

commit fb3f3730e4 added mechanism to generate virtual instruction
exception during instruction decode when virt is enabled.

However in some situations, illegal instruction exception can be raised
due to state of CPU. One such situation is implementing branch tracking.
[1] An indirect branch if doesn't land on a landing pad instruction, then
cpu must raise an illegal instruction exception.
Implementation would raise such expcetion due to missing landing pad inst
and not due to decode. Thus DisasContext must have `virt_inst_excp`
initialized to false during DisasContxt initialization for TB.

[1] - https://github.com/riscv/riscv-cfi

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230127191758.755844-1-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
+    ctx->virt_inst_excp = false;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.39.1

From: Vladimir Isaev <vladimir.isaev@syntacore.com>

According to spec, ctzw should work with 32-bit register, not 64.

For example, previous implementation returns 33 for (1<<33) input
when the new one returns 32.

Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230204082312.43557-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
+    ctx->ol = MXL_RV32;
     return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
 }
 
-- 
2.39.1

From: Vladimir Isaev <vladimir.isaev@syntacore.com>

Character must be returned via ret[0] field (copied to a0 by KVM).

Return value should be set to 0 to indicate successful processing.

Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230203135155.12449-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     case SBI_EXT_0_1_CONSOLE_GETCHAR:
         ret = qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch));
         if (ret == sizeof(ch)) {
-            run->riscv_sbi.args[0] = ch;
+            run->riscv_sbi.ret[0] = ch;
         } else {
-            run->riscv_sbi.args[0] = -1;
+            run->riscv_sbi.ret[0] = -1;
         }
+        ret = 0;
         break;
     default:
         qemu_log_mask(LOG_UNIMP,
-- 
2.39.1

From: Bin Meng <bmeng@tinylab.org>

There is no need to declare an intermediate "MachineState *ms".

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230206085007.3618715-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_aia(Object *obj, const char *val, Error **errp)
 
 static bool virt_get_aclint(Object *obj, Error **errp)
 {
-    MachineState *ms = MACHINE(obj);
-    RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 
     return s->have_aclint;
 }
 
 static void virt_set_aclint(Object *obj, bool value, Error **errp)
 {
-    MachineState *ms = MACHINE(obj);
-    RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 
     s->have_aclint = value;
 }
-- 
2.39.1

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1