Series comparison

-[PULL 00/37] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-From: Alistair Francis <alistair.francis@wdc.com>
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-The following changes since commit 239b8b0699a222fd21da1c5fdeba0a2456085a47:
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
   Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-01-19 15:05:29 +0000)
 are available in the Git repository at:
-  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230120
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to b748352c555b42d497fe8ee00ee2e44eb8627660:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() (2023-01-20 10:14:14 +1000)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-Second RISC-V PR for QEMU 8.0
+RISC-V PR for 9.1
-* riscv_htif: Support console output via proxy syscall
+* APLICs add child earlier than realize
-* Cleanup firmware and device tree loading
+* Fix exposure of Zkr
-* Fix elen check when using vector extensions
+* Raise exceptions on wrs.nto
-* add RISC-V OpenSBI boot test
+* Implement SBI debug console (DBCN) calls for KVM
-* Ensure we always follow MISA parsing
+* Support 64-bit addresses for initrd
-* Fix up masking of vsip/vsie accesses
+* Change RISCV_EXCP_SEMIHOST exception number to 63
-* Trap on writes to stimecmp from VS when hvictl.VTI=1
+* Tolerate KVM disable ext errors
-* Introduce helper_set_rounding_mode_chkfrm
+* Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Andrew Bresticker (2):
+Alexei Filippov (1):
-      target/riscv: Fix up masking of vsip/vsie accesses
+      target/riscv: do not set mtval2 for non guest-page faults
       target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
-Bin Meng (11):
+Alistair Francis (2):
-      hw/char: riscv_htif: Avoid using magic numbers
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      hw/char: riscv_htif: Drop {to, from}host_size in HTIFState
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       hw/char: riscv_htif: Drop useless assignment of memory region
       hw/char: riscv_htif: Use conventional 's' for HTIFState
       hw/char: riscv_htif: Move registers from CPUArchState to HTIFState
       hw/char: riscv_htif: Remove forward declarations for non-existent variables
       hw/char: riscv_htif: Support console output via proxy syscall
       hw/riscv: spike: Remove the out-of-date comments
       hw/riscv/boot.c: Introduce riscv_find_firmware()
       hw/riscv: spike: Decouple create_fdt() dependency to ELF loading
       target/riscv: Use TARGET_FMT_lx for env->mhartid
-Daniel Henrique Barboza (20):
+Andrew Jones (2):
-      hw/riscv/boot.c: make riscv_find_firmware() static
+      target/riscv/kvm: Fix exposure of Zkr
-      hw/riscv/boot.c: introduce riscv_default_firmware_name()
+      target/riscv: Raise exceptions on wrs.nto
       tests/avocado: add RISC-V OpenSBI boot test
       hw/riscv/spike: use 'fdt' from MachineState
       hw/riscv/sifive_u: use 'fdt' from MachineState
       hw/riscv/boot.c: exit early if filename is NULL in load functions
       hw/riscv/spike.c: load initrd right after riscv_load_kernel()
       hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
       hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
       hw/riscv/boot.c: use MachineState in riscv_load_initrd()
       hw/riscv/boot.c: use MachineState in riscv_load_kernel()
       target/riscv/cpu: set cpu->cfg in register_cpu_props()
       target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
       hw/riscv/spike.c: simplify create_fdt()
       hw/riscv/virt.c: simplify create_fdt()
       hw/riscv/sifive_u.c: simplify create_fdt()
       hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
       hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
       hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
       hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()
-Dongxue Zhang (1):
+Cheng Yang (1):
-      target/riscv/cpu.c: Fix elen check
+      hw/riscv/boot.c: Support 64-bit address for initrd
-Richard Henderson (3):
+Christoph Müllner (1):
-      tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
+      riscv: thead: Add th.sxstatus CSR emulation
       target/riscv: Introduce helper_set_rounding_mode_chkfrm
       target/riscv: Remove helper_set_rod_rounding_mode
- include/hw/char/riscv_htif.h            |  19 +-
+Clément Léger (1):
- include/hw/riscv/boot.h                 |   9 +-
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
- include/hw/riscv/numa.h                 |  10 +-
- include/hw/riscv/sifive_u.h             |   3 -
+Daniel Henrique Barboza (6):
- include/hw/riscv/spike.h                |   2 -
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
- target/riscv/cpu.h                      |   8 +-
+      target/riscv/kvm: tolerate KVM disable ext errors
- target/riscv/helper.h                   |   2 +-
+      target/riscv/debug: set tval=pc in breakpoint exceptions
- hw/char/riscv_htif.c                    | 172 +++++++-----
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
- hw/riscv/boot.c                         | 105 +++++---
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
- hw/riscv/microchip_pfsoc.c              |  12 +-
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
- hw/riscv/numa.c                         |  14 +-
- hw/riscv/opentitan.c                    |   3 +-
+Huang Tao (2):
- hw/riscv/sifive_e.c                     |   3 +-
+      target/riscv: Fix the element agnostic function problem
- hw/riscv/sifive_u.c                     |  53 ++--
+      target/riscv: Implement dynamic establishment of custom decoder
- hw/riscv/spike.c                        | 108 ++++----
- hw/riscv/virt.c                         |  86 +++---
+Jason Chien (3):
- target/riscv/cpu.c                      | 445 ++++++++++++++++++--------------
+      target/riscv: Add support for Zve32x extension
- target/riscv/csr.c                      |  41 ++-
+      target/riscv: Add support for Zve64x extension
- target/riscv/fpu_helper.c               |  36 ++-
+      target/riscv: Relax vector register check in RISCV gdbstub
- target/riscv/machine.c                  |   6 +-
- target/riscv/translate.c                |  21 +-
+Max Chou (4):
- target/riscv/insn_trans/trans_rvv.c.inc |  24 +-
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
- tcg/riscv/tcg-target.c.inc              |   2 +-
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
- tests/avocado/riscv_opensbi.py          |  65 +++++
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-files changed, 713 insertions(+), 536 deletions(-)
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
- create mode 100644 tests/avocado/riscv_opensbi.py
 Rob Bradford (1):
       target/riscv: Remove experimental prefix from "B" extension
 Yangyu Chen (1):
       target/riscv/cpu.c: fix Zvkb extension config
 Yong-Xuan Wang (1):
       target/riscv/kvm.c: Fix the hart bit setting of AIA
 Yu-Ming Chang (1):
       target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
 yang.zhang (1):
       hw/intc/riscv_aplic: APLICs should add child earlier than realize
  MAINTAINERS                                    |   1 +
  target/riscv/cpu.h                             |  11 ++
  target/riscv/cpu_bits.h                        |   2 +-
  target/riscv/cpu_cfg.h                         |   2 +
  target/riscv/helper.h                          |   1 +
  target/riscv/sbi_ecall_interface.h             |  17 +++
  target/riscv/tcg/tcg-cpu.h                     |  15 +++
  disas/riscv.c                                  |  65 +++++++++-
  hw/intc/riscv_aplic.c                          |   8 +-
  hw/riscv/boot.c                                |   4 +-
  target/riscv/cpu.c                             |  10 +-
  target/riscv/cpu_helper.c                      |  37 +++---
  target/riscv/csr.c                             |  71 +++++++++--
  target/riscv/debug.c                           |   3 +
  target/riscv/gdbstub.c                         |   8 +-
  target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
  target/riscv/op_helper.c                       |  17 ++-
  target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
  target/riscv/th_csr.c                          |  79 +++++++++++++
  target/riscv/translate.c                       |  31 +++--
  target/riscv/vector_internals.c                |  22 ++++
  target/riscv/insn_trans/trans_privileged.c.inc |   2 +
  target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
  target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
  target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
  target/riscv/meson.build                       |   1 +
 files changed, 596 insertions(+), 109 deletions(-)
  create mode 100644 target/riscv/th_csr.c

-[PULL 01/37] hw/char: riscv_htif: Avoid using magic numbers
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-The Spike HTIF is poorly documented. The only relevant info we can
-get from the internet is from Andrew Waterman at [1].
-Add a comment block before htif_handle_tohost_write() to explain
-the tohost register format, and use meaningful macros instead of
-magic numbers in the codes.
-While we are here, correct 2 multi-line comment blocks that have
-wrong format.
-Link: https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754 [1]
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-2-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/char/riscv_htif.c | 72 ++++++++++++++++++++++++++++++++------------
-file changed, 52 insertions(+), 20 deletions(-)
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
-+++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@
-         }                                                                      \
-     } while (0)
-+#define HTIF_DEV_SHIFT          56
-+#define HTIF_CMD_SHIFT          48
-+
-+#define HTIF_DEV_SYSTEM         0
-+#define HTIF_DEV_CONSOLE        1
-+
-+#define HTIF_SYSTEM_CMD_SYSCALL 0
-+#define HTIF_CONSOLE_CMD_GETC   0
-+#define HTIF_CONSOLE_CMD_PUTC   1
-+
- static uint64_t fromhost_addr, tohost_addr;
- static int address_symbol_set;
-@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
-         return;
-     }
--    /* TODO - we need to check whether mfromhost is zero which indicates
--              the device is ready to receive. The current implementation
--              will drop characters */
-+    /*
-+     * TODO - we need to check whether mfromhost is zero which indicates
-+     *        the device is ready to receive. The current implementation
-+     *        will drop characters
-+     */
-     uint64_t val_written = htifstate->pending_read;
-     uint64_t resp = 0x100 | *buf;
-@@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque)
-     return 0;
- }
-+/*
-+ * See below the tohost register format.
-+ *
-+ * Bits 63:56 indicate the "device".
-+ * Bits 55:48 indicate the "command".
-+ *
-+ * Device 0 is the syscall device, which is used to emulate Unixy syscalls.
-+ * It only implements command 0, which has two subfunctions:
-+ * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
-+ *   describing the syscall.
-+ * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
-+ *   value indicating success and other values indicating failure.
-+ *
-+ * Device 1 is the blocking character device.
-+ * - Command 0 reads a character
-+ * - Command 1 writes a character from the 8 LSBs of tohost
-+ *
-+ * For RV32, the tohost register is zero-extended, so only device=0 and
-+ * command=0 (i.e. HTIF syscalls/exit codes) are supported.
-+ */
- static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
- {
--    uint8_t device = val_written >> 56;
--    uint8_t cmd = val_written >> 48;
-+    uint8_t device = val_written >> HTIF_DEV_SHIFT;
-+    uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
-     uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
-     int resp = 0;
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-      * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
-      * 1: Console
-      */
--    if (unlikely(device == 0x0)) {
-+    if (unlikely(device == HTIF_DEV_SYSTEM)) {
-         /* frontend syscall handler, shutdown and exit code support */
--        if (cmd == 0x0) {
-+        if (cmd == HTIF_SYSTEM_CMD_SYSCALL) {
-             if (payload & 0x1) {
-                 /* exit code */
-                 int exit_code = payload >> 1;
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-         } else {
-             qemu_log("HTIF device %d: unknown command\n", device);
-         }
--    } else if (likely(device == 0x1)) {
-+    } else if (likely(device == HTIF_DEV_CONSOLE)) {
-         /* HTIF Console */
--        if (cmd == 0x0) {
-+        if (cmd == HTIF_CONSOLE_CMD_GETC) {
-             /* this should be a queue, but not yet implemented as such */
-             htifstate->pending_read = val_written;
-             htifstate->env->mtohost = 0; /* clear to indicate we read */
-             return;
--        } else if (cmd == 0x1) {
-+        } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
-             qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
-             resp = 0x100 | (uint8_t)payload;
-         } else {
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-             " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
-     }
-     /*
--     * - latest bbl does not set fromhost to 0 if there is a value in tohost
--     * - with this code enabled, qemu hangs waiting for fromhost to go to 0
--     * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
--     * - HTIF needs protocol documentation and a more complete state machine
--
--        while (!htifstate->fromhost_inprogress &&
--            htifstate->env->mfromhost != 0x0) {
--        }
--    */
-+     * Latest bbl does not set fromhost to 0 if there is a value in tohost.
-+     * With this code enabled, qemu hangs waiting for fromhost to go to 0.
-+     * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
-+     * HTIF needs protocol documentation and a more complete state machine.
-+     *
-+     *  while (!htifstate->fromhost_inprogress &&
-+     *      htifstate->env->mfromhost != 0x0) {
-+     *  }
-+     */
-     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
-     htifstate->env->mtohost = 0; /* clear to indicate we read */
- }
-@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
- /* CPU wrote to an HTIF register */
- static void htif_mm_write(void *opaque, hwaddr addr,
--                            uint64_t value, unsigned size)
-+                          uint64_t value, unsigned size)
- {
-     HTIFState *htifstate = opaque;
-     if (addr == TOHOST_OFFSET1) {
---
-.39.0

-[PULL 02/37] hw/char: riscv_htif: Drop {to, from}host_size in HTIFState
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-These are not used anywhere. Drop them.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-3-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/riscv_htif.h | 2 --
-file changed, 2 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
-+++ b/include/hw/char/riscv_htif.h
-@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
-     hwaddr tohost_offset;
-     hwaddr fromhost_offset;
--    uint64_t tohost_size;
--    uint64_t fromhost_size;
-     MemoryRegion mmio;
-     MemoryRegion *address_space;
-     MemoryRegion *main_mem;
---
-.39.0

-[PULL 03/37] hw/char: riscv_htif: Drop useless assignment of memory region
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-struct HTIFState has 3 members for address space and memory region,
-and are initialized during htif_mm_init(). But they are actually
-useless. Drop them.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-4-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/riscv_htif.h | 7 ++-----
- hw/char/riscv_htif.c         | 7 ++-----
- hw/riscv/spike.c             | 5 ++---
-files changed, 6 insertions(+), 13 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
-+++ b/include/hw/char/riscv_htif.h
-@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
-     hwaddr tohost_offset;
-     hwaddr fromhost_offset;
-     MemoryRegion mmio;
--    MemoryRegion *address_space;
--    MemoryRegion *main_mem;
--    void *main_mem_ram_ptr;
-     CPURISCVState *env;
-     CharBackend chr;
-@@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
- bool htif_uses_elf_symbols(void);
- /* legacy pre qom */
--HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
--    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
-+HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
-+                        Chardev *chr, uint64_t nonelf_base);
- #endif
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
-+++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void)
-     return (address_symbol_set == 3) ? true : false;
- }
--HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
--    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
-+HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
-+                        Chardev *chr, uint64_t nonelf_base)
- {
-     uint64_t base, size, tohost_offset, fromhost_offset;
-@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-     fromhost_offset = fromhost_addr - base;
-     HTIFState *s = g_new0(HTIFState, 1);
--    s->address_space = address_space;
--    s->main_mem = main_mem;
--    s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
-     s->env = env;
-     s->tohost_offset = tohost_offset;
-     s->fromhost_offset = fromhost_offset;
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-                               fdt_load_addr);
-     /* initialize HTIF using symbols found in load_kernel */
--    htif_mm_init(system_memory, mask_rom,
--                 &s->soc[0].harts[0].env, serial_hd(0),
--                 memmap[SPIKE_HTIF].base);
-+    htif_mm_init(system_memory, &s->soc[0].harts[0].env,
-+                 serial_hd(0), memmap[SPIKE_HTIF].base);
- }
- static void spike_machine_instance_init(Object *obj)
---
-.39.0

-[PULL 04/37] hw/char: riscv_htif: Use conventional 's' for HTIFState
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-QEMU source codes tend to use 's' to represent the hardware state.
-Let's use it for HTIFState.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-5-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/char/riscv_htif.c | 64 ++++++++++++++++++++++----------------------
-file changed, 32 insertions(+), 32 deletions(-)
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
-+++ b/hw/char/riscv_htif.c
-@@ -XXX,XX +XXX,XX @@ static int htif_can_recv(void *opaque)
-  */
- static void htif_recv(void *opaque, const uint8_t *buf, int size)
- {
--    HTIFState *htifstate = opaque;
-+    HTIFState *s = opaque;
-     if (size != 1) {
-         return;
-@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
-      *        will drop characters
-      */
--    uint64_t val_written = htifstate->pending_read;
-+    uint64_t val_written = s->pending_read;
-     uint64_t resp = 0x100 | *buf;
--    htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
-+    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
- }
- /*
-@@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque)
-  * For RV32, the tohost register is zero-extended, so only device=0 and
-  * command=0 (i.e. HTIF syscalls/exit codes) are supported.
-  */
--static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-+static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
- {
-     uint8_t device = val_written >> HTIF_DEV_SHIFT;
-     uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-         /* HTIF Console */
-         if (cmd == HTIF_CONSOLE_CMD_GETC) {
-             /* this should be a queue, but not yet implemented as such */
--            htifstate->pending_read = val_written;
--            htifstate->env->mtohost = 0; /* clear to indicate we read */
-+            s->pending_read = val_written;
-+            s->env->mtohost = 0; /* clear to indicate we read */
-             return;
-         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
--            qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
-+            qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
-             resp = 0x100 | (uint8_t)payload;
-         } else {
-             qemu_log("HTIF device %d: unknown command\n", device);
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
-      * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
-      * HTIF needs protocol documentation and a more complete state machine.
-      *
--     *  while (!htifstate->fromhost_inprogress &&
--     *      htifstate->env->mfromhost != 0x0) {
-+     *  while (!s->fromhost_inprogress &&
-+     *      s->env->mfromhost != 0x0) {
-      *  }
-      */
--    htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
--    htifstate->env->mtohost = 0; /* clear to indicate we read */
-+    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
-+    s->env->mtohost = 0; /* clear to indicate we read */
- }
--#define TOHOST_OFFSET1 (htifstate->tohost_offset)
--#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
--#define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
--#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
-+#define TOHOST_OFFSET1      (s->tohost_offset)
-+#define TOHOST_OFFSET2      (s->tohost_offset + 4)
-+#define FROMHOST_OFFSET1    (s->fromhost_offset)
-+#define FROMHOST_OFFSET2    (s->fromhost_offset + 4)
- /* CPU wants to read an HTIF register */
- static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
- {
--    HTIFState *htifstate = opaque;
-+    HTIFState *s = opaque;
-     if (addr == TOHOST_OFFSET1) {
--        return htifstate->env->mtohost & 0xFFFFFFFF;
-+        return s->env->mtohost & 0xFFFFFFFF;
-     } else if (addr == TOHOST_OFFSET2) {
--        return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
-+        return (s->env->mtohost >> 32) & 0xFFFFFFFF;
-     } else if (addr == FROMHOST_OFFSET1) {
--        return htifstate->env->mfromhost & 0xFFFFFFFF;
-+        return s->env->mfromhost & 0xFFFFFFFF;
-     } else if (addr == FROMHOST_OFFSET2) {
--        return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
-+        return (s->env->mfromhost >> 32) & 0xFFFFFFFF;
-     } else {
-         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
-             (uint64_t)addr);
-@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
- static void htif_mm_write(void *opaque, hwaddr addr,
-                           uint64_t value, unsigned size)
- {
--    HTIFState *htifstate = opaque;
-+    HTIFState *s = opaque;
-     if (addr == TOHOST_OFFSET1) {
--        if (htifstate->env->mtohost == 0x0) {
--            htifstate->allow_tohost = 1;
--            htifstate->env->mtohost = value & 0xFFFFFFFF;
-+        if (s->env->mtohost == 0x0) {
-+            s->allow_tohost = 1;
-+            s->env->mtohost = value & 0xFFFFFFFF;
-         } else {
--            htifstate->allow_tohost = 0;
-+            s->allow_tohost = 0;
-         }
-     } else if (addr == TOHOST_OFFSET2) {
--        if (htifstate->allow_tohost) {
--            htifstate->env->mtohost |= value << 32;
--            htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
-+        if (s->allow_tohost) {
-+            s->env->mtohost |= value << 32;
-+            htif_handle_tohost_write(s, s->env->mtohost);
-         }
-     } else if (addr == FROMHOST_OFFSET1) {
--        htifstate->fromhost_inprogress = 1;
--        htifstate->env->mfromhost = value & 0xFFFFFFFF;
-+        s->fromhost_inprogress = 1;
-+        s->env->mfromhost = value & 0xFFFFFFFF;
-     } else if (addr == FROMHOST_OFFSET2) {
--        htifstate->env->mfromhost |= value << 32;
--        htifstate->fromhost_inprogress = 0;
-+        s->env->mfromhost |= value << 32;
-+        s->fromhost_inprogress = 0;
-     } else {
-         qemu_log("Invalid htif write: address %016" PRIx64 "\n",
-             (uint64_t)addr);
---
-.39.0

-[PULL 18/37] hw/riscv/spike.c: load initrd right after riscv_load_kernel()
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: "yang.zhang" <yang.zhang@hexintek.com>
-This will make the code more in line with what the other boards are
+Since only root APLICs can have hw IRQ lines, aplic->parent should
-doing. We'll also avoid an extra check to machine->kernel_filename since
+be initialized first.
 we already checked that before executing riscv_load_kernel().
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com>
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/spike.c | 31 +++++++++++++++----------------
+ hw/intc/riscv_aplic.c | 8 ++++----
-file changed, 15 insertions(+), 16 deletions(-)
+file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/hw/intc/riscv_aplic.c
-+++ b/hw/riscv/spike.c
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
-         g_free(firmware_name);
+     qdev_prop_set_bit(dev, "msimode", msimode);
      qdev_prop_set_bit(dev, "mmode", mmode);
 +    if (parent) {
 +        riscv_aplic_add_child(parent, dev);
 +    }
 +
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      if (!is_kvm_aia(msimode)) {
          sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      }
-+    /* Create device tree */
+-    if (parent) {
-+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+-        riscv_aplic_add_child(parent, dev);
 +               riscv_is_32bit(&s->soc[0]), htif_custom_base);
 +
      /* Load kernel */
      if (machine->kernel_filename) {
          kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                           kernel_start_addr,
                                           htif_symbol_callback);
 +
 +        if (machine->initrd_filename) {
 +            hwaddr start;
 +            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 +                                           machine->ram_size, kernel_entry,
 +                                           &start);
 +            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 +                                  "linux,initrd-start", start);
 +            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 +                                  end);
 +        }
      } else {
         /*
          * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
          kernel_entry = 0;
      }
 -    /* Create device tree */
 -    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 -               riscv_is_32bit(&s->soc[0]), htif_custom_base);
 -
 -    /* Load initrd */
 -    if (machine->kernel_filename && machine->initrd_filename) {
 -        hwaddr start;
 -        hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                       machine->ram_size, kernel_entry,
 -                                       &start);
 -        qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                              "linux,initrd-start", start);
 -        qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 -                              end);
 -    }
 -
-     /* Compute the fdt load address in dram */
+     if (!msimode) {
-     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
+         for (i = 0; i < num_harts; i++) {
-                                    machine->ram_size, machine->fdt);
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
 --
-.39.0
+.45.1

-[PULL 33/37] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
-From: Andrew Bresticker <abrestic@rivosinc.com>
+From: Andrew Jones <ajones@ventanamicro.com>
-Per the AIA specification, writes to stimecmp from VS level should
+The Zkr extension may only be exposed to KVM guests if the VMM
-trap when hvictl.VTI is set since the write may cause vsip.STIP to
+implements the SEED CSR. Use the same implementation as TCG.
 become unset.
-Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
+Without this patch, running with a KVM which does not forward the
-Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
+SEED CSR access to QEMU will result in an ILL exception being
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+injected into the guest (this results in Linux guests crashing on
-Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com>
+boot). And, when running with a KVM which does forward the access,
 QEMU will crash, since QEMU doesn't know what to do with the exit.
 Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
 Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 6 ++++++
+ target/riscv/cpu.h         |  3 +++
-file changed, 6 insertions(+)
+ target/riscv/csr.c         | 18 ++++++++++++++----
  target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 files changed, 42 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask);
++
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
-     RISCVCPU *cpu = env_archcpu(env);
+ #endif
-     if (riscv_cpu_virt_enabled(env)) {
+ /* Crypto Extension */
-+        if (env->hvictl & HVICTL_VTI) {
+-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+-                               target_ulong *ret_value,
-+        }
+-                               target_ulong new_value,
-         return write_vstimecmp(env, csrno, val);
+-                               target_ulong write_mask)
 +target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
      uint16_t random_v;
      Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
          rval = random_v | SEED_OPST_ES16;
      }
-@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
++    return rval;
-     RISCVCPU *cpu = env_archcpu(env);
++}
++
-     if (riscv_cpu_virt_enabled(env)) {
++static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-+        if (env->hvictl & HVICTL_VTI) {
++                               target_ulong *ret_value,
-+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
++                               target_ulong new_value,
-+        }
++                               target_ulong write_mask)
-         return write_vstimecmph(env, csrno, val);
++{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
 +static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
 +{
 +    target_ulong csr_num = run->riscv_csr.csr_num;
 +    target_ulong new_value = run->riscv_csr.new_value;
 +    target_ulong write_mask = run->riscv_csr.write_mask;
 +    int ret = 0;
 +
 +    switch (csr_num) {
 +    case CSR_SEED:
 +        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_UNIMP,
 +                      "%s: un-handled CSR EXIT for CSR %lx\n",
 +                      __func__, csr_num);
 +        ret = -1;
 +        break;
 +    }
 +
 +    return ret;
 +}
 +
  int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
      case KVM_EXIT_RISCV_SBI:
          ret = kvm_riscv_handle_sbi(cs, run);
          break;
 +    case KVM_EXIT_RISCV_CSR:
 +        ret = kvm_riscv_handle_csr(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                        __func__, run->exit_reason);
 --
-.39.0
+.45.1

-[PULL 36/37] target/riscv: Remove helper_set_rod_rounding_mode
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <ajones@ventanamicro.com>
-The only setting of RISCV_FRM_ROD is from the vector unit,
+Implementing wrs.nto to always just return is consistent with the
-and now handled by helper_set_rounding_mode_chkfrm.
+specification, as the instruction is permitted to terminate the
-This helper is now unused.
+stall for any reason, but it's not useful for virtualization, where
 we'd like the guest to trap to the hypervisor in order to allow
 scheduling of the lock holding VCPU. Change to always immediately
 raise exceptions when the appropriate conditions are present,
 otherwise continue to just return. Note, immediately raising
 exceptions is also consistent with the specification since the
 time limit that should expire prior to the exception is
 implementation-specific.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org>
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h     | 1 -
+ target/riscv/helper.h                       |  1 +
- target/riscv/fpu_helper.c | 5 -----
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/translate.c  | 4 ----
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
-files changed, 10 deletions(-)
+files changed, 32 insertions(+), 9 deletions(-)
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- /* Floating Point - rounding mode */
+ DEF_HELPER_1(sret, tl, env)
- DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+ DEF_HELPER_1(mret, tl, env)
- DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
+ DEF_HELPER_1(wfi, void, env)
--DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
++DEF_HELPER_1(wrs_nto, void, env)
+ DEF_HELPER_1(tlb_flush, void, env)
- /* Floating Point - fused */
+ DEF_HELPER_1(tlb_flush_all, void, env)
- DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
+ /* Native Debug */
-diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/fpu_helper.c
+--- a/target/riscv/op_helper.c
-+++ b/target/riscv/fpu_helper.c
++++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
-     set_float_rounding_mode(softrm, &env->fp_status);
+     }
  }
--void helper_set_rod_rounding_mode(CPURISCVState *env)
++void helper_wrs_nto(CPURISCVState *env)
--{
++{
--    set_float_rounding_mode(float_round_to_odd, &env->fp_status);
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
 +        get_field(env->hstatus, HSTATUS_VTW) &&
 +        !get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +}
 +
  void helper_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
 diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
 -static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
 -#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
--
++static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
- static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
++{
-                            uint64_t rs3, int flags)
++    if (!ctx->cfg_ptr->ext_zawrs) {
- {
++        return false;
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
++    }
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
+-GEN_TRANS_WRS(wrs_nto)
-+++ b/target/riscv/translate.c
+-GEN_TRANS_WRS(wrs_sto)
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
++    /*
-     }
++     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
-     ctx->frm = rm;
++     * should raise an exception when the implementation-specific bounded time
++     * limit has expired. Our time limit is zero, so we either return
--    if (rm == RISCV_FRM_ROD) {
++     * immediately, as does our implementation of wrs.sto, or raise an
--        gen_helper_set_rod_rounding_mode(cpu_env);
++     * exception, as handled by the wrs.nto helper.
--        return;
++     */
--    }
++#ifndef CONFIG_USER_ONLY
-     if (rm == RISCV_FRM_DYN) {
++    gen_helper_wrs_nto(tcg_env);
-         /* The helper will return only if frm valid. */
++#endif
-         ctx->frm_valid = true;
++
 +    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
 +    return trans_wrs_sto(ctx, NULL);
 +}
 --
-.39.0
+.45.1

-[PULL 15/37] hw/riscv/spike: use 'fdt' from MachineState
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The MachineState object provides a 'fdt' pointer that is already being
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
-used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
+the legacy console putchar and getchar SBI extensions.
-command.
+The appeal of the DBCN extension is that it allows multiple bytes to be
-Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
+read/written in the SBI console in a single SBI call.
-instead.
 As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
 module to userspace. But this will only happens if the KVM module
 actually supports this SBI extension and we activate it.
 We'll check for DBCN support during init time, checking if get-reg-list
 is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
 kvm_set_one_reg() during kvm_arch_init_vcpu().
 Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
 SBI_EXT_DBCN, reading and writing as required.
 A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
 host, takes around 20 seconds to boot without using DBCN. With this
 patch we're taking around 14 seconds to boot due to the speed-up in the
 terminal output.  There's no change in boot time if the guest isn't
 using earlycon.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Reviewed-by: Bin Meng <bmeng@tinylab.org>
 Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/spike.h |  2 --
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- hw/riscv/spike.c         | 12 +++++-------
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
-files changed, 5 insertions(+), 9 deletions(-)
+files changed, 128 insertions(+)
-diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/spike.h
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/include/hw/riscv/spike.h
++++ b/target/riscv/sbi_ecall_interface.h
-@@ -XXX,XX +XXX,XX @@ struct SpikeState {
+@@ -XXX,XX +XXX,XX @@
-     /*< public >*/
+ /* clang-format off */
-     RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
--    void *fdt;
++#define SBI_SUCCESS                      0
--    int fdt_size;
++#define SBI_ERR_FAILED                  -1
 +#define SBI_ERR_NOT_SUPPORTED           -2
 +#define SBI_ERR_INVALID_PARAM           -3
 +#define SBI_ERR_DENIED                  -4
 +#define SBI_ERR_INVALID_ADDRESS         -5
 +#define SBI_ERR_ALREADY_AVAILABLE       -6
 +#define SBI_ERR_ALREADY_STARTED         -7
 +#define SBI_ERR_ALREADY_STOPPED         -8
 +#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
- enum {
++static KVMCPUConfig kvm_sbi_dbcn = {
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
++    .name = "sbi_dbcn",
-index XXXXXXX..XXXXXXX 100644
++    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
---- a/hw/riscv/spike.c
++                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
-+++ b/hw/riscv/spike.c
++};
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
++
-                        bool is_32_bit, bool htif_custom_base)
+ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
-     void *fdt;
+     CPURISCVState *env = &cpu->env;
-+    int fdt_size;
+@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
-     uint64_t addr, size;
+     return 0;
-     unsigned long clint_addr;
+ }
-     int cpu, socket;
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
++static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
-         "sifive,clint0", "riscv,clint0"
++                                             KVMScratchCPU *kvmcpu,
-     };
++                                             struct kvm_reg_list *reglist)
++{
--    fdt = s->fdt = create_device_tree(&s->fdt_size);
++    struct kvm_reg_list *reg_search;
-+    fdt = mc->fdt = create_device_tree(&fdt_size);
++
-     if (!fdt) {
++    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
-         error_report("create_device_tree() failed");
++                         sizeof(uint64_t), uint64_cmp);
-         exit(1);
++
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
++    if (reg_search) {
-         hwaddr end = riscv_load_initrd(machine->initrd_filename,
++        kvm_sbi_dbcn.supported = true;
-                                        machine->ram_size, kernel_entry,
++    }
-                                        &start);
++}
--        qemu_fdt_setprop_cell(s->fdt, "/chosen",
++
-+        qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
-                               "linux,initrd-start", start);
+                                  struct kvm_reg_list *reglist)
--        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ {
-+        qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
-                               end);
+     if (riscv_has_ext(&cpu->env, RVV)) {
          kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
      }
++
-     /* Compute the fdt load address in dram */
++    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
-     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
+ }
--                                   machine->ram_size, s->fdt);
--
+ static void riscv_init_kvm_registers(Object *cpu_obj)
--    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
--    machine->fdt = s->fdt;
+     return ret;
-+                                   machine->ram_size, machine->fdt);
+ }
-     /* load the reset vector */
++static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
-     riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
++{
 +    target_ulong reg = 1;
 +
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
  int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
 +    g_autofree uint8_t *buf = NULL;
 +    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
  static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
          }
          ret = 0;
          break;
 +    case SBI_EXT_DBCN:
 +        kvm_riscv_handle_sbi_dbcn(cs, run);
 +        break;
      default:
          qemu_log_mask(LOG_UNIMP,
                        "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 --
-.39.0
+.45.1

-[PULL 22/37] hw/riscv/boot.c: use MachineState in riscv_load_kernel()
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Cheng Yang <yangcheng.work@foxmail.com>
-All callers are using kernel_filename as machine->kernel_filename.
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
 to set the address of initrd in FDT to support 64-bit address.
-This will also simplify the changes in riscv_load_kernel() that we're
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
 going to do next.
 Cc: Palmer Dabbelt <palmer@dabbelt.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h    | 2 +-
+ hw/riscv/boot.c | 4 ++--
- hw/riscv/boot.c            | 3 ++-
+file changed, 2 insertions(+), 2 deletions(-)
  hw/riscv/microchip_pfsoc.c | 3 +--
  hw/riscv/opentitan.c       | 3 +--
  hw/riscv/sifive_e.c        | 3 +--
  hw/riscv/sifive_u.c        | 3 +--
  hw/riscv/spike.c           | 3 +--
  hw/riscv/virt.c            | 3 +--
 files changed, 9 insertions(+), 14 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename,
- target_ulong riscv_load_firmware(const char *firmware_filename,
-                                  hwaddr firmware_load_addr,
-                                  symbol_fn_t sym_cb);
--target_ulong riscv_load_kernel(const char *kernel_filename,
-+target_ulong riscv_load_kernel(MachineState *machine,
-                                target_ulong firmware_end_addr,
-                                symbol_fn_t sym_cb);
- void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
-     exit(1);
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
- }
+     if (fdt) {
+         end = start + size;
--target_ulong riscv_load_kernel(const char *kernel_filename,
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-+target_ulong riscv_load_kernel(MachineState *machine,
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
-                                target_ulong kernel_start_addr,
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
-                                symbol_fn_t sym_cb)
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
  {
 +    const char *kernel_filename = machine->kernel_filename;
      uint64_t kernel_load_base, kernel_entry;
      g_assert(kernel_filename != NULL);
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
          kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
                                                           firmware_end_addr);
 -        kernel_entry = riscv_load_kernel(machine->kernel_filename,
 -                                         kernel_start_addr, NULL);
 +        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
          if (machine->initrd_filename) {
              riscv_load_initrd(machine, kernel_entry);
 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/opentitan.c
 +++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void opentitan_board_init(MachineState *machine)
      }
      if (machine->kernel_filename) {
 -        riscv_load_kernel(machine->kernel_filename,
 -                          memmap[IBEX_DEV_RAM].base, NULL);
 +        riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
      }
  }
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
-+++ b/hw/riscv/sifive_e.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
-                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
-     if (machine->kernel_filename) {
--        riscv_load_kernel(machine->kernel_filename,
--                          memmap[SIFIVE_E_DEV_DTIM].base, NULL);
-+        riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
-     }
- }
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
-                                                          firmware_end_addr);
--        kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                         kernel_start_addr, NULL);
-+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-         if (machine->initrd_filename) {
-             riscv_load_initrd(machine, kernel_entry);
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
-                                                          firmware_end_addr);
--        kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                         kernel_start_addr,
-+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
-                                          htif_symbol_callback);
-         if (machine->initrd_filename) {
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
-                                                          firmware_end_addr);
--        kernel_entry = riscv_load_kernel(machine->kernel_filename,
--                                         kernel_start_addr, NULL);
-+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
-         if (machine->initrd_filename) {
-             riscv_load_initrd(machine, kernel_entry);
 --
-.39.0
+.45.1

-[PULL 29/37] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Clément Léger <cleger@rivosinc.com>
-create_fdt_socket_cpus() writes a different 'mmu-type' value if we're
+The current semihost exception number (16) is a reserved number (range
-running in 32 or 64 bits. However, the flag is being calculated during
+[16-17]). The upcoming double trap specification uses that number for
-virt_machine_init(), and is passed around in create_fdt(), then
+the double trap exception. Since the privileged spec (Table 22) defines
-create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of
+ranges for custom uses change the semihosting exception number to 63
-the intermediate functions are using the flag, which is a bit
+which belongs to the range [48-63] in order to avoid any future
-misleading.
+collisions with reserved exception.
-Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
 using the already available RISCVVirtState pointer. This will also
 change the signature of create_fdt_socket() and create_fdt(), making it
 clear that these functions don't do anything special when we're running
 in 32 bit mode.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 18 +++++++++---------
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 9 insertions(+), 9 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu_bits.h
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
- static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
-                                    char *clust_name, uint32_t *phandle,
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--                                   bool is_32_bit, uint32_t *intc_phandles)
+-    RISCV_EXCP_SEMIHOST = 0x10,
-+                                   uint32_t *intc_phandles)
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
- {
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
-     int cpu;
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
-     uint32_t cpu_phandle;
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
-     MachineState *mc = MACHINE(s);
++    RISCV_EXCP_SEMIHOST = 0x3f,
-     char *name, *cpu_name, *core_name, *intc_name;
+ } RISCVException;
-+    bool is_32_bit = riscv_is_32bit(&s->soc[0]);
+ #define RISCV_EXCP_INT_FLAG                0x80000000
      for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
          cpu_phandle = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s)
  }
  static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
 -                               bool is_32_bit, uint32_t *phandle,
 +                               uint32_t *phandle,
                                 uint32_t *irq_mmio_phandle,
                                 uint32_t *irq_pcie_phandle,
                                 uint32_t *irq_virtio_phandle,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
          qemu_fdt_add_subnode(mc->fdt, clust_name);
          create_fdt_socket_cpus(s, socket, clust_name, phandle,
 -            is_32_bit, &intc_phandles[phandle_pos]);
 +                               &intc_phandles[phandle_pos]);
          create_fdt_socket_memory(s, memmap, socket);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
      g_free(nodename);
  }
 -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
 -                       bool is_32_bit)
 +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
  {
      MachineState *mc = MACHINE(s);
      uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
      qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
      qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
 -    create_fdt_sockets(s, memmap, is_32_bit, &phandle,
 -        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
 -        &msi_pcie_phandle);
 +    create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
 +                       &irq_pcie_phandle, &irq_virtio_phandle,
 +                       &msi_pcie_phandle);
      create_fdt_virtio(s, memmap, irq_virtio_phandle);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      virt_flash_map(s, system_memory);
      /* create device tree */
 -    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]));
 +    create_fdt(s, memmap);
      s->machine_done.notify = virt_machine_done;
      qemu_add_machine_init_done_notifier(&s->machine_done);
 --
-.39.0
+.45.1

-[PULL 31/37] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-There's no need to use a MachineState pointer and a fdt pointer now that
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
-all RISC-V machines are using the FDT from the MachineState.
+enabled, will fail with a kernel oops SIGILL right at the start. The
 reason is that we can't expose zkr without implementing the SEED CSR.
 Disabling zkr in the guest would be a workaround, but if the KVM doesn't
 allow it we'll error out and never boot.
+In hindsight this is too strict. If we keep proceeding, despite not
+disabling the extension in the KVM vcpu, we'll not add the extension in
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
+it's ok to keep booting in this case.
+Change our current logic to not error out if we fail to disable an
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
+is important to throw a warning because we must make the user aware that
+the extension is still available in the vcpu, meaning that an
+ill-behaved guest can ignore the riscv,isa settings and  use the
+extension.
+The case we're handling happens with an EINVAL error code. If we fail to
+disable the extension in KVM for any other reason, error out.
+We'll also keep erroring out when we fail to enable an extension in KVM,
+since adding the extension in riscv,isa at this point will cause a guest
+malfunction because the extension isn't enabled in the vcpu.
+Suggested-by: Andrew Jones <ajones@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com>
+Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/numa.h | 4 ++--
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
- hw/riscv/numa.c         | 8 ++++----
+file changed, 8 insertions(+), 4 deletions(-)
  hw/riscv/spike.c        | 2 +-
  hw/riscv/virt.c         | 2 +-
 files changed, 8 insertions(+), 8 deletions(-)
-diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/numa.h
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/include/hw/riscv/numa.h
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
-  * @ms: pointer to machine state
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
-  * @socket_id: socket index
+         ret = kvm_set_one_reg(cs, id, &reg);
-  *
+         if (ret != 0) {
-- * Write NUMA distance matrix in FDT for given machine
+-            error_report("Unable to %s extension %s in KVM, error %d",
-+ * Write NUMA distance matrix in MachineState->fdt
+-                         reg ? "enable" : "disable",
-  */
+-                         multi_ext_cfg->name, ret);
--void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
+-            exit(EXIT_FAILURE);
-+void riscv_socket_fdt_write_distance_matrix(const MachineState *ms);
++            if (!reg && ret == -EINVAL) {
++                warn_report("KVM cannot disable extension %s",
- CpuInstanceProperties
++                            multi_ext_cfg->name);
- riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
++            } else {
-diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
++                error_report("Unable to enable extension %s in KVM, error %d",
-index XXXXXXX..XXXXXXX 100644
++                             multi_ext_cfg->name, ret);
---- a/hw/riscv/numa.c
++                exit(EXIT_FAILURE);
-+++ b/hw/riscv/numa.c
++            }
-@@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
+         }
      }
  }
--void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
-+void riscv_socket_fdt_write_distance_matrix(const MachineState *ms)
- {
-     int i, j, idx;
-     uint32_t *dist_matrix, dist_matrix_size;
-@@ -XXX,XX +XXX,XX @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
-             }
-         }
--        qemu_fdt_add_subnode(fdt, "/distance-map");
--        qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
-+        qemu_fdt_add_subnode(ms->fdt, "/distance-map");
-+        qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible",
-                                 "numa-distance-map-v1");
--        qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
-+        qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix",
-                          dist_matrix, dist_matrix_size);
-         g_free(dist_matrix);
-     }
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-         g_free(clust_name);
-     }
--    riscv_socket_fdt_write_distance_matrix(mc, fdt);
-+    riscv_socket_fdt_write_distance_matrix(mc);
-     qemu_fdt_add_subnode(fdt, "/chosen");
-     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
-         }
-     }
--    riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
-+    riscv_socket_fdt_write_distance_matrix(mc);
- }
- static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
 --
-.39.0
+.45.1

-[PULL 27/37] hw/riscv/virt.c: simplify create_fdt()
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-'mem_size' and 'cmdline' aren't being used. Remove them.
+We're not setting (s/m)tval when triggering breakpoints of type 2
 (mcontrol) and 6 (mcontrol6). According to the debug spec section
 .7.12, "Match Control Type 6":
 "The Privileged Spec says that breakpoint exceptions that occur on
 instruction fetches, loads, or stores update the tval CSR with either
 zero or the faulting virtual address. The faulting virtual address for
 an mcontrol6 trigger with action = 0 is the address being accessed and
 which caused that trigger to fire."
 A similar text is also found in the Debug spec section 5.7.11 w.r.t.
 mcontrol.
 Note that what we're doing ATM is not violating the spec, but it's
 simple enough to set mtval/stval and it makes life easier for any
 software that relies on this info.
 Given that we always use action = 0, save the faulting address for the
 mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
 used as as scratch area for traps with address information. 'tval' is
 then set during riscv_cpu_do_interrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 5 ++---
+ target/riscv/cpu_helper.c | 1 +
-file changed, 2 insertions(+), 3 deletions(-)
+ target/riscv/debug.c      | 3 +++
 files changed, 4 insertions(+)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
- }
+             tval = env->bins;
+             break;
- static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+         case RISCV_EXCP_BREAKPOINT:
--                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
++            tval = env->badaddr;
-+                       bool is_32_bit)
+             if (cs->watchpoint_hit) {
- {
+                 tval = cs->watchpoint_hit->hitaddr;
-     MachineState *mc = MACHINE(s);
+                 cs->watchpoint_hit = NULL;
-     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+index XXXXXXX..XXXXXXX 100644
-     virt_flash_map(s, system_memory);
+--- a/target/riscv/debug.c
++++ b/target/riscv/debug.c
-     /* create device tree */
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
--    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
--               riscv_is_32bit(&s->soc[0]));
+                     /* check U/S/M bit against current privilege level */
-+    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]));
+                     if ((ctrl >> 3) & BIT(env->priv)) {
++                        env->badaddr = pc;
-     s->machine_done.notify = virt_machine_done;
+                         return true;
-     qemu_add_machine_init_done_notifier(&s->machine_done);
+                     }
                  }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                      if (env->virt_enabled) {
                          /* check VU/VS bit against current privilege level */
                          if ((ctrl >> 23) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      } else {
                          /* check U/S/M bit against current privilege level */
                          if ((ctrl >> 3) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      }
 --
-.39.0
+.45.1

-[PULL 26/37] hw/riscv/spike.c: simplify create_fdt()
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-'mem_size' and 'cmdline' are unused.
+Privileged spec section 4.1.9 mentions:
 "When a trap is taken into S-mode, stval is written with
 exception-specific information to assist software in handling the trap.
 (...)
 If stval is written with a nonzero value when a breakpoint,
 address-misaligned, access-fault, or page-fault exception occurs on an
 instruction fetch, load, or store, then stval will contain the faulting
 virtual address."
 A similar text is found for mtval in section 3.1.16.
 Setting mtval/stval in this scenario is optional, but some softwares read
 these regs when handling ebreaks.
 Write 'badaddr' in all ebreak breakpoints to write the appropriate
 'tval' during riscv_do_cpu_interrrupt().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/spike.c | 4 +---
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
-file changed, 1 insertion(+), 3 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
-+++ b/hw/riscv/spike.c
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
- };
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
- static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+     } else {
--                       uint64_t mem_size, const char *cmdline,
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
-                        bool is_32_bit, bool htif_custom_base)
++                      offsetof(CPURISCVState, badaddr));
- {
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
      void *fdt;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      }
+     return true;
      /* Create device tree */
 -    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 -               riscv_is_32bit(&s->soc[0]), htif_custom_base);
 +    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
      /* Load kernel */
      if (machine->kernel_filename) {
 --
-.39.0
+.45.1

-[PULL 32/37] target/riscv: Fix up masking of vsip/vsie accesses
+[PULL 10/28] target/riscv: Add support for Zve32x extension
-From: Andrew Bresticker <abrestic@rivosinc.com>
+From: Jason Chien <jason.chien@sifive.com>
-The current logic attempts to shift the VS-level bits into their correct
+Add support for Zve32x extension and replace some checks for Zve32f with
-position in mip while leaving the remaining bits in-tact. This is both
+Zve32x, since Zve32f depends on Zve32x.
 pointless and likely incorrect since one would expect that any new, future
 VS-level interrupts will get their own position in mip rather than sharing
 with their (H)S-level equivalent. Fix this, and make the logic more
 readable, by just making off the VS-level bits and shifting them into
 position.
-This also fixes reads of vsip, which would only ever report vsip.VSSIP
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-since the non-writable bits got masked off as well.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32")
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 35 +++++++++++------------------------
+ target/riscv/cpu_cfg.h                  |  1 +
-file changed, 11 insertions(+), 24 deletions(-)
+ target/riscv/cpu.c                      |  2 ++
  target/riscv/cpu_helper.c               |  2 +-
  target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zhinx;
+     bool ext_zhinxmin;
+     bool ext_zve32f;
++    bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
+     bool ext_zvbb;
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
+     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
+     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
++    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_helper.c
++++ b/target/riscv/cpu_helper.c
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
+     *cs_base = 0;
+-    if (cpu->cfg.ext_zve32f) {
++    if (cpu->cfg.ext_zve32x) {
+         /*
+          * If env->vl equals to VLMAX, we can use generic vector operation
+          * expanders (GVEC) to accerlate the vector operations.
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
-                                  uint64_t new_val, uint64_t wr_mask)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
-     RISCVException ret;
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
--    uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
-+    uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
+ #if !defined(CONFIG_USER_ONLY)
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
-     /* Bring VS-level bits to correct position */
+             return RISCV_EXCP_ILLEGAL_INST;
--    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
--    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
+index XXXXXXX..XXXXXXX 100644
--    new_val |= vsbits << 1;
+--- a/target/riscv/tcg/tcg-cpu.c
--    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
++++ b/target/riscv/tcg/tcg-cpu.c
--    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
--    wr_mask |= vsbits << 1;
+         return;
 +    new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
 +    wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
      ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
      if (ret_val) {
 -        rval &= mask;
 -        vsbits = rval & VS_MODE_INTERRUPTS;
 -        rval &= ~VS_MODE_INTERRUPTS;
 -        *ret_val = rval | (vsbits >> 1);
 +        *ret_val = (rval & mask) >> 1;
      }
-     return ret;
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-                                  uint64_t new_val, uint64_t wr_mask)
+-        return;
 +    /* The Zve32f extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
-     RISCVException ret;
+     TCGv s1, dst;
--    uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
-+    uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
+-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
++    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
-     /* Bring VS-level bits to correct position */
+         return false;
 -    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
 -    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
 -    new_val |= vsbits << 1;
 -    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
 -    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
 -    wr_mask |= vsbits << 1;
 -
 -    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
 +    new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
 +    wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
 +
 +    ret = rmw_mip64(env, csrno, &rval, new_val,
 +                    wr_mask & mask & vsip_writable_mask);
      if (ret_val) {
 -        rval &= mask;
 -        vsbits = rval & VS_MODE_INTERRUPTS;
 -        rval &= ~VS_MODE_INTERRUPTS;
 -        *ret_val = rval | (vsbits >> 1);
 +        *ret_val = (rval & mask) >> 1;
      }
-     return ret;
+@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
      TCGv dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
 --
-.39.0
+.45.1

-[PULL 24/37] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
+[PULL 11/28] target/riscv: Add support for Zve64x extension
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Jason Chien <jason.chien@sifive.com>
-All RISCV CPUs are setting cpu->cfg during their cpu_init() functions,
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
-meaning that there's no reason to skip all the misa validation and setup
+enabling Zve64x enables Zve32x according to their dependency.
 if misa_ext was set beforehand - especially since we're setting an
 updated value in set_misa() in the end.
-Put this code chunk into a new riscv_cpu_validate_set_extensions()
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
-helper and always execute it regardless of what the board set in
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-env->misa_ext.
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-This will put more responsibility in how each board is going to init
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-their attributes and extensions if they're not using the defaults.
+Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 It'll also allow realize() to do its job looking only at the extensions
 enabled per se, not corner cases that some CPUs might have, and we won't
 have to change multiple code paths to fix or change how extensions work.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Bin Meng <bmeng@tinylab.org>
 Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com>
 [ Changes by AF:
  - Rebase
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 399 +++++++++++++++++++++++----------------------
+ target/riscv/cpu_cfg.h     |  1 +
-file changed, 205 insertions(+), 194 deletions(-)
+ target/riscv/cpu.c         |  2 ++
  target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 files changed, 14 insertions(+), 6 deletions(-)
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu_cfg.h
++++ b/target/riscv/cpu_cfg.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
+     bool ext_zve32x;
+     bool ext_zve64f;
+     bool ext_zve64d;
++    bool ext_zve64x;
+     bool ext_zvbb;
+     bool ext_zvbc;
+     bool ext_zvkb;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-     }
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
- }
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+/*
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
-+ * Check consistency between chosen extensions while setting
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
-+ * cpu->cfg accordingly, doing a set_misa() in the end.
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
-+ */
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-+static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-+{
+     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
-+    CPURISCVState *env = &cpu->env;
+     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
-+    uint32_t ext = 0;
+     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
-+
++    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
-+    /* Do some ISA extension error checking */
+     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
-+    if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+     MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
-+                            cpu->cfg.ext_a && cpu->cfg.ext_f &&
+     MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
-+                            cpu->cfg.ext_d &&
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-+                            cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+index XXXXXXX..XXXXXXX 100644
-+        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+--- a/target/riscv/tcg/tcg-cpu.c
-+        cpu->cfg.ext_i = true;
++++ b/target/riscv/tcg/tcg-cpu.c
-+        cpu->cfg.ext_m = true;
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-+        cpu->cfg.ext_a = true;
-+        cpu->cfg.ext_f = true;
+     /* The Zve64d extension depends on the Zve64f extension */
-+        cpu->cfg.ext_d = true;
+     if (cpu->cfg.ext_zve64d) {
-+        cpu->cfg.ext_icsr = true;
++        if (!riscv_has_ext(env, RVD)) {
-+        cpu->cfg.ext_ifencei = true;
++            error_setg(errp, "Zve64d/V extensions require D extension");
 +    }
 +
 +    if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 +        error_setg(errp,
 +                   "I and E extensions are incompatible");
 +        return;
 +    }
 +
 +    if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 +        error_setg(errp,
 +                   "Either I or E extension must be set");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
 +        error_setg(errp,
 +                   "Setting S extension without U extension is illegal");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
 +        error_setg(errp,
 +                   "H depends on an I base integer ISA with 32 x registers");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
 +        error_setg(errp, "H extension implicitly requires S-mode");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
 +        error_setg(errp, "F extension requires Zicsr");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
 +        error_setg(errp, "Zawrs extension requires A extension");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
 +        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
 +        error_setg(errp, "D extension requires F extension");
 +        return;
 +    }
 +
 +    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
 +        error_setg(errp, "V extension requires D extension");
 +        return;
 +    }
 +
 +    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
 +        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +        return;
 +    }
 +
 +    /* Set the ISA extensions, checks should have happened above */
 +    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
 +        cpu->cfg.ext_zhinxmin) {
 +        cpu->cfg.ext_zfinx = true;
 +    }
 +
 +    if (cpu->cfg.ext_zfinx) {
 +        if (!cpu->cfg.ext_icsr) {
 +            error_setg(errp, "Zfinx extension requires Zicsr");
 +            return;
 +        }
-+        if (cpu->cfg.ext_f) {
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
 +            error_setg(errp,
 +                "Zfinx cannot be supported together with F extension");
 +            return;
 +        }
 +    }
 +
 +    if (cpu->cfg.ext_zk) {
 +        cpu->cfg.ext_zkn = true;
 +        cpu->cfg.ext_zkr = true;
 +        cpu->cfg.ext_zkt = true;
 +    }
 +
 +    if (cpu->cfg.ext_zkn) {
 +        cpu->cfg.ext_zbkb = true;
 +        cpu->cfg.ext_zbkc = true;
 +        cpu->cfg.ext_zbkx = true;
 +        cpu->cfg.ext_zkne = true;
 +        cpu->cfg.ext_zknd = true;
 +        cpu->cfg.ext_zknh = true;
 +    }
 +
 +    if (cpu->cfg.ext_zks) {
 +        cpu->cfg.ext_zbkb = true;
 +        cpu->cfg.ext_zbkc = true;
 +        cpu->cfg.ext_zbkx = true;
 +        cpu->cfg.ext_zksed = true;
 +        cpu->cfg.ext_zksh = true;
 +    }
 +
 +    if (cpu->cfg.ext_i) {
 +        ext |= RVI;
 +    }
 +    if (cpu->cfg.ext_e) {
 +        ext |= RVE;
 +    }
 +    if (cpu->cfg.ext_m) {
 +        ext |= RVM;
 +    }
 +    if (cpu->cfg.ext_a) {
 +        ext |= RVA;
 +    }
 +    if (cpu->cfg.ext_f) {
 +        ext |= RVF;
 +    }
 +    if (cpu->cfg.ext_d) {
 +        ext |= RVD;
 +    }
 +    if (cpu->cfg.ext_c) {
 +        ext |= RVC;
 +    }
 +    if (cpu->cfg.ext_s) {
 +        ext |= RVS;
 +    }
 +    if (cpu->cfg.ext_u) {
 +        ext |= RVU;
 +    }
 +    if (cpu->cfg.ext_h) {
 +        ext |= RVH;
 +    }
 +    if (cpu->cfg.ext_v) {
 +        int vext_version = VEXT_VERSION_1_00_0;
 +        ext |= RVV;
 +        if (!is_power_of_2(cpu->cfg.vlen)) {
 +            error_setg(errp,
 +                    "Vector extension VLEN must be power of 2");
 +            return;
 +        }
 +        if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 +            error_setg(errp,
 +                    "Vector extension implementation only supports VLEN "
 +                    "in the range [128, %d]", RV_VLEN_MAX);
 +            return;
 +        }
 +        if (!is_power_of_2(cpu->cfg.elen)) {
 +            error_setg(errp,
 +                    "Vector extension ELEN must be power of 2");
 +            return;
 +        }
 +    if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
 +        error_setg(errp,
 +                "Vector extension implementation only supports ELEN "
 +                "in the range [8, 64]");
 +        return;
 +    }
 +    if (cpu->cfg.vext_spec) {
 +        if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
 +            vext_version = VEXT_VERSION_1_00_0;
 +        } else {
 +            error_setg(errp,
 +                   "Unsupported vector spec version '%s'",
 +                   cpu->cfg.vext_spec);
 +            return;
 +        }
 +    } else {
 +        qemu_log("vector version is not specified, "
 +                 "use the default value v1.0\n");
 +    }
 +    set_vext_version(env, vext_version);
 +    }
 +    if (cpu->cfg.ext_j) {
 +        ext |= RVJ;
 +    }
 +
 +    set_misa(env, env->misa_mxl, ext);
 +}
 +
  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  {
      CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      }
-     assert(env->misa_mxl_max == env->misa_mxl);
+-    /* The Zve64f extension depends on the Zve32f extension */
--    /* If only MISA_EXT is unset for misa, then set it from properties */
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
--    if (env->misa_ext == 0) {
+     if (cpu->cfg.ext_zve64f) {
--        uint32_t ext = 0;
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
--
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 -        /* Do some ISA extension error checking */
 -        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
 -                                cpu->cfg.ext_a && cpu->cfg.ext_f &&
 -                                cpu->cfg.ext_d &&
 -                                cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
 -            warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
 -            cpu->cfg.ext_i = true;
 -            cpu->cfg.ext_m = true;
 -            cpu->cfg.ext_a = true;
 -            cpu->cfg.ext_f = true;
 -            cpu->cfg.ext_d = true;
 -            cpu->cfg.ext_icsr = true;
 -            cpu->cfg.ext_ifencei = true;
 -        }
 -
 -        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 -            error_setg(errp,
 -                       "I and E extensions are incompatible");
 -            return;
 -        }
 -
 -        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 -            error_setg(errp,
 -                       "Either I or E extension must be set");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
 -            error_setg(errp,
 -                       "Setting S extension without U extension is illegal");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
 -            error_setg(errp,
 -                       "H depends on an I base integer ISA with 32 x registers");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
 -            error_setg(errp, "H extension implicitly requires S-mode");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
 -            error_setg(errp, "F extension requires Zicsr");
 -            return;
 -        }
 -
 -        if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
 -            error_setg(errp, "Zawrs extension requires A extension");
 -            return;
 -        }
 -
 -        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
 -            error_setg(errp, "Zfh/Zfhmin extensions require F extension");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
 -            error_setg(errp, "D extension requires F extension");
 -            return;
 -        }
 -
 -        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
 -            error_setg(errp, "V extension requires D extension");
 -            return;
 -        }
 -
 -        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
 -            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 -            return;
 -        }
 -
 -        /* Set the ISA extensions, checks should have happened above */
 -        if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
 -            cpu->cfg.ext_zhinxmin) {
 -            cpu->cfg.ext_zfinx = true;
 -        }
 -
 -        if (cpu->cfg.ext_zfinx) {
 -            if (!cpu->cfg.ext_icsr) {
 -                error_setg(errp, "Zfinx extension requires Zicsr");
 -                return;
 -            }
 -            if (cpu->cfg.ext_f) {
 -                error_setg(errp,
 -                    "Zfinx cannot be supported together with F extension");
 -                return;
 -            }
 -        }
 -
 -        if (cpu->cfg.ext_zk) {
 -            cpu->cfg.ext_zkn = true;
 -            cpu->cfg.ext_zkr = true;
 -            cpu->cfg.ext_zkt = true;
 -        }
 -
 -        if (cpu->cfg.ext_zkn) {
 -            cpu->cfg.ext_zbkb = true;
 -            cpu->cfg.ext_zbkc = true;
 -            cpu->cfg.ext_zbkx = true;
 -            cpu->cfg.ext_zkne = true;
 -            cpu->cfg.ext_zknd = true;
 -            cpu->cfg.ext_zknh = true;
 -        }
 -
 -        if (cpu->cfg.ext_zks) {
 -            cpu->cfg.ext_zbkb = true;
 -            cpu->cfg.ext_zbkc = true;
 -            cpu->cfg.ext_zbkx = true;
 -            cpu->cfg.ext_zksed = true;
 -            cpu->cfg.ext_zksh = true;
 -        }
 -
 -        if (cpu->cfg.ext_i) {
 -            ext |= RVI;
 -        }
 -        if (cpu->cfg.ext_e) {
 -            ext |= RVE;
 -        }
 -        if (cpu->cfg.ext_m) {
 -            ext |= RVM;
 -        }
 -        if (cpu->cfg.ext_a) {
 -            ext |= RVA;
 -        }
 -        if (cpu->cfg.ext_f) {
 -            ext |= RVF;
 -        }
 -        if (cpu->cfg.ext_d) {
 -            ext |= RVD;
 -        }
 -        if (cpu->cfg.ext_c) {
 -            ext |= RVC;
 -        }
 -        if (cpu->cfg.ext_s) {
 -            ext |= RVS;
 -        }
 -        if (cpu->cfg.ext_u) {
 -            ext |= RVU;
 -        }
 -        if (cpu->cfg.ext_h) {
 -            ext |= RVH;
 -        }
 -        if (cpu->cfg.ext_v) {
 -            int vext_version = VEXT_VERSION_1_00_0;
 -            ext |= RVV;
 -            if (!is_power_of_2(cpu->cfg.vlen)) {
 -                error_setg(errp,
 -                        "Vector extension VLEN must be power of 2");
 -                return;
 -            }
 -            if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 -                error_setg(errp,
 -                        "Vector extension implementation only supports VLEN "
 -                        "in the range [128, %d]", RV_VLEN_MAX);
 -                return;
 -            }
 -            if (!is_power_of_2(cpu->cfg.elen)) {
 -                error_setg(errp,
 -                        "Vector extension ELEN must be power of 2");
 -                return;
 -            }
 -            if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
 -                error_setg(errp,
 -                        "Vector extension implementation only supports ELEN "
 -                        "in the range [8, 64]");
 -                return;
 -            }
 -            if (cpu->cfg.vext_spec) {
 -                if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
 -                    vext_version = VEXT_VERSION_1_00_0;
 -                } else {
 -                    error_setg(errp,
 -                           "Unsupported vector spec version '%s'",
 -                           cpu->cfg.vext_spec);
 -                    return;
 -                }
 -            } else {
 -                qemu_log("vector version is not specified, "
 -                         "use the default value v1.0\n");
 -            }
 -            set_vext_version(env, vext_version);
 -        }
 -        if (cpu->cfg.ext_j) {
 -            ext |= RVJ;
 -        }
 -
 -        set_misa(env, env->misa_mxl, ext);
 +    riscv_cpu_validate_set_extensions(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return;
      }
- #ifndef CONFIG_USER_ONLY
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
 -        error_setg(errp, "Zve64d/V extensions require D extension");
 -        return;
 +    /* The Zve64x extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve64x) {
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      /* The Zve32f extension depends on the Zve32x extension */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          return;
      }
 -    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
 +    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
          error_setg(
              errp,
 -            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
 +            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
          return;
      }
 --
-.39.0
+.45.1

-[PULL 34/37] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Jason Chien <jason.chien@sifive.com>
-We failed to update this with the w^x split, so misses the fact
+In current implementation, the gdbstub allows reading vector registers
-that true pc-relative offsets are usually small.
+only if V extension is supported. However, all vector extensions and
 vector crypto extensions have the vector registers and they all depend
 on Zve32x. The gdbstub should check for Zve32x instead.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org>
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- tcg/riscv/tcg-target.c.inc | 2 +-
+ target/riscv/gdbstub.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
+--- a/target/riscv/gdbstub.c
-+++ b/tcg/riscv/tcg-target.c.inc
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
-     intptr_t imm12 = sextreg(offset, 0, 12);
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+);
-     if (offset != imm12) {
+     }
--        intptr_t diff = offset - (uintptr_t)s->code_ptr;
+-    if (env->misa_ext & RVV) {
-+        intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
++    if (cpu->cfg.ext_zve32x) {
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
-         if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
+                                  riscv_gdb_set_vector,
-             imm12 = sextreg(diff, 0, 12);
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
 --
-.39.0
+.45.1

-[PULL 21/37] hw/riscv/boot.c: use MachineState in riscv_load_initrd()
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
-retrieved by the MachineState object for all callers.
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
 agnostic policy.
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+However, this function can't deal the big endian situation. This patch fixes
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+the problem by adding handling of such case.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h    | 3 +--
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
- hw/riscv/boot.c            | 6 ++++--
+file changed, 22 insertions(+)
  hw/riscv/microchip_pfsoc.c | 3 +--
  hw/riscv/sifive_u.c        | 3 +--
  hw/riscv/spike.c           | 3 +--
  hw/riscv/virt.c            | 3 +--
 files changed, 9 insertions(+), 12 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/vector_internals.c
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/vector_internals.c
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
- target_ulong riscv_load_kernel(const char *kernel_filename,
+     if (tot - cnt == 0) {
-                                target_ulong firmware_end_addr,
+         return ;
-                                symbol_fn_t sym_cb);
+     }
--void riscv_load_initrd(const char *filename, uint64_t mem_size,
++
--                       uint64_t kernel_entry, void *fdt);
++    if (HOST_BIG_ENDIAN) {
-+void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
++        /*
- uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
++         * Deal the situation when the elements are insdie
- void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
++         * only one uint64 block including setting the
-                                hwaddr saddr,
++         * masked-off element.
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
++         */
-index XXXXXXX..XXXXXXX 100644
++        if (((tot - 1) ^ cnt) < 8) {
---- a/hw/riscv/boot.c
++            memset(base + H1(tot - 1), -1, tot - cnt);
-+++ b/hw/riscv/boot.c
++            return;
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
++        }
-     exit(1);
++        /*
 +         * Otherwise, at least cross two uint64_t blocks.
 +         * Set first unaligned block.
 +         */
 +        if (cnt % 8 != 0) {
 +            uint32_t j = ROUND_UP(cnt, 8);
 +            memset(base + H1(j - 1), -1, j - cnt);
 +            cnt = j;
 +        }
 +        /* Set other 64bit aligend blocks */
 +    }
      memset(base + cnt, -1, tot - cnt);
  }
--void riscv_load_initrd(const char *filename, uint64_t mem_size,
--                       uint64_t kernel_entry, void *fdt)
-+void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
- {
-+    const char *filename = machine->initrd_filename;
-+    uint64_t mem_size = machine->ram_size;
-+    void *fdt = machine->fdt;
-     hwaddr start, end;
-     ssize_t size;
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
-+++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-                                          kernel_start_addr, NULL);
-         if (machine->initrd_filename) {
--            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
--                              kernel_entry, machine->fdt);
-+            riscv_load_initrd(machine, kernel_entry);
-         }
-         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-                                          kernel_start_addr, NULL);
-         if (machine->initrd_filename) {
--            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
--                              kernel_entry, machine->fdt);
-+            riscv_load_initrd(machine, kernel_entry);
-         }
-         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-                                          htif_symbol_callback);
-         if (machine->initrd_filename) {
--            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
--                              kernel_entry, machine->fdt);
-+            riscv_load_initrd(machine, kernel_entry);
-         }
-         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
-                                          kernel_start_addr, NULL);
-         if (machine->initrd_filename) {
--            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
--                              kernel_entry, machine->fdt);
-+            riscv_load_initrd(machine, kernel_entry);
-         }
-         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 --
-.39.0
+.45.1

-[PULL 13/37] target/riscv/cpu.c: Fix elen check
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Dongxue Zhang <elta.era@gmail.com>
+From: Yangyu Chen <cyy@cyyself.name>
-The elen check should be cpu->cfg.elen in range [8, 64].
+This code has a typo that writes zvkb to zvkg, causing users can't
 enable zvkb through the config. This patch gets this fixed.
-Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
-Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <167236721596.15277.2653405273227256289-0@git.sr.ht>
+Reviewed-by: Max Chou <max.chou@sifive.com>
-[ Changes by AF:
+Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
- - Tidy up commit message
+Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
-]
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-                         "Vector extension ELEN must be power of 2");
+     /* Vector cryptography extensions */
-                 return;
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
-             }
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
--            if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-+            if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
-                 error_setg(errp,
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
-                         "Vector extension implementation only supports ELEN "
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
-                         "in the range [8, 64]");
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
 --
-.39.0
+.45.1

-[PULL 09/37] hw/riscv/boot.c: make riscv_find_firmware() static
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-The only caller is riscv_find_and_load_firmware(), which is in the same
+In this patch, we modify the decoder to be a freely composable data
-file.
+structure instead of a hardcoded one. It can be dynamically builded up
 according to the extensions.
 This approach has several benefits:
 . Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
 Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com>
 Message-Id: <20221229091828.1945072-10-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h |  1 -
+ target/riscv/cpu.h         |  1 +
- hw/riscv/boot.c         | 44 ++++++++++++++++++++---------------------
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
-files changed, 22 insertions(+), 23 deletions(-)
+ target/riscv/cpu.c         |  1 +
  target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/cpu.h
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-                                           const char *default_machine_firmware,
+     uint32_t pmu_avail_ctrs;
-                                           hwaddr firmware_load_addr,
+     /* Mapping of events to counters */
-                                           symbol_fn_t sym_cb);
+     GHashTable *pmu_event_ctr_map;
--char *riscv_find_firmware(const char *firmware_filename);
++    const GPtrArray *decoders;
- target_ulong riscv_load_firmware(const char *firmware_filename,
+ };
-                                  hwaddr firmware_load_addr,
-                                  symbol_fn_t sym_cb);
+ /**
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
+--- a/target/riscv/tcg/tcg-cpu.h
-+++ b/hw/riscv/boot.c
++++ b/target/riscv/tcg/tcg-cpu.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
  void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 +struct DisasContext;
 +struct RISCVCPUConfig;
 +typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
 +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +
 +extern const size_t decoder_table_size;
 +
 +extern const RISCVDecoder decoder_table[];
 +
 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
 +
  #endif
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
              error_propagate(errp, local_err);
              return;
          }
 +        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
      } else if (kvm_enabled()) {
          riscv_kvm_cpu_finalize_features(cpu, &local_err);
          if (local_err != NULL) {
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
      }
  }
-+static char *riscv_find_firmware(const char *firmware_filename)
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
 +{
-+    char *filename;
++    GPtrArray *dynamic_decoders;
-+
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
-+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
++    for (size_t i = 0; i < decoder_table_size; ++i) {
-+    if (filename == NULL) {
++        if (decoder_table[i].guard_func &&
-+        if (!qtest_enabled()) {
++            decoder_table[i].guard_func(&cpu->cfg)) {
-+            /*
++            g_ptr_array_add(dynamic_decoders,
-+             * We only ship OpenSBI binary bios images in the QEMU source.
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
 +             * For machines that use images other than the default bios,
 +             * running QEMU test will complain hence let's suppress the error
 +             * report for QEMU testing.
 +             */
 +            error_report("Unable to load the RISC-V firmware \"%s\"",
 +                         firmware_filename);
 +            exit(1);
 +        }
 +    }
 +
-+    return filename;
++    cpu->decoders = dynamic_decoders;
 +}
 +
- target_ulong riscv_find_and_load_firmware(MachineState *machine,
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
-                                           const char *default_machine_firmware,
+ {
-                                           hwaddr firmware_load_addr,
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-     return firmware_end_addr;
+index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-info.c.inc"
  #undef  HELPER_H
 +#include "tcg/tcg-cpu.h"
 +
  /* global register indices */
  static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
  static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* FRM is known to contain a valid value. */
      bool frm_valid;
      bool insn_start_updated;
 +    const GPtrArray *decoders;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
      return (first_word & 3) == 3 ? 4 : 2;
  }
--char *riscv_find_firmware(const char *firmware_filename)
++const RISCVDecoder decoder_table[] = {
--{
++    { always_true_p, decode_insn32 },
--    char *filename;
++    { has_xthead_p, decode_xthead},
 +    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
 +};
 +
 +const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
 +
  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
 -    /*
 -     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
--    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
+     ctx->virt_inst_excp = false;
--    if (filename == NULL) {
+     ctx->cur_insn_len = insn_len(opcode);
--        if (!qtest_enabled()) {
+     /* Check for compressed insn */
--            /*
+@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
--             * We only ship OpenSBI binary bios images in the QEMU source.
+                                              ctx->base.pc_next + 2));
--             * For machines that use images other than the default bios,
+         ctx->opcode = opcode32;
--             * running QEMU test will complain hence let's suppress the error
--             * report for QEMU testing.
+-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
--             */
+-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
--            error_report("Unable to load the RISC-V firmware \"%s\"",
+-                decoders[i].decode_func(ctx, opcode32)) {
--                         firmware_filename);
++        for (guint i = 0; i < ctx->decoders->len; ++i) {
--            exit(1);
++            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
--        }
++            if (func(ctx, opcode32)) {
--    }
+                 return;
--
+             }
--    return filename;
+         }
--}
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
+     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
- target_ulong riscv_load_firmware(const char *firmware_filename,
+     ctx->zero = tcg_constant_tl(0);
-                                  hwaddr firmware_load_addr,
+     ctx->virt_inst_excp = false;
-                                  symbol_fn_t sym_cb)
++    ctx->decoders = cpu->decoders;
  }
  static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 --
-.39.0
+.45.1

-[PULL 23/37] target/riscv/cpu: set cpu->cfg in register_cpu_props()
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-There is an informal contract between the cpu_init() functions and
+The th.sxstatus CSR can be used to identify available custom extension
-riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the
+on T-Head CPUs. The CSR is documented here:
-default settings were loaded via register_cpu_props() and do validations
+  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
 to set env.misa_ext. If it's not zero, skip this whole process and
 assume that the board somehow did everything.
-At this moment, all SiFive CPUs are setting a non-zero misa_ext during
+An important property of this patch is, that the th.sxstatus MAEE field
-their cpu_init() and skipping a good chunk of riscv_cpu_realize().  This
+is not set (indicating that XTheadMae is not available).
-causes problems when the code being skipped in riscv_cpu_realize()
+XTheadMae is a memory attribute extension (similar to Svpbmt) which is
-contains fixes or assumptions that affects all CPUs, meaning that SiFive
+implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
-CPUs are missing out.
+in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-To allow this code to not be skipped anymore, all the cpu->cfg.ext_*
+Further context can be found on the list:
-attributes needs to be set during cpu_init() time. At this moment this
+https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
 is being done in register_cpu_props(). The SiFive boards are setting
 their own extensions during cpu_init() though, meaning that they don't
 want all the defaults from register_cpu_props().
-Let's move the contract between *_cpu_init() and riscv_cpu_realize() to
+Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 register_cpu_props(). Inside this function we'll check if
 cpu->env.misa_ext was set and, if that's the case, set all relevant
 cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case
 as is today, i.e. loading all the defaults from riscv_cpu_extensions[].
 register_cpu_props() can then be called by all the cpu_init() functions,
 including the SiFive ones. This will make all CPUs behave more in line
 with what riscv_cpu_realize() expects.
 This will also make the cpu_init() functions even more alike, but at this
 moment we would need some design changes in how we're initializing
 extensions/attributes (e.g. some CPUs are setting cfg options after
 register_cpu_props(), so we can't simply add the function to a common
 post_init() hook)  to make a common cpu_init() code across all CPUs.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com>
+Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h |  4 ++++
+ MAINTAINERS              |  1 +
- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
+ target/riscv/cpu.h       |  3 ++
-files changed, 44 insertions(+)
+ target/riscv/cpu.c       |  1 +
  target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
  target/riscv/meson.build |  1 +
 files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
+ S: Supported
+ F: target/riscv/insn_trans/trans_xthead.c.inc
+ F: target/riscv/xthead*.decode
++F: target/riscv/th_*
+ F: disas/riscv-xthead*
+ RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
+ uint8_t satp_mode_max_from_map(uint32_t map);
- #define RV(x) ((target_ulong)1 << (x - 'A'))
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
-+/*
++/* Implemented in th_csr.c */
-+ * Consider updating register_cpu_props() when adding
++void th_register_custom_csrs(RISCVCPU *cpu);
-+ * new MISA bits here.
++
-+ */
+ #endif /* RISCV_CPU_H */
  #define RVI RV('I')
  #define RVE RV('E') /* E and I are mutually exclusive */
  #define RVM RV('M')
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
- {
+     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
+ #ifndef CONFIG_USER_ONLY
-     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-+    register_cpu_props(DEVICE(obj));
++    th_register_custom_csrs(cpu);
-     set_priv_version(env, PRIV_VERSION_1_10_0);
+ #endif
- }
+     /* inherited from parent obj via riscv_cpu_init() */
-@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
+diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
-     RISCVCPU *cpu = RISCV_CPU(obj);
+new file mode 100644
+index XXXXXXX..XXXXXXX
-     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+--- /dev/null
-+    register_cpu_props(DEVICE(obj));
++++ b/target/riscv/th_csr.c
-     set_priv_version(env, PRIV_VERSION_1_10_0);
+@@ -XXX,XX +XXX,XX @@
      cpu->cfg.mmu = false;
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    register_cpu_props(DEVICE(obj));
      set_priv_version(env, PRIV_VERSION_1_10_0);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
      RISCVCPU *cpu = RISCV_CPU(obj);
      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
 +    register_cpu_props(DEVICE(obj));
      set_priv_version(env, PRIV_VERSION_1_10_0);
      cpu->cfg.mmu = false;
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
      RISCVCPU *cpu = RISCV_CPU(obj);
      set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
 +    register_cpu_props(DEVICE(obj));
      set_priv_version(env, PRIV_VERSION_1_11_0);
      cpu->cfg.mmu = false;
      cpu->cfg.epmp = true;
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
      RISCVCPU *cpu = RISCV_CPU(obj);
      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
 +    register_cpu_props(DEVICE(obj));
      set_priv_version(env, PRIV_VERSION_1_10_0);
      cpu->cfg.mmu = false;
  }
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
      DEFINE_PROP_END_OF_LIST(),
  };
 +/*
-+ * Register CPU props based on env.misa_ext. If a non-zero
++ * T-Head-specific CSRs.
-+ * value was set, register only the required cpu->cfg.ext_*
++ *
-+ * properties and leave. env.misa_ext = 0 means that we want
++ * Copyright (c) 2024 VRULL GmbH
-+ * all the default properties to be registered.
++ *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
- static void register_cpu_props(DeviceState *dev)
- {
-+    RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
-+    uint32_t misa_ext = cpu->env.misa_ext;
-     Property *prop;
-+    /*
-+     * If misa_ext is not zero, set cfg properties now to
-+     * allow them to be read during riscv_cpu_realize()
-+     * later on.
-+     */
-+    if (cpu->env.misa_ext != 0) {
-+        cpu->cfg.ext_i = misa_ext & RVI;
-+        cpu->cfg.ext_e = misa_ext & RVE;
-+        cpu->cfg.ext_m = misa_ext & RVM;
-+        cpu->cfg.ext_a = misa_ext & RVA;
-+        cpu->cfg.ext_f = misa_ext & RVF;
-+        cpu->cfg.ext_d = misa_ext & RVD;
-+        cpu->cfg.ext_v = misa_ext & RVV;
-+        cpu->cfg.ext_c = misa_ext & RVC;
-+        cpu->cfg.ext_s = misa_ext & RVS;
-+        cpu->cfg.ext_u = misa_ext & RVU;
-+        cpu->cfg.ext_h = misa_ext & RVH;
-+        cpu->cfg.ext_j = misa_ext & RVJ;
 +
-+        /*
++#include "qemu/osdep.h"
-+         * We don't want to set the default riscv_cpu_extensions
++#include "cpu.h"
-+         * in this case.
++#include "cpu_vendorid.h"
-+         */
++
-+        return;
++#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
 +    if (riscv_has_ext(env, RVS)) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
-     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
++    return RISCV_EXCP_ILLEGAL_INST;
-         qdev_property_add_static(dev, prop);
++}
-     }
++
 +static int test_thead_mvendorid(RISCVCPU *cpu)
 +{
 +    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
 +        return -1;
 +    }
 +
 +    return 0;
 +}
 +
 +static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
 +{
 +    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
 +static riscv_csr th_csr_list[] = {
 +    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
 +};
 +
 +void th_register_custom_csrs(RISCVCPU *cpu)
 +{
 +    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
 +        int csrno = th_csr_list[i].csrno;
 +        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
 +        if (!th_csr_list[i].insertion_test(cpu)) {
 +            riscv_set_csr_ops(csrno, csr_ops);
 +        }
 +    }
 +}
 diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/meson.build
 +++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
    'monitor.c',
    'machine.c',
    'pmu.c',
 +  'th_csr.c',
    'time_helper.c',
    'riscv-qmp-cmds.c',
  ))
 --
-.39.0
+.45.1

-[PULL 10/37] hw/riscv/boot.c: introduce riscv_default_firmware_name()
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Max Chou <max.chou@sifive.com>
-Some boards are duplicating the 'riscv_find_and_load_firmware' call
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-because the 32 and 64 bits images have different names. Create
+instructions will be affected by Zvfhmin extension.
-a function to handle this detail instead of hardcoding it in the boards.
+And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
 conversions of
-Ideally we would bake this logic inside riscv_find_and_load_firmware(),
+* From 1*SEW(16/32) to 2*SEW(32/64)
-or even create a riscv_load_default_firmware(), but at this moment we
+* From 2*SEW(32/64) to 1*SEW(16/32)
 cannot infer whether the machine is running 32 or 64 bits without
 accessing RISCVHartArrayState, which in turn can't be accessed via the
 common code from boot.c. In the end we would exchange 'firmware_name'
 for a flag with riscv_is_32bit(), which isn't much better than what we
 already have today.
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+Signed-off-by: Max Chou <max.chou@sifive.com>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com>
 Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h |  1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
- hw/riscv/boot.c         |  9 +++++++++
+file changed, 18 insertions(+), 2 deletions(-)
  hw/riscv/sifive_u.c     | 11 ++++-------
  hw/riscv/spike.c        | 14 +++++---------
  hw/riscv/virt.c         | 10 +++-------
 files changed, 22 insertions(+), 23 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
                                            const char *default_machine_firmware,
                                            hwaddr firmware_load_addr,
                                            symbol_fn_t sym_cb);
 +const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
  target_ulong riscv_load_firmware(const char *firmware_filename,
                                   hwaddr firmware_load_addr,
                                   symbol_fn_t sym_cb);
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
      }
  }
-+const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
++static bool require_rvfmin(DisasContext *s)
 +{
-+    if (riscv_is_32bit(harts)) {
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+        return RISCV32_BIOS_BIN;
++        return false;
 +    }
 +
-+    return RISCV64_BIOS_BIN;
++    switch (s->sew) {
 +    case MO_16:
 +        return s->cfg_ptr->ext_zvfhmin;
 +    case MO_32:
 +        return s->cfg_ptr->ext_zve32f;
 +    default:
 +        return false;
 +    }
 +}
 +
- static char *riscv_find_firmware(const char *firmware_filename)
+ static bool require_scale_rvf(DisasContext *s)
  {
-     char *filename;
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      MemoryRegion *flash0 = g_new(MemoryRegion, 1);
      target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
      target_ulong firmware_end_addr, kernel_start_addr;
 +    const char *firmware_name;
      uint32_t start_addr_hi32 = 0x00000000;
      int i;
      uint32_t fdt_load_addr;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
          break;
      }
--    if (riscv_is_32bit(&s->soc.u_cpus)) {
+     switch (s->sew) {
--        firmware_end_addr = riscv_find_and_load_firmware(machine,
+-    case MO_8:
--                                    RISCV32_BIOS_BIN, start_addr, NULL);
+-        return s->cfg_ptr->ext_zvfhmin;
--    } else {
+     case MO_16:
--        firmware_end_addr = riscv_find_and_load_firmware(machine,
+         return s->cfg_ptr->ext_zve32f;
--                                    RISCV64_BIOS_BIN, start_addr, NULL);
+     case MO_32:
--    }
+@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
-+    firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
+ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
-+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+ {
-+                                                     start_addr, NULL);
+     return opfv_widen_check(s, a) &&
++           require_rvfmin(s) &&
-     if (machine->kernel_filename) {
+            require_scale_rvfmin(s) &&
-         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+            (s->sew != MO_8);
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+ }
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
---- a/hw/riscv/spike.c
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-+++ b/hw/riscv/spike.c
+ {
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
+     return opfv_narrow_check(s, a) &&
-     MemoryRegion *system_memory = get_system_memory();
++           require_rvfmin(s) &&
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+            require_scale_rvfmin(s) &&
-     target_ulong firmware_end_addr, kernel_start_addr;
+            (s->sew != MO_8);
-+    const char *firmware_name;
+ }
      uint32_t fdt_load_addr;
      uint64_t kernel_entry;
      char *soc_name;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                  mask_rom);
 -    if (riscv_is_32bit(&s->soc[0])) {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
 -                                    htif_symbol_callback);
 -    } else {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
 -                                    htif_symbol_callback);
 -    }
 +    firmware_name = riscv_default_firmware_name(&s->soc[0]);
 +    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 +                                                     memmap[SPIKE_DRAM].base,
 +                                                     htif_symbol_callback);
      /* Load kernel */
      if (machine->kernel_filename) {
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
      MachineState *machine = MACHINE(s);
      target_ulong start_addr = memmap[VIRT_DRAM].base;
      target_ulong firmware_end_addr, kernel_start_addr;
 +    const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
      uint32_t fdt_load_addr;
      uint64_t kernel_entry;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
          }
      }
 -    if (riscv_is_32bit(&s->soc[0])) {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV32_BIOS_BIN, start_addr, NULL);
 -    } else {
 -        firmware_end_addr = riscv_find_and_load_firmware(machine,
 -                                    RISCV64_BIOS_BIN, start_addr, NULL);
 -    }
 +    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 +                                                     start_addr, NULL);
      /*
       * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
 --
-.39.0
+.45.1

-[PULL 28/37] hw/riscv/sifive_u.c: simplify create_fdt()
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Max Chou <max.chou@sifive.com>
-'cmdline' isn't being used. Remove it.
+The require_scale_rvf function only checks the double width operator for
 the vector floating point widen instructions, so most of the widen
 checking functions need to add require_rvf for single width operator.
-A MachineState pointer is being retrieved via a MACHINE() macro calling
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
-qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev().
+integer to double width float, so the opfxv_widen_check function doesn’t
 need require_rvf for the single width operator(integer).
- 'mem_size' is being set as machine->ram_size by the caller. Retrieve it
+Signed-off-by: Max Chou <max.chou@sifive.com>
-via ms->ram_size.
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_u.c | 8 ++++----
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
-file changed, 4 insertions(+), 4 deletions(-)
+file changed, 5 insertions(+)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/riscv/sifive_u.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_u_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
- #define GEM_REVISION        0x10070109
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
  static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
 -                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
 +                       bool is_32_bit)
  {
--    MachineState *ms = MACHINE(qdev_get_machine());
+     return require_rvv(s) &&
-+    MachineState *ms = MACHINE(s);
++           require_rvf(s) &&
-+    uint64_t mem_size = ms->ram_size;
+            require_scale_rvf(s) &&
-     void *fdt;
+            (s->sew != MO_8) &&
-     int cpu, fdt_size;
+            vext_check_isa_ill(s) &&
-     uint32_t *cells;
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
+ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
-                           qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
+ {
+     return require_rvv(s) &&
-     /* create device tree */
++           require_rvf(s) &&
--    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+            require_scale_rvf(s) &&
--               riscv_is_32bit(&s->soc.u_cpus));
+            (s->sew != MO_8) &&
-+    create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
+            vext_check_isa_ill(s) &&
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
-     if (s->start_in_flash) {
+ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-         /*
+ {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
 --
-.39.0
+.45.1

-[PULL 35/37] target/riscv: Introduce helper_set_rounding_mode_chkfrm
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Max Chou <max.chou@sifive.com>
-The new helper always validates the contents of FRM, even
+The opfv_narrow_check needs to check the single width float operator by
-if the new rounding mode is not DYN.  This is required by
+require_rvf.
 the vector unit.
-Track whether we've validated FRM separately from whether
+Signed-off-by: Max Chou <max.chou@sifive.com>
 we've updated fp_status with a given rounding mode, so that
 we can elide calls correctly.
 This partially reverts d6c4d3f2a69 which attempted the to do
 the same thing, but with two calls to gen_set_rm(), which is
 both inefficient and tickles an assertion in decode_save_opc.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org>
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/helper.h                   |  1 +
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
- target/riscv/fpu_helper.c               | 37 +++++++++++++++++++++++++
+file changed, 1 insertion(+)
  target/riscv/translate.c                | 19 +++++++++++++
  target/riscv/insn_trans/trans_rvv.c.inc | 24 +++-------------
 files changed, 61 insertions(+), 20 deletions(-)
-diff --git a/target/riscv/helper.h b/target/riscv/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
-+++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
- /* Floating Point - rounding mode */
- DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
-+DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
- DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
- /* Floating Point - fused */
-diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/fpu_helper.c
-+++ b/target/riscv/fpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
-     set_float_rounding_mode(softrm, &env->fp_status);
- }
-+void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
-+{
-+    int softrm;
-+
-+    /* Always validate frm, even if rm != DYN. */
-+    if (unlikely(env->frm >= 5)) {
-+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    }
-+    if (rm == RISCV_FRM_DYN) {
-+        rm = env->frm;
-+    }
-+    switch (rm) {
-+    case RISCV_FRM_RNE:
-+        softrm = float_round_nearest_even;
-+        break;
-+    case RISCV_FRM_RTZ:
-+        softrm = float_round_to_zero;
-+        break;
-+    case RISCV_FRM_RDN:
-+        softrm = float_round_down;
-+        break;
-+    case RISCV_FRM_RUP:
-+        softrm = float_round_up;
-+        break;
-+    case RISCV_FRM_RMM:
-+        softrm = float_round_ties_away;
-+        break;
-+    case RISCV_FRM_ROD:
-+        softrm = float_round_to_odd;
-+        break;
-+    default:
-+        g_assert_not_reached();
-+    }
-+
-+    set_float_rounding_mode(softrm, &env->fp_status);
-+}
-+
- void helper_set_rod_rounding_mode(CPURISCVState *env)
- {
-     set_float_rounding_mode(float_round_to_odd, &env->fp_status);
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-     bool pm_base_enabled;
-     /* Use icount trigger for native debug */
-     bool itrigger;
-+    /* FRM is known to contain a valid value. */
-+    bool frm_valid;
-     /* TCG of the current insn_start */
-     TCGOp *insn_start;
- } DisasContext;
-@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
-         gen_helper_set_rod_rounding_mode(cpu_env);
-         return;
-     }
-+    if (rm == RISCV_FRM_DYN) {
-+        /* The helper will return only if frm valid. */
-+        ctx->frm_valid = true;
-+    }
-     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
-     decode_save_opc(ctx);
-     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
- }
-+static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
-+{
-+    if (ctx->frm == rm && ctx->frm_valid) {
-+        return;
-+    }
-+    ctx->frm = rm;
-+    ctx->frm_valid = true;
-+
-+    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
-+    decode_save_opc(ctx);
-+    gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
-+}
-+
- static int ex_plus_1(DisasContext *ctx, int nf)
- {
-     return nf + 1;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-                     int rm)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
  {
-     if (checkfn(s, a)) {
+     return opfv_narrow_check(s, a) &&
--        if (rm != RISCV_FRM_DYN) {
++           require_rvf(s) &&
--            gen_set_rm(s, RISCV_FRM_DYN);
+            require_scale_rvf(s) &&
--        }
+            (s->sew != MO_8);
--
+ }
          uint32_t data = 0;
          TCGLabel *over = gen_new_label();
 -        gen_set_rm(s, rm);
 +        gen_set_rm_chkfrm(s, rm);
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
  {                                                                  \
      if (CHECK(s, a)) {                                             \
 -        if (FRM != RISCV_FRM_DYN) {                                \
 -            gen_set_rm(s, RISCV_FRM_DYN);                          \
 -        }                                                          \
 -                                                                   \
          uint32_t data = 0;                                         \
          static gen_helper_gvec_3_ptr * const fns[2] = {            \
              gen_helper_##HELPER##_h,                               \
              gen_helper_##HELPER##_w,                               \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
 -        gen_set_rm(s, FRM);                                        \
 +        gen_set_rm_chkfrm(s, FRM);                                 \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
  {                                                                  \
      if (CHECK(s, a)) {                                             \
 -        if (FRM != RISCV_FRM_DYN) {                                \
 -            gen_set_rm(s, RISCV_FRM_DYN);                          \
 -        }                                                          \
 -                                                                   \
          uint32_t data = 0;                                         \
          static gen_helper_gvec_3_ptr * const fns[2] = {            \
              gen_helper_##HELPER##_h,                               \
              gen_helper_##HELPER##_w,                               \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
 -        gen_set_rm(s, FRM);                                        \
 +        gen_set_rm_chkfrm(s, FRM);                                 \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
  static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
  {                                                                  \
      if (opxfv_narrow_check(s, a)) {                                \
 -        if (FRM != RISCV_FRM_DYN) {                                \
 -            gen_set_rm(s, RISCV_FRM_DYN);                          \
 -        }                                                          \
 -                                                                   \
          uint32_t data = 0;                                         \
          static gen_helper_gvec_3_ptr * const fns[3] = {            \
              gen_helper_##HELPER##_b,                               \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
              gen_helper_##HELPER##_w,                               \
          };                                                         \
          TCGLabel *over = gen_new_label();                          \
 -        gen_set_rm(s, FRM);                                        \
 +        gen_set_rm_chkfrm(s, FRM);                                 \
          tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
          tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                     \
 --
-.39.0
+.45.1

-[PULL 12/37] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
-From: Bin Meng <bmeng@tinylab.org>
+From: Max Chou <max.chou@sifive.com>
-At present create_fdt() calls htif_uses_elf_symbols() to determine
+If the checking functions check both the single and double width
-whether to insert a <reg> property for the HTIF. This unfortunately
+operators at the same time, then the single width operator checking
-creates a hidden dependency to riscv_load_{firmware,kernel} that
+functions (require_rvf[min]) will check whether the SEW is 8.
 create_fdt() must be called after the ELF {firmware,kernel} image
 has been loaded.
-Decouple such dependency be adding a new parameter to create_fdt(),
+Signed-off-by: Max Chou <max.chou@sifive.com>
 whether custom HTIF base address is used. The flag will be set if
 non ELF {firmware,kernel} image is given by user.
 Signed-off-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Message-Id: <20221229091828.1945072-13-bmeng@tinylab.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/riscv_htif.h |  5 +--
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
- hw/char/riscv_htif.c         | 17 +++++-----
+file changed, 4 insertions(+), 12 deletions(-)
  hw/riscv/spike.c             | 61 ++++++++++++++++++++++++++++++------
 files changed, 59 insertions(+), 24 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/include/hw/char/riscv_htif.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
- void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
+     return require_rvv(s) &&
-     uint64_t st_size);
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
--/* Check if HTIF uses ELF symbols */
+-           (s->sew != MO_8) &&
--bool htif_uses_elf_symbols(void);
+            vext_check_isa_ill(s) &&
--
+            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
- /* legacy pre qom */
+ }
- HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
+@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
--                        uint64_t nonelf_base);
+     return require_rvv(s) &&
-+                        uint64_t nonelf_base, bool custom_base);
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
- #endif
+-           (s->sew != MO_8) &&
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
+            vext_check_isa_ill(s) &&
-index XXXXXXX..XXXXXXX 100644
+            vext_check_ds(s, a->rd, a->rs2, a->vm);
---- a/hw/char/riscv_htif.c
+ }
-+++ b/hw/char/riscv_htif.c
+@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
-@@ -XXX,XX +XXX,XX @@
+     return require_rvv(s) &&
- #define PK_SYS_WRITE            64
+            require_rvf(s) &&
+            require_scale_rvf(s) &&
- static uint64_t fromhost_addr, tohost_addr;
+-           (s->sew != MO_8) &&
--static int address_symbol_set;
+            vext_check_isa_ill(s) &&
+            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
- void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
+ }
-                           uint64_t st_size)
+@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
-     if (strcmp("fromhost", st_name) == 0) {
+     return opfv_widen_check(s, a) &&
--        address_symbol_set |= 1;
+            require_rvfmin(s) &&
-         fromhost_addr = st_value;
+-           require_scale_rvfmin(s) &&
-         if (st_size != 8) {
+-           (s->sew != MO_8);
-             error_report("HTIF fromhost must be 8 bytes");
++           require_scale_rvfmin(s);
-             exit(1);
+ }
-         }
-     } else if (strcmp("tohost", st_name) == 0) {
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
--        address_symbol_set |= 2;
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
          tohost_addr = st_value;
          if (st_size != 8) {
              error_report("HTIF tohost must be 8 bytes");
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
      .write = htif_mm_write,
  };
 -bool htif_uses_elf_symbols(void)
 -{
 -    return (address_symbol_set == 3) ? true : false;
 -}
 -
  HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
 -                        uint64_t nonelf_base)
 +                        uint64_t nonelf_base, bool custom_base)
  {
-     uint64_t base, size, tohost_offset, fromhost_offset;
+     return opfv_narrow_check(s, a) &&
+            require_rvfmin(s) &&
--    if (!htif_uses_elf_symbols()) {
+-           require_scale_rvfmin(s) &&
-+    if (custom_base) {
+-           (s->sew != MO_8);
-         fromhost_addr = nonelf_base;
++           require_scale_rvfmin(s);
-         tohost_addr = nonelf_base + 8;
+ }
-+    } else {
-+        if (!fromhost_addr || !tohost_addr) {
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 +            error_report("Invalid HTIF fromhost or tohost address");
 +            exit(1);
 +        }
      }
      base = MIN(tohost_addr, fromhost_addr);
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = {
  };
  static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 -                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
 +                       uint64_t mem_size, const char *cmdline,
 +                       bool is_32_bit, bool htif_custom_base)
  {
-     void *fdt;
+     return opfv_narrow_check(s, a) &&
-     uint64_t addr, size;
+            require_rvf(s) &&
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
+-           require_scale_rvf(s) &&
+-           (s->sew != MO_8);
-     qemu_fdt_add_subnode(fdt, "/htif");
++           require_scale_rvf(s);
      qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
 -    if (!htif_uses_elf_symbols()) {
 +    if (htif_custom_base) {
          qemu_fdt_setprop_cells(fdt, "/htif", "reg",
 x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
      }
  }
-+static bool spike_test_elf_image(char *filename)
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
-+{
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 +    Error *err = NULL;
 +
 +    load_elf_hdr(filename, NULL, NULL, &err);
 +    if (err) {
 +        error_free(err);
 +        return false;
 +    } else {
 +        return true;
 +    }
 +}
 +
  static void spike_board_init(MachineState *machine)
  {
-     const MemMapEntry *memmap = spike_memmap;
+     return reduction_widen_check(s, a) &&
-     SpikeState *s = SPIKE_MACHINE(machine);
+            require_rvf(s) &&
-     MemoryRegion *system_memory = get_system_memory();
+-           require_scale_rvf(s) &&
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+-           (s->sew != MO_8);
--    target_ulong firmware_end_addr, kernel_start_addr;
++           require_scale_rvf(s);
 -    const char *firmware_name;
 +    target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
 +    target_ulong kernel_start_addr;
 +    char *firmware_name;
      uint32_t fdt_load_addr;
      uint64_t kernel_entry;
      char *soc_name;
      int i, base_hartid, hart_count;
 +    bool htif_custom_base = false;
      /* Check socket count limit */
      if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                  mask_rom);
 -    firmware_name = riscv_default_firmware_name(&s->soc[0]);
 -    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 -                                                     memmap[SPIKE_DRAM].base,
 -                                                     htif_symbol_callback);
 +    /* Find firmware */
 +    firmware_name = riscv_find_firmware(machine->firmware,
 +                        riscv_default_firmware_name(&s->soc[0]));
 +
 +    /*
 +     * Test the given firmware or kernel file to see if it is an ELF image.
 +     * If it is an ELF, we assume it contains the symbols required for
 +     * the HTIF console, otherwise we fall back to use the custom base
 +     * passed from device tree for the HTIF console.
 +     */
 +    if (!firmware_name && !machine->kernel_filename) {
 +        htif_custom_base = true;
 +    } else {
 +        if (firmware_name) {
 +            htif_custom_base = !spike_test_elf_image(firmware_name);
 +        }
 +        if (!htif_custom_base && machine->kernel_filename) {
 +            htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
 +        }
 +    }
 +
 +    /* Load firmware */
 +    if (firmware_name) {
 +        firmware_end_addr = riscv_load_firmware(firmware_name,
 +                                                memmap[SPIKE_DRAM].base,
 +                                                htif_symbol_callback);
 +        g_free(firmware_name);
 +    }
      /* Load kernel */
      if (machine->kernel_filename) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      /* Create device tree */
      create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
 -               riscv_is_32bit(&s->soc[0]));
 +               riscv_is_32bit(&s->soc[0]), htif_custom_base);
      /* Load initrd */
      if (machine->kernel_filename && machine->initrd_filename) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                fdt_load_addr);
      /* initialize HTIF using symbols found in load_kernel */
 -    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
 +    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
 +                 htif_custom_base);
  }
- static void spike_machine_instance_init(Object *obj)
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.39.0
+.45.1

-[PULL 37/37] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier")
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
-moved the initialization of fw_cfg to the virt_machine_done() callback.
+checking first if virt_enabled && !first_stage, and then considering the
 regular inst/load/store faults.
-Problem is that the validation of fw_cfg by devices such as ramfb is
+There's no mention in the spec about guest page fault being a higher
-done before the machine done notifier is called. Moving create_fw_cfg()
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
 to machine_done() results in QEMU failing to boot when using a ramfb
 device:
-./qemu-system-riscv64 -machine virt -device ramfb -serial stdio
+"Attempting to fetch an instruction from a PMP region that does not have
-qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA
+execute permissions raises an instruction access-fault exception.
 Attempting to execute a load or load-reserved instruction which accesses
 a physical address within a PMP region without read permissions raises a
 load access-fault exception. Attempting to execute a store,
 store-conditional, or AMO instruction which accesses a physical address
 within a PMP region without write permissions raises a store
 access-fault exception."
-The fix is simple: move create_fw_cfg() config back to
+So, in fact, we're doing it wrong - PMP faults should always be thrown,
-virt_machine_init(). This happens to be the same way the ARM 'virt'
+regardless of also being a first or second stage fault.
 machine deals with fw_cfg (see machvirt_init() and virt_machine_done()
 in hw/arm/virt.c), so we're keeping consistency with how other machines
 handle this device.
-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343
+The way riscv_cpu_tlb_fill() and get_physical_address() work is
 adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
 reflected in the 'pmp_violation' flag. What we need is to change
 raise_mmu_exception() to prioritize it.
 Reported-by: Joseph Chan <jchan@ventanamicro.com>
 Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/virt.c | 14 +++++++-------
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 7 insertions(+), 7 deletions(-)
+file changed, 12 insertions(+), 10 deletions(-)
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/riscv/virt.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
+@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
-     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
-                                                      start_addr, NULL);
+     switch (access_type) {
+     case MMU_INST_FETCH:
--    /*
+-        if (env->virt_enabled && !first_stage) {
--     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
++        if (pmp_violation) {
--     * tree cannot be altered and we get FDT_ERR_NOSPACE.
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
--     */
++        } else if (env->virt_enabled && !first_stage) {
--    s->fw_cfg = create_fw_cfg(machine);
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
--    rom_set_fw(s->fw_cfg);
+         } else {
--
+-            cs->exception_index = pmp_violation ?
-     if (drive_get(IF_PFLASH, 0, 1)) {
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
-         /*
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
-          * S-mode FW like EDK2 will be kept in second plash (unit 1).
+         }
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+         break;
-     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
+     case MMU_DATA_LOAD:
-                                 mask_rom);
+-        if (two_stage && !first_stage) {
++        if (pmp_violation) {
-+    /*
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
-+     * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
++        } else if (two_stage && !first_stage) {
-+     * device tree cannot be altered and we get FDT_ERR_NOSPACE.
+             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
-+     */
+         } else {
-+    s->fw_cfg = create_fw_cfg(machine);
+-            cs->exception_index = pmp_violation ?
-+    rom_set_fw(s->fw_cfg);
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
-+
++            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
-     /* SiFive Test MMIO device */
+         }
-     sifive_test_create(memmap[VIRT_TEST].base);
+         break;
+     case MMU_DATA_STORE:
 -        if (two_stage && !first_stage) {
 +        if (pmp_violation) {
 +            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
 -            cs->exception_index = pmp_violation ?
 -                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
 -                RISCV_EXCP_STORE_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
          }
          break;
      default:
 --
-.39.0
+.45.1

-[PULL 07/37] hw/char: riscv_htif: Support console output via proxy syscall
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
-From: Bin Meng <bmeng@tinylab.org>
+From: Alexei Filippov <alexei.filippov@syntacore.com>
-At present the HTIF proxy syscall is unsupported. On RV32, only
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
-device 0 is supported so there is no console device for RV32.
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
-The only way to implement console funtionality on RV32 is to
+translation part, mtval2 will be set in case of successes 2 stage translation but
-support the SYS_WRITE syscall.
+failed pmp check.
-With this commit, the Spike machine is able to boot the 32-bit
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
-OpenSBI generic image.
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
 should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
 page-fault is taken into M-mode, mtval2 is written with either zero or guest
 physical address that faulted, shifted by 2 bits. *For other traps, mtval2
 is set to zero...*
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-8-bmeng@tinylab.org>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/char/riscv_htif.c | 17 ++++++++++++++++-
+ target/riscv/cpu_helper.c | 12 ++++++------
-file changed, 16 insertions(+), 1 deletion(-)
+file changed, 6 insertions(+), 6 deletions(-)
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
+--- a/target/riscv/cpu_helper.c
-+++ b/hw/char/riscv_htif.c
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- #define HTIF_CONSOLE_CMD_GETC   0
+                               __func__, pa, ret, prot_pmp, tlb_size);
- #define HTIF_CONSOLE_CMD_PUTC   1
+                 prot &= prot_pmp;
-+/* PK system call number */
+-            }
-+#define PK_SYS_WRITE            64
+-
-+
+-            if (ret != TRANSLATE_SUCCESS) {
- static uint64_t fromhost_addr, tohost_addr;
++            } else {
- static int address_symbol_set;
+                 /*
+                  * Guest physical address translation failed, this is a HS
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
+                  * level exception
-                 int exit_code = payload >> 1;
+                  */
-                 exit(exit_code);
+                 first_stage_error = false;
-             } else {
+-                env->guest_phys_fault_addr = (im_address |
--                qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
+-                                              (address &
-+                uint64_t syscall[8];
+-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
-+                cpu_physical_memory_read(payload, syscall, sizeof(syscall));
++                if (ret != TRANSLATE_PMP_FAIL) {
-+                if (syscall[0] == PK_SYS_WRITE &&
++                    env->guest_phys_fault_addr = (im_address |
-+                    syscall[1] == HTIF_DEV_CONSOLE &&
++                                                  (address &
-+                    syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
++                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
 +                    uint8_t ch;
 +                    cpu_physical_memory_read(syscall[2], &ch, 1);
 +                    qemu_chr_fe_write(&s->chr, &ch, 1);
 +                    resp = 0x100 | (uint8_t)payload;
 +                } else {
 +                    qemu_log_mask(LOG_UNIMP,
 +                                  "pk syscall proxy not supported\n");
 +                }
              }
-         } else {
+         }
-             qemu_log("HTIF device %d: unknown command\n", device);
+     } else {
 --
-.39.0
+.45.1

-[PULL 25/37] target/riscv: Use TARGET_FMT_lx for env->mhartid
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
-From: Bin Meng <bmeng@tinylab.org>
+From: Rob Bradford <rbradford@rivosinc.com>
-env->mhartid is currently casted to long before printed, which drops
+This extension has now been ratified:
-the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
 removed.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
+Since this is now a ratified extension add it to the list of extensions
 included in the "max" CPU variant.
 Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230109152655.340114-1-bmeng@tinylab.org>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.c | 6 +++---
+ target/riscv/cpu.c         | 2 +-
-file changed, 3 insertions(+), 3 deletions(-)
+ target/riscv/tcg/tcg-cpu.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
-             (env->priv_ver < isa_edata_arr[i].min_version)) {
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
-             isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
- #ifndef CONFIG_USER_ONLY
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
--            warn_report("disabling %s extension for hart 0x%lx because "
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
--                        "privilege spec version does not match",
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
--                        isa_edata_arr[i].name, (unsigned long)env->mhartid);
+ };
-+            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
-+                        " because privilege spec version does not match",
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
-+                        isa_edata_arr[i].name, env->mhartid);
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
- #else
+index XXXXXXX..XXXXXXX 100644
-             warn_report("disabling %s extension because "
+--- a/target/riscv/tcg/tcg-cpu.c
-                         "privilege spec version does not match",
++++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
      const RISCVCPUMultiExtConfig *prop;
      /* Enable RVG, RVJ and RVV that are disabled by default */
 -    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
 +    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
      for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
          isa_ext_update_enabled(cpu, prop->offset, true);
 --
-.39.0
+.45.1

-[PULL 30/37] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Alistair Francis <alistair23@gmail.com>
-There's no need to use a MachineState pointer and a fdt pointer now that
+When running the instruction
 all RISC-V machines are using the FDT from the MachineState.
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+```
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+    cbo.flush 0(x0)
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+```
-Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com>
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
 Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/numa.h |  6 +++---
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- hw/riscv/numa.c         |  6 +++---
+file changed, 12 insertions(+), 4 deletions(-)
  hw/riscv/spike.c        |  6 +++---
  hw/riscv/virt.c         | 18 +++++++++---------
 files changed, 18 insertions(+), 18 deletions(-)
-diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/numa.h
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/include/hw/riscv/numa.h
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
+@@ -XXX,XX +XXX,XX @@
-  * @ms: pointer to machine state
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
-  * @socket_id: socket index
+ {
-  *
+     REQUIRE_ZICBOM(ctx);
-- * Write NUMA node-id FDT property for given FDT node
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-+ * Write NUMA node-id FDT property in MachineState->fdt
++    TCGv src = get_address(ctx, a->rs1, 0);
-  */
++
--void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
++    gen_helper_cbo_clean_flush(tcg_env, src);
--                               const char *node_name, int socket_id);
+     return true;
 +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
 +                               int socket_id);
  /**
   * riscv_socket_fdt_write_distance_matrix:
 diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/numa.c
 +++ b/hw/riscv/numa.c
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
              ms->numa_state->nodes[socket_id].node_mem : 0;
  }
--void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 -                               const char *node_name, int socket_id)
 +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
 +                               int socket_id)
  {
-     if (numa_enabled(ms)) {
+     REQUIRE_ZICBOM(ctx);
--        qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-+        qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id);
++    TCGv src = get_address(ctx, a->rs1, 0);
-     }
++
 +    gen_helper_cbo_clean_flush(tcg_env, src);
      return true;
  }
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+ static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/riscv/spike.c
+     REQUIRE_ZICBOM(ctx);
-+++ b/hw/riscv/spike.c
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
++    TCGv src = get_address(ctx, a->rs1, 0);
-             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
++
-                 s->soc[socket].hartid_base + cpu);
++    gen_helper_cbo_inval(tcg_env, src);
-             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
+     return true;
 -            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
 +            riscv_socket_fdt_write_id(mc, cpu_name, socket);
              qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
              intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
          qemu_fdt_setprop_cells(fdt, mem_name, "reg",
              addr >> 32, addr, size >> 32, size);
          qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
 -        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
 +        riscv_socket_fdt_write_id(mc, mem_name, socket);
          g_free(mem_name);
          clint_addr = memmap[SPIKE_CLINT].base +
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
          qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
              clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 -        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
 +        riscv_socket_fdt_write_id(mc, clint_name, socket);
          g_free(clint_name);
          g_free(clint_cells);
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
          qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
              s->soc[socket].hartid_base + cpu);
          qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
 -        riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
 +        riscv_socket_fdt_write_id(mc, cpu_name, socket);
          qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
          intc_phandles[cpu] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_memory(RISCVVirtState *s,
      qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
          addr >> 32, addr, size >> 32, size);
      qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
 -    riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
 +    riscv_socket_fdt_write_id(mc, mem_name, socket);
      g_free(mem_name);
  }
-@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
+ static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
-x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+ {
-     qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
+     REQUIRE_ZICBOZ(ctx);
-         clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
--    riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
++    TCGv src = get_address(ctx, a->rs1, 0);
-+    riscv_socket_fdt_write_id(mc, clint_name, socket);
++
-     g_free(clint_name);
++    gen_helper_cbo_zero(tcg_env, src);
+     return true;
-     g_free(clint_cells);
+ }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
              aclint_mswi_cells, aclint_cells_size);
          qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
          qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
 -        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
 +        riscv_socket_fdt_write_id(mc, name, socket);
          g_free(name);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
 x0, RISCV_ACLINT_DEFAULT_MTIME);
      qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
          aclint_mtimer_cells, aclint_cells_size);
 -    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
 +    riscv_socket_fdt_write_id(mc, name, socket);
      g_free(name);
      if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
              aclint_sswi_cells, aclint_cells_size);
          qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
          qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
 -        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
 +        riscv_socket_fdt_write_id(mc, name, socket);
          g_free(name);
      }
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
 x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
      qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
                            VIRT_IRQCHIP_NUM_SOURCES - 1);
 -    riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
 +    riscv_socket_fdt_write_id(mc, plic_name, socket);
      qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
          plic_phandles[socket]);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
          aplic_s_phandle);
      qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
          aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
 -    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
 +    riscv_socket_fdt_write_id(mc, aplic_name, socket);
      qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
      g_free(aplic_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
 x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
      qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
          VIRT_IRQCHIP_NUM_SOURCES);
 -    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
 +    riscv_socket_fdt_write_id(mc, aplic_name, socket);
      qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
      if (!socket) {
 --
-.39.0
+.45.1

-[PULL 19/37] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-riscv_load_initrd() returns the initrd end addr while also writing a
+In AIA spec, each hart (or each hart within a group) has a unique hart
-'start' var to mark the addr start. These informations are being used
+number to locate the memory pages of interrupt files in the address
-just to write the initrd FDT node. Every existing caller of
+space. The number of bits required to represent any hart number is equal
-riscv_load_initrd() is writing the FDT in the same manner.
+to ceil(log2(hmax + 1)), where hmax is the largest hart number among
 groups.
-We can simplify things by writing the FDT inside riscv_load_initrd(),
+However, if the largest hart number among groups is a power of 2, QEMU
-sparing callers from having to manage start/end addrs to write the FDT
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
-themselves.
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
 to represent 4 harts, but we passes 3 to Linux. The code needs to be
 updated to ensure accurate hart-index-bit settings.
-An 'if (fdt)' check is already inserted at the end of the function
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
-because we'll end up using it later on with other boards that doesn´t
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
 have a FDT.
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com>
+Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/boot.h    |  4 ++--
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
- hw/riscv/boot.c            | 18 ++++++++++++------
+file changed, 8 insertions(+), 1 deletion(-)
  hw/riscv/microchip_pfsoc.c | 10 ++--------
  hw/riscv/sifive_u.c        | 10 ++--------
  hw/riscv/spike.c           | 10 ++--------
  hw/riscv/virt.c            | 10 ++--------
 files changed, 22 insertions(+), 40 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/include/hw/riscv/boot.h
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
  target_ulong riscv_load_kernel(const char *kernel_filename,
                                 target_ulong firmware_end_addr,
                                 symbol_fn_t sym_cb);
 -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
 -                         uint64_t kernel_entry, hwaddr *start);
 +void riscv_load_initrd(const char *filename, uint64_t mem_size,
 +                       uint64_t kernel_entry, void *fdt);
  uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
  void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                 hwaddr saddr,
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
      exit(1);
  }
 -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
 -                         uint64_t kernel_entry, hwaddr *start)
 +void riscv_load_initrd(const char *filename, uint64_t mem_size,
 +                       uint64_t kernel_entry, void *fdt)
  {
 +    hwaddr start, end;
      ssize_t size;
      g_assert(filename != NULL);
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
       * halfway into RAM, and for boards with 256MB of RAM or more we put
       * the initrd at 128MB.
       */
 -    *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
 +    start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
 -    size = load_ramdisk(filename, *start, mem_size - *start);
 +    size = load_ramdisk(filename, start, mem_size - start);
      if (size == -1) {
 -        size = load_image_targphys(filename, *start, mem_size - *start);
 +        size = load_image_targphys(filename, start, mem_size - start);
          if (size == -1) {
              error_report("could not load ramdisk '%s'", filename);
              exit(1);
          }
      }
--    return *start + size;
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+    /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
++
-+    if (fdt) {
++    if (max_hart_per_socket > 1) {
-+        end = start + size;
++        max_hart_per_socket--;
-+        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
-+        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
++    } else {
 +        hart_bits = 0;
 +    }
- }
++
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
- uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+                             &hart_bits, true, NULL);
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                           kernel_start_addr, NULL);
          if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-end", end);
 +            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
 +                              kernel_entry, machine->fdt);
          }
          if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
                                           kernel_start_addr, NULL);
          if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 -                                  end);
 +            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
 +                              kernel_entry, machine->fdt);
          }
      } else {
         /*
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                           htif_symbol_callback);
          if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 -                                  end);
 +            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
 +                              kernel_entry, machine->fdt);
          }
      } else {
         /*
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
                                           kernel_start_addr, NULL);
          if (machine->initrd_filename) {
 -            hwaddr start;
 -            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 -                                           machine->ram_size, kernel_entry,
 -                                           &start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 -                                  "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
 -                                  end);
 +            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
 +                              kernel_entry, machine->fdt);
          }
      } else {
         /*
 --
-.39.0
+.45.1

-[PULL 16/37] hw/riscv/sifive_u: use 'fdt' from MachineState
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
 From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The MachineState object provides a 'fdt' pointer that is already being
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
+in bytes, when in this context we want 'reg_width' as the length in
-command.
+bits.
-Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
-instead.
+("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com>
+Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_u.h |  3 ---
+ target/riscv/gdbstub.c | 6 +++---
- hw/riscv/sifive_u.c         | 15 ++++++---------
+file changed, 3 insertions(+), 3 deletions(-)
 files changed, 6 insertions(+), 12 deletions(-)
-diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/target/riscv/gdbstub.c
-+++ b/include/hw/riscv/sifive_u.h
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUState {
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
-     /*< public >*/
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      SiFiveUSoCState soc;
 -    void *fdt;
 -    int fdt_size;
 -
      bool start_in_flash;
      uint32_t msel;
      uint32_t serial;
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
  {
-     MachineState *ms = MACHINE(qdev_get_machine());
+     RISCVCPU *cpu = RISCV_CPU(cs);
-     void *fdt;
+-    int reg_width = cpu->cfg.vlenb;
--    int cpu;
++    int bitsize = cpu->cfg.vlenb << 3;
-+    int cpu, fdt_size;
+     GDBFeatureBuilder builder;
-     uint32_t *cells;
+     int i;
-     char *nodename;
-     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-     };
+     /* First define types and totals in a whole VL */
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-     if (ms->dtb) {
+-        int count = reg_width / vec_lanes[i].size;
--        fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
++        int count = bitsize / vec_lanes[i].size;
-+        fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
+         gdb_feature_builder_append_tag(
-         if (!fdt) {
+             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
-             error_report("load_device_tree() failed");
+             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
-             exit(1);
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-         }
+     /* Define vector registers */
-         goto update_bootargs;
+     for (i = 0; i < 32; i++) {
-     } else {
+         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
--        fdt = s->fdt = create_device_tree(&s->fdt_size);
+-                                       reg_width, i, "riscv_vector", "vector");
-+        fdt = ms->fdt = create_device_tree(&fdt_size);
++                                       bitsize, i, "riscv_vector", "vector");
          if (!fdt) {
              error_report("create_device_tree() failed");
              exit(1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
              hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                             machine->ram_size, kernel_entry,
                                             &start);
 -            qemu_fdt_setprop_cell(s->fdt, "/chosen",
 +            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
                                    "linux,initrd-start", start);
 -            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 +            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
                                    end);
          }
      } else {
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      /* Compute the fdt load address in dram */
      fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
 -                                   machine->ram_size, s->fdt);
 +                                   machine->ram_size, machine->fdt);
      if (!riscv_is_32bit(&s->soc.u_cpus)) {
          start_addr_hi32 = (uint64_t)start_addr >> 32;
      }
--    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
+     gdb_feature_builder_end(&builder);
 -    machine->fdt = s->fdt;
 -
      /* reset vector */
      uint32_t reset_vec[12] = {
          s->msel,                       /* MSEL pin state */
 --
-.39.0
+.45.1

-[PULL 20/37] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+From: Alistair Francis <alistair23@gmail.com>
-The sifive_u, spike and virt machines are writing the 'bootargs' FDT
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
-node during their respective create_fdt().
+CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
 CSRs are part of the disassembly.
-Given that bootargs is written only when '-append' is used, and this
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
-option is only allowed with the '-kernel' option, which in turn is
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-already being check before executing riscv_load_kernel(), write
+Fixes: ea10325917 ("RISC-V Disassembler")
-'bootargs' in the same code path as riscv_load_kernel().
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Cc: Palmer Dabbelt <palmer@dabbelt.com>
+Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Bin Meng <bmeng@tinylab.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_u.c | 11 +++++------
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
- hw/riscv/spike.c    |  9 +++++----
+file changed, 64 insertions(+), 1 deletion(-)
  hw/riscv/virt.c     | 11 +++++------
 files changed, 15 insertions(+), 16 deletions(-)
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+diff --git a/disas/riscv.c b/disas/riscv.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
+--- a/disas/riscv.c
-+++ b/hw/riscv/sifive_u.c
++++ b/disas/riscv.c
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-             error_report("load_device_tree() failed");
+     case 0x0383: return "mibound";
-             exit(1);
+     case 0x0384: return "mdbase";
-         }
+     case 0x0385: return "mdbound";
--        goto update_bootargs;
+-    case 0x03a0: return "pmpcfg3";
-     } else {
++    case 0x03a0: return "pmpcfg0";
-         fdt = ms->fdt = create_device_tree(&fdt_size);
++    case 0x03a1: return "pmpcfg1";
-         if (!fdt) {
++    case 0x03a2: return "pmpcfg2";
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
++    case 0x03a3: return "pmpcfg3";
-     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
++    case 0x03a4: return "pmpcfg4";
++    case 0x03a5: return "pmpcfg5";
-     g_free(nodename);
++    case 0x03a6: return "pmpcfg6";
--
++    case 0x03a7: return "pmpcfg7";
--update_bootargs:
++    case 0x03a8: return "pmpcfg8";
--    if (cmdline && *cmdline) {
++    case 0x03a9: return "pmpcfg9";
--        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
++    case 0x03aa: return "pmpcfg10";
--    }
++    case 0x03ab: return "pmpcfg11";
- }
++    case 0x03ac: return "pmpcfg12";
++    case 0x03ad: return "pmpcfg13";
- static void sifive_u_machine_reset(void *opaque, int n, int level)
++    case 0x03ae: return "pmpcfg14";
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
++    case 0x03af: return "pmpcfg15";
-             riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+     case 0x03b0: return "pmpaddr0";
-                               kernel_entry, machine->fdt);
+     case 0x03b1: return "pmpaddr1";
-         }
+     case 0x03b2: return "pmpaddr2";
-+
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
-+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+     case 0x03bd: return "pmpaddr13";
-+            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+     case 0x03be: return "pmpaddr14";
-+                                    machine->kernel_cmdline);
+     case 0x03bf: return "pmpaddr15";
-+        }
++    case 0x03c0: return "pmpaddr16";
-     } else {
++    case 0x03c1: return "pmpaddr17";
-        /*
++    case 0x03c2: return "pmpaddr18";
-         * If dynamic firmware is used, it doesn't know where is the next mode
++    case 0x03c3: return "pmpaddr19";
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
++    case 0x03c4: return "pmpaddr20";
-index XXXXXXX..XXXXXXX 100644
++    case 0x03c5: return "pmpaddr21";
---- a/hw/riscv/spike.c
++    case 0x03c6: return "pmpaddr22";
-+++ b/hw/riscv/spike.c
++    case 0x03c7: return "pmpaddr23";
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
++    case 0x03c8: return "pmpaddr24";
++    case 0x03c9: return "pmpaddr25";
-     qemu_fdt_add_subnode(fdt, "/chosen");
++    case 0x03ca: return "pmpaddr26";
-     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
++    case 0x03cb: return "pmpaddr27";
--
++    case 0x03cc: return "pmpaddr28";
--    if (cmdline && *cmdline) {
++    case 0x03cd: return "pmpaddr29";
--        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
++    case 0x03ce: return "pmpaddr30";
--    }
++    case 0x03cf: return "pmpaddr31";
- }
++    case 0x03d0: return "pmpaddr32";
++    case 0x03d1: return "pmpaddr33";
- static bool spike_test_elf_image(char *filename)
++    case 0x03d2: return "pmpaddr34";
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
++    case 0x03d3: return "pmpaddr35";
-             riscv_load_initrd(machine->initrd_filename, machine->ram_size,
++    case 0x03d4: return "pmpaddr36";
-                               kernel_entry, machine->fdt);
++    case 0x03d5: return "pmpaddr37";
-         }
++    case 0x03d6: return "pmpaddr38";
-+
++    case 0x03d7: return "pmpaddr39";
-+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
++    case 0x03d8: return "pmpaddr40";
-+            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
++    case 0x03d9: return "pmpaddr41";
-+                                    machine->kernel_cmdline);
++    case 0x03da: return "pmpaddr42";
-+        }
++    case 0x03db: return "pmpaddr43";
-     } else {
++    case 0x03dc: return "pmpaddr44";
-        /*
++    case 0x03dd: return "pmpaddr45";
-         * If dynamic firmware is used, it doesn't know where is the next mode
++    case 0x03de: return "pmpaddr46";
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
++    case 0x03df: return "pmpaddr47";
-index XXXXXXX..XXXXXXX 100644
++    case 0x03e0: return "pmpaddr48";
---- a/hw/riscv/virt.c
++    case 0x03e1: return "pmpaddr49";
-+++ b/hw/riscv/virt.c
++    case 0x03e2: return "pmpaddr50";
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
++    case 0x03e3: return "pmpaddr51";
-             error_report("load_device_tree() failed");
++    case 0x03e4: return "pmpaddr52";
-             exit(1);
++    case 0x03e5: return "pmpaddr53";
-         }
++    case 0x03e6: return "pmpaddr54";
--        goto update_bootargs;
++    case 0x03e7: return "pmpaddr55";
-     } else {
++    case 0x03e8: return "pmpaddr56";
-         mc->fdt = create_device_tree(&s->fdt_size);
++    case 0x03e9: return "pmpaddr57";
-         if (!mc->fdt) {
++    case 0x03ea: return "pmpaddr58";
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
++    case 0x03eb: return "pmpaddr59";
-     create_fdt_fw_cfg(s, memmap);
++    case 0x03ec: return "pmpaddr60";
-     create_fdt_pmu(s);
++    case 0x03ed: return "pmpaddr61";
++    case 0x03ee: return "pmpaddr62";
--update_bootargs:
++    case 0x03ef: return "pmpaddr63";
--    if (cmdline && *cmdline) {
+     case 0x0780: return "mtohost";
--        qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
+     case 0x0781: return "mfromhost";
--    }
+     case 0x0782: return "mreset";
 -
      /* Pass seed to RNG */
      qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
      qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
              riscv_load_initrd(machine->initrd_filename, machine->ram_size,
                                kernel_entry, machine->fdt);
          }
 +
 +        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
 +            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
 +                                    machine->kernel_cmdline);
 +        }
      } else {
         /*
          * If dynamic firmware is used, it doesn't know where is the next mode
 --
-.39.0
+.45.1

-[PULL 05/37] hw/char: riscv_htif: Move registers from CPUArchState to HTIFState
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
-From: Bin Meng <bmeng@tinylab.org>
+From: Yu-Ming Chang <yumin686@andestech.com>
-At present for some unknown reason the HTIF registers (fromhost &
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
-tohost) are defined in the RISC-V CPUArchState. It should really
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
-be put in the HTIFState struct as it is only meaningful to HTIF.
+holding a zero value other than x0, the instruction will still attempt to write
 the unmodified value back to the CSR and will cause any attendant side effects.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+a register holding a zero value, an illegal instruction exception should be
 raised.
 Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/riscv_htif.h |  8 ++++----
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/cpu.h           |  4 ----
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- hw/char/riscv_htif.c         | 35 +++++++++++++++++------------------
+ target/riscv/op_helper.c |  6 ++---
- hw/riscv/spike.c             |  3 +--
+files changed, 53 insertions(+), 8 deletions(-)
  target/riscv/machine.c       |  6 ++----
 files changed, 24 insertions(+), 32 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
-+++ b/include/hw/char/riscv_htif.h
-@@ -XXX,XX +XXX,XX @@
- #include "chardev/char.h"
- #include "chardev/char-fe.h"
- #include "exec/memory.h"
--#include "target/riscv/cpu.h"
- #define TYPE_HTIF_UART "riscv.htif.uart"
-@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
-     int allow_tohost;
-     int fromhost_inprogress;
-+    uint64_t tohost;
-+    uint64_t fromhost;
-     hwaddr tohost_offset;
-     hwaddr fromhost_offset;
-     MemoryRegion mmio;
--    CPURISCVState *env;
-     CharBackend chr;
-     uint64_t pending_read;
- } HTIFState;
-@@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
- bool htif_uses_elf_symbols(void);
- /* legacy pre qom */
--HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
--                        Chardev *chr, uint64_t nonelf_base);
-+HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
-+                        uint64_t nonelf_base);
- #endif
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-     target_ulong sscratch;
+ void riscv_cpu_update_mask(CPURISCVState *env);
-     target_ulong mscratch;
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
--    /* temporary htif regs */
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
--    uint64_t mfromhost;
++                          target_ulong *ret_value);
--    uint64_t mtohost;
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
--
+                            target_ulong *ret_value,
-     /* Sstc CSRs */
+                            target_ulong new_value, target_ulong write_mask);
-     uint64_t stimecmp;
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
+                                           target_ulong new_value,
-diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
+                                           target_ulong write_mask);
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value);
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/riscv_htif.c
+--- a/target/riscv/csr.c
-+++ b/hw/char/riscv_htif.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-     uint64_t val_written = s->pending_read;
-     uint64_t resp = 0x100 | *buf;
+ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
+                                                int csrno,
--    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+-                                               bool write_mask)
-+    s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
++                                               bool write)
  {
      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
      bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
      }
      /* read / write check */
 -    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
- /*
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
++                           target_ulong *ret_value)
-         if (cmd == HTIF_CONSOLE_CMD_GETC) {
++{
-             /* this should be a queue, but not yet implemented as such */
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-             s->pending_read = val_written;
++    if (ret != RISCV_EXCP_NONE) {
--            s->env->mtohost = 0; /* clear to indicate we read */
++        return ret;
-+            s->tohost = 0; /* clear to indicate we read */
++    }
-             return;
++
-         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
-             qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
++}
-@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
++
-      * HTIF needs protocol documentation and a more complete state machine.
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
-      *
+                            target_ulong *ret_value,
-      *  while (!s->fromhost_inprogress &&
+                            target_ulong new_value, target_ulong write_mask)
--     *      s->env->mfromhost != 0x0) {
+ {
-+     *      s->fromhost != 0x0) {
+-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
-      *  }
++    RISCVException ret = riscv_csrrw_check(env, csrno, true);
-      */
+     if (ret != RISCV_EXCP_NONE) {
--    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+         return ret;
--    s->env->mtohost = 0; /* clear to indicate we read */
+     }
-+    s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
-+    s->tohost = 0; /* clear to indicate we read */
+     return RISCV_EXCP_NONE;
  }
- #define TOHOST_OFFSET1      (s->tohost_offset)
++RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
++                               Int128 *ret_value)
 +{
 +    RISCVException ret;
 +
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
 +    if (csr_ops[csrno].read128) {
 +        return riscv_csrrw_do128(env, csrno, ret_value,
 +                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
-     HTIFState *s = opaque;
+     RISCVException ret;
-     if (addr == TOHOST_OFFSET1) {
--        return s->env->mtohost & 0xFFFFFFFF;
+-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
-+        return s->tohost & 0xFFFFFFFF;
++    ret = riscv_csrrw_check(env, csrno, true);
-     } else if (addr == TOHOST_OFFSET2) {
+     if (ret != RISCV_EXCP_NONE) {
--        return (s->env->mtohost >> 32) & 0xFFFFFFFF;
+         return ret;
-+        return (s->tohost >> 32) & 0xFFFFFFFF;
+     }
-     } else if (addr == FROMHOST_OFFSET1) {
+diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
--        return s->env->mfromhost & 0xFFFFFFFF;
+index XXXXXXX..XXXXXXX 100644
-+        return s->fromhost & 0xFFFFFFFF;
+--- a/target/riscv/op_helper.c
-     } else if (addr == FROMHOST_OFFSET2) {
++++ b/target/riscv/op_helper.c
--        return (s->env->mfromhost >> 32) & 0xFFFFFFFF;
+@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
-+        return (s->fromhost >> 32) & 0xFFFFFFFF;
+     }
-     } else {
-         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
+     target_ulong val = 0;
-             (uint64_t)addr);
+-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
-@@ -XXX,XX +XXX,XX @@ static void htif_mm_write(void *opaque, hwaddr addr,
++    RISCVException ret = riscv_csrr(env, csr, &val);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
-     HTIFState *s = opaque;
+     Int128 rv = int128_zero();
-     if (addr == TOHOST_OFFSET1) {
+-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
--        if (s->env->mtohost == 0x0) {
+-                                          int128_zero(),
-+        if (s->tohost == 0x0) {
+-                                          int128_zero());
-             s->allow_tohost = 1;
++    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
--            s->env->mtohost = value & 0xFFFFFFFF;
-+            s->tohost = value & 0xFFFFFFFF;
+     if (ret != RISCV_EXCP_NONE) {
-         } else {
+         riscv_raise_exception(env, ret, GETPC());
              s->allow_tohost = 0;
          }
      } else if (addr == TOHOST_OFFSET2) {
          if (s->allow_tohost) {
 -            s->env->mtohost |= value << 32;
 -            htif_handle_tohost_write(s, s->env->mtohost);
 +            s->tohost |= value << 32;
 +            htif_handle_tohost_write(s, s->tohost);
          }
      } else if (addr == FROMHOST_OFFSET1) {
          s->fromhost_inprogress = 1;
 -        s->env->mfromhost = value & 0xFFFFFFFF;
 +        s->fromhost = value & 0xFFFFFFFF;
      } else if (addr == FROMHOST_OFFSET2) {
 -        s->env->mfromhost |= value << 32;
 +        s->fromhost |= value << 32;
          s->fromhost_inprogress = 0;
      } else {
          qemu_log("Invalid htif write: address %016" PRIx64 "\n",
@@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void)
      return (address_symbol_set == 3) ? true : false;
  }
 -HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
 -                        Chardev *chr, uint64_t nonelf_base)
 +HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
 +                        uint64_t nonelf_base)
  {
      uint64_t base, size, tohost_offset, fromhost_offset;
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
      fromhost_offset = fromhost_addr - base;
      HTIFState *s = g_new0(HTIFState, 1);
 -    s->env = env;
      s->tohost_offset = tohost_offset;
      s->fromhost_offset = fromhost_offset;
      s->pending_read = 0;
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                fdt_load_addr);
      /* initialize HTIF using symbols found in load_kernel */
 -    htif_mm_init(system_memory, &s->soc[0].harts[0].env,
 -                 serial_hd(0), memmap[SPIKE_HTIF].base);
 +    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
  }
  static void spike_machine_instance_init(Object *obj)
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = {
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
 -    .version_id = 5,
 -    .minimum_version_id = 5,
 +    .version_id = 6,
 +    .minimum_version_id = 6,
      .post_load = riscv_cpu_post_load,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
          VMSTATE_UINTTL(env.sscratch, RISCVCPU),
          VMSTATE_UINTTL(env.mscratch, RISCVCPU),
 -        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
 -        VMSTATE_UINT64(env.mtohost, RISCVCPU),
          VMSTATE_UINT64(env.stimecmp, RISCVCPU),
          VMSTATE_END_OF_LIST()
 --
-.39.0
+.45.1

-[PULL 06/37] hw/char: riscv_htif: Remove forward declarations for non-existent variables
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-There are forward declarations for 'vmstate_htif' and 'htif_io_ops'
-in riscv_htif.h however there are no definitions in the C codes.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-7-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/char/riscv_htif.h | 3 ---
-file changed, 3 deletions(-)
-diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/char/riscv_htif.h
-+++ b/include/hw/char/riscv_htif.h
-@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
-     uint64_t pending_read;
- } HTIFState;
--extern const VMStateDescription vmstate_htif;
--extern const MemoryRegionOps htif_io_ops;
--
- /* HTIF symbol callback */
- void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
-     uint64_t st_size);
---
-.39.0

-[PULL 08/37] hw/riscv: spike: Remove the out-of-date comments
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-Spike machine now supports OpenSBI plain binary bios image, so the
-comments are no longer valid.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-9-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/spike.c | 5 -----
-file changed, 5 deletions(-)
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
-                                 mask_rom);
--    /*
--     * Not like other RISC-V machines that use plain binary bios images,
--     * keeping ELF files here was intentional because BIN files don't work
--     * for the Spike machine as HTIF emulation depends on ELF parsing.
--     */
-     if (riscv_is_32bit(&s->soc[0])) {
-         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                     RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
---
-.39.0

-[PULL 11/37] hw/riscv/boot.c: Introduce riscv_find_firmware()
+Deleted patch
-From: Bin Meng <bmeng@tinylab.org>
-Rename previous riscv_find_firmware() to riscv_find_bios(), and
-introduce a new riscv_find_firmware() to implement the first half
-part of the work done in riscv_find_and_load_firmware().
-This new API is helpful for machine that wants to know the final
-chosen firmware file name but does not want to load it.
-Signed-off-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20221229091828.1945072-12-bmeng@tinylab.org>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- include/hw/riscv/boot.h |  2 ++
- hw/riscv/boot.c         | 39 +++++++++++++++++++++++++--------------
-files changed, 27 insertions(+), 14 deletions(-)
-diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                           hwaddr firmware_load_addr,
-                                           symbol_fn_t sym_cb);
- const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
-+char *riscv_find_firmware(const char *firmware_filename,
-+                          const char *default_machine_firmware);
- target_ulong riscv_load_firmware(const char *firmware_filename,
-                                  hwaddr firmware_load_addr,
-                                  symbol_fn_t sym_cb);
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
-     return RISCV64_BIOS_BIN;
- }
--static char *riscv_find_firmware(const char *firmware_filename)
-+static char *riscv_find_bios(const char *bios_filename)
- {
-     char *filename;
--    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
-+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename);
-     if (filename == NULL) {
-         if (!qtest_enabled()) {
-             /*
-@@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename)
-              * running QEMU test will complain hence let's suppress the error
-              * report for QEMU testing.
-              */
--            error_report("Unable to load the RISC-V firmware \"%s\"",
--                         firmware_filename);
-+            error_report("Unable to find the RISC-V BIOS \"%s\"",
-+                         bios_filename);
-             exit(1);
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename)
-     return filename;
- }
--target_ulong riscv_find_and_load_firmware(MachineState *machine,
--                                          const char *default_machine_firmware,
--                                          hwaddr firmware_load_addr,
--                                          symbol_fn_t sym_cb)
-+char *riscv_find_firmware(const char *firmware_filename,
-+                          const char *default_machine_firmware)
- {
--    char *firmware_filename = NULL;
--    target_ulong firmware_end_addr = firmware_load_addr;
-+    char *filename = NULL;
--    if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
-+    if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) {
-         /*
-          * The user didn't specify -bios, or has specified "-bios default".
-          * That means we are going to load the OpenSBI binary included in
-          * the QEMU source.
-          */
--        firmware_filename = riscv_find_firmware(default_machine_firmware);
--    } else if (strcmp(machine->firmware, "none")) {
--        firmware_filename = riscv_find_firmware(machine->firmware);
-+        filename = riscv_find_bios(default_machine_firmware);
-+    } else if (strcmp(firmware_filename, "none")) {
-+        filename = riscv_find_bios(firmware_filename);
-     }
-+    return filename;
-+}
-+
-+target_ulong riscv_find_and_load_firmware(MachineState *machine,
-+                                          const char *default_machine_firmware,
-+                                          hwaddr firmware_load_addr,
-+                                          symbol_fn_t sym_cb)
-+{
-+    char *firmware_filename;
-+    target_ulong firmware_end_addr = firmware_load_addr;
-+
-+    firmware_filename = riscv_find_firmware(machine->firmware,
-+                                            default_machine_firmware);
-+
-     if (firmware_filename) {
-         /* If not "none" load the firmware */
-         firmware_end_addr = riscv_load_firmware(firmware_filename,
---
-.39.0

-[PULL 14/37] tests/avocado: add RISC-V OpenSBI boot test
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This test is used to do a quick sanity check to ensure that we're able
-to run the existing QEMU FW image.
-'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
-'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
-RISCV32_BIOS_BIN firmware with minimal options.
-The riscv32 'spike' machine isn't bootable at this moment, requiring an
-OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
-or add a 'skip' test to remind us about it. To work as a reminder that
-we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
-QEMU rom receives the fix, we're adding a 'skip' test:
-(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
-        SKIP: requires OpenSBI fix to work
-[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
-[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
-Cc: Cleber Rosa <crosa@redhat.com>
-Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
-Tested-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++
-file changed, 65 insertions(+)
- create mode 100644 tests/avocado/riscv_opensbi.py
-diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/tests/avocado/riscv_opensbi.py
-@@ -XXX,XX +XXX,XX @@
-+# OpenSBI boot test for RISC-V machines
-+#
-+# Copyright (c) 2022, Ventana Micro
-+#
-+# This work is licensed under the terms of the GNU GPL, version 2 or
-+# later.  See the COPYING file in the top-level directory.
-+
-+from avocado_qemu import QemuSystemTest
-+from avocado import skip
-+from avocado_qemu import wait_for_console_pattern
-+
-+class RiscvOpenSBI(QemuSystemTest):
-+    """
-+    :avocado: tags=accel:tcg
-+    """
-+    timeout = 5
-+
-+    def boot_opensbi(self):
-+        self.vm.set_console()
-+        self.vm.launch()
-+        wait_for_console_pattern(self, 'Platform Name')
-+        wait_for_console_pattern(self, 'Boot HART MEDELEG')
-+
-+    @skip("requires OpenSBI fix to work")
-+    def test_riscv32_spike(self):
-+        """
-+        :avocado: tags=arch:riscv32
-+        :avocado: tags=machine:spike
-+        """
-+        self.boot_opensbi()
-+
-+    def test_riscv64_spike(self):
-+        """
-+        :avocado: tags=arch:riscv64
-+        :avocado: tags=machine:spike
-+        """
-+        self.boot_opensbi()
-+
-+    def test_riscv32_sifive_u(self):
-+        """
-+        :avocado: tags=arch:riscv32
-+        :avocado: tags=machine:sifive_u
-+        """
-+        self.boot_opensbi()
-+
-+    def test_riscv64_sifive_u(self):
-+        """
-+        :avocado: tags=arch:riscv64
-+        :avocado: tags=machine:sifive_u
-+        """
-+        self.boot_opensbi()
-+
-+    def test_riscv32_virt(self):
-+        """
-+        :avocado: tags=arch:riscv32
-+        :avocado: tags=machine:virt
-+        """
-+        self.boot_opensbi()
-+
-+    def test_riscv64_virt(self):
-+        """
-+        :avocado: tags=arch:riscv64
-+        :avocado: tags=machine:virt
-+        """
-+        self.boot_opensbi()
---
-.39.0

-[PULL 17/37] hw/riscv/boot.c: exit early if filename is NULL in load functions
+Deleted patch
-From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works
-under the assumption that a 'filename' parameter is always not NULL.
-This is currently the case since all callers of these functions are
-checking for NULL before calling them. Add an g_assert() to make sure
-that a NULL value in these cases are to be considered a bug.
-Suggested-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Reviewed-by: Bin Meng <bmeng@tinylab.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com>
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
----
- hw/riscv/boot.c | 6 ++++++
-file changed, 6 insertions(+)
-diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/boot.c
-+++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
-     uint64_t firmware_entry, firmware_end;
-     ssize_t firmware_size;
-+    g_assert(firmware_filename != NULL);
-+
-     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
-                          &firmware_entry, NULL, &firmware_end, NULL,
-, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
-@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
- {
-     uint64_t kernel_load_base, kernel_entry;
-+    g_assert(kernel_filename != NULL);
-+
-     /*
-      * NB: Use low address not ELF entry point to ensure that the fw_dynamic
-      * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
-@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
- {
-     ssize_t size;
-+    g_assert(filename != NULL);
-+
-     /*
-      * We want to put the initrd far enough into RAM that when the
-      * kernel is uncompressed it will not clobber the initrd. However
---
-.39.0

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 239b8b0699a222fd21da1c5fdeba0a2456085a47:

Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-01-19 15:05:29 +0000)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230120

for you to fetch changes up to b748352c555b42d497fe8ee00ee2e44eb8627660:

hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() (2023-01-20 10:14:14 +1000)

----------------------------------------------------------------
Second RISC-V PR for QEMU 8.0

* riscv_htif: Support console output via proxy syscall
* Cleanup firmware and device tree loading
* Fix elen check when using vector extensions
* add RISC-V OpenSBI boot test
* Ensure we always follow MISA parsing
* Fix up masking of vsip/vsie accesses
* Trap on writes to stimecmp from VS when hvictl.VTI=1
* Introduce helper_set_rounding_mode_chkfrm

----------------------------------------------------------------
Andrew Bresticker (2):
      target/riscv: Fix up masking of vsip/vsie accesses
      target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1

Bin Meng (11):
      hw/char: riscv_htif: Avoid using magic numbers
      hw/char: riscv_htif: Drop {to, from}host_size in HTIFState
      hw/char: riscv_htif: Drop useless assignment of memory region
      hw/char: riscv_htif: Use conventional 's' for HTIFState
      hw/char: riscv_htif: Move registers from CPUArchState to HTIFState
      hw/char: riscv_htif: Remove forward declarations for non-existent variables
      hw/char: riscv_htif: Support console output via proxy syscall
      hw/riscv: spike: Remove the out-of-date comments
      hw/riscv/boot.c: Introduce riscv_find_firmware()
      hw/riscv: spike: Decouple create_fdt() dependency to ELF loading
      target/riscv: Use TARGET_FMT_lx for env->mhartid

Daniel Henrique Barboza (20):
      hw/riscv/boot.c: make riscv_find_firmware() static
      hw/riscv/boot.c: introduce riscv_default_firmware_name()
      tests/avocado: add RISC-V OpenSBI boot test
      hw/riscv/spike: use 'fdt' from MachineState
      hw/riscv/sifive_u: use 'fdt' from MachineState
      hw/riscv/boot.c: exit early if filename is NULL in load functions
      hw/riscv/spike.c: load initrd right after riscv_load_kernel()
      hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd()
      hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel()
      hw/riscv/boot.c: use MachineState in riscv_load_initrd()
      hw/riscv/boot.c: use MachineState in riscv_load_kernel()
      target/riscv/cpu: set cpu->cfg in register_cpu_props()
      target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()
      hw/riscv/spike.c: simplify create_fdt()
      hw/riscv/virt.c: simplify create_fdt()
      hw/riscv/sifive_u.c: simplify create_fdt()
      hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus()
      hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id()
      hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
      hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init()

Dongxue Zhang (1):
      target/riscv/cpu.c: Fix elen check

Richard Henderson (3):
      tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst
      target/riscv: Introduce helper_set_rounding_mode_chkfrm
      target/riscv: Remove helper_set_rod_rounding_mode

From: Bin Meng <bmeng@tinylab.org>

The Spike HTIF is poorly documented. The only relevant info we can
get from the internet is from Andrew Waterman at [1].

Add a comment block before htif_handle_tohost_write() to explain
the tohost register format, and use meaningful macros instead of
magic numbers in the codes.

While we are here, correct 2 multi-line comment blocks that have
wrong format.

Link: https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754 [1]
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-2-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 72 ++++++++++++++++++++++++++++++++------------
 1 file changed, 52 insertions(+), 20 deletions(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
         }                                                                      \
     } while (0)
 
+#define HTIF_DEV_SHIFT          56
+#define HTIF_CMD_SHIFT          48
+
+#define HTIF_DEV_SYSTEM         0
+#define HTIF_DEV_CONSOLE        1
+
+#define HTIF_SYSTEM_CMD_SYSCALL 0
+#define HTIF_CONSOLE_CMD_GETC   0
+#define HTIF_CONSOLE_CMD_PUTC   1
+
 static uint64_t fromhost_addr, tohost_addr;
 static int address_symbol_set;
 
@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
         return;
     }
 
-    /* TODO - we need to check whether mfromhost is zero which indicates
-              the device is ready to receive. The current implementation
-              will drop characters */
+    /*
+     * TODO - we need to check whether mfromhost is zero which indicates
+     *        the device is ready to receive. The current implementation
+     *        will drop characters
+     */
 
     uint64_t val_written = htifstate->pending_read;
     uint64_t resp = 0x100 | *buf;
@@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque)
     return 0;
 }
 
+/*
+ * See below the tohost register format.
+ *
+ * Bits 63:56 indicate the "device".
+ * Bits 55:48 indicate the "command".
+ *
+ * Device 0 is the syscall device, which is used to emulate Unixy syscalls.
+ * It only implements command 0, which has two subfunctions:
+ * - If bit 0 is clear, then bits 47:0 represent a pointer to a struct
+ *   describing the syscall.
+ * - If bit 1 is set, then bits 47:1 represent an exit code, with a zero
+ *   value indicating success and other values indicating failure.
+ *
+ * Device 1 is the blocking character device.
+ * - Command 0 reads a character
+ * - Command 1 writes a character from the 8 LSBs of tohost
+ *
+ * For RV32, the tohost register is zero-extended, so only device=0 and
+ * command=0 (i.e. HTIF syscalls/exit codes) are supported.
+ */
 static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
 {
-    uint8_t device = val_written >> 56;
-    uint8_t cmd = val_written >> 48;
+    uint8_t device = val_written >> HTIF_DEV_SHIFT;
+    uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
     uint64_t payload = val_written & 0xFFFFFFFFFFFFULL;
     int resp = 0;
 
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
      * 0: riscv-tests Pass/Fail Reporting Only (no syscall proxy)
      * 1: Console
      */
-    if (unlikely(device == 0x0)) {
+    if (unlikely(device == HTIF_DEV_SYSTEM)) {
         /* frontend syscall handler, shutdown and exit code support */
-        if (cmd == 0x0) {
+        if (cmd == HTIF_SYSTEM_CMD_SYSCALL) {
             if (payload & 0x1) {
                 /* exit code */
                 int exit_code = payload >> 1;
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
         } else {
             qemu_log("HTIF device %d: unknown command\n", device);
         }
-    } else if (likely(device == 0x1)) {
+    } else if (likely(device == HTIF_DEV_CONSOLE)) {
         /* HTIF Console */
-        if (cmd == 0x0) {
+        if (cmd == HTIF_CONSOLE_CMD_GETC) {
             /* this should be a queue, but not yet implemented as such */
             htifstate->pending_read = val_written;
             htifstate->env->mtohost = 0; /* clear to indicate we read */
             return;
-        } else if (cmd == 0x1) {
+        } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
             qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
             resp = 0x100 | (uint8_t)payload;
         } else {
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
             " payload: %016" PRIx64, device, cmd, payload & 0xFF, payload);
     }
     /*
-     * - latest bbl does not set fromhost to 0 if there is a value in tohost
-     * - with this code enabled, qemu hangs waiting for fromhost to go to 0
-     * - with this code disabled, qemu works with bbl priv v1.9.1 and v1.10
-     * - HTIF needs protocol documentation and a more complete state machine
-
-        while (!htifstate->fromhost_inprogress &&
-            htifstate->env->mfromhost != 0x0) {
-        }
-    */
+     * Latest bbl does not set fromhost to 0 if there is a value in tohost.
+     * With this code enabled, qemu hangs waiting for fromhost to go to 0.
+     * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
+     * HTIF needs protocol documentation and a more complete state machine.
+     *
+     *  while (!htifstate->fromhost_inprogress &&
+     *      htifstate->env->mfromhost != 0x0) {
+     *  }
+     */
     htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
     htifstate->env->mtohost = 0; /* clear to indicate we read */
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 
 /* CPU wrote to an HTIF register */
 static void htif_mm_write(void *opaque, hwaddr addr,
-                            uint64_t value, unsigned size)
+                          uint64_t value, unsigned size)
 {
     HTIFState *htifstate = opaque;
     if (addr == TOHOST_OFFSET1) {
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

struct HTIFState has 3 members for address space and memory region,
and are initialized during htif_mm_init(). But they are actually
useless. Drop them.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-4-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/riscv_htif.h | 7 ++-----
 hw/char/riscv_htif.c         | 7 ++-----
 hw/riscv/spike.c             | 5 ++---
 3 files changed, 6 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
     hwaddr tohost_offset;
     hwaddr fromhost_offset;
     MemoryRegion mmio;
-    MemoryRegion *address_space;
-    MemoryRegion *main_mem;
-    void *main_mem_ram_ptr;
 
     CPURISCVState *env;
     CharBackend chr;
@@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
 bool htif_uses_elf_symbols(void);
 
 /* legacy pre qom */
-HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base);
+HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
+                        Chardev *chr, uint64_t nonelf_base);
 
 #endif
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void)
     return (address_symbol_set == 3) ? true : false;
 }
 
-HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
-    CPURISCVState *env, Chardev *chr, uint64_t nonelf_base)
+HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
+                        Chardev *chr, uint64_t nonelf_base)
 {
     uint64_t base, size, tohost_offset, fromhost_offset;
 
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
     fromhost_offset = fromhost_addr - base;
 
     HTIFState *s = g_new0(HTIFState, 1);
-    s->address_space = address_space;
-    s->main_mem = main_mem;
-    s->main_mem_ram_ptr = memory_region_get_ram_ptr(main_mem);
     s->env = env;
     s->tohost_offset = tohost_offset;
     s->fromhost_offset = fromhost_offset;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                               fdt_load_addr);
 
     /* initialize HTIF using symbols found in load_kernel */
-    htif_mm_init(system_memory, mask_rom,
-                 &s->soc[0].harts[0].env, serial_hd(0),
-                 memmap[SPIKE_HTIF].base);
+    htif_mm_init(system_memory, &s->soc[0].harts[0].env,
+                 serial_hd(0), memmap[SPIKE_HTIF].base);
 }
 
 static void spike_machine_instance_init(Object *obj)
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

QEMU source codes tend to use 's' to represent the hardware state.
Let's use it for HTIFState.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-5-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 64 ++++++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static int htif_can_recv(void *opaque)
  */
 static void htif_recv(void *opaque, const uint8_t *buf, int size)
 {
-    HTIFState *htifstate = opaque;
+    HTIFState *s = opaque;
 
     if (size != 1) {
         return;
@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
      *        will drop characters
      */
 
-    uint64_t val_written = htifstate->pending_read;
+    uint64_t val_written = s->pending_read;
     uint64_t resp = 0x100 | *buf;
 
-    htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static int htif_be_change(void *opaque)
  * For RV32, the tohost register is zero-extended, so only device=0 and
  * command=0 (i.e. HTIF syscalls/exit codes) are supported.
  */
-static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
+static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
 {
     uint8_t device = val_written >> HTIF_DEV_SHIFT;
     uint8_t cmd = val_written >> HTIF_CMD_SHIFT;
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
         /* HTIF Console */
         if (cmd == HTIF_CONSOLE_CMD_GETC) {
             /* this should be a queue, but not yet implemented as such */
-            htifstate->pending_read = val_written;
-            htifstate->env->mtohost = 0; /* clear to indicate we read */
+            s->pending_read = val_written;
+            s->env->mtohost = 0; /* clear to indicate we read */
             return;
         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
-            qemu_chr_fe_write(&htifstate->chr, (uint8_t *)&payload, 1);
+            qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
             resp = 0x100 | (uint8_t)payload;
         } else {
             qemu_log("HTIF device %d: unknown command\n", device);
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *htifstate, uint64_t val_written)
      * With this code disabled, qemu works with bbl priv v1.9.1 and v1.10.
      * HTIF needs protocol documentation and a more complete state machine.
      *
-     *  while (!htifstate->fromhost_inprogress &&
-     *      htifstate->env->mfromhost != 0x0) {
+     *  while (!s->fromhost_inprogress &&
+     *      s->env->mfromhost != 0x0) {
      *  }
      */
-    htifstate->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
-    htifstate->env->mtohost = 0; /* clear to indicate we read */
+    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+    s->env->mtohost = 0; /* clear to indicate we read */
 }
 
-#define TOHOST_OFFSET1 (htifstate->tohost_offset)
-#define TOHOST_OFFSET2 (htifstate->tohost_offset + 4)
-#define FROMHOST_OFFSET1 (htifstate->fromhost_offset)
-#define FROMHOST_OFFSET2 (htifstate->fromhost_offset + 4)
+#define TOHOST_OFFSET1      (s->tohost_offset)
+#define TOHOST_OFFSET2      (s->tohost_offset + 4)
+#define FROMHOST_OFFSET1    (s->fromhost_offset)
+#define FROMHOST_OFFSET2    (s->fromhost_offset + 4)
 
 /* CPU wants to read an HTIF register */
 static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 {
-    HTIFState *htifstate = opaque;
+    HTIFState *s = opaque;
     if (addr == TOHOST_OFFSET1) {
-        return htifstate->env->mtohost & 0xFFFFFFFF;
+        return s->env->mtohost & 0xFFFFFFFF;
     } else if (addr == TOHOST_OFFSET2) {
-        return (htifstate->env->mtohost >> 32) & 0xFFFFFFFF;
+        return (s->env->mtohost >> 32) & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET1) {
-        return htifstate->env->mfromhost & 0xFFFFFFFF;
+        return s->env->mfromhost & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET2) {
-        return (htifstate->env->mfromhost >> 32) & 0xFFFFFFFF;
+        return (s->env->mfromhost >> 32) & 0xFFFFFFFF;
     } else {
         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
             (uint64_t)addr);
@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 static void htif_mm_write(void *opaque, hwaddr addr,
                           uint64_t value, unsigned size)
 {
-    HTIFState *htifstate = opaque;
+    HTIFState *s = opaque;
     if (addr == TOHOST_OFFSET1) {
-        if (htifstate->env->mtohost == 0x0) {
-            htifstate->allow_tohost = 1;
-            htifstate->env->mtohost = value & 0xFFFFFFFF;
+        if (s->env->mtohost == 0x0) {
+            s->allow_tohost = 1;
+            s->env->mtohost = value & 0xFFFFFFFF;
         } else {
-            htifstate->allow_tohost = 0;
+            s->allow_tohost = 0;
         }
     } else if (addr == TOHOST_OFFSET2) {
-        if (htifstate->allow_tohost) {
-            htifstate->env->mtohost |= value << 32;
-            htif_handle_tohost_write(htifstate, htifstate->env->mtohost);
+        if (s->allow_tohost) {
+            s->env->mtohost |= value << 32;
+            htif_handle_tohost_write(s, s->env->mtohost);
         }
     } else if (addr == FROMHOST_OFFSET1) {
-        htifstate->fromhost_inprogress = 1;
-        htifstate->env->mfromhost = value & 0xFFFFFFFF;
+        s->fromhost_inprogress = 1;
+        s->env->mfromhost = value & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET2) {
-        htifstate->env->mfromhost |= value << 32;
-        htifstate->fromhost_inprogress = 0;
+        s->env->mfromhost |= value << 32;
+        s->fromhost_inprogress = 0;
     } else {
         qemu_log("Invalid htif write: address %016" PRIx64 "\n",
             (uint64_t)addr);
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

At present for some unknown reason the HTIF registers (fromhost &
tohost) are defined in the RISC-V CPUArchState. It should really
be put in the HTIFState struct as it is only meaningful to HTIF.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-6-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/riscv_htif.h |  8 ++++----
 target/riscv/cpu.h           |  4 ----
 hw/char/riscv_htif.c         | 35 +++++++++++++++++------------------
 hw/riscv/spike.c             |  3 +--
 target/riscv/machine.c       |  6 ++----
 5 files changed, 24 insertions(+), 32 deletions(-)

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
 #include "exec/memory.h"
-#include "target/riscv/cpu.h"
 
 #define TYPE_HTIF_UART "riscv.htif.uart"
 
@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
     int allow_tohost;
     int fromhost_inprogress;
 
+    uint64_t tohost;
+    uint64_t fromhost;
     hwaddr tohost_offset;
     hwaddr fromhost_offset;
     MemoryRegion mmio;
 
-    CPURISCVState *env;
     CharBackend chr;
     uint64_t pending_read;
 } HTIFState;
@@ -XXX,XX +XXX,XX @@ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
 bool htif_uses_elf_symbols(void);
 
 /* legacy pre qom */
-HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
-                        Chardev *chr, uint64_t nonelf_base);
+HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
+                        uint64_t nonelf_base);
 
 #endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
     target_ulong sscratch;
     target_ulong mscratch;
 
-    /* temporary htif regs */
-    uint64_t mfromhost;
-    uint64_t mtohost;
-
     /* Sstc CSRs */
     uint64_t stimecmp;
 
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static void htif_recv(void *opaque, const uint8_t *buf, int size)
     uint64_t val_written = s->pending_read;
     uint64_t resp = 0x100 | *buf;
 
-    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+    s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
         if (cmd == HTIF_CONSOLE_CMD_GETC) {
             /* this should be a queue, but not yet implemented as such */
             s->pending_read = val_written;
-            s->env->mtohost = 0; /* clear to indicate we read */
+            s->tohost = 0; /* clear to indicate we read */
             return;
         } else if (cmd == HTIF_CONSOLE_CMD_PUTC) {
             qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1);
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
      * HTIF needs protocol documentation and a more complete state machine.
      *
      *  while (!s->fromhost_inprogress &&
-     *      s->env->mfromhost != 0x0) {
+     *      s->fromhost != 0x0) {
      *  }
      */
-    s->env->mfromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
-    s->env->mtohost = 0; /* clear to indicate we read */
+    s->fromhost = (val_written >> 48 << 48) | (resp << 16 >> 16);
+    s->tohost = 0; /* clear to indicate we read */
 }
 
 #define TOHOST_OFFSET1      (s->tohost_offset)
@@ -XXX,XX +XXX,XX @@ static uint64_t htif_mm_read(void *opaque, hwaddr addr, unsigned size)
 {
     HTIFState *s = opaque;
     if (addr == TOHOST_OFFSET1) {
-        return s->env->mtohost & 0xFFFFFFFF;
+        return s->tohost & 0xFFFFFFFF;
     } else if (addr == TOHOST_OFFSET2) {
-        return (s->env->mtohost >> 32) & 0xFFFFFFFF;
+        return (s->tohost >> 32) & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET1) {
-        return s->env->mfromhost & 0xFFFFFFFF;
+        return s->fromhost & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET2) {
-        return (s->env->mfromhost >> 32) & 0xFFFFFFFF;
+        return (s->fromhost >> 32) & 0xFFFFFFFF;
     } else {
         qemu_log("Invalid htif read: address %016" PRIx64 "\n",
             (uint64_t)addr);
@@ -XXX,XX +XXX,XX @@ static void htif_mm_write(void *opaque, hwaddr addr,
 {
     HTIFState *s = opaque;
     if (addr == TOHOST_OFFSET1) {
-        if (s->env->mtohost == 0x0) {
+        if (s->tohost == 0x0) {
             s->allow_tohost = 1;
-            s->env->mtohost = value & 0xFFFFFFFF;
+            s->tohost = value & 0xFFFFFFFF;
         } else {
             s->allow_tohost = 0;
         }
     } else if (addr == TOHOST_OFFSET2) {
         if (s->allow_tohost) {
-            s->env->mtohost |= value << 32;
-            htif_handle_tohost_write(s, s->env->mtohost);
+            s->tohost |= value << 32;
+            htif_handle_tohost_write(s, s->tohost);
         }
     } else if (addr == FROMHOST_OFFSET1) {
         s->fromhost_inprogress = 1;
-        s->env->mfromhost = value & 0xFFFFFFFF;
+        s->fromhost = value & 0xFFFFFFFF;
     } else if (addr == FROMHOST_OFFSET2) {
-        s->env->mfromhost |= value << 32;
+        s->fromhost |= value << 32;
         s->fromhost_inprogress = 0;
     } else {
         qemu_log("Invalid htif write: address %016" PRIx64 "\n",
@@ -XXX,XX +XXX,XX @@ bool htif_uses_elf_symbols(void)
     return (address_symbol_set == 3) ? true : false;
 }
 
-HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
-                        Chardev *chr, uint64_t nonelf_base)
+HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
+                        uint64_t nonelf_base)
 {
     uint64_t base, size, tohost_offset, fromhost_offset;
 
@@ -XXX,XX +XXX,XX @@ HTIFState *htif_mm_init(MemoryRegion *address_space, CPURISCVState *env,
     fromhost_offset = fromhost_addr - base;
 
     HTIFState *s = g_new0(HTIFState, 1);
-    s->env = env;
     s->tohost_offset = tohost_offset;
     s->fromhost_offset = fromhost_offset;
     s->pending_read = 0;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                               fdt_load_addr);
 
     /* initialize HTIF using symbols found in load_kernel */
-    htif_mm_init(system_memory, &s->soc[0].harts[0].env,
-                 serial_hd(0), memmap[SPIKE_HTIF].base);
+    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
 }
 
 static void spike_machine_instance_init(Object *obj)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmu_ctr_state = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 5,
-    .minimum_version_id = 5,
+    .version_id = 6,
+    .minimum_version_id = 6,
     .post_load = riscv_cpu_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
         VMSTATE_UINTTL(env.sscratch, RISCVCPU),
         VMSTATE_UINTTL(env.mscratch, RISCVCPU),
-        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
-        VMSTATE_UINT64(env.mtohost, RISCVCPU),
         VMSTATE_UINT64(env.stimecmp, RISCVCPU),
 
         VMSTATE_END_OF_LIST()
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

There are forward declarations for 'vmstate_htif' and 'htif_io_ops'
in riscv_htif.h however there are no definitions in the C codes.

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
     uint64_t pending_read;
 } HTIFState;
 
-extern const VMStateDescription vmstate_htif;
-extern const MemoryRegionOps htif_io_ops;
-
 /* HTIF symbol callback */
 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
     uint64_t st_size);
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

At present the HTIF proxy syscall is unsupported. On RV32, only
device 0 is supported so there is no console device for RV32.
The only way to implement console funtionality on RV32 is to
support the SYS_WRITE syscall.

With this commit, the Spike machine is able to boot the 32-bit
OpenSBI generic image.

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #define HTIF_CONSOLE_CMD_GETC   0
 #define HTIF_CONSOLE_CMD_PUTC   1
 
+/* PK system call number */
+#define PK_SYS_WRITE            64
+
 static uint64_t fromhost_addr, tohost_addr;
 static int address_symbol_set;
 
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
                 int exit_code = payload >> 1;
                 exit(exit_code);
             } else {
-                qemu_log_mask(LOG_UNIMP, "pk syscall proxy not supported\n");
+                uint64_t syscall[8];
+                cpu_physical_memory_read(payload, syscall, sizeof(syscall));
+                if (syscall[0] == PK_SYS_WRITE &&
+                    syscall[1] == HTIF_DEV_CONSOLE &&
+                    syscall[3] == HTIF_CONSOLE_CMD_PUTC) {
+                    uint8_t ch;
+                    cpu_physical_memory_read(syscall[2], &ch, 1);
+                    qemu_chr_fe_write(&s->chr, &ch, 1);
+                    resp = 0x100 | (uint8_t)payload;
+                } else {
+                    qemu_log_mask(LOG_UNIMP,
+                                  "pk syscall proxy not supported\n");
+                }
             }
         } else {
             qemu_log("HTIF device %d: unknown command\n", device);
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

Spike machine now supports OpenSBI plain binary bios image, so the
comments are no longer valid.

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                 mask_rom);
 
-    /*
-     * Not like other RISC-V machines that use plain binary bios images,
-     * keeping ELF files here was intentional because BIN files don't work
-     * for the Spike machine as HTIF emulation depends on ELF parsing.
-     */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
                                     RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The only caller is riscv_find_and_load_firmware(), which is in the same
file.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221221182300.307900-5-dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-10-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  1 -
 hw/riscv/boot.c         | 44 ++++++++++++++++++++---------------------
 2 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
                                           symbol_fn_t sym_cb);
-char *riscv_find_firmware(const char *firmware_filename);
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb);
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
     }
 }
 
+static char *riscv_find_firmware(const char *firmware_filename)
+{
+    char *filename;
+
+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
+    if (filename == NULL) {
+        if (!qtest_enabled()) {
+            /*
+             * We only ship OpenSBI binary bios images in the QEMU source.
+             * For machines that use images other than the default bios,
+             * running QEMU test will complain hence let's suppress the error
+             * report for QEMU testing.
+             */
+            error_report("Unable to load the RISC-V firmware \"%s\"",
+                         firmware_filename);
+            exit(1);
+        }
+    }
+
+    return filename;
+}
+
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
     return firmware_end_addr;
 }
 
-char *riscv_find_firmware(const char *firmware_filename)
-{
-    char *filename;
-
-    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
-    if (filename == NULL) {
-        if (!qtest_enabled()) {
-            /*
-             * We only ship OpenSBI binary bios images in the QEMU source.
-             * For machines that use images other than the default bios,
-             * running QEMU test will complain hence let's suppress the error
-             * report for QEMU testing.
-             */
-            error_report("Unable to load the RISC-V firmware \"%s\"",
-                         firmware_filename);
-            exit(1);
-        }
-    }
-
-    return filename;
-}
-
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb)
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Some boards are duplicating the 'riscv_find_and_load_firmware' call
because the 32 and 64 bits images have different names. Create
a function to handle this detail instead of hardcoding it in the boards.

Ideally we would bake this logic inside riscv_find_and_load_firmware(),
or even create a riscv_load_default_firmware(), but at this moment we
cannot infer whether the machine is running 32 or 64 bits without
accessing RISCVHartArrayState, which in turn can't be accessed via the
common code from boot.c. In the end we would exchange 'firmware_name'
for a flag with riscv_is_32bit(), which isn't much better than what we
already have today.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20221221182300.307900-6-dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-11-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  1 +
 hw/riscv/boot.c         |  9 +++++++++
 hw/riscv/sifive_u.c     | 11 ++++-------
 hw/riscv/spike.c        | 14 +++++---------
 hw/riscv/virt.c         | 10 +++-------
 5 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
                                           hwaddr firmware_load_addr,
                                           symbol_fn_t sym_cb);
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb);
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
     }
 }
 
+const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
+{
+    if (riscv_is_32bit(harts)) {
+        return RISCV32_BIOS_BIN;
+    }
+
+    return RISCV64_BIOS_BIN;
+}
+
 static char *riscv_find_firmware(const char *firmware_filename)
 {
     char *filename;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name;
     uint32_t start_addr_hi32 = 0x00000000;
     int i;
     uint32_t fdt_load_addr;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         break;
     }
 
-    if (riscv_is_32bit(&s->soc.u_cpus)) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, start_addr, NULL);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, start_addr, NULL);
-    }
+    firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     start_addr, NULL);
 
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
     char *soc_name;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                 mask_rom);
 
-    if (riscv_is_32bit(&s->soc[0])) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                    htif_symbol_callback);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
-                                    htif_symbol_callback);
-    }
+    firmware_name = riscv_default_firmware_name(&s->soc[0]);
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     memmap[SPIKE_DRAM].base,
+                                                     htif_symbol_callback);
 
     /* Load kernel */
     if (machine->kernel_filename) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
     MachineState *machine = MACHINE(s);
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
+    const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
         }
     }
 
-    if (riscv_is_32bit(&s->soc[0])) {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_BIN, start_addr, NULL);
-    } else {
-        firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_BIN, start_addr, NULL);
-    }
+    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
+                                                     start_addr, NULL);
 
     /*
      * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

Rename previous riscv_find_firmware() to riscv_find_bios(), and
introduce a new riscv_find_firmware() to implement the first half
part of the work done in riscv_find_and_load_firmware().

This new API is helpful for machine that wants to know the final
chosen firmware file name but does not want to load it.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221229091828.1945072-12-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h |  2 ++
 hw/riscv/boot.c         | 39 +++++++++++++++++++++++++--------------
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           hwaddr firmware_load_addr,
                                           symbol_fn_t sym_cb);
 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
+char *riscv_find_firmware(const char *firmware_filename,
+                          const char *default_machine_firmware);
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb);
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_default_firmware_name(RISCVHartArrayState *harts)
     return RISCV64_BIOS_BIN;
 }
 
-static char *riscv_find_firmware(const char *firmware_filename)
+static char *riscv_find_bios(const char *bios_filename)
 {
     char *filename;
 
-    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_filename);
     if (filename == NULL) {
         if (!qtest_enabled()) {
             /*
@@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename)
              * running QEMU test will complain hence let's suppress the error
              * report for QEMU testing.
              */
-            error_report("Unable to load the RISC-V firmware \"%s\"",
-                         firmware_filename);
+            error_report("Unable to find the RISC-V BIOS \"%s\"",
+                         bios_filename);
             exit(1);
         }
     }
@@ -XXX,XX +XXX,XX @@ static char *riscv_find_firmware(const char *firmware_filename)
     return filename;
 }
 
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                          const char *default_machine_firmware,
-                                          hwaddr firmware_load_addr,
-                                          symbol_fn_t sym_cb)
+char *riscv_find_firmware(const char *firmware_filename,
+                          const char *default_machine_firmware)
 {
-    char *firmware_filename = NULL;
-    target_ulong firmware_end_addr = firmware_load_addr;
+    char *filename = NULL;
 
-    if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
+    if ((!firmware_filename) || (!strcmp(firmware_filename, "default"))) {
         /*
          * The user didn't specify -bios, or has specified "-bios default".
          * That means we are going to load the OpenSBI binary included in
          * the QEMU source.
          */
-        firmware_filename = riscv_find_firmware(default_machine_firmware);
-    } else if (strcmp(machine->firmware, "none")) {
-        firmware_filename = riscv_find_firmware(machine->firmware);
+        filename = riscv_find_bios(default_machine_firmware);
+    } else if (strcmp(firmware_filename, "none")) {
+        filename = riscv_find_bios(firmware_filename);
     }
 
+    return filename;
+}
+
+target_ulong riscv_find_and_load_firmware(MachineState *machine,
+                                          const char *default_machine_firmware,
+                                          hwaddr firmware_load_addr,
+                                          symbol_fn_t sym_cb)
+{
+    char *firmware_filename;
+    target_ulong firmware_end_addr = firmware_load_addr;
+
+    firmware_filename = riscv_find_firmware(machine->firmware,
+                                            default_machine_firmware);
+
     if (firmware_filename) {
         /* If not "none" load the firmware */
         firmware_end_addr = riscv_load_firmware(firmware_filename,
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

At present create_fdt() calls htif_uses_elf_symbols() to determine
whether to insert a <reg> property for the HTIF. This unfortunately
creates a hidden dependency to riscv_load_{firmware,kernel} that
create_fdt() must be called after the ELF {firmware,kernel} image
has been loaded.

Decouple such dependency be adding a new parameter to create_fdt(),
whether custom HTIF base address is used. The flag will be set if
non ELF {firmware,kernel} image is given by user.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20221229091828.1945072-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/riscv_htif.h |  5 +--
 hw/char/riscv_htif.c         | 17 +++++-----
 hw/riscv/spike.c             | 61 ++++++++++++++++++++++++++++++------
 3 files changed, 59 insertions(+), 24 deletions(-)

diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/riscv_htif.h
+++ b/include/hw/char/riscv_htif.h
@@ -XXX,XX +XXX,XX @@ typedef struct HTIFState {
 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
     uint64_t st_size);
 
-/* Check if HTIF uses ELF symbols */
-bool htif_uses_elf_symbols(void);
-
 /* legacy pre qom */
 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
-                        uint64_t nonelf_base);
+                        uint64_t nonelf_base, bool custom_base);
 
 #endif
diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #define PK_SYS_WRITE            64
 
 static uint64_t fromhost_addr, tohost_addr;
-static int address_symbol_set;
 
 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value,
                           uint64_t st_size)
 {
     if (strcmp("fromhost", st_name) == 0) {
-        address_symbol_set |= 1;
         fromhost_addr = st_value;
         if (st_size != 8) {
             error_report("HTIF fromhost must be 8 bytes");
             exit(1);
         }
     } else if (strcmp("tohost", st_name) == 0) {
-        address_symbol_set |= 2;
         tohost_addr = st_value;
         if (st_size != 8) {
             error_report("HTIF tohost must be 8 bytes");
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
     .write = htif_mm_write,
 };
 
-bool htif_uses_elf_symbols(void)
-{
-    return (address_symbol_set == 3) ? true : false;
-}
-
 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
-                        uint64_t nonelf_base)
+                        uint64_t nonelf_base, bool custom_base)
 {
     uint64_t base, size, tohost_offset, fromhost_offset;
 
-    if (!htif_uses_elf_symbols()) {
+    if (custom_base) {
         fromhost_addr = nonelf_base;
         tohost_addr = nonelf_base + 8;
+    } else {
+        if (!fromhost_addr || !tohost_addr) {
+            error_report("Invalid HTIF fromhost or tohost address");
+            exit(1);
+        }
     }
 
     base = MIN(tohost_addr, fromhost_addr);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = {
 };
 
 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
+                       uint64_t mem_size, const char *cmdline,
+                       bool is_32_bit, bool htif_custom_base)
 {
     void *fdt;
     uint64_t addr, size;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/htif");
     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
-    if (!htif_uses_elf_symbols()) {
+    if (htif_custom_base) {
         qemu_fdt_setprop_cells(fdt, "/htif", "reg",
             0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size);
     }
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
     }
 }
 
+static bool spike_test_elf_image(char *filename)
+{
+    Error *err = NULL;
+
+    load_elf_hdr(filename, NULL, NULL, &err);
+    if (err) {
+        error_free(err);
+        return false;
+    } else {
+        return true;
+    }
+}
+
 static void spike_board_init(MachineState *machine)
 {
     const MemMapEntry *memmap = spike_memmap;
     SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    target_ulong firmware_end_addr, kernel_start_addr;
-    const char *firmware_name;
+    target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
+    target_ulong kernel_start_addr;
+    char *firmware_name;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
     char *soc_name;
     int i, base_hartid, hart_count;
+    bool htif_custom_base = false;
 
     /* Check socket count limit */
     if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
                                 mask_rom);
 
-    firmware_name = riscv_default_firmware_name(&s->soc[0]);
-    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
-                                                     memmap[SPIKE_DRAM].base,
-                                                     htif_symbol_callback);
+    /* Find firmware */
+    firmware_name = riscv_find_firmware(machine->firmware,
+                        riscv_default_firmware_name(&s->soc[0]));
+
+    /*
+     * Test the given firmware or kernel file to see if it is an ELF image.
+     * If it is an ELF, we assume it contains the symbols required for
+     * the HTIF console, otherwise we fall back to use the custom base
+     * passed from device tree for the HTIF console.
+     */
+    if (!firmware_name && !machine->kernel_filename) {
+        htif_custom_base = true;
+    } else {
+        if (firmware_name) {
+            htif_custom_base = !spike_test_elf_image(firmware_name);
+        }
+        if (!htif_custom_base && machine->kernel_filename) {
+            htif_custom_base = !spike_test_elf_image(machine->kernel_filename);
+        }
+    }
+
+    /* Load firmware */
+    if (firmware_name) {
+        firmware_end_addr = riscv_load_firmware(firmware_name,
+                                                memmap[SPIKE_DRAM].base,
+                                                htif_symbol_callback);
+        g_free(firmware_name);
+    }
 
     /* Load kernel */
     if (machine->kernel_filename) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     /* Create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]));
+               riscv_is_32bit(&s->soc[0]), htif_custom_base);
 
     /* Load initrd */
     if (machine->kernel_filename && machine->initrd_filename) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                               fdt_load_addr);
 
     /* initialize HTIF using symbols found in load_kernel */
-    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base);
+    htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base,
+                 htif_custom_base);
 }
 
 static void spike_machine_instance_init(Object *obj)
-- 
2.39.0

From: Dongxue Zhang <elta.era@gmail.com>

The elen check should be cpu->cfg.elen in range [8, 64].

Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <167236721596.15277.2653405273227256289-0@git.sr.ht>
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
                         "Vector extension ELEN must be power of 2");
                 return;
             }
-            if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
+            if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
                 error_setg(errp,
                         "Vector extension implementation only supports ELEN "
                         "in the range [8, 64]");
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.

'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.

The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:

(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
        SKIP: requires OpenSBI fix to work

[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 tests/avocado/riscv_opensbi.py

diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/avocado/riscv_opensbi.py
@@ -XXX,XX +XXX,XX @@
+# OpenSBI boot test for RISC-V machines
+#
+# Copyright (c) 2022, Ventana Micro
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later.  See the COPYING file in the top-level directory.
+
+from avocado_qemu import QemuSystemTest
+from avocado import skip
+from avocado_qemu import wait_for_console_pattern
+
+class RiscvOpenSBI(QemuSystemTest):
+    """
+    :avocado: tags=accel:tcg
+    """
+    timeout = 5
+
+    def boot_opensbi(self):
+        self.vm.set_console()
+        self.vm.launch()
+        wait_for_console_pattern(self, 'Platform Name')
+        wait_for_console_pattern(self, 'Boot HART MEDELEG')
+
+    @skip("requires OpenSBI fix to work")
+    def test_riscv32_spike(self):
+        """
+        :avocado: tags=arch:riscv32
+        :avocado: tags=machine:spike
+        """
+        self.boot_opensbi()
+
+    def test_riscv64_spike(self):
+        """
+        :avocado: tags=arch:riscv64
+        :avocado: tags=machine:spike
+        """
+        self.boot_opensbi()
+
+    def test_riscv32_sifive_u(self):
+        """
+        :avocado: tags=arch:riscv32
+        :avocado: tags=machine:sifive_u
+        """
+        self.boot_opensbi()
+
+    def test_riscv64_sifive_u(self):
+        """
+        :avocado: tags=arch:riscv64
+        :avocado: tags=machine:sifive_u
+        """
+        self.boot_opensbi()
+
+    def test_riscv32_virt(self):
+        """
+        :avocado: tags=arch:riscv32
+        :avocado: tags=machine:virt
+        """
+        self.boot_opensbi()
+
+    def test_riscv64_virt(self):
+        """
+        :avocado: tags=arch:riscv64
+        :avocado: tags=machine:virt
+        """
+        self.boot_opensbi()
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.

Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/spike.h |  2 --
 hw/riscv/spike.c         | 12 +++++-------
 2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -XXX,XX +XXX,XX @@ struct SpikeState {
 
     /*< public >*/
     RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
-    void *fdt;
-    int fdt_size;
 };
 
 enum {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
                        bool is_32_bit, bool htif_custom_base)
 {
     void *fdt;
+    int fdt_size;
     uint64_t addr, size;
     unsigned long clint_addr;
     int cpu, socket;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
         "sifive,clint0", "riscv,clint0"
     };
 
-    fdt = s->fdt = create_device_tree(&s->fdt_size);
+    fdt = mc->fdt = create_device_tree(&fdt_size);
     if (!fdt) {
         error_report("create_device_tree() failed");
         exit(1);
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                        machine->ram_size, kernel_entry,
                                        &start);
-        qemu_fdt_setprop_cell(s->fdt, "/chosen",
+        qemu_fdt_setprop_cell(machine->fdt, "/chosen",
                               "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+        qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
                               end);
     }
 
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
-                                   machine->ram_size, s->fdt);
-
-    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
-    machine->fdt = s->fdt;
+                                   machine->ram_size, machine->fdt);
 
     /* load the reset vector */
     riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.

Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_u.h |  3 ---
 hw/riscv/sifive_u.c         | 15 ++++++---------
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUState {
     /*< public >*/
     SiFiveUSoCState soc;
 
-    void *fdt;
-    int fdt_size;
-
     bool start_in_flash;
     uint32_t msel;
     uint32_t serial;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
 {
     MachineState *ms = MACHINE(qdev_get_machine());
     void *fdt;
-    int cpu;
+    int cpu, fdt_size;
     uint32_t *cells;
     char *nodename;
     uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     };
 
     if (ms->dtb) {
-        fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
+        fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size);
         if (!fdt) {
             error_report("load_device_tree() failed");
             exit(1);
         }
         goto update_bootargs;
     } else {
-        fdt = s->fdt = create_device_tree(&s->fdt_size);
+        fdt = ms->fdt = create_device_tree(&fdt_size);
         if (!fdt) {
             error_report("create_device_tree() failed");
             exit(1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
             hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                            machine->ram_size, kernel_entry,
                                            &start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen",
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
                                   "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
     } else {
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
 
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
-                                   machine->ram_size, s->fdt);
+                                   machine->ram_size, machine->fdt);
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
         start_addr_hi32 = (uint64_t)start_addr >> 32;
     }
 
-    /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
-    machine->fdt = s->fdt;
-
     /* reset vector */
     uint32_t reset_vec[12] = {
         s->msel,                       /* MSEL pin state */
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works
under the assumption that a 'filename' parameter is always not NULL.

This is currently the case since all callers of these functions are
checking for NULL before calling them. Add an g_assert() to make sure
that a NULL value in these cases are to be considered a bug.

Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
     uint64_t firmware_entry, firmware_end;
     ssize_t firmware_size;
 
+    g_assert(firmware_filename != NULL);
+
     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
                          &firmware_entry, NULL, &firmware_end, NULL,
                          0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
 {
     uint64_t kernel_load_base, kernel_entry;
 
+    g_assert(kernel_filename != NULL);
+
     /*
      * NB: Use low address not ELF entry point to ensure that the fw_dynamic
      * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
 {
     ssize_t size;
 
+    g_assert(filename != NULL);
+
     /*
      * We want to put the initrd far enough into RAM that when the
      * kernel is uncompressed it will not clobber the initrd. However
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

This will make the code more in line with what the other boards are
doing. We'll also avoid an extra check to machine->kernel_filename since
we already checked that before executing riscv_load_kernel().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         g_free(firmware_name);
     }
 
+    /* Create device tree */
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
+               riscv_is_32bit(&s->soc[0]), htif_custom_base);
+
     /* Load kernel */
     if (machine->kernel_filename) {
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = riscv_load_kernel(machine->kernel_filename,
                                          kernel_start_addr,
                                          htif_symbol_callback);
+
+        if (machine->initrd_filename) {
+            hwaddr start;
+            hwaddr end = riscv_load_initrd(machine->initrd_filename,
+                                           machine->ram_size, kernel_entry,
+                                           &start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
+                                  "linux,initrd-start", start);
+            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
+                                  end);
+        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_entry = 0;
     }
 
-    /* Create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]), htif_custom_base);
-
-    /* Load initrd */
-    if (machine->kernel_filename && machine->initrd_filename) {
-        hwaddr start;
-        hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                       machine->ram_size, kernel_entry,
-                                       &start);
-        qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                              "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
-                              end);
-    }
-
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
                                    machine->ram_size, machine->fdt);
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

riscv_load_initrd() returns the initrd end addr while also writing a
'start' var to mark the addr start. These informations are being used
just to write the initrd FDT node. Every existing caller of
riscv_load_initrd() is writing the FDT in the same manner.

We can simplify things by writing the FDT inside riscv_load_initrd(),
sparing callers from having to manage start/end addrs to write the FDT
themselves.

An 'if (fdt)' check is already inserted at the end of the function
because we'll end up using it later on with other boards that doesn´t
have a FDT.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    |  4 ++--
 hw/riscv/boot.c            | 18 ++++++++++++------
 hw/riscv/microchip_pfsoc.c | 10 ++--------
 hw/riscv/sifive_u.c        | 10 ++--------
 hw/riscv/spike.c           | 10 ++--------
 hw/riscv/virt.c            | 10 ++--------
 6 files changed, 22 insertions(+), 40 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
 target_ulong riscv_load_kernel(const char *kernel_filename,
                                target_ulong firmware_end_addr,
                                symbol_fn_t sym_cb);
-hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
-                         uint64_t kernel_entry, hwaddr *start);
+void riscv_load_initrd(const char *filename, uint64_t mem_size,
+                       uint64_t kernel_entry, void *fdt);
 uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
     exit(1);
 }
 
-hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
-                         uint64_t kernel_entry, hwaddr *start)
+void riscv_load_initrd(const char *filename, uint64_t mem_size,
+                       uint64_t kernel_entry, void *fdt)
 {
+    hwaddr start, end;
     ssize_t size;
 
     g_assert(filename != NULL);
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
      * halfway into RAM, and for boards with 256MB of RAM or more we put
      * the initrd at 128MB.
      */
-    *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
+    start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
 
-    size = load_ramdisk(filename, *start, mem_size - *start);
+    size = load_ramdisk(filename, start, mem_size - start);
     if (size == -1) {
-        size = load_image_targphys(filename, *start, mem_size - *start);
+        size = load_image_targphys(filename, start, mem_size - start);
         if (size == -1) {
             error_report("could not load ramdisk '%s'", filename);
             exit(1);
         }
     }
 
-    return *start + size;
+    /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+    if (fdt) {
+        end = start + size;
+        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+    }
 }
 
 uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                                          kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-end", end);
+            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+                              kernel_entry, machine->fdt);
         }
 
         if (machine->kernel_cmdline && *machine->kernel_cmdline) {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
                                          kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
-                                  end);
+            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+                              kernel_entry, machine->fdt);
         }
     } else {
        /*
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                          htif_symbol_callback);
 
         if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
-                                  end);
+            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+                              kernel_entry, machine->fdt);
         }
     } else {
        /*
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
                                          kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
-            hwaddr start;
-            hwaddr end = riscv_load_initrd(machine->initrd_filename,
-                                           machine->ram_size, kernel_entry,
-                                           &start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
-                                  "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
-                                  end);
+            riscv_load_initrd(machine->initrd_filename, machine->ram_size,
+                              kernel_entry, machine->fdt);
         }
     } else {
        /*
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The sifive_u, spike and virt machines are writing the 'bootargs' FDT
node during their respective create_fdt().

Given that bootargs is written only when '-append' is used, and this
option is only allowed with the '-kernel' option, which in turn is
already being check before executing riscv_load_kernel(), write
'bootargs' in the same code path as riscv_load_kernel().

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 11 +++++------
 hw/riscv/spike.c    |  9 +++++----
 hw/riscv/virt.c     | 11 +++++------
 3 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
             error_report("load_device_tree() failed");
             exit(1);
         }
-        goto update_bootargs;
     } else {
         fdt = ms->fdt = create_device_tree(&fdt_size);
         if (!fdt) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 
     g_free(nodename);
-
-update_bootargs:
-    if (cmdline && *cmdline) {
-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-    }
 }
 
 static void sifive_u_machine_reset(void *opaque, int n, int level)
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
             riscv_load_initrd(machine->initrd_filename, machine->ram_size,
                               kernel_entry, machine->fdt);
         }
+
+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+                                    machine->kernel_cmdline);
+        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
 
     qemu_fdt_add_subnode(fdt, "/chosen");
     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
-
-    if (cmdline && *cmdline) {
-        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-    }
 }
 
 static bool spike_test_elf_image(char *filename)
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
             riscv_load_initrd(machine->initrd_filename, machine->ram_size,
                               kernel_entry, machine->fdt);
         }
+
+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+                                    machine->kernel_cmdline);
+        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
             error_report("load_device_tree() failed");
             exit(1);
         }
-        goto update_bootargs;
     } else {
         mc->fdt = create_device_tree(&s->fdt_size);
         if (!mc->fdt) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     create_fdt_fw_cfg(s, memmap);
     create_fdt_pmu(s);
 
-update_bootargs:
-    if (cmdline && *cmdline) {
-        qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
-    }
-
     /* Pass seed to RNG */
     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
     qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
             riscv_load_initrd(machine->initrd_filename, machine->ram_size,
                               kernel_entry, machine->fdt);
         }
+
+        if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+            qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs",
+                                    machine->kernel_cmdline);
+        }
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    | 3 +--
 hw/riscv/boot.c            | 6 ++++--
 hw/riscv/microchip_pfsoc.c | 3 +--
 hw/riscv/sifive_u.c        | 3 +--
 hw/riscv/spike.c           | 3 +--
 hw/riscv/virt.c            | 3 +--
 6 files changed, 9 insertions(+), 12 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All callers are using kernel_filename as machine->kernel_filename.

This will also simplify the changes in riscv_load_kernel() that we're
going to do next.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    | 2 +-
 hw/riscv/boot.c            | 3 ++-
 hw/riscv/microchip_pfsoc.c | 3 +--
 hw/riscv/opentitan.c       | 3 +--
 hw/riscv/sifive_e.c        | 3 +--
 hw/riscv/sifive_u.c        | 3 +--
 hw/riscv/spike.c           | 3 +--
 hw/riscv/virt.c            | 3 +--
 8 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename,
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr firmware_load_addr,
                                  symbol_fn_t sym_cb);
-target_ulong riscv_load_kernel(const char *kernel_filename,
+target_ulong riscv_load_kernel(MachineState *machine,
                                target_ulong firmware_end_addr,
                                symbol_fn_t sym_cb);
 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry);
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
     exit(1);
 }
 
-target_ulong riscv_load_kernel(const char *kernel_filename,
+target_ulong riscv_load_kernel(MachineState *machine,
                                target_ulong kernel_start_addr,
                                symbol_fn_t sym_cb)
 {
+    const char *kernel_filename = machine->kernel_filename;
     uint64_t kernel_load_base, kernel_entry;
 
     g_assert(kernel_filename != NULL);
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                         kernel_start_addr, NULL);
+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
             riscv_load_initrd(machine, kernel_entry);
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void opentitan_board_init(MachineState *machine)
     }
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename,
-                          memmap[IBEX_DEV_RAM].base, NULL);
+        riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
     }
 }
 
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine->kernel_filename,
-                          memmap[SIFIVE_E_DEV_DTIM].base, NULL);
+        riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
     }
 }
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                         kernel_start_addr, NULL);
+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
             riscv_load_initrd(machine, kernel_entry);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                         kernel_start_addr,
+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr,
                                          htif_symbol_callback);
 
         if (machine->initrd_filename) {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine->kernel_filename,
-                                         kernel_start_addr, NULL);
+        kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL);
 
         if (machine->initrd_filename) {
             riscv_load_initrd(machine, kernel_entry);
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

There is an informal contract between the cpu_init() functions and
riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the
default settings were loaded via register_cpu_props() and do validations
to set env.misa_ext. If it's not zero, skip this whole process and
assume that the board somehow did everything.

At this moment, all SiFive CPUs are setting a non-zero misa_ext during
their cpu_init() and skipping a good chunk of riscv_cpu_realize().  This
causes problems when the code being skipped in riscv_cpu_realize()
contains fixes or assumptions that affects all CPUs, meaning that SiFive
CPUs are missing out.

To allow this code to not be skipped anymore, all the cpu->cfg.ext_*
attributes needs to be set during cpu_init() time. At this moment this
is being done in register_cpu_props(). The SiFive boards are setting
their own extensions during cpu_init() though, meaning that they don't
want all the defaults from register_cpu_props().

Let's move the contract between *_cpu_init() and riscv_cpu_realize() to
register_cpu_props(). Inside this function we'll check if
cpu->env.misa_ext was set and, if that's the case, set all relevant
cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case
as is today, i.e. loading all the defaults from riscv_cpu_extensions[].

register_cpu_props() can then be called by all the cpu_init() functions,
including the SiFive ones. This will make all CPUs behave more in line
with what riscv_cpu_realize() expects.

This will also make the cpu_init() functions even more alike, but at this
moment we would need some design changes in how we're initializing
extensions/attributes (e.g. some CPUs are setting cfg options after
register_cpu_props(), so we can't simply add the function to a common
post_init() hook)  to make a common cpu_init() code across all CPUs.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h |  4 ++++
 target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
+/*
+ * Consider updating register_cpu_props() when adding
+ * new MISA bits here.
+ */
 #define RVI RV('I')
 #define RVE RV('E') /* E and I are mutually exclusive */
 #define RVM RV('M')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
@@ -XXX,XX +XXX,XX @@ static void rv64_sifive_e_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_10_0);
     cpu->cfg.mmu = false;
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_10_0);
     cpu->cfg.mmu = false;
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_11_0);
     cpu->cfg.mmu = false;
     cpu->cfg.epmp = true;
@@ -XXX,XX +XXX,XX @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
     RISCVCPU *cpu = RISCV_CPU(obj);
 
     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+    register_cpu_props(DEVICE(obj));
     set_priv_version(env, PRIV_VERSION_1_10_0);
     cpu->cfg.mmu = false;
 }
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+/*
+ * Register CPU props based on env.misa_ext. If a non-zero
+ * value was set, register only the required cpu->cfg.ext_*
+ * properties and leave. env.misa_ext = 0 means that we want
+ * all the default properties to be registered.
+ */
 static void register_cpu_props(DeviceState *dev)
 {
+    RISCVCPU *cpu = RISCV_CPU(OBJECT(dev));
+    uint32_t misa_ext = cpu->env.misa_ext;
     Property *prop;
 
+    /*
+     * If misa_ext is not zero, set cfg properties now to
+     * allow them to be read during riscv_cpu_realize()
+     * later on.
+     */
+    if (cpu->env.misa_ext != 0) {
+        cpu->cfg.ext_i = misa_ext & RVI;
+        cpu->cfg.ext_e = misa_ext & RVE;
+        cpu->cfg.ext_m = misa_ext & RVM;
+        cpu->cfg.ext_a = misa_ext & RVA;
+        cpu->cfg.ext_f = misa_ext & RVF;
+        cpu->cfg.ext_d = misa_ext & RVD;
+        cpu->cfg.ext_v = misa_ext & RVV;
+        cpu->cfg.ext_c = misa_ext & RVC;
+        cpu->cfg.ext_s = misa_ext & RVS;
+        cpu->cfg.ext_u = misa_ext & RVU;
+        cpu->cfg.ext_h = misa_ext & RVH;
+        cpu->cfg.ext_j = misa_ext & RVJ;
+
+        /*
+         * We don't want to set the default riscv_cpu_extensions
+         * in this case.
+         */
+        return;
+    }
+
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         qdev_property_add_static(dev, prop);
     }
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

All RISCV CPUs are setting cpu->cfg during their cpu_init() functions,
meaning that there's no reason to skip all the misa validation and setup
if misa_ext was set beforehand - especially since we're setting an
updated value in set_misa() in the end.

Put this code chunk into a new riscv_cpu_validate_set_extensions()
helper and always execute it regardless of what the board set in
env->misa_ext.

This will put more responsibility in how each board is going to init
their attributes and extensions if they're not using the defaults.
It'll also allow realize() to do its job looking only at the extensions
enabled per se, not corner cases that some CPUs might have, and we won't
have to change multiple code paths to fix or change how extensions work.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com>
[ Changes by AF:
 - Rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 399 +++++++++++++++++++++++----------------------
 1 file changed, 205 insertions(+), 194 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
     }
 }
 
+/*
+ * Check consistency between chosen extensions while setting
+ * cpu->cfg accordingly, doing a set_misa() in the end.
+ */
+static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
+{
+    CPURISCVState *env = &cpu->env;
+    uint32_t ext = 0;
+
+    /* Do some ISA extension error checking */
+    if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
+                            cpu->cfg.ext_a && cpu->cfg.ext_f &&
+                            cpu->cfg.ext_d &&
+                            cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+        warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
+        cpu->cfg.ext_i = true;
+        cpu->cfg.ext_m = true;
+        cpu->cfg.ext_a = true;
+        cpu->cfg.ext_f = true;
+        cpu->cfg.ext_d = true;
+        cpu->cfg.ext_icsr = true;
+        cpu->cfg.ext_ifencei = true;
+    }
+
+    if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
+        error_setg(errp,
+                   "I and E extensions are incompatible");
+        return;
+    }
+
+    if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+        error_setg(errp,
+                   "Either I or E extension must be set");
+        return;
+    }
+
+    if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
+        error_setg(errp,
+                   "Setting S extension without U extension is illegal");
+        return;
+    }
+
+    if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+        error_setg(errp,
+                   "H depends on an I base integer ISA with 32 x registers");
+        return;
+    }
+
+    if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
+        error_setg(errp, "H extension implicitly requires S-mode");
+        return;
+    }
+
+    if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
+        error_setg(errp, "F extension requires Zicsr");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
+        error_setg(errp, "Zawrs extension requires A extension");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
+        error_setg(errp, "Zfh/Zfhmin extensions require F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
+        error_setg(errp, "D extension requires F extension");
+        return;
+    }
+
+    if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
+        error_setg(errp, "V extension requires D extension");
+        return;
+    }
+
+    if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
+        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+        return;
+    }
+
+    /* Set the ISA extensions, checks should have happened above */
+    if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
+        cpu->cfg.ext_zhinxmin) {
+        cpu->cfg.ext_zfinx = true;
+    }
+
+    if (cpu->cfg.ext_zfinx) {
+        if (!cpu->cfg.ext_icsr) {
+            error_setg(errp, "Zfinx extension requires Zicsr");
+            return;
+        }
+        if (cpu->cfg.ext_f) {
+            error_setg(errp,
+                "Zfinx cannot be supported together with F extension");
+            return;
+        }
+    }
+
+    if (cpu->cfg.ext_zk) {
+        cpu->cfg.ext_zkn = true;
+        cpu->cfg.ext_zkr = true;
+        cpu->cfg.ext_zkt = true;
+    }
+
+    if (cpu->cfg.ext_zkn) {
+        cpu->cfg.ext_zbkb = true;
+        cpu->cfg.ext_zbkc = true;
+        cpu->cfg.ext_zbkx = true;
+        cpu->cfg.ext_zkne = true;
+        cpu->cfg.ext_zknd = true;
+        cpu->cfg.ext_zknh = true;
+    }
+
+    if (cpu->cfg.ext_zks) {
+        cpu->cfg.ext_zbkb = true;
+        cpu->cfg.ext_zbkc = true;
+        cpu->cfg.ext_zbkx = true;
+        cpu->cfg.ext_zksed = true;
+        cpu->cfg.ext_zksh = true;
+    }
+
+    if (cpu->cfg.ext_i) {
+        ext |= RVI;
+    }
+    if (cpu->cfg.ext_e) {
+        ext |= RVE;
+    }
+    if (cpu->cfg.ext_m) {
+        ext |= RVM;
+    }
+    if (cpu->cfg.ext_a) {
+        ext |= RVA;
+    }
+    if (cpu->cfg.ext_f) {
+        ext |= RVF;
+    }
+    if (cpu->cfg.ext_d) {
+        ext |= RVD;
+    }
+    if (cpu->cfg.ext_c) {
+        ext |= RVC;
+    }
+    if (cpu->cfg.ext_s) {
+        ext |= RVS;
+    }
+    if (cpu->cfg.ext_u) {
+        ext |= RVU;
+    }
+    if (cpu->cfg.ext_h) {
+        ext |= RVH;
+    }
+    if (cpu->cfg.ext_v) {
+        int vext_version = VEXT_VERSION_1_00_0;
+        ext |= RVV;
+        if (!is_power_of_2(cpu->cfg.vlen)) {
+            error_setg(errp,
+                    "Vector extension VLEN must be power of 2");
+            return;
+        }
+        if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+            error_setg(errp,
+                    "Vector extension implementation only supports VLEN "
+                    "in the range [128, %d]", RV_VLEN_MAX);
+            return;
+        }
+        if (!is_power_of_2(cpu->cfg.elen)) {
+            error_setg(errp,
+                    "Vector extension ELEN must be power of 2");
+            return;
+        }
+    if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
+        error_setg(errp,
+                "Vector extension implementation only supports ELEN "
+                "in the range [8, 64]");
+        return;
+    }
+    if (cpu->cfg.vext_spec) {
+        if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+            vext_version = VEXT_VERSION_1_00_0;
+        } else {
+            error_setg(errp,
+                   "Unsupported vector spec version '%s'",
+                   cpu->cfg.vext_spec);
+            return;
+        }
+    } else {
+        qemu_log("vector version is not specified, "
+                 "use the default value v1.0\n");
+    }
+    set_vext_version(env, vext_version);
+    }
+    if (cpu->cfg.ext_j) {
+        ext |= RVJ;
+    }
+
+    set_misa(env, env->misa_mxl, ext);
+}
+
 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     }
     assert(env->misa_mxl_max == env->misa_mxl);
 
-    /* If only MISA_EXT is unset for misa, then set it from properties */
-    if (env->misa_ext == 0) {
-        uint32_t ext = 0;
-
-        /* Do some ISA extension error checking */
-        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
-                                cpu->cfg.ext_a && cpu->cfg.ext_f &&
-                                cpu->cfg.ext_d &&
-                                cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
-            warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
-            cpu->cfg.ext_i = true;
-            cpu->cfg.ext_m = true;
-            cpu->cfg.ext_a = true;
-            cpu->cfg.ext_f = true;
-            cpu->cfg.ext_d = true;
-            cpu->cfg.ext_icsr = true;
-            cpu->cfg.ext_ifencei = true;
-        }
-
-        if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
-            error_setg(errp,
-                       "I and E extensions are incompatible");
-            return;
-        }
-
-        if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
-            error_setg(errp,
-                       "Either I or E extension must be set");
-            return;
-        }
-
-        if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
-            error_setg(errp,
-                       "Setting S extension without U extension is illegal");
-            return;
-        }
-
-        if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
-            error_setg(errp,
-                       "H depends on an I base integer ISA with 32 x registers");
-            return;
-        }
-
-        if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
-            error_setg(errp, "H extension implicitly requires S-mode");
-            return;
-        }
-
-        if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
-            error_setg(errp, "F extension requires Zicsr");
-            return;
-        }
-
-        if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
-            error_setg(errp, "Zawrs extension requires A extension");
-            return;
-        }
-
-        if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zfh/Zfhmin extensions require F extension");
-            return;
-        }
-
-        if (cpu->cfg.ext_d && !cpu->cfg.ext_f) {
-            error_setg(errp, "D extension requires F extension");
-            return;
-        }
-
-        if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
-            error_setg(errp, "V extension requires D extension");
-            return;
-        }
-
-        if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
-            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-            return;
-        }
-
-        /* Set the ISA extensions, checks should have happened above */
-        if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
-            cpu->cfg.ext_zhinxmin) {
-            cpu->cfg.ext_zfinx = true;
-        }
-
-        if (cpu->cfg.ext_zfinx) {
-            if (!cpu->cfg.ext_icsr) {
-                error_setg(errp, "Zfinx extension requires Zicsr");
-                return;
-            }
-            if (cpu->cfg.ext_f) {
-                error_setg(errp,
-                    "Zfinx cannot be supported together with F extension");
-                return;
-            }
-        }
-
-        if (cpu->cfg.ext_zk) {
-            cpu->cfg.ext_zkn = true;
-            cpu->cfg.ext_zkr = true;
-            cpu->cfg.ext_zkt = true;
-        }
-
-        if (cpu->cfg.ext_zkn) {
-            cpu->cfg.ext_zbkb = true;
-            cpu->cfg.ext_zbkc = true;
-            cpu->cfg.ext_zbkx = true;
-            cpu->cfg.ext_zkne = true;
-            cpu->cfg.ext_zknd = true;
-            cpu->cfg.ext_zknh = true;
-        }
-
-        if (cpu->cfg.ext_zks) {
-            cpu->cfg.ext_zbkb = true;
-            cpu->cfg.ext_zbkc = true;
-            cpu->cfg.ext_zbkx = true;
-            cpu->cfg.ext_zksed = true;
-            cpu->cfg.ext_zksh = true;
-        }
-
-        if (cpu->cfg.ext_i) {
-            ext |= RVI;
-        }
-        if (cpu->cfg.ext_e) {
-            ext |= RVE;
-        }
-        if (cpu->cfg.ext_m) {
-            ext |= RVM;
-        }
-        if (cpu->cfg.ext_a) {
-            ext |= RVA;
-        }
-        if (cpu->cfg.ext_f) {
-            ext |= RVF;
-        }
-        if (cpu->cfg.ext_d) {
-            ext |= RVD;
-        }
-        if (cpu->cfg.ext_c) {
-            ext |= RVC;
-        }
-        if (cpu->cfg.ext_s) {
-            ext |= RVS;
-        }
-        if (cpu->cfg.ext_u) {
-            ext |= RVU;
-        }
-        if (cpu->cfg.ext_h) {
-            ext |= RVH;
-        }
-        if (cpu->cfg.ext_v) {
-            int vext_version = VEXT_VERSION_1_00_0;
-            ext |= RVV;
-            if (!is_power_of_2(cpu->cfg.vlen)) {
-                error_setg(errp,
-                        "Vector extension VLEN must be power of 2");
-                return;
-            }
-            if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
-                error_setg(errp,
-                        "Vector extension implementation only supports VLEN "
-                        "in the range [128, %d]", RV_VLEN_MAX);
-                return;
-            }
-            if (!is_power_of_2(cpu->cfg.elen)) {
-                error_setg(errp,
-                        "Vector extension ELEN must be power of 2");
-                return;
-            }
-            if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
-                error_setg(errp,
-                        "Vector extension implementation only supports ELEN "
-                        "in the range [8, 64]");
-                return;
-            }
-            if (cpu->cfg.vext_spec) {
-                if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
-                    vext_version = VEXT_VERSION_1_00_0;
-                } else {
-                    error_setg(errp,
-                           "Unsupported vector spec version '%s'",
-                           cpu->cfg.vext_spec);
-                    return;
-                }
-            } else {
-                qemu_log("vector version is not specified, "
-                         "use the default value v1.0\n");
-            }
-            set_vext_version(env, vext_version);
-        }
-        if (cpu->cfg.ext_j) {
-            ext |= RVJ;
-        }
-
-        set_misa(env, env->misa_mxl, ext);
+    riscv_cpu_validate_set_extensions(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.39.0

From: Bin Meng <bmeng@tinylab.org>

env->mhartid is currently casted to long before printed, which drops
the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230109152655.340114-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             (env->priv_ver < isa_edata_arr[i].min_version)) {
             isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
 #ifndef CONFIG_USER_ONLY
-            warn_report("disabling %s extension for hart 0x%lx because "
-                        "privilege spec version does not match",
-                        isa_edata_arr[i].name, (unsigned long)env->mhartid);
+            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+                        " because privilege spec version does not match",
+                        isa_edata_arr[i].name, env->mhartid);
 #else
             warn_report("disabling %s extension because "
                         "privilege spec version does not match",
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

'mem_size' and 'cmdline' are unused.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry spike_memmap[] = {
 };
 
 static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
-                       uint64_t mem_size, const char *cmdline,
                        bool is_32_bit, bool htif_custom_base)
 {
     void *fdt;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     }
 
     /* Create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]), htif_custom_base);
+    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
 
     /* Load kernel */
     if (machine->kernel_filename) {
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

'mem_size' and 'cmdline' aren't being used. Remove them.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
 }
 
 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
+                       bool is_32_bit)
 {
     MachineState *mc = MACHINE(s);
     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     virt_flash_map(s, system_memory);
 
     /* create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc[0]));
+    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]));
 
     s->machine_done.notify = virt_machine_done;
     qemu_add_machine_init_done_notifier(&s->machine_done);
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

'cmdline' isn't being used. Remove it.

A MachineState pointer is being retrieved via a MACHINE() macro calling
qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev().

'mem_size' is being set as machine->ram_size by the caller. Retrieve it
via ms->ram_size.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_u_memmap[] = {
 #define GEM_REVISION        0x10070109
 
 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
-                       uint64_t mem_size, const char *cmdline, bool is_32_bit)
+                       bool is_32_bit)
 {
-    MachineState *ms = MACHINE(qdev_get_machine());
+    MachineState *ms = MACHINE(s);
+    uint64_t mem_size = ms->ram_size;
     void *fdt;
     int cpu, fdt_size;
     uint32_t *cells;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
                           qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
 
     /* create device tree */
-    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-               riscv_is_32bit(&s->soc.u_cpus));
+    create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
 
     if (s->start_in_flash) {
         /*
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

create_fdt_socket_cpus() writes a different 'mmu-type' value if we're
running in 32 or 64 bits. However, the flag is being calculated during
virt_machine_init(), and is passed around in create_fdt(), then
create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of
the intermediate functions are using the flag, which is a bit
misleading.

Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it
using the already available RISCVVirtState pointer. This will also
change the signature of create_fdt_socket() and create_fdt(), making it
clear that these functions don't do anything special when we're running
in 32 bit mode.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
 
 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
                                    char *clust_name, uint32_t *phandle,
-                                   bool is_32_bit, uint32_t *intc_phandles)
+                                   uint32_t *intc_phandles)
 {
     int cpu;
     uint32_t cpu_phandle;
     MachineState *mc = MACHINE(s);
     char *name, *cpu_name, *core_name, *intc_name;
+    bool is_32_bit = riscv_is_32bit(&s->soc[0]);
 
     for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
         cpu_phandle = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s)
 }
 
 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
-                               bool is_32_bit, uint32_t *phandle,
+                               uint32_t *phandle,
                                uint32_t *irq_mmio_phandle,
                                uint32_t *irq_pcie_phandle,
                                uint32_t *irq_virtio_phandle,
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         qemu_fdt_add_subnode(mc->fdt, clust_name);
 
         create_fdt_socket_cpus(s, socket, clust_name, phandle,
-            is_32_bit, &intc_phandles[phandle_pos]);
+                               &intc_phandles[phandle_pos]);
 
         create_fdt_socket_memory(s, memmap, socket);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap)
     g_free(nodename);
 }
 
-static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
-                       bool is_32_bit)
+static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
 {
     MachineState *mc = MACHINE(s);
     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
     qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
 
-    create_fdt_sockets(s, memmap, is_32_bit, &phandle,
-        &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
-        &msi_pcie_phandle);
+    create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle,
+                       &irq_pcie_phandle, &irq_virtio_phandle,
+                       &msi_pcie_phandle);
 
     create_fdt_virtio(s, memmap, irq_virtio_phandle);
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     virt_flash_map(s, system_memory);
 
     /* create device tree */
-    create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]));
+    create_fdt(s, memmap);
 
     s->machine_done.notify = virt_machine_done;
     qemu_add_machine_init_done_notifier(&s->machine_done);
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

There's no need to use a MachineState pointer and a fdt pointer now that
all RISC-V machines are using the FDT from the MachineState.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/numa.h |  6 +++---
 hw/riscv/numa.c         |  6 +++---
 hw/riscv/spike.c        |  6 +++---
 hw/riscv/virt.c         | 18 +++++++++---------
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/numa.h
+++ b/include/hw/riscv/numa.h
@@ -XXX,XX +XXX,XX @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
  * @ms: pointer to machine state
  * @socket_id: socket index
  *
- * Write NUMA node-id FDT property for given FDT node
+ * Write NUMA node-id FDT property in MachineState->fdt
  */
-void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
-                               const char *node_name, int socket_id);
+void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
+                               int socket_id);
 
 /**
  * riscv_socket_fdt_write_distance_matrix:
diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/numa.c
+++ b/hw/riscv/numa.c
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
             ms->numa_state->nodes[socket_id].node_mem : 0;
 }
 
-void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
-                               const char *node_name, int socket_id)
+void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name,
+                               int socket_id)
 {
     if (numa_enabled(ms)) {
-        qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
+        qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id);
     }
 }
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
                 s->soc[socket].hartid_base + cpu);
             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
-            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
+            riscv_socket_fdt_write_id(mc, cpu_name, socket);
             qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 
             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
         qemu_fdt_setprop_cells(fdt, mem_name, "reg",
             addr >> 32, addr, size >> 32, size);
         qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
-        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
+        riscv_socket_fdt_write_id(mc, mem_name, socket);
         g_free(mem_name);
 
         clint_addr = memmap[SPIKE_CLINT].base +
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
+        riscv_socket_fdt_write_id(mc, clint_name, socket);
 
         g_free(clint_name);
         g_free(clint_cells);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
         qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
             s->soc[socket].hartid_base + cpu);
         qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
-        riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
+        riscv_socket_fdt_write_id(mc, cpu_name, socket);
         qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
 
         intc_phandles[cpu] = (*phandle)++;
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_memory(RISCVVirtState *s,
     qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
         addr >> 32, addr, size >> 32, size);
     qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
-    riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
+    riscv_socket_fdt_write_id(mc, mem_name, socket);
     g_free(mem_name);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_clint(RISCVVirtState *s,
         0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
     qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
         clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-    riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
+    riscv_socket_fdt_write_id(mc, clint_name, socket);
     g_free(clint_name);
 
     g_free(clint_cells);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
             aclint_mswi_cells, aclint_cells_size);
         qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
         qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+        riscv_socket_fdt_write_id(mc, name, socket);
         g_free(name);
     }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
         0x0, RISCV_ACLINT_DEFAULT_MTIME);
     qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
         aclint_mtimer_cells, aclint_cells_size);
-    riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+    riscv_socket_fdt_write_id(mc, name, socket);
     g_free(name);
 
     if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
             aclint_sswi_cells, aclint_cells_size);
         qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
         qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
-        riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
+        riscv_socket_fdt_write_id(mc, name, socket);
         g_free(name);
     }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
         0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
                           VIRT_IRQCHIP_NUM_SOURCES - 1);
-    riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
+    riscv_socket_fdt_write_id(mc, plic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
         plic_phandles[socket]);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
         aplic_s_phandle);
     qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
         aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
-    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+    riscv_socket_fdt_write_id(mc, aplic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
     g_free(aplic_name);
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
         0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
         VIRT_IRQCHIP_NUM_SOURCES);
-    riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
+    riscv_socket_fdt_write_id(mc, aplic_name, socket);
     qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
 
     if (!socket) {
-- 
2.39.0

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

There's no need to use a MachineState pointer and a fdt pointer now that
all RISC-V machines are using the FDT from the MachineState.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/numa.h | 4 ++--
 hw/riscv/numa.c         | 8 ++++----
 hw/riscv/spike.c        | 2 +-
 hw/riscv/virt.c         | 2 +-
 4 files changed, 8 insertions(+), 8 deletions(-)

From: Andrew Bresticker <abrestic@rivosinc.com>

The current logic attempts to shift the VS-level bits into their correct
position in mip while leaving the remaining bits in-tact. This is both
pointless and likely incorrect since one would expect that any new, future
VS-level interrupts will get their own position in mip rather than sharing
with their (H)S-level equivalent. Fix this, and make the logic more
readable, by just making off the VS-level bits and shifting them into
position.

This also fixes reads of vsip, which would only ever report vsip.VSSIP
since the non-writable bits got masked off as well.

Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 35 +++++++++++------------------------
 1 file changed, 11 insertions(+), 24 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno,
                                  uint64_t new_val, uint64_t wr_mask)
 {
     RISCVException ret;
-    uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS;
+    uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
 
     /* Bring VS-level bits to correct position */
-    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
-    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
-    new_val |= vsbits << 1;
-    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
-    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
-    wr_mask |= vsbits << 1;
+    new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+    wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
 
     ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask);
     if (ret_val) {
-        rval &= mask;
-        vsbits = rval & VS_MODE_INTERRUPTS;
-        rval &= ~VS_MODE_INTERRUPTS;
-        *ret_val = rval | (vsbits >> 1);
+        *ret_val = (rval & mask) >> 1;
     }
 
     return ret;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno,
                                  uint64_t new_val, uint64_t wr_mask)
 {
     RISCVException ret;
-    uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask;
+    uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS;
 
     /* Bring VS-level bits to correct position */
-    vsbits = new_val & (VS_MODE_INTERRUPTS >> 1);
-    new_val &= ~(VS_MODE_INTERRUPTS >> 1);
-    new_val |= vsbits << 1;
-    vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1);
-    wr_mask &= ~(VS_MODE_INTERRUPTS >> 1);
-    wr_mask |= vsbits << 1;
-
-    ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask);
+    new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1;
+    wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1;
+
+    ret = rmw_mip64(env, csrno, &rval, new_val,
+                    wr_mask & mask & vsip_writable_mask);
     if (ret_val) {
-        rval &= mask;
-        vsbits = rval & VS_MODE_INTERRUPTS;
-        rval &= ~VS_MODE_INTERRUPTS;
-        *ret_val = rval | (vsbits >> 1);
+        *ret_val = (rval & mask) >> 1;
     }
 
     return ret;
-- 
2.39.0

From: Andrew Bresticker <abrestic@rivosinc.com>

Per the AIA specification, writes to stimecmp from VS level should
trap when hvictl.VTI is set since the write may cause vsip.STIP to
become unset.

Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support")
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221215224541.1423431-2-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
     RISCVCPU *cpu = env_archcpu(env);
 
     if (riscv_cpu_virt_enabled(env)) {
+        if (env->hvictl & HVICTL_VTI) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         return write_vstimecmp(env, csrno, val);
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
     RISCVCPU *cpu = env_archcpu(env);
 
     if (riscv_cpu_virt_enabled(env)) {
+        if (env->hvictl & HVICTL_VTI) {
+            return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+        }
         return write_vstimecmph(env, csrno, val);
     }
 
-- 
2.39.0

From: Richard Henderson <richard.henderson@linaro.org>

We failed to update this with the w^x split, so misses the fact
that true pc-relative offsets are usually small.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tcg/riscv/tcg-target.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
     intptr_t imm12 = sextreg(offset, 0, 12);
 
     if (offset != imm12) {
-        intptr_t diff = offset - (uintptr_t)s->code_ptr;
+        intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
 
         if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
             imm12 = sextreg(diff, 0, 12);
-- 
2.39.0

From: Richard Henderson <richard.henderson@linaro.org>

The new helper always validates the contents of FRM, even
if the new rounding mode is not DYN.  This is required by
the vector unit.

Track whether we've validated FRM separately from whether
we've updated fp_status with a given rounding mode, so that
we can elide calls correctly.

This partially reverts d6c4d3f2a69 which attempted the to do
the same thing, but with two calls to gen_set_rm(), which is
both inefficient and tickles an assertion in decode_save_opc.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  1 +
 target/riscv/fpu_helper.c               | 37 +++++++++++++++++++++++++
 target/riscv/translate.c                | 19 +++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc | 24 +++-------------
 4 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
 
 /* Floating Point - rounding mode */
 DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
 DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
 
 /* Floating Point - fused */
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
     set_float_rounding_mode(softrm, &env->fp_status);
 }
 
+void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
+{
+    int softrm;
+
+    /* Always validate frm, even if rm != DYN. */
+    if (unlikely(env->frm >= 5)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+    if (rm == RISCV_FRM_DYN) {
+        rm = env->frm;
+    }
+    switch (rm) {
+    case RISCV_FRM_RNE:
+        softrm = float_round_nearest_even;
+        break;
+    case RISCV_FRM_RTZ:
+        softrm = float_round_to_zero;
+        break;
+    case RISCV_FRM_RDN:
+        softrm = float_round_down;
+        break;
+    case RISCV_FRM_RUP:
+        softrm = float_round_up;
+        break;
+    case RISCV_FRM_RMM:
+        softrm = float_round_ties_away;
+        break;
+    case RISCV_FRM_ROD:
+        softrm = float_round_to_odd;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    set_float_rounding_mode(softrm, &env->fp_status);
+}
+
 void helper_set_rod_rounding_mode(CPURISCVState *env)
 {
     set_float_rounding_mode(float_round_to_odd, &env->fp_status);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool pm_base_enabled;
     /* Use icount trigger for native debug */
     bool itrigger;
+    /* FRM is known to contain a valid value. */
+    bool frm_valid;
     /* TCG of the current insn_start */
     TCGOp *insn_start;
 } DisasContext;
@@ -XXX,XX +XXX,XX @@ static void gen_set_rm(DisasContext *ctx, int rm)
         gen_helper_set_rod_rounding_mode(cpu_env);
         return;
     }
+    if (rm == RISCV_FRM_DYN) {
+        /* The helper will return only if frm valid. */
+        ctx->frm_valid = true;
+    }
 
     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
     decode_save_opc(ctx);
     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 }
 
+static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
+{
+    if (ctx->frm == rm && ctx->frm_valid) {
+        return;
+    }
+    ctx->frm = rm;
+    ctx->frm_valid = true;
+
+    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
+    decode_save_opc(ctx);
+    gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
+}
+
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
                     int rm)
 {
     if (checkfn(s, a)) {
-        if (rm != RISCV_FRM_DYN) {
-            gen_set_rm(s, RISCV_FRM_DYN);
-        }
-
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
-        gen_set_rm(s, rm);
+        gen_set_rm_chkfrm(s, rm);
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (CHECK(s, a)) {                                             \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[2] = {            \
             gen_helper_##HELPER##_h,                               \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (CHECK(s, a)) {                                             \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[2] = {            \
             gen_helper_##HELPER##_h,                               \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
@@ -XXX,XX +XXX,XX @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (opxfv_narrow_check(s, a)) {                                \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[3] = {            \
             gen_helper_##HELPER##_b,                               \
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
-- 
2.39.0

From: Richard Henderson <richard.henderson@linaro.org>

The only setting of RISCV_FRM_ROD is from the vector unit,
and now handled by helper_set_rounding_mode_chkfrm.
This helper is now unused.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h     | 1 -
 target/riscv/fpu_helper.c | 5 -----
 target/riscv/translate.c  | 4 ----
 3 files changed, 10 deletions(-)

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier")
moved the initialization of fw_cfg to the virt_machine_done() callback.

Problem is that the validation of fw_cfg by devices such as ramfb is
done before the machine done notifier is called. Moving create_fw_cfg()
to machine_done() results in QEMU failing to boot when using a ramfb
device:

./qemu-system-riscv64 -machine virt -device ramfb -serial stdio
qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA

The fix is simple: move create_fw_cfg() config back to
virt_machine_init(). This happens to be the same way the ARM 'virt'
machine deals with fw_cfg (see machvirt_init() and virt_machine_done()
in hw/arm/virt.c), so we're keeping consistency with how other machines
handle this device.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
                                                      start_addr, NULL);
 
-    /*
-     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
-     * tree cannot be altered and we get FDT_ERR_NOSPACE.
-     */
-    s->fw_cfg = create_fw_cfg(machine);
-    rom_set_fw(s->fw_cfg);
-
     if (drive_get(IF_PFLASH, 0, 1)) {
         /*
          * S-mode FW like EDK2 will be kept in second plash (unit 1).
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                 mask_rom);
 
+    /*
+     * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the
+     * device tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(machine);
+    rom_set_fw(s->fw_cfg);
+
     /* SiFive Test MMIO device */
     sifive_test_create(memmap[VIRT_TEST].base);
 
-- 
2.39.0

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1