1 | The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd: | 1 | The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2: |
---|---|---|---|
2 | 2 | ||
3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-01-12 13:51:36 +0000) | 3 | Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230113 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203 |
8 | 8 | ||
9 | for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31: | 9 | for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6: |
10 | 10 | ||
11 | target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled (2023-01-13 13:19:36 +0000) | 11 | target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | target-arm queue: | 14 | target-arm queue: |
15 | hw/arm/stm32f405: correctly describe the memory layout | 15 | * Fix physical address resolution for Stage2 |
16 | hw/arm: Add Olimex H405 board | 16 | * pl011: refactoring, implement reset method |
17 | cubieboard: Support booting from an SD card image with u-boot on it | 17 | * Support GICv3 with hvf acceleration |
18 | target/arm: Fix sve_probe_page | 18 | * sbsa-ref: remove cortex-a76 from list of supported cpus |
19 | target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled | 19 | * Correct syndrome for ATS12NSO* traps at Secure EL1 |
20 | various code cleanups | 20 | * Fix priority of HSTR_EL2 traps vs UNDEFs |
21 | * Implement FEAT_FGT for '-cpu max' | ||
21 | 22 | ||
22 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
23 | Evgeny Iakovlev (1): | 24 | Alexander Graf (3): |
24 | target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled | 25 | hvf: arm: Add support for GICv3 |
26 | hw/arm/virt: Consolidate GIC finalize logic | ||
27 | hw/arm/virt: Make accels in GIC finalize logic explicit | ||
25 | 28 | ||
26 | Felipe Balbi (2): | 29 | Evgeny Iakovlev (4): |
27 | hw/arm/stm32f405: correctly describe the memory layout | 30 | hw/char/pl011: refactor FIFO depth handling code |
28 | hw/arm: Add Olimex H405 | 31 | hw/char/pl011: add post_load hook for backwards-compatibility |
32 | hw/char/pl011: implement a reset method | ||
33 | hw/char/pl011: better handling of FIFO flags on LCR reset | ||
29 | 34 | ||
30 | Philippe Mathieu-Daudé (27): | 35 | Marcin Juszkiewicz (1): |
31 | hw/arm/pxa2xx: Simplify pxa255_init() | 36 | sbsa-ref: remove cortex-a76 from list of supported cpus |
32 | hw/arm/pxa2xx: Simplify pxa270_init() | ||
33 | hw/arm/collie: Use the IEC binary prefix definitions | ||
34 | hw/arm/collie: Simplify flash creation using for() loop | ||
35 | hw/arm/gumstix: Improve documentation | ||
36 | hw/arm/gumstix: Use the IEC binary prefix definitions | ||
37 | hw/arm/mainstone: Use the IEC binary prefix definitions | ||
38 | hw/arm/musicpal: Use the IEC binary prefix definitions | ||
39 | hw/arm/omap_sx1: Remove unused 'total_ram' definitions | ||
40 | hw/arm/omap_sx1: Use the IEC binary prefix definitions | ||
41 | hw/arm/z2: Use the IEC binary prefix definitions | ||
42 | hw/arm/vexpress: Remove dead code in vexpress_common_init() | ||
43 | hw/arm: Remove unreachable code calling pflash_cfi01_register() | ||
44 | hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState | ||
45 | hw/gpio/omap_gpio: Add local variable to avoid embedded cast | ||
46 | hw/arm/omap: Drop useless casts from void * to pointer | ||
47 | hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name | ||
48 | hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name | ||
49 | hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name | ||
50 | hw/arm/stellaris: Drop useless casts from void * to pointer | ||
51 | hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name | ||
52 | hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE() | ||
53 | hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() | ||
54 | hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC | ||
55 | hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() | ||
56 | hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' | ||
57 | hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock' | ||
58 | 37 | ||
59 | Richard Henderson (1): | 38 | Peter Maydell (23): |
60 | target/arm: Fix sve_probe_page | 39 | target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly |
40 | target/arm: Correct syndrome for ATS12NSO* at Secure EL1 | ||
41 | target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} | ||
42 | target/arm: Move do_coproc_insn() syndrome calculation earlier | ||
43 | target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps | ||
44 | target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1 | ||
45 | target/arm: Disable HSTR_EL2 traps if EL2 is not enabled | ||
46 | target/arm: Define the FEAT_FGT registers | ||
47 | target/arm: Implement FGT trapping infrastructure | ||
48 | target/arm: Mark up sysregs for HFGRTR bits 0..11 | ||
49 | target/arm: Mark up sysregs for HFGRTR bits 12..23 | ||
50 | target/arm: Mark up sysregs for HFGRTR bits 24..35 | ||
51 | target/arm: Mark up sysregs for HFGRTR bits 36..63 | ||
52 | target/arm: Mark up sysregs for HDFGRTR bits 0..11 | ||
53 | target/arm: Mark up sysregs for HDFGRTR bits 12..63 | ||
54 | target/arm: Mark up sysregs for HFGITR bits 0..11 | ||
55 | target/arm: Mark up sysregs for HFGITR bits 12..17 | ||
56 | target/arm: Mark up sysregs for HFGITR bits 18..47 | ||
57 | target/arm: Mark up sysregs for HFGITR bits 48..63 | ||
58 | target/arm: Implement the HFGITR_EL2.ERET trap | ||
59 | target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps | ||
60 | target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps | ||
61 | target/arm: Enable FEAT_FGT on '-cpu max' | ||
61 | 62 | ||
62 | Strahinja Jankovic (7): | 63 | Richard Henderson (2): |
63 | hw/misc: Allwinner-A10 Clock Controller Module Emulation | 64 | hw/arm: Use TYPE_ARM_SMMUV3 |
64 | hw/misc: Allwinner A10 DRAM Controller Emulation | 65 | target/arm: Fix physical address resolution for Stage2 |
65 | {hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation | ||
66 | hw/misc: AXP209 PMU Emulation | ||
67 | hw/arm: Add AXP209 to Cubieboard | ||
68 | hw/arm: Allwinner A10 enable SPL load from MMC | ||
69 | tests/avocado: Add SD boot test to Cubieboard | ||
70 | 66 | ||
71 | docs/system/arm/cubieboard.rst | 1 + | 67 | docs/system/arm/emulation.rst | 1 + |
72 | docs/system/arm/orangepi.rst | 1 + | 68 | include/hw/arm/virt.h | 15 +- |
73 | docs/system/arm/stm32.rst | 1 + | 69 | include/hw/char/pl011.h | 5 +- |
74 | configs/devices/arm-softmmu/default.mak | 1 + | 70 | target/arm/cpregs.h | 484 +++++++++++++++++++++++++++++++++++++++++- |
75 | include/hw/adc/npcm7xx_adc.h | 7 +- | 71 | target/arm/cpu.h | 18 ++ |
76 | include/hw/arm/allwinner-a10.h | 27 ++ | 72 | target/arm/internals.h | 20 ++ |
77 | include/hw/arm/allwinner-h3.h | 3 + | 73 | target/arm/syndrome.h | 10 + |
78 | include/hw/arm/npcm7xx.h | 18 +- | 74 | target/arm/translate.h | 6 + |
79 | include/hw/arm/omap.h | 24 +- | 75 | hw/arm/sbsa-ref.c | 4 +- |
80 | include/hw/arm/pxa.h | 11 +- | 76 | hw/arm/virt.c | 203 +++++++++--------- |
81 | include/hw/arm/stm32f405_soc.h | 5 +- | 77 | hw/char/pl011.c | 93 ++++++-- |
82 | include/hw/i2c/allwinner-i2c.h | 55 ++++ | 78 | hw/intc/arm_gicv3_cpuif.c | 18 +- |
83 | include/hw/i2c/npcm7xx_smbus.h | 7 +- | 79 | target/arm/cpu64.c | 1 + |
84 | include/hw/misc/allwinner-a10-ccm.h | 67 +++++ | 80 | target/arm/debug_helper.c | 46 +++- |
85 | include/hw/misc/allwinner-a10-dramc.h | 68 +++++ | 81 | target/arm/helper.c | 245 ++++++++++++++++++++- |
86 | include/hw/misc/npcm7xx_clk.h | 2 +- | 82 | target/arm/hvf/hvf.c | 151 +++++++++++++ |
87 | include/hw/misc/npcm7xx_gcr.h | 6 +- | 83 | target/arm/op_helper.c | 58 ++++- |
88 | include/hw/misc/npcm7xx_mft.h | 7 +- | 84 | target/arm/ptw.c | 2 +- |
89 | include/hw/misc/npcm7xx_pwm.h | 3 +- | 85 | target/arm/translate-a64.c | 22 +- |
90 | include/hw/misc/npcm7xx_rng.h | 6 +- | 86 | target/arm/translate.c | 125 +++++++---- |
91 | include/hw/net/npcm7xx_emc.h | 5 +- | 87 | target/arm/hvf/trace-events | 2 + |
92 | include/hw/sd/npcm7xx_sdhci.h | 4 +- | 88 | 21 files changed, 1340 insertions(+), 189 deletions(-) |
93 | hw/arm/allwinner-a10.c | 40 +++ | ||
94 | hw/arm/allwinner-h3.c | 11 +- | ||
95 | hw/arm/bcm2836.c | 9 +- | ||
96 | hw/arm/collie.c | 25 +- | ||
97 | hw/arm/cubieboard.c | 11 + | ||
98 | hw/arm/gumstix.c | 45 ++-- | ||
99 | hw/arm/mainstone.c | 37 ++- | ||
100 | hw/arm/musicpal.c | 9 +- | ||
101 | hw/arm/olimex-stm32-h405.c | 69 +++++ | ||
102 | hw/arm/omap1.c | 115 ++++---- | ||
103 | hw/arm/omap2.c | 40 ++- | ||
104 | hw/arm/omap_sx1.c | 53 ++-- | ||
105 | hw/arm/palm.c | 2 +- | ||
106 | hw/arm/pxa2xx.c | 8 +- | ||
107 | hw/arm/spitz.c | 6 +- | ||
108 | hw/arm/stellaris.c | 73 +++-- | ||
109 | hw/arm/stm32f405_soc.c | 8 + | ||
110 | hw/arm/tosa.c | 2 +- | ||
111 | hw/arm/versatilepb.c | 6 +- | ||
112 | hw/arm/vexpress.c | 10 +- | ||
113 | hw/arm/z2.c | 16 +- | ||
114 | hw/char/omap_uart.c | 7 +- | ||
115 | hw/display/omap_dss.c | 15 +- | ||
116 | hw/display/omap_lcdc.c | 9 +- | ||
117 | hw/dma/omap_dma.c | 15 +- | ||
118 | hw/gpio/omap_gpio.c | 48 ++-- | ||
119 | hw/i2c/allwinner-i2c.c | 459 ++++++++++++++++++++++++++++++++ | ||
120 | hw/intc/omap_intc.c | 38 +-- | ||
121 | hw/intc/xilinx_intc.c | 28 +- | ||
122 | hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++ | ||
123 | hw/misc/allwinner-a10-dramc.c | 179 +++++++++++++ | ||
124 | hw/misc/axp209.c | 238 +++++++++++++++++ | ||
125 | hw/misc/omap_gpmc.c | 12 +- | ||
126 | hw/misc/omap_l4.c | 7 +- | ||
127 | hw/misc/omap_sdrc.c | 7 +- | ||
128 | hw/misc/omap_tap.c | 5 +- | ||
129 | hw/misc/sbsa_ec.c | 12 +- | ||
130 | hw/sd/omap_mmc.c | 9 +- | ||
131 | hw/ssi/omap_spi.c | 7 +- | ||
132 | hw/timer/omap_gptimer.c | 22 +- | ||
133 | hw/timer/omap_synctimer.c | 4 +- | ||
134 | hw/timer/xilinx_timer.c | 27 +- | ||
135 | target/arm/helper.c | 3 + | ||
136 | target/arm/sve_helper.c | 14 +- | ||
137 | MAINTAINERS | 8 + | ||
138 | hw/arm/Kconfig | 9 + | ||
139 | hw/arm/meson.build | 1 + | ||
140 | hw/i2c/Kconfig | 4 + | ||
141 | hw/i2c/meson.build | 1 + | ||
142 | hw/i2c/trace-events | 5 + | ||
143 | hw/misc/Kconfig | 10 + | ||
144 | hw/misc/meson.build | 3 + | ||
145 | hw/misc/trace-events | 5 + | ||
146 | tests/avocado/boot_linux_console.py | 47 ++++ | ||
147 | 76 files changed, 1951 insertions(+), 455 deletions(-) | ||
148 | create mode 100644 include/hw/i2c/allwinner-i2c.h | ||
149 | create mode 100644 include/hw/misc/allwinner-a10-ccm.h | ||
150 | create mode 100644 include/hw/misc/allwinner-a10-dramc.h | ||
151 | create mode 100644 hw/arm/olimex-stm32-h405.c | ||
152 | create mode 100644 hw/i2c/allwinner-i2c.c | ||
153 | create mode 100644 hw/misc/allwinner-a10-ccm.c | ||
154 | create mode 100644 hw/misc/allwinner-a10-dramc.c | ||
155 | create mode 100644 hw/misc/axp209.c | ||
156 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Felipe Balbi <balbi@kernel.org> | ||
2 | 1 | ||
3 | STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled | ||
4 | Memory) at a different base address. Correctly describe the memory | ||
5 | layout to give existing FW images a chance to run unmodified. | ||
6 | |||
7 | Reviewed-by: Alistair Francis <alistair@alistair23.me> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Felipe Balbi <balbi@kernel.org> | ||
10 | Message-id: 20221230145733.200496-2-balbi@kernel.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/arm/stm32f405_soc.h | 5 ++++- | ||
14 | hw/arm/stm32f405_soc.c | 8 ++++++++ | ||
15 | 2 files changed, 12 insertions(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/stm32f405_soc.h | ||
20 | +++ b/include/hw/arm/stm32f405_soc.h | ||
21 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC) | ||
22 | #define FLASH_BASE_ADDRESS 0x08000000 | ||
23 | #define FLASH_SIZE (1024 * 1024) | ||
24 | #define SRAM_BASE_ADDRESS 0x20000000 | ||
25 | -#define SRAM_SIZE (192 * 1024) | ||
26 | +#define SRAM_SIZE (128 * 1024) | ||
27 | +#define CCM_BASE_ADDRESS 0x10000000 | ||
28 | +#define CCM_SIZE (64 * 1024) | ||
29 | |||
30 | struct STM32F405State { | ||
31 | /*< private >*/ | ||
32 | @@ -XXX,XX +XXX,XX @@ struct STM32F405State { | ||
33 | STM32F2XXADCState adc[STM_NUM_ADCS]; | ||
34 | STM32F2XXSPIState spi[STM_NUM_SPIS]; | ||
35 | |||
36 | + MemoryRegion ccm; | ||
37 | MemoryRegion sram; | ||
38 | MemoryRegion flash; | ||
39 | MemoryRegion flash_alias; | ||
40 | diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/stm32f405_soc.c | ||
43 | +++ b/hw/arm/stm32f405_soc.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) | ||
45 | } | ||
46 | memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); | ||
47 | |||
48 | + memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE, | ||
49 | + &err); | ||
50 | + if (err != NULL) { | ||
51 | + error_propagate(errp, err); | ||
52 | + return; | ||
53 | + } | ||
54 | + memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm); | ||
55 | + | ||
56 | armv7m = DEVICE(&s->armv7m); | ||
57 | qdev_prop_set_uint32(armv7m, "num-irq", 96); | ||
58 | qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); | ||
59 | -- | ||
60 | 2.34.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Upon introduction in commit b8433303fb ("Set proper device-width | 3 | Use the macro instead of two explicit string literals. |
4 | for vexpress flash"), ve_pflash_cfi01_register() was calling | ||
5 | qdev_init_nofail() which can not fail. This call was later | ||
6 | converted with a script to use &error_fatal, still unable to | ||
7 | fail. Remove the unreachable code. | ||
8 | 4 | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Message-id: 20230109115316.2235-13-philmd@linaro.org | 7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
8 | Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | hw/arm/vexpress.c | 10 +--------- | 11 | hw/arm/sbsa-ref.c | 3 ++- |
15 | 1 file changed, 1 insertion(+), 9 deletions(-) | 12 | hw/arm/virt.c | 2 +- |
13 | 2 files changed, 3 insertions(+), 2 deletions(-) | ||
16 | 14 | ||
17 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | 15 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/vexpress.c | 17 | --- a/hw/arm/sbsa-ref.c |
20 | +++ b/hw/arm/vexpress.c | 18 | +++ b/hw/arm/sbsa-ref.c |
21 | @@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine) | 19 | @@ -XXX,XX +XXX,XX @@ |
22 | dinfo = drive_get(IF_PFLASH, 0, 0); | 20 | #include "exec/hwaddr.h" |
23 | pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", | 21 | #include "kvm_arm.h" |
24 | dinfo); | 22 | #include "hw/arm/boot.h" |
25 | - if (!pflash0) { | 23 | +#include "hw/arm/smmuv3.h" |
26 | - error_report("vexpress: error registering flash 0"); | 24 | #include "hw/block/flash.h" |
27 | - exit(1); | 25 | #include "hw/boards.h" |
28 | - } | 26 | #include "hw/ide/internal.h" |
29 | 27 | @@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) | |
30 | if (map[VE_NORFLASHALIAS] != -1) { | 28 | DeviceState *dev; |
31 | /* Map flash 0 as an alias into low memory */ | 29 | int i; |
32 | @@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine) | 30 | |
31 | - dev = qdev_new("arm-smmuv3"); | ||
32 | + dev = qdev_new(TYPE_ARM_SMMUV3); | ||
33 | |||
34 | object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), | ||
35 | &error_abort); | ||
36 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/arm/virt.c | ||
39 | +++ b/hw/arm/virt.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms, | ||
41 | return; | ||
33 | } | 42 | } |
34 | 43 | ||
35 | dinfo = drive_get(IF_PFLASH, 0, 1); | 44 | - dev = qdev_new("arm-smmuv3"); |
36 | - if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", | 45 | + dev = qdev_new(TYPE_ARM_SMMUV3); |
37 | - dinfo)) { | 46 | |
38 | - error_report("vexpress: error registering flash 1"); | 47 | object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), |
39 | - exit(1); | 48 | &error_abort); |
40 | - } | ||
41 | + ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo); | ||
42 | |||
43 | sram_size = 0x2000000; | ||
44 | memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, | ||
45 | -- | 49 | -- |
46 | 2.34.1 | 50 | 2.34.1 |
47 | 51 | ||
48 | 52 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Don't dereference CPUTLBEntryFull until we verify that | 3 | Conversion to probe_access_full missed applying the page offset. |
4 | the page is valid. Move the other user-only info field | ||
5 | updates after the valid check to match. | ||
6 | 4 | ||
7 | Cc: qemu-stable@nongnu.org | 5 | Cc: qemu-stable@nongnu.org |
8 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412 | 6 | Reported-by: Sid Manning <sidneym@quicinc.com> |
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Message-id: 20230104190056.305143-1-richard.henderson@linaro.org | 9 | Message-id: 20230126233134.103193-1-richard.henderson@linaro.org |
10 | Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking") | ||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 13 | --- |
14 | target/arm/sve_helper.c | 14 +++++++++----- | 14 | target/arm/ptw.c | 2 +- |
15 | 1 file changed, 9 insertions(+), 5 deletions(-) | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
16 | 16 | ||
17 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 17 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/sve_helper.c | 19 | --- a/target/arm/ptw.c |
20 | +++ b/target/arm/sve_helper.c | 20 | +++ b/target/arm/ptw.c |
21 | @@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, | 21 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
22 | #ifdef CONFIG_USER_ONLY | 22 | if (unlikely(flags & TLB_INVALID_MASK)) { |
23 | flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault, | 23 | goto fail; |
24 | &info->host, retaddr); | 24 | } |
25 | - memset(&info->attrs, 0, sizeof(info->attrs)); | 25 | - ptw->out_phys = full->phys_addr; |
26 | - /* Require both ANON and MTE; see allocation_tag_mem(). */ | 26 | + ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); |
27 | - info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE); | 27 | ptw->out_rw = full->prot & PAGE_WRITE; |
28 | #else | 28 | pte_attrs = full->pte_attrs; |
29 | CPUTLBEntryFull *full; | 29 | pte_secure = full->attrs.secure; |
30 | flags = probe_access_full(env, addr, access_type, mmu_idx, nofault, | ||
31 | &info->host, &full, retaddr); | ||
32 | - info->attrs = full->attrs; | ||
33 | - info->tagged = full->pte_attrs == 0xf0; | ||
34 | #endif | ||
35 | info->flags = flags; | ||
36 | |||
37 | @@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, | ||
38 | return false; | ||
39 | } | ||
40 | |||
41 | +#ifdef CONFIG_USER_ONLY | ||
42 | + memset(&info->attrs, 0, sizeof(info->attrs)); | ||
43 | + /* Require both ANON and MTE; see allocation_tag_mem(). */ | ||
44 | + info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE); | ||
45 | +#else | ||
46 | + info->attrs = full->attrs; | ||
47 | + info->tagged = full->pte_attrs == 0xf0; | ||
48 | +#endif | ||
49 | + | ||
50 | /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ | ||
51 | info->host -= mem_off; | ||
52 | return true; | ||
53 | -- | 30 | -- |
54 | 2.34.1 | 31 | 2.34.1 |
55 | 32 | ||
56 | 33 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
---|---|---|---|
2 | 2 | ||
3 | Following docs/devel/style.rst guidelines, rename | 3 | PL011 can be in either of 2 modes depending guest config: FIFO and |
4 | stellaris_adc_state -> StellarisADCState. This also remove a | 4 | single register. The last mode could be viewed as a 1-element-deep FIFO. |
5 | use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call. | ||
6 | 5 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 6 | Current code open-codes a bunch of depth-dependent logic. Refactor FIFO |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | depth handling code to isolate calculating current FIFO depth. |
9 | Message-id: 20230109140306.23161-9-philmd@linaro.org | 8 | |
9 | One functional (albeit guest-invisible) side-effect of this change is | ||
10 | that previously we would always increment s->read_pos in UARTDR read | ||
11 | handler even if FIFO was disabled, now we are limiting read_pos to not | ||
12 | exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO). | ||
13 | |||
14 | Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
17 | Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 19 | --- |
12 | hw/arm/stellaris.c | 73 +++++++++++++++++++++++----------------------- | 20 | include/hw/char/pl011.h | 5 ++++- |
13 | 1 file changed, 36 insertions(+), 37 deletions(-) | 21 | hw/char/pl011.c | 30 ++++++++++++++++++------------ |
22 | 2 files changed, 22 insertions(+), 13 deletions(-) | ||
14 | 23 | ||
15 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 24 | diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h |
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/stellaris.c | 26 | --- a/include/hw/char/pl011.h |
18 | +++ b/hw/arm/stellaris.c | 27 | +++ b/include/hw/char/pl011.h |
19 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj) | 28 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011) |
20 | #define STELLARIS_ADC_FIFO_FULL 0x1000 | 29 | /* This shares the same struct (and cast macro) as the base pl011 device */ |
21 | 30 | #define TYPE_PL011_LUMINARY "pl011_luminary" | |
22 | #define TYPE_STELLARIS_ADC "stellaris-adc" | 31 | |
23 | -typedef struct StellarisADCState stellaris_adc_state; | 32 | +/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */ |
24 | -DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC, | 33 | +#define PL011_FIFO_DEPTH 16 |
25 | - TYPE_STELLARIS_ADC) | 34 | + |
26 | +typedef struct StellarisADCState StellarisADCState; | 35 | struct PL011State { |
27 | +DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC) | ||
28 | |||
29 | struct StellarisADCState { | ||
30 | SysBusDevice parent_obj; | 36 | SysBusDevice parent_obj; |
31 | @@ -XXX,XX +XXX,XX @@ struct StellarisADCState { | 37 | |
32 | qemu_irq irq[4]; | 38 | @@ -XXX,XX +XXX,XX @@ struct PL011State { |
33 | }; | 39 | uint32_t dmacr; |
34 | 40 | uint32_t int_enabled; | |
35 | -static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) | 41 | uint32_t int_level; |
36 | +static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n) | 42 | - uint32_t read_fifo[16]; |
37 | { | 43 | + uint32_t read_fifo[PL011_FIFO_DEPTH]; |
38 | int tail; | 44 | uint32_t ilpr; |
39 | 45 | uint32_t ibrd; | |
40 | @@ -XXX,XX +XXX,XX @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n) | 46 | uint32_t fbrd; |
41 | return s->fifo[n].data[tail]; | 47 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c |
42 | } | 48 | index XXXXXXX..XXXXXXX 100644 |
43 | 49 | --- a/hw/char/pl011.c | |
44 | -static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, | 50 | +++ b/hw/char/pl011.c |
45 | +static void stellaris_adc_fifo_write(StellarisADCState *s, int n, | 51 | @@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s) |
46 | uint32_t value) | ||
47 | { | ||
48 | int head; | ||
49 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n, | ||
50 | s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL; | ||
51 | } | ||
52 | |||
53 | -static void stellaris_adc_update(stellaris_adc_state *s) | ||
54 | +static void stellaris_adc_update(StellarisADCState *s) | ||
55 | { | ||
56 | int level; | ||
57 | int n; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s) | ||
59 | |||
60 | static void stellaris_adc_trigger(void *opaque, int irq, int level) | ||
61 | { | ||
62 | - stellaris_adc_state *s = opaque; | ||
63 | + StellarisADCState *s = opaque; | ||
64 | int n; | ||
65 | |||
66 | for (n = 0; n < 4; n++) { | ||
67 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level) | ||
68 | } | 52 | } |
69 | } | 53 | } |
70 | 54 | ||
71 | -static void stellaris_adc_reset(stellaris_adc_state *s) | 55 | +static bool pl011_is_fifo_enabled(PL011State *s) |
72 | +static void stellaris_adc_reset(StellarisADCState *s) | 56 | +{ |
57 | + return (s->lcr & 0x10) != 0; | ||
58 | +} | ||
59 | + | ||
60 | +static inline unsigned pl011_get_fifo_depth(PL011State *s) | ||
61 | +{ | ||
62 | + /* Note: FIFO depth is expected to be power-of-2 */ | ||
63 | + return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; | ||
64 | +} | ||
65 | + | ||
66 | static uint64_t pl011_read(void *opaque, hwaddr offset, | ||
67 | unsigned size) | ||
73 | { | 68 | { |
74 | int n; | 69 | @@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset, |
75 | 70 | c = s->read_fifo[s->read_pos]; | |
76 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s) | 71 | if (s->read_count > 0) { |
77 | static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, | 72 | s->read_count--; |
78 | unsigned size) | 73 | - if (++s->read_pos == 16) |
74 | - s->read_pos = 0; | ||
75 | + s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1); | ||
76 | } | ||
77 | if (s->read_count == 0) { | ||
78 | s->flags |= PL011_FLAG_RXFE; | ||
79 | @@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque) | ||
80 | PL011State *s = (PL011State *)opaque; | ||
81 | int r; | ||
82 | |||
83 | - if (s->lcr & 0x10) { | ||
84 | - r = s->read_count < 16; | ||
85 | - } else { | ||
86 | - r = s->read_count < 1; | ||
87 | - } | ||
88 | + r = s->read_count < pl011_get_fifo_depth(s); | ||
89 | trace_pl011_can_receive(s->lcr, s->read_count, r); | ||
90 | return r; | ||
91 | } | ||
92 | @@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value) | ||
79 | { | 93 | { |
80 | - stellaris_adc_state *s = opaque; | 94 | PL011State *s = (PL011State *)opaque; |
81 | + StellarisADCState *s = opaque; | 95 | int slot; |
82 | 96 | + unsigned pipe_depth; | |
83 | /* TODO: Implement this. */ | 97 | |
84 | if (offset >= 0x40 && offset < 0xc0) { | 98 | - slot = s->read_pos + s->read_count; |
85 | @@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, | 99 | - if (slot >= 16) |
86 | static void stellaris_adc_write(void *opaque, hwaddr offset, | 100 | - slot -= 16; |
87 | uint64_t value, unsigned size) | 101 | + pipe_depth = pl011_get_fifo_depth(s); |
88 | { | 102 | + slot = (s->read_pos + s->read_count) & (pipe_depth - 1); |
89 | - stellaris_adc_state *s = opaque; | 103 | s->read_fifo[slot] = value; |
90 | + StellarisADCState *s = opaque; | 104 | s->read_count++; |
91 | 105 | s->flags &= ~PL011_FLAG_RXFE; | |
92 | /* TODO: Implement this. */ | 106 | trace_pl011_put_fifo(value, s->read_count); |
93 | if (offset >= 0x40 && offset < 0xc0) { | 107 | - if (!(s->lcr & 0x10) || s->read_count == 16) { |
94 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = { | 108 | + if (s->read_count == pipe_depth) { |
95 | .version_id = 1, | 109 | trace_pl011_put_fifo_full(); |
96 | .minimum_version_id = 1, | 110 | s->flags |= PL011_FLAG_RXFF; |
97 | .fields = (VMStateField[]) { | ||
98 | - VMSTATE_UINT32(actss, stellaris_adc_state), | ||
99 | - VMSTATE_UINT32(ris, stellaris_adc_state), | ||
100 | - VMSTATE_UINT32(im, stellaris_adc_state), | ||
101 | - VMSTATE_UINT32(emux, stellaris_adc_state), | ||
102 | - VMSTATE_UINT32(ostat, stellaris_adc_state), | ||
103 | - VMSTATE_UINT32(ustat, stellaris_adc_state), | ||
104 | - VMSTATE_UINT32(sspri, stellaris_adc_state), | ||
105 | - VMSTATE_UINT32(sac, stellaris_adc_state), | ||
106 | - VMSTATE_UINT32(fifo[0].state, stellaris_adc_state), | ||
107 | - VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16), | ||
108 | - VMSTATE_UINT32(ssmux[0], stellaris_adc_state), | ||
109 | - VMSTATE_UINT32(ssctl[0], stellaris_adc_state), | ||
110 | - VMSTATE_UINT32(fifo[1].state, stellaris_adc_state), | ||
111 | - VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16), | ||
112 | - VMSTATE_UINT32(ssmux[1], stellaris_adc_state), | ||
113 | - VMSTATE_UINT32(ssctl[1], stellaris_adc_state), | ||
114 | - VMSTATE_UINT32(fifo[2].state, stellaris_adc_state), | ||
115 | - VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16), | ||
116 | - VMSTATE_UINT32(ssmux[2], stellaris_adc_state), | ||
117 | - VMSTATE_UINT32(ssctl[2], stellaris_adc_state), | ||
118 | - VMSTATE_UINT32(fifo[3].state, stellaris_adc_state), | ||
119 | - VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16), | ||
120 | - VMSTATE_UINT32(ssmux[3], stellaris_adc_state), | ||
121 | - VMSTATE_UINT32(ssctl[3], stellaris_adc_state), | ||
122 | - VMSTATE_UINT32(noise, stellaris_adc_state), | ||
123 | + VMSTATE_UINT32(actss, StellarisADCState), | ||
124 | + VMSTATE_UINT32(ris, StellarisADCState), | ||
125 | + VMSTATE_UINT32(im, StellarisADCState), | ||
126 | + VMSTATE_UINT32(emux, StellarisADCState), | ||
127 | + VMSTATE_UINT32(ostat, StellarisADCState), | ||
128 | + VMSTATE_UINT32(ustat, StellarisADCState), | ||
129 | + VMSTATE_UINT32(sspri, StellarisADCState), | ||
130 | + VMSTATE_UINT32(sac, StellarisADCState), | ||
131 | + VMSTATE_UINT32(fifo[0].state, StellarisADCState), | ||
132 | + VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16), | ||
133 | + VMSTATE_UINT32(ssmux[0], StellarisADCState), | ||
134 | + VMSTATE_UINT32(ssctl[0], StellarisADCState), | ||
135 | + VMSTATE_UINT32(fifo[1].state, StellarisADCState), | ||
136 | + VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16), | ||
137 | + VMSTATE_UINT32(ssmux[1], StellarisADCState), | ||
138 | + VMSTATE_UINT32(ssctl[1], StellarisADCState), | ||
139 | + VMSTATE_UINT32(fifo[2].state, StellarisADCState), | ||
140 | + VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16), | ||
141 | + VMSTATE_UINT32(ssmux[2], StellarisADCState), | ||
142 | + VMSTATE_UINT32(ssctl[2], StellarisADCState), | ||
143 | + VMSTATE_UINT32(fifo[3].state, StellarisADCState), | ||
144 | + VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16), | ||
145 | + VMSTATE_UINT32(ssmux[3], StellarisADCState), | ||
146 | + VMSTATE_UINT32(ssctl[3], StellarisADCState), | ||
147 | + VMSTATE_UINT32(noise, StellarisADCState), | ||
148 | VMSTATE_END_OF_LIST() | ||
149 | } | 111 | } |
150 | }; | 112 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = { |
151 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = { | 113 | VMSTATE_UINT32(dmacr, PL011State), |
152 | static void stellaris_adc_init(Object *obj) | 114 | VMSTATE_UINT32(int_enabled, PL011State), |
153 | { | 115 | VMSTATE_UINT32(int_level, PL011State), |
154 | DeviceState *dev = DEVICE(obj); | 116 | - VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16), |
155 | - stellaris_adc_state *s = STELLARIS_ADC(obj); | 117 | + VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH), |
156 | + StellarisADCState *s = STELLARIS_ADC(obj); | 118 | VMSTATE_UINT32(ilpr, PL011State), |
157 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 119 | VMSTATE_UINT32(ibrd, PL011State), |
158 | int n; | 120 | VMSTATE_UINT32(fbrd, PL011State), |
159 | |||
160 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data) | ||
161 | static const TypeInfo stellaris_adc_info = { | ||
162 | .name = TYPE_STELLARIS_ADC, | ||
163 | .parent = TYPE_SYS_BUS_DEVICE, | ||
164 | - .instance_size = sizeof(stellaris_adc_state), | ||
165 | + .instance_size = sizeof(StellarisADCState), | ||
166 | .instance_init = stellaris_adc_init, | ||
167 | .class_init = stellaris_adc_class_init, | ||
168 | }; | ||
169 | -- | 121 | -- |
170 | 2.34.1 | 122 | 2.34.1 |
171 | 123 | ||
172 | 124 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
---|---|---|---|
2 | 2 | ||
3 | This patch adds minimal support for AXP-209 PMU. | 3 | Previous change slightly modified the way we handle data writes when |
4 | Most important is chip ID since U-Boot SPL expects version 0x1. Besides | 4 | FIFO is disabled. Previously we kept incrementing read_pos and were |
5 | the chip ID register, reset values for two more registers used by A10 | 5 | storing data at that position, although we only have a |
6 | U-Boot SPL are covered. | 6 | single-register-deep FIFO now. Then we changed it to always store data |
7 | at pos 0. | ||
7 | 8 | ||
8 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 9 | If guest disables FIFO and the proceeds to read data, it will work out |
9 | Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com | 10 | fine, because we still read from current read_pos before setting it to |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | 0. |
12 | |||
13 | However, to make code less fragile, introduce a post_load hook for | ||
14 | PL011State and move fixup read FIFO state when FIFO is disabled. Since | ||
15 | we are introducing a post_load hook, also do some sanity checking on | ||
16 | untrusted incoming input state. | ||
17 | |||
18 | Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | ||
19 | Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 21 | --- |
13 | hw/misc/axp209.c | 238 +++++++++++++++++++++++++++++++++++++++++++ | 22 | hw/char/pl011.c | 25 +++++++++++++++++++++++++ |
14 | MAINTAINERS | 2 + | 23 | 1 file changed, 25 insertions(+) |
15 | hw/misc/Kconfig | 4 + | ||
16 | hw/misc/meson.build | 1 + | ||
17 | hw/misc/trace-events | 5 + | ||
18 | 5 files changed, 250 insertions(+) | ||
19 | create mode 100644 hw/misc/axp209.c | ||
20 | 24 | ||
21 | diff --git a/hw/misc/axp209.c b/hw/misc/axp209.c | 25 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c |
22 | new file mode 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
23 | index XXXXXXX..XXXXXXX | 27 | --- a/hw/char/pl011.c |
24 | --- /dev/null | 28 | +++ b/hw/char/pl011.c |
25 | +++ b/hw/misc/axp209.c | 29 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = { |
26 | @@ -XXX,XX +XXX,XX @@ | 30 | } |
27 | +/* | 31 | }; |
28 | + * AXP-209 PMU Emulation | 32 | |
29 | + * | 33 | +static int pl011_post_load(void *opaque, int version_id) |
30 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 34 | +{ |
31 | + * | 35 | + PL011State* s = opaque; |
32 | + * Permission is hereby granted, free of charge, to any person obtaining a | ||
33 | + * copy of this software and associated documentation files (the "Software"), | ||
34 | + * to deal in the Software without restriction, including without limitation | ||
35 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
36 | + * and/or sell copies of the Software, and to permit persons to whom the | ||
37 | + * Software is furnished to do so, subject to the following conditions: | ||
38 | + * | ||
39 | + * The above copyright notice and this permission notice shall be included in | ||
40 | + * all copies or substantial portions of the Software. | ||
41 | + * | ||
42 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
43 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
44 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
45 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
46 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
47 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
48 | + * DEALINGS IN THE SOFTWARE. | ||
49 | + * | ||
50 | + * SPDX-License-Identifier: MIT | ||
51 | + */ | ||
52 | + | 36 | + |
53 | +#include "qemu/osdep.h" | 37 | + /* Sanity-check input state */ |
54 | +#include "qemu/log.h" | 38 | + if (s->read_pos >= ARRAY_SIZE(s->read_fifo) || |
55 | +#include "trace.h" | 39 | + s->read_count > ARRAY_SIZE(s->read_fifo)) { |
56 | +#include "hw/i2c/i2c.h" | 40 | + return -1; |
57 | +#include "migration/vmstate.h" | ||
58 | + | ||
59 | +#define TYPE_AXP209_PMU "axp209_pmu" | ||
60 | + | ||
61 | +#define AXP209(obj) \ | ||
62 | + OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU) | ||
63 | + | ||
64 | +/* registers */ | ||
65 | +enum { | ||
66 | + REG_POWER_STATUS = 0x0u, | ||
67 | + REG_OPERATING_MODE, | ||
68 | + REG_OTG_VBUS_STATUS, | ||
69 | + REG_CHIP_VERSION, | ||
70 | + REG_DATA_CACHE_0, | ||
71 | + REG_DATA_CACHE_1, | ||
72 | + REG_DATA_CACHE_2, | ||
73 | + REG_DATA_CACHE_3, | ||
74 | + REG_DATA_CACHE_4, | ||
75 | + REG_DATA_CACHE_5, | ||
76 | + REG_DATA_CACHE_6, | ||
77 | + REG_DATA_CACHE_7, | ||
78 | + REG_DATA_CACHE_8, | ||
79 | + REG_DATA_CACHE_9, | ||
80 | + REG_DATA_CACHE_A, | ||
81 | + REG_DATA_CACHE_B, | ||
82 | + REG_POWER_OUTPUT_CTRL = 0x12u, | ||
83 | + REG_DC_DC2_OUT_V_CTRL = 0x23u, | ||
84 | + REG_DC_DC2_DVS_CTRL = 0x25u, | ||
85 | + REG_DC_DC3_OUT_V_CTRL = 0x27u, | ||
86 | + REG_LDO2_4_OUT_V_CTRL, | ||
87 | + REG_LDO3_OUT_V_CTRL, | ||
88 | + REG_VBUS_CH_MGMT = 0x30u, | ||
89 | + REG_SHUTDOWN_V_CTRL, | ||
90 | + REG_SHUTDOWN_CTRL, | ||
91 | + REG_CHARGE_CTRL_1, | ||
92 | + REG_CHARGE_CTRL_2, | ||
93 | + REG_SPARE_CHARGE_CTRL, | ||
94 | + REG_PEK_KEY_CTRL, | ||
95 | + REG_DC_DC_FREQ_SET, | ||
96 | + REG_CHR_TEMP_TH_SET, | ||
97 | + REG_CHR_HIGH_TEMP_TH_CTRL, | ||
98 | + REG_IPSOUT_WARN_L1, | ||
99 | + REG_IPSOUT_WARN_L2, | ||
100 | + REG_DISCHR_TEMP_TH_SET, | ||
101 | + REG_DISCHR_HIGH_TEMP_TH_CTRL, | ||
102 | + REG_IRQ_BANK_1_CTRL = 0x40u, | ||
103 | + REG_IRQ_BANK_2_CTRL, | ||
104 | + REG_IRQ_BANK_3_CTRL, | ||
105 | + REG_IRQ_BANK_4_CTRL, | ||
106 | + REG_IRQ_BANK_5_CTRL, | ||
107 | + REG_IRQ_BANK_1_STAT = 0x48u, | ||
108 | + REG_IRQ_BANK_2_STAT, | ||
109 | + REG_IRQ_BANK_3_STAT, | ||
110 | + REG_IRQ_BANK_4_STAT, | ||
111 | + REG_IRQ_BANK_5_STAT, | ||
112 | + REG_ADC_ACIN_V_H = 0x56u, | ||
113 | + REG_ADC_ACIN_V_L, | ||
114 | + REG_ADC_ACIN_CURR_H, | ||
115 | + REG_ADC_ACIN_CURR_L, | ||
116 | + REG_ADC_VBUS_V_H, | ||
117 | + REG_ADC_VBUS_V_L, | ||
118 | + REG_ADC_VBUS_CURR_H, | ||
119 | + REG_ADC_VBUS_CURR_L, | ||
120 | + REG_ADC_INT_TEMP_H, | ||
121 | + REG_ADC_INT_TEMP_L, | ||
122 | + REG_ADC_TEMP_SENS_V_H = 0x62u, | ||
123 | + REG_ADC_TEMP_SENS_V_L, | ||
124 | + REG_ADC_BAT_V_H = 0x78u, | ||
125 | + REG_ADC_BAT_V_L, | ||
126 | + REG_ADC_BAT_DISCHR_CURR_H, | ||
127 | + REG_ADC_BAT_DISCHR_CURR_L, | ||
128 | + REG_ADC_BAT_CHR_CURR_H, | ||
129 | + REG_ADC_BAT_CHR_CURR_L, | ||
130 | + REG_ADC_IPSOUT_V_H, | ||
131 | + REG_ADC_IPSOUT_V_L, | ||
132 | + REG_DC_DC_MOD_SEL = 0x80u, | ||
133 | + REG_ADC_EN_1, | ||
134 | + REG_ADC_EN_2, | ||
135 | + REG_ADC_SR_CTRL, | ||
136 | + REG_ADC_IN_RANGE, | ||
137 | + REG_GPIO1_ADC_IRQ_RISING_TH, | ||
138 | + REG_GPIO1_ADC_IRQ_FALLING_TH, | ||
139 | + REG_TIMER_CTRL = 0x8au, | ||
140 | + REG_VBUS_CTRL_MON_SRP, | ||
141 | + REG_OVER_TEMP_SHUTDOWN = 0x8fu, | ||
142 | + REG_GPIO0_FEAT_SET, | ||
143 | + REG_GPIO_OUT_HIGH_SET, | ||
144 | + REG_GPIO1_FEAT_SET, | ||
145 | + REG_GPIO2_FEAT_SET, | ||
146 | + REG_GPIO_SIG_STATE_SET_MON, | ||
147 | + REG_GPIO3_SET, | ||
148 | + REG_COULOMB_CNTR_CTRL = 0xb8u, | ||
149 | + REG_POWER_MEAS_RES, | ||
150 | + NR_REGS | ||
151 | +}; | ||
152 | + | ||
153 | +#define AXP209_CHIP_VERSION_ID (0x01) | ||
154 | +#define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16) | ||
155 | +#define AXP209_IRQ_BANK_1_CTRL_RESET (0xd8) | ||
156 | + | ||
157 | +/* A simple I2C slave which returns values of ID or CNT register. */ | ||
158 | +typedef struct AXP209I2CState { | ||
159 | + /*< private >*/ | ||
160 | + I2CSlave i2c; | ||
161 | + /*< public >*/ | ||
162 | + uint8_t regs[NR_REGS]; /* peripheral registers */ | ||
163 | + uint8_t ptr; /* current register index */ | ||
164 | + uint8_t count; /* counter used for tx/rx */ | ||
165 | +} AXP209I2CState; | ||
166 | + | ||
167 | +/* Reset all counters and load ID register */ | ||
168 | +static void axp209_reset_enter(Object *obj, ResetType type) | ||
169 | +{ | ||
170 | + AXP209I2CState *s = AXP209(obj); | ||
171 | + | ||
172 | + memset(s->regs, 0, NR_REGS); | ||
173 | + s->ptr = 0; | ||
174 | + s->count = 0; | ||
175 | + s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID; | ||
176 | + s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET; | ||
177 | + s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET; | ||
178 | +} | ||
179 | + | ||
180 | +/* Handle events from master. */ | ||
181 | +static int axp209_event(I2CSlave *i2c, enum i2c_event event) | ||
182 | +{ | ||
183 | + AXP209I2CState *s = AXP209(i2c); | ||
184 | + | ||
185 | + s->count = 0; | ||
186 | + | ||
187 | + return 0; | ||
188 | +} | ||
189 | + | ||
190 | +/* Called when master requests read */ | ||
191 | +static uint8_t axp209_rx(I2CSlave *i2c) | ||
192 | +{ | ||
193 | + AXP209I2CState *s = AXP209(i2c); | ||
194 | + uint8_t ret = 0xff; | ||
195 | + | ||
196 | + if (s->ptr < NR_REGS) { | ||
197 | + ret = s->regs[s->ptr++]; | ||
198 | + } | 41 | + } |
199 | + | 42 | + |
200 | + trace_axp209_rx(s->ptr - 1, ret); | 43 | + if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) { |
201 | + | 44 | + /* |
202 | + return ret; | 45 | + * Older versions of PL011 didn't ensure that the single |
203 | +} | 46 | + * character in the FIFO in FIFO-disabled mode is in |
204 | + | 47 | + * element 0 of the array; convert to follow the current |
205 | +/* | 48 | + * code's assumptions. |
206 | + * Called when master sends write. | 49 | + */ |
207 | + * Update ptr with byte 0, then perform write with second byte. | 50 | + s->read_fifo[0] = s->read_fifo[s->read_pos]; |
208 | + */ | 51 | + s->read_pos = 0; |
209 | +static int axp209_tx(I2CSlave *i2c, uint8_t data) | ||
210 | +{ | ||
211 | + AXP209I2CState *s = AXP209(i2c); | ||
212 | + | ||
213 | + if (s->count == 0) { | ||
214 | + /* Store register address */ | ||
215 | + s->ptr = data; | ||
216 | + s->count++; | ||
217 | + trace_axp209_select(data); | ||
218 | + } else { | ||
219 | + trace_axp209_tx(s->ptr, data); | ||
220 | + if (s->ptr == REG_DC_DC2_OUT_V_CTRL) { | ||
221 | + s->regs[s->ptr++] = data; | ||
222 | + } | ||
223 | + } | 52 | + } |
224 | + | 53 | + |
225 | + return 0; | 54 | + return 0; |
226 | +} | 55 | +} |
227 | + | 56 | + |
228 | +static const VMStateDescription vmstate_axp209 = { | 57 | static const VMStateDescription vmstate_pl011 = { |
229 | + .name = TYPE_AXP209_PMU, | 58 | .name = "pl011", |
230 | + .version_id = 1, | 59 | .version_id = 2, |
231 | + .fields = (VMStateField[]) { | 60 | .minimum_version_id = 2, |
232 | + VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS), | 61 | + .post_load = pl011_post_load, |
233 | + VMSTATE_UINT8(count, AXP209I2CState), | 62 | .fields = (VMStateField[]) { |
234 | + VMSTATE_UINT8(ptr, AXP209I2CState), | 63 | VMSTATE_UINT32(readbuff, PL011State), |
235 | + VMSTATE_END_OF_LIST() | 64 | VMSTATE_UINT32(flags, PL011State), |
236 | + } | ||
237 | +}; | ||
238 | + | ||
239 | +static void axp209_class_init(ObjectClass *oc, void *data) | ||
240 | +{ | ||
241 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
242 | + I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc); | ||
243 | + ResettableClass *rc = RESETTABLE_CLASS(oc); | ||
244 | + | ||
245 | + rc->phases.enter = axp209_reset_enter; | ||
246 | + dc->vmsd = &vmstate_axp209; | ||
247 | + isc->event = axp209_event; | ||
248 | + isc->recv = axp209_rx; | ||
249 | + isc->send = axp209_tx; | ||
250 | +} | ||
251 | + | ||
252 | +static const TypeInfo axp209_info = { | ||
253 | + .name = TYPE_AXP209_PMU, | ||
254 | + .parent = TYPE_I2C_SLAVE, | ||
255 | + .instance_size = sizeof(AXP209I2CState), | ||
256 | + .class_init = axp209_class_init | ||
257 | +}; | ||
258 | + | ||
259 | +static void axp209_register_devices(void) | ||
260 | +{ | ||
261 | + type_register_static(&axp209_info); | ||
262 | +} | ||
263 | + | ||
264 | +type_init(axp209_register_devices); | ||
265 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
266 | index XXXXXXX..XXXXXXX 100644 | ||
267 | --- a/MAINTAINERS | ||
268 | +++ b/MAINTAINERS | ||
269 | @@ -XXX,XX +XXX,XX @@ ARM Machines | ||
270 | Allwinner-a10 | ||
271 | M: Beniamino Galvani <b.galvani@gmail.com> | ||
272 | M: Peter Maydell <peter.maydell@linaro.org> | ||
273 | +R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
274 | L: qemu-arm@nongnu.org | ||
275 | S: Odd Fixes | ||
276 | F: hw/*/allwinner* | ||
277 | F: include/hw/*/allwinner* | ||
278 | F: hw/arm/cubieboard.c | ||
279 | F: docs/system/arm/cubieboard.rst | ||
280 | +F: hw/misc/axp209.c | ||
281 | |||
282 | Allwinner-h3 | ||
283 | M: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
284 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
285 | index XXXXXXX..XXXXXXX 100644 | ||
286 | --- a/hw/misc/Kconfig | ||
287 | +++ b/hw/misc/Kconfig | ||
288 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10_CCM | ||
289 | config ALLWINNER_A10_DRAMC | ||
290 | bool | ||
291 | |||
292 | +config AXP209_PMU | ||
293 | + bool | ||
294 | + depends on I2C | ||
295 | + | ||
296 | source macio/Kconfig | ||
297 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
298 | index XXXXXXX..XXXXXXX 100644 | ||
299 | --- a/hw/misc/meson.build | ||
300 | +++ b/hw/misc/meson.build | ||
301 | @@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c' | ||
302 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c')) | ||
303 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c')) | ||
304 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c')) | ||
305 | +softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c')) | ||
306 | softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c')) | ||
307 | softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c')) | ||
308 | softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c')) | ||
309 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
310 | index XXXXXXX..XXXXXXX 100644 | ||
311 | --- a/hw/misc/trace-events | ||
312 | +++ b/hw/misc/trace-events | ||
313 | @@ -XXX,XX +XXX,XX @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" | ||
314 | avr_power_read(uint8_t value) "power_reduc read value:%u" | ||
315 | avr_power_write(uint8_t value) "power_reduc write value:%u" | ||
316 | |||
317 | +# axp209.c | ||
318 | +axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8 | ||
319 | +axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8 | ||
320 | +axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8 | ||
321 | + | ||
322 | # eccmemctl.c | ||
323 | ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" | ||
324 | ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" | ||
325 | -- | 65 | -- |
326 | 2.34.1 | 66 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
---|---|---|---|
2 | 2 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 3 | PL011 currently lacks a reset method. Implement it. |
4 | 4 | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 5 | Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20230109115316.2235-11-philmd@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | hw/arm/omap_sx1.c | 33 +++++++++++++++++---------------- | 11 | hw/char/pl011.c | 26 +++++++++++++++++++++----- |
11 | 1 file changed, 17 insertions(+), 16 deletions(-) | 12 | 1 file changed, 21 insertions(+), 5 deletions(-) |
12 | 13 | ||
13 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | 14 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/omap_sx1.c | 16 | --- a/hw/char/pl011.c |
16 | +++ b/hw/arm/omap_sx1.c | 17 | +++ b/hw/char/pl011.c |
17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj) |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | 19 | s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s, |
19 | */ | 20 | ClockUpdate); |
20 | #include "qemu/osdep.h" | 21 | |
21 | +#include "qemu/units.h" | 22 | - s->read_trigger = 1; |
22 | #include "qapi/error.h" | 23 | - s->ifl = 0x12; |
23 | #include "ui/console.h" | 24 | - s->cr = 0x300; |
24 | #include "hw/arm/omap.h" | 25 | - s->flags = 0x90; |
25 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = { | 26 | - |
26 | .endianness = DEVICE_NATIVE_ENDIAN, | 27 | s->id = pl011_id_arm; |
27 | }; | ||
28 | |||
29 | -#define sdram_size 0x02000000 | ||
30 | -#define sector_size (128 * 1024) | ||
31 | -#define flash0_size (16 * 1024 * 1024) | ||
32 | -#define flash1_size ( 8 * 1024 * 1024) | ||
33 | -#define flash2_size (32 * 1024 * 1024) | ||
34 | +#define SDRAM_SIZE (32 * MiB) | ||
35 | +#define SECTOR_SIZE (128 * KiB) | ||
36 | +#define FLASH0_SIZE (16 * MiB) | ||
37 | +#define FLASH1_SIZE (8 * MiB) | ||
38 | +#define FLASH2_SIZE (32 * MiB) | ||
39 | |||
40 | static struct arm_boot_info sx1_binfo = { | ||
41 | .loader_start = OMAP_EMIFF_BASE, | ||
42 | - .ram_size = sdram_size, | ||
43 | + .ram_size = SDRAM_SIZE, | ||
44 | .board_id = 0x265, | ||
45 | }; | ||
46 | |||
47 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
48 | static uint32_t cs3val = 0x00001139; | ||
49 | DriveInfo *dinfo; | ||
50 | int fl_idx; | ||
51 | - uint32_t flash_size = flash0_size; | ||
52 | + uint32_t flash_size = FLASH0_SIZE; | ||
53 | |||
54 | if (machine->ram_size != mc->default_ram_size) { | ||
55 | char *sz = size_to_str(mc->default_ram_size); | ||
56 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
57 | } | ||
58 | |||
59 | if (version == 2) { | ||
60 | - flash_size = flash2_size; | ||
61 | + flash_size = FLASH2_SIZE; | ||
62 | } | ||
63 | |||
64 | memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
66 | if (!pflash_cfi01_register(OMAP_CS0_BASE, | ||
67 | "omap_sx1.flash0-1", flash_size, | ||
68 | blk_by_legacy_dinfo(dinfo), | ||
69 | - sector_size, 4, 0, 0, 0, 0, 0)) { | ||
70 | + SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
71 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
72 | fl_idx); | ||
73 | } | ||
74 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
75 | (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { | ||
76 | MemoryRegion *flash_1 = g_new(MemoryRegion, 1); | ||
77 | memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0", | ||
78 | - flash1_size, &error_fatal); | ||
79 | + FLASH1_SIZE, &error_fatal); | ||
80 | memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1); | ||
81 | |||
82 | memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, | ||
83 | - "sx1.cs1", OMAP_CS1_SIZE - flash1_size); | ||
84 | + "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE); | ||
85 | memory_region_add_subregion(address_space, | ||
86 | - OMAP_CS1_BASE + flash1_size, &cs[1]); | ||
87 | + OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]); | ||
88 | |||
89 | if (!pflash_cfi01_register(OMAP_CS1_BASE, | ||
90 | - "omap_sx1.flash1-1", flash1_size, | ||
91 | + "omap_sx1.flash1-1", FLASH1_SIZE, | ||
92 | blk_by_legacy_dinfo(dinfo), | ||
93 | - sector_size, 4, 0, 0, 0, 0, 0)) { | ||
94 | + SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
95 | fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
96 | fl_idx); | ||
97 | } | ||
98 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) | ||
99 | mc->init = sx1_init_v2; | ||
100 | mc->ignore_memory_transaction_failures = true; | ||
101 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); | ||
102 | - mc->default_ram_size = sdram_size; | ||
103 | + mc->default_ram_size = SDRAM_SIZE; | ||
104 | mc->default_ram_id = "omap1.dram"; | ||
105 | } | 28 | } |
106 | 29 | ||
107 | @@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) | 30 | @@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp) |
108 | mc->init = sx1_init_v1; | 31 | pl011_event, NULL, s, NULL, true); |
109 | mc->ignore_memory_transaction_failures = true; | ||
110 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); | ||
111 | - mc->default_ram_size = sdram_size; | ||
112 | + mc->default_ram_size = SDRAM_SIZE; | ||
113 | mc->default_ram_id = "omap1.dram"; | ||
114 | } | 32 | } |
115 | 33 | ||
34 | +static void pl011_reset(DeviceState *dev) | ||
35 | +{ | ||
36 | + PL011State *s = PL011(dev); | ||
37 | + | ||
38 | + s->lcr = 0; | ||
39 | + s->rsr = 0; | ||
40 | + s->dmacr = 0; | ||
41 | + s->int_enabled = 0; | ||
42 | + s->int_level = 0; | ||
43 | + s->ilpr = 0; | ||
44 | + s->ibrd = 0; | ||
45 | + s->fbrd = 0; | ||
46 | + s->read_pos = 0; | ||
47 | + s->read_count = 0; | ||
48 | + s->read_trigger = 1; | ||
49 | + s->ifl = 0x12; | ||
50 | + s->cr = 0x300; | ||
51 | + s->flags = 0x90; | ||
52 | +} | ||
53 | + | ||
54 | static void pl011_class_init(ObjectClass *oc, void *data) | ||
55 | { | ||
56 | DeviceClass *dc = DEVICE_CLASS(oc); | ||
57 | |||
58 | dc->realize = pl011_realize; | ||
59 | + dc->reset = pl011_reset; | ||
60 | dc->vmsd = &vmstate_pl011; | ||
61 | device_class_set_props(dc, pl011_properties); | ||
62 | } | ||
116 | -- | 63 | -- |
117 | 2.34.1 | 64 | 2.34.1 |
118 | 65 | ||
119 | 66 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
---|---|---|---|
2 | 2 | ||
3 | The structure is named SECUREECState. Rename the type accordingly. | 3 | Current FIFO handling code does not reset RXFE/RXFF flags when guest |
4 | resets FIFO by writing to UARTLCR register, although internal FIFO state | ||
5 | is reset to 0 read count. Actual guest-visible flag update will happen | ||
6 | only on next data read or write attempt. As a result of that any guest | ||
7 | that expects RXFE flag to be set (and RXFF to be cleared) after resetting | ||
8 | FIFO will never see that happen. | ||
4 | 9 | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 10 | Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20230109140306.23161-12-philmd@linaro.org | 12 | Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 14 | --- |
10 | hw/misc/sbsa_ec.c | 13 +++++++------ | 15 | hw/char/pl011.c | 18 +++++++++++++----- |
11 | 1 file changed, 7 insertions(+), 6 deletions(-) | 16 | 1 file changed, 13 insertions(+), 5 deletions(-) |
12 | 17 | ||
13 | diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c | 18 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c |
14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/misc/sbsa_ec.c | 20 | --- a/hw/char/pl011.c |
16 | +++ b/hw/misc/sbsa_ec.c | 21 | +++ b/hw/char/pl011.c |
17 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s) |
18 | #include "hw/sysbus.h" | 23 | return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; |
19 | #include "sysemu/runstate.h" | ||
20 | |||
21 | -typedef struct { | ||
22 | +typedef struct SECUREECState { | ||
23 | SysBusDevice parent_obj; | ||
24 | MemoryRegion iomem; | ||
25 | } SECUREECState; | ||
26 | |||
27 | -#define TYPE_SBSA_EC "sbsa-ec" | ||
28 | -#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC) | ||
29 | +#define TYPE_SBSA_SECURE_EC "sbsa-ec" | ||
30 | +#define SBSA_SECURE_EC(obj) \ | ||
31 | + OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC) | ||
32 | |||
33 | enum sbsa_ec_powerstates { | ||
34 | SBSA_EC_CMD_POWEROFF = 0x01, | ||
35 | @@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size) | ||
36 | } | 24 | } |
37 | 25 | ||
38 | static void sbsa_ec_write(void *opaque, hwaddr offset, | 26 | +static inline void pl011_reset_fifo(PL011State *s) |
39 | - uint64_t value, unsigned size) | 27 | +{ |
40 | + uint64_t value, unsigned size) | 28 | + s->read_count = 0; |
29 | + s->read_pos = 0; | ||
30 | + | ||
31 | + /* Reset FIFO flags */ | ||
32 | + s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); | ||
33 | + s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE; | ||
34 | +} | ||
35 | + | ||
36 | static uint64_t pl011_read(void *opaque, hwaddr offset, | ||
37 | unsigned size) | ||
41 | { | 38 | { |
42 | if (offset == 0) { /* PSCI machine power command register */ | 39 | @@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset, |
43 | switch (value) { | 40 | case 11: /* UARTLCR_H */ |
44 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sbsa_ec_ops = { | 41 | /* Reset the FIFO state on FIFO enable or disable */ |
45 | 42 | if ((s->lcr ^ value) & 0x10) { | |
46 | static void sbsa_ec_init(Object *obj) | 43 | - s->read_count = 0; |
47 | { | 44 | - s->read_pos = 0; |
48 | - SECUREECState *s = SECURE_EC(obj); | 45 | + pl011_reset_fifo(s); |
49 | + SECUREECState *s = SBSA_SECURE_EC(obj); | 46 | } |
50 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | 47 | if ((s->lcr ^ value) & 0x1) { |
51 | 48 | int break_enable = value & 0x1; | |
52 | memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec", | 49 | @@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev) |
53 | @@ -XXX,XX +XXX,XX @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data) | 50 | s->ilpr = 0; |
51 | s->ibrd = 0; | ||
52 | s->fbrd = 0; | ||
53 | - s->read_pos = 0; | ||
54 | - s->read_count = 0; | ||
55 | s->read_trigger = 1; | ||
56 | s->ifl = 0x12; | ||
57 | s->cr = 0x300; | ||
58 | - s->flags = 0x90; | ||
59 | + s->flags = 0; | ||
60 | + pl011_reset_fifo(s); | ||
54 | } | 61 | } |
55 | 62 | ||
56 | static const TypeInfo sbsa_ec_info = { | 63 | static void pl011_class_init(ObjectClass *oc, void *data) |
57 | - .name = TYPE_SBSA_EC, | ||
58 | + .name = TYPE_SBSA_SECURE_EC, | ||
59 | .parent = TYPE_SYS_BUS_DEVICE, | ||
60 | .instance_size = sizeof(SECUREECState), | ||
61 | .instance_init = sbsa_ec_init, | ||
62 | -- | 64 | -- |
63 | 2.34.1 | 65 | 2.34.1 |
64 | |||
65 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Following docs/devel/style.rst guidelines, rename | 3 | We currently only support GICv2 emulation. To also support GICv3, we will |
4 | omap_intr_handler_s -> OMAPIntcState. This also remove a | 4 | need to pass a few system registers into their respective handler functions. |
5 | use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call. | 5 | |
6 | 6 | This patch adds support for HVF to call into the TCG callbacks for GICv3 | |
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | system register handlers. This is safe because the GICv3 TCG code is generic |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | as long as we limit ourselves to EL0 and EL1 - which are the only modes |
9 | Message-id: 20230109140306.23161-7-philmd@linaro.org | 9 | supported by HVF. |
10 | |||
11 | To make sure nobody trips over that, we also annotate callbacks that don't | ||
12 | work in HVF mode, such as EL state change hooks. | ||
13 | |||
14 | With GICv3 support in place, we can run with more than 8 vCPUs. | ||
15 | |||
16 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
17 | Message-id: 20230128224459.70676-1-agraf@csgraf.de | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 20 | --- |
12 | include/hw/arm/omap.h | 9 ++++----- | 21 | hw/intc/arm_gicv3_cpuif.c | 16 +++- |
13 | hw/intc/omap_intc.c | 38 +++++++++++++++++++------------------- | 22 | target/arm/hvf/hvf.c | 151 ++++++++++++++++++++++++++++++++++++ |
14 | 2 files changed, 23 insertions(+), 24 deletions(-) | 23 | target/arm/hvf/trace-events | 2 + |
15 | 24 | 3 files changed, 168 insertions(+), 1 deletion(-) | |
16 | diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h | 25 | |
26 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/omap.h | 28 | --- a/hw/intc/arm_gicv3_cpuif.c |
19 | +++ b/include/hw/arm/omap.h | 29 | +++ b/hw/intc/arm_gicv3_cpuif.c |
20 | @@ -XXX,XX +XXX,XX @@ void omap_clk_reparent(omap_clk clk, omap_clk parent); | 30 | @@ -XXX,XX +XXX,XX @@ |
21 | 31 | #include "hw/irq.h" | |
22 | /* omap_intc.c */ | 32 | #include "cpu.h" |
23 | #define TYPE_OMAP_INTC "common-omap-intc" | 33 | #include "target/arm/cpregs.h" |
24 | -typedef struct omap_intr_handler_s omap_intr_handler; | 34 | +#include "sysemu/tcg.h" |
25 | -DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC, | 35 | +#include "sysemu/qtest.h" |
26 | - TYPE_OMAP_INTC) | ||
27 | +typedef struct OMAPIntcState OMAPIntcState; | ||
28 | +DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) | ||
29 | |||
30 | 36 | ||
31 | /* | 37 | /* |
32 | @@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC, | 38 | * Special case return value from hppvi_index(); must be larger than |
33 | * (ie the struct omap_mpu_state_s*) to do the clockname to pointer | 39 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) |
34 | * translation.) | 40 | * which case we'd get the wrong value. |
35 | */ | 41 | * So instead we define the regs with no ri->opaque info, and |
36 | -void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); | 42 | * get back to the GICv3CPUState from the CPUARMState. |
37 | -void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); | 43 | + * |
38 | +void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); | 44 | + * These CP regs callbacks can be called from either TCG or HVF code. |
39 | +void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); | 45 | */ |
40 | 46 | define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); | |
41 | /* omap_i2c.c */ | 47 | |
42 | #define TYPE_OMAP_I2C "omap_i2c" | 48 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) |
43 | diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c | 49 | define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo); |
44 | index XXXXXXX..XXXXXXX 100644 | 50 | } |
45 | --- a/hw/intc/omap_intc.c | 51 | } |
46 | +++ b/hw/intc/omap_intc.c | 52 | - arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); |
47 | @@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_bank_s { | 53 | + if (tcg_enabled() || qtest_enabled()) { |
48 | unsigned char priority[32]; | 54 | + /* |
49 | }; | 55 | + * We can only trap EL changes with TCG. However the GIC interrupt |
50 | 56 | + * state only changes on EL changes involving EL2 or EL3, so for | |
51 | -struct omap_intr_handler_s { | 57 | + * the non-TCG case this is OK, as EL2 and EL3 can't exist. |
52 | +struct OMAPIntcState { | 58 | + */ |
53 | SysBusDevice parent_obj; | 59 | + arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); |
54 | 60 | + } else { | |
55 | qemu_irq *pins; | 61 | + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); |
56 | @@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_s { | 62 | + assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); |
57 | struct omap_intr_handler_bank_s bank[3]; | 63 | + } |
58 | }; | ||
59 | |||
60 | -static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) | ||
61 | +static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq) | ||
62 | { | ||
63 | int i, j, sir_intr, p_intr, p; | ||
64 | uint32_t level; | ||
65 | @@ -XXX,XX +XXX,XX @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) | ||
66 | s->sir_intr[is_fiq] = sir_intr; | ||
67 | } | ||
68 | |||
69 | -static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) | ||
70 | +static inline void omap_inth_update(OMAPIntcState *s, int is_fiq) | ||
71 | { | ||
72 | int i; | ||
73 | uint32_t has_intr = 0; | ||
74 | @@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) | ||
75 | |||
76 | static void omap_set_intr(void *opaque, int irq, int req) | ||
77 | { | ||
78 | - struct omap_intr_handler_s *ih = opaque; | ||
79 | + OMAPIntcState *ih = opaque; | ||
80 | uint32_t rise; | ||
81 | |||
82 | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req) | ||
84 | /* Simplified version with no edge detection */ | ||
85 | static void omap_set_intr_noedge(void *opaque, int irq, int req) | ||
86 | { | ||
87 | - struct omap_intr_handler_s *ih = opaque; | ||
88 | + OMAPIntcState *ih = opaque; | ||
89 | uint32_t rise; | ||
90 | |||
91 | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; | ||
92 | @@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req) | ||
93 | static uint64_t omap_inth_read(void *opaque, hwaddr addr, | ||
94 | unsigned size) | ||
95 | { | ||
96 | - struct omap_intr_handler_s *s = opaque; | ||
97 | + OMAPIntcState *s = opaque; | ||
98 | int i, offset = addr; | ||
99 | int bank_no = offset >> 8; | ||
100 | int line_no; | ||
101 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr, | ||
102 | static void omap_inth_write(void *opaque, hwaddr addr, | ||
103 | uint64_t value, unsigned size) | ||
104 | { | ||
105 | - struct omap_intr_handler_s *s = opaque; | ||
106 | + OMAPIntcState *s = opaque; | ||
107 | int i, offset = addr; | ||
108 | int bank_no = offset >> 8; | ||
109 | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; | ||
110 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_inth_mem_ops = { | ||
111 | |||
112 | static void omap_inth_reset(DeviceState *dev) | ||
113 | { | ||
114 | - struct omap_intr_handler_s *s = OMAP_INTC(dev); | ||
115 | + OMAPIntcState *s = OMAP_INTC(dev); | ||
116 | int i; | ||
117 | |||
118 | for (i = 0; i < s->nbanks; ++i){ | ||
119 | @@ -XXX,XX +XXX,XX @@ static void omap_inth_reset(DeviceState *dev) | ||
120 | static void omap_intc_init(Object *obj) | ||
121 | { | ||
122 | DeviceState *dev = DEVICE(obj); | ||
123 | - struct omap_intr_handler_s *s = OMAP_INTC(obj); | ||
124 | + OMAPIntcState *s = OMAP_INTC(obj); | ||
125 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
126 | |||
127 | s->nbanks = 1; | ||
128 | @@ -XXX,XX +XXX,XX @@ static void omap_intc_init(Object *obj) | ||
129 | |||
130 | static void omap_intc_realize(DeviceState *dev, Error **errp) | ||
131 | { | ||
132 | - struct omap_intr_handler_s *s = OMAP_INTC(dev); | ||
133 | + OMAPIntcState *s = OMAP_INTC(dev); | ||
134 | |||
135 | if (!s->iclk) { | ||
136 | error_setg(errp, "omap-intc: clk not connected"); | ||
137 | } | 64 | } |
138 | } | 65 | } |
139 | 66 | diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c | |
140 | -void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk) | 67 | index XXXXXXX..XXXXXXX 100644 |
141 | +void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk) | 68 | --- a/target/arm/hvf/hvf.c |
69 | +++ b/target/arm/hvf/hvf.c | ||
70 | @@ -XXX,XX +XXX,XX @@ | ||
71 | #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0) | ||
72 | #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7) | ||
73 | |||
74 | +#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 12, 8, 4) | ||
75 | +#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 12, 8, 5) | ||
76 | +#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 12, 8, 6) | ||
77 | +#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 12, 8, 7) | ||
78 | +#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 12, 9, 0) | ||
79 | +#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 12, 9, 1) | ||
80 | +#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 12, 9, 2) | ||
81 | +#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 12, 9, 3) | ||
82 | +#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 12, 11, 6) | ||
83 | +#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 12, 8, 3) | ||
84 | +#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 12, 12, 3) | ||
85 | +#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 12, 12, 4) | ||
86 | +#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 12, 11, 1) | ||
87 | +#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 12, 8, 1) | ||
88 | +#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 12, 12, 1) | ||
89 | +#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 12, 8, 2) | ||
90 | +#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 12, 12, 2) | ||
91 | +#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 12, 8, 0) | ||
92 | +#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 12, 12, 0) | ||
93 | +#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 12, 12, 6) | ||
94 | +#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 12, 12, 7) | ||
95 | +#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 4, 6, 0) | ||
96 | +#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 12, 11, 3) | ||
97 | +#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 12, 11, 7) | ||
98 | +#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 12, 11, 5) | ||
99 | +#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 12, 12, 5) | ||
100 | + | ||
101 | #define WFX_IS_WFE (1 << 0) | ||
102 | |||
103 | #define TMR_CTL_ENABLE (1 << 0) | ||
104 | @@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg) | ||
105 | SYSREG_CRM(reg) < 8; | ||
106 | } | ||
107 | |||
108 | +static uint32_t hvf_reg2cp_reg(uint32_t reg) | ||
109 | +{ | ||
110 | + return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, | ||
111 | + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, | ||
112 | + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, | ||
113 | + (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, | ||
114 | + (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, | ||
115 | + (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); | ||
116 | +} | ||
117 | + | ||
118 | +static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val) | ||
119 | +{ | ||
120 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
121 | + CPUARMState *env = &arm_cpu->env; | ||
122 | + const ARMCPRegInfo *ri; | ||
123 | + | ||
124 | + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); | ||
125 | + if (ri) { | ||
126 | + if (ri->accessfn) { | ||
127 | + if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) { | ||
128 | + return false; | ||
129 | + } | ||
130 | + } | ||
131 | + if (ri->type & ARM_CP_CONST) { | ||
132 | + *val = ri->resetvalue; | ||
133 | + } else if (ri->readfn) { | ||
134 | + *val = ri->readfn(env, ri); | ||
135 | + } else { | ||
136 | + *val = CPREG_FIELD64(env, ri); | ||
137 | + } | ||
138 | + trace_hvf_vgic_read(ri->name, *val); | ||
139 | + return true; | ||
140 | + } | ||
141 | + | ||
142 | + return false; | ||
143 | +} | ||
144 | + | ||
145 | static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
142 | { | 146 | { |
143 | intc->iclk = clk; | 147 | ARMCPU *arm_cpu = ARM_CPU(cpu); |
148 | @@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt) | ||
149 | case SYSREG_OSDLR_EL1: | ||
150 | /* Dummy register */ | ||
151 | break; | ||
152 | + case SYSREG_ICC_AP0R0_EL1: | ||
153 | + case SYSREG_ICC_AP0R1_EL1: | ||
154 | + case SYSREG_ICC_AP0R2_EL1: | ||
155 | + case SYSREG_ICC_AP0R3_EL1: | ||
156 | + case SYSREG_ICC_AP1R0_EL1: | ||
157 | + case SYSREG_ICC_AP1R1_EL1: | ||
158 | + case SYSREG_ICC_AP1R2_EL1: | ||
159 | + case SYSREG_ICC_AP1R3_EL1: | ||
160 | + case SYSREG_ICC_ASGI1R_EL1: | ||
161 | + case SYSREG_ICC_BPR0_EL1: | ||
162 | + case SYSREG_ICC_BPR1_EL1: | ||
163 | + case SYSREG_ICC_DIR_EL1: | ||
164 | + case SYSREG_ICC_EOIR0_EL1: | ||
165 | + case SYSREG_ICC_EOIR1_EL1: | ||
166 | + case SYSREG_ICC_HPPIR0_EL1: | ||
167 | + case SYSREG_ICC_HPPIR1_EL1: | ||
168 | + case SYSREG_ICC_IAR0_EL1: | ||
169 | + case SYSREG_ICC_IAR1_EL1: | ||
170 | + case SYSREG_ICC_IGRPEN0_EL1: | ||
171 | + case SYSREG_ICC_IGRPEN1_EL1: | ||
172 | + case SYSREG_ICC_PMR_EL1: | ||
173 | + case SYSREG_ICC_SGI0R_EL1: | ||
174 | + case SYSREG_ICC_SGI1R_EL1: | ||
175 | + case SYSREG_ICC_SRE_EL1: | ||
176 | + case SYSREG_ICC_CTLR_EL1: | ||
177 | + /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ | ||
178 | + if (!hvf_sysreg_read_cp(cpu, reg, &val)) { | ||
179 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); | ||
180 | + } | ||
181 | + break; | ||
182 | default: | ||
183 | if (is_id_sysreg(reg)) { | ||
184 | /* ID system registers read as RES0 */ | ||
185 | @@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value) | ||
186 | } | ||
144 | } | 187 | } |
145 | 188 | ||
146 | -void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk) | 189 | +static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) |
147 | +void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk) | 190 | +{ |
191 | + ARMCPU *arm_cpu = ARM_CPU(cpu); | ||
192 | + CPUARMState *env = &arm_cpu->env; | ||
193 | + const ARMCPRegInfo *ri; | ||
194 | + | ||
195 | + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); | ||
196 | + | ||
197 | + if (ri) { | ||
198 | + if (ri->accessfn) { | ||
199 | + if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) { | ||
200 | + return false; | ||
201 | + } | ||
202 | + } | ||
203 | + if (ri->writefn) { | ||
204 | + ri->writefn(env, ri, val); | ||
205 | + } else { | ||
206 | + CPREG_FIELD64(env, ri) = val; | ||
207 | + } | ||
208 | + | ||
209 | + trace_hvf_vgic_write(ri->name, val); | ||
210 | + return true; | ||
211 | + } | ||
212 | + | ||
213 | + return false; | ||
214 | +} | ||
215 | + | ||
216 | static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) | ||
148 | { | 217 | { |
149 | intc->fclk = clk; | 218 | ARMCPU *arm_cpu = ARM_CPU(cpu); |
150 | } | 219 | @@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) |
151 | 220 | case SYSREG_OSDLR_EL1: | |
152 | static Property omap_intc_properties[] = { | 221 | /* Dummy register */ |
153 | - DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100), | 222 | break; |
154 | + DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100), | 223 | + case SYSREG_ICC_AP0R0_EL1: |
155 | DEFINE_PROP_END_OF_LIST(), | 224 | + case SYSREG_ICC_AP0R1_EL1: |
156 | }; | 225 | + case SYSREG_ICC_AP0R2_EL1: |
157 | 226 | + case SYSREG_ICC_AP0R3_EL1: | |
158 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = { | 227 | + case SYSREG_ICC_AP1R0_EL1: |
159 | static uint64_t omap2_inth_read(void *opaque, hwaddr addr, | 228 | + case SYSREG_ICC_AP1R1_EL1: |
160 | unsigned size) | 229 | + case SYSREG_ICC_AP1R2_EL1: |
161 | { | 230 | + case SYSREG_ICC_AP1R3_EL1: |
162 | - struct omap_intr_handler_s *s = opaque; | 231 | + case SYSREG_ICC_ASGI1R_EL1: |
163 | + OMAPIntcState *s = opaque; | 232 | + case SYSREG_ICC_BPR0_EL1: |
164 | int offset = addr; | 233 | + case SYSREG_ICC_BPR1_EL1: |
165 | int bank_no, line_no; | 234 | + case SYSREG_ICC_CTLR_EL1: |
166 | struct omap_intr_handler_bank_s *bank = NULL; | 235 | + case SYSREG_ICC_DIR_EL1: |
167 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr, | 236 | + case SYSREG_ICC_EOIR0_EL1: |
168 | static void omap2_inth_write(void *opaque, hwaddr addr, | 237 | + case SYSREG_ICC_EOIR1_EL1: |
169 | uint64_t value, unsigned size) | 238 | + case SYSREG_ICC_HPPIR0_EL1: |
170 | { | 239 | + case SYSREG_ICC_HPPIR1_EL1: |
171 | - struct omap_intr_handler_s *s = opaque; | 240 | + case SYSREG_ICC_IAR0_EL1: |
172 | + OMAPIntcState *s = opaque; | 241 | + case SYSREG_ICC_IAR1_EL1: |
173 | int offset = addr; | 242 | + case SYSREG_ICC_IGRPEN0_EL1: |
174 | int bank_no, line_no; | 243 | + case SYSREG_ICC_IGRPEN1_EL1: |
175 | struct omap_intr_handler_bank_s *bank = NULL; | 244 | + case SYSREG_ICC_PMR_EL1: |
176 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_inth_mem_ops = { | 245 | + case SYSREG_ICC_SGI0R_EL1: |
177 | static void omap2_intc_init(Object *obj) | 246 | + case SYSREG_ICC_SGI1R_EL1: |
178 | { | 247 | + case SYSREG_ICC_SRE_EL1: |
179 | DeviceState *dev = DEVICE(obj); | 248 | + /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */ |
180 | - struct omap_intr_handler_s *s = OMAP_INTC(obj); | 249 | + if (!hvf_sysreg_write_cp(cpu, reg, val)) { |
181 | + OMAPIntcState *s = OMAP_INTC(obj); | 250 | + hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized()); |
182 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 251 | + } |
183 | 252 | + break; | |
184 | s->level_only = 1; | 253 | default: |
185 | @@ -XXX,XX +XXX,XX @@ static void omap2_intc_init(Object *obj) | 254 | cpu_synchronize_state(cpu); |
186 | 255 | trace_hvf_unhandled_sysreg_write(env->pc, reg, | |
187 | static void omap2_intc_realize(DeviceState *dev, Error **errp) | 256 | diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events |
188 | { | 257 | index XXXXXXX..XXXXXXX 100644 |
189 | - struct omap_intr_handler_s *s = OMAP_INTC(dev); | 258 | --- a/target/arm/hvf/trace-events |
190 | + OMAPIntcState *s = OMAP_INTC(dev); | 259 | +++ b/target/arm/hvf/trace-events |
191 | 260 | @@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64 | |
192 | if (!s->iclk) { | 261 | hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64 |
193 | error_setg(errp, "omap2-intc: iclk not connected"); | 262 | hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]" |
194 | @@ -XXX,XX +XXX,XX @@ static void omap2_intc_realize(DeviceState *dev, Error **errp) | 263 | hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x" |
195 | } | 264 | +hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]" |
196 | 265 | +hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]" | |
197 | static Property omap2_intc_properties[] = { | ||
198 | - DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s, | ||
199 | + DEFINE_PROP_UINT8("revision", OMAPIntcState, | ||
200 | revision, 0x21), | ||
201 | DEFINE_PROP_END_OF_LIST(), | ||
202 | }; | ||
203 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo omap2_intc_info = { | ||
204 | static const TypeInfo omap_intc_type_info = { | ||
205 | .name = TYPE_OMAP_INTC, | ||
206 | .parent = TYPE_SYS_BUS_DEVICE, | ||
207 | - .instance_size = sizeof(omap_intr_handler), | ||
208 | + .instance_size = sizeof(OMAPIntcState), | ||
209 | .abstract = true, | ||
210 | }; | ||
211 | |||
212 | -- | 266 | -- |
213 | 2.34.1 | 267 | 2.34.1 |
214 | |||
215 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 3 | Up to now, the finalize_gic_version() code open coded what is essentially |
4 | a support bitmap match between host/emulation environment and desired | ||
5 | target GIC type. | ||
6 | |||
7 | This open coding leads to undesirable side effects. For example, a VM with | ||
8 | KVM and -smp 10 will automatically choose GICv3 while the same command | ||
9 | line with TCG will stay on GICv2 and fail the launch. | ||
10 | |||
11 | This patch combines the TCG and KVM matching code paths by making | ||
12 | everything a 2 pass process. First, we determine which GIC versions the | ||
13 | current environment is able to support, then we go through a single | ||
14 | state machine to determine which target GIC mode that means for us. | ||
15 | |||
16 | After this patch, the only user noticable changes should be consolidated | ||
17 | error messages as well as TCG -M virt supporting -smp > 8 automatically. | ||
18 | |||
19 | Signed-off-by: Alexander Graf <agraf@csgraf.de> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20230109140306.23161-4-philmd@linaro.org | 21 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> |
22 | Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> | ||
23 | Message-id: 20221223090107.98888-2-agraf@csgraf.de | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 25 | --- |
8 | hw/arm/omap1.c | 115 ++++++++++++++++++-------------------- | 26 | include/hw/arm/virt.h | 15 ++-- |
9 | hw/arm/omap2.c | 40 ++++++------- | 27 | hw/arm/virt.c | 198 ++++++++++++++++++++++-------------------- |
10 | hw/arm/omap_sx1.c | 2 +- | 28 | 2 files changed, 112 insertions(+), 101 deletions(-) |
11 | hw/arm/palm.c | 2 +- | 29 | |
12 | hw/char/omap_uart.c | 7 +-- | 30 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h |
13 | hw/display/omap_dss.c | 15 +++-- | ||
14 | hw/display/omap_lcdc.c | 9 ++- | ||
15 | hw/dma/omap_dma.c | 15 +++-- | ||
16 | hw/gpio/omap_gpio.c | 15 +++-- | ||
17 | hw/intc/omap_intc.c | 12 ++-- | ||
18 | hw/misc/omap_gpmc.c | 12 ++-- | ||
19 | hw/misc/omap_l4.c | 7 +-- | ||
20 | hw/misc/omap_sdrc.c | 7 +-- | ||
21 | hw/misc/omap_tap.c | 5 +- | ||
22 | hw/sd/omap_mmc.c | 9 ++- | ||
23 | hw/ssi/omap_spi.c | 7 +-- | ||
24 | hw/timer/omap_gptimer.c | 22 ++++---- | ||
25 | hw/timer/omap_synctimer.c | 4 +- | ||
26 | 18 files changed, 142 insertions(+), 163 deletions(-) | ||
27 | |||
28 | diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/omap1.c | 32 | --- a/include/hw/arm/virt.h |
31 | +++ b/hw/arm/omap1.c | 33 | +++ b/include/hw/arm/virt.h |
32 | @@ -XXX,XX +XXX,XX @@ static void omap_timer_fire(void *opaque) | 34 | @@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType { |
33 | 35 | } VirtMSIControllerType; | |
34 | static void omap_timer_tick(void *opaque) | 36 | |
35 | { | 37 | typedef enum VirtGICType { |
36 | - struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | 38 | - VIRT_GIC_VERSION_MAX, |
37 | + struct omap_mpu_timer_s *timer = opaque; | 39 | - VIRT_GIC_VERSION_HOST, |
38 | 40 | - VIRT_GIC_VERSION_2, | |
39 | omap_timer_sync(timer); | 41 | - VIRT_GIC_VERSION_3, |
40 | omap_timer_fire(timer); | 42 | - VIRT_GIC_VERSION_4, |
41 | @@ -XXX,XX +XXX,XX @@ static void omap_timer_tick(void *opaque) | 43 | + VIRT_GIC_VERSION_MAX = 0, |
42 | 44 | + VIRT_GIC_VERSION_HOST = 1, | |
43 | static void omap_timer_clk_update(void *opaque, int line, int on) | 45 | + /* The concrete GIC values have to match the GIC version number */ |
44 | { | 46 | + VIRT_GIC_VERSION_2 = 2, |
45 | - struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; | 47 | + VIRT_GIC_VERSION_3 = 3, |
46 | + struct omap_mpu_timer_s *timer = opaque; | 48 | + VIRT_GIC_VERSION_4 = 4, |
47 | 49 | VIRT_GIC_VERSION_NOSEL, | |
48 | omap_timer_sync(timer); | 50 | } VirtGICType; |
49 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; | 51 | |
50 | @@ -XXX,XX +XXX,XX @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) | 52 | +#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2) |
51 | static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, | 53 | +#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3) |
52 | unsigned size) | 54 | +#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4) |
53 | { | 55 | + |
54 | - struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | 56 | struct VirtMachineClass { |
55 | + struct omap_mpu_timer_s *s = opaque; | 57 | MachineClass parent; |
56 | 58 | bool disallow_affinity_adjustment; | |
57 | if (size != 4) { | 59 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
58 | return omap_badwidth_read32(opaque, addr); | 60 | index XXXXXXX..XXXXXXX 100644 |
59 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr, | 61 | --- a/hw/arm/virt.c |
60 | static void omap_mpu_timer_write(void *opaque, hwaddr addr, | 62 | +++ b/hw/arm/virt.c |
61 | uint64_t value, unsigned size) | 63 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits) |
62 | { | ||
63 | - struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; | ||
64 | + struct omap_mpu_timer_s *s = opaque; | ||
65 | |||
66 | if (size != 4) { | ||
67 | omap_badwidth_write32(opaque, addr, value); | ||
68 | @@ -XXX,XX +XXX,XX @@ struct omap_watchdog_timer_s { | ||
69 | static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, | ||
70 | unsigned size) | ||
71 | { | ||
72 | - struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | ||
73 | + struct omap_watchdog_timer_s *s = opaque; | ||
74 | |||
75 | if (size != 2) { | ||
76 | return omap_badwidth_read16(opaque, addr); | ||
77 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr, | ||
78 | static void omap_wd_timer_write(void *opaque, hwaddr addr, | ||
79 | uint64_t value, unsigned size) | ||
80 | { | ||
81 | - struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; | ||
82 | + struct omap_watchdog_timer_s *s = opaque; | ||
83 | |||
84 | if (size != 2) { | ||
85 | omap_badwidth_write16(opaque, addr, value); | ||
86 | @@ -XXX,XX +XXX,XX @@ struct omap_32khz_timer_s { | ||
87 | static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, | ||
88 | unsigned size) | ||
89 | { | ||
90 | - struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | ||
91 | + struct omap_32khz_timer_s *s = opaque; | ||
92 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
93 | |||
94 | if (size != 4) { | ||
95 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr, | ||
96 | static void omap_os_timer_write(void *opaque, hwaddr addr, | ||
97 | uint64_t value, unsigned size) | ||
98 | { | ||
99 | - struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; | ||
100 | + struct omap_32khz_timer_s *s = opaque; | ||
101 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
102 | |||
103 | if (size != 4) { | ||
104 | @@ -XXX,XX +XXX,XX @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory, | ||
105 | static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr, | ||
106 | unsigned size) | ||
107 | { | ||
108 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
109 | + struct omap_mpu_state_s *s = opaque; | ||
110 | uint16_t ret; | ||
111 | |||
112 | if (size != 2) { | ||
113 | @@ -XXX,XX +XXX,XX @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, | ||
114 | static void omap_ulpd_pm_write(void *opaque, hwaddr addr, | ||
115 | uint64_t value, unsigned size) | ||
116 | { | ||
117 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
118 | + struct omap_mpu_state_s *s = opaque; | ||
119 | int64_t now, ticks; | ||
120 | int div, mult; | ||
121 | static const int bypass_div[4] = { 1, 2, 4, 4 }; | ||
122 | @@ -XXX,XX +XXX,XX @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory, | ||
123 | static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr, | ||
124 | unsigned size) | ||
125 | { | ||
126 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
127 | + struct omap_mpu_state_s *s = opaque; | ||
128 | |||
129 | if (size != 4) { | ||
130 | return omap_badwidth_read32(opaque, addr); | ||
131 | @@ -XXX,XX +XXX,XX @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, | ||
132 | static void omap_pin_cfg_write(void *opaque, hwaddr addr, | ||
133 | uint64_t value, unsigned size) | ||
134 | { | ||
135 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
136 | + struct omap_mpu_state_s *s = opaque; | ||
137 | uint32_t diff; | ||
138 | |||
139 | if (size != 4) { | ||
140 | @@ -XXX,XX +XXX,XX @@ static void omap_pin_cfg_init(MemoryRegion *system_memory, | ||
141 | static uint64_t omap_id_read(void *opaque, hwaddr addr, | ||
142 | unsigned size) | ||
143 | { | ||
144 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
145 | + struct omap_mpu_state_s *s = opaque; | ||
146 | |||
147 | if (size != 4) { | ||
148 | return omap_badwidth_read32(opaque, addr); | ||
149 | @@ -XXX,XX +XXX,XX @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu) | ||
150 | static uint64_t omap_mpui_read(void *opaque, hwaddr addr, | ||
151 | unsigned size) | ||
152 | { | ||
153 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
154 | + struct omap_mpu_state_s *s = opaque; | ||
155 | |||
156 | if (size != 4) { | ||
157 | return omap_badwidth_read32(opaque, addr); | ||
158 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr, | ||
159 | static void omap_mpui_write(void *opaque, hwaddr addr, | ||
160 | uint64_t value, unsigned size) | ||
161 | { | ||
162 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
163 | + struct omap_mpu_state_s *s = opaque; | ||
164 | |||
165 | if (size != 4) { | ||
166 | omap_badwidth_write32(opaque, addr, value); | ||
167 | @@ -XXX,XX +XXX,XX @@ struct omap_tipb_bridge_s { | ||
168 | static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, | ||
169 | unsigned size) | ||
170 | { | ||
171 | - struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | ||
172 | + struct omap_tipb_bridge_s *s = opaque; | ||
173 | |||
174 | if (size < 2) { | ||
175 | return omap_badwidth_read16(opaque, addr); | ||
176 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr, | ||
177 | static void omap_tipb_bridge_write(void *opaque, hwaddr addr, | ||
178 | uint64_t value, unsigned size) | ||
179 | { | ||
180 | - struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; | ||
181 | + struct omap_tipb_bridge_s *s = opaque; | ||
182 | |||
183 | if (size < 2) { | ||
184 | omap_badwidth_write16(opaque, addr, value); | ||
185 | @@ -XXX,XX +XXX,XX @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init( | ||
186 | static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, | ||
187 | unsigned size) | ||
188 | { | ||
189 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
190 | + struct omap_mpu_state_s *s = opaque; | ||
191 | uint32_t ret; | ||
192 | |||
193 | if (size != 4) { | ||
194 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr, | ||
195 | static void omap_tcmi_write(void *opaque, hwaddr addr, | ||
196 | uint64_t value, unsigned size) | ||
197 | { | ||
198 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
199 | + struct omap_mpu_state_s *s = opaque; | ||
200 | |||
201 | if (size != 4) { | ||
202 | omap_badwidth_write32(opaque, addr, value); | ||
203 | @@ -XXX,XX +XXX,XX @@ struct dpll_ctl_s { | ||
204 | static uint64_t omap_dpll_read(void *opaque, hwaddr addr, | ||
205 | unsigned size) | ||
206 | { | ||
207 | - struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | ||
208 | + struct dpll_ctl_s *s = opaque; | ||
209 | |||
210 | if (size != 2) { | ||
211 | return omap_badwidth_read16(opaque, addr); | ||
212 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr, | ||
213 | static void omap_dpll_write(void *opaque, hwaddr addr, | ||
214 | uint64_t value, unsigned size) | ||
215 | { | ||
216 | - struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; | ||
217 | + struct dpll_ctl_s *s = opaque; | ||
218 | uint16_t diff; | ||
219 | static const int bypass_div[4] = { 1, 2, 4, 4 }; | ||
220 | int div, mult; | ||
221 | @@ -XXX,XX +XXX,XX @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory, | ||
222 | static uint64_t omap_clkm_read(void *opaque, hwaddr addr, | ||
223 | unsigned size) | ||
224 | { | ||
225 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
226 | + struct omap_mpu_state_s *s = opaque; | ||
227 | |||
228 | if (size != 2) { | ||
229 | return omap_badwidth_read16(opaque, addr); | ||
230 | @@ -XXX,XX +XXX,XX @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, | ||
231 | static void omap_clkm_write(void *opaque, hwaddr addr, | ||
232 | uint64_t value, unsigned size) | ||
233 | { | ||
234 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
235 | + struct omap_mpu_state_s *s = opaque; | ||
236 | uint16_t diff; | ||
237 | omap_clk clk; | ||
238 | static const char *clkschemename[8] = { | ||
239 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_clkm_ops = { | ||
240 | static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, | ||
241 | unsigned size) | ||
242 | { | ||
243 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
244 | + struct omap_mpu_state_s *s = opaque; | ||
245 | CPUState *cpu = CPU(s->cpu); | ||
246 | |||
247 | if (size != 2) { | ||
248 | @@ -XXX,XX +XXX,XX @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, | ||
249 | static void omap_clkdsp_write(void *opaque, hwaddr addr, | ||
250 | uint64_t value, unsigned size) | ||
251 | { | ||
252 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
253 | + struct omap_mpu_state_s *s = opaque; | ||
254 | uint16_t diff; | ||
255 | |||
256 | if (size != 2) { | ||
257 | @@ -XXX,XX +XXX,XX @@ struct omap_mpuio_s { | ||
258 | |||
259 | static void omap_mpuio_set(void *opaque, int line, int level) | ||
260 | { | ||
261 | - struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | ||
262 | + struct omap_mpuio_s *s = opaque; | ||
263 | uint16_t prev = s->inputs; | ||
264 | |||
265 | if (level) | ||
266 | @@ -XXX,XX +XXX,XX @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) | ||
267 | static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, | ||
268 | unsigned size) | ||
269 | { | ||
270 | - struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | ||
271 | + struct omap_mpuio_s *s = opaque; | ||
272 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
273 | uint16_t ret; | ||
274 | |||
275 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr, | ||
276 | static void omap_mpuio_write(void *opaque, hwaddr addr, | ||
277 | uint64_t value, unsigned size) | ||
278 | { | ||
279 | - struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | ||
280 | + struct omap_mpuio_s *s = opaque; | ||
281 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
282 | uint16_t diff; | ||
283 | int ln; | ||
284 | @@ -XXX,XX +XXX,XX @@ static void omap_mpuio_reset(struct omap_mpuio_s *s) | ||
285 | |||
286 | static void omap_mpuio_onoff(void *opaque, int line, int on) | ||
287 | { | ||
288 | - struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; | ||
289 | + struct omap_mpuio_s *s = opaque; | ||
290 | |||
291 | s->clk = on; | ||
292 | if (on) | ||
293 | @@ -XXX,XX +XXX,XX @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s) | ||
294 | } | 64 | } |
295 | } | 65 | } |
296 | 66 | ||
297 | -static uint64_t omap_uwire_read(void *opaque, hwaddr addr, | 67 | +static VirtGICType finalize_gic_version_do(const char *accel_name, |
298 | - unsigned size) | 68 | + VirtGICType gic_version, |
299 | +static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size) | 69 | + int gics_supported, |
70 | + unsigned int max_cpus) | ||
71 | +{ | ||
72 | + /* Convert host/max/nosel to GIC version number */ | ||
73 | + switch (gic_version) { | ||
74 | + case VIRT_GIC_VERSION_HOST: | ||
75 | + if (!kvm_enabled()) { | ||
76 | + error_report("gic-version=host requires KVM"); | ||
77 | + exit(1); | ||
78 | + } | ||
79 | + | ||
80 | + /* For KVM, gic-version=host means gic-version=max */ | ||
81 | + return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX, | ||
82 | + gics_supported, max_cpus); | ||
83 | + case VIRT_GIC_VERSION_MAX: | ||
84 | + if (gics_supported & VIRT_GIC_VERSION_4_MASK) { | ||
85 | + gic_version = VIRT_GIC_VERSION_4; | ||
86 | + } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { | ||
87 | + gic_version = VIRT_GIC_VERSION_3; | ||
88 | + } else { | ||
89 | + gic_version = VIRT_GIC_VERSION_2; | ||
90 | + } | ||
91 | + break; | ||
92 | + case VIRT_GIC_VERSION_NOSEL: | ||
93 | + if ((gics_supported & VIRT_GIC_VERSION_2_MASK) && | ||
94 | + max_cpus <= GIC_NCPU) { | ||
95 | + gic_version = VIRT_GIC_VERSION_2; | ||
96 | + } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) { | ||
97 | + /* | ||
98 | + * in case the host does not support v2 emulation or | ||
99 | + * the end-user requested more than 8 VCPUs we now default | ||
100 | + * to v3. In any case defaulting to v2 would be broken. | ||
101 | + */ | ||
102 | + gic_version = VIRT_GIC_VERSION_3; | ||
103 | + } else if (max_cpus > GIC_NCPU) { | ||
104 | + error_report("%s only supports GICv2 emulation but more than 8 " | ||
105 | + "vcpus are requested", accel_name); | ||
106 | + exit(1); | ||
107 | + } | ||
108 | + break; | ||
109 | + case VIRT_GIC_VERSION_2: | ||
110 | + case VIRT_GIC_VERSION_3: | ||
111 | + case VIRT_GIC_VERSION_4: | ||
112 | + break; | ||
113 | + } | ||
114 | + | ||
115 | + /* Check chosen version is effectively supported */ | ||
116 | + switch (gic_version) { | ||
117 | + case VIRT_GIC_VERSION_2: | ||
118 | + if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) { | ||
119 | + error_report("%s does not support GICv2 emulation", accel_name); | ||
120 | + exit(1); | ||
121 | + } | ||
122 | + break; | ||
123 | + case VIRT_GIC_VERSION_3: | ||
124 | + if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) { | ||
125 | + error_report("%s does not support GICv3 emulation", accel_name); | ||
126 | + exit(1); | ||
127 | + } | ||
128 | + break; | ||
129 | + case VIRT_GIC_VERSION_4: | ||
130 | + if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) { | ||
131 | + error_report("%s does not support GICv4 emulation, is virtualization=on?", | ||
132 | + accel_name); | ||
133 | + exit(1); | ||
134 | + } | ||
135 | + break; | ||
136 | + default: | ||
137 | + error_report("logic error in finalize_gic_version"); | ||
138 | + exit(1); | ||
139 | + break; | ||
140 | + } | ||
141 | + | ||
142 | + return gic_version; | ||
143 | +} | ||
144 | + | ||
145 | /* | ||
146 | * finalize_gic_version - Determines the final gic_version | ||
147 | * according to the gic-version property | ||
148 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits) | ||
149 | */ | ||
150 | static void finalize_gic_version(VirtMachineState *vms) | ||
300 | { | 151 | { |
301 | - struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | 152 | + const char *accel_name = current_accel_name(); |
302 | + struct omap_uwire_s *s = opaque; | 153 | unsigned int max_cpus = MACHINE(vms)->smp.max_cpus; |
303 | int offset = addr & OMAP_MPUI_REG_MASK; | 154 | + int gics_supported = 0; |
304 | 155 | ||
305 | if (size != 2) { | 156 | - if (kvm_enabled()) { |
306 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr, | 157 | - int probe_bitmap; |
307 | static void omap_uwire_write(void *opaque, hwaddr addr, | 158 | + /* Determine which GIC versions the current environment supports */ |
308 | uint64_t value, unsigned size) | 159 | + if (kvm_enabled() && kvm_irqchip_in_kernel()) { |
309 | { | 160 | + int probe_bitmap = kvm_arm_vgic_probe(); |
310 | - struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; | 161 | |
311 | + struct omap_uwire_s *s = opaque; | 162 | - if (!kvm_irqchip_in_kernel()) { |
312 | int offset = addr & OMAP_MPUI_REG_MASK; | 163 | - switch (vms->gic_version) { |
313 | 164 | - case VIRT_GIC_VERSION_HOST: | |
314 | if (size != 2) { | 165 | - warn_report( |
315 | @@ -XXX,XX +XXX,XX @@ static void omap_pwl_update(struct omap_pwl_s *s) | 166 | - "gic-version=host not relevant with kernel-irqchip=off " |
167 | - "as only userspace GICv2 is supported. Using v2 ..."); | ||
168 | - return; | ||
169 | - case VIRT_GIC_VERSION_MAX: | ||
170 | - case VIRT_GIC_VERSION_NOSEL: | ||
171 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
172 | - return; | ||
173 | - case VIRT_GIC_VERSION_2: | ||
174 | - return; | ||
175 | - case VIRT_GIC_VERSION_3: | ||
176 | - error_report( | ||
177 | - "gic-version=3 is not supported with kernel-irqchip=off"); | ||
178 | - exit(1); | ||
179 | - case VIRT_GIC_VERSION_4: | ||
180 | - error_report( | ||
181 | - "gic-version=4 is not supported with kernel-irqchip=off"); | ||
182 | - exit(1); | ||
183 | - } | ||
184 | - } | ||
185 | - | ||
186 | - probe_bitmap = kvm_arm_vgic_probe(); | ||
187 | if (!probe_bitmap) { | ||
188 | error_report("Unable to determine GIC version supported by host"); | ||
189 | exit(1); | ||
190 | } | ||
191 | |||
192 | - switch (vms->gic_version) { | ||
193 | - case VIRT_GIC_VERSION_HOST: | ||
194 | - case VIRT_GIC_VERSION_MAX: | ||
195 | - if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
196 | - vms->gic_version = VIRT_GIC_VERSION_3; | ||
197 | - } else { | ||
198 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
199 | - } | ||
200 | - return; | ||
201 | - case VIRT_GIC_VERSION_NOSEL: | ||
202 | - if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) { | ||
203 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
204 | - } else if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
205 | - /* | ||
206 | - * in case the host does not support v2 in-kernel emulation or | ||
207 | - * the end-user requested more than 8 VCPUs we now default | ||
208 | - * to v3. In any case defaulting to v2 would be broken. | ||
209 | - */ | ||
210 | - vms->gic_version = VIRT_GIC_VERSION_3; | ||
211 | - } else if (max_cpus > GIC_NCPU) { | ||
212 | - error_report("host only supports in-kernel GICv2 emulation " | ||
213 | - "but more than 8 vcpus are requested"); | ||
214 | - exit(1); | ||
215 | - } | ||
216 | - break; | ||
217 | - case VIRT_GIC_VERSION_2: | ||
218 | - case VIRT_GIC_VERSION_3: | ||
219 | - break; | ||
220 | - case VIRT_GIC_VERSION_4: | ||
221 | - error_report("gic-version=4 is not supported with KVM"); | ||
222 | - exit(1); | ||
223 | + if (probe_bitmap & KVM_ARM_VGIC_V2) { | ||
224 | + gics_supported |= VIRT_GIC_VERSION_2_MASK; | ||
225 | } | ||
226 | - | ||
227 | - /* Check chosen version is effectively supported by the host */ | ||
228 | - if (vms->gic_version == VIRT_GIC_VERSION_2 && | ||
229 | - !(probe_bitmap & KVM_ARM_VGIC_V2)) { | ||
230 | - error_report("host does not support in-kernel GICv2 emulation"); | ||
231 | - exit(1); | ||
232 | - } else if (vms->gic_version == VIRT_GIC_VERSION_3 && | ||
233 | - !(probe_bitmap & KVM_ARM_VGIC_V3)) { | ||
234 | - error_report("host does not support in-kernel GICv3 emulation"); | ||
235 | - exit(1); | ||
236 | + if (probe_bitmap & KVM_ARM_VGIC_V3) { | ||
237 | + gics_supported |= VIRT_GIC_VERSION_3_MASK; | ||
238 | } | ||
239 | - return; | ||
240 | - } | ||
241 | - | ||
242 | - /* TCG mode */ | ||
243 | - switch (vms->gic_version) { | ||
244 | - case VIRT_GIC_VERSION_NOSEL: | ||
245 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
246 | - break; | ||
247 | - case VIRT_GIC_VERSION_MAX: | ||
248 | + } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) { | ||
249 | + /* KVM w/o kernel irqchip can only deal with GICv2 */ | ||
250 | + gics_supported |= VIRT_GIC_VERSION_2_MASK; | ||
251 | + accel_name = "KVM with kernel-irqchip=off"; | ||
252 | + } else { | ||
253 | + gics_supported |= VIRT_GIC_VERSION_2_MASK; | ||
254 | if (module_object_class_by_name("arm-gicv3")) { | ||
255 | - /* CONFIG_ARM_GICV3_TCG was set */ | ||
256 | + gics_supported |= VIRT_GIC_VERSION_3_MASK; | ||
257 | if (vms->virt) { | ||
258 | /* GICv4 only makes sense if CPU has EL2 */ | ||
259 | - vms->gic_version = VIRT_GIC_VERSION_4; | ||
260 | - } else { | ||
261 | - vms->gic_version = VIRT_GIC_VERSION_3; | ||
262 | + gics_supported |= VIRT_GIC_VERSION_4_MASK; | ||
263 | } | ||
264 | - } else { | ||
265 | - vms->gic_version = VIRT_GIC_VERSION_2; | ||
266 | } | ||
267 | - break; | ||
268 | - case VIRT_GIC_VERSION_HOST: | ||
269 | - error_report("gic-version=host requires KVM"); | ||
270 | - exit(1); | ||
271 | - case VIRT_GIC_VERSION_4: | ||
272 | - if (!vms->virt) { | ||
273 | - error_report("gic-version=4 requires virtualization enabled"); | ||
274 | - exit(1); | ||
275 | - } | ||
276 | - break; | ||
277 | - case VIRT_GIC_VERSION_2: | ||
278 | - case VIRT_GIC_VERSION_3: | ||
279 | - break; | ||
316 | } | 280 | } |
281 | + | ||
282 | + /* | ||
283 | + * Then convert helpers like host/max to concrete GIC versions and ensure | ||
284 | + * the desired version is supported | ||
285 | + */ | ||
286 | + vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version, | ||
287 | + gics_supported, max_cpus); | ||
317 | } | 288 | } |
318 | 289 | ||
319 | -static uint64_t omap_pwl_read(void *opaque, hwaddr addr, | 290 | /* |
320 | - unsigned size) | ||
321 | +static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size) | ||
322 | { | ||
323 | - struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; | ||
324 | + struct omap_pwl_s *s = opaque; | ||
325 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
326 | |||
327 | if (size != 1) { | ||
328 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr, | ||
329 | static void omap_pwl_write(void *opaque, hwaddr addr, | ||
330 | uint64_t value, unsigned size) | ||
331 | { | ||
332 | - struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; | ||
333 | + struct omap_pwl_s *s = opaque; | ||
334 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
335 | |||
336 | if (size != 1) { | ||
337 | @@ -XXX,XX +XXX,XX @@ static void omap_pwl_reset(struct omap_pwl_s *s) | ||
338 | |||
339 | static void omap_pwl_clk_update(void *opaque, int line, int on) | ||
340 | { | ||
341 | - struct omap_pwl_s *s = (struct omap_pwl_s *) opaque; | ||
342 | + struct omap_pwl_s *s = opaque; | ||
343 | |||
344 | s->clk = on; | ||
345 | omap_pwl_update(s); | ||
346 | @@ -XXX,XX +XXX,XX @@ struct omap_pwt_s { | ||
347 | omap_clk clk; | ||
348 | }; | ||
349 | |||
350 | -static uint64_t omap_pwt_read(void *opaque, hwaddr addr, | ||
351 | - unsigned size) | ||
352 | +static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size) | ||
353 | { | ||
354 | - struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; | ||
355 | + struct omap_pwt_s *s = opaque; | ||
356 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
357 | |||
358 | if (size != 1) { | ||
359 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr, | ||
360 | static void omap_pwt_write(void *opaque, hwaddr addr, | ||
361 | uint64_t value, unsigned size) | ||
362 | { | ||
363 | - struct omap_pwt_s *s = (struct omap_pwt_s *) opaque; | ||
364 | + struct omap_pwt_s *s = opaque; | ||
365 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
366 | |||
367 | if (size != 1) { | ||
368 | @@ -XXX,XX +XXX,XX @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s) | ||
369 | printf("%s: conversion failed\n", __func__); | ||
370 | } | ||
371 | |||
372 | -static uint64_t omap_rtc_read(void *opaque, hwaddr addr, | ||
373 | - unsigned size) | ||
374 | +static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size) | ||
375 | { | ||
376 | - struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | ||
377 | + struct omap_rtc_s *s = opaque; | ||
378 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
379 | uint8_t i; | ||
380 | |||
381 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr, | ||
382 | static void omap_rtc_write(void *opaque, hwaddr addr, | ||
383 | uint64_t value, unsigned size) | ||
384 | { | ||
385 | - struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; | ||
386 | + struct omap_rtc_s *s = opaque; | ||
387 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
388 | struct tm new_tm; | ||
389 | time_t ti[2]; | ||
390 | @@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) | ||
391 | |||
392 | static void omap_mcbsp_source_tick(void *opaque) | ||
393 | { | ||
394 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
395 | + struct omap_mcbsp_s *s = opaque; | ||
396 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | ||
397 | |||
398 | if (!s->rx_rate) | ||
399 | @@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) | ||
400 | |||
401 | static void omap_mcbsp_sink_tick(void *opaque) | ||
402 | { | ||
403 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
404 | + struct omap_mcbsp_s *s = opaque; | ||
405 | static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; | ||
406 | |||
407 | if (!s->tx_rate) | ||
408 | @@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) | ||
409 | static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, | ||
410 | unsigned size) | ||
411 | { | ||
412 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
413 | + struct omap_mcbsp_s *s = opaque; | ||
414 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
415 | uint16_t ret; | ||
416 | |||
417 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr, | ||
418 | static void omap_mcbsp_writeh(void *opaque, hwaddr addr, | ||
419 | uint32_t value) | ||
420 | { | ||
421 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
422 | + struct omap_mcbsp_s *s = opaque; | ||
423 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
424 | |||
425 | switch (offset) { | ||
426 | @@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr, | ||
427 | static void omap_mcbsp_writew(void *opaque, hwaddr addr, | ||
428 | uint32_t value) | ||
429 | { | ||
430 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
431 | + struct omap_mcbsp_s *s = opaque; | ||
432 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
433 | |||
434 | if (offset == 0x04) { /* DXR */ | ||
435 | @@ -XXX,XX +XXX,XX @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory, | ||
436 | |||
437 | static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) | ||
438 | { | ||
439 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
440 | + struct omap_mcbsp_s *s = opaque; | ||
441 | |||
442 | if (s->rx_rate) { | ||
443 | s->rx_req = s->codec->in.len; | ||
444 | @@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) | ||
445 | |||
446 | static void omap_mcbsp_i2s_start(void *opaque, int line, int level) | ||
447 | { | ||
448 | - struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; | ||
449 | + struct omap_mcbsp_s *s = opaque; | ||
450 | |||
451 | if (s->tx_rate) { | ||
452 | s->tx_req = s->codec->out.size; | ||
453 | @@ -XXX,XX +XXX,XX @@ static void omap_lpg_reset(struct omap_lpg_s *s) | ||
454 | omap_lpg_update(s); | ||
455 | } | ||
456 | |||
457 | -static uint64_t omap_lpg_read(void *opaque, hwaddr addr, | ||
458 | - unsigned size) | ||
459 | +static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size) | ||
460 | { | ||
461 | - struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | ||
462 | + struct omap_lpg_s *s = opaque; | ||
463 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
464 | |||
465 | if (size != 1) { | ||
466 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr, | ||
467 | static void omap_lpg_write(void *opaque, hwaddr addr, | ||
468 | uint64_t value, unsigned size) | ||
469 | { | ||
470 | - struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | ||
471 | + struct omap_lpg_s *s = opaque; | ||
472 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
473 | |||
474 | if (size != 1) { | ||
475 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_lpg_ops = { | ||
476 | |||
477 | static void omap_lpg_clk_update(void *opaque, int line, int on) | ||
478 | { | ||
479 | - struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; | ||
480 | + struct omap_lpg_s *s = opaque; | ||
481 | |||
482 | s->clk = on; | ||
483 | omap_lpg_update(s); | ||
484 | @@ -XXX,XX +XXX,XX @@ static void omap_setup_mpui_io(MemoryRegion *system_memory, | ||
485 | /* General chip reset */ | ||
486 | static void omap1_mpu_reset(void *opaque) | ||
487 | { | ||
488 | - struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | ||
489 | + struct omap_mpu_state_s *mpu = opaque; | ||
490 | |||
491 | omap_dma_reset(mpu->dma); | ||
492 | omap_mpu_timer_reset(mpu->timer[0]); | ||
493 | @@ -XXX,XX +XXX,XX @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory, | ||
494 | |||
495 | void omap_mpu_wakeup(void *opaque, int irq, int req) | ||
496 | { | ||
497 | - struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | ||
498 | + struct omap_mpu_state_s *mpu = opaque; | ||
499 | CPUState *cpu = CPU(mpu->cpu); | ||
500 | |||
501 | if (cpu->halted) { | ||
502 | diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c | ||
503 | index XXXXXXX..XXXXXXX 100644 | ||
504 | --- a/hw/arm/omap2.c | ||
505 | +++ b/hw/arm/omap2.c | ||
506 | @@ -XXX,XX +XXX,XX @@ static inline void omap_eac_out_empty(struct omap_eac_s *s) | ||
507 | |||
508 | static void omap_eac_in_cb(void *opaque, int avail_b) | ||
509 | { | ||
510 | - struct omap_eac_s *s = (struct omap_eac_s *) opaque; | ||
511 | + struct omap_eac_s *s = opaque; | ||
512 | |||
513 | s->codec.rxavail = avail_b >> 2; | ||
514 | omap_eac_in_refill(s); | ||
515 | @@ -XXX,XX +XXX,XX @@ static void omap_eac_in_cb(void *opaque, int avail_b) | ||
516 | |||
517 | static void omap_eac_out_cb(void *opaque, int free_b) | ||
518 | { | ||
519 | - struct omap_eac_s *s = (struct omap_eac_s *) opaque; | ||
520 | + struct omap_eac_s *s = opaque; | ||
521 | |||
522 | s->codec.txavail = free_b >> 2; | ||
523 | if (s->codec.txlen) | ||
524 | @@ -XXX,XX +XXX,XX @@ static void omap_eac_reset(struct omap_eac_s *s) | ||
525 | omap_eac_interrupt_update(s); | ||
526 | } | ||
527 | |||
528 | -static uint64_t omap_eac_read(void *opaque, hwaddr addr, | ||
529 | - unsigned size) | ||
530 | +static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size) | ||
531 | { | ||
532 | - struct omap_eac_s *s = (struct omap_eac_s *) opaque; | ||
533 | + struct omap_eac_s *s = opaque; | ||
534 | uint32_t ret; | ||
535 | |||
536 | if (size != 2) { | ||
537 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr, | ||
538 | static void omap_eac_write(void *opaque, hwaddr addr, | ||
539 | uint64_t value, unsigned size) | ||
540 | { | ||
541 | - struct omap_eac_s *s = (struct omap_eac_s *) opaque; | ||
542 | + struct omap_eac_s *s = opaque; | ||
543 | |||
544 | if (size != 2) { | ||
545 | omap_badwidth_write16(opaque, addr, value); | ||
546 | @@ -XXX,XX +XXX,XX @@ static void omap_sti_reset(struct omap_sti_s *s) | ||
547 | static uint64_t omap_sti_read(void *opaque, hwaddr addr, | ||
548 | unsigned size) | ||
549 | { | ||
550 | - struct omap_sti_s *s = (struct omap_sti_s *) opaque; | ||
551 | + struct omap_sti_s *s = opaque; | ||
552 | |||
553 | if (size != 4) { | ||
554 | return omap_badwidth_read32(opaque, addr); | ||
555 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr, | ||
556 | static void omap_sti_write(void *opaque, hwaddr addr, | ||
557 | uint64_t value, unsigned size) | ||
558 | { | ||
559 | - struct omap_sti_s *s = (struct omap_sti_s *) opaque; | ||
560 | + struct omap_sti_s *s = opaque; | ||
561 | |||
562 | if (size != 4) { | ||
563 | omap_badwidth_write32(opaque, addr, value); | ||
564 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_sti_ops = { | ||
565 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
566 | }; | ||
567 | |||
568 | -static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, | ||
569 | - unsigned size) | ||
570 | +static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size) | ||
571 | { | ||
572 | OMAP_BAD_REG(addr); | ||
573 | return 0; | ||
574 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, | ||
575 | static void omap_sti_fifo_write(void *opaque, hwaddr addr, | ||
576 | uint64_t value, unsigned size) | ||
577 | { | ||
578 | - struct omap_sti_s *s = (struct omap_sti_s *) opaque; | ||
579 | + struct omap_sti_s *s = opaque; | ||
580 | int ch = addr >> 6; | ||
581 | uint8_t byte = value; | ||
582 | |||
583 | @@ -XXX,XX +XXX,XX @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom) | ||
584 | static uint64_t omap_prcm_read(void *opaque, hwaddr addr, | ||
585 | unsigned size) | ||
586 | { | ||
587 | - struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; | ||
588 | + struct omap_prcm_s *s = opaque; | ||
589 | uint32_t ret; | ||
590 | |||
591 | if (size != 4) { | ||
592 | @@ -XXX,XX +XXX,XX @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s) | ||
593 | static void omap_prcm_write(void *opaque, hwaddr addr, | ||
594 | uint64_t value, unsigned size) | ||
595 | { | ||
596 | - struct omap_prcm_s *s = (struct omap_prcm_s *) opaque; | ||
597 | + struct omap_prcm_s *s = opaque; | ||
598 | |||
599 | if (size != 4) { | ||
600 | omap_badwidth_write32(opaque, addr, value); | ||
601 | @@ -XXX,XX +XXX,XX @@ struct omap_sysctl_s { | ||
602 | static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr) | ||
603 | { | ||
604 | |||
605 | - struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | ||
606 | + struct omap_sysctl_s *s = opaque; | ||
607 | int pad_offset, byte_offset; | ||
608 | int value; | ||
609 | |||
610 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr) | ||
611 | |||
612 | static uint32_t omap_sysctl_read(void *opaque, hwaddr addr) | ||
613 | { | ||
614 | - struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | ||
615 | + struct omap_sysctl_s *s = opaque; | ||
616 | |||
617 | switch (addr) { | ||
618 | case 0x000: /* CONTROL_REVISION */ | ||
619 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr) | ||
620 | return 0; | ||
621 | } | ||
622 | |||
623 | -static void omap_sysctl_write8(void *opaque, hwaddr addr, | ||
624 | - uint32_t value) | ||
625 | +static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value) | ||
626 | { | ||
627 | - struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | ||
628 | + struct omap_sysctl_s *s = opaque; | ||
629 | int pad_offset, byte_offset; | ||
630 | int prev_value; | ||
631 | |||
632 | @@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write8(void *opaque, hwaddr addr, | ||
633 | } | ||
634 | } | ||
635 | |||
636 | -static void omap_sysctl_write(void *opaque, hwaddr addr, | ||
637 | - uint32_t value) | ||
638 | +static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value) | ||
639 | { | ||
640 | - struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque; | ||
641 | + struct omap_sysctl_s *s = opaque; | ||
642 | |||
643 | switch (addr) { | ||
644 | case 0x000: /* CONTROL_REVISION */ | ||
645 | @@ -XXX,XX +XXX,XX @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, | ||
646 | /* General chip reset */ | ||
647 | static void omap2_mpu_reset(void *opaque) | ||
648 | { | ||
649 | - struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; | ||
650 | + struct omap_mpu_state_s *mpu = opaque; | ||
651 | |||
652 | omap_dma_reset(mpu->dma); | ||
653 | omap_prcm_reset(mpu->prcm); | ||
654 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
655 | index XXXXXXX..XXXXXXX 100644 | ||
656 | --- a/hw/arm/omap_sx1.c | ||
657 | +++ b/hw/arm/omap_sx1.c | ||
658 | @@ -XXX,XX +XXX,XX @@ | ||
659 | static uint64_t static_read(void *opaque, hwaddr offset, | ||
660 | unsigned size) | ||
661 | { | ||
662 | - uint32_t *val = (uint32_t *) opaque; | ||
663 | + uint32_t *val = opaque; | ||
664 | uint32_t mask = (4 / size) - 1; | ||
665 | |||
666 | return *val >> ((offset & mask) << 3); | ||
667 | diff --git a/hw/arm/palm.c b/hw/arm/palm.c | ||
668 | index XXXXXXX..XXXXXXX 100644 | ||
669 | --- a/hw/arm/palm.c | ||
670 | +++ b/hw/arm/palm.c | ||
671 | @@ -XXX,XX +XXX,XX @@ static struct { | ||
672 | |||
673 | static void palmte_button_event(void *opaque, int keycode) | ||
674 | { | ||
675 | - struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque; | ||
676 | + struct omap_mpu_state_s *cpu = opaque; | ||
677 | |||
678 | if (palmte_keymap[keycode & 0x7f].row != -1) | ||
679 | omap_mpuio_key(cpu->mpuio, | ||
680 | diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c | ||
681 | index XXXXXXX..XXXXXXX 100644 | ||
682 | --- a/hw/char/omap_uart.c | ||
683 | +++ b/hw/char/omap_uart.c | ||
684 | @@ -XXX,XX +XXX,XX @@ struct omap_uart_s *omap_uart_init(hwaddr base, | ||
685 | return s; | ||
686 | } | ||
687 | |||
688 | -static uint64_t omap_uart_read(void *opaque, hwaddr addr, | ||
689 | - unsigned size) | ||
690 | +static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size) | ||
691 | { | ||
692 | - struct omap_uart_s *s = (struct omap_uart_s *) opaque; | ||
693 | + struct omap_uart_s *s = opaque; | ||
694 | |||
695 | if (size == 4) { | ||
696 | return omap_badwidth_read8(opaque, addr); | ||
697 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr, | ||
698 | static void omap_uart_write(void *opaque, hwaddr addr, | ||
699 | uint64_t value, unsigned size) | ||
700 | { | ||
701 | - struct omap_uart_s *s = (struct omap_uart_s *) opaque; | ||
702 | + struct omap_uart_s *s = opaque; | ||
703 | |||
704 | if (size == 4) { | ||
705 | omap_badwidth_write8(opaque, addr, value); | ||
706 | diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c | ||
707 | index XXXXXXX..XXXXXXX 100644 | ||
708 | --- a/hw/display/omap_dss.c | ||
709 | +++ b/hw/display/omap_dss.c | ||
710 | @@ -XXX,XX +XXX,XX @@ void omap_dss_reset(struct omap_dss_s *s) | ||
711 | static uint64_t omap_diss_read(void *opaque, hwaddr addr, | ||
712 | unsigned size) | ||
713 | { | ||
714 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
715 | + struct omap_dss_s *s = opaque; | ||
716 | |||
717 | if (size != 4) { | ||
718 | return omap_badwidth_read32(opaque, addr); | ||
719 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr, | ||
720 | static void omap_diss_write(void *opaque, hwaddr addr, | ||
721 | uint64_t value, unsigned size) | ||
722 | { | ||
723 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
724 | + struct omap_dss_s *s = opaque; | ||
725 | |||
726 | if (size != 4) { | ||
727 | omap_badwidth_write32(opaque, addr, value); | ||
728 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_diss_ops = { | ||
729 | static uint64_t omap_disc_read(void *opaque, hwaddr addr, | ||
730 | unsigned size) | ||
731 | { | ||
732 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
733 | + struct omap_dss_s *s = opaque; | ||
734 | |||
735 | if (size != 4) { | ||
736 | return omap_badwidth_read32(opaque, addr); | ||
737 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr, | ||
738 | static void omap_disc_write(void *opaque, hwaddr addr, | ||
739 | uint64_t value, unsigned size) | ||
740 | { | ||
741 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
742 | + struct omap_dss_s *s = opaque; | ||
743 | |||
744 | if (size != 4) { | ||
745 | omap_badwidth_write32(opaque, addr, value); | ||
746 | @@ -XXX,XX +XXX,XX @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) | ||
747 | omap_dispc_interrupt_update(s); | ||
748 | } | ||
749 | |||
750 | -static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, | ||
751 | - unsigned size) | ||
752 | +static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size) | ||
753 | { | ||
754 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
755 | + struct omap_dss_s *s = opaque; | ||
756 | |||
757 | if (size != 4) { | ||
758 | return omap_badwidth_read32(opaque, addr); | ||
759 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, | ||
760 | static void omap_rfbi_write(void *opaque, hwaddr addr, | ||
761 | uint64_t value, unsigned size) | ||
762 | { | ||
763 | - struct omap_dss_s *s = (struct omap_dss_s *) opaque; | ||
764 | + struct omap_dss_s *s = opaque; | ||
765 | |||
766 | if (size != 4) { | ||
767 | omap_badwidth_write32(opaque, addr, value); | ||
768 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c | ||
769 | index XXXXXXX..XXXXXXX 100644 | ||
770 | --- a/hw/display/omap_lcdc.c | ||
771 | +++ b/hw/display/omap_lcdc.c | ||
772 | @@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s, | ||
773 | |||
774 | static void omap_update_display(void *opaque) | ||
775 | { | ||
776 | - struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; | ||
777 | + struct omap_lcd_panel_s *omap_lcd = opaque; | ||
778 | DisplaySurface *surface; | ||
779 | drawfn draw_line; | ||
780 | int size, height, first, last; | ||
781 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) { | ||
782 | } | ||
783 | } | ||
784 | |||
785 | -static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, | ||
786 | - unsigned size) | ||
787 | +static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size) | ||
788 | { | ||
789 | - struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; | ||
790 | + struct omap_lcd_panel_s *s = opaque; | ||
791 | |||
792 | switch (addr) { | ||
793 | case 0x00: /* LCD_CONTROL */ | ||
794 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, | ||
795 | static void omap_lcdc_write(void *opaque, hwaddr addr, | ||
796 | uint64_t value, unsigned size) | ||
797 | { | ||
798 | - struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque; | ||
799 | + struct omap_lcd_panel_s *s = opaque; | ||
800 | |||
801 | switch (addr) { | ||
802 | case 0x00: /* LCD_CONTROL */ | ||
803 | diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c | ||
804 | index XXXXXXX..XXXXXXX 100644 | ||
805 | --- a/hw/dma/omap_dma.c | ||
806 | +++ b/hw/dma/omap_dma.c | ||
807 | @@ -XXX,XX +XXX,XX @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset, | ||
808 | return 0; | ||
809 | } | ||
810 | |||
811 | -static uint64_t omap_dma_read(void *opaque, hwaddr addr, | ||
812 | - unsigned size) | ||
813 | +static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size) | ||
814 | { | ||
815 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
816 | + struct omap_dma_s *s = opaque; | ||
817 | int reg, ch; | ||
818 | uint16_t ret; | ||
819 | |||
820 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr, | ||
821 | static void omap_dma_write(void *opaque, hwaddr addr, | ||
822 | uint64_t value, unsigned size) | ||
823 | { | ||
824 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
825 | + struct omap_dma_s *s = opaque; | ||
826 | int reg, ch; | ||
827 | |||
828 | if (size != 2) { | ||
829 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_dma_ops = { | ||
830 | |||
831 | static void omap_dma_request(void *opaque, int drq, int req) | ||
832 | { | ||
833 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
834 | + struct omap_dma_s *s = opaque; | ||
835 | /* The request pins are level triggered in QEMU. */ | ||
836 | if (req) { | ||
837 | if (~s->dma->drqbmp & (1ULL << drq)) { | ||
838 | @@ -XXX,XX +XXX,XX @@ static void omap_dma_request(void *opaque, int drq, int req) | ||
839 | /* XXX: this won't be needed once soc_dma knows about clocks. */ | ||
840 | static void omap_dma_clk_update(void *opaque, int line, int on) | ||
841 | { | ||
842 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
843 | + struct omap_dma_s *s = opaque; | ||
844 | int i; | ||
845 | |||
846 | s->dma->freq = omap_clk_getrate(s->clk); | ||
847 | @@ -XXX,XX +XXX,XX @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s) | ||
848 | static uint64_t omap_dma4_read(void *opaque, hwaddr addr, | ||
849 | unsigned size) | ||
850 | { | ||
851 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
852 | + struct omap_dma_s *s = opaque; | ||
853 | int irqn = 0, chnum; | ||
854 | struct omap_dma_channel_s *ch; | ||
855 | |||
856 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr, | ||
857 | static void omap_dma4_write(void *opaque, hwaddr addr, | ||
858 | uint64_t value, unsigned size) | ||
859 | { | ||
860 | - struct omap_dma_s *s = (struct omap_dma_s *) opaque; | ||
861 | + struct omap_dma_s *s = opaque; | ||
862 | int chnum, irqn = 0; | ||
863 | struct omap_dma_channel_s *ch; | ||
864 | |||
865 | diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c | ||
866 | index XXXXXXX..XXXXXXX 100644 | ||
867 | --- a/hw/gpio/omap_gpio.c | ||
868 | +++ b/hw/gpio/omap_gpio.c | ||
869 | @@ -XXX,XX +XXX,XX @@ static void omap_gpio_set(void *opaque, int line, int level) | ||
870 | static uint64_t omap_gpio_read(void *opaque, hwaddr addr, | ||
871 | unsigned size) | ||
872 | { | ||
873 | - struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; | ||
874 | + struct omap_gpio_s *s = opaque; | ||
875 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
876 | |||
877 | if (size != 2) { | ||
878 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr, | ||
879 | static void omap_gpio_write(void *opaque, hwaddr addr, | ||
880 | uint64_t value, unsigned size) | ||
881 | { | ||
882 | - struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; | ||
883 | + struct omap_gpio_s *s = opaque; | ||
884 | int offset = addr & OMAP_MPUI_REG_MASK; | ||
885 | uint16_t diff; | ||
886 | int ln; | ||
887 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s) | ||
888 | |||
889 | static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) | ||
890 | { | ||
891 | - struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | ||
892 | + struct omap2_gpio_s *s = opaque; | ||
893 | |||
894 | switch (addr) { | ||
895 | case 0x00: /* GPIO_REVISION */ | ||
896 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr) | ||
897 | static void omap2_gpio_module_write(void *opaque, hwaddr addr, | ||
898 | uint32_t value) | ||
899 | { | ||
900 | - struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; | ||
901 | + struct omap2_gpio_s *s = opaque; | ||
902 | uint32_t diff; | ||
903 | int ln; | ||
904 | |||
905 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev) | ||
906 | s->gpo = 0; | ||
907 | } | ||
908 | |||
909 | -static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, | ||
910 | - unsigned size) | ||
911 | +static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size) | ||
912 | { | ||
913 | - struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; | ||
914 | + struct omap2_gpif_s *s = opaque; | ||
915 | |||
916 | switch (addr) { | ||
917 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | ||
918 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, | ||
919 | static void omap2_gpif_top_write(void *opaque, hwaddr addr, | ||
920 | uint64_t value, unsigned size) | ||
921 | { | ||
922 | - struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque; | ||
923 | + struct omap2_gpif_s *s = opaque; | ||
924 | |||
925 | switch (addr) { | ||
926 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | ||
927 | diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c | ||
928 | index XXXXXXX..XXXXXXX 100644 | ||
929 | --- a/hw/intc/omap_intc.c | ||
930 | +++ b/hw/intc/omap_intc.c | ||
931 | @@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) | ||
932 | |||
933 | static void omap_set_intr(void *opaque, int irq, int req) | ||
934 | { | ||
935 | - struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; | ||
936 | + struct omap_intr_handler_s *ih = opaque; | ||
937 | uint32_t rise; | ||
938 | |||
939 | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; | ||
940 | @@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req) | ||
941 | /* Simplified version with no edge detection */ | ||
942 | static void omap_set_intr_noedge(void *opaque, int irq, int req) | ||
943 | { | ||
944 | - struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; | ||
945 | + struct omap_intr_handler_s *ih = opaque; | ||
946 | uint32_t rise; | ||
947 | |||
948 | struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; | ||
949 | @@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req) | ||
950 | static uint64_t omap_inth_read(void *opaque, hwaddr addr, | ||
951 | unsigned size) | ||
952 | { | ||
953 | - struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; | ||
954 | + struct omap_intr_handler_s *s = opaque; | ||
955 | int i, offset = addr; | ||
956 | int bank_no = offset >> 8; | ||
957 | int line_no; | ||
958 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr, | ||
959 | static void omap_inth_write(void *opaque, hwaddr addr, | ||
960 | uint64_t value, unsigned size) | ||
961 | { | ||
962 | - struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; | ||
963 | + struct omap_intr_handler_s *s = opaque; | ||
964 | int i, offset = addr; | ||
965 | int bank_no = offset >> 8; | ||
966 | struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; | ||
967 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = { | ||
968 | static uint64_t omap2_inth_read(void *opaque, hwaddr addr, | ||
969 | unsigned size) | ||
970 | { | ||
971 | - struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; | ||
972 | + struct omap_intr_handler_s *s = opaque; | ||
973 | int offset = addr; | ||
974 | int bank_no, line_no; | ||
975 | struct omap_intr_handler_bank_s *bank = NULL; | ||
976 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr, | ||
977 | static void omap2_inth_write(void *opaque, hwaddr addr, | ||
978 | uint64_t value, unsigned size) | ||
979 | { | ||
980 | - struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; | ||
981 | + struct omap_intr_handler_s *s = opaque; | ||
982 | int offset = addr; | ||
983 | int bank_no, line_no; | ||
984 | struct omap_intr_handler_bank_s *bank = NULL; | ||
985 | diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c | ||
986 | index XXXXXXX..XXXXXXX 100644 | ||
987 | --- a/hw/misc/omap_gpmc.c | ||
988 | +++ b/hw/misc/omap_gpmc.c | ||
989 | @@ -XXX,XX +XXX,XX @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value) | ||
990 | static uint64_t omap_nand_read(void *opaque, hwaddr addr, | ||
991 | unsigned size) | ||
992 | { | ||
993 | - struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque; | ||
994 | + struct omap_gpmc_cs_file_s *f = opaque; | ||
995 | uint64_t v; | ||
996 | nand_setpins(f->dev, 0, 0, 0, 1, 0); | ||
997 | switch (omap_gpmc_devsize(f)) { | ||
998 | @@ -XXX,XX +XXX,XX @@ static void omap_nand_setio(DeviceState *dev, uint64_t value, | ||
999 | static void omap_nand_write(void *opaque, hwaddr addr, | ||
1000 | uint64_t value, unsigned size) | ||
1001 | { | ||
1002 | - struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque; | ||
1003 | + struct omap_gpmc_cs_file_s *f = opaque; | ||
1004 | nand_setpins(f->dev, 0, 0, 0, 1, 0); | ||
1005 | omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size); | ||
1006 | } | ||
1007 | @@ -XXX,XX +XXX,XX @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s) | ||
1008 | static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr, | ||
1009 | unsigned size) | ||
1010 | { | ||
1011 | - struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | ||
1012 | + struct omap_gpmc_s *s = opaque; | ||
1013 | uint32_t data; | ||
1014 | if (s->prefetch.config1 & 1) { | ||
1015 | /* The TRM doesn't define the behaviour if you read from the | ||
1016 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr, | ||
1017 | static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr, | ||
1018 | uint64_t value, unsigned size) | ||
1019 | { | ||
1020 | - struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | ||
1021 | + struct omap_gpmc_s *s = opaque; | ||
1022 | int cs = prefetch_cs(s->prefetch.config1); | ||
1023 | if ((s->prefetch.config1 & 1) == 0) { | ||
1024 | /* The TRM doesn't define the behaviour of writing to the | ||
1025 | @@ -XXX,XX +XXX,XX @@ static int gpmc_wordaccess_only(hwaddr addr) | ||
1026 | static uint64_t omap_gpmc_read(void *opaque, hwaddr addr, | ||
1027 | unsigned size) | ||
1028 | { | ||
1029 | - struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | ||
1030 | + struct omap_gpmc_s *s = opaque; | ||
1031 | int cs; | ||
1032 | struct omap_gpmc_cs_file_s *f; | ||
1033 | |||
1034 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr, | ||
1035 | static void omap_gpmc_write(void *opaque, hwaddr addr, | ||
1036 | uint64_t value, unsigned size) | ||
1037 | { | ||
1038 | - struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque; | ||
1039 | + struct omap_gpmc_s *s = opaque; | ||
1040 | int cs; | ||
1041 | struct omap_gpmc_cs_file_s *f; | ||
1042 | |||
1043 | diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c | ||
1044 | index XXXXXXX..XXXXXXX 100644 | ||
1045 | --- a/hw/misc/omap_l4.c | ||
1046 | +++ b/hw/misc/omap_l4.c | ||
1047 | @@ -XXX,XX +XXX,XX @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, | ||
1048 | return ta->start[region].size; | ||
1049 | } | ||
1050 | |||
1051 | -static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, | ||
1052 | - unsigned size) | ||
1053 | +static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size) | ||
1054 | { | ||
1055 | - struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; | ||
1056 | + struct omap_target_agent_s *s = opaque; | ||
1057 | |||
1058 | if (size != 2) { | ||
1059 | return omap_badwidth_read16(opaque, addr); | ||
1060 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, | ||
1061 | static void omap_l4ta_write(void *opaque, hwaddr addr, | ||
1062 | uint64_t value, unsigned size) | ||
1063 | { | ||
1064 | - struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque; | ||
1065 | + struct omap_target_agent_s *s = opaque; | ||
1066 | |||
1067 | if (size != 4) { | ||
1068 | omap_badwidth_write32(opaque, addr, value); | ||
1069 | diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c | ||
1070 | index XXXXXXX..XXXXXXX 100644 | ||
1071 | --- a/hw/misc/omap_sdrc.c | ||
1072 | +++ b/hw/misc/omap_sdrc.c | ||
1073 | @@ -XXX,XX +XXX,XX @@ void omap_sdrc_reset(struct omap_sdrc_s *s) | ||
1074 | s->config = 0x10; | ||
1075 | } | ||
1076 | |||
1077 | -static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, | ||
1078 | - unsigned size) | ||
1079 | +static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size) | ||
1080 | { | ||
1081 | - struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; | ||
1082 | + struct omap_sdrc_s *s = opaque; | ||
1083 | |||
1084 | if (size != 4) { | ||
1085 | return omap_badwidth_read32(opaque, addr); | ||
1086 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, | ||
1087 | static void omap_sdrc_write(void *opaque, hwaddr addr, | ||
1088 | uint64_t value, unsigned size) | ||
1089 | { | ||
1090 | - struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque; | ||
1091 | + struct omap_sdrc_s *s = opaque; | ||
1092 | |||
1093 | if (size != 4) { | ||
1094 | omap_badwidth_write32(opaque, addr, value); | ||
1095 | diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c | ||
1096 | index XXXXXXX..XXXXXXX 100644 | ||
1097 | --- a/hw/misc/omap_tap.c | ||
1098 | +++ b/hw/misc/omap_tap.c | ||
1099 | @@ -XXX,XX +XXX,XX @@ | ||
1100 | #include "hw/arm/omap.h" | ||
1101 | |||
1102 | /* TEST-Chip-level TAP */ | ||
1103 | -static uint64_t omap_tap_read(void *opaque, hwaddr addr, | ||
1104 | - unsigned size) | ||
1105 | +static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size) | ||
1106 | { | ||
1107 | - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; | ||
1108 | + struct omap_mpu_state_s *s = opaque; | ||
1109 | |||
1110 | if (size != 4) { | ||
1111 | return omap_badwidth_read32(opaque, addr); | ||
1112 | diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c | ||
1113 | index XXXXXXX..XXXXXXX 100644 | ||
1114 | --- a/hw/sd/omap_mmc.c | ||
1115 | +++ b/hw/sd/omap_mmc.c | ||
1116 | @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) | ||
1117 | device_cold_reset(DEVICE(host->card)); | ||
1118 | } | ||
1119 | |||
1120 | -static uint64_t omap_mmc_read(void *opaque, hwaddr offset, | ||
1121 | - unsigned size) | ||
1122 | +static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size) | ||
1123 | { | ||
1124 | uint16_t i; | ||
1125 | - struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; | ||
1126 | + struct omap_mmc_s *s = opaque; | ||
1127 | |||
1128 | if (size != 2) { | ||
1129 | return omap_badwidth_read16(opaque, offset); | ||
1130 | @@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset, | ||
1131 | uint64_t value, unsigned size) | ||
1132 | { | ||
1133 | int i; | ||
1134 | - struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; | ||
1135 | + struct omap_mmc_s *s = opaque; | ||
1136 | |||
1137 | if (size != 2) { | ||
1138 | omap_badwidth_write16(opaque, offset, value); | ||
1139 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_mmc_ops = { | ||
1140 | |||
1141 | static void omap_mmc_cover_cb(void *opaque, int line, int level) | ||
1142 | { | ||
1143 | - struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; | ||
1144 | + struct omap_mmc_s *host = opaque; | ||
1145 | |||
1146 | if (!host->cdet_state && level) { | ||
1147 | host->status |= 0x0002; | ||
1148 | diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c | ||
1149 | index XXXXXXX..XXXXXXX 100644 | ||
1150 | --- a/hw/ssi/omap_spi.c | ||
1151 | +++ b/hw/ssi/omap_spi.c | ||
1152 | @@ -XXX,XX +XXX,XX @@ void omap_mcspi_reset(struct omap_mcspi_s *s) | ||
1153 | omap_mcspi_interrupt_update(s); | ||
1154 | } | ||
1155 | |||
1156 | -static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, | ||
1157 | - unsigned size) | ||
1158 | +static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size) | ||
1159 | { | ||
1160 | - struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; | ||
1161 | + struct omap_mcspi_s *s = opaque; | ||
1162 | int ch = 0; | ||
1163 | uint32_t ret; | ||
1164 | |||
1165 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, | ||
1166 | static void omap_mcspi_write(void *opaque, hwaddr addr, | ||
1167 | uint64_t value, unsigned size) | ||
1168 | { | ||
1169 | - struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; | ||
1170 | + struct omap_mcspi_s *s = opaque; | ||
1171 | int ch = 0; | ||
1172 | |||
1173 | if (size != 4) { | ||
1174 | diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c | ||
1175 | index XXXXXXX..XXXXXXX 100644 | ||
1176 | --- a/hw/timer/omap_gptimer.c | ||
1177 | +++ b/hw/timer/omap_gptimer.c | ||
1178 | @@ -XXX,XX +XXX,XX @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer) | ||
1179 | |||
1180 | static void omap_gp_timer_tick(void *opaque) | ||
1181 | { | ||
1182 | - struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | ||
1183 | + struct omap_gp_timer_s *timer = opaque; | ||
1184 | |||
1185 | if (!timer->ar) { | ||
1186 | timer->st = 0; | ||
1187 | @@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_tick(void *opaque) | ||
1188 | |||
1189 | static void omap_gp_timer_match(void *opaque) | ||
1190 | { | ||
1191 | - struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | ||
1192 | + struct omap_gp_timer_s *timer = opaque; | ||
1193 | |||
1194 | if (timer->trigger == gpt_trigger_both) | ||
1195 | omap_gp_timer_trigger(timer); | ||
1196 | @@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_match(void *opaque) | ||
1197 | |||
1198 | static void omap_gp_timer_input(void *opaque, int line, int on) | ||
1199 | { | ||
1200 | - struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | ||
1201 | + struct omap_gp_timer_s *s = opaque; | ||
1202 | int trigger; | ||
1203 | |||
1204 | switch (s->capture) { | ||
1205 | @@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_input(void *opaque, int line, int on) | ||
1206 | |||
1207 | static void omap_gp_timer_clk_update(void *opaque, int line, int on) | ||
1208 | { | ||
1209 | - struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque; | ||
1210 | + struct omap_gp_timer_s *timer = opaque; | ||
1211 | |||
1212 | omap_gp_timer_sync(timer); | ||
1213 | timer->rate = on ? omap_clk_getrate(timer->clk) : 0; | ||
1214 | @@ -XXX,XX +XXX,XX @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s) | ||
1215 | |||
1216 | static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) | ||
1217 | { | ||
1218 | - struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | ||
1219 | + struct omap_gp_timer_s *s = opaque; | ||
1220 | |||
1221 | switch (addr) { | ||
1222 | case 0x00: /* TIDR */ | ||
1223 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr) | ||
1224 | |||
1225 | static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr) | ||
1226 | { | ||
1227 | - struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | ||
1228 | + struct omap_gp_timer_s *s = opaque; | ||
1229 | uint32_t ret; | ||
1230 | |||
1231 | if (addr & 2) | ||
1232 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr) | ||
1233 | } | ||
1234 | } | ||
1235 | |||
1236 | -static void omap_gp_timer_write(void *opaque, hwaddr addr, | ||
1237 | - uint32_t value) | ||
1238 | +static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value) | ||
1239 | { | ||
1240 | - struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | ||
1241 | + struct omap_gp_timer_s *s = opaque; | ||
1242 | |||
1243 | switch (addr) { | ||
1244 | case 0x00: /* TIDR */ | ||
1245 | @@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_write(void *opaque, hwaddr addr, | ||
1246 | } | ||
1247 | } | ||
1248 | |||
1249 | -static void omap_gp_timer_writeh(void *opaque, hwaddr addr, | ||
1250 | - uint32_t value) | ||
1251 | +static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value) | ||
1252 | { | ||
1253 | - struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque; | ||
1254 | + struct omap_gp_timer_s *s = opaque; | ||
1255 | |||
1256 | if (addr & 2) | ||
1257 | omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh); | ||
1258 | diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c | ||
1259 | index XXXXXXX..XXXXXXX 100644 | ||
1260 | --- a/hw/timer/omap_synctimer.c | ||
1261 | +++ b/hw/timer/omap_synctimer.c | ||
1262 | @@ -XXX,XX +XXX,XX @@ void omap_synctimer_reset(struct omap_synctimer_s *s) | ||
1263 | |||
1264 | static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr) | ||
1265 | { | ||
1266 | - struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | ||
1267 | + struct omap_synctimer_s *s = opaque; | ||
1268 | |||
1269 | switch (addr) { | ||
1270 | case 0x00: /* 32KSYNCNT_REV */ | ||
1271 | @@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr) | ||
1272 | |||
1273 | static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr) | ||
1274 | { | ||
1275 | - struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | ||
1276 | + struct omap_synctimer_s *s = opaque; | ||
1277 | uint32_t ret; | ||
1278 | |||
1279 | if (addr & 2) | ||
1280 | -- | 291 | -- |
1281 | 2.34.1 | 292 | 2.34.1 |
1282 | |||
1283 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Alexander Graf <agraf@csgraf.de> |
---|---|---|---|
2 | 2 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 3 | Let's explicitly list out all accelerators that we support when trying to |
4 | determine the supported set of GIC versions. KVM was already separate, so | ||
5 | the only missing one is HVF which simply reuses all of TCG's emulation | ||
6 | code and thus has the same compatibility matrix. | ||
4 | 7 | ||
5 | Add definitions for RAM / Flash / Flash blocksize. | 8 | Signed-off-by: Alexander Graf <agraf@csgraf.de> |
6 | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> |
11 | Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230109115316.2235-7-philmd@linaro.org | 13 | Message-id: 20221223090107.98888-3-agraf@csgraf.de |
10 | Message-Id: <20200223231044.8003-3-philmd@redhat.com> | 14 | [PMM: Added qtest to the list of accelerators] |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 16 | --- |
13 | hw/arm/gumstix.c | 27 ++++++++++++++------------- | 17 | hw/arm/virt.c | 7 ++++++- |
14 | 1 file changed, 14 insertions(+), 13 deletions(-) | 18 | 1 file changed, 6 insertions(+), 1 deletion(-) |
15 | 19 | ||
16 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | 20 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
17 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/gumstix.c | 22 | --- a/hw/arm/virt.c |
19 | +++ b/hw/arm/gumstix.c | 23 | +++ b/hw/arm/virt.c |
20 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
21 | */ | 25 | #include "sysemu/numa.h" |
22 | 26 | #include "sysemu/runstate.h" | |
23 | #include "qemu/osdep.h" | 27 | #include "sysemu/tpm.h" |
24 | +#include "qemu/units.h" | 28 | +#include "sysemu/tcg.h" |
25 | #include "qemu/error-report.h" | 29 | #include "sysemu/kvm.h" |
26 | #include "hw/arm/pxa.h" | 30 | #include "sysemu/hvf.h" |
27 | #include "net/net.h" | 31 | +#include "sysemu/qtest.h" |
28 | @@ -XXX,XX +XXX,XX @@ | 32 | #include "hw/loader.h" |
29 | #include "sysemu/qtest.h" | 33 | #include "qapi/error.h" |
30 | #include "cpu.h" | 34 | #include "qemu/bitops.h" |
31 | 35 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | |
32 | -static const int sector_len = 128 * 1024; | 36 | /* KVM w/o kernel irqchip can only deal with GICv2 */ |
33 | +#define CONNEX_FLASH_SIZE (16 * MiB) | 37 | gics_supported |= VIRT_GIC_VERSION_2_MASK; |
34 | +#define CONNEX_RAM_SIZE (64 * MiB) | 38 | accel_name = "KVM with kernel-irqchip=off"; |
35 | + | 39 | - } else { |
36 | +#define VERDEX_FLASH_SIZE (32 * MiB) | 40 | + } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { |
37 | +#define VERDEX_RAM_SIZE (256 * MiB) | 41 | gics_supported |= VIRT_GIC_VERSION_2_MASK; |
38 | + | 42 | if (module_object_class_by_name("arm-gicv3")) { |
39 | +#define FLASH_SECTOR_SIZE (128 * KiB) | 43 | gics_supported |= VIRT_GIC_VERSION_3_MASK; |
40 | 44 | @@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms) | |
41 | static void connex_init(MachineState *machine) | 45 | gics_supported |= VIRT_GIC_VERSION_4_MASK; |
42 | { | 46 | } |
43 | PXA2xxState *cpu; | 47 | } |
44 | DriveInfo *dinfo; | 48 | + } else { |
45 | 49 | + error_report("Unsupported accelerator, can not determine GIC support"); | |
46 | - uint32_t connex_rom = 0x01000000; | 50 | + exit(1); |
47 | - uint32_t connex_ram = 0x04000000; | ||
48 | - | ||
49 | - cpu = pxa255_init(connex_ram); | ||
50 | + cpu = pxa255_init(CONNEX_RAM_SIZE); | ||
51 | |||
52 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
53 | if (!dinfo && !qtest_enabled()) { | ||
54 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | ||
55 | } | 51 | } |
56 | 52 | ||
57 | /* Numonyx RC28F128J3F75 */ | 53 | /* |
58 | - if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, | ||
59 | + if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE, | ||
60 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
61 | - sector_len, 2, 0, 0, 0, 0, 0)) { | ||
62 | + FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) { | ||
63 | error_report("Error registering flash memory"); | ||
64 | exit(1); | ||
65 | } | ||
66 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | ||
67 | PXA2xxState *cpu; | ||
68 | DriveInfo *dinfo; | ||
69 | |||
70 | - uint32_t verdex_rom = 0x02000000; | ||
71 | - uint32_t verdex_ram = 0x10000000; | ||
72 | - | ||
73 | - cpu = pxa270_init(verdex_ram, machine->cpu_type); | ||
74 | + cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type); | ||
75 | |||
76 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
77 | if (!dinfo && !qtest_enabled()) { | ||
78 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | ||
79 | } | ||
80 | |||
81 | /* Micron RC28F256P30TFA */ | ||
82 | - if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, | ||
83 | + if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE, | ||
84 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
85 | - sector_len, 2, 0, 0, 0, 0, 0)) { | ||
86 | + FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) { | ||
87 | error_report("Error registering flash memory"); | ||
88 | exit(1); | ||
89 | } | ||
90 | -- | 54 | -- |
91 | 2.34.1 | 55 | 2.34.1 |
92 | 56 | ||
93 | 57 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER() | 3 | Cortex-A76 supports 40bits of address space. sbsa-ref's memory |
4 | macro call, to avoid after a QOM refactor: | 4 | starts above this limit. |
5 | 5 | ||
6 | hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition | 6 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
7 | DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER, | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
8 | ^ | ||
9 | |||
10 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> | 9 | Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org |
13 | Message-id: 20230109140306.23161-15-philmd@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 11 | --- |
16 | hw/timer/xilinx_timer.c | 27 +++++++++++++-------------- | 12 | hw/arm/sbsa-ref.c | 1 - |
17 | 1 file changed, 13 insertions(+), 14 deletions(-) | 13 | 1 file changed, 1 deletion(-) |
18 | 14 | ||
19 | diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c | 15 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/timer/xilinx_timer.c | 17 | --- a/hw/arm/sbsa-ref.c |
22 | +++ b/hw/timer/xilinx_timer.c | 18 | +++ b/hw/arm/sbsa-ref.c |
23 | @@ -XXX,XX +XXX,XX @@ struct xlx_timer | 19 | @@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = { |
24 | }; | 20 | static const char * const valid_cpus[] = { |
25 | 21 | ARM_CPU_TYPE_NAME("cortex-a57"), | |
26 | #define TYPE_XILINX_TIMER "xlnx.xps-timer" | 22 | ARM_CPU_TYPE_NAME("cortex-a72"), |
27 | -DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER, | 23 | - ARM_CPU_TYPE_NAME("cortex-a76"), |
28 | - TYPE_XILINX_TIMER) | 24 | ARM_CPU_TYPE_NAME("neoverse-n1"), |
29 | +typedef struct XpsTimerState XpsTimerState; | 25 | ARM_CPU_TYPE_NAME("max"), |
30 | +DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER) | ||
31 | |||
32 | -struct timerblock | ||
33 | +struct XpsTimerState | ||
34 | { | ||
35 | SysBusDevice parent_obj; | ||
36 | |||
37 | @@ -XXX,XX +XXX,XX @@ struct timerblock | ||
38 | struct xlx_timer *timers; | ||
39 | }; | ||
40 | |||
41 | -static inline unsigned int num_timers(struct timerblock *t) | ||
42 | +static inline unsigned int num_timers(XpsTimerState *t) | ||
43 | { | ||
44 | return 2 - t->one_timer_only; | ||
45 | } | ||
46 | @@ -XXX,XX +XXX,XX @@ static inline unsigned int timer_from_addr(hwaddr addr) | ||
47 | return addr >> 2; | ||
48 | } | ||
49 | |||
50 | -static void timer_update_irq(struct timerblock *t) | ||
51 | +static void timer_update_irq(XpsTimerState *t) | ||
52 | { | ||
53 | unsigned int i, irq = 0; | ||
54 | uint32_t csr; | ||
55 | @@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct timerblock *t) | ||
56 | static uint64_t | ||
57 | timer_read(void *opaque, hwaddr addr, unsigned int size) | ||
58 | { | ||
59 | - struct timerblock *t = opaque; | ||
60 | + XpsTimerState *t = opaque; | ||
61 | struct xlx_timer *xt; | ||
62 | uint32_t r = 0; | ||
63 | unsigned int timer; | ||
64 | @@ -XXX,XX +XXX,XX @@ static void | ||
65 | timer_write(void *opaque, hwaddr addr, | ||
66 | uint64_t val64, unsigned int size) | ||
67 | { | ||
68 | - struct timerblock *t = opaque; | ||
69 | + XpsTimerState *t = opaque; | ||
70 | struct xlx_timer *xt; | ||
71 | unsigned int timer; | ||
72 | uint32_t value = val64; | ||
73 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = { | ||
74 | static void timer_hit(void *opaque) | ||
75 | { | ||
76 | struct xlx_timer *xt = opaque; | ||
77 | - struct timerblock *t = xt->parent; | ||
78 | + XpsTimerState *t = xt->parent; | ||
79 | D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); | ||
80 | xt->regs[R_TCSR] |= TCSR_TINT; | ||
81 | |||
82 | @@ -XXX,XX +XXX,XX @@ static void timer_hit(void *opaque) | ||
83 | |||
84 | static void xilinx_timer_realize(DeviceState *dev, Error **errp) | ||
85 | { | ||
86 | - struct timerblock *t = XILINX_TIMER(dev); | ||
87 | + XpsTimerState *t = XILINX_TIMER(dev); | ||
88 | unsigned int i; | ||
89 | |||
90 | /* Init all the ptimers. */ | ||
91 | @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp) | ||
92 | |||
93 | static void xilinx_timer_init(Object *obj) | ||
94 | { | ||
95 | - struct timerblock *t = XILINX_TIMER(obj); | ||
96 | + XpsTimerState *t = XILINX_TIMER(obj); | ||
97 | |||
98 | /* All timers share a single irq line. */ | ||
99 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq); | ||
100 | } | ||
101 | |||
102 | static Property xilinx_timer_properties[] = { | ||
103 | - DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz, | ||
104 | - 62 * 1000000), | ||
105 | - DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0), | ||
106 | + DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000), | ||
107 | + DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0), | ||
108 | DEFINE_PROP_END_OF_LIST(), | ||
109 | }; | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data) | ||
112 | static const TypeInfo xilinx_timer_info = { | ||
113 | .name = TYPE_XILINX_TIMER, | ||
114 | .parent = TYPE_SYS_BUS_DEVICE, | ||
115 | - .instance_size = sizeof(struct timerblock), | ||
116 | + .instance_size = sizeof(XpsTimerState), | ||
117 | .instance_init = xilinx_timer_init, | ||
118 | .class_init = xilinx_timer_class_init, | ||
119 | }; | 26 | }; |
120 | -- | 27 | -- |
121 | 2.34.1 | 28 | 2.34.1 |
122 | 29 | ||
123 | 30 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT |
---|---|---|---|
2 | S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name | ||
3 | them AT S1E1R and AT S1E1W (which are entirely different | ||
4 | instructions). Fix the names. | ||
2 | 5 | ||
3 | This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER() | 6 | (This has no guest-visible effect as the names are for debug purposes |
4 | macro call, to avoid after a QOM refactor: | 7 | only.) |
5 | 8 | ||
6 | hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC, | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | ^ | 11 | Tested-by: Fuad Tabba <tabba@google.com> |
12 | Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org | ||
13 | Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org | ||
14 | --- | ||
15 | target/arm/helper.c | 4 ++-- | ||
16 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
9 | 17 | ||
10 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 18 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> | ||
13 | Message-id: 20230109140306.23161-14-philmd@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/intc/xilinx_intc.c | 28 +++++++++++++--------------- | ||
17 | 1 file changed, 13 insertions(+), 15 deletions(-) | ||
18 | |||
19 | diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/intc/xilinx_intc.c | 20 | --- a/target/arm/helper.c |
22 | +++ b/hw/intc/xilinx_intc.c | 21 | +++ b/target/arm/helper.c |
23 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { |
24 | #define R_MAX 8 | 23 | |
25 | 24 | #ifndef CONFIG_USER_ONLY | |
26 | #define TYPE_XILINX_INTC "xlnx.xps-intc" | 25 | static const ARMCPRegInfo ats1e1_reginfo[] = { |
27 | -DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC, | 26 | - { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, |
28 | - TYPE_XILINX_INTC) | 27 | + { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, |
29 | +typedef struct XpsIntc XpsIntc; | 28 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, |
30 | +DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC) | 29 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
31 | 30 | .writefn = ats_write64 }, | |
32 | -struct xlx_pic | 31 | - { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, |
33 | +struct XpsIntc | 32 | + { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, |
34 | { | 33 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, |
35 | SysBusDevice parent_obj; | 34 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, |
36 | 35 | .writefn = ats_write64 }, | |
37 | @@ -XXX,XX +XXX,XX @@ struct xlx_pic | ||
38 | uint32_t irq_pin_state; | ||
39 | }; | ||
40 | |||
41 | -static void update_irq(struct xlx_pic *p) | ||
42 | +static void update_irq(XpsIntc *p) | ||
43 | { | ||
44 | uint32_t i; | ||
45 | |||
46 | @@ -XXX,XX +XXX,XX @@ static void update_irq(struct xlx_pic *p) | ||
47 | qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]); | ||
48 | } | ||
49 | |||
50 | -static uint64_t | ||
51 | -pic_read(void *opaque, hwaddr addr, unsigned int size) | ||
52 | +static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size) | ||
53 | { | ||
54 | - struct xlx_pic *p = opaque; | ||
55 | + XpsIntc *p = opaque; | ||
56 | uint32_t r = 0; | ||
57 | |||
58 | addr >>= 2; | ||
59 | @@ -XXX,XX +XXX,XX @@ pic_read(void *opaque, hwaddr addr, unsigned int size) | ||
60 | return r; | ||
61 | } | ||
62 | |||
63 | -static void | ||
64 | -pic_write(void *opaque, hwaddr addr, | ||
65 | - uint64_t val64, unsigned int size) | ||
66 | +static void pic_write(void *opaque, hwaddr addr, | ||
67 | + uint64_t val64, unsigned int size) | ||
68 | { | ||
69 | - struct xlx_pic *p = opaque; | ||
70 | + XpsIntc *p = opaque; | ||
71 | uint32_t value = val64; | ||
72 | |||
73 | addr >>= 2; | ||
74 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = { | ||
75 | |||
76 | static void irq_handler(void *opaque, int irq, int level) | ||
77 | { | ||
78 | - struct xlx_pic *p = opaque; | ||
79 | + XpsIntc *p = opaque; | ||
80 | |||
81 | /* edge triggered interrupt */ | ||
82 | if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) { | ||
83 | @@ -XXX,XX +XXX,XX @@ static void irq_handler(void *opaque, int irq, int level) | ||
84 | |||
85 | static void xilinx_intc_init(Object *obj) | ||
86 | { | ||
87 | - struct xlx_pic *p = XILINX_INTC(obj); | ||
88 | + XpsIntc *p = XILINX_INTC(obj); | ||
89 | |||
90 | qdev_init_gpio_in(DEVICE(obj), irq_handler, 32); | ||
91 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq); | ||
92 | @@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj) | ||
93 | } | ||
94 | |||
95 | static Property xilinx_intc_properties[] = { | ||
96 | - DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0), | ||
97 | + DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), | ||
98 | DEFINE_PROP_END_OF_LIST(), | ||
99 | }; | ||
100 | |||
101 | @@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data) | ||
102 | static const TypeInfo xilinx_intc_info = { | ||
103 | .name = TYPE_XILINX_INTC, | ||
104 | .parent = TYPE_SYS_BUS_DEVICE, | ||
105 | - .instance_size = sizeof(struct xlx_pic), | ||
106 | + .instance_size = sizeof(XpsIntc), | ||
107 | .instance_init = xilinx_intc_init, | ||
108 | .class_init = xilinx_intc_class_init, | ||
109 | }; | ||
110 | -- | 36 | -- |
111 | 2.34.1 | 37 | 2.34.1 |
112 | |||
113 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | The AArch32 ATS12NSO* address translation operations are supposed to |
---|---|---|---|
2 | trap to either EL2 or EL3 if they're executed at Secure EL1 (which | ||
3 | can only happen if EL3 is AArch64). We implement this, but we got | ||
4 | the syndrome value wrong: like other traps to EL2 or EL3 on an | ||
5 | AArch32 cpreg access, they should report the 0x3 syndrome, not the | ||
6 | 0x0 'uncategorized' syndrome. This is clear in the access pseudocode | ||
7 | for these instructions. | ||
2 | 8 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 9 | Fix the syndrome value for these operations by correcting the |
10 | returned value from the ats_access() function. | ||
4 | 11 | ||
5 | Add the FLASH_SECTOR_SIZE definition. | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Tested-by: Fuad Tabba <tabba@google.com> | ||
15 | Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org | ||
16 | Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org | ||
17 | --- | ||
18 | target/arm/helper.c | 4 ++-- | ||
19 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
6 | 20 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230109115316.2235-8-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/mainstone.c | 18 ++++++++++-------- | ||
13 | 1 file changed, 10 insertions(+), 8 deletions(-) | ||
14 | |||
15 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/mainstone.c | 23 | --- a/target/arm/helper.c |
18 | +++ b/hw/arm/mainstone.c | 24 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, |
20 | * GNU GPL, version 2 or (at your option) any later version. | 26 | if (arm_current_el(env) == 1) { |
21 | */ | 27 | if (arm_is_secure_below_el3(env)) { |
22 | #include "qemu/osdep.h" | 28 | if (env->cp15.scr_el3 & SCR_EEL2) { |
23 | +#include "qemu/units.h" | 29 | - return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; |
24 | #include "qemu/error-report.h" | 30 | + return CP_ACCESS_TRAP_EL2; |
25 | #include "qapi/error.h" | 31 | } |
26 | #include "hw/arm/pxa.h" | 32 | - return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; |
27 | @@ -XXX,XX +XXX,XX @@ static const struct keymap map[0xE0] = { | 33 | + return CP_ACCESS_TRAP_EL3; |
28 | 34 | } | |
29 | enum mainstone_model_e { mainstone }; | 35 | return CP_ACCESS_TRAP_UNCATEGORIZED; |
30 | |||
31 | -#define MAINSTONE_RAM 0x04000000 | ||
32 | -#define MAINSTONE_ROM 0x00800000 | ||
33 | -#define MAINSTONE_FLASH 0x02000000 | ||
34 | +#define MAINSTONE_RAM_SIZE (64 * MiB) | ||
35 | +#define MAINSTONE_ROM_SIZE (8 * MiB) | ||
36 | +#define MAINSTONE_FLASH_SIZE (32 * MiB) | ||
37 | |||
38 | static struct arm_boot_info mainstone_binfo = { | ||
39 | .loader_start = PXA2XX_SDRAM_BASE, | ||
40 | - .ram_size = 0x04000000, | ||
41 | + .ram_size = MAINSTONE_RAM_SIZE, | ||
42 | }; | ||
43 | |||
44 | +#define FLASH_SECTOR_SIZE (256 * KiB) | ||
45 | + | ||
46 | static void mainstone_common_init(MachineState *machine, | ||
47 | enum mainstone_model_e model, int arm_id) | ||
48 | { | ||
49 | - uint32_t sector_len = 256 * 1024; | ||
50 | hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; | ||
51 | PXA2xxState *mpu; | ||
52 | DeviceState *mst_irq; | ||
53 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine, | ||
54 | |||
55 | /* Setup CPU & memory */ | ||
56 | mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type); | ||
57 | - memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM, | ||
58 | + memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE, | ||
59 | &error_fatal); | ||
60 | memory_region_add_subregion(get_system_memory(), 0x00000000, rom); | ||
61 | |||
62 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine, | ||
63 | dinfo = drive_get(IF_PFLASH, 0, i); | ||
64 | if (!pflash_cfi01_register(mainstone_flash_base[i], | ||
65 | i ? "mainstone.flash1" : "mainstone.flash0", | ||
66 | - MAINSTONE_FLASH, | ||
67 | + MAINSTONE_FLASH_SIZE, | ||
68 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
69 | - sector_len, 4, 0, 0, 0, 0, 0)) { | ||
70 | + FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
71 | error_report("Error registering flash memory"); | ||
72 | exit(1); | ||
73 | } | 36 | } |
74 | -- | 37 | -- |
75 | 2.34.1 | 38 | 2.34.1 |
76 | |||
77 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2 |
---|---|---|---|
2 | and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in | ||
3 | the ats_access() function, but doing so was incorrect (a bug fixed in | ||
4 | a previous commit). There aren't any cases where we want an access | ||
5 | function to be able to request a trap to EL2 or EL3 with a zero | ||
6 | syndrome value, so remove these enum values. | ||
2 | 7 | ||
3 | This model was merged few days before the QOM cleanup from | 8 | As well as cleaning up dead code, the motivation here is that |
4 | commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible") | 9 | we'd like to implement fine-grained-trap handling in |
5 | was pulled and merged. Manually adapt. | 10 | helper_access_check_cp_reg(). Although the fine-grained traps |
11 | to EL2 are always lower priority than trap-to-same-EL and | ||
12 | higher priority than trap-to-EL3, they are in the middle of | ||
13 | various other kinds of trap-to-EL2. Knowing that a trap-to-EL2 | ||
14 | must always for us have the same syndrome (ie that an access | ||
15 | function will return CP_ACCESS_TRAP_EL2 and there is no other | ||
16 | kind of trap-to-EL2 enum value) means we don't have to try | ||
17 | to choose which of the two syndrome values to report if the | ||
18 | access would trap to EL2 both for the fine-grained-trap and | ||
19 | because the access function requires it. | ||
6 | 20 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230109140306.23161-13-philmd@linaro.org | 23 | Tested-by: Fuad Tabba <tabba@google.com> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org |
25 | Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org | ||
11 | --- | 26 | --- |
12 | hw/misc/sbsa_ec.c | 3 +-- | 27 | target/arm/cpregs.h | 4 ++-- |
13 | 1 file changed, 1 insertion(+), 2 deletions(-) | 28 | target/arm/op_helper.c | 2 ++ |
29 | 2 files changed, 4 insertions(+), 2 deletions(-) | ||
14 | 30 | ||
15 | diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c | 31 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
16 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/misc/sbsa_ec.c | 33 | --- a/target/arm/cpregs.h |
18 | +++ b/hw/misc/sbsa_ec.c | 34 | +++ b/target/arm/cpregs.h |
19 | @@ -XXX,XX +XXX,XX @@ typedef struct SECUREECState { | 35 | @@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult { |
20 | } SECUREECState; | 36 | * Access fails and results in an exception syndrome 0x0 ("uncategorized"). |
21 | 37 | * Note that this is not a catch-all case -- the set of cases which may | |
22 | #define TYPE_SBSA_SECURE_EC "sbsa-ec" | 38 | * result in this failure is specifically defined by the architecture. |
23 | -#define SBSA_SECURE_EC(obj) \ | 39 | + * This trap is always to the usual target EL, never directly to a |
24 | - OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC) | 40 | + * specified target EL. |
25 | +OBJECT_DECLARE_SIMPLE_TYPE(SECUREECState, SBSA_SECURE_EC) | 41 | */ |
26 | 42 | CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), | |
27 | enum sbsa_ec_powerstates { | 43 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2, |
28 | SBSA_EC_CMD_POWEROFF = 0x01, | 44 | - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3, |
45 | } CPAccessResult; | ||
46 | |||
47 | typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
48 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/op_helper.c | ||
51 | +++ b/target/arm/op_helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, | ||
53 | case CP_ACCESS_TRAP: | ||
54 | break; | ||
55 | case CP_ACCESS_TRAP_UNCATEGORIZED: | ||
56 | + /* Only CP_ACCESS_TRAP traps are direct to a specified EL */ | ||
57 | + assert((res & CP_ACCESS_EL_MASK) == 0); | ||
58 | if (cpu_isar_feature(aa64_ids, cpu) && isread && | ||
59 | arm_cpreg_in_idspace(ri)) { | ||
60 | /* | ||
29 | -- | 61 | -- |
30 | 2.34.1 | 62 | 2.34.1 |
31 | |||
32 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | Rearrange the code in do_coproc_insn() so that we calculate the |
---|---|---|---|
2 | syndrome value for a potential trap early; we're about to add a | ||
3 | second check that wants this value earlier than where it is currently | ||
4 | determined. | ||
2 | 5 | ||
3 | During SPL boot several DRAM Controller registers are used. Most | 6 | (Specifically, a trap to EL2 because of HSTR_EL2 should take |
4 | important registers are those related to DRAM initialization and | 7 | priority over an UNDEF to EL1, even when the UNDEF is because |
5 | calibration, where SPL initiates process and waits until certain bit is | 8 | the register does not exist at all or because its ri->access |
6 | set/cleared. | 9 | bits non-configurably fail the access. So the check we put in |
10 | for HSTR_EL2 trapping at EL1 (which needs the syndrome) is | ||
11 | going to have to be done before the check "is the ARMCPRegInfo | ||
12 | pointer NULL".) | ||
7 | 13 | ||
8 | This patch adds these registers, initializes reset values from user's | 14 | This commit is just code motion; the change to HSTR_EL2 |
9 | guide and updates state of registers as SPL expects it. | 15 | handling that will use the 'syndrome' variable is in a |
16 | subsequent commit. | ||
10 | 17 | ||
11 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Tested-by: Fuad Tabba <tabba@google.com> | ||
21 | Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org | ||
22 | Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org | ||
23 | --- | ||
24 | target/arm/translate.c | 83 +++++++++++++++++++++--------------------- | ||
25 | 1 file changed, 41 insertions(+), 42 deletions(-) | ||
12 | 26 | ||
13 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 27 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | include/hw/arm/allwinner-a10.h | 2 + | ||
18 | include/hw/misc/allwinner-a10-dramc.h | 68 ++++++++++ | ||
19 | hw/arm/allwinner-a10.c | 7 + | ||
20 | hw/misc/allwinner-a10-dramc.c | 179 ++++++++++++++++++++++++++ | ||
21 | hw/arm/Kconfig | 1 + | ||
22 | hw/misc/Kconfig | 3 + | ||
23 | hw/misc/meson.build | 1 + | ||
24 | 7 files changed, 261 insertions(+) | ||
25 | create mode 100644 include/hw/misc/allwinner-a10-dramc.h | ||
26 | create mode 100644 hw/misc/allwinner-a10-dramc.c | ||
27 | |||
28 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/hw/arm/allwinner-a10.h | 29 | --- a/target/arm/translate.c |
31 | +++ b/include/hw/arm/allwinner-a10.h | 30 | +++ b/target/arm/translate.c |
32 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
33 | #include "hw/usb/hcd-ehci.h" | 32 | const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); |
34 | #include "hw/rtc/allwinner-rtc.h" | 33 | TCGv_ptr tcg_ri = NULL; |
35 | #include "hw/misc/allwinner-a10-ccm.h" | 34 | bool need_exit_tb; |
36 | +#include "hw/misc/allwinner-a10-dramc.h" | 35 | + uint32_t syndrome; |
37 | |||
38 | #include "target/arm/cpu.h" | ||
39 | #include "qom/object.h" | ||
40 | @@ -XXX,XX +XXX,XX @@ struct AwA10State { | ||
41 | |||
42 | ARMCPU cpu; | ||
43 | AwA10ClockCtlState ccm; | ||
44 | + AwA10DramControllerState dramc; | ||
45 | AwA10PITState timer; | ||
46 | AwA10PICState intc; | ||
47 | AwEmacState emac; | ||
48 | diff --git a/include/hw/misc/allwinner-a10-dramc.h b/include/hw/misc/allwinner-a10-dramc.h | ||
49 | new file mode 100644 | ||
50 | index XXXXXXX..XXXXXXX | ||
51 | --- /dev/null | ||
52 | +++ b/include/hw/misc/allwinner-a10-dramc.h | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | +/* | ||
55 | + * Allwinner A10 DRAM Controller emulation | ||
56 | + * | ||
57 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
58 | + * | ||
59 | + * This file is derived from Allwinner H3 DRAMC, | ||
60 | + * by Niek Linnenbank. | ||
61 | + * | ||
62 | + * This program is free software: you can redistribute it and/or modify | ||
63 | + * it under the terms of the GNU General Public License as published by | ||
64 | + * the Free Software Foundation, either version 2 of the License, or | ||
65 | + * (at your option) any later version. | ||
66 | + * | ||
67 | + * This program is distributed in the hope that it will be useful, | ||
68 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
69 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
70 | + * GNU General Public License for more details. | ||
71 | + * | ||
72 | + * You should have received a copy of the GNU General Public License | ||
73 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
74 | + */ | ||
75 | + | 36 | + |
76 | +#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H | 37 | + /* |
77 | +#define HW_MISC_ALLWINNER_A10_DRAMC_H | 38 | + * Note that since we are an implementation which takes an |
78 | + | 39 | + * exception on a trapped conditional instruction only if the |
79 | +#include "qom/object.h" | 40 | + * instruction passes its condition code check, we can take |
80 | +#include "hw/sysbus.h" | 41 | + * advantage of the clause in the ARM ARM that allows us to set |
81 | +#include "hw/register.h" | 42 | + * the COND field in the instruction to 0xE in all cases. |
82 | + | 43 | + * We could fish the actual condition out of the insn (ARM) |
83 | +/** | 44 | + * or the condexec bits (Thumb) but it isn't necessary. |
84 | + * @name Constants | 45 | + */ |
85 | + * @{ | 46 | + switch (cpnum) { |
86 | + */ | 47 | + case 14: |
87 | + | 48 | + if (is64) { |
88 | +/** Size of register I/O address space used by DRAMC device */ | 49 | + syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
89 | +#define AW_A10_DRAMC_IOSIZE (0x1000) | 50 | + isread, false); |
90 | + | 51 | + } else { |
91 | +/** Total number of known registers */ | 52 | + syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
92 | +#define AW_A10_DRAMC_REGS_NUM (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t)) | 53 | + rt, isread, false); |
93 | + | ||
94 | +/** @} */ | ||
95 | + | ||
96 | +/** | ||
97 | + * @name Object model | ||
98 | + * @{ | ||
99 | + */ | ||
100 | + | ||
101 | +#define TYPE_AW_A10_DRAMC "allwinner-a10-dramc" | ||
102 | +OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC) | ||
103 | + | ||
104 | +/** @} */ | ||
105 | + | ||
106 | +/** | ||
107 | + * Allwinner A10 DRAMC object instance state. | ||
108 | + */ | ||
109 | +struct AwA10DramControllerState { | ||
110 | + /*< private >*/ | ||
111 | + SysBusDevice parent_obj; | ||
112 | + /*< public >*/ | ||
113 | + | ||
114 | + /** Maps I/O registers in physical memory */ | ||
115 | + MemoryRegion iomem; | ||
116 | + | ||
117 | + /** Array of hardware registers */ | ||
118 | + uint32_t regs[AW_A10_DRAMC_REGS_NUM]; | ||
119 | +}; | ||
120 | + | ||
121 | +#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */ | ||
122 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
123 | index XXXXXXX..XXXXXXX 100644 | ||
124 | --- a/hw/arm/allwinner-a10.c | ||
125 | +++ b/hw/arm/allwinner-a10.c | ||
126 | @@ -XXX,XX +XXX,XX @@ | ||
127 | #include "hw/boards.h" | ||
128 | #include "hw/usb/hcd-ohci.h" | ||
129 | |||
130 | +#define AW_A10_DRAMC_BASE 0x01c01000 | ||
131 | #define AW_A10_MMC0_BASE 0x01c0f000 | ||
132 | #define AW_A10_CCM_BASE 0x01c20000 | ||
133 | #define AW_A10_PIC_REG_BASE 0x01c20400 | ||
134 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) | ||
135 | |||
136 | object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM); | ||
137 | |||
138 | + object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC); | ||
139 | + | ||
140 | object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); | ||
141 | |||
142 | object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); | ||
143 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
144 | sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal); | ||
145 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE); | ||
146 | |||
147 | + /* DRAM Control Module */ | ||
148 | + sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal); | ||
149 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE); | ||
150 | + | ||
151 | /* FIXME use qdev NIC properties instead of nd_table[] */ | ||
152 | if (nd_table[0].used) { | ||
153 | qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); | ||
154 | diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c | ||
155 | new file mode 100644 | ||
156 | index XXXXXXX..XXXXXXX | ||
157 | --- /dev/null | ||
158 | +++ b/hw/misc/allwinner-a10-dramc.c | ||
159 | @@ -XXX,XX +XXX,XX @@ | ||
160 | +/* | ||
161 | + * Allwinner A10 DRAM Controller emulation | ||
162 | + * | ||
163 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
164 | + * | ||
165 | + * This file is derived from Allwinner H3 DRAMC, | ||
166 | + * by Niek Linnenbank. | ||
167 | + * | ||
168 | + * This program is free software: you can redistribute it and/or modify | ||
169 | + * it under the terms of the GNU General Public License as published by | ||
170 | + * the Free Software Foundation, either version 2 of the License, or | ||
171 | + * (at your option) any later version. | ||
172 | + * | ||
173 | + * This program is distributed in the hope that it will be useful, | ||
174 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
175 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
176 | + * GNU General Public License for more details. | ||
177 | + * | ||
178 | + * You should have received a copy of the GNU General Public License | ||
179 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
180 | + */ | ||
181 | + | ||
182 | +#include "qemu/osdep.h" | ||
183 | +#include "qemu/units.h" | ||
184 | +#include "hw/sysbus.h" | ||
185 | +#include "migration/vmstate.h" | ||
186 | +#include "qemu/log.h" | ||
187 | +#include "qemu/module.h" | ||
188 | +#include "hw/misc/allwinner-a10-dramc.h" | ||
189 | + | ||
190 | +/* DRAMC register offsets */ | ||
191 | +enum { | ||
192 | + REG_SDR_CCR = 0x0000, | ||
193 | + REG_SDR_ZQCR0 = 0x00a8, | ||
194 | + REG_SDR_ZQSR = 0x00b0 | ||
195 | +}; | ||
196 | + | ||
197 | +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) | ||
198 | + | ||
199 | +/* DRAMC register flags */ | ||
200 | +enum { | ||
201 | + REG_SDR_CCR_DATA_TRAINING = (1 << 30), | ||
202 | + REG_SDR_CCR_DRAM_INIT = (1 << 31), | ||
203 | +}; | ||
204 | +enum { | ||
205 | + REG_SDR_ZQSR_ZCAL = (1 << 31), | ||
206 | +}; | ||
207 | + | ||
208 | +/* DRAMC register reset values */ | ||
209 | +enum { | ||
210 | + REG_SDR_CCR_RESET = 0x80020000, | ||
211 | + REG_SDR_ZQCR0_RESET = 0x07b00000, | ||
212 | + REG_SDR_ZQSR_RESET = 0x80000000 | ||
213 | +}; | ||
214 | + | ||
215 | +static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset, | ||
216 | + unsigned size) | ||
217 | +{ | ||
218 | + const AwA10DramControllerState *s = AW_A10_DRAMC(opaque); | ||
219 | + const uint32_t idx = REG_INDEX(offset); | ||
220 | + | ||
221 | + switch (offset) { | ||
222 | + case REG_SDR_CCR: | ||
223 | + case REG_SDR_ZQCR0: | ||
224 | + case REG_SDR_ZQSR: | ||
225 | + break; | ||
226 | + case 0x2e4 ... AW_A10_DRAMC_IOSIZE: | ||
227 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
228 | + __func__, (uint32_t)offset); | ||
229 | + return 0; | ||
230 | + default: | ||
231 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n", | ||
232 | + __func__, (uint32_t)offset); | ||
233 | + return 0; | ||
234 | + } | ||
235 | + | ||
236 | + return s->regs[idx]; | ||
237 | +} | ||
238 | + | ||
239 | +static void allwinner_a10_dramc_write(void *opaque, hwaddr offset, | ||
240 | + uint64_t val, unsigned size) | ||
241 | +{ | ||
242 | + AwA10DramControllerState *s = AW_A10_DRAMC(opaque); | ||
243 | + const uint32_t idx = REG_INDEX(offset); | ||
244 | + | ||
245 | + switch (offset) { | ||
246 | + case REG_SDR_CCR: | ||
247 | + if (val & REG_SDR_CCR_DRAM_INIT) { | ||
248 | + /* Clear DRAM_INIT to indicate process is done. */ | ||
249 | + val &= ~REG_SDR_CCR_DRAM_INIT; | ||
250 | + } | ||
251 | + if (val & REG_SDR_CCR_DATA_TRAINING) { | ||
252 | + /* Clear DATA_TRAINING to indicate process is done. */ | ||
253 | + val &= ~REG_SDR_CCR_DATA_TRAINING; | ||
254 | + } | 54 | + } |
255 | + break; | 55 | + break; |
256 | + case REG_SDR_ZQCR0: | 56 | + case 15: |
257 | + /* Set ZCAL in ZQSR to indicate calibration is done. */ | 57 | + if (is64) { |
258 | + s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL; | 58 | + syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
259 | + break; | 59 | + isread, false); |
260 | + case 0x2e4 ... AW_A10_DRAMC_IOSIZE: | 60 | + } else { |
261 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | 61 | + syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
262 | + __func__, (uint32_t)offset); | 62 | + rt, isread, false); |
63 | + } | ||
263 | + break; | 64 | + break; |
264 | + default: | 65 | + default: |
265 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", | 66 | + /* |
266 | + __func__, (uint32_t)offset); | 67 | + * ARMv8 defines that only coprocessors 14 and 15 exist, |
68 | + * so this can only happen if this is an ARMv7 or earlier CPU, | ||
69 | + * in which case the syndrome information won't actually be | ||
70 | + * guest visible. | ||
71 | + */ | ||
72 | + assert(!arm_dc_feature(s, ARM_FEATURE_V8)); | ||
73 | + syndrome = syn_uncategorized(); | ||
267 | + break; | 74 | + break; |
268 | + } | 75 | + } |
269 | + | 76 | |
270 | + s->regs[idx] = (uint32_t) val; | 77 | if (!ri) { |
271 | +} | 78 | /* |
272 | + | 79 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
273 | +static const MemoryRegionOps allwinner_a10_dramc_ops = { | 80 | * Note that on XScale all cp0..c13 registers do an access check |
274 | + .read = allwinner_a10_dramc_read, | 81 | * call in order to handle c15_cpar. |
275 | + .write = allwinner_a10_dramc_write, | 82 | */ |
276 | + .endianness = DEVICE_NATIVE_ENDIAN, | 83 | - uint32_t syndrome; |
277 | + .valid = { | 84 | - |
278 | + .min_access_size = 4, | 85 | - /* |
279 | + .max_access_size = 4, | 86 | - * Note that since we are an implementation which takes an |
280 | + }, | 87 | - * exception on a trapped conditional instruction only if the |
281 | + .impl.min_access_size = 4, | 88 | - * instruction passes its condition code check, we can take |
282 | +}; | 89 | - * advantage of the clause in the ARM ARM that allows us to set |
283 | + | 90 | - * the COND field in the instruction to 0xE in all cases. |
284 | +static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type) | 91 | - * We could fish the actual condition out of the insn (ARM) |
285 | +{ | 92 | - * or the condexec bits (Thumb) but it isn't necessary. |
286 | + AwA10DramControllerState *s = AW_A10_DRAMC(obj); | 93 | - */ |
287 | + | 94 | - switch (cpnum) { |
288 | + /* Set default values for registers */ | 95 | - case 14: |
289 | + s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET; | 96 | - if (is64) { |
290 | + s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET; | 97 | - syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
291 | + s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET; | 98 | - isread, false); |
292 | +} | 99 | - } else { |
293 | + | 100 | - syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
294 | +static void allwinner_a10_dramc_init(Object *obj) | 101 | - rt, isread, false); |
295 | +{ | 102 | - } |
296 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 103 | - break; |
297 | + AwA10DramControllerState *s = AW_A10_DRAMC(obj); | 104 | - case 15: |
298 | + | 105 | - if (is64) { |
299 | + /* Memory mapping */ | 106 | - syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, |
300 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s, | 107 | - isread, false); |
301 | + TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE); | 108 | - } else { |
302 | + sysbus_init_mmio(sbd, &s->iomem); | 109 | - syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, |
303 | +} | 110 | - rt, isread, false); |
304 | + | 111 | - } |
305 | +static const VMStateDescription allwinner_a10_dramc_vmstate = { | 112 | - break; |
306 | + .name = "allwinner-a10-dramc", | 113 | - default: |
307 | + .version_id = 1, | 114 | - /* |
308 | + .minimum_version_id = 1, | 115 | - * ARMv8 defines that only coprocessors 14 and 15 exist, |
309 | + .fields = (VMStateField[]) { | 116 | - * so this can only happen if this is an ARMv7 or earlier CPU, |
310 | + VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState, | 117 | - * in which case the syndrome information won't actually be |
311 | + AW_A10_DRAMC_REGS_NUM), | 118 | - * guest visible. |
312 | + VMSTATE_END_OF_LIST() | 119 | - */ |
313 | + } | 120 | - assert(!arm_dc_feature(s, ARM_FEATURE_V8)); |
314 | +}; | 121 | - syndrome = syn_uncategorized(); |
315 | + | 122 | - break; |
316 | +static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data) | 123 | - } |
317 | +{ | 124 | - |
318 | + DeviceClass *dc = DEVICE_CLASS(klass); | 125 | gen_set_condexec(s); |
319 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | 126 | gen_update_pc(s, 0); |
320 | + | 127 | tcg_ri = tcg_temp_new_ptr(); |
321 | + rc->phases.enter = allwinner_a10_dramc_reset_enter; | ||
322 | + dc->vmsd = &allwinner_a10_dramc_vmstate; | ||
323 | +} | ||
324 | + | ||
325 | +static const TypeInfo allwinner_a10_dramc_info = { | ||
326 | + .name = TYPE_AW_A10_DRAMC, | ||
327 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
328 | + .instance_init = allwinner_a10_dramc_init, | ||
329 | + .instance_size = sizeof(AwA10DramControllerState), | ||
330 | + .class_init = allwinner_a10_dramc_class_init, | ||
331 | +}; | ||
332 | + | ||
333 | +static void allwinner_a10_dramc_register(void) | ||
334 | +{ | ||
335 | + type_register_static(&allwinner_a10_dramc_info); | ||
336 | +} | ||
337 | + | ||
338 | +type_init(allwinner_a10_dramc_register) | ||
339 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
340 | index XXXXXXX..XXXXXXX 100644 | ||
341 | --- a/hw/arm/Kconfig | ||
342 | +++ b/hw/arm/Kconfig | ||
343 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | ||
344 | select ALLWINNER_A10_PIT | ||
345 | select ALLWINNER_A10_PIC | ||
346 | select ALLWINNER_A10_CCM | ||
347 | + select ALLWINNER_A10_DRAMC | ||
348 | select ALLWINNER_EMAC | ||
349 | select SERIAL | ||
350 | select UNIMP | ||
351 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
352 | index XXXXXXX..XXXXXXX 100644 | ||
353 | --- a/hw/misc/Kconfig | ||
354 | +++ b/hw/misc/Kconfig | ||
355 | @@ -XXX,XX +XXX,XX @@ config LASI | ||
356 | config ALLWINNER_A10_CCM | ||
357 | bool | ||
358 | |||
359 | +config ALLWINNER_A10_DRAMC | ||
360 | + bool | ||
361 | + | ||
362 | source macio/Kconfig | ||
363 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
364 | index XXXXXXX..XXXXXXX 100644 | ||
365 | --- a/hw/misc/meson.build | ||
366 | +++ b/hw/misc/meson.build | ||
367 | @@ -XXX,XX +XXX,XX @@ subdir('macio') | ||
368 | softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c')) | ||
369 | |||
370 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c')) | ||
371 | +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c')) | ||
372 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c')) | ||
373 | specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c')) | ||
374 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c')) | ||
375 | -- | 128 | -- |
376 | 2.34.1 | 129 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | The HSTR_EL2 register has a collection of trap bits which allow |
---|---|---|---|
2 | trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor | ||
3 | registers. The specification of these bits is that when the bit is | ||
4 | set we should trap | ||
5 | * EL1 accesses | ||
6 | * EL0 accesses, if the access is not UNDEFINED when the | ||
7 | trap bit is 0 | ||
2 | 8 | ||
3 | During SPL boot several Clock Controller Module (CCM) registers are | 9 | In other words, all UNDEF traps from EL0 to EL1 take precedence over |
4 | read, most important are PLL and Tuning, as well as divisor registers. | 10 | the HSTR_EL2 trap to EL2. (Since this is all AArch32, the only kind |
11 | of trap-to-EL1 is the UNDEF.) | ||
5 | 12 | ||
6 | This patch adds these registers and initializes reset values from user's | 13 | Our implementation doesn't quite get this right -- we check for traps |
7 | guide. | 14 | in the order: |
15 | * no such register | ||
16 | * ARMCPRegInfo::access bits | ||
17 | * HSTR_EL2 trap bits | ||
18 | * ARMCPRegInfo::accessfn | ||
8 | 19 | ||
9 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 20 | So UNDEFs that happen because of the access bits or because the |
21 | register doesn't exist at all correctly take priority over the | ||
22 | HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the | ||
23 | accessfn we are incorrectly always taking the HSTR_EL2 trap. There | ||
24 | aren't many of these, but one example is the PMCR; if you look at the | ||
25 | access pseudocode for this register you can see that UNDEFs taken | ||
26 | because of the value of PMUSERENR.EN are checked before the HSTR_EL2 | ||
27 | bit. | ||
10 | 28 | ||
11 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 29 | Rearrange helper_access_check_cp_reg() so that we always call the |
12 | Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com | 30 | accessfn, and use its return value if it indicates that the access |
31 | traps to EL0 rather than continuing to do the HSTR_EL2 check. | ||
32 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 33 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
34 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
35 | Tested-by: Fuad Tabba <tabba@google.com> | ||
36 | Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org | ||
37 | Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org | ||
14 | --- | 38 | --- |
15 | include/hw/arm/allwinner-a10.h | 2 + | 39 | target/arm/op_helper.c | 21 ++++++++++++++++----- |
16 | include/hw/misc/allwinner-a10-ccm.h | 67 +++++++++ | 40 | 1 file changed, 16 insertions(+), 5 deletions(-) |
17 | hw/arm/allwinner-a10.c | 7 + | ||
18 | hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++++++++++++++ | ||
19 | hw/arm/Kconfig | 1 + | ||
20 | hw/misc/Kconfig | 3 + | ||
21 | hw/misc/meson.build | 1 + | ||
22 | 7 files changed, 305 insertions(+) | ||
23 | create mode 100644 include/hw/misc/allwinner-a10-ccm.h | ||
24 | create mode 100644 hw/misc/allwinner-a10-ccm.c | ||
25 | 41 | ||
26 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | 42 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c |
27 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/include/hw/arm/allwinner-a10.h | 44 | --- a/target/arm/op_helper.c |
29 | +++ b/include/hw/arm/allwinner-a10.h | 45 | +++ b/target/arm/op_helper.c |
30 | @@ -XXX,XX +XXX,XX @@ | 46 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
31 | #include "hw/usb/hcd-ohci.h" | 47 | goto fail; |
32 | #include "hw/usb/hcd-ehci.h" | 48 | } |
33 | #include "hw/rtc/allwinner-rtc.h" | 49 | |
34 | +#include "hw/misc/allwinner-a10-ccm.h" | 50 | + if (ri->accessfn) { |
35 | 51 | + res = ri->accessfn(env, ri, isread); | |
36 | #include "target/arm/cpu.h" | ||
37 | #include "qom/object.h" | ||
38 | @@ -XXX,XX +XXX,XX @@ struct AwA10State { | ||
39 | /*< public >*/ | ||
40 | |||
41 | ARMCPU cpu; | ||
42 | + AwA10ClockCtlState ccm; | ||
43 | AwA10PITState timer; | ||
44 | AwA10PICState intc; | ||
45 | AwEmacState emac; | ||
46 | diff --git a/include/hw/misc/allwinner-a10-ccm.h b/include/hw/misc/allwinner-a10-ccm.h | ||
47 | new file mode 100644 | ||
48 | index XXXXXXX..XXXXXXX | ||
49 | --- /dev/null | ||
50 | +++ b/include/hw/misc/allwinner-a10-ccm.h | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | +/* | ||
53 | + * Allwinner A10 Clock Control Module emulation | ||
54 | + * | ||
55 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
56 | + * | ||
57 | + * This file is derived from Allwinner H3 CCU, | ||
58 | + * by Niek Linnenbank. | ||
59 | + * | ||
60 | + * This program is free software: you can redistribute it and/or modify | ||
61 | + * it under the terms of the GNU General Public License as published by | ||
62 | + * the Free Software Foundation, either version 2 of the License, or | ||
63 | + * (at your option) any later version. | ||
64 | + * | ||
65 | + * This program is distributed in the hope that it will be useful, | ||
66 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
67 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
68 | + * GNU General Public License for more details. | ||
69 | + * | ||
70 | + * You should have received a copy of the GNU General Public License | ||
71 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
72 | + */ | ||
73 | + | ||
74 | +#ifndef HW_MISC_ALLWINNER_A10_CCM_H | ||
75 | +#define HW_MISC_ALLWINNER_A10_CCM_H | ||
76 | + | ||
77 | +#include "qom/object.h" | ||
78 | +#include "hw/sysbus.h" | ||
79 | + | ||
80 | +/** | ||
81 | + * @name Constants | ||
82 | + * @{ | ||
83 | + */ | ||
84 | + | ||
85 | +/** Size of register I/O address space used by CCM device */ | ||
86 | +#define AW_A10_CCM_IOSIZE (0x400) | ||
87 | + | ||
88 | +/** Total number of known registers */ | ||
89 | +#define AW_A10_CCM_REGS_NUM (AW_A10_CCM_IOSIZE / sizeof(uint32_t)) | ||
90 | + | ||
91 | +/** @} */ | ||
92 | + | ||
93 | +/** | ||
94 | + * @name Object model | ||
95 | + * @{ | ||
96 | + */ | ||
97 | + | ||
98 | +#define TYPE_AW_A10_CCM "allwinner-a10-ccm" | ||
99 | +OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM) | ||
100 | + | ||
101 | +/** @} */ | ||
102 | + | ||
103 | +/** | ||
104 | + * Allwinner A10 CCM object instance state. | ||
105 | + */ | ||
106 | +struct AwA10ClockCtlState { | ||
107 | + /*< private >*/ | ||
108 | + SysBusDevice parent_obj; | ||
109 | + /*< public >*/ | ||
110 | + | ||
111 | + /** Maps I/O registers in physical memory */ | ||
112 | + MemoryRegion iomem; | ||
113 | + | ||
114 | + /** Array of hardware registers */ | ||
115 | + uint32_t regs[AW_A10_CCM_REGS_NUM]; | ||
116 | +}; | ||
117 | + | ||
118 | +#endif /* HW_MISC_ALLWINNER_H3_CCU_H */ | ||
119 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/hw/arm/allwinner-a10.c | ||
122 | +++ b/hw/arm/allwinner-a10.c | ||
123 | @@ -XXX,XX +XXX,XX @@ | ||
124 | #include "hw/usb/hcd-ohci.h" | ||
125 | |||
126 | #define AW_A10_MMC0_BASE 0x01c0f000 | ||
127 | +#define AW_A10_CCM_BASE 0x01c20000 | ||
128 | #define AW_A10_PIC_REG_BASE 0x01c20400 | ||
129 | #define AW_A10_PIT_REG_BASE 0x01c20c00 | ||
130 | #define AW_A10_UART0_REG_BASE 0x01c28000 | ||
131 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) | ||
132 | |||
133 | object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT); | ||
134 | |||
135 | + object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM); | ||
136 | + | ||
137 | object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); | ||
138 | |||
139 | object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); | ||
140 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | ||
141 | memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a); | ||
142 | create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB); | ||
143 | |||
144 | + /* Clock Control Module */ | ||
145 | + sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal); | ||
146 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE); | ||
147 | + | ||
148 | /* FIXME use qdev NIC properties instead of nd_table[] */ | ||
149 | if (nd_table[0].used) { | ||
150 | qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC); | ||
151 | diff --git a/hw/misc/allwinner-a10-ccm.c b/hw/misc/allwinner-a10-ccm.c | ||
152 | new file mode 100644 | ||
153 | index XXXXXXX..XXXXXXX | ||
154 | --- /dev/null | ||
155 | +++ b/hw/misc/allwinner-a10-ccm.c | ||
156 | @@ -XXX,XX +XXX,XX @@ | ||
157 | +/* | ||
158 | + * Allwinner A10 Clock Control Module emulation | ||
159 | + * | ||
160 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
161 | + * | ||
162 | + * This file is derived from Allwinner H3 CCU, | ||
163 | + * by Niek Linnenbank. | ||
164 | + * | ||
165 | + * This program is free software: you can redistribute it and/or modify | ||
166 | + * it under the terms of the GNU General Public License as published by | ||
167 | + * the Free Software Foundation, either version 2 of the License, or | ||
168 | + * (at your option) any later version. | ||
169 | + * | ||
170 | + * This program is distributed in the hope that it will be useful, | ||
171 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
172 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
173 | + * GNU General Public License for more details. | ||
174 | + * | ||
175 | + * You should have received a copy of the GNU General Public License | ||
176 | + * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
177 | + */ | ||
178 | + | ||
179 | +#include "qemu/osdep.h" | ||
180 | +#include "qemu/units.h" | ||
181 | +#include "hw/sysbus.h" | ||
182 | +#include "migration/vmstate.h" | ||
183 | +#include "qemu/log.h" | ||
184 | +#include "qemu/module.h" | ||
185 | +#include "hw/misc/allwinner-a10-ccm.h" | ||
186 | + | ||
187 | +/* CCM register offsets */ | ||
188 | +enum { | ||
189 | + REG_PLL1_CFG = 0x0000, /* PLL1 Control */ | ||
190 | + REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */ | ||
191 | + REG_PLL2_CFG = 0x0008, /* PLL2 Control */ | ||
192 | + REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */ | ||
193 | + REG_PLL3_CFG = 0x0010, /* PLL3 Control */ | ||
194 | + REG_PLL4_CFG = 0x0018, /* PLL4 Control */ | ||
195 | + REG_PLL5_CFG = 0x0020, /* PLL5 Control */ | ||
196 | + REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */ | ||
197 | + REG_PLL6_CFG = 0x0028, /* PLL6 Control */ | ||
198 | + REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */ | ||
199 | + REG_PLL7_CFG = 0x0030, /* PLL7 Control */ | ||
200 | + REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */ | ||
201 | + REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */ | ||
202 | + REG_PLL8_CFG = 0x0040, /* PLL8 Control */ | ||
203 | + REG_OSC24M_CFG = 0x0050, /* OSC24M Control */ | ||
204 | + REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */ | ||
205 | +}; | ||
206 | + | ||
207 | +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) | ||
208 | + | ||
209 | +/* CCM register reset values */ | ||
210 | +enum { | ||
211 | + REG_PLL1_CFG_RST = 0x21005000, | ||
212 | + REG_PLL1_TUN_RST = 0x0A101000, | ||
213 | + REG_PLL2_CFG_RST = 0x08100010, | ||
214 | + REG_PLL2_TUN_RST = 0x00000000, | ||
215 | + REG_PLL3_CFG_RST = 0x0010D063, | ||
216 | + REG_PLL4_CFG_RST = 0x21009911, | ||
217 | + REG_PLL5_CFG_RST = 0x11049280, | ||
218 | + REG_PLL5_TUN_RST = 0x14888000, | ||
219 | + REG_PLL6_CFG_RST = 0x21009911, | ||
220 | + REG_PLL6_TUN_RST = 0x00000000, | ||
221 | + REG_PLL7_CFG_RST = 0x0010D063, | ||
222 | + REG_PLL1_TUN2_RST = 0x00000000, | ||
223 | + REG_PLL5_TUN2_RST = 0x00000000, | ||
224 | + REG_PLL8_CFG_RST = 0x21009911, | ||
225 | + REG_OSC24M_CFG_RST = 0x00138013, | ||
226 | + REG_CPU_AHB_APB0_CFG_RST = 0x00010010, | ||
227 | +}; | ||
228 | + | ||
229 | +static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset, | ||
230 | + unsigned size) | ||
231 | +{ | ||
232 | + const AwA10ClockCtlState *s = AW_A10_CCM(opaque); | ||
233 | + const uint32_t idx = REG_INDEX(offset); | ||
234 | + | ||
235 | + switch (offset) { | ||
236 | + case REG_PLL1_CFG: | ||
237 | + case REG_PLL1_TUN: | ||
238 | + case REG_PLL2_CFG: | ||
239 | + case REG_PLL2_TUN: | ||
240 | + case REG_PLL3_CFG: | ||
241 | + case REG_PLL4_CFG: | ||
242 | + case REG_PLL5_CFG: | ||
243 | + case REG_PLL5_TUN: | ||
244 | + case REG_PLL6_CFG: | ||
245 | + case REG_PLL6_TUN: | ||
246 | + case REG_PLL7_CFG: | ||
247 | + case REG_PLL1_TUN2: | ||
248 | + case REG_PLL5_TUN2: | ||
249 | + case REG_PLL8_CFG: | ||
250 | + case REG_OSC24M_CFG: | ||
251 | + case REG_CPU_AHB_APB0_CFG: | ||
252 | + break; | ||
253 | + case 0x158 ... AW_A10_CCM_IOSIZE: | ||
254 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
255 | + __func__, (uint32_t)offset); | ||
256 | + return 0; | ||
257 | + default: | ||
258 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n", | ||
259 | + __func__, (uint32_t)offset); | ||
260 | + return 0; | ||
261 | + } | 52 | + } |
262 | + | 53 | + |
263 | + return s->regs[idx]; | 54 | /* |
264 | +} | 55 | - * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses |
265 | + | 56 | - * to sysregs non accessible at EL0 to have UNDEF-ed already. |
266 | +static void allwinner_a10_ccm_write(void *opaque, hwaddr offset, | 57 | + * If the access function indicates a trap from EL0 to EL1 then |
267 | + uint64_t val, unsigned size) | 58 | + * that always takes priority over the HSTR_EL2 trap. (If it indicates |
268 | +{ | 59 | + * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates |
269 | + AwA10ClockCtlState *s = AW_A10_CCM(opaque); | 60 | + * a trap to EL2, then the syndrome is the same either way so we don't |
270 | + const uint32_t idx = REG_INDEX(offset); | 61 | + * care whether technically the architecture says that HSTR_EL2 trap or |
271 | + | 62 | + * the other trap takes priority. So we take the "check HSTR_EL2" path |
272 | + switch (offset) { | 63 | + * for all of those cases.) |
273 | + case REG_PLL1_CFG: | 64 | */ |
274 | + case REG_PLL1_TUN: | 65 | + if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) && |
275 | + case REG_PLL2_CFG: | 66 | + arm_current_el(env) == 0) { |
276 | + case REG_PLL2_TUN: | 67 | + goto fail; |
277 | + case REG_PLL3_CFG: | ||
278 | + case REG_PLL4_CFG: | ||
279 | + case REG_PLL5_CFG: | ||
280 | + case REG_PLL5_TUN: | ||
281 | + case REG_PLL6_CFG: | ||
282 | + case REG_PLL6_TUN: | ||
283 | + case REG_PLL7_CFG: | ||
284 | + case REG_PLL1_TUN2: | ||
285 | + case REG_PLL5_TUN2: | ||
286 | + case REG_PLL8_CFG: | ||
287 | + case REG_OSC24M_CFG: | ||
288 | + case REG_CPU_AHB_APB0_CFG: | ||
289 | + break; | ||
290 | + case 0x158 ... AW_A10_CCM_IOSIZE: | ||
291 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n", | ||
292 | + __func__, (uint32_t)offset); | ||
293 | + break; | ||
294 | + default: | ||
295 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n", | ||
296 | + __func__, (uint32_t)offset); | ||
297 | + break; | ||
298 | + } | 68 | + } |
299 | + | 69 | + |
300 | + s->regs[idx] = (uint32_t) val; | 70 | if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 && |
301 | +} | 71 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
302 | + | 72 | uint32_t mask = 1 << ri->crn; |
303 | +static const MemoryRegionOps allwinner_a10_ccm_ops = { | 73 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
304 | + .read = allwinner_a10_ccm_read, | 74 | } |
305 | + .write = allwinner_a10_ccm_write, | 75 | } |
306 | + .endianness = DEVICE_NATIVE_ENDIAN, | 76 | |
307 | + .valid = { | 77 | - if (ri->accessfn) { |
308 | + .min_access_size = 4, | 78 | - res = ri->accessfn(env, ri, isread); |
309 | + .max_access_size = 4, | 79 | - } |
310 | + }, | 80 | if (likely(res == CP_ACCESS_OK)) { |
311 | + .impl.min_access_size = 4, | 81 | return ri; |
312 | +}; | 82 | } |
313 | + | ||
314 | +static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type) | ||
315 | +{ | ||
316 | + AwA10ClockCtlState *s = AW_A10_CCM(obj); | ||
317 | + | ||
318 | + /* Set default values for registers */ | ||
319 | + s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST; | ||
320 | + s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST; | ||
321 | + s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST; | ||
322 | + s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST; | ||
323 | + s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST; | ||
324 | + s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST; | ||
325 | + s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST; | ||
326 | + s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST; | ||
327 | + s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST; | ||
328 | + s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST; | ||
329 | + s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST; | ||
330 | + s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST; | ||
331 | + s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST; | ||
332 | + s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST; | ||
333 | + s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST; | ||
334 | + s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST; | ||
335 | +} | ||
336 | + | ||
337 | +static void allwinner_a10_ccm_init(Object *obj) | ||
338 | +{ | ||
339 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
340 | + AwA10ClockCtlState *s = AW_A10_CCM(obj); | ||
341 | + | ||
342 | + /* Memory mapping */ | ||
343 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s, | ||
344 | + TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE); | ||
345 | + sysbus_init_mmio(sbd, &s->iomem); | ||
346 | +} | ||
347 | + | ||
348 | +static const VMStateDescription allwinner_a10_ccm_vmstate = { | ||
349 | + .name = "allwinner-a10-ccm", | ||
350 | + .version_id = 1, | ||
351 | + .minimum_version_id = 1, | ||
352 | + .fields = (VMStateField[]) { | ||
353 | + VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM), | ||
354 | + VMSTATE_END_OF_LIST() | ||
355 | + } | ||
356 | +}; | ||
357 | + | ||
358 | +static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data) | ||
359 | +{ | ||
360 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
361 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
362 | + | ||
363 | + rc->phases.enter = allwinner_a10_ccm_reset_enter; | ||
364 | + dc->vmsd = &allwinner_a10_ccm_vmstate; | ||
365 | +} | ||
366 | + | ||
367 | +static const TypeInfo allwinner_a10_ccm_info = { | ||
368 | + .name = TYPE_AW_A10_CCM, | ||
369 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
370 | + .instance_init = allwinner_a10_ccm_init, | ||
371 | + .instance_size = sizeof(AwA10ClockCtlState), | ||
372 | + .class_init = allwinner_a10_ccm_class_init, | ||
373 | +}; | ||
374 | + | ||
375 | +static void allwinner_a10_ccm_register(void) | ||
376 | +{ | ||
377 | + type_register_static(&allwinner_a10_ccm_info); | ||
378 | +} | ||
379 | + | ||
380 | +type_init(allwinner_a10_ccm_register) | ||
381 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
382 | index XXXXXXX..XXXXXXX 100644 | ||
383 | --- a/hw/arm/Kconfig | ||
384 | +++ b/hw/arm/Kconfig | ||
385 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | ||
386 | select AHCI | ||
387 | select ALLWINNER_A10_PIT | ||
388 | select ALLWINNER_A10_PIC | ||
389 | + select ALLWINNER_A10_CCM | ||
390 | select ALLWINNER_EMAC | ||
391 | select SERIAL | ||
392 | select UNIMP | ||
393 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
394 | index XXXXXXX..XXXXXXX 100644 | ||
395 | --- a/hw/misc/Kconfig | ||
396 | +++ b/hw/misc/Kconfig | ||
397 | @@ -XXX,XX +XXX,XX @@ config VIRT_CTRL | ||
398 | config LASI | ||
399 | bool | ||
400 | |||
401 | +config ALLWINNER_A10_CCM | ||
402 | + bool | ||
403 | + | ||
404 | source macio/Kconfig | ||
405 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
406 | index XXXXXXX..XXXXXXX 100644 | ||
407 | --- a/hw/misc/meson.build | ||
408 | +++ b/hw/misc/meson.build | ||
409 | @@ -XXX,XX +XXX,XX @@ subdir('macio') | ||
410 | |||
411 | softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c')) | ||
412 | |||
413 | +softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c')) | ||
414 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c')) | ||
415 | specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c')) | ||
416 | softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c')) | ||
417 | -- | 83 | -- |
418 | 2.34.1 | 84 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | The semantics of HSTR_EL2 require that it traps cpreg accesses |
---|---|---|---|
2 | to EL2 for: | ||
3 | * EL1 accesses | ||
4 | * EL0 accesses, if the access is not UNDEFINED when the | ||
5 | trap bit is 0 | ||
2 | 6 | ||
3 | Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x: | 7 | (You can see this in the I_ZFGJP priority ordering, where HSTR_EL2 |
4 | QOMified") the pflash_cfi01_register() function does not fail. | 8 | traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and |
9 | HSTR_EL2 traps from EL0 are priority 15.) | ||
5 | 10 | ||
6 | This call was later converted with a script to use &error_fatal, | 11 | However, we don't get this right for EL1 accesses which UNDEF because |
7 | still unable to fail. Remove the unreachable code. | 12 | the register doesn't exist at all or because its ri->access bits |
13 | non-configurably forbid the access. At EL1, check for the HSTR_EL2 | ||
14 | trap early, before either of these UNDEF reasons. | ||
8 | 15 | ||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 16 | We have to retain the HSTR_EL2 check in access_check_cp_reg(), |
17 | because at EL0 any kind of UNDEF-to-EL1 (including "no such | ||
18 | register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'") | ||
19 | takes precedence over the trap to EL2. But we only need to do that | ||
20 | check for EL0 now. | ||
21 | |||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | Tested-by: Fuad Tabba <tabba@google.com> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20230109115316.2235-14-philmd@linaro.org | 25 | Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org |
13 | --- | 27 | --- |
14 | hw/arm/gumstix.c | 18 ++++++------------ | 28 | target/arm/op_helper.c | 6 +++++- |
15 | hw/arm/mainstone.c | 13 +++++-------- | 29 | target/arm/translate.c | 28 +++++++++++++++++++++++++++- |
16 | hw/arm/omap_sx1.c | 22 ++++++++-------------- | 30 | 2 files changed, 32 insertions(+), 2 deletions(-) |
17 | hw/arm/versatilepb.c | 6 ++---- | ||
18 | hw/arm/z2.c | 9 +++------ | ||
19 | 5 files changed, 24 insertions(+), 44 deletions(-) | ||
20 | 31 | ||
21 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | 32 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c |
22 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/gumstix.c | 34 | --- a/target/arm/op_helper.c |
24 | +++ b/hw/arm/gumstix.c | 35 | +++ b/target/arm/op_helper.c |
25 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | 36 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
37 | goto fail; | ||
26 | } | 38 | } |
27 | 39 | ||
28 | /* Numonyx RC28F128J3F75 */ | 40 | - if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 && |
29 | - if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE, | 41 | + /* |
30 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 42 | + * HSTR_EL2 traps from EL1 are checked earlier, in generated code; |
31 | - FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) { | 43 | + * we only need to check here for traps from EL0. |
32 | - error_report("Error registering flash memory"); | 44 | + */ |
33 | - exit(1); | 45 | + if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && |
34 | - } | 46 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
35 | + pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE, | 47 | uint32_t mask = 1 << ri->crn; |
36 | + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 48 | |
37 | + FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0); | 49 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
38 | 50 | index XXXXXXX..XXXXXXX 100644 | |
39 | /* Interrupt line of NIC is connected to GPIO line 36 */ | 51 | --- a/target/arm/translate.c |
40 | smc91c111_init(&nd_table[0], 0x04000300, | 52 | +++ b/target/arm/translate.c |
41 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | 53 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
54 | break; | ||
42 | } | 55 | } |
43 | 56 | ||
44 | /* Micron RC28F256P30TFA */ | 57 | + if (s->hstr_active && cpnum == 15 && s->current_el == 1) { |
45 | - if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE, | 58 | + /* |
46 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 59 | + * At EL1, check for a HSTR_EL2 trap, which must take precedence |
47 | - FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) { | 60 | + * over the UNDEF for "no such register" or the UNDEF for "access |
48 | - error_report("Error registering flash memory"); | 61 | + * permissions forbid this EL1 access". HSTR_EL2 traps from EL0 |
49 | - exit(1); | 62 | + * only happen if the cpreg doesn't UNDEF at EL0, so we do those in |
50 | - } | 63 | + * access_check_cp_reg(), after the checks for whether the access |
51 | + pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE, | 64 | + * configurably trapped to EL1. |
52 | + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 65 | + */ |
53 | + FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0); | 66 | + uint32_t maskbit = is64 ? crm : crn; |
54 | 67 | + | |
55 | /* Interrupt line of NIC is connected to GPIO line 99 */ | 68 | + if (maskbit != 4 && maskbit != 14) { |
56 | smc91c111_init(&nd_table[0], 0x04000300, | 69 | + /* T4 and T14 are RES0 so never cause traps */ |
57 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | 70 | + TCGv_i32 t; |
58 | index XXXXXXX..XXXXXXX 100644 | 71 | + DisasLabel over = gen_disas_label(s); |
59 | --- a/hw/arm/mainstone.c | 72 | + |
60 | +++ b/hw/arm/mainstone.c | 73 | + t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2)); |
61 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine, | 74 | + tcg_gen_andi_i32(t, t, 1u << maskbit); |
62 | /* There are two 32MiB flash devices on the board */ | 75 | + tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); |
63 | for (i = 0; i < 2; i ++) { | 76 | + tcg_temp_free_i32(t); |
64 | dinfo = drive_get(IF_PFLASH, 0, i); | 77 | + |
65 | - if (!pflash_cfi01_register(mainstone_flash_base[i], | 78 | + gen_exception_insn(s, 0, EXCP_UDEF, syndrome); |
66 | - i ? "mainstone.flash1" : "mainstone.flash0", | 79 | + set_disas_label(s, over); |
67 | - MAINSTONE_FLASH_SIZE, | 80 | + } |
68 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 81 | + } |
69 | - FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | 82 | + |
70 | - error_report("Error registering flash memory"); | 83 | if (!ri) { |
71 | - exit(1); | 84 | /* |
72 | - } | 85 | * Unknown register; this might be a guest error or a QEMU |
73 | + pflash_cfi01_register(mainstone_flash_base[i], | 86 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
74 | + i ? "mainstone.flash1" : "mainstone.flash0", | 87 | return; |
75 | + MAINSTONE_FLASH_SIZE, | ||
76 | + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
77 | + FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0); | ||
78 | } | 88 | } |
79 | 89 | ||
80 | mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS, | 90 | - if (s->hstr_active || ri->accessfn || |
81 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | 91 | + if ((s->hstr_active && s->current_el == 0) || ri->accessfn || |
82 | index XXXXXXX..XXXXXXX 100644 | 92 | (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { |
83 | --- a/hw/arm/omap_sx1.c | 93 | /* |
84 | +++ b/hw/arm/omap_sx1.c | 94 | * Emit code to perform further access permissions checks at |
85 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
86 | |||
87 | fl_idx = 0; | ||
88 | if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { | ||
89 | - if (!pflash_cfi01_register(OMAP_CS0_BASE, | ||
90 | - "omap_sx1.flash0-1", flash_size, | ||
91 | - blk_by_legacy_dinfo(dinfo), | ||
92 | - SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
93 | - fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
94 | - fl_idx); | ||
95 | - } | ||
96 | + pflash_cfi01_register(OMAP_CS0_BASE, | ||
97 | + "omap_sx1.flash0-1", flash_size, | ||
98 | + blk_by_legacy_dinfo(dinfo), | ||
99 | + SECTOR_SIZE, 4, 0, 0, 0, 0, 0); | ||
100 | fl_idx++; | ||
101 | } | ||
102 | |||
103 | @@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version) | ||
104 | memory_region_add_subregion(address_space, | ||
105 | OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]); | ||
106 | |||
107 | - if (!pflash_cfi01_register(OMAP_CS1_BASE, | ||
108 | - "omap_sx1.flash1-1", FLASH1_SIZE, | ||
109 | - blk_by_legacy_dinfo(dinfo), | ||
110 | - SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
111 | - fprintf(stderr, "qemu: Error registering flash memory %d.\n", | ||
112 | - fl_idx); | ||
113 | - } | ||
114 | + pflash_cfi01_register(OMAP_CS1_BASE, | ||
115 | + "omap_sx1.flash1-1", FLASH1_SIZE, | ||
116 | + blk_by_legacy_dinfo(dinfo), | ||
117 | + SECTOR_SIZE, 4, 0, 0, 0, 0, 0); | ||
118 | fl_idx++; | ||
119 | } else { | ||
120 | memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, | ||
121 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/hw/arm/versatilepb.c | ||
124 | +++ b/hw/arm/versatilepb.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id) | ||
126 | /* 0x34000000 NOR Flash */ | ||
127 | |||
128 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
129 | - if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", | ||
130 | + pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", | ||
131 | VERSATILE_FLASH_SIZE, | ||
132 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
133 | VERSATILE_FLASH_SECT_SIZE, | ||
134 | - 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { | ||
135 | - fprintf(stderr, "qemu: Error registering flash memory.\n"); | ||
136 | - } | ||
137 | + 4, 0x0089, 0x0018, 0x0000, 0x0, 0); | ||
138 | |||
139 | versatile_binfo.ram_size = machine->ram_size; | ||
140 | versatile_binfo.board_id = board_id; | ||
141 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
142 | index XXXXXXX..XXXXXXX 100644 | ||
143 | --- a/hw/arm/z2.c | ||
144 | +++ b/hw/arm/z2.c | ||
145 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) | ||
146 | mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type); | ||
147 | |||
148 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
149 | - if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, | ||
150 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
151 | - FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
152 | - error_report("Error registering flash memory"); | ||
153 | - exit(1); | ||
154 | - } | ||
155 | + pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, | ||
156 | + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
157 | + FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0); | ||
158 | |||
159 | /* setup keypad */ | ||
160 | pxa27x_register_keypad(mpu->kp, map, 0x100); | ||
161 | -- | 95 | -- |
162 | 2.34.1 | 96 | 2.34.1 |
163 | |||
164 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | The HSTR_EL2 register is not supposed to have an effect unless EL2 is |
---|---|---|---|
2 | enabled in the current security state. We weren't checking for this, | ||
3 | which meant that if the guest set up the HSTR_EL2 register we would | ||
4 | incorrectly trap even for accesses from Secure EL0 and EL1. | ||
2 | 5 | ||
3 | SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus. | 6 | Add the missing checks. (Other places where we look at HSTR_EL2 |
7 | for the not-in-v8A bits TTEE and TJDBX are already checking that | ||
8 | we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.) | ||
4 | 9 | ||
5 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Tested-by: Fuad Tabba <tabba@google.com> | ||
13 | Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org | ||
14 | Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/arm/helper.c | 2 +- | ||
17 | target/arm/op_helper.c | 1 + | ||
18 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
6 | 19 | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 20 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
8 | Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/arm/cubieboard.c | 6 ++++++ | ||
12 | hw/arm/Kconfig | 1 + | ||
13 | 2 files changed, 7 insertions(+) | ||
14 | |||
15 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/cubieboard.c | 22 | --- a/target/arm/helper.c |
18 | +++ b/hw/arm/cubieboard.c | 23 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
20 | #include "hw/boards.h" | 25 | DP_TBFLAG_A32(flags, VFPEN, 1); |
21 | #include "hw/qdev-properties.h" | ||
22 | #include "hw/arm/allwinner-a10.h" | ||
23 | +#include "hw/i2c/i2c.h" | ||
24 | |||
25 | static struct arm_boot_info cubieboard_binfo = { | ||
26 | .loader_start = AW_A10_SDRAM_BASE, | ||
27 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | ||
28 | BlockBackend *blk; | ||
29 | BusState *bus; | ||
30 | DeviceState *carddev; | ||
31 | + I2CBus *i2c; | ||
32 | |||
33 | /* BIOS is not supported by this board */ | ||
34 | if (machine->firmware) { | ||
35 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | ||
36 | exit(1); | ||
37 | } | 26 | } |
38 | 27 | ||
39 | + /* Connect AXP 209 */ | 28 | - if (el < 2 && env->cp15.hstr_el2 && |
40 | + i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c")); | 29 | + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && |
41 | + i2c_slave_create_simple(i2c, "axp209_pmu", 0x34); | 30 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
42 | + | 31 | DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); |
43 | /* Retrieve SD bus */ | 32 | } |
44 | di = drive_get(IF_SD, 0, 0); | 33 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c |
45 | blk = di ? blk_by_legacy_dinfo(di) : NULL; | ||
46 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
47 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/hw/arm/Kconfig | 35 | --- a/target/arm/op_helper.c |
49 | +++ b/hw/arm/Kconfig | 36 | +++ b/target/arm/op_helper.c |
50 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | 37 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
51 | select ALLWINNER_A10_DRAMC | 38 | * we only need to check here for traps from EL0. |
52 | select ALLWINNER_EMAC | 39 | */ |
53 | select ALLWINNER_I2C | 40 | if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 && |
54 | + select AXP209_PMU | 41 | + arm_is_el2_enabled(env) && |
55 | select SERIAL | 42 | (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { |
56 | select UNIMP | 43 | uint32_t mask = 1 << ri->crn; |
57 | 44 | ||
58 | -- | 45 | -- |
59 | 2.34.1 | 46 | 2.34.1 |
60 | |||
61 | diff view generated by jsdifflib |
1 | From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | 1 | Define the system registers which are provided by the |
---|---|---|---|
2 | 2 | FEAT_FGT fine-grained trap architectural feature: | |
3 | ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit | 3 | HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2 |
4 | to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu | 4 | |
5 | uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 | 5 | All these registers are a set of bit fields, where each bit is set |
6 | write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is | 6 | for a trap and clear to not trap on a particular system register |
7 | enabled and exposed to the guest. As a result EL3 writes of that bit are | 7 | access. The R and W register pairs are for system registers, |
8 | ignored. | 8 | allowing trapping to be done separately for reads and writes; the I |
9 | 9 | register is for system instructions where trapping is on instruction | |
10 | Cc: qemu-stable@nongnu.org | 10 | execution. |
11 | Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> | 11 | |
12 | Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com | 12 | The data storage in the CPU state struct is arranged as a set of |
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | arrays rather than separate fields so that when we're looking up the |
14 | bits for a system register access we can just index into the array | ||
15 | rather than having to use a switch to select a named struct member. | ||
16 | The later FEAT_FGT2 will add extra elements to these arrays. | ||
17 | |||
18 | The field definitions for the new registers are in cpregs.h because | ||
19 | in practice the code that needs them is code that also needs | ||
20 | the cpregs information; cpu.h is included in a lot more files. | ||
21 | We're also going to add some FGT-specific definitions to cpregs.h | ||
22 | in the next commit. | ||
23 | |||
24 | We do not implement HAFGRTR_EL2, because we don't implement | ||
25 | FEAT_AMUv1. | ||
26 | |||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
29 | Tested-by: Fuad Tabba <tabba@google.com> | ||
30 | Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org | ||
31 | Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org | ||
15 | --- | 32 | --- |
16 | target/arm/helper.c | 3 +++ | 33 | target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++ |
17 | 1 file changed, 3 insertions(+) | 34 | target/arm/cpu.h | 15 +++ |
18 | 35 | target/arm/helper.c | 40 +++++++ | |
36 | 3 files changed, 340 insertions(+) | ||
37 | |||
38 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/cpregs.h | ||
41 | +++ b/target/arm/cpregs.h | ||
42 | @@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult { | ||
43 | CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2), | ||
44 | } CPAccessResult; | ||
45 | |||
46 | +/* Indexes into fgt_read[] */ | ||
47 | +#define FGTREG_HFGRTR 0 | ||
48 | +#define FGTREG_HDFGRTR 1 | ||
49 | +/* Indexes into fgt_write[] */ | ||
50 | +#define FGTREG_HFGWTR 0 | ||
51 | +#define FGTREG_HDFGWTR 1 | ||
52 | +/* Indexes into fgt_exec[] */ | ||
53 | +#define FGTREG_HFGITR 0 | ||
54 | + | ||
55 | +FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) | ||
56 | +FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1) | ||
57 | +FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1) | ||
58 | +FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1) | ||
59 | +FIELD(HFGRTR_EL2, APDAKEY, 4, 1) | ||
60 | +FIELD(HFGRTR_EL2, APDBKEY, 5, 1) | ||
61 | +FIELD(HFGRTR_EL2, APGAKEY, 6, 1) | ||
62 | +FIELD(HFGRTR_EL2, APIAKEY, 7, 1) | ||
63 | +FIELD(HFGRTR_EL2, APIBKEY, 8, 1) | ||
64 | +FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1) | ||
65 | +FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1) | ||
66 | +FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1) | ||
67 | +FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1) | ||
68 | +FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1) | ||
69 | +FIELD(HFGRTR_EL2, CTR_EL0, 14, 1) | ||
70 | +FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1) | ||
71 | +FIELD(HFGRTR_EL2, ESR_EL1, 16, 1) | ||
72 | +FIELD(HFGRTR_EL2, FAR_EL1, 17, 1) | ||
73 | +FIELD(HFGRTR_EL2, ISR_EL1, 18, 1) | ||
74 | +FIELD(HFGRTR_EL2, LORC_EL1, 19, 1) | ||
75 | +FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1) | ||
76 | +FIELD(HFGRTR_EL2, LORID_EL1, 21, 1) | ||
77 | +FIELD(HFGRTR_EL2, LORN_EL1, 22, 1) | ||
78 | +FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1) | ||
79 | +FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1) | ||
80 | +FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1) | ||
81 | +FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1) | ||
82 | +FIELD(HFGRTR_EL2, PAR_EL1, 27, 1) | ||
83 | +FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1) | ||
84 | +FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1) | ||
85 | +FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1) | ||
86 | +FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1) | ||
87 | +FIELD(HFGRTR_EL2, TCR_EL1, 32, 1) | ||
88 | +FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1) | ||
89 | +FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1) | ||
90 | +FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1) | ||
91 | +FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1) | ||
92 | +FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1) | ||
93 | +FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1) | ||
94 | +FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1) | ||
95 | +FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1) | ||
96 | +FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1) | ||
97 | +FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1) | ||
98 | +FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1) | ||
99 | +FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1) | ||
100 | +FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1) | ||
101 | +FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1) | ||
102 | +FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) | ||
103 | +FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) | ||
104 | +FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) | ||
105 | +FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) | ||
106 | +/* 51-53: RES0 */ | ||
107 | +FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) | ||
108 | +FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) | ||
109 | +/* 56-63: RES0 */ | ||
110 | + | ||
111 | +/* These match HFGRTR but bits for RO registers are RES0 */ | ||
112 | +FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) | ||
113 | +FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1) | ||
114 | +FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1) | ||
115 | +FIELD(HFGWTR_EL2, APDAKEY, 4, 1) | ||
116 | +FIELD(HFGWTR_EL2, APDBKEY, 5, 1) | ||
117 | +FIELD(HFGWTR_EL2, APGAKEY, 6, 1) | ||
118 | +FIELD(HFGWTR_EL2, APIAKEY, 7, 1) | ||
119 | +FIELD(HFGWTR_EL2, APIBKEY, 8, 1) | ||
120 | +FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1) | ||
121 | +FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1) | ||
122 | +FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1) | ||
123 | +FIELD(HFGWTR_EL2, ESR_EL1, 16, 1) | ||
124 | +FIELD(HFGWTR_EL2, FAR_EL1, 17, 1) | ||
125 | +FIELD(HFGWTR_EL2, LORC_EL1, 19, 1) | ||
126 | +FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1) | ||
127 | +FIELD(HFGWTR_EL2, LORN_EL1, 22, 1) | ||
128 | +FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1) | ||
129 | +FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1) | ||
130 | +FIELD(HFGWTR_EL2, PAR_EL1, 27, 1) | ||
131 | +FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1) | ||
132 | +FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1) | ||
133 | +FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1) | ||
134 | +FIELD(HFGWTR_EL2, TCR_EL1, 32, 1) | ||
135 | +FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1) | ||
136 | +FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1) | ||
137 | +FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1) | ||
138 | +FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1) | ||
139 | +FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1) | ||
140 | +FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1) | ||
141 | +FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1) | ||
142 | +FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1) | ||
143 | +FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1) | ||
144 | +FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1) | ||
145 | +FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1) | ||
146 | +FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) | ||
147 | +FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) | ||
148 | +FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) | ||
149 | +FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) | ||
150 | +FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) | ||
151 | +FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) | ||
152 | + | ||
153 | +FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) | ||
154 | +FIELD(HFGITR_EL2, ICIALLU, 1, 1) | ||
155 | +FIELD(HFGITR_EL2, ICIVAU, 2, 1) | ||
156 | +FIELD(HFGITR_EL2, DCIVAC, 3, 1) | ||
157 | +FIELD(HFGITR_EL2, DCISW, 4, 1) | ||
158 | +FIELD(HFGITR_EL2, DCCSW, 5, 1) | ||
159 | +FIELD(HFGITR_EL2, DCCISW, 6, 1) | ||
160 | +FIELD(HFGITR_EL2, DCCVAU, 7, 1) | ||
161 | +FIELD(HFGITR_EL2, DCCVAP, 8, 1) | ||
162 | +FIELD(HFGITR_EL2, DCCVADP, 9, 1) | ||
163 | +FIELD(HFGITR_EL2, DCCIVAC, 10, 1) | ||
164 | +FIELD(HFGITR_EL2, DCZVA, 11, 1) | ||
165 | +FIELD(HFGITR_EL2, ATS1E1R, 12, 1) | ||
166 | +FIELD(HFGITR_EL2, ATS1E1W, 13, 1) | ||
167 | +FIELD(HFGITR_EL2, ATS1E0R, 14, 1) | ||
168 | +FIELD(HFGITR_EL2, ATS1E0W, 15, 1) | ||
169 | +FIELD(HFGITR_EL2, ATS1E1RP, 16, 1) | ||
170 | +FIELD(HFGITR_EL2, ATS1E1WP, 17, 1) | ||
171 | +FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1) | ||
172 | +FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1) | ||
173 | +FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1) | ||
174 | +FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1) | ||
175 | +FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1) | ||
176 | +FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1) | ||
177 | +FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1) | ||
178 | +FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1) | ||
179 | +FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1) | ||
180 | +FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1) | ||
181 | +FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1) | ||
182 | +FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1) | ||
183 | +FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1) | ||
184 | +FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1) | ||
185 | +FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1) | ||
186 | +FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1) | ||
187 | +FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1) | ||
188 | +FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1) | ||
189 | +FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1) | ||
190 | +FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1) | ||
191 | +FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1) | ||
192 | +FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1) | ||
193 | +FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1) | ||
194 | +FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1) | ||
195 | +FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1) | ||
196 | +FIELD(HFGITR_EL2, TLBIVAE1, 43, 1) | ||
197 | +FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1) | ||
198 | +FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1) | ||
199 | +FIELD(HFGITR_EL2, TLBIVALE1, 46, 1) | ||
200 | +FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1) | ||
201 | +FIELD(HFGITR_EL2, CFPRCTX, 48, 1) | ||
202 | +FIELD(HFGITR_EL2, DVPRCTX, 49, 1) | ||
203 | +FIELD(HFGITR_EL2, CPPRCTX, 50, 1) | ||
204 | +FIELD(HFGITR_EL2, ERET, 51, 1) | ||
205 | +FIELD(HFGITR_EL2, SVC_EL0, 52, 1) | ||
206 | +FIELD(HFGITR_EL2, SVC_EL1, 53, 1) | ||
207 | +FIELD(HFGITR_EL2, DCCVAC, 54, 1) | ||
208 | +FIELD(HFGITR_EL2, NBRBINJ, 55, 1) | ||
209 | +FIELD(HFGITR_EL2, NBRBIALL, 56, 1) | ||
210 | + | ||
211 | +FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) | ||
212 | +FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) | ||
213 | +FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1) | ||
214 | +FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1) | ||
215 | +FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1) | ||
216 | +FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1) | ||
217 | +FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1) | ||
218 | +FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1) | ||
219 | +/* 8: RES0: OSLAR_EL1 is WO */ | ||
220 | +FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1) | ||
221 | +FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1) | ||
222 | +FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1) | ||
223 | +FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1) | ||
224 | +FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1) | ||
225 | +FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1) | ||
226 | +FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1) | ||
227 | +FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1) | ||
228 | +FIELD(HDFGRTR_EL2, PMINTEN, 17, 1) | ||
229 | +FIELD(HDFGRTR_EL2, PMOVS, 18, 1) | ||
230 | +FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1) | ||
231 | +/* 20: RES0: PMSWINC_EL0 is WO */ | ||
232 | +/* 21: RES0: PMCR_EL0 is WO */ | ||
233 | +FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1) | ||
234 | +FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1) | ||
235 | +FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1) | ||
236 | +FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1) | ||
237 | +FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1) | ||
238 | +FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1) | ||
239 | +FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1) | ||
240 | +FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1) | ||
241 | +FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1) | ||
242 | +FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1) | ||
243 | +FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1) | ||
244 | +FIELD(HDFGRTR_EL2, TRC, 33, 1) | ||
245 | +FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1) | ||
246 | +FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1) | ||
247 | +FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1) | ||
248 | +FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1) | ||
249 | +/* 38, 39: RES0 */ | ||
250 | +FIELD(HDFGRTR_EL2, TRCID, 40, 1) | ||
251 | +FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1) | ||
252 | +/* 42: RES0: TRCOSLAR is WO */ | ||
253 | +FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1) | ||
254 | +FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1) | ||
255 | +FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1) | ||
256 | +FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1) | ||
257 | +FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1) | ||
258 | +FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1) | ||
259 | +/* 49: RES0: TRFCR_EL1 is WO */ | ||
260 | +FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1) | ||
261 | +FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1) | ||
262 | +FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1) | ||
263 | +FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1) | ||
264 | +FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1) | ||
265 | +FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1) | ||
266 | +FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1) | ||
267 | +FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1) | ||
268 | +FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1) | ||
269 | +FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1) | ||
270 | +FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1) | ||
271 | +FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1) | ||
272 | +FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1) | ||
273 | +FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1) | ||
274 | + | ||
275 | +/* | ||
276 | + * These match HDFGRTR_EL2, but bits for RO registers are RES0. | ||
277 | + * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0. | ||
278 | + */ | ||
279 | +FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1) | ||
280 | +FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1) | ||
281 | +FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1) | ||
282 | +FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1) | ||
283 | +FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1) | ||
284 | +FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1) | ||
285 | +FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1) | ||
286 | +FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1) | ||
287 | +FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1) | ||
288 | +FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1) | ||
289 | +FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1) | ||
290 | +FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1) | ||
291 | +FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1) | ||
292 | +FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1) | ||
293 | +FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1) | ||
294 | +FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1) | ||
295 | +FIELD(HDFGWTR_EL2, PMINTEN, 17, 1) | ||
296 | +FIELD(HDFGWTR_EL2, PMOVS, 18, 1) | ||
297 | +FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1) | ||
298 | +FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1) | ||
299 | +FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1) | ||
300 | +FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1) | ||
301 | +FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1) | ||
302 | +FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1) | ||
303 | +FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1) | ||
304 | +FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1) | ||
305 | +FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1) | ||
306 | +FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1) | ||
307 | +FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1) | ||
308 | +FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1) | ||
309 | +FIELD(HDFGWTR_EL2, TRC, 33, 1) | ||
310 | +FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1) | ||
311 | +FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1) | ||
312 | +FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1) | ||
313 | +FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1) | ||
314 | +FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1) | ||
315 | +FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1) | ||
316 | +FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1) | ||
317 | +FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1) | ||
318 | +FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1) | ||
319 | +FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1) | ||
320 | +FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1) | ||
321 | +FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1) | ||
322 | +FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1) | ||
323 | +FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1) | ||
324 | +FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1) | ||
325 | +FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1) | ||
326 | +FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1) | ||
327 | +FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) | ||
328 | +FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) | ||
329 | +FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) | ||
330 | + | ||
331 | typedef struct ARMCPRegInfo ARMCPRegInfo; | ||
332 | |||
333 | /* | ||
334 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
335 | index XXXXXXX..XXXXXXX 100644 | ||
336 | --- a/target/arm/cpu.h | ||
337 | +++ b/target/arm/cpu.h | ||
338 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
339 | uint64_t disr_el1; | ||
340 | uint64_t vdisr_el2; | ||
341 | uint64_t vsesr_el2; | ||
342 | + | ||
343 | + /* | ||
344 | + * Fine-Grained Trap registers. We store these as arrays so the | ||
345 | + * access checking code doesn't have to manually select | ||
346 | + * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test. | ||
347 | + * FEAT_FGT2 will add more elements to these arrays. | ||
348 | + */ | ||
349 | + uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ | ||
350 | + uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ | ||
351 | + uint64_t fgt_exec[1]; /* HFGITR */ | ||
352 | } cp15; | ||
353 | |||
354 | struct { | ||
355 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id) | ||
356 | return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id)); | ||
357 | } | ||
358 | |||
359 | +static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id) | ||
360 | +{ | ||
361 | + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0; | ||
362 | +} | ||
363 | + | ||
364 | static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) | ||
365 | { | ||
366 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; | ||
19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 367 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
20 | index XXXXXXX..XXXXXXX 100644 | 368 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/helper.c | 369 | --- a/target/arm/helper.c |
22 | +++ b/target/arm/helper.c | 370 | +++ b/target/arm/helper.c |
23 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 371 | @@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) |
24 | if (cpu_isar_feature(aa64_sme, cpu)) { | 372 | if (cpu_isar_feature(aa64_hcx, cpu)) { |
25 | valid_mask |= SCR_ENTP2; | 373 | valid_mask |= SCR_HXEN; |
26 | } | 374 | } |
27 | + if (cpu_isar_feature(aa64_hcx, cpu)) { | 375 | + if (cpu_isar_feature(aa64_fgt, cpu)) { |
28 | + valid_mask |= SCR_HXEN; | 376 | + valid_mask |= SCR_FGTEN; |
29 | + } | 377 | + } |
30 | } else { | 378 | } else { |
31 | valid_mask &= ~(SCR_RW | SCR_ST); | 379 | valid_mask &= ~(SCR_RW | SCR_ST); |
32 | if (cpu_isar_feature(aa32_ras, cpu)) { | 380 | if (cpu_isar_feature(aa32_ras, cpu)) { |
381 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
382 | .access = PL3_RW, | ||
383 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, | ||
384 | }; | ||
385 | + | ||
386 | +static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri, | ||
387 | + bool isread) | ||
388 | +{ | ||
389 | + if (arm_current_el(env) == 2 && | ||
390 | + arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) { | ||
391 | + return CP_ACCESS_TRAP_EL3; | ||
392 | + } | ||
393 | + return CP_ACCESS_OK; | ||
394 | +} | ||
395 | + | ||
396 | +static const ARMCPRegInfo fgt_reginfo[] = { | ||
397 | + { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64, | ||
398 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, | ||
399 | + .access = PL2_RW, .accessfn = access_fgt, | ||
400 | + .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) }, | ||
401 | + { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64, | ||
402 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5, | ||
403 | + .access = PL2_RW, .accessfn = access_fgt, | ||
404 | + .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) }, | ||
405 | + { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64, | ||
406 | + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4, | ||
407 | + .access = PL2_RW, .accessfn = access_fgt, | ||
408 | + .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) }, | ||
409 | + { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64, | ||
410 | + .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5, | ||
411 | + .access = PL2_RW, .accessfn = access_fgt, | ||
412 | + .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) }, | ||
413 | + { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64, | ||
414 | + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6, | ||
415 | + .access = PL2_RW, .accessfn = access_fgt, | ||
416 | + .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) }, | ||
417 | +}; | ||
418 | #endif /* TARGET_AARCH64 */ | ||
419 | |||
420 | static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
421 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
422 | if (cpu_isar_feature(aa64_scxtnum, cpu)) { | ||
423 | define_arm_cp_regs(cpu, scxtnum_reginfo); | ||
424 | } | ||
425 | + | ||
426 | + if (cpu_isar_feature(aa64_fgt, cpu)) { | ||
427 | + define_arm_cp_regs(cpu, fgt_reginfo); | ||
428 | + } | ||
429 | #endif | ||
430 | |||
431 | if (cpu_isar_feature(any_predinv, cpu)) { | ||
33 | -- | 432 | -- |
34 | 2.34.1 | 433 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | Implement the machinery for fine-grained traps on normal sysregs. |
---|---|---|---|
2 | 2 | Any sysreg with a fine-grained trap will set the new field to | |
3 | This patch implements Allwinner TWI/I2C controller emulation. Only | 3 | indicate which FGT register bit it should trap on. |
4 | master-mode functionality is implemented. | 4 | |
5 | 5 | FGT traps only happen when an AArch64 EL2 enables them for | |
6 | The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is | 6 | an AArch64 EL1. They therefore are only relevant for AArch32 |
7 | first part enabling the TWI/I2C bus operation. | 7 | cpregs when the cpreg can be accessed from EL0. The logic |
8 | 8 | in access_check_cp_reg() will check this, so it is safe to | |
9 | Since both Allwinner A10 and H3 use the same module, it is added for | 9 | add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. |
10 | both boards. | 10 | |
11 | 11 | The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname | |
12 | Docs are also updated for Cubieboard and Orangepi-PC board to indicate | 12 | which can be used to specify the FGT bit, eg |
13 | I2C availability. | 13 | .fgt = FGT_AFSR0_EL1 |
14 | 14 | (We assume that there is no bit name duplication across the FGT | |
15 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 15 | registers, for brevity's sake.) |
16 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | 16 | |
17 | Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com | 17 | Subsequent commits will add the .fgt fields to the relevant register |
18 | definitions and define the FGT_nnn values for them. | ||
19 | |||
20 | Note that some of the FGT traps are for instructions that we don't | ||
21 | handle via the cpregs mechanisms (mostly these are instruction traps). | ||
22 | Those we will have to handle separately. | ||
23 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Tested-by: Fuad Tabba <tabba@google.com> | ||
27 | Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org | ||
28 | Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org | ||
19 | --- | 29 | --- |
20 | docs/system/arm/cubieboard.rst | 1 + | 30 | target/arm/cpregs.h | 72 ++++++++++++++++++++++++++++++++++++++ |
21 | docs/system/arm/orangepi.rst | 1 + | 31 | target/arm/cpu.h | 1 + |
22 | include/hw/arm/allwinner-a10.h | 2 + | 32 | target/arm/internals.h | 20 +++++++++++ |
23 | include/hw/arm/allwinner-h3.h | 3 + | 33 | target/arm/translate.h | 2 ++ |
24 | include/hw/i2c/allwinner-i2c.h | 55 ++++ | 34 | target/arm/helper.c | 9 +++++ |
25 | hw/arm/allwinner-a10.c | 8 + | 35 | target/arm/op_helper.c | 30 ++++++++++++++++ |
26 | hw/arm/allwinner-h3.c | 11 +- | 36 | target/arm/translate-a64.c | 3 +- |
27 | hw/i2c/allwinner-i2c.c | 459 +++++++++++++++++++++++++++++++++ | 37 | target/arm/translate.c | 2 ++ |
28 | hw/arm/Kconfig | 2 + | 38 | 8 files changed, 138 insertions(+), 1 deletion(-) |
29 | hw/i2c/Kconfig | 4 + | 39 | |
30 | hw/i2c/meson.build | 1 + | 40 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
31 | hw/i2c/trace-events | 5 + | 41 | index XXXXXXX..XXXXXXX 100644 |
32 | 12 files changed, 551 insertions(+), 1 deletion(-) | 42 | --- a/target/arm/cpregs.h |
33 | create mode 100644 include/hw/i2c/allwinner-i2c.h | 43 | +++ b/target/arm/cpregs.h |
34 | create mode 100644 hw/i2c/allwinner-i2c.c | 44 | @@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1) |
35 | 45 | FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1) | |
36 | diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst | 46 | FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1) |
37 | index XXXXXXX..XXXXXXX 100644 | 47 | |
38 | --- a/docs/system/arm/cubieboard.rst | 48 | +/* Which fine-grained trap bit register to check, if any */ |
39 | +++ b/docs/system/arm/cubieboard.rst | 49 | +FIELD(FGT, TYPE, 10, 3) |
40 | @@ -XXX,XX +XXX,XX @@ Emulated devices: | 50 | +FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */ |
41 | - SDHCI | 51 | +FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */ |
42 | - USB controller | 52 | +FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */ |
43 | - SATA controller | 53 | + |
44 | +- TWI (I2C) controller | ||
45 | diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/docs/system/arm/orangepi.rst | ||
48 | +++ b/docs/system/arm/orangepi.rst | ||
49 | @@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices: | ||
50 | * Clock Control Unit | ||
51 | * System Control module | ||
52 | * Security Identifier device | ||
53 | + * TWI (I2C) | ||
54 | |||
55 | Limitations | ||
56 | """"""""""" | ||
57 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/include/hw/arm/allwinner-a10.h | ||
60 | +++ b/include/hw/arm/allwinner-a10.h | ||
61 | @@ -XXX,XX +XXX,XX @@ | ||
62 | #include "hw/rtc/allwinner-rtc.h" | ||
63 | #include "hw/misc/allwinner-a10-ccm.h" | ||
64 | #include "hw/misc/allwinner-a10-dramc.h" | ||
65 | +#include "hw/i2c/allwinner-i2c.h" | ||
66 | |||
67 | #include "target/arm/cpu.h" | ||
68 | #include "qom/object.h" | ||
69 | @@ -XXX,XX +XXX,XX @@ struct AwA10State { | ||
70 | AwEmacState emac; | ||
71 | AllwinnerAHCIState sata; | ||
72 | AwSdHostState mmc0; | ||
73 | + AWI2CState i2c0; | ||
74 | AwRtcState rtc; | ||
75 | MemoryRegion sram_a; | ||
76 | EHCISysBusState ehci[AW_A10_NUM_USB]; | ||
77 | diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/include/hw/arm/allwinner-h3.h | ||
80 | +++ b/include/hw/arm/allwinner-h3.h | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | #include "hw/sd/allwinner-sdhost.h" | ||
83 | #include "hw/net/allwinner-sun8i-emac.h" | ||
84 | #include "hw/rtc/allwinner-rtc.h" | ||
85 | +#include "hw/i2c/allwinner-i2c.h" | ||
86 | #include "target/arm/cpu.h" | ||
87 | #include "sysemu/block-backend.h" | ||
88 | |||
89 | @@ -XXX,XX +XXX,XX @@ enum { | ||
90 | AW_H3_DEV_UART2, | ||
91 | AW_H3_DEV_UART3, | ||
92 | AW_H3_DEV_EMAC, | ||
93 | + AW_H3_DEV_TWI0, | ||
94 | AW_H3_DEV_DRAMCOM, | ||
95 | AW_H3_DEV_DRAMCTL, | ||
96 | AW_H3_DEV_DRAMPHY, | ||
97 | @@ -XXX,XX +XXX,XX @@ struct AwH3State { | ||
98 | AwH3SysCtrlState sysctrl; | ||
99 | AwSidState sid; | ||
100 | AwSdHostState mmc0; | ||
101 | + AWI2CState i2c0; | ||
102 | AwSun8iEmacState emac; | ||
103 | AwRtcState rtc; | ||
104 | GICState gic; | ||
105 | diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h | ||
106 | new file mode 100644 | ||
107 | index XXXXXXX..XXXXXXX | ||
108 | --- /dev/null | ||
109 | +++ b/include/hw/i2c/allwinner-i2c.h | ||
110 | @@ -XXX,XX +XXX,XX @@ | ||
111 | +/* | 54 | +/* |
112 | + * Allwinner I2C Bus Serial Interface registers definition | 55 | + * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt |
113 | + * | 56 | + * fields. We assume for brevity's sake that there are no duplicated |
114 | + * Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com> | 57 | + * bit names across the various FGT registers. |
115 | + * | ||
116 | + * This file is derived from IMX I2C controller, | ||
117 | + * by Jean-Christophe DUBOIS . | ||
118 | + * | ||
119 | + * This program is free software; you can redistribute it and/or modify it | ||
120 | + * under the terms of the GNU General Public License as published by the | ||
121 | + * Free Software Foundation; either version 2 of the License, or | ||
122 | + * (at your option) any later version. | ||
123 | + * | ||
124 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
125 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
126 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
127 | + * for more details. | ||
128 | + * | ||
129 | + * You should have received a copy of the GNU General Public License along | ||
130 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
131 | + * | ||
132 | + */ | 58 | + */ |
133 | + | 59 | +#define DO_BIT(REG, BITNAME) \ |
134 | +#ifndef ALLWINNER_I2C_H | 60 | + FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT |
135 | +#define ALLWINNER_I2C_H | 61 | + |
136 | + | 62 | +/* Some bits have reversed sense, so 0 means trap and 1 means not */ |
137 | +#include "hw/sysbus.h" | 63 | +#define DO_REV_BIT(REG, BITNAME) \ |
138 | +#include "qom/object.h" | 64 | + FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT |
139 | + | 65 | + |
140 | +#define TYPE_AW_I2C "allwinner.i2c" | 66 | +typedef enum FGTBit { |
141 | +OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C) | 67 | + /* |
142 | + | 68 | + * These bits tell us which register arrays to use: |
143 | +#define AW_I2C_MEM_SIZE 0x24 | 69 | + * if FGT_R is set then reads are checked against fgt_read[]; |
144 | + | 70 | + * if FGT_W is set then writes are checked against fgt_write[]; |
145 | +struct AWI2CState { | 71 | + * if FGT_EXEC is set then all accesses are checked against fgt_exec[]. |
146 | + /*< private >*/ | 72 | + * |
147 | + SysBusDevice parent_obj; | 73 | + * For almost all bits in the R/W register pairs, the bit exists in |
148 | + | 74 | + * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register |
149 | + /*< public >*/ | 75 | + * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa |
150 | + MemoryRegion iomem; | 76 | + * for a WO register. There are unfortunately a couple of exceptions |
151 | + I2CBus *bus; | 77 | + * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but |
152 | + qemu_irq irq; | 78 | + * the FGT system only allows trapping of writes, not reads. |
153 | + | 79 | + * |
154 | + uint8_t addr; | 80 | + * Note that we arrange these bits so that a 0 FGTBit means "no trap". |
155 | + uint8_t xaddr; | 81 | + */ |
156 | + uint8_t data; | 82 | + FGT_R = 1 << R_FGT_TYPE_SHIFT, |
157 | + uint8_t cntr; | 83 | + FGT_W = 2 << R_FGT_TYPE_SHIFT, |
158 | + uint8_t stat; | 84 | + FGT_EXEC = 4 << R_FGT_TYPE_SHIFT, |
159 | + uint8_t ccr; | 85 | + FGT_RW = FGT_R | FGT_W, |
160 | + uint8_t srst; | 86 | + /* Bit to identify whether trap bit is reversed sense */ |
161 | + uint8_t efr; | 87 | + FGT_REV = R_FGT_REV_MASK, |
162 | + uint8_t lcr; | 88 | + |
163 | +}; | 89 | + /* |
164 | + | 90 | + * If a bit exists in HFGRTR/HDFGRTR then either the register being |
165 | +#endif /* ALLWINNER_I2C_H */ | 91 | + * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either |
166 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | 92 | + * want to trap for both reads and writes or else it's harmless to mark |
167 | index XXXXXXX..XXXXXXX 100644 | 93 | + * it as trap-on-writes. |
168 | --- a/hw/arm/allwinner-a10.c | 94 | + * If a bit exists only in HFGWTR/HDFGWTR then either the register being |
169 | +++ b/hw/arm/allwinner-a10.c | 95 | + * trapped is WO, or else it is one of the two oddball special cases |
170 | @@ -XXX,XX +XXX,XX @@ | 96 | + * which are RW but have only a write trap. We mark these as only |
171 | #define AW_A10_OHCI_BASE 0x01c14400 | 97 | + * FGT_W so we get the right behaviour for those special cases. |
172 | #define AW_A10_SATA_BASE 0x01c18000 | 98 | + * (If a bit was added in future that provided only a read trap for an |
173 | #define AW_A10_RTC_BASE 0x01c20d00 | 99 | + * RW register we'd need to do something special to get the FGT_R bit |
174 | +#define AW_A10_I2C0_BASE 0x01c2ac00 | 100 | + * only. But this seems unlikely to happen.) |
175 | 101 | + * | |
176 | static void aw_a10_init(Object *obj) | 102 | + * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if |
177 | { | 103 | + * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR. |
178 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj) | 104 | + */ |
179 | 105 | + FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT), | |
180 | object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); | 106 | + FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT), |
181 | 107 | + FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), | |
182 | + object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C); | 108 | + FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), |
183 | + | 109 | + FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), |
184 | if (machine_usb(current_machine)) { | 110 | +} FGTBit; |
185 | int i; | 111 | + |
186 | 112 | +#undef DO_BIT | |
187 | @@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp) | 113 | +#undef DO_REV_BIT |
188 | /* RTC */ | 114 | + |
189 | sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal); | 115 | typedef struct ARMCPRegInfo ARMCPRegInfo; |
190 | sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10); | 116 | |
191 | + | 117 | /* |
192 | + /* I2C */ | 118 | @@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo { |
193 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); | 119 | CPAccessRights access; |
194 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE); | 120 | /* Security state: ARM_CP_SECSTATE_* bits/values */ |
195 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7)); | 121 | CPSecureState secure; |
122 | + /* | ||
123 | + * Which fine-grained trap register bit to check, if any. This | ||
124 | + * value encodes both the trap register and bit within it. | ||
125 | + */ | ||
126 | + FGTBit fgt; | ||
127 | /* | ||
128 | * The opaque pointer passed to define_arm_cp_regs_with_opaque() when | ||
129 | * this register was defined: can be used to hand data through to the | ||
130 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
131 | index XXXXXXX..XXXXXXX 100644 | ||
132 | --- a/target/arm/cpu.h | ||
133 | +++ b/target/arm/cpu.h | ||
134 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) | ||
135 | /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ | ||
136 | FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) | ||
137 | FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) | ||
138 | +FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) | ||
139 | |||
140 | /* | ||
141 | * Bit usage when in AArch32 state, both A- and M-profile. | ||
142 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
143 | index XXXXXXX..XXXXXXX 100644 | ||
144 | --- a/target/arm/internals.h | ||
145 | +++ b/target/arm/internals.h | ||
146 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) | ||
147 | ((1 << (1 - 1)) | (1 << (2 - 1)) | \ | ||
148 | (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) | ||
149 | |||
150 | +/* | ||
151 | + * Return true if it is possible to take a fine-grained-trap to EL2. | ||
152 | + */ | ||
153 | +static inline bool arm_fgt_active(CPUARMState *env, int el) | ||
154 | +{ | ||
155 | + /* | ||
156 | + * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps | ||
157 | + * that can affect EL0, but it is harmless to do the test also for | ||
158 | + * traps on registers that are only accessible at EL1 because if the test | ||
159 | + * returns true then we can't be executing at EL1 anyway. | ||
160 | + * FGT traps only happen when EL2 is enabled and EL1 is AArch64; | ||
161 | + * traps from AArch32 only happen for the EL0 is AArch32 case. | ||
162 | + */ | ||
163 | + return cpu_isar_feature(aa64_fgt, env_archcpu(env)) && | ||
164 | + el < 2 && arm_is_el2_enabled(env) && | ||
165 | + arm_el_is_aa64(env, 1) && | ||
166 | + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) && | ||
167 | + (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); | ||
168 | +} | ||
169 | + | ||
170 | #endif | ||
171 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
172 | index XXXXXXX..XXXXXXX 100644 | ||
173 | --- a/target/arm/translate.h | ||
174 | +++ b/target/arm/translate.h | ||
175 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
176 | bool is_nonstreaming; | ||
177 | /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ | ||
178 | bool mve_no_pred; | ||
179 | + /* True if fine-grained traps are active */ | ||
180 | + bool fgt_active; | ||
181 | /* | ||
182 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. | ||
183 | * < 0, set by the current instruction. | ||
184 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
185 | index XXXXXXX..XXXXXXX 100644 | ||
186 | --- a/target/arm/helper.c | ||
187 | +++ b/target/arm/helper.c | ||
188 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, | ||
189 | if (arm_singlestep_active(env)) { | ||
190 | DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); | ||
191 | } | ||
192 | + | ||
193 | return flags; | ||
196 | } | 194 | } |
197 | 195 | ||
198 | static void aw_a10_class_init(ObjectClass *oc, void *data) | 196 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
199 | diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c | 197 | DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); |
200 | index XXXXXXX..XXXXXXX 100644 | 198 | } |
201 | --- a/hw/arm/allwinner-h3.c | 199 | |
202 | +++ b/hw/arm/allwinner-h3.c | 200 | + if (arm_fgt_active(env, el)) { |
203 | @@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = { | 201 | + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); |
204 | [AW_H3_DEV_UART1] = 0x01c28400, | ||
205 | [AW_H3_DEV_UART2] = 0x01c28800, | ||
206 | [AW_H3_DEV_UART3] = 0x01c28c00, | ||
207 | + [AW_H3_DEV_TWI0] = 0x01c2ac00, | ||
208 | [AW_H3_DEV_EMAC] = 0x01c30000, | ||
209 | [AW_H3_DEV_DRAMCOM] = 0x01c62000, | ||
210 | [AW_H3_DEV_DRAMCTL] = 0x01c63000, | ||
211 | @@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented { | ||
212 | { "uart1", 0x01c28400, 1 * KiB }, | ||
213 | { "uart2", 0x01c28800, 1 * KiB }, | ||
214 | { "uart3", 0x01c28c00, 1 * KiB }, | ||
215 | - { "twi0", 0x01c2ac00, 1 * KiB }, | ||
216 | { "twi1", 0x01c2b000, 1 * KiB }, | ||
217 | { "twi2", 0x01c2b400, 1 * KiB }, | ||
218 | { "scr", 0x01c2c400, 1 * KiB }, | ||
219 | @@ -XXX,XX +XXX,XX @@ enum { | ||
220 | AW_H3_GIC_SPI_UART1 = 1, | ||
221 | AW_H3_GIC_SPI_UART2 = 2, | ||
222 | AW_H3_GIC_SPI_UART3 = 3, | ||
223 | + AW_H3_GIC_SPI_TWI0 = 6, | ||
224 | AW_H3_GIC_SPI_TIMER0 = 18, | ||
225 | AW_H3_GIC_SPI_TIMER1 = 19, | ||
226 | AW_H3_GIC_SPI_MMC0 = 60, | ||
227 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj) | ||
228 | "ram-size"); | ||
229 | |||
230 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I); | ||
231 | + | ||
232 | + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C); | ||
233 | } | ||
234 | |||
235 | static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
236 | @@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) | ||
237 | sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal); | ||
238 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]); | ||
239 | |||
240 | + /* I2C */ | ||
241 | + sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal); | ||
242 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]); | ||
243 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, | ||
244 | + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0)); | ||
245 | + | ||
246 | /* Unimplemented devices */ | ||
247 | for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { | ||
248 | create_unimplemented_device(unimplemented[i].device_name, | ||
249 | diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c | ||
250 | new file mode 100644 | ||
251 | index XXXXXXX..XXXXXXX | ||
252 | --- /dev/null | ||
253 | +++ b/hw/i2c/allwinner-i2c.c | ||
254 | @@ -XXX,XX +XXX,XX @@ | ||
255 | +/* | ||
256 | + * Allwinner I2C Bus Serial Interface Emulation | ||
257 | + * | ||
258 | + * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
259 | + * | ||
260 | + * This file is derived from IMX I2C controller, | ||
261 | + * by Jean-Christophe DUBOIS . | ||
262 | + * | ||
263 | + * This program is free software; you can redistribute it and/or modify it | ||
264 | + * under the terms of the GNU General Public License as published by the | ||
265 | + * Free Software Foundation; either version 2 of the License, or | ||
266 | + * (at your option) any later version. | ||
267 | + * | ||
268 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
269 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
270 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
271 | + * for more details. | ||
272 | + * | ||
273 | + * You should have received a copy of the GNU General Public License along | ||
274 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
275 | + * | ||
276 | + * SPDX-License-Identifier: MIT | ||
277 | + */ | ||
278 | + | ||
279 | +#include "qemu/osdep.h" | ||
280 | +#include "hw/i2c/allwinner-i2c.h" | ||
281 | +#include "hw/irq.h" | ||
282 | +#include "migration/vmstate.h" | ||
283 | +#include "hw/i2c/i2c.h" | ||
284 | +#include "qemu/log.h" | ||
285 | +#include "trace.h" | ||
286 | +#include "qemu/module.h" | ||
287 | + | ||
288 | +/* Allwinner I2C memory map */ | ||
289 | +#define TWI_ADDR_REG 0x00 /* slave address register */ | ||
290 | +#define TWI_XADDR_REG 0x04 /* extended slave address register */ | ||
291 | +#define TWI_DATA_REG 0x08 /* data register */ | ||
292 | +#define TWI_CNTR_REG 0x0c /* control register */ | ||
293 | +#define TWI_STAT_REG 0x10 /* status register */ | ||
294 | +#define TWI_CCR_REG 0x14 /* clock control register */ | ||
295 | +#define TWI_SRST_REG 0x18 /* software reset register */ | ||
296 | +#define TWI_EFR_REG 0x1c /* enhance feature register */ | ||
297 | +#define TWI_LCR_REG 0x20 /* line control register */ | ||
298 | + | ||
299 | +/* Used only in slave mode, do not set */ | ||
300 | +#define TWI_ADDR_RESET 0 | ||
301 | +#define TWI_XADDR_RESET 0 | ||
302 | + | ||
303 | +/* Data register */ | ||
304 | +#define TWI_DATA_MASK 0xFF | ||
305 | +#define TWI_DATA_RESET 0 | ||
306 | + | ||
307 | +/* Control register */ | ||
308 | +#define TWI_CNTR_INT_EN (1 << 7) | ||
309 | +#define TWI_CNTR_BUS_EN (1 << 6) | ||
310 | +#define TWI_CNTR_M_STA (1 << 5) | ||
311 | +#define TWI_CNTR_M_STP (1 << 4) | ||
312 | +#define TWI_CNTR_INT_FLAG (1 << 3) | ||
313 | +#define TWI_CNTR_A_ACK (1 << 2) | ||
314 | +#define TWI_CNTR_MASK 0xFC | ||
315 | +#define TWI_CNTR_RESET 0 | ||
316 | + | ||
317 | +/* Status register */ | ||
318 | +#define TWI_STAT_MASK 0xF8 | ||
319 | +#define TWI_STAT_RESET 0xF8 | ||
320 | + | ||
321 | +/* Clock register */ | ||
322 | +#define TWI_CCR_CLK_M_MASK 0x78 | ||
323 | +#define TWI_CCR_CLK_N_MASK 0x07 | ||
324 | +#define TWI_CCR_MASK 0x7F | ||
325 | +#define TWI_CCR_RESET 0 | ||
326 | + | ||
327 | +/* Soft reset */ | ||
328 | +#define TWI_SRST_MASK 0x01 | ||
329 | +#define TWI_SRST_RESET 0 | ||
330 | + | ||
331 | +/* Enhance feature */ | ||
332 | +#define TWI_EFR_MASK 0x03 | ||
333 | +#define TWI_EFR_RESET 0 | ||
334 | + | ||
335 | +/* Line control */ | ||
336 | +#define TWI_LCR_SCL_STATE (1 << 5) | ||
337 | +#define TWI_LCR_SDA_STATE (1 << 4) | ||
338 | +#define TWI_LCR_SCL_CTL (1 << 3) | ||
339 | +#define TWI_LCR_SCL_CTL_EN (1 << 2) | ||
340 | +#define TWI_LCR_SDA_CTL (1 << 1) | ||
341 | +#define TWI_LCR_SDA_CTL_EN (1 << 0) | ||
342 | +#define TWI_LCR_MASK 0x3F | ||
343 | +#define TWI_LCR_RESET 0x3A | ||
344 | + | ||
345 | +/* Status value in STAT register is shifted by 3 bits */ | ||
346 | +#define TWI_STAT_SHIFT 3 | ||
347 | +#define STAT_FROM_STA(x) ((x) << TWI_STAT_SHIFT) | ||
348 | +#define STAT_TO_STA(x) ((x) >> TWI_STAT_SHIFT) | ||
349 | + | ||
350 | +enum { | ||
351 | + STAT_BUS_ERROR = 0, | ||
352 | + /* Master mode */ | ||
353 | + STAT_M_STA_TX, | ||
354 | + STAT_M_RSTA_TX, | ||
355 | + STAT_M_ADDR_WR_ACK, | ||
356 | + STAT_M_ADDR_WR_NACK, | ||
357 | + STAT_M_DATA_TX_ACK, | ||
358 | + STAT_M_DATA_TX_NACK, | ||
359 | + STAT_M_ARB_LOST, | ||
360 | + STAT_M_ADDR_RD_ACK, | ||
361 | + STAT_M_ADDR_RD_NACK, | ||
362 | + STAT_M_DATA_RX_ACK, | ||
363 | + STAT_M_DATA_RX_NACK, | ||
364 | + /* Slave mode */ | ||
365 | + STAT_S_ADDR_WR_ACK, | ||
366 | + STAT_S_ARB_LOST_AW_ACK, | ||
367 | + STAT_S_GCA_ACK, | ||
368 | + STAT_S_ARB_LOST_GCA_ACK, | ||
369 | + STAT_S_DATA_RX_SA_ACK, | ||
370 | + STAT_S_DATA_RX_SA_NACK, | ||
371 | + STAT_S_DATA_RX_GCA_ACK, | ||
372 | + STAT_S_DATA_RX_GCA_NACK, | ||
373 | + STAT_S_STP_RSTA, | ||
374 | + STAT_S_ADDR_RD_ACK, | ||
375 | + STAT_S_ARB_LOST_AR_ACK, | ||
376 | + STAT_S_DATA_TX_ACK, | ||
377 | + STAT_S_DATA_TX_NACK, | ||
378 | + STAT_S_LB_TX_ACK, | ||
379 | + /* Master mode, 10-bit */ | ||
380 | + STAT_M_2ND_ADDR_WR_ACK, | ||
381 | + STAT_M_2ND_ADDR_WR_NACK, | ||
382 | + /* Idle */ | ||
383 | + STAT_IDLE = 0x1f | ||
384 | +} TWI_STAT_STA; | ||
385 | + | ||
386 | +static const char *allwinner_i2c_get_regname(unsigned offset) | ||
387 | +{ | ||
388 | + switch (offset) { | ||
389 | + case TWI_ADDR_REG: | ||
390 | + return "ADDR"; | ||
391 | + case TWI_XADDR_REG: | ||
392 | + return "XADDR"; | ||
393 | + case TWI_DATA_REG: | ||
394 | + return "DATA"; | ||
395 | + case TWI_CNTR_REG: | ||
396 | + return "CNTR"; | ||
397 | + case TWI_STAT_REG: | ||
398 | + return "STAT"; | ||
399 | + case TWI_CCR_REG: | ||
400 | + return "CCR"; | ||
401 | + case TWI_SRST_REG: | ||
402 | + return "SRST"; | ||
403 | + case TWI_EFR_REG: | ||
404 | + return "EFR"; | ||
405 | + case TWI_LCR_REG: | ||
406 | + return "LCR"; | ||
407 | + default: | ||
408 | + return "[?]"; | ||
409 | + } | 202 | + } |
410 | +} | 203 | + |
411 | + | 204 | if (env->uncached_cpsr & CPSR_IL) { |
412 | +static inline bool allwinner_i2c_is_reset(AWI2CState *s) | 205 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); |
413 | +{ | 206 | } |
414 | + return s->srst & TWI_SRST_MASK; | 207 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
415 | +} | 208 | DP_TBFLAG_ANY(flags, PSTATE__IL, 1); |
416 | + | 209 | } |
417 | +static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s) | 210 | |
418 | +{ | 211 | + if (arm_fgt_active(env, el)) { |
419 | + return s->cntr & TWI_CNTR_BUS_EN; | 212 | + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); |
420 | +} | ||
421 | + | ||
422 | +static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s) | ||
423 | +{ | ||
424 | + return s->cntr & TWI_CNTR_INT_EN; | ||
425 | +} | ||
426 | + | ||
427 | +static void allwinner_i2c_reset_hold(Object *obj) | ||
428 | +{ | ||
429 | + AWI2CState *s = AW_I2C(obj); | ||
430 | + | ||
431 | + if (STAT_TO_STA(s->stat) != STAT_IDLE) { | ||
432 | + i2c_end_transfer(s->bus); | ||
433 | + } | 213 | + } |
434 | + | 214 | + |
435 | + s->addr = TWI_ADDR_RESET; | 215 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |
436 | + s->xaddr = TWI_XADDR_RESET; | 216 | /* |
437 | + s->data = TWI_DATA_RESET; | 217 | * Set MTE_ACTIVE if any access may be Checked, and leave clear |
438 | + s->cntr = TWI_CNTR_RESET; | 218 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c |
439 | + s->stat = TWI_STAT_RESET; | 219 | index XXXXXXX..XXXXXXX 100644 |
440 | + s->ccr = TWI_CCR_RESET; | 220 | --- a/target/arm/op_helper.c |
441 | + s->srst = TWI_SRST_RESET; | 221 | +++ b/target/arm/op_helper.c |
442 | + s->efr = TWI_EFR_RESET; | 222 | @@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key, |
443 | + s->lcr = TWI_LCR_RESET; | 223 | } |
444 | +} | 224 | } |
445 | + | 225 | |
446 | +static inline void allwinner_i2c_raise_interrupt(AWI2CState *s) | 226 | + /* |
447 | +{ | 227 | + * Fine-grained traps also are lower priority than undef-to-EL1, |
448 | + /* | 228 | + * higher priority than trap-to-EL3, and we don't care about priority |
449 | + * Raise an interrupt if the device is not reset and it is configured | 229 | + * order with other EL2 traps because the syndrome value is the same. |
450 | + * to generate some interrupts. | 230 | + */ |
451 | + */ | 231 | + if (arm_fgt_active(env, arm_current_el(env))) { |
452 | + if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) { | 232 | + uint64_t trapword = 0; |
453 | + if (STAT_TO_STA(s->stat) != STAT_IDLE) { | 233 | + unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX); |
454 | + s->cntr |= TWI_CNTR_INT_FLAG; | 234 | + unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS); |
455 | + if (allwinner_i2c_interrupt_is_enabled(s)) { | 235 | + bool rev = FIELD_EX32(ri->fgt, FGT, REV); |
456 | + qemu_irq_raise(s->irq); | 236 | + bool trapbit; |
457 | + } | 237 | + |
238 | + if (ri->fgt & FGT_EXEC) { | ||
239 | + assert(idx < ARRAY_SIZE(env->cp15.fgt_exec)); | ||
240 | + trapword = env->cp15.fgt_exec[idx]; | ||
241 | + } else if (isread && (ri->fgt & FGT_R)) { | ||
242 | + assert(idx < ARRAY_SIZE(env->cp15.fgt_read)); | ||
243 | + trapword = env->cp15.fgt_read[idx]; | ||
244 | + } else if (!isread && (ri->fgt & FGT_W)) { | ||
245 | + assert(idx < ARRAY_SIZE(env->cp15.fgt_write)); | ||
246 | + trapword = env->cp15.fgt_write[idx]; | ||
247 | + } | ||
248 | + | ||
249 | + trapbit = extract64(trapword, bitpos, 1); | ||
250 | + if (trapbit != rev) { | ||
251 | + res = CP_ACCESS_TRAP_EL2; | ||
252 | + goto fail; | ||
458 | + } | 253 | + } |
459 | + } | 254 | + } |
460 | +} | 255 | + |
461 | + | 256 | if (likely(res == CP_ACCESS_OK)) { |
462 | +static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset, | 257 | return ri; |
463 | + unsigned size) | 258 | } |
464 | +{ | 259 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
465 | + uint16_t value; | 260 | index XXXXXXX..XXXXXXX 100644 |
466 | + AWI2CState *s = AW_I2C(opaque); | 261 | --- a/target/arm/translate-a64.c |
467 | + | 262 | +++ b/target/arm/translate-a64.c |
468 | + switch (offset) { | 263 | @@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, |
469 | + case TWI_ADDR_REG: | 264 | return; |
470 | + value = s->addr; | 265 | } |
471 | + break; | 266 | |
472 | + case TWI_XADDR_REG: | 267 | - if (ri->accessfn) { |
473 | + value = s->xaddr; | 268 | + if (ri->accessfn || (ri->fgt && s->fgt_active)) { |
474 | + break; | 269 | /* Emit code to perform further access permissions checks at |
475 | + case TWI_DATA_REG: | 270 | * runtime; this may result in an exception. |
476 | + if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) || | 271 | */ |
477 | + (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) || | 272 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
478 | + (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) { | 273 | dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); |
479 | + /* Get the next byte */ | 274 | dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); |
480 | + s->data = i2c_recv(s->bus); | 275 | dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); |
481 | + | 276 | + dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); |
482 | + if (s->cntr & TWI_CNTR_A_ACK) { | 277 | dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); |
483 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); | 278 | dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); |
484 | + } else { | 279 | dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; |
485 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); | 280 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
486 | + } | 281 | index XXXXXXX..XXXXXXX 100644 |
487 | + allwinner_i2c_raise_interrupt(s); | 282 | --- a/target/arm/translate.c |
488 | + } | 283 | +++ b/target/arm/translate.c |
489 | + value = s->data; | 284 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
490 | + break; | 285 | } |
491 | + case TWI_CNTR_REG: | 286 | |
492 | + value = s->cntr; | 287 | if ((s->hstr_active && s->current_el == 0) || ri->accessfn || |
493 | + break; | 288 | + (ri->fgt && s->fgt_active) || |
494 | + case TWI_STAT_REG: | 289 | (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) { |
495 | + value = s->stat; | 290 | /* |
496 | + /* | 291 | * Emit code to perform further access permissions checks at |
497 | + * If polling when reading then change state to indicate data | 292 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
498 | + * is available | 293 | dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); |
499 | + */ | 294 | dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); |
500 | + if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) { | 295 | dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); |
501 | + if (s->cntr & TWI_CNTR_A_ACK) { | 296 | + dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); |
502 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); | 297 | |
503 | + } else { | 298 | if (arm_feature(env, ARM_FEATURE_M)) { |
504 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); | 299 | dc->vfp_enabled = 1; |
505 | + } | ||
506 | + allwinner_i2c_raise_interrupt(s); | ||
507 | + } | ||
508 | + break; | ||
509 | + case TWI_CCR_REG: | ||
510 | + value = s->ccr; | ||
511 | + break; | ||
512 | + case TWI_SRST_REG: | ||
513 | + value = s->srst; | ||
514 | + break; | ||
515 | + case TWI_EFR_REG: | ||
516 | + value = s->efr; | ||
517 | + break; | ||
518 | + case TWI_LCR_REG: | ||
519 | + value = s->lcr; | ||
520 | + break; | ||
521 | + default: | ||
522 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" | ||
523 | + HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset); | ||
524 | + value = 0; | ||
525 | + break; | ||
526 | + } | ||
527 | + | ||
528 | + trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value); | ||
529 | + | ||
530 | + return (uint64_t)value; | ||
531 | +} | ||
532 | + | ||
533 | +static void allwinner_i2c_write(void *opaque, hwaddr offset, | ||
534 | + uint64_t value, unsigned size) | ||
535 | +{ | ||
536 | + AWI2CState *s = AW_I2C(opaque); | ||
537 | + | ||
538 | + value &= 0xff; | ||
539 | + | ||
540 | + trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value); | ||
541 | + | ||
542 | + switch (offset) { | ||
543 | + case TWI_ADDR_REG: | ||
544 | + s->addr = (uint8_t)value; | ||
545 | + break; | ||
546 | + case TWI_XADDR_REG: | ||
547 | + s->xaddr = (uint8_t)value; | ||
548 | + break; | ||
549 | + case TWI_DATA_REG: | ||
550 | + /* If the device is in reset or not enabled, nothing to do */ | ||
551 | + if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) { | ||
552 | + break; | ||
553 | + } | ||
554 | + | ||
555 | + s->data = value & TWI_DATA_MASK; | ||
556 | + | ||
557 | + switch (STAT_TO_STA(s->stat)) { | ||
558 | + case STAT_M_STA_TX: | ||
559 | + case STAT_M_RSTA_TX: | ||
560 | + /* Send address */ | ||
561 | + if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7), | ||
562 | + extract32(s->data, 0, 1))) { | ||
563 | + /* If non zero is returned, the address is not valid */ | ||
564 | + s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK); | ||
565 | + } else { | ||
566 | + /* Determine if read of write */ | ||
567 | + if (extract32(s->data, 0, 1)) { | ||
568 | + s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK); | ||
569 | + } else { | ||
570 | + s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK); | ||
571 | + } | ||
572 | + allwinner_i2c_raise_interrupt(s); | ||
573 | + } | ||
574 | + break; | ||
575 | + case STAT_M_ADDR_WR_ACK: | ||
576 | + case STAT_M_DATA_TX_ACK: | ||
577 | + if (i2c_send(s->bus, s->data)) { | ||
578 | + /* If the target return non zero then end the transfer */ | ||
579 | + s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK); | ||
580 | + i2c_end_transfer(s->bus); | ||
581 | + } else { | ||
582 | + s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK); | ||
583 | + allwinner_i2c_raise_interrupt(s); | ||
584 | + } | ||
585 | + break; | ||
586 | + default: | ||
587 | + break; | ||
588 | + } | ||
589 | + break; | ||
590 | + case TWI_CNTR_REG: | ||
591 | + if (!allwinner_i2c_is_reset(s)) { | ||
592 | + /* Do something only if not in software reset */ | ||
593 | + s->cntr = value & TWI_CNTR_MASK; | ||
594 | + | ||
595 | + /* Check if start condition should be sent */ | ||
596 | + if (s->cntr & TWI_CNTR_M_STA) { | ||
597 | + /* Update status */ | ||
598 | + if (STAT_TO_STA(s->stat) == STAT_IDLE) { | ||
599 | + /* Send start condition */ | ||
600 | + s->stat = STAT_FROM_STA(STAT_M_STA_TX); | ||
601 | + } else { | ||
602 | + /* Send repeated start condition */ | ||
603 | + s->stat = STAT_FROM_STA(STAT_M_RSTA_TX); | ||
604 | + } | ||
605 | + /* Clear start condition */ | ||
606 | + s->cntr &= ~TWI_CNTR_M_STA; | ||
607 | + } | ||
608 | + if (s->cntr & TWI_CNTR_M_STP) { | ||
609 | + /* Update status */ | ||
610 | + i2c_end_transfer(s->bus); | ||
611 | + s->stat = STAT_FROM_STA(STAT_IDLE); | ||
612 | + s->cntr &= ~TWI_CNTR_M_STP; | ||
613 | + } | ||
614 | + if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) { | ||
615 | + /* Interrupt flag cleared */ | ||
616 | + qemu_irq_lower(s->irq); | ||
617 | + } | ||
618 | + if ((s->cntr & TWI_CNTR_A_ACK) == 0) { | ||
619 | + if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { | ||
620 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); | ||
621 | + } | ||
622 | + } else { | ||
623 | + if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) { | ||
624 | + s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK); | ||
625 | + } | ||
626 | + } | ||
627 | + allwinner_i2c_raise_interrupt(s); | ||
628 | + | ||
629 | + } | ||
630 | + break; | ||
631 | + case TWI_CCR_REG: | ||
632 | + s->ccr = value & TWI_CCR_MASK; | ||
633 | + break; | ||
634 | + case TWI_SRST_REG: | ||
635 | + if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) { | ||
636 | + /* Perform reset */ | ||
637 | + allwinner_i2c_reset_hold(OBJECT(s)); | ||
638 | + } | ||
639 | + s->srst = value & TWI_SRST_MASK; | ||
640 | + break; | ||
641 | + case TWI_EFR_REG: | ||
642 | + s->efr = value & TWI_EFR_MASK; | ||
643 | + break; | ||
644 | + case TWI_LCR_REG: | ||
645 | + s->lcr = value & TWI_LCR_MASK; | ||
646 | + break; | ||
647 | + default: | ||
648 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" | ||
649 | + HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset); | ||
650 | + break; | ||
651 | + } | ||
652 | +} | ||
653 | + | ||
654 | +static const MemoryRegionOps allwinner_i2c_ops = { | ||
655 | + .read = allwinner_i2c_read, | ||
656 | + .write = allwinner_i2c_write, | ||
657 | + .valid.min_access_size = 1, | ||
658 | + .valid.max_access_size = 4, | ||
659 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
660 | +}; | ||
661 | + | ||
662 | +static const VMStateDescription allwinner_i2c_vmstate = { | ||
663 | + .name = TYPE_AW_I2C, | ||
664 | + .version_id = 1, | ||
665 | + .minimum_version_id = 1, | ||
666 | + .fields = (VMStateField[]) { | ||
667 | + VMSTATE_UINT8(addr, AWI2CState), | ||
668 | + VMSTATE_UINT8(xaddr, AWI2CState), | ||
669 | + VMSTATE_UINT8(data, AWI2CState), | ||
670 | + VMSTATE_UINT8(cntr, AWI2CState), | ||
671 | + VMSTATE_UINT8(ccr, AWI2CState), | ||
672 | + VMSTATE_UINT8(srst, AWI2CState), | ||
673 | + VMSTATE_UINT8(efr, AWI2CState), | ||
674 | + VMSTATE_UINT8(lcr, AWI2CState), | ||
675 | + VMSTATE_END_OF_LIST() | ||
676 | + } | ||
677 | +}; | ||
678 | + | ||
679 | +static void allwinner_i2c_realize(DeviceState *dev, Error **errp) | ||
680 | +{ | ||
681 | + AWI2CState *s = AW_I2C(dev); | ||
682 | + | ||
683 | + memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s, | ||
684 | + TYPE_AW_I2C, AW_I2C_MEM_SIZE); | ||
685 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
686 | + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); | ||
687 | + s->bus = i2c_init_bus(dev, "i2c"); | ||
688 | +} | ||
689 | + | ||
690 | +static void allwinner_i2c_class_init(ObjectClass *klass, void *data) | ||
691 | +{ | ||
692 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
693 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
694 | + | ||
695 | + rc->phases.hold = allwinner_i2c_reset_hold; | ||
696 | + dc->vmsd = &allwinner_i2c_vmstate; | ||
697 | + dc->realize = allwinner_i2c_realize; | ||
698 | + dc->desc = "Allwinner I2C Controller"; | ||
699 | +} | ||
700 | + | ||
701 | +static const TypeInfo allwinner_i2c_type_info = { | ||
702 | + .name = TYPE_AW_I2C, | ||
703 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
704 | + .instance_size = sizeof(AWI2CState), | ||
705 | + .class_init = allwinner_i2c_class_init, | ||
706 | +}; | ||
707 | + | ||
708 | +static void allwinner_i2c_register_types(void) | ||
709 | +{ | ||
710 | + type_register_static(&allwinner_i2c_type_info); | ||
711 | +} | ||
712 | + | ||
713 | +type_init(allwinner_i2c_register_types) | ||
714 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
715 | index XXXXXXX..XXXXXXX 100644 | ||
716 | --- a/hw/arm/Kconfig | ||
717 | +++ b/hw/arm/Kconfig | ||
718 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10 | ||
719 | select ALLWINNER_A10_CCM | ||
720 | select ALLWINNER_A10_DRAMC | ||
721 | select ALLWINNER_EMAC | ||
722 | + select ALLWINNER_I2C | ||
723 | select SERIAL | ||
724 | select UNIMP | ||
725 | |||
726 | @@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3 | ||
727 | bool | ||
728 | select ALLWINNER_A10_PIT | ||
729 | select ALLWINNER_SUN8I_EMAC | ||
730 | + select ALLWINNER_I2C | ||
731 | select SERIAL | ||
732 | select ARM_TIMER | ||
733 | select ARM_GIC | ||
734 | diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig | ||
735 | index XXXXXXX..XXXXXXX 100644 | ||
736 | --- a/hw/i2c/Kconfig | ||
737 | +++ b/hw/i2c/Kconfig | ||
738 | @@ -XXX,XX +XXX,XX @@ config MPC_I2C | ||
739 | bool | ||
740 | select I2C | ||
741 | |||
742 | +config ALLWINNER_I2C | ||
743 | + bool | ||
744 | + select I2C | ||
745 | + | ||
746 | config PCA954X | ||
747 | bool | ||
748 | select I2C | ||
749 | diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build | ||
750 | index XXXXXXX..XXXXXXX 100644 | ||
751 | --- a/hw/i2c/meson.build | ||
752 | +++ b/hw/i2c/meson.build | ||
753 | @@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c')) | ||
754 | i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c')) | ||
755 | i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c')) | ||
756 | i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c')) | ||
757 | +i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c')) | ||
758 | i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c')) | ||
759 | i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c')) | ||
760 | i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c')) | ||
761 | diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events | ||
762 | index XXXXXXX..XXXXXXX 100644 | ||
763 | --- a/hw/i2c/trace-events | ||
764 | +++ b/hw/i2c/trace-events | ||
765 | @@ -XXX,XX +XXX,XX @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0 | ||
766 | i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x" | ||
767 | i2c_ack(void) "" | ||
768 | |||
769 | +# allwinner_i2c.c | ||
770 | + | ||
771 | +allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 | ||
772 | +allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 | ||
773 | + | ||
774 | # aspeed_i2c.c | ||
775 | |||
776 | aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x" | ||
777 | -- | 300 | -- |
778 | 2.34.1 | 301 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the registers trapped |
---|---|---|---|
2 | by HFGRTR/HFGWTR bits 0..11. | ||
2 | 3 | ||
3 | NPCM7XX models have been commited after the conversion from | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Manually convert them. | 6 | Tested-by: Fuad Tabba <tabba@google.com> |
7 | Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org | ||
8 | Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/cpregs.h | 14 ++++++++++++++ | ||
11 | target/arm/helper.c | 17 +++++++++++++++++ | ||
12 | 2 files changed, 31 insertions(+) | ||
6 | 13 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 14 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230109140306.23161-11-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/adc/npcm7xx_adc.h | 7 +++---- | ||
13 | include/hw/arm/npcm7xx.h | 18 ++++++------------ | ||
14 | include/hw/i2c/npcm7xx_smbus.h | 7 +++---- | ||
15 | include/hw/misc/npcm7xx_clk.h | 2 +- | ||
16 | include/hw/misc/npcm7xx_gcr.h | 6 +++--- | ||
17 | include/hw/misc/npcm7xx_mft.h | 7 +++---- | ||
18 | include/hw/misc/npcm7xx_pwm.h | 3 +-- | ||
19 | include/hw/misc/npcm7xx_rng.h | 6 +++--- | ||
20 | include/hw/net/npcm7xx_emc.h | 5 +---- | ||
21 | include/hw/sd/npcm7xx_sdhci.h | 4 ++-- | ||
22 | 10 files changed, 26 insertions(+), 39 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/adc/npcm7xx_adc.h | 16 | --- a/target/arm/cpregs.h |
27 | +++ b/include/hw/adc/npcm7xx_adc.h | 17 | +++ b/target/arm/cpregs.h |
28 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
29 | * @iref: The internal reference voltage, initialized at launch time. | 19 | FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT), |
30 | * @rv: The calibrated output values of 0.5V and 1.5V for the ADC. | 20 | FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT), |
31 | */ | 21 | FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT), |
32 | -typedef struct { | 22 | + |
33 | +struct NPCM7xxADCState { | 23 | + /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */ |
34 | SysBusDevice parent; | 24 | + DO_BIT(HFGRTR, AFSR0_EL1), |
35 | 25 | + DO_BIT(HFGRTR, AFSR1_EL1), | |
36 | MemoryRegion iomem; | 26 | + DO_BIT(HFGRTR, AIDR_EL1), |
37 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 27 | + DO_BIT(HFGRTR, AMAIR_EL1), |
38 | uint32_t iref; | 28 | + DO_BIT(HFGRTR, APDAKEY), |
39 | 29 | + DO_BIT(HFGRTR, APDBKEY), | |
40 | uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB]; | 30 | + DO_BIT(HFGRTR, APGAKEY), |
41 | -} NPCM7xxADCState; | 31 | + DO_BIT(HFGRTR, APIAKEY), |
42 | +}; | 32 | + DO_BIT(HFGRTR, APIBKEY), |
43 | 33 | + DO_BIT(HFGRTR, CCSIDR_EL1), | |
44 | #define TYPE_NPCM7XX_ADC "npcm7xx-adc" | 34 | + DO_BIT(HFGRTR, CLIDR_EL1), |
45 | -#define NPCM7XX_ADC(obj) \ | 35 | + DO_BIT(HFGRTR, CONTEXTIDR_EL1), |
46 | - OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC) | 36 | } FGTBit; |
47 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC) | 37 | |
48 | 38 | #undef DO_BIT | |
49 | #endif /* NPCM7XX_ADC_H */ | 39 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
50 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
51 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
52 | --- a/include/hw/arm/npcm7xx.h | 41 | --- a/target/arm/helper.c |
53 | +++ b/include/hw/arm/npcm7xx.h | 42 | +++ b/target/arm/helper.c |
54 | @@ -XXX,XX +XXX,XX @@ | 43 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = { |
55 | 44 | { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH, | |
56 | #define NPCM7XX_NR_PWM_MODULES 2 | 45 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1, |
57 | 46 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
58 | -typedef struct NPCM7xxMachine { | 47 | + .fgt = FGT_CONTEXTIDR_EL1, |
59 | +struct NPCM7xxMachine { | 48 | .secure = ARM_CP_SECSTATE_NS, |
60 | MachineState parent; | 49 | .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]), |
50 | .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, }, | ||
51 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
52 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | ||
53 | .access = PL1_R, | ||
54 | .accessfn = access_tid4, | ||
55 | + .fgt = FGT_CCSIDR_EL1, | ||
56 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | ||
57 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, | ||
58 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | ||
59 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
60 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, | ||
61 | .access = PL1_R, .type = ARM_CP_CONST, | ||
62 | .accessfn = access_aa64_tid1, | ||
63 | + .fgt = FGT_AIDR_EL1, | ||
64 | .resetvalue = 0 }, | ||
61 | /* | 65 | /* |
62 | * PWM fan splitter. each splitter connects to one PWM output and | 66 | * Auxiliary fault status registers: these also are IMPDEF, and we |
63 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachine { | 67 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { |
64 | */ | 68 | { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, |
65 | SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES * | 69 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, |
66 | NPCM7XX_PWM_PER_MODULE]; | 70 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
67 | -} NPCM7xxMachine; | 71 | + .fgt = FGT_AFSR0_EL1, |
68 | +}; | 72 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
69 | 73 | { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, | |
70 | #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") | 74 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, |
71 | -#define NPCM7XX_MACHINE(obj) \ | 75 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
72 | - OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) | 76 | + .fgt = FGT_AFSR1_EL1, |
73 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE) | 77 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
74 | 78 | /* | |
75 | typedef struct NPCM7xxMachineClass { | 79 | * MAIR can just read-as-written because we don't implement caches |
76 | MachineClass parent; | 80 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { |
77 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachineClass { | 81 | { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, |
78 | #define NPCM7XX_MACHINE_GET_CLASS(obj) \ | 82 | .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0, |
79 | OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) | 83 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
80 | 84 | + .fgt = FGT_AMAIR_EL1, | |
81 | -typedef struct NPCM7xxState { | 85 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
82 | +struct NPCM7xxState { | 86 | /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ |
83 | DeviceState parent; | 87 | { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1, |
84 | 88 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = { | |
85 | ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; | 89 | { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
86 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState { | 90 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0, |
87 | NPCM7xxFIUState fiu[2]; | 91 | .access = PL1_RW, .accessfn = access_pauth, |
88 | NPCM7xxEMCState emc[2]; | 92 | + .fgt = FGT_APDAKEY, |
89 | NPCM7xxSDHCIState mmc; | 93 | .fieldoffset = offsetof(CPUARMState, keys.apda.lo) }, |
90 | -} NPCM7xxState; | 94 | { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
91 | +}; | 95 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1, |
92 | 96 | .access = PL1_RW, .accessfn = access_pauth, | |
93 | #define TYPE_NPCM7XX "npcm7xx" | 97 | + .fgt = FGT_APDAKEY, |
94 | -#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) | 98 | .fieldoffset = offsetof(CPUARMState, keys.apda.hi) }, |
95 | +OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX) | 99 | { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
96 | 100 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2, | |
97 | #define TYPE_NPCM730 "npcm730" | 101 | .access = PL1_RW, .accessfn = access_pauth, |
98 | #define TYPE_NPCM750 "npcm750" | 102 | + .fgt = FGT_APDBKEY, |
99 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxClass { | 103 | .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) }, |
100 | uint32_t num_cpus; | 104 | { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
101 | } NPCM7xxClass; | 105 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3, |
102 | 106 | .access = PL1_RW, .accessfn = access_pauth, | |
103 | -#define NPCM7XX_CLASS(klass) \ | 107 | + .fgt = FGT_APDBKEY, |
104 | - OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) | 108 | .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) }, |
105 | -#define NPCM7XX_GET_CLASS(obj) \ | 109 | { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
106 | - OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) | 110 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0, |
107 | - | 111 | .access = PL1_RW, .accessfn = access_pauth, |
108 | /** | 112 | + .fgt = FGT_APGAKEY, |
109 | * npcm7xx_load_kernel - Loads memory with everything needed to boot | 113 | .fieldoffset = offsetof(CPUARMState, keys.apga.lo) }, |
110 | * @machine - The machine containing the SoC to be booted. | 114 | { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
111 | diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h | 115 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1, |
112 | index XXXXXXX..XXXXXXX 100644 | 116 | .access = PL1_RW, .accessfn = access_pauth, |
113 | --- a/include/hw/i2c/npcm7xx_smbus.h | 117 | + .fgt = FGT_APGAKEY, |
114 | +++ b/include/hw/i2c/npcm7xx_smbus.h | 118 | .fieldoffset = offsetof(CPUARMState, keys.apga.hi) }, |
115 | @@ -XXX,XX +XXX,XX @@ typedef enum NPCM7xxSMBusStatus { | 119 | { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
116 | * @rx_cur: The current position of rx_fifo. | 120 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0, |
117 | * @status: The current status of the SMBus. | 121 | .access = PL1_RW, .accessfn = access_pauth, |
118 | */ | 122 | + .fgt = FGT_APIAKEY, |
119 | -typedef struct NPCM7xxSMBusState { | 123 | .fieldoffset = offsetof(CPUARMState, keys.apia.lo) }, |
120 | +struct NPCM7xxSMBusState { | 124 | { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64, |
121 | SysBusDevice parent; | 125 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1, |
122 | 126 | .access = PL1_RW, .accessfn = access_pauth, | |
123 | MemoryRegion iomem; | 127 | + .fgt = FGT_APIAKEY, |
124 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSMBusState { | 128 | .fieldoffset = offsetof(CPUARMState, keys.apia.hi) }, |
125 | uint8_t rx_cur; | 129 | { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64, |
126 | 130 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2, | |
127 | NPCM7xxSMBusStatus status; | 131 | .access = PL1_RW, .accessfn = access_pauth, |
128 | -} NPCM7xxSMBusState; | 132 | + .fgt = FGT_APIBKEY, |
129 | +}; | 133 | .fieldoffset = offsetof(CPUARMState, keys.apib.lo) }, |
130 | 134 | { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64, | |
131 | #define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus" | 135 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3, |
132 | -#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \ | 136 | .access = PL1_RW, .accessfn = access_pauth, |
133 | - TYPE_NPCM7XX_SMBUS) | 137 | + .fgt = FGT_APIBKEY, |
134 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS) | 138 | .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, |
135 | |||
136 | #endif /* NPCM7XX_SMBUS_H */ | ||
137 | diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h | ||
138 | index XXXXXXX..XXXXXXX 100644 | ||
139 | --- a/include/hw/misc/npcm7xx_clk.h | ||
140 | +++ b/include/hw/misc/npcm7xx_clk.h | ||
141 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxCLKState { | ||
142 | }; | 139 | }; |
143 | 140 | ||
144 | #define TYPE_NPCM7XX_CLK "npcm7xx-clk" | 141 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
145 | -#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK) | 142 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, |
146 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK) | 143 | .access = PL1_R, .type = ARM_CP_CONST, |
147 | 144 | .accessfn = access_tid4, | |
148 | #endif /* NPCM7XX_CLK_H */ | 145 | + .fgt = FGT_CLIDR_EL1, |
149 | diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h | 146 | .resetvalue = cpu->clidr |
150 | index XXXXXXX..XXXXXXX 100644 | 147 | }; |
151 | --- a/include/hw/misc/npcm7xx_gcr.h | 148 | define_one_arm_cp_reg(cpu, &clidr); |
152 | +++ b/include/hw/misc/npcm7xx_gcr.h | ||
153 | @@ -XXX,XX +XXX,XX @@ | ||
154 | */ | ||
155 | #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) | ||
156 | |||
157 | -typedef struct NPCM7xxGCRState { | ||
158 | +struct NPCM7xxGCRState { | ||
159 | SysBusDevice parent; | ||
160 | |||
161 | MemoryRegion iomem; | ||
162 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxGCRState { | ||
163 | uint32_t reset_pwron; | ||
164 | uint32_t reset_mdlr; | ||
165 | uint32_t reset_intcr3; | ||
166 | -} NPCM7xxGCRState; | ||
167 | +}; | ||
168 | |||
169 | #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" | ||
170 | -#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR) | ||
171 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR) | ||
172 | |||
173 | #endif /* NPCM7XX_GCR_H */ | ||
174 | diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h | ||
175 | index XXXXXXX..XXXXXXX 100644 | ||
176 | --- a/include/hw/misc/npcm7xx_mft.h | ||
177 | +++ b/include/hw/misc/npcm7xx_mft.h | ||
178 | @@ -XXX,XX +XXX,XX @@ | ||
179 | * @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1. | ||
180 | * @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY. | ||
181 | */ | ||
182 | -typedef struct NPCM7xxMFTState { | ||
183 | +struct NPCM7xxMFTState { | ||
184 | SysBusDevice parent; | ||
185 | |||
186 | MemoryRegion iomem; | ||
187 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMFTState { | ||
188 | |||
189 | uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT]; | ||
190 | uint32_t duty[NPCM7XX_MFT_FANIN_COUNT]; | ||
191 | -} NPCM7xxMFTState; | ||
192 | +}; | ||
193 | |||
194 | #define TYPE_NPCM7XX_MFT "npcm7xx-mft" | ||
195 | -#define NPCM7XX_MFT(obj) \ | ||
196 | - OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT) | ||
197 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT) | ||
198 | |||
199 | #endif /* NPCM7XX_MFT_H */ | ||
200 | diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h | ||
201 | index XXXXXXX..XXXXXXX 100644 | ||
202 | --- a/include/hw/misc/npcm7xx_pwm.h | ||
203 | +++ b/include/hw/misc/npcm7xx_pwm.h | ||
204 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState { | ||
205 | }; | ||
206 | |||
207 | #define TYPE_NPCM7XX_PWM "npcm7xx-pwm" | ||
208 | -#define NPCM7XX_PWM(obj) \ | ||
209 | - OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM) | ||
210 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM) | ||
211 | |||
212 | #endif /* NPCM7XX_PWM_H */ | ||
213 | diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h | ||
214 | index XXXXXXX..XXXXXXX 100644 | ||
215 | --- a/include/hw/misc/npcm7xx_rng.h | ||
216 | +++ b/include/hw/misc/npcm7xx_rng.h | ||
217 | @@ -XXX,XX +XXX,XX @@ | ||
218 | |||
219 | #include "hw/sysbus.h" | ||
220 | |||
221 | -typedef struct NPCM7xxRNGState { | ||
222 | +struct NPCM7xxRNGState { | ||
223 | SysBusDevice parent; | ||
224 | |||
225 | MemoryRegion iomem; | ||
226 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRNGState { | ||
227 | uint8_t rngcs; | ||
228 | uint8_t rngd; | ||
229 | uint8_t rngmode; | ||
230 | -} NPCM7xxRNGState; | ||
231 | +}; | ||
232 | |||
233 | #define TYPE_NPCM7XX_RNG "npcm7xx-rng" | ||
234 | -#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG) | ||
235 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG) | ||
236 | |||
237 | #endif /* NPCM7XX_RNG_H */ | ||
238 | diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h | ||
239 | index XXXXXXX..XXXXXXX 100644 | ||
240 | --- a/include/hw/net/npcm7xx_emc.h | ||
241 | +++ b/include/hw/net/npcm7xx_emc.h | ||
242 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxEMCState { | ||
243 | bool rx_active; | ||
244 | }; | ||
245 | |||
246 | -typedef struct NPCM7xxEMCState NPCM7xxEMCState; | ||
247 | - | ||
248 | #define TYPE_NPCM7XX_EMC "npcm7xx-emc" | ||
249 | -#define NPCM7XX_EMC(obj) \ | ||
250 | - OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC) | ||
251 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC) | ||
252 | |||
253 | #endif /* NPCM7XX_EMC_H */ | ||
254 | diff --git a/include/hw/sd/npcm7xx_sdhci.h b/include/hw/sd/npcm7xx_sdhci.h | ||
255 | index XXXXXXX..XXXXXXX 100644 | ||
256 | --- a/include/hw/sd/npcm7xx_sdhci.h | ||
257 | +++ b/include/hw/sd/npcm7xx_sdhci.h | ||
258 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRegs { | ||
259 | uint32_t boottoctrl; | ||
260 | } NPCM7xxRegisters; | ||
261 | |||
262 | -typedef struct NPCM7xxSDHCIState { | ||
263 | +struct NPCM7xxSDHCIState { | ||
264 | SysBusDevice parent; | ||
265 | |||
266 | MemoryRegion container; | ||
267 | @@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSDHCIState { | ||
268 | NPCM7xxRegisters regs; | ||
269 | |||
270 | SDHCIState sdhci; | ||
271 | -} NPCM7xxSDHCIState; | ||
272 | +}; | ||
273 | |||
274 | #endif /* NPCM7XX_SDHCI_H */ | ||
275 | -- | 149 | -- |
276 | 2.34.1 | 150 | 2.34.1 |
277 | |||
278 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the registers trapped |
---|---|---|---|
2 | by HFGRTR/HFGWTR bits 12..23. | ||
2 | 3 | ||
3 | Following docs/devel/style.rst guidelines, rename omap2_gpif_s -> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Omap2GpioState. This also remove a use of 'struct' in the | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | DECLARE_INSTANCE_CHECKER() macro call. | 6 | Tested-by: Fuad Tabba <tabba@google.com> |
7 | Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org | ||
8 | Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/cpregs.h | 12 ++++++++++++ | ||
11 | target/arm/helper.c | 12 ++++++++++++ | ||
12 | 2 files changed, 24 insertions(+) | ||
6 | 13 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 14 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230109140306.23161-6-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/omap.h | 9 ++++----- | ||
13 | hw/gpio/omap_gpio.c | 20 ++++++++++---------- | ||
14 | 2 files changed, 14 insertions(+), 15 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/omap.h | 16 | --- a/target/arm/cpregs.h |
19 | +++ b/include/hw/arm/omap.h | 17 | +++ b/target/arm/cpregs.h |
20 | @@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, | 18 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
21 | TYPE_OMAP1_GPIO) | 19 | DO_BIT(HFGRTR, CCSIDR_EL1), |
22 | 20 | DO_BIT(HFGRTR, CLIDR_EL1), | |
23 | #define TYPE_OMAP2_GPIO "omap2-gpio" | 21 | DO_BIT(HFGRTR, CONTEXTIDR_EL1), |
24 | -DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO, | 22 | + DO_BIT(HFGRTR, CPACR_EL1), |
25 | +typedef struct Omap2GpioState Omap2GpioState; | 23 | + DO_BIT(HFGRTR, CSSELR_EL1), |
26 | +DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO, | 24 | + DO_BIT(HFGRTR, CTR_EL0), |
27 | TYPE_OMAP2_GPIO) | 25 | + DO_BIT(HFGRTR, DCZID_EL0), |
28 | 26 | + DO_BIT(HFGRTR, ESR_EL1), | |
29 | -typedef struct omap2_gpif_s omap2_gpif; | 27 | + DO_BIT(HFGRTR, FAR_EL1), |
30 | - | 28 | + DO_BIT(HFGRTR, ISR_EL1), |
31 | /* TODO: clock framework (see above) */ | 29 | + DO_BIT(HFGRTR, LORC_EL1), |
32 | void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); | 30 | + DO_BIT(HFGRTR, LOREA_EL1), |
33 | 31 | + DO_BIT(HFGRTR, LORID_EL1), | |
34 | -void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); | 32 | + DO_BIT(HFGRTR, LORN_EL1), |
35 | -void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); | 33 | + DO_BIT(HFGRTR, LORSA_EL1), |
36 | +void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk); | 34 | } FGTBit; |
37 | +void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk); | 35 | |
38 | 36 | #undef DO_BIT | |
39 | /* OMAP2 l4 Interconnect */ | 37 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
40 | struct omap_l4_s; | ||
41 | diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
43 | --- a/hw/gpio/omap_gpio.c | 39 | --- a/target/arm/helper.c |
44 | +++ b/hw/gpio/omap_gpio.c | 40 | +++ b/target/arm/helper.c |
45 | @@ -XXX,XX +XXX,XX @@ struct omap2_gpio_s { | 41 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { |
46 | uint8_t delay; | 42 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, |
43 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, | ||
44 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, | ||
45 | + .fgt = FGT_CPACR_EL1, | ||
46 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), | ||
47 | .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read }, | ||
47 | }; | 48 | }; |
48 | 49 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | |
49 | -struct omap2_gpif_s { | 50 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, |
50 | +struct Omap2GpioState { | 51 | .access = PL1_RW, |
51 | SysBusDevice parent_obj; | 52 | .accessfn = access_tid4, |
52 | 53 | + .fgt = FGT_CSSELR_EL1, | |
53 | MemoryRegion iomem; | 54 | .writefn = csselr_write, .resetvalue = 0, |
54 | @@ -XXX,XX +XXX,XX @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line) | 55 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), |
55 | 56 | offsetof(CPUARMState, cp15.csselr_ns) } }, | |
56 | static void omap2_gpio_set(void *opaque, int line, int level) | 57 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { |
57 | { | 58 | .resetfn = arm_cp_reset_ignore }, |
58 | - struct omap2_gpif_s *p = opaque; | 59 | { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, |
59 | + Omap2GpioState *p = opaque; | 60 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0, |
60 | struct omap2_gpio_s *s = &p->modules[line >> 5]; | 61 | + .fgt = FGT_ISR_EL1, |
61 | 62 | .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read }, | |
62 | line &= 31; | 63 | /* 32 bit ITLB invalidates */ |
63 | @@ -XXX,XX +XXX,XX @@ static void omap_gpif_reset(DeviceState *dev) | 64 | { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0, |
64 | 65 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { | |
65 | static void omap2_gpif_reset(DeviceState *dev) | 66 | { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64, |
66 | { | 67 | .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, |
67 | - struct omap2_gpif_s *s = OMAP2_GPIO(dev); | 68 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
68 | + Omap2GpioState *s = OMAP2_GPIO(dev); | 69 | + .fgt = FGT_FAR_EL1, |
69 | int i; | 70 | .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]), |
70 | 71 | .resetvalue = 0, }, | |
71 | for (i = 0; i < s->modulecount; i++) { | ||
72 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev) | ||
73 | |||
74 | static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size) | ||
75 | { | ||
76 | - struct omap2_gpif_s *s = opaque; | ||
77 | + Omap2GpioState *s = opaque; | ||
78 | |||
79 | switch (addr) { | ||
80 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | ||
81 | @@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size) | ||
82 | static void omap2_gpif_top_write(void *opaque, hwaddr addr, | ||
83 | uint64_t value, unsigned size) | ||
84 | { | ||
85 | - struct omap2_gpif_s *s = opaque; | ||
86 | + Omap2GpioState *s = opaque; | ||
87 | |||
88 | switch (addr) { | ||
89 | case 0x00: /* IPGENERICOCPSPL_REVISION */ | ||
90 | @@ -XXX,XX +XXX,XX @@ static void omap_gpio_realize(DeviceState *dev, Error **errp) | ||
91 | |||
92 | static void omap2_gpio_realize(DeviceState *dev, Error **errp) | ||
93 | { | ||
94 | - struct omap2_gpif_s *s = OMAP2_GPIO(dev); | ||
95 | + Omap2GpioState *s = OMAP2_GPIO(dev); | ||
96 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
97 | int i; | ||
98 | |||
99 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_gpio_info = { | ||
100 | .class_init = omap_gpio_class_init, | ||
101 | }; | 72 | }; |
102 | 73 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | |
103 | -void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) | 74 | { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, |
104 | +void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk) | 75 | .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, |
105 | { | 76 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
106 | gpio->iclk = clk; | 77 | + .fgt = FGT_ESR_EL1, |
107 | } | 78 | .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, }, |
108 | 79 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, | |
109 | -void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) | 80 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, |
110 | +void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk) | 81 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
111 | { | 82 | { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64, |
112 | assert(i <= 5); | 83 | .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0, |
113 | gpio->fclk[i] = clk; | 84 | .access = PL0_R, .type = ARM_CP_NO_RAW, |
114 | } | 85 | + .fgt = FGT_DCZID_EL0, |
115 | 86 | .readfn = aa64_dczid_read }, | |
116 | static Property omap2_gpio_properties[] = { | 87 | { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64, |
117 | - DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), | 88 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1, |
118 | + DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0), | 89 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { |
119 | DEFINE_PROP_END_OF_LIST(), | 90 | { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, |
91 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, | ||
92 | .access = PL1_RW, .accessfn = access_lor_other, | ||
93 | + .fgt = FGT_LORSA_EL1, | ||
94 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
95 | { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, | ||
96 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, | ||
97 | .access = PL1_RW, .accessfn = access_lor_other, | ||
98 | + .fgt = FGT_LOREA_EL1, | ||
99 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
100 | { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, | ||
101 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, | ||
102 | .access = PL1_RW, .accessfn = access_lor_other, | ||
103 | + .fgt = FGT_LORN_EL1, | ||
104 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
105 | { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, | ||
106 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, | ||
107 | .access = PL1_RW, .accessfn = access_lor_other, | ||
108 | + .fgt = FGT_LORC_EL1, | ||
109 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
110 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | ||
111 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | ||
112 | .access = PL1_R, .accessfn = access_lor_ns, | ||
113 | + .fgt = FGT_LORID_EL1, | ||
114 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
120 | }; | 115 | }; |
121 | 116 | ||
122 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data) | 117 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
123 | static const TypeInfo omap2_gpio_info = { | 118 | { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64, |
124 | .name = TYPE_OMAP2_GPIO, | 119 | .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0, |
125 | .parent = TYPE_SYS_BUS_DEVICE, | 120 | .access = PL0_R, .accessfn = ctr_el0_access, |
126 | - .instance_size = sizeof(struct omap2_gpif_s), | 121 | + .fgt = FGT_CTR_EL0, |
127 | + .instance_size = sizeof(Omap2GpioState), | 122 | .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, |
128 | .class_init = omap2_gpio_class_init, | 123 | /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ |
129 | }; | 124 | { .name = "TCMTR", |
130 | |||
131 | -- | 125 | -- |
132 | 2.34.1 | 126 | 2.34.1 |
133 | |||
134 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the registers trapped |
---|---|---|---|
2 | by HFGRTR/HFGWTR bits 24..35. | ||
2 | 3 | ||
3 | The typedef and definitions are generated by the OBJECT_DECLARE_TYPE | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | macro in "hw/arm/bcm2836.h": | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Tested-by: Fuad Tabba <tabba@google.com> | ||
7 | Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org | ||
8 | Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/cpregs.h | 12 ++++++++++++ | ||
11 | target/arm/helper.c | 14 ++++++++++++++ | ||
12 | 2 files changed, 26 insertions(+) | ||
5 | 13 | ||
6 | 20 #define TYPE_BCM283X "bcm283x" | 14 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
7 | 21 OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X) | ||
8 | |||
9 | The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when | ||
10 | possible") missed them because they are declared in a different | ||
11 | file unit. Remove them. | ||
12 | |||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20230109140306.23161-10-philmd@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | hw/arm/bcm2836.c | 9 ++------- | ||
19 | 1 file changed, 2 insertions(+), 7 deletions(-) | ||
20 | |||
21 | diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/bcm2836.c | 16 | --- a/target/arm/cpregs.h |
24 | +++ b/hw/arm/bcm2836.c | 17 | +++ b/target/arm/cpregs.h |
25 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
26 | #include "hw/arm/raspi_platform.h" | 19 | DO_BIT(HFGRTR, LORID_EL1), |
27 | #include "hw/sysbus.h" | 20 | DO_BIT(HFGRTR, LORN_EL1), |
28 | 21 | DO_BIT(HFGRTR, LORSA_EL1), | |
29 | -typedef struct BCM283XClass { | 22 | + DO_BIT(HFGRTR, MAIR_EL1), |
30 | +struct BCM283XClass { | 23 | + DO_BIT(HFGRTR, MIDR_EL1), |
31 | /*< private >*/ | 24 | + DO_BIT(HFGRTR, MPIDR_EL1), |
32 | DeviceClass parent_class; | 25 | + DO_BIT(HFGRTR, PAR_EL1), |
33 | /*< public >*/ | 26 | + DO_BIT(HFGRTR, REVIDR_EL1), |
34 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass { | 27 | + DO_BIT(HFGRTR, SCTLR_EL1), |
35 | hwaddr peri_base; /* Peripheral base address seen by the CPU */ | 28 | + DO_BIT(HFGRTR, SCXTNUM_EL1), |
36 | hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ | 29 | + DO_BIT(HFGRTR, SCXTNUM_EL0), |
37 | int clusterid; | 30 | + DO_BIT(HFGRTR, TCR_EL1), |
38 | -} BCM283XClass; | 31 | + DO_BIT(HFGRTR, TPIDR_EL1), |
39 | - | 32 | + DO_BIT(HFGRTR, TPIDRRO_EL0), |
40 | -#define BCM283X_CLASS(klass) \ | 33 | + DO_BIT(HFGRTR, TPIDR_EL0), |
41 | - OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) | 34 | } FGTBit; |
42 | -#define BCM283X_GET_CLASS(obj) \ | 35 | |
43 | - OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) | 36 | #undef DO_BIT |
44 | +}; | 37 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
45 | 38 | index XXXXXXX..XXXXXXX 100644 | |
46 | static Property bcm2836_enabled_cores_property = | 39 | --- a/target/arm/helper.c |
47 | DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); | 40 | +++ b/target/arm/helper.c |
41 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
42 | { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, | ||
43 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, | ||
44 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
45 | + .fgt = FGT_MAIR_EL1, | ||
46 | .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), | ||
47 | .resetvalue = 0 }, | ||
48 | { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64, | ||
49 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { | ||
50 | { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64, | ||
51 | .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0, | ||
52 | .access = PL0_RW, | ||
53 | + .fgt = FGT_TPIDR_EL0, | ||
54 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 }, | ||
55 | { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2, | ||
56 | .access = PL0_RW, | ||
57 | + .fgt = FGT_TPIDR_EL0, | ||
58 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s), | ||
59 | offsetoflow32(CPUARMState, cp15.tpidrurw_ns) }, | ||
60 | .resetfn = arm_cp_reset_ignore }, | ||
61 | { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64, | ||
62 | .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0, | ||
63 | .access = PL0_R | PL1_W, | ||
64 | + .fgt = FGT_TPIDRRO_EL0, | ||
65 | .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]), | ||
66 | .resetvalue = 0}, | ||
67 | { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3, | ||
68 | .access = PL0_R | PL1_W, | ||
69 | + .fgt = FGT_TPIDRRO_EL0, | ||
70 | .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s), | ||
71 | offsetoflow32(CPUARMState, cp15.tpidruro_ns) }, | ||
72 | .resetfn = arm_cp_reset_ignore }, | ||
73 | { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64, | ||
74 | .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0, | ||
75 | .access = PL1_RW, | ||
76 | + .fgt = FGT_TPIDR_EL1, | ||
77 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 }, | ||
78 | { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4, | ||
79 | .access = PL1_RW, | ||
80 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
81 | { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, | ||
82 | .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, | ||
83 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
84 | + .fgt = FGT_TCR_EL1, | ||
85 | .writefn = vmsa_tcr_el12_write, | ||
86 | .raw_writefn = raw_write, | ||
87 | .resetvalue = 0, | ||
88 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
89 | .type = ARM_CP_ALIAS, | ||
90 | .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, | ||
91 | .access = PL1_RW, .resetvalue = 0, | ||
92 | + .fgt = FGT_PAR_EL1, | ||
93 | .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), | ||
94 | .writefn = par_write }, | ||
95 | #endif | ||
96 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = { | ||
97 | { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, | ||
98 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7, | ||
99 | .access = PL0_RW, .accessfn = access_scxtnum, | ||
100 | + .fgt = FGT_SCXTNUM_EL0, | ||
101 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, | ||
102 | { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, | ||
103 | .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7, | ||
104 | .access = PL1_RW, .accessfn = access_scxtnum, | ||
105 | + .fgt = FGT_SCXTNUM_EL1, | ||
106 | .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, | ||
107 | { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, | ||
108 | .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7, | ||
109 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
110 | { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
111 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0, | ||
112 | .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, | ||
113 | + .fgt = FGT_MIDR_EL1, | ||
114 | .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), | ||
115 | .readfn = midr_read }, | ||
116 | /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */ | ||
117 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
118 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6, | ||
119 | .access = PL1_R, | ||
120 | .accessfn = access_aa64_tid1, | ||
121 | + .fgt = FGT_REVIDR_EL1, | ||
122 | .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, | ||
123 | }; | ||
124 | ARMCPRegInfo id_v8_midr_alias_cp_reginfo = { | ||
125 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
126 | ARMCPRegInfo mpidr_cp_reginfo[] = { | ||
127 | { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
128 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, | ||
129 | + .fgt = FGT_MPIDR_EL1, | ||
130 | .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, | ||
131 | }; | ||
132 | #ifdef CONFIG_USER_ONLY | ||
133 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
134 | .name = "SCTLR", .state = ARM_CP_STATE_BOTH, | ||
135 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, | ||
136 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
137 | + .fgt = FGT_SCTLR_EL1, | ||
138 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s), | ||
139 | offsetof(CPUARMState, cp15.sctlr_ns) }, | ||
140 | .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr, | ||
48 | -- | 141 | -- |
49 | 2.34.1 | 142 | 2.34.1 |
50 | |||
51 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the registers trapped |
---|---|---|---|
2 | by HFGRTR/HFGWTR bits 36..63. | ||
2 | 3 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 4 | Of these, some correspond to RAS registers which we implement as |
5 | always-UNDEF: these don't need any extra handling for FGT because the | ||
6 | UNDEF-to-EL1 always takes priority over any theoretical | ||
7 | FGT-trap-to-EL2. | ||
8 | |||
9 | Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part | ||
10 | of the FEAT_LS64_ACCDATA feature which we don't yet implement. | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20230109140306.23161-8-philmd@linaro.org | 14 | Tested-by: Fuad Tabba <tabba@google.com> |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org |
16 | Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org | ||
7 | --- | 17 | --- |
8 | hw/arm/stellaris.c | 6 +++--- | 18 | target/arm/cpregs.h | 7 +++++++ |
9 | 1 file changed, 3 insertions(+), 3 deletions(-) | 19 | hw/intc/arm_gicv3_cpuif.c | 2 ++ |
20 | target/arm/helper.c | 10 ++++++++++ | ||
21 | 3 files changed, 19 insertions(+) | ||
10 | 22 | ||
11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 23 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
12 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/stellaris.c | 25 | --- a/target/arm/cpregs.h |
14 | +++ b/hw/arm/stellaris.c | 26 | +++ b/target/arm/cpregs.h |
15 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s) | 27 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
16 | 28 | DO_BIT(HFGRTR, TPIDR_EL1), | |
17 | static void stellaris_adc_trigger(void *opaque, int irq, int level) | 29 | DO_BIT(HFGRTR, TPIDRRO_EL0), |
18 | { | 30 | DO_BIT(HFGRTR, TPIDR_EL0), |
19 | - stellaris_adc_state *s = (stellaris_adc_state *)opaque; | 31 | + DO_BIT(HFGRTR, TTBR0_EL1), |
20 | + stellaris_adc_state *s = opaque; | 32 | + DO_BIT(HFGRTR, TTBR1_EL1), |
21 | int n; | 33 | + DO_BIT(HFGRTR, VBAR_EL1), |
22 | 34 | + DO_BIT(HFGRTR, ICC_IGRPENN_EL1), | |
23 | for (n = 0; n < 4; n++) { | 35 | + DO_BIT(HFGRTR, ERRIDR_EL1), |
24 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s) | 36 | + DO_REV_BIT(HFGRTR, NSMPRI_EL1), |
25 | static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, | 37 | + DO_REV_BIT(HFGRTR, NTPIDR2_EL0), |
26 | unsigned size) | 38 | } FGTBit; |
27 | { | 39 | |
28 | - stellaris_adc_state *s = (stellaris_adc_state *)opaque; | 40 | #undef DO_BIT |
29 | + stellaris_adc_state *s = opaque; | 41 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
30 | 42 | index XXXXXXX..XXXXXXX 100644 | |
31 | /* TODO: Implement this. */ | 43 | --- a/hw/intc/arm_gicv3_cpuif.c |
32 | if (offset >= 0x40 && offset < 0xc0) { | 44 | +++ b/hw/intc/arm_gicv3_cpuif.c |
33 | @@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset, | 45 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { |
34 | static void stellaris_adc_write(void *opaque, hwaddr offset, | 46 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6, |
35 | uint64_t value, unsigned size) | 47 | .type = ARM_CP_IO | ARM_CP_NO_RAW, |
36 | { | 48 | .access = PL1_RW, .accessfn = gicv3_fiq_access, |
37 | - stellaris_adc_state *s = (stellaris_adc_state *)opaque; | 49 | + .fgt = FGT_ICC_IGRPENN_EL1, |
38 | + stellaris_adc_state *s = opaque; | 50 | .readfn = icc_igrpen_read, |
39 | 51 | .writefn = icc_igrpen_write, | |
40 | /* TODO: Implement this. */ | 52 | }, |
41 | if (offset >= 0x40 && offset < 0xc0) { | 53 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = { |
54 | .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, | ||
55 | .type = ARM_CP_IO | ARM_CP_NO_RAW, | ||
56 | .access = PL1_RW, .accessfn = gicv3_irq_access, | ||
57 | + .fgt = FGT_ICC_IGRPENN_EL1, | ||
58 | .readfn = icc_igrpen_read, | ||
59 | .writefn = icc_igrpen_write, | ||
60 | }, | ||
61 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/helper.c | ||
64 | +++ b/target/arm/helper.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { | ||
66 | { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, | ||
67 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, | ||
68 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
69 | + .fgt = FGT_TTBR0_EL1, | ||
70 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
71 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), | ||
72 | offsetof(CPUARMState, cp15.ttbr0_ns) } }, | ||
73 | { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, | ||
74 | .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, | ||
75 | .access = PL1_RW, .accessfn = access_tvm_trvm, | ||
76 | + .fgt = FGT_TTBR1_EL1, | ||
77 | .writefn = vmsa_ttbr_write, .resetvalue = 0, | ||
78 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), | ||
79 | offsetof(CPUARMState, cp15.ttbr1_ns) } }, | ||
80 | @@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) | ||
81 | * ERRSELR_EL1 | ||
82 | * may generate UNDEFINED, which is the effect we get by not | ||
83 | * listing them at all. | ||
84 | + * | ||
85 | + * These registers have fine-grained trap bits, but UNDEF-to-EL1 | ||
86 | + * is higher priority than FGT-to-EL2 so we do not need to list them | ||
87 | + * in order to check for an FGT. | ||
88 | */ | ||
89 | static const ARMCPRegInfo minimal_ras_reginfo[] = { | ||
90 | { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH, | ||
91 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = { | ||
92 | { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH, | ||
93 | .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0, | ||
94 | .access = PL1_R, .accessfn = access_terr, | ||
95 | + .fgt = FGT_ERRIDR_EL1, | ||
96 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
97 | { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH, | ||
98 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1, | ||
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = { | ||
100 | { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64, | ||
101 | .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5, | ||
102 | .access = PL0_RW, .accessfn = access_tpidr2, | ||
103 | + .fgt = FGT_NTPIDR2_EL0, | ||
104 | .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) }, | ||
105 | { .name = "SVCR", .state = ARM_CP_STATE_AA64, | ||
106 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2, | ||
107 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = { | ||
108 | { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64, | ||
109 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4, | ||
110 | .access = PL1_RW, .accessfn = access_esm, | ||
111 | + .fgt = FGT_NSMPRI_EL1, | ||
112 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
113 | { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64, | ||
114 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5, | ||
115 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
116 | { .name = "VBAR", .state = ARM_CP_STATE_BOTH, | ||
117 | .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, | ||
118 | .access = PL1_RW, .writefn = vbar_write, | ||
119 | + .fgt = FGT_VBAR_EL1, | ||
120 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s), | ||
121 | offsetof(CPUARMState, cp15.vbar_ns) }, | ||
122 | .resetvalue = 0 }, | ||
42 | -- | 123 | -- |
43 | 2.34.1 | 124 | 2.34.1 |
44 | |||
45 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitons for the registers trapped |
---|---|---|---|
2 | by HDFGRTR/HDFGWTR bits 0..11. These cover various debug | ||
3 | related registers. | ||
2 | 4 | ||
3 | Add a local 'struct omap_gpif_s *' variable to improve readability. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | (This also eases next commit conversion). | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Tested-by: Fuad Tabba <tabba@google.com> | ||
8 | Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org | ||
9 | Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpregs.h | 12 ++++++++++++ | ||
12 | target/arm/debug_helper.c | 11 +++++++++++ | ||
13 | 2 files changed, 23 insertions(+) | ||
5 | 14 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 15 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230109140306.23161-3-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/gpio/omap_gpio.c | 3 ++- | ||
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/gpio/omap_gpio.c | 17 | --- a/target/arm/cpregs.h |
17 | +++ b/hw/gpio/omap_gpio.c | 18 | +++ b/target/arm/cpregs.h |
18 | @@ -XXX,XX +XXX,XX @@ struct omap_gpif_s { | 19 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
19 | /* General-Purpose I/O of OMAP1 */ | 20 | DO_BIT(HFGRTR, ERRIDR_EL1), |
20 | static void omap_gpio_set(void *opaque, int line, int level) | 21 | DO_REV_BIT(HFGRTR, NSMPRI_EL1), |
21 | { | 22 | DO_REV_BIT(HFGRTR, NTPIDR2_EL0), |
22 | - struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1; | 23 | + |
23 | + struct omap_gpif_s *p = opaque; | 24 | + /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ |
24 | + struct omap_gpio_s *s = &p->omap1; | 25 | + DO_BIT(HDFGRTR, DBGBCRN_EL1), |
25 | uint16_t prev = s->inputs; | 26 | + DO_BIT(HDFGRTR, DBGBVRN_EL1), |
26 | 27 | + DO_BIT(HDFGRTR, DBGWCRN_EL1), | |
27 | if (level) | 28 | + DO_BIT(HDFGRTR, DBGWVRN_EL1), |
29 | + DO_BIT(HDFGRTR, MDSCR_EL1), | ||
30 | + DO_BIT(HDFGRTR, DBGCLAIM), | ||
31 | + DO_BIT(HDFGWTR, OSLAR_EL1), | ||
32 | + DO_BIT(HDFGRTR, OSLSR_EL1), | ||
33 | + DO_BIT(HDFGRTR, OSECCR_EL1), | ||
34 | + DO_BIT(HDFGRTR, OSDLR_EL1), | ||
35 | } FGTBit; | ||
36 | |||
37 | #undef DO_BIT | ||
38 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/debug_helper.c | ||
41 | +++ b/target/arm/debug_helper.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
43 | { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH, | ||
44 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | ||
45 | .access = PL1_RW, .accessfn = access_tda, | ||
46 | + .fgt = FGT_MDSCR_EL1, | ||
47 | .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), | ||
48 | .resetvalue = 0 }, | ||
49 | /* | ||
50 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
51 | { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, | ||
52 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | ||
53 | .access = PL1_RW, .accessfn = access_tda, | ||
54 | + .fgt = FGT_OSECCR_EL1, | ||
55 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
56 | /* | ||
57 | * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as | ||
58 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
59 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4, | ||
60 | .access = PL1_W, .type = ARM_CP_NO_RAW, | ||
61 | .accessfn = access_tdosa, | ||
62 | + .fgt = FGT_OSLAR_EL1, | ||
63 | .writefn = oslar_write }, | ||
64 | { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH, | ||
65 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4, | ||
66 | .access = PL1_R, .resetvalue = 10, | ||
67 | .accessfn = access_tdosa, | ||
68 | + .fgt = FGT_OSLSR_EL1, | ||
69 | .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) }, | ||
70 | /* Dummy OSDLR_EL1: 32-bit Linux will read this */ | ||
71 | { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH, | ||
72 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4, | ||
73 | .access = PL1_RW, .accessfn = access_tdosa, | ||
74 | + .fgt = FGT_OSDLR_EL1, | ||
75 | .writefn = osdlr_write, | ||
76 | .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) }, | ||
77 | /* | ||
78 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { | ||
79 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6, | ||
80 | .type = ARM_CP_ALIAS, | ||
81 | .access = PL1_RW, .accessfn = access_tda, | ||
82 | + .fgt = FGT_DBGCLAIM, | ||
83 | .writefn = dbgclaimset_write, .readfn = dbgclaimset_read }, | ||
84 | { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH, | ||
85 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6, | ||
86 | .access = PL1_RW, .accessfn = access_tda, | ||
87 | + .fgt = FGT_DBGCLAIM, | ||
88 | .writefn = dbgclaimclr_write, .raw_writefn = raw_write, | ||
89 | .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) }, | ||
90 | }; | ||
91 | @@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu) | ||
92 | { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
93 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4, | ||
94 | .access = PL1_RW, .accessfn = access_tda, | ||
95 | + .fgt = FGT_DBGBVRN_EL1, | ||
96 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]), | ||
97 | .writefn = dbgbvr_write, .raw_writefn = raw_write | ||
98 | }, | ||
99 | { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
100 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5, | ||
101 | .access = PL1_RW, .accessfn = access_tda, | ||
102 | + .fgt = FGT_DBGBCRN_EL1, | ||
103 | .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]), | ||
104 | .writefn = dbgbcr_write, .raw_writefn = raw_write | ||
105 | }, | ||
106 | @@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu) | ||
107 | { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
108 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6, | ||
109 | .access = PL1_RW, .accessfn = access_tda, | ||
110 | + .fgt = FGT_DBGWVRN_EL1, | ||
111 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]), | ||
112 | .writefn = dbgwvr_write, .raw_writefn = raw_write | ||
113 | }, | ||
114 | { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH, | ||
115 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7, | ||
116 | .access = PL1_RW, .accessfn = access_tda, | ||
117 | + .fgt = FGT_DBGWCRN_EL1, | ||
118 | .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]), | ||
119 | .writefn = dbgwcr_write, .raw_writefn = raw_write | ||
120 | }, | ||
28 | -- | 121 | -- |
29 | 2.34.1 | 122 | 2.34.1 |
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the registers trapped |
---|---|---|---|
2 | 2 | by HDFGRTR/HDFGWTR bits 12..x. | |
3 | IEC binary prefixes ease code review: the unit is explicit. | 3 | |
4 | 4 | Bits 12..22 and bit 58 are for PMU registers. | |
5 | Add definitions for RAM / Flash / Flash blocksize. | 5 | |
6 | 6 | The remaining bits in HDFGRTR/HDFGWTR are for traps on | |
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 7 | registers that are part of features we don't implement: |
8 | |||
9 | Bits 23..32 and 63 : FEAT_SPE | ||
10 | Bits 33..48 : FEAT_ETE | ||
11 | Bits 50..56 : FEAT_TRBE | ||
12 | Bits 59..61 : FEAT_BRBE | ||
13 | Bit 62 : FEAT_SPEv1p2. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230109115316.2235-4-philmd@linaro.org | 17 | Tested-by: Fuad Tabba <tabba@google.com> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org |
19 | Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org | ||
11 | --- | 20 | --- |
12 | hw/arm/collie.c | 16 ++++++++++------ | 21 | target/arm/cpregs.h | 12 ++++++++++++ |
13 | 1 file changed, 10 insertions(+), 6 deletions(-) | 22 | target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++ |
14 | 23 | 2 files changed, 49 insertions(+) | |
15 | diff --git a/hw/arm/collie.c b/hw/arm/collie.c | 24 | |
25 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/collie.c | 27 | --- a/target/arm/cpregs.h |
18 | +++ b/hw/arm/collie.c | 28 | +++ b/target/arm/cpregs.h |
19 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
20 | #include "cpu.h" | 30 | DO_BIT(HDFGRTR, OSLSR_EL1), |
21 | #include "qom/object.h" | 31 | DO_BIT(HDFGRTR, OSECCR_EL1), |
22 | 32 | DO_BIT(HDFGRTR, OSDLR_EL1), | |
23 | +#define RAM_SIZE (512 * MiB) | 33 | + DO_BIT(HDFGRTR, PMEVCNTRN_EL0), |
24 | +#define FLASH_SIZE (32 * MiB) | 34 | + DO_BIT(HDFGRTR, PMEVTYPERN_EL0), |
25 | +#define FLASH_SECTOR_SIZE (64 * KiB) | 35 | + DO_BIT(HDFGRTR, PMCCFILTR_EL0), |
26 | + | 36 | + DO_BIT(HDFGRTR, PMCCNTR_EL0), |
27 | struct CollieMachineState { | 37 | + DO_BIT(HDFGRTR, PMCNTEN), |
28 | MachineState parent; | 38 | + DO_BIT(HDFGRTR, PMINTEN), |
29 | 39 | + DO_BIT(HDFGRTR, PMOVS), | |
30 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE) | 40 | + DO_BIT(HDFGRTR, PMSELR_EL0), |
31 | 41 | + DO_BIT(HDFGWTR, PMSWINC_EL0), | |
32 | static struct arm_boot_info collie_binfo = { | 42 | + DO_BIT(HDFGWTR, PMCR_EL0), |
33 | .loader_start = SA_SDCS0, | 43 | + DO_BIT(HDFGRTR, PMMIR_EL1), |
34 | - .ram_size = 0x20000000, | 44 | + DO_BIT(HDFGRTR, PMCEIDN_EL0), |
35 | + .ram_size = RAM_SIZE, | 45 | } FGTBit; |
36 | }; | 46 | |
37 | 47 | #undef DO_BIT | |
38 | static void collie_init(MachineState *machine) | 48 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
39 | @@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine) | 49 | index XXXXXXX..XXXXXXX 100644 |
40 | memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); | 50 | --- a/target/arm/helper.c |
41 | 51 | +++ b/target/arm/helper.c | |
42 | dinfo = drive_get(IF_PFLASH, 0, 0); | 52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { |
43 | - pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, | 53 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
44 | + pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE, | 54 | .writefn = pmcntenset_write, |
45 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 55 | .accessfn = pmreg_access, |
46 | - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); | 56 | + .fgt = FGT_PMCNTEN, |
47 | + FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0); | 57 | .raw_writefn = raw_write }, |
48 | 58 | { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, | |
49 | dinfo = drive_get(IF_PFLASH, 0, 1); | 59 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1, |
50 | - pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000, | 60 | .access = PL0_RW, .accessfn = pmreg_access, |
51 | + pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE, | 61 | + .fgt = FGT_PMCNTEN, |
52 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 62 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0, |
53 | - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); | 63 | .writefn = pmcntenset_write, .raw_writefn = raw_write }, |
54 | + FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0); | 64 | { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2, |
55 | 65 | .access = PL0_RW, | |
56 | sysbus_create_simple("scoop", 0x40800000, NULL); | 66 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten), |
57 | 67 | .accessfn = pmreg_access, | |
58 | @@ -XXX,XX +XXX,XX @@ static void collie_machine_class_init(ObjectClass *oc, void *data) | 68 | + .fgt = FGT_PMCNTEN, |
59 | mc->init = collie_init; | 69 | .writefn = pmcntenclr_write, |
60 | mc->ignore_memory_transaction_failures = true; | 70 | .type = ARM_CP_ALIAS | ARM_CP_IO }, |
61 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110"); | 71 | { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64, |
62 | - mc->default_ram_size = 0x20000000; | 72 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2, |
63 | + mc->default_ram_size = RAM_SIZE; | 73 | .access = PL0_RW, .accessfn = pmreg_access, |
64 | mc->default_ram_id = "strongarm.sdram"; | 74 | + .fgt = FGT_PMCNTEN, |
65 | } | 75 | .type = ARM_CP_ALIAS | ARM_CP_IO, |
66 | 76 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), | |
77 | .writefn = pmcntenclr_write }, | ||
78 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
79 | .access = PL0_RW, .type = ARM_CP_IO, | ||
80 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), | ||
81 | .accessfn = pmreg_access, | ||
82 | + .fgt = FGT_PMOVS, | ||
83 | .writefn = pmovsr_write, | ||
84 | .raw_writefn = raw_write }, | ||
85 | { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, | ||
86 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, | ||
87 | .access = PL0_RW, .accessfn = pmreg_access, | ||
88 | + .fgt = FGT_PMOVS, | ||
89 | .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
90 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | ||
91 | .writefn = pmovsr_write, | ||
92 | .raw_writefn = raw_write }, | ||
93 | { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, | ||
94 | .access = PL0_W, .accessfn = pmreg_access_swinc, | ||
95 | + .fgt = FGT_PMSWINC_EL0, | ||
96 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
97 | .writefn = pmswinc_write }, | ||
98 | { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64, | ||
99 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4, | ||
100 | .access = PL0_W, .accessfn = pmreg_access_swinc, | ||
101 | + .fgt = FGT_PMSWINC_EL0, | ||
102 | .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
103 | .writefn = pmswinc_write }, | ||
104 | { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5, | ||
105 | .access = PL0_RW, .type = ARM_CP_ALIAS, | ||
106 | + .fgt = FGT_PMSELR_EL0, | ||
107 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr), | ||
108 | .accessfn = pmreg_access_selr, .writefn = pmselr_write, | ||
109 | .raw_writefn = raw_write}, | ||
110 | { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64, | ||
111 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5, | ||
112 | .access = PL0_RW, .accessfn = pmreg_access_selr, | ||
113 | + .fgt = FGT_PMSELR_EL0, | ||
114 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr), | ||
115 | .writefn = pmselr_write, .raw_writefn = raw_write, }, | ||
116 | { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, | ||
117 | .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
118 | + .fgt = FGT_PMCCNTR_EL0, | ||
119 | .readfn = pmccntr_read, .writefn = pmccntr_write32, | ||
120 | .accessfn = pmreg_access_ccntr }, | ||
121 | { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64, | ||
122 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0, | ||
123 | .access = PL0_RW, .accessfn = pmreg_access_ccntr, | ||
124 | + .fgt = FGT_PMCCNTR_EL0, | ||
125 | .type = ARM_CP_IO, | ||
126 | .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt), | ||
127 | .readfn = pmccntr_read, .writefn = pmccntr_write, | ||
128 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
129 | { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7, | ||
130 | .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32, | ||
131 | .access = PL0_RW, .accessfn = pmreg_access, | ||
132 | + .fgt = FGT_PMCCFILTR_EL0, | ||
133 | .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
134 | .resetvalue = 0, }, | ||
135 | { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64, | ||
136 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7, | ||
137 | .writefn = pmccfiltr_write, .raw_writefn = raw_write, | ||
138 | .access = PL0_RW, .accessfn = pmreg_access, | ||
139 | + .fgt = FGT_PMCCFILTR_EL0, | ||
140 | .type = ARM_CP_IO, | ||
141 | .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0), | ||
142 | .resetvalue = 0, }, | ||
143 | { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, | ||
144 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
145 | .accessfn = pmreg_access, | ||
146 | + .fgt = FGT_PMEVTYPERN_EL0, | ||
147 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | ||
148 | { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64, | ||
149 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1, | ||
150 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
151 | .accessfn = pmreg_access, | ||
152 | + .fgt = FGT_PMEVTYPERN_EL0, | ||
153 | .writefn = pmxevtyper_write, .readfn = pmxevtyper_read }, | ||
154 | { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2, | ||
155 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
156 | .accessfn = pmreg_access_xevcntr, | ||
157 | + .fgt = FGT_PMEVCNTRN_EL0, | ||
158 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | ||
159 | { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64, | ||
160 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2, | ||
161 | .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO, | ||
162 | .accessfn = pmreg_access_xevcntr, | ||
163 | + .fgt = FGT_PMEVCNTRN_EL0, | ||
164 | .writefn = pmxevcntr_write, .readfn = pmxevcntr_read }, | ||
165 | { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0, | ||
166 | .access = PL0_R | PL1_RW, .accessfn = access_tpm, | ||
167 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
168 | .writefn = pmuserenr_write, .raw_writefn = raw_write }, | ||
169 | { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, | ||
170 | .access = PL1_RW, .accessfn = access_tpm, | ||
171 | + .fgt = FGT_PMINTEN, | ||
172 | .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
173 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten), | ||
174 | .resetvalue = 0, | ||
175 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
176 | { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64, | ||
177 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1, | ||
178 | .access = PL1_RW, .accessfn = access_tpm, | ||
179 | + .fgt = FGT_PMINTEN, | ||
180 | .type = ARM_CP_IO, | ||
181 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
182 | .writefn = pmintenset_write, .raw_writefn = raw_write, | ||
183 | .resetvalue = 0x0 }, | ||
184 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, | ||
185 | .access = PL1_RW, .accessfn = access_tpm, | ||
186 | + .fgt = FGT_PMINTEN, | ||
187 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, | ||
188 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
189 | .writefn = pmintenclr_write, }, | ||
190 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, | ||
191 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | ||
192 | .access = PL1_RW, .accessfn = access_tpm, | ||
193 | + .fgt = FGT_PMINTEN, | ||
194 | .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, | ||
195 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
196 | .writefn = pmintenclr_write }, | ||
197 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
198 | /* PMOVSSET is not implemented in v7 before v7ve */ | ||
199 | { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3, | ||
200 | .access = PL0_RW, .accessfn = pmreg_access, | ||
201 | + .fgt = FGT_PMOVS, | ||
202 | .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
203 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr), | ||
204 | .writefn = pmovsset_write, | ||
205 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = { | ||
206 | { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64, | ||
207 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3, | ||
208 | .access = PL0_RW, .accessfn = pmreg_access, | ||
209 | + .fgt = FGT_PMOVS, | ||
210 | .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
211 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), | ||
212 | .writefn = pmovsset_write, | ||
213 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
214 | ARMCPRegInfo pmcr = { | ||
215 | .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, | ||
216 | .access = PL0_RW, | ||
217 | + .fgt = FGT_PMCR_EL0, | ||
218 | .type = ARM_CP_IO | ARM_CP_ALIAS, | ||
219 | .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr), | ||
220 | .accessfn = pmreg_access, .writefn = pmcr_write, | ||
221 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
222 | .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64, | ||
223 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0, | ||
224 | .access = PL0_RW, .accessfn = pmreg_access, | ||
225 | + .fgt = FGT_PMCR_EL0, | ||
226 | .type = ARM_CP_IO, | ||
227 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr), | ||
228 | .resetvalue = cpu->isar.reset_pmcr_el0, | ||
229 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
230 | { .name = pmevcntr_name, .cp = 15, .crn = 14, | ||
231 | .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | ||
232 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | ||
233 | + .fgt = FGT_PMEVCNTRN_EL0, | ||
234 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | ||
235 | .accessfn = pmreg_access_xevcntr }, | ||
236 | { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, | ||
237 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), | ||
238 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, | ||
239 | .type = ARM_CP_IO, | ||
240 | + .fgt = FGT_PMEVCNTRN_EL0, | ||
241 | .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, | ||
242 | .raw_readfn = pmevcntr_rawread, | ||
243 | .raw_writefn = pmevcntr_rawwrite }, | ||
244 | { .name = pmevtyper_name, .cp = 15, .crn = 14, | ||
245 | .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, | ||
246 | .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, | ||
247 | + .fgt = FGT_PMEVTYPERN_EL0, | ||
248 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | ||
249 | .accessfn = pmreg_access }, | ||
250 | { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64, | ||
251 | .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)), | ||
252 | .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, | ||
253 | + .fgt = FGT_PMEVTYPERN_EL0, | ||
254 | .type = ARM_CP_IO, | ||
255 | .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn, | ||
256 | .raw_writefn = pmevtyper_rawwrite }, | ||
257 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
258 | { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, | ||
259 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, | ||
260 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
261 | + .fgt = FGT_PMCEIDN_EL0, | ||
262 | .resetvalue = extract64(cpu->pmceid0, 32, 32) }, | ||
263 | { .name = "PMCEID3", .state = ARM_CP_STATE_AA32, | ||
264 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5, | ||
265 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
266 | + .fgt = FGT_PMCEIDN_EL0, | ||
267 | .resetvalue = extract64(cpu->pmceid1, 32, 32) }, | ||
268 | }; | ||
269 | define_arm_cp_regs(cpu, v81_pmu_regs); | ||
270 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) | ||
271 | .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, | ||
272 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, | ||
273 | .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
274 | + .fgt = FGT_PMMIR_EL1, | ||
275 | .resetvalue = 0 | ||
276 | }; | ||
277 | define_one_arm_cp_reg(cpu, &v84_pmmir); | ||
278 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
279 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, | ||
280 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | ||
281 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
282 | + .fgt = FGT_PMCEIDN_EL0, | ||
283 | .resetvalue = extract64(cpu->pmceid0, 0, 32) }, | ||
284 | { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64, | ||
285 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6, | ||
286 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
287 | + .fgt = FGT_PMCEIDN_EL0, | ||
288 | .resetvalue = cpu->pmceid0 }, | ||
289 | { .name = "PMCEID1", .state = ARM_CP_STATE_AA32, | ||
290 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7, | ||
291 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
292 | + .fgt = FGT_PMCEIDN_EL0, | ||
293 | .resetvalue = extract64(cpu->pmceid1, 0, 32) }, | ||
294 | { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64, | ||
295 | .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7, | ||
296 | .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST, | ||
297 | + .fgt = FGT_PMCEIDN_EL0, | ||
298 | .resetvalue = cpu->pmceid1 }, | ||
299 | }; | ||
300 | #ifdef CONFIG_USER_ONLY | ||
67 | -- | 301 | -- |
68 | 2.34.1 | 302 | 2.34.1 |
69 | |||
70 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the system instructions |
---|---|---|---|
2 | trapped by HFGITR bits 0..11. These bits cover various | ||
3 | cache maintenance operations. | ||
2 | 4 | ||
3 | Following docs/devel/style.rst guidelines, rename omap_gpif_s -> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Omap1GpioState. This also remove a use of 'struct' in the | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | DECLARE_INSTANCE_CHECKER() macro call. | 7 | Tested-by: Fuad Tabba <tabba@google.com> |
8 | Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org | ||
9 | Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpregs.h | 14 ++++++++++++++ | ||
12 | target/arm/helper.c | 28 ++++++++++++++++++++++++++++ | ||
13 | 2 files changed, 42 insertions(+) | ||
6 | 14 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 15 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230109140306.23161-5-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/omap.h | 6 +++--- | ||
13 | hw/gpio/omap_gpio.c | 16 ++++++++-------- | ||
14 | 2 files changed, 11 insertions(+), 11 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/arm/omap.h | 17 | --- a/target/arm/cpregs.h |
19 | +++ b/include/hw/arm/omap.h | 18 | +++ b/target/arm/cpregs.h |
20 | @@ -XXX,XX +XXX,XX @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); | 19 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
21 | 20 | DO_BIT(HDFGWTR, PMCR_EL0), | |
22 | /* omap_gpio.c */ | 21 | DO_BIT(HDFGRTR, PMMIR_EL1), |
23 | #define TYPE_OMAP1_GPIO "omap-gpio" | 22 | DO_BIT(HDFGRTR, PMCEIDN_EL0), |
24 | -DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO, | 23 | + |
25 | +typedef struct Omap1GpioState Omap1GpioState; | 24 | + /* Trap bits in HFGITR_EL2, starting from bit 0 */ |
26 | +DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, | 25 | + DO_BIT(HFGITR, ICIALLUIS), |
27 | TYPE_OMAP1_GPIO) | 26 | + DO_BIT(HFGITR, ICIALLU), |
28 | 27 | + DO_BIT(HFGITR, ICIVAU), | |
29 | #define TYPE_OMAP2_GPIO "omap2-gpio" | 28 | + DO_BIT(HFGITR, DCIVAC), |
30 | DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO, | 29 | + DO_BIT(HFGITR, DCISW), |
31 | TYPE_OMAP2_GPIO) | 30 | + DO_BIT(HFGITR, DCCSW), |
32 | 31 | + DO_BIT(HFGITR, DCCISW), | |
33 | -typedef struct omap_gpif_s omap_gpif; | 32 | + DO_BIT(HFGITR, DCCVAU), |
34 | typedef struct omap2_gpif_s omap2_gpif; | 33 | + DO_BIT(HFGITR, DCCVAP), |
35 | 34 | + DO_BIT(HFGITR, DCCVADP), | |
36 | /* TODO: clock framework (see above) */ | 35 | + DO_BIT(HFGITR, DCCIVAC), |
37 | -void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk); | 36 | + DO_BIT(HFGITR, DCZVA), |
38 | +void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); | 37 | } FGTBit; |
39 | 38 | ||
40 | void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); | 39 | #undef DO_BIT |
41 | void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); | 40 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
42 | diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
44 | --- a/hw/gpio/omap_gpio.c | 42 | --- a/target/arm/helper.c |
45 | +++ b/hw/gpio/omap_gpio.c | 43 | +++ b/target/arm/helper.c |
46 | @@ -XXX,XX +XXX,XX @@ struct omap_gpio_s { | 44 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
47 | uint16_t pins; | 45 | #ifndef CONFIG_USER_ONLY |
48 | }; | 46 | /* Avoid overhead of an access check that always passes in user-mode */ |
49 | 47 | .accessfn = aa64_zva_access, | |
50 | -struct omap_gpif_s { | 48 | + .fgt = FGT_DCZVA, |
51 | +struct Omap1GpioState { | 49 | #endif |
52 | SysBusDevice parent_obj; | 50 | }, |
53 | 51 | { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, | |
54 | MemoryRegion iomem; | 52 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
55 | @@ -XXX,XX +XXX,XX @@ struct omap_gpif_s { | 53 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, |
56 | /* General-Purpose I/O of OMAP1 */ | 54 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, |
57 | static void omap_gpio_set(void *opaque, int line, int level) | 55 | .access = PL1_W, .type = ARM_CP_NOP, |
58 | { | 56 | + .fgt = FGT_ICIALLUIS, |
59 | - struct omap_gpif_s *p = opaque; | 57 | .accessfn = access_ticab }, |
60 | + Omap1GpioState *p = opaque; | 58 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, |
61 | struct omap_gpio_s *s = &p->omap1; | 59 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, |
62 | uint16_t prev = s->inputs; | 60 | .access = PL1_W, .type = ARM_CP_NOP, |
63 | 61 | + .fgt = FGT_ICIALLU, | |
64 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpio_module_ops = { | 62 | .accessfn = access_tocu }, |
65 | 63 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | |
66 | static void omap_gpif_reset(DeviceState *dev) | 64 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, |
67 | { | 65 | .access = PL0_W, .type = ARM_CP_NOP, |
68 | - struct omap_gpif_s *s = OMAP1_GPIO(dev); | 66 | + .fgt = FGT_ICIVAU, |
69 | + Omap1GpioState *s = OMAP1_GPIO(dev); | 67 | .accessfn = access_tocu }, |
70 | 68 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | |
71 | omap_gpio_reset(&s->omap1); | 69 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, |
72 | } | 70 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, |
73 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpif_top_ops = { | 71 | + .fgt = FGT_DCIVAC, |
74 | static void omap_gpio_init(Object *obj) | 72 | .type = ARM_CP_NOP }, |
75 | { | 73 | { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, |
76 | DeviceState *dev = DEVICE(obj); | 74 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, |
77 | - struct omap_gpif_s *s = OMAP1_GPIO(obj); | 75 | + .fgt = FGT_DCISW, |
78 | + Omap1GpioState *s = OMAP1_GPIO(obj); | 76 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
79 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 77 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, |
80 | 78 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | |
81 | qdev_init_gpio_in(dev, omap_gpio_set, 16); | 79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { |
82 | @@ -XXX,XX +XXX,XX @@ static void omap_gpio_init(Object *obj) | 80 | .accessfn = aa64_cacheop_poc_access }, |
83 | 81 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | |
84 | static void omap_gpio_realize(DeviceState *dev, Error **errp) | 82 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, |
85 | { | 83 | + .fgt = FGT_DCCSW, |
86 | - struct omap_gpif_s *s = OMAP1_GPIO(dev); | 84 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, |
87 | + Omap1GpioState *s = OMAP1_GPIO(dev); | 85 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, |
88 | 86 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | |
89 | if (!s->clk) { | 87 | .access = PL0_W, .type = ARM_CP_NOP, |
90 | error_setg(errp, "omap-gpio: clk not connected"); | 88 | + .fgt = FGT_DCCVAU, |
91 | @@ -XXX,XX +XXX,XX @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp) | 89 | .accessfn = access_tocu }, |
92 | } | 90 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, |
93 | } | 91 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, |
94 | 92 | .access = PL0_W, .type = ARM_CP_NOP, | |
95 | -void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) | 93 | + .fgt = FGT_DCCIVAC, |
96 | +void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) | 94 | .accessfn = aa64_cacheop_poc_access }, |
97 | { | 95 | { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, |
98 | gpio->clk = clk; | 96 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, |
99 | } | 97 | + .fgt = FGT_DCCISW, |
100 | 98 | .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, | |
101 | static Property omap_gpio_properties[] = { | 99 | /* TLBI operations */ |
102 | - DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), | 100 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, |
103 | + DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0), | 101 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = { |
104 | DEFINE_PROP_END_OF_LIST(), | 102 | { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64, |
105 | }; | 103 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1, |
106 | 104 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, | |
107 | @@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data) | 105 | + .fgt = FGT_DCCVAP, |
108 | static const TypeInfo omap_gpio_info = { | 106 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, |
109 | .name = TYPE_OMAP1_GPIO, | 107 | }; |
110 | .parent = TYPE_SYS_BUS_DEVICE, | 108 | |
111 | - .instance_size = sizeof(struct omap_gpif_s), | 109 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = { |
112 | + .instance_size = sizeof(Omap1GpioState), | 110 | { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64, |
113 | .instance_init = omap_gpio_init, | 111 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1, |
114 | .class_init = omap_gpio_class_init, | 112 | .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, |
113 | + .fgt = FGT_DCCVADP, | ||
114 | .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn }, | ||
115 | }; | ||
116 | #endif /*CONFIG_USER_ONLY*/ | ||
117 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
118 | { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64, | ||
119 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3, | ||
120 | .type = ARM_CP_NOP, .access = PL1_W, | ||
121 | + .fgt = FGT_DCIVAC, | ||
122 | .accessfn = aa64_cacheop_poc_access }, | ||
123 | { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64, | ||
124 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4, | ||
125 | + .fgt = FGT_DCISW, | ||
126 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
127 | { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64, | ||
128 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5, | ||
129 | .type = ARM_CP_NOP, .access = PL1_W, | ||
130 | + .fgt = FGT_DCIVAC, | ||
131 | .accessfn = aa64_cacheop_poc_access }, | ||
132 | { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64, | ||
133 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6, | ||
134 | + .fgt = FGT_DCISW, | ||
135 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
136 | { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64, | ||
137 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4, | ||
138 | + .fgt = FGT_DCCSW, | ||
139 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
140 | { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64, | ||
141 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6, | ||
142 | + .fgt = FGT_DCCSW, | ||
143 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
144 | { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64, | ||
145 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4, | ||
146 | + .fgt = FGT_DCCISW, | ||
147 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
148 | { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64, | ||
149 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6, | ||
150 | + .fgt = FGT_DCCISW, | ||
151 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
152 | }; | ||
153 | |||
154 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
155 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | ||
156 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | ||
157 | .type = ARM_CP_NOP, .access = PL0_W, | ||
158 | + .fgt = FGT_DCCVAP, | ||
159 | .accessfn = aa64_cacheop_poc_access }, | ||
160 | { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64, | ||
161 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5, | ||
162 | .type = ARM_CP_NOP, .access = PL0_W, | ||
163 | + .fgt = FGT_DCCVAP, | ||
164 | .accessfn = aa64_cacheop_poc_access }, | ||
165 | { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64, | ||
166 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3, | ||
167 | .type = ARM_CP_NOP, .access = PL0_W, | ||
168 | + .fgt = FGT_DCCVADP, | ||
169 | .accessfn = aa64_cacheop_poc_access }, | ||
170 | { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64, | ||
171 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5, | ||
172 | .type = ARM_CP_NOP, .access = PL0_W, | ||
173 | + .fgt = FGT_DCCVADP, | ||
174 | .accessfn = aa64_cacheop_poc_access }, | ||
175 | { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64, | ||
176 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3, | ||
177 | .type = ARM_CP_NOP, .access = PL0_W, | ||
178 | + .fgt = FGT_DCCIVAC, | ||
179 | .accessfn = aa64_cacheop_poc_access }, | ||
180 | { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5, | ||
182 | .type = ARM_CP_NOP, .access = PL0_W, | ||
183 | + .fgt = FGT_DCCIVAC, | ||
184 | .accessfn = aa64_cacheop_poc_access }, | ||
185 | { .name = "DC_GVA", .state = ARM_CP_STATE_AA64, | ||
186 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3, | ||
187 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
188 | #ifndef CONFIG_USER_ONLY | ||
189 | /* Avoid overhead of an access check that always passes in user-mode */ | ||
190 | .accessfn = aa64_zva_access, | ||
191 | + .fgt = FGT_DCZVA, | ||
192 | #endif | ||
193 | }, | ||
194 | { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64, | ||
195 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
196 | #ifndef CONFIG_USER_ONLY | ||
197 | /* Avoid overhead of an access check that always passes in user-mode */ | ||
198 | .accessfn = aa64_zva_access, | ||
199 | + .fgt = FGT_DCZVA, | ||
200 | #endif | ||
201 | }, | ||
115 | }; | 202 | }; |
116 | -- | 203 | -- |
117 | 2.34.1 | 204 | 2.34.1 |
118 | |||
119 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the system instructions |
---|---|---|---|
2 | trapped by HFGITR bits 12..17. These bits cover AT address | ||
3 | translation instructions. | ||
2 | 4 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Tested-by: Fuad Tabba <tabba@google.com> | ||
8 | Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org | ||
9 | Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/cpregs.h | 6 ++++++ | ||
12 | target/arm/helper.c | 6 ++++++ | ||
13 | 2 files changed, 12 insertions(+) | ||
4 | 14 | ||
5 | Add the FLASH_SECTOR_SIZE definition. | 15 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230109115316.2235-12-philmd@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/z2.c | 6 ++++-- | ||
13 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/z2.c | 17 | --- a/target/arm/cpregs.h |
18 | +++ b/hw/arm/z2.c | 18 | +++ b/target/arm/cpregs.h |
19 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
20 | */ | 20 | DO_BIT(HFGITR, DCCVADP), |
21 | 21 | DO_BIT(HFGITR, DCCIVAC), | |
22 | #include "qemu/osdep.h" | 22 | DO_BIT(HFGITR, DCZVA), |
23 | +#include "qemu/units.h" | 23 | + DO_BIT(HFGITR, ATS1E1R), |
24 | #include "hw/arm/pxa.h" | 24 | + DO_BIT(HFGITR, ATS1E1W), |
25 | #include "hw/arm/boot.h" | 25 | + DO_BIT(HFGITR, ATS1E0R), |
26 | #include "hw/i2c/i2c.h" | 26 | + DO_BIT(HFGITR, ATS1E0W), |
27 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = { | 27 | + DO_BIT(HFGITR, ATS1E1RP), |
28 | .class_init = aer915_class_init, | 28 | + DO_BIT(HFGITR, ATS1E1WP), |
29 | } FGTBit; | ||
30 | |||
31 | #undef DO_BIT | ||
32 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/helper.c | ||
35 | +++ b/target/arm/helper.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
37 | { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, | ||
38 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0, | ||
39 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
40 | + .fgt = FGT_ATS1E1R, | ||
41 | .writefn = ats_write64 }, | ||
42 | { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, | ||
43 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1, | ||
44 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
45 | + .fgt = FGT_ATS1E1W, | ||
46 | .writefn = ats_write64 }, | ||
47 | { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64, | ||
48 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2, | ||
49 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
50 | + .fgt = FGT_ATS1E0R, | ||
51 | .writefn = ats_write64 }, | ||
52 | { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64, | ||
53 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3, | ||
54 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
55 | + .fgt = FGT_ATS1E0W, | ||
56 | .writefn = ats_write64 }, | ||
57 | { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64, | ||
58 | .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4, | ||
59 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = { | ||
60 | { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64, | ||
61 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, | ||
62 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
63 | + .fgt = FGT_ATS1E1RP, | ||
64 | .writefn = ats_write64 }, | ||
65 | { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64, | ||
66 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, | ||
67 | .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, | ||
68 | + .fgt = FGT_ATS1E1WP, | ||
69 | .writefn = ats_write64 }, | ||
29 | }; | 70 | }; |
30 | 71 | ||
31 | +#define FLASH_SECTOR_SIZE (64 * KiB) | ||
32 | + | ||
33 | static void z2_init(MachineState *machine) | ||
34 | { | ||
35 | - uint32_t sector_len = 0x10000; | ||
36 | PXA2xxState *mpu; | ||
37 | DriveInfo *dinfo; | ||
38 | void *z2_lcd; | ||
39 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) | ||
40 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
41 | if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, | ||
42 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
43 | - sector_len, 4, 0, 0, 0, 0, 0)) { | ||
44 | + FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) { | ||
45 | error_report("Error registering flash memory"); | ||
46 | exit(1); | ||
47 | } | ||
48 | -- | 72 | -- |
49 | 2.34.1 | 73 | 2.34.1 |
50 | |||
51 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the system instructions |
---|---|---|---|
2 | trapped by HFGITR bits 18..47. These bits cover TLBI | ||
3 | TLB maintenance instructions. | ||
2 | 4 | ||
3 | To avoid forward-declaring PXA2xxI2CState, declare | 5 | (If we implemented FEAT_XS we would need to trap some of the |
4 | PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype. | 6 | instructions added by that feature using these bits; but we don't |
7 | yet, so will need to add the .fgt markup when we do.) | ||
5 | 8 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20230109140306.23161-2-philmd@linaro.org | 11 | Tested-by: Fuad Tabba <tabba@google.com> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org |
13 | Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org | ||
10 | --- | 14 | --- |
11 | include/hw/arm/pxa.h | 6 +++--- | 15 | target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++ |
12 | 1 file changed, 3 insertions(+), 3 deletions(-) | 16 | target/arm/helper.c | 30 ++++++++++++++++++++++++++++++ |
17 | 2 files changed, 60 insertions(+) | ||
13 | 18 | ||
14 | diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h | 19 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
15 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/arm/pxa.h | 21 | --- a/target/arm/cpregs.h |
17 | +++ b/include/hw/arm/pxa.h | 22 | +++ b/target/arm/cpregs.h |
18 | @@ -XXX,XX +XXX,XX @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp, | 23 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
19 | const struct keymap *map, int size); | 24 | DO_BIT(HFGITR, ATS1E0W), |
20 | 25 | DO_BIT(HFGITR, ATS1E1RP), | |
21 | /* pxa2xx.c */ | 26 | DO_BIT(HFGITR, ATS1E1WP), |
22 | -typedef struct PXA2xxI2CState PXA2xxI2CState; | 27 | + DO_BIT(HFGITR, TLBIVMALLE1OS), |
23 | +#define TYPE_PXA2XX_I2C "pxa2xx_i2c" | 28 | + DO_BIT(HFGITR, TLBIVAE1OS), |
24 | +OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C) | 29 | + DO_BIT(HFGITR, TLBIASIDE1OS), |
25 | + | 30 | + DO_BIT(HFGITR, TLBIVAAE1OS), |
26 | PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, | 31 | + DO_BIT(HFGITR, TLBIVALE1OS), |
27 | qemu_irq irq, uint32_t page_size); | 32 | + DO_BIT(HFGITR, TLBIVAALE1OS), |
28 | I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s); | 33 | + DO_BIT(HFGITR, TLBIRVAE1OS), |
29 | 34 | + DO_BIT(HFGITR, TLBIRVAAE1OS), | |
30 | -#define TYPE_PXA2XX_I2C "pxa2xx_i2c" | 35 | + DO_BIT(HFGITR, TLBIRVALE1OS), |
31 | typedef struct PXA2xxI2SState PXA2xxI2SState; | 36 | + DO_BIT(HFGITR, TLBIRVAALE1OS), |
32 | -OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C) | 37 | + DO_BIT(HFGITR, TLBIVMALLE1IS), |
33 | 38 | + DO_BIT(HFGITR, TLBIVAE1IS), | |
34 | #define TYPE_PXA2XX_FIR "pxa2xx-fir" | 39 | + DO_BIT(HFGITR, TLBIASIDE1IS), |
35 | OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR) | 40 | + DO_BIT(HFGITR, TLBIVAAE1IS), |
41 | + DO_BIT(HFGITR, TLBIVALE1IS), | ||
42 | + DO_BIT(HFGITR, TLBIVAALE1IS), | ||
43 | + DO_BIT(HFGITR, TLBIRVAE1IS), | ||
44 | + DO_BIT(HFGITR, TLBIRVAAE1IS), | ||
45 | + DO_BIT(HFGITR, TLBIRVALE1IS), | ||
46 | + DO_BIT(HFGITR, TLBIRVAALE1IS), | ||
47 | + DO_BIT(HFGITR, TLBIRVAE1), | ||
48 | + DO_BIT(HFGITR, TLBIRVAAE1), | ||
49 | + DO_BIT(HFGITR, TLBIRVALE1), | ||
50 | + DO_BIT(HFGITR, TLBIRVAALE1), | ||
51 | + DO_BIT(HFGITR, TLBIVMALLE1), | ||
52 | + DO_BIT(HFGITR, TLBIVAE1), | ||
53 | + DO_BIT(HFGITR, TLBIASIDE1), | ||
54 | + DO_BIT(HFGITR, TLBIVAAE1), | ||
55 | + DO_BIT(HFGITR, TLBIVALE1), | ||
56 | + DO_BIT(HFGITR, TLBIVAALE1), | ||
57 | } FGTBit; | ||
58 | |||
59 | #undef DO_BIT | ||
60 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/helper.c | ||
63 | +++ b/target/arm/helper.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
65 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | ||
66 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | ||
67 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
68 | + .fgt = FGT_TLBIVMALLE1IS, | ||
69 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
70 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | ||
71 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | ||
72 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
73 | + .fgt = FGT_TLBIVAE1IS, | ||
74 | .writefn = tlbi_aa64_vae1is_write }, | ||
75 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | ||
76 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | ||
77 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
78 | + .fgt = FGT_TLBIASIDE1IS, | ||
79 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
80 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | ||
81 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | ||
82 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
83 | + .fgt = FGT_TLBIVAAE1IS, | ||
84 | .writefn = tlbi_aa64_vae1is_write }, | ||
85 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | ||
86 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | ||
87 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
88 | + .fgt = FGT_TLBIVALE1IS, | ||
89 | .writefn = tlbi_aa64_vae1is_write }, | ||
90 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | ||
91 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | ||
92 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
93 | + .fgt = FGT_TLBIVAALE1IS, | ||
94 | .writefn = tlbi_aa64_vae1is_write }, | ||
95 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | ||
96 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | ||
97 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
98 | + .fgt = FGT_TLBIVMALLE1, | ||
99 | .writefn = tlbi_aa64_vmalle1_write }, | ||
100 | { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64, | ||
101 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1, | ||
102 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
103 | + .fgt = FGT_TLBIVAE1, | ||
104 | .writefn = tlbi_aa64_vae1_write }, | ||
105 | { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64, | ||
106 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2, | ||
107 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
108 | + .fgt = FGT_TLBIASIDE1, | ||
109 | .writefn = tlbi_aa64_vmalle1_write }, | ||
110 | { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64, | ||
111 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3, | ||
112 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
113 | + .fgt = FGT_TLBIVAAE1, | ||
114 | .writefn = tlbi_aa64_vae1_write }, | ||
115 | { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64, | ||
116 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | ||
117 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
118 | + .fgt = FGT_TLBIVALE1, | ||
119 | .writefn = tlbi_aa64_vae1_write }, | ||
120 | { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64, | ||
121 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7, | ||
122 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
123 | + .fgt = FGT_TLBIVAALE1, | ||
124 | .writefn = tlbi_aa64_vae1_write }, | ||
125 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, | ||
126 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | ||
127 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
128 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | ||
129 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | ||
130 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
131 | + .fgt = FGT_TLBIRVAE1IS, | ||
132 | .writefn = tlbi_aa64_rvae1is_write }, | ||
133 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | ||
134 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | ||
135 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
136 | + .fgt = FGT_TLBIRVAAE1IS, | ||
137 | .writefn = tlbi_aa64_rvae1is_write }, | ||
138 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | ||
139 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | ||
140 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
141 | + .fgt = FGT_TLBIRVALE1IS, | ||
142 | .writefn = tlbi_aa64_rvae1is_write }, | ||
143 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | ||
144 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | ||
145 | .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | ||
146 | + .fgt = FGT_TLBIRVAALE1IS, | ||
147 | .writefn = tlbi_aa64_rvae1is_write }, | ||
148 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | ||
149 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | ||
150 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
151 | + .fgt = FGT_TLBIRVAE1OS, | ||
152 | .writefn = tlbi_aa64_rvae1is_write }, | ||
153 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | ||
154 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | ||
155 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
156 | + .fgt = FGT_TLBIRVAAE1OS, | ||
157 | .writefn = tlbi_aa64_rvae1is_write }, | ||
158 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | ||
159 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | ||
160 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
161 | + .fgt = FGT_TLBIRVALE1OS, | ||
162 | .writefn = tlbi_aa64_rvae1is_write }, | ||
163 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | ||
164 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | ||
165 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
166 | + .fgt = FGT_TLBIRVAALE1OS, | ||
167 | .writefn = tlbi_aa64_rvae1is_write }, | ||
168 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | ||
169 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | ||
170 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
171 | + .fgt = FGT_TLBIRVAE1, | ||
172 | .writefn = tlbi_aa64_rvae1_write }, | ||
173 | { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, | ||
174 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, | ||
175 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
176 | + .fgt = FGT_TLBIRVAAE1, | ||
177 | .writefn = tlbi_aa64_rvae1_write }, | ||
178 | { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, | ||
179 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, | ||
180 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
181 | + .fgt = FGT_TLBIRVALE1, | ||
182 | .writefn = tlbi_aa64_rvae1_write }, | ||
183 | { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, | ||
184 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, | ||
185 | .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
186 | + .fgt = FGT_TLBIRVAALE1, | ||
187 | .writefn = tlbi_aa64_rvae1_write }, | ||
188 | { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, | ||
189 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, | ||
190 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = { | ||
191 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | ||
192 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | ||
193 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
194 | + .fgt = FGT_TLBIVMALLE1OS, | ||
195 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
196 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, | ||
197 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | ||
198 | + .fgt = FGT_TLBIVAE1OS, | ||
199 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
200 | .writefn = tlbi_aa64_vae1is_write }, | ||
201 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, | ||
202 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | ||
203 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
204 | + .fgt = FGT_TLBIASIDE1OS, | ||
205 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
206 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, | ||
207 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | ||
208 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
209 | + .fgt = FGT_TLBIVAAE1OS, | ||
210 | .writefn = tlbi_aa64_vae1is_write }, | ||
211 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | ||
212 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | ||
213 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
214 | + .fgt = FGT_TLBIVALE1OS, | ||
215 | .writefn = tlbi_aa64_vae1is_write }, | ||
216 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | ||
217 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | ||
218 | .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
219 | + .fgt = FGT_TLBIVAALE1OS, | ||
220 | .writefn = tlbi_aa64_vae1is_write }, | ||
221 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
222 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
36 | -- | 223 | -- |
37 | 2.34.1 | 224 | 2.34.1 |
38 | |||
39 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | Mark up the sysreg definitions for the system instructions |
---|---|---|---|
2 | trapped by HFGITR bits 48..63. | ||
2 | 3 | ||
3 | IEC binary prefixes ease code review: the unit is explicit. | 4 | Some of these bits are for trapping instructions which are |
5 | not in the system instruction encoding (i.e. which are | ||
6 | not handled by the ARMCPRegInfo mechanism): | ||
7 | * ERET, ERETAA, ERETAB | ||
8 | * SVC | ||
4 | 9 | ||
5 | Add the FLASH_SECTOR_SIZE definition. | 10 | We will have to handle those separately and manually. |
6 | 11 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20230109115316.2235-9-philmd@linaro.org | 14 | Tested-by: Fuad Tabba <tabba@google.com> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org |
16 | Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org | ||
11 | --- | 17 | --- |
12 | hw/arm/musicpal.c | 9 ++++++--- | 18 | target/arm/cpregs.h | 4 ++++ |
13 | 1 file changed, 6 insertions(+), 3 deletions(-) | 19 | target/arm/helper.c | 9 +++++++++ |
20 | 2 files changed, 13 insertions(+) | ||
14 | 21 | ||
15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 22 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
16 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/musicpal.c | 24 | --- a/target/arm/cpregs.h |
18 | +++ b/hw/arm/musicpal.c | 25 | +++ b/target/arm/cpregs.h |
19 | @@ -XXX,XX +XXX,XX @@ | 26 | @@ -XXX,XX +XXX,XX @@ typedef enum FGTBit { |
20 | */ | 27 | DO_BIT(HFGITR, TLBIVAAE1), |
21 | 28 | DO_BIT(HFGITR, TLBIVALE1), | |
22 | #include "qemu/osdep.h" | 29 | DO_BIT(HFGITR, TLBIVAALE1), |
23 | +#include "qemu/units.h" | 30 | + DO_BIT(HFGITR, CFPRCTX), |
24 | #include "qapi/error.h" | 31 | + DO_BIT(HFGITR, DVPRCTX), |
25 | #include "cpu.h" | 32 | + DO_BIT(HFGITR, CPPRCTX), |
26 | #include "hw/sysbus.h" | 33 | + DO_BIT(HFGITR, DCCVAC), |
27 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo musicpal_key_info = { | 34 | } FGTBit; |
28 | .class_init = musicpal_key_class_init, | 35 | |
36 | #undef DO_BIT | ||
37 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/helper.c | ||
40 | +++ b/target/arm/helper.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
42 | { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, | ||
43 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, | ||
44 | .access = PL0_W, .type = ARM_CP_NOP, | ||
45 | + .fgt = FGT_DCCVAC, | ||
46 | .accessfn = aa64_cacheop_poc_access }, | ||
47 | { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, | ||
48 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | ||
49 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { | ||
50 | { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64, | ||
51 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3, | ||
52 | .type = ARM_CP_NOP, .access = PL0_W, | ||
53 | + .fgt = FGT_DCCVAC, | ||
54 | .accessfn = aa64_cacheop_poc_access }, | ||
55 | { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64, | ||
56 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5, | ||
57 | .type = ARM_CP_NOP, .access = PL0_W, | ||
58 | + .fgt = FGT_DCCVAC, | ||
59 | .accessfn = aa64_cacheop_poc_access }, | ||
60 | { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64, | ||
61 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3, | ||
62 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | ||
63 | static const ARMCPRegInfo predinv_reginfo[] = { | ||
64 | { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | ||
65 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | ||
66 | + .fgt = FGT_CFPRCTX, | ||
67 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
68 | { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | ||
69 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | ||
70 | + .fgt = FGT_DVPRCTX, | ||
71 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
72 | { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | ||
73 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | ||
74 | + .fgt = FGT_CPPRCTX, | ||
75 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
76 | /* | ||
77 | * Note the AArch32 opcodes have a different OPC1. | ||
78 | */ | ||
79 | { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | ||
80 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | ||
81 | + .fgt = FGT_CFPRCTX, | ||
82 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
83 | { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | ||
84 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | ||
85 | + .fgt = FGT_DVPRCTX, | ||
86 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
87 | { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | ||
88 | .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | ||
89 | + .fgt = FGT_CPPRCTX, | ||
90 | .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
29 | }; | 91 | }; |
30 | 92 | ||
31 | +#define FLASH_SECTOR_SIZE (64 * KiB) | ||
32 | + | ||
33 | static struct arm_boot_info musicpal_binfo = { | ||
34 | .loader_start = 0x0, | ||
35 | .board_id = 0x20e, | ||
36 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
37 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); | ||
38 | |||
39 | flash_size = blk_getlength(blk); | ||
40 | - if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && | ||
41 | - flash_size != 32*1024*1024) { | ||
42 | + if (flash_size != 8 * MiB && flash_size != 16 * MiB && | ||
43 | + flash_size != 32 * MiB) { | ||
44 | error_report("Invalid flash image size"); | ||
45 | exit(1); | ||
46 | } | ||
47 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
48 | */ | ||
49 | pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, | ||
50 | "musicpal.flash", flash_size, | ||
51 | - blk, 0x10000, | ||
52 | + blk, FLASH_SECTOR_SIZE, | ||
53 | MP_FLASH_SIZE_MAX / flash_size, | ||
54 | 2, 0x00BF, 0x236D, 0x0000, 0x0000, | ||
55 | 0x5555, 0x2AAA, 0); | ||
56 | -- | 93 | -- |
57 | 2.34.1 | 94 | 2.34.1 |
58 | |||
59 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | Implement the HFGITR_EL2.ERET fine-grained trap. This traps |
---|---|---|---|
2 | execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is | ||
3 | reported with a syndrome value of 0x1a. | ||
2 | 4 | ||
3 | This patch enables copying of SPL from MMC if `-kernel` parameter is not | 5 | The trap must take precedence over a possible pointer-authentication |
4 | passed when starting QEMU. SPL is copied to SRAM_A. | 6 | trap for ERETAA and ERETAB. |
5 | 7 | ||
6 | The approach is reused from Allwinner H3 implementation. | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Tested-by: Fuad Tabba <tabba@google.com> | ||
11 | Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org | ||
12 | Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/arm/cpu.h | 1 + | ||
15 | target/arm/syndrome.h | 10 ++++++++++ | ||
16 | target/arm/translate.h | 2 ++ | ||
17 | target/arm/helper.c | 3 +++ | ||
18 | target/arm/translate-a64.c | 10 ++++++++++ | ||
19 | 5 files changed, 26 insertions(+) | ||
7 | 20 | ||
8 | Tested with Armbian and custom Yocto image. | 21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
9 | |||
10 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | ||
11 | |||
12 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
13 | Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/arm/allwinner-a10.h | 21 +++++++++++++++++++++ | ||
17 | hw/arm/allwinner-a10.c | 18 ++++++++++++++++++ | ||
18 | hw/arm/cubieboard.c | 5 +++++ | ||
19 | 3 files changed, 44 insertions(+) | ||
20 | |||
21 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/arm/allwinner-a10.h | 23 | --- a/target/arm/cpu.h |
24 | +++ b/include/hw/arm/allwinner-a10.h | 24 | +++ b/target/arm/cpu.h |
25 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1) |
26 | #include "hw/misc/allwinner-a10-ccm.h" | 26 | FIELD(TBFLAG_A64, SVL, 24, 4) |
27 | #include "hw/misc/allwinner-a10-dramc.h" | 27 | /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */ |
28 | #include "hw/i2c/allwinner-i2c.h" | 28 | FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) |
29 | +#include "sysemu/block-backend.h" | 29 | +FIELD(TBFLAG_A64, FGT_ERET, 29, 1) |
30 | 30 | ||
31 | #include "target/arm/cpu.h" | 31 | /* |
32 | #include "qom/object.h" | 32 | * Helpers for using the above. |
33 | @@ -XXX,XX +XXX,XX @@ struct AwA10State { | 33 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
34 | OHCISysBusState ohci[AW_A10_NUM_USB]; | 34 | index XXXXXXX..XXXXXXX 100644 |
35 | }; | 35 | --- a/target/arm/syndrome.h |
36 | 36 | +++ b/target/arm/syndrome.h | |
37 | +/** | 37 | @@ -XXX,XX +XXX,XX @@ enum arm_exception_class { |
38 | + * Emulate Boot ROM firmware setup functionality. | 38 | EC_AA64_SMC = 0x17, |
39 | + * | 39 | EC_SYSTEMREGISTERTRAP = 0x18, |
40 | + * A real Allwinner A10 SoC contains a Boot ROM | 40 | EC_SVEACCESSTRAP = 0x19, |
41 | + * which is the first code that runs right after | 41 | + EC_ERETTRAP = 0x1a, |
42 | + * the SoC is powered on. The Boot ROM is responsible | 42 | EC_SMETRAP = 0x1d, |
43 | + * for loading user code (e.g. a bootloader) from any | 43 | EC_INSNABORT = 0x20, |
44 | + * of the supported external devices and writing the | 44 | EC_INSNABORT_SAME_EL = 0x21, |
45 | + * downloaded code to internal SRAM. After loading the SoC | 45 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void) |
46 | + * begins executing the code written to SRAM. | 46 | return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT; |
47 | + * | 47 | } |
48 | + * This function emulates the Boot ROM by copying 32 KiB | 48 | |
49 | + * of data at offset 8 KiB from the given block device and writes it to | 49 | +/* |
50 | + * the start of the first internal SRAM memory. | 50 | + * eret_op is bits [1:0] of the ERET instruction, so: |
51 | + * | 51 | + * 0 for ERET, 2 for ERETAA, 3 for ERETAB. |
52 | + * @s: Allwinner A10 state object pointer | ||
53 | + * @blk: Block backend device object pointer | ||
54 | + */ | 52 | + */ |
55 | +void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk); | 53 | +static inline uint32_t syn_erettrap(int eret_op) |
56 | + | ||
57 | #endif | ||
58 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/hw/arm/allwinner-a10.c | ||
61 | +++ b/hw/arm/allwinner-a10.c | ||
62 | @@ -XXX,XX +XXX,XX @@ | ||
63 | #include "sysemu/sysemu.h" | ||
64 | #include "hw/boards.h" | ||
65 | #include "hw/usb/hcd-ohci.h" | ||
66 | +#include "hw/loader.h" | ||
67 | |||
68 | +#define AW_A10_SRAM_A_BASE 0x00000000 | ||
69 | #define AW_A10_DRAMC_BASE 0x01c01000 | ||
70 | #define AW_A10_MMC0_BASE 0x01c0f000 | ||
71 | #define AW_A10_CCM_BASE 0x01c20000 | ||
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | #define AW_A10_RTC_BASE 0x01c20d00 | ||
74 | #define AW_A10_I2C0_BASE 0x01c2ac00 | ||
75 | |||
76 | +void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk) | ||
77 | +{ | 54 | +{ |
78 | + const int64_t rom_size = 32 * KiB; | 55 | + return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op; |
79 | + g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size); | ||
80 | + | ||
81 | + if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) { | ||
82 | + error_setg(&error_fatal, "%s: failed to read BlockBackend data", | ||
83 | + __func__); | ||
84 | + return; | ||
85 | + } | ||
86 | + | ||
87 | + rom_add_blob("allwinner-a10.bootrom", buffer, rom_size, | ||
88 | + rom_size, AW_A10_SRAM_A_BASE, | ||
89 | + NULL, NULL, NULL, NULL, false); | ||
90 | +} | 56 | +} |
91 | + | 57 | + |
92 | static void aw_a10_init(Object *obj) | 58 | static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) |
93 | { | 59 | { |
94 | AwA10State *s = AW_A10(obj); | 60 | return (EC_SMETRAP << ARM_EL_EC_SHIFT) |
95 | diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c | 61 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
96 | index XXXXXXX..XXXXXXX 100644 | 62 | index XXXXXXX..XXXXXXX 100644 |
97 | --- a/hw/arm/cubieboard.c | 63 | --- a/target/arm/translate.h |
98 | +++ b/hw/arm/cubieboard.c | 64 | +++ b/target/arm/translate.h |
99 | @@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine) | 65 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
100 | memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, | 66 | bool mve_no_pred; |
101 | machine->ram); | 67 | /* True if fine-grained traps are active */ |
102 | 68 | bool fgt_active; | |
103 | + /* Load target kernel or start using BootROM */ | 69 | + /* True if fine-grained trap on ERET is enabled */ |
104 | + if (!machine->kernel_filename && blk && blk_is_available(blk)) { | 70 | + bool fgt_eret; |
105 | + /* Use Boot ROM to copy data from SD card to SRAM */ | 71 | /* |
106 | + allwinner_a10_bootrom_setup(a10, blk); | 72 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. |
107 | + } | 73 | * < 0, set by the current instruction. |
108 | /* TODO create and connect IDE devices for ide_drive_get() */ | 74 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
109 | 75 | index XXXXXXX..XXXXXXX 100644 | |
110 | cubieboard_binfo.ram_size = machine->ram_size; | 76 | --- a/target/arm/helper.c |
77 | +++ b/target/arm/helper.c | ||
78 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
79 | |||
80 | if (arm_fgt_active(env, el)) { | ||
81 | DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); | ||
82 | + if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { | ||
83 | + DP_TBFLAG_A64(flags, FGT_ERET, 1); | ||
84 | + } | ||
85 | } | ||
86 | |||
87 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { | ||
88 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/arm/translate-a64.c | ||
91 | +++ b/target/arm/translate-a64.c | ||
92 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
93 | if (op4 != 0) { | ||
94 | goto do_unallocated; | ||
95 | } | ||
96 | + if (s->fgt_eret) { | ||
97 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); | ||
98 | + return; | ||
99 | + } | ||
100 | dst = tcg_temp_new_i64(); | ||
101 | tcg_gen_ld_i64(dst, cpu_env, | ||
102 | offsetof(CPUARMState, elr_el[s->current_el])); | ||
103 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
104 | if (rn != 0x1f || op4 != 0x1f) { | ||
105 | goto do_unallocated; | ||
106 | } | ||
107 | + /* The FGT trap takes precedence over an auth trap. */ | ||
108 | + if (s->fgt_eret) { | ||
109 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2); | ||
110 | + return; | ||
111 | + } | ||
112 | dst = tcg_temp_new_i64(); | ||
113 | tcg_gen_ld_i64(dst, cpu_env, | ||
114 | offsetof(CPUARMState, elr_el[s->current_el])); | ||
115 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
116 | dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); | ||
117 | dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); | ||
118 | dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); | ||
119 | + dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET); | ||
120 | dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); | ||
121 | dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); | ||
122 | dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16; | ||
111 | -- | 123 | -- |
112 | 2.34.1 | 124 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps. |
---|---|---|---|
2 | These trap execution of the SVC instruction from AArch32 and AArch64. | ||
3 | (As usual, AArch32 can only trap from EL0, as fine grained traps are | ||
4 | disabled with an AArch32 EL1.) | ||
2 | 5 | ||
3 | Add a comment describing the Connex uses a Numonyx RC28F128J3F75 | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | flash, and the Verdex uses a Micron RC28F256P30TFA. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Tested-by: Fuad Tabba <tabba@google.com> | ||
9 | Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org | ||
10 | Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/cpu.h | 1 + | ||
13 | target/arm/translate.h | 2 ++ | ||
14 | target/arm/helper.c | 20 ++++++++++++++++++++ | ||
15 | target/arm/translate-a64.c | 9 ++++++++- | ||
16 | target/arm/translate.c | 12 +++++++++--- | ||
17 | 5 files changed, 40 insertions(+), 4 deletions(-) | ||
5 | 18 | ||
6 | Correct the Verdex machine description (we model the 'Pro' board). | 19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
7 | |||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20230109115316.2235-6-philmd@linaro.org | ||
11 | Message-Id: <20200223231044.8003-3-philmd@redhat.com> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/gumstix.c | 6 ++++-- | ||
15 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/gumstix.c | 21 | --- a/target/arm/cpu.h |
20 | +++ b/hw/arm/gumstix.c | 22 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) |
22 | * Contributions after 2012-01-13 are licensed under the terms of the | 24 | FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) |
23 | * GNU GPL, version 2 or (at your option) any later version. | 25 | FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) |
24 | */ | 26 | FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1) |
25 | - | 27 | +FIELD(TBFLAG_ANY, FGT_SVC, 13, 1) |
28 | |||
29 | /* | ||
30 | * Bit usage when in AArch32 state, both A- and M-profile. | ||
31 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate.h | ||
34 | +++ b/target/arm/translate.h | ||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
36 | bool fgt_active; | ||
37 | /* True if fine-grained trap on ERET is enabled */ | ||
38 | bool fgt_eret; | ||
39 | + /* True if fine-grained trap on SVC is enabled */ | ||
40 | + bool fgt_svc; | ||
41 | /* | ||
42 | * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. | ||
43 | * < 0, set by the current instruction. | ||
44 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/helper.c | ||
47 | +++ b/target/arm/helper.c | ||
48 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) | ||
49 | return arm_mmu_idx_el(env, arm_current_el(env)); | ||
50 | } | ||
51 | |||
52 | +static inline bool fgt_svc(CPUARMState *env, int el) | ||
53 | +{ | ||
54 | + /* | ||
55 | + * Assuming fine-grained-traps are active, return true if we | ||
56 | + * should be trapping on SVC instructions. Only AArch64 can | ||
57 | + * trap on an SVC at EL1, but we don't need to special-case this | ||
58 | + * because if this is AArch32 EL1 then arm_fgt_active() is false. | ||
59 | + * We also know el is 0 or 1. | ||
60 | + */ | ||
61 | + return el == 0 ? | ||
62 | + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : | ||
63 | + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); | ||
64 | +} | ||
26 | + | 65 | + |
27 | /* | 66 | static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, |
28 | * Example usage: | 67 | ARMMMUIdx mmu_idx, |
29 | * | 68 | CPUARMTBFlags flags) |
30 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | 69 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, |
31 | exit(1); | 70 | |
71 | if (arm_fgt_active(env, el)) { | ||
72 | DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); | ||
73 | + if (fgt_svc(env, el)) { | ||
74 | + DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
75 | + } | ||
32 | } | 76 | } |
33 | 77 | ||
34 | + /* Numonyx RC28F128J3F75 */ | 78 | if (env->uncached_cpsr & CPSR_IL) { |
35 | if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, | 79 | @@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, |
36 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 80 | if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { |
37 | sector_len, 2, 0, 0, 0, 0, 0)) { | 81 | DP_TBFLAG_A64(flags, FGT_ERET, 1); |
38 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | 82 | } |
39 | exit(1); | 83 | + if (fgt_svc(env, el)) { |
84 | + DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
85 | + } | ||
40 | } | 86 | } |
41 | 87 | ||
42 | + /* Micron RC28F256P30TFA */ | 88 | if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { |
43 | if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, | 89 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
44 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | 90 | index XXXXXXX..XXXXXXX 100644 |
45 | sector_len, 2, 0, 0, 0, 0, 0)) { | 91 | --- a/target/arm/translate-a64.c |
46 | @@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data) | 92 | +++ b/target/arm/translate-a64.c |
47 | { | 93 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) |
48 | MachineClass *mc = MACHINE_CLASS(oc); | 94 | int opc = extract32(insn, 21, 3); |
49 | 95 | int op2_ll = extract32(insn, 0, 5); | |
50 | - mc->desc = "Gumstix Verdex (PXA270)"; | 96 | int imm16 = extract32(insn, 5, 16); |
51 | + mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)"; | 97 | + uint32_t syndrome; |
52 | mc->init = verdex_init; | 98 | |
53 | mc->ignore_memory_transaction_failures = true; | 99 | switch (opc) { |
54 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); | 100 | case 0: |
101 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
102 | */ | ||
103 | switch (op2_ll) { | ||
104 | case 1: /* SVC */ | ||
105 | + syndrome = syn_aa64_svc(imm16); | ||
106 | + if (s->fgt_svc) { | ||
107 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); | ||
108 | + break; | ||
109 | + } | ||
110 | gen_ss_advance(s); | ||
111 | - gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16)); | ||
112 | + gen_exception_insn(s, 4, EXCP_SWI, syndrome); | ||
113 | break; | ||
114 | case 2: /* HVC */ | ||
115 | if (s->current_el == 0) { | ||
116 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
117 | dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); | ||
118 | dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); | ||
119 | dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); | ||
120 | + dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC); | ||
121 | dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET); | ||
122 | dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL); | ||
123 | dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL); | ||
124 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/target/arm/translate.c | ||
127 | +++ b/target/arm/translate.c | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) | ||
129 | (a->imm == semihost_imm)) { | ||
130 | gen_exception_internal_insn(s, EXCP_SEMIHOST); | ||
131 | } else { | ||
132 | - gen_update_pc(s, curr_insn_len(s)); | ||
133 | - s->svc_imm = a->imm; | ||
134 | - s->base.is_jmp = DISAS_SWI; | ||
135 | + if (s->fgt_svc) { | ||
136 | + uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb); | ||
137 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); | ||
138 | + } else { | ||
139 | + gen_update_pc(s, curr_insn_len(s)); | ||
140 | + s->svc_imm = a->imm; | ||
141 | + s->base.is_jmp = DISAS_SWI; | ||
142 | + } | ||
143 | } | ||
144 | return true; | ||
145 | } | ||
146 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
147 | dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); | ||
148 | dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL); | ||
149 | dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE); | ||
150 | + dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC); | ||
151 | |||
152 | if (arm_feature(env, ARM_FEATURE_M)) { | ||
153 | dc->vfp_enabled = 1; | ||
55 | -- | 154 | -- |
56 | 2.34.1 | 155 | 2.34.1 |
57 | |||
58 | diff view generated by jsdifflib |
1 | From: Felipe Balbi <balbi@kernel.org> | 1 | FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and |
---|---|---|---|
2 | MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug | ||
3 | Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0, | ||
4 | MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their | ||
5 | AArch32 equivalents). This trapping is independent of whether | ||
6 | fine-grained traps are enabled or not. | ||
2 | 7 | ||
3 | Olimex makes a series of low-cost STM32 boards. This commit introduces | 8 | Implement these extra traps. (We don't implement DBGDTR_EL0, |
4 | the minimum setup to support SMT32-H405. See [1] for details | 9 | DBGDTRRX_EL0 and DBGDTRTX_EL0.) |
5 | 10 | ||
6 | [1] https://www.olimex.com/Products/ARM/ST/STM32-H405/ | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Tested-by: Fuad Tabba <tabba@google.com> | ||
14 | Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org | ||
15 | Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org | ||
16 | --- | ||
17 | target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++---- | ||
18 | 1 file changed, 31 insertions(+), 4 deletions(-) | ||
7 | 19 | ||
8 | Signed-off-by: Felipe Balbi <balbi@kernel.org> | 20 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | Message-id: 20221230145733.200496-3-balbi@kernel.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | docs/system/arm/stm32.rst | 1 + | ||
15 | configs/devices/arm-softmmu/default.mak | 1 + | ||
16 | hw/arm/olimex-stm32-h405.c | 69 +++++++++++++++++++++++++ | ||
17 | MAINTAINERS | 6 +++ | ||
18 | hw/arm/Kconfig | 4 ++ | ||
19 | hw/arm/meson.build | 1 + | ||
20 | 6 files changed, 82 insertions(+) | ||
21 | create mode 100644 hw/arm/olimex-stm32-h405.c | ||
22 | |||
23 | diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst | ||
24 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/docs/system/arm/stm32.rst | 22 | --- a/target/arm/debug_helper.c |
26 | +++ b/docs/system/arm/stm32.rst | 23 | +++ b/target/arm/debug_helper.c |
27 | @@ -XXX,XX +XXX,XX @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin | 24 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, |
28 | compatible with STM32F2 series. The following machines are based on this chip : | 25 | return CP_ACCESS_OK; |
29 | 26 | } | |
30 | - ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller | 27 | |
31 | +- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller | ||
32 | |||
33 | There are many other STM32 series that are currently not supported by QEMU. | ||
34 | |||
35 | diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/configs/devices/arm-softmmu/default.mak | ||
38 | +++ b/configs/devices/arm-softmmu/default.mak | ||
39 | @@ -XXX,XX +XXX,XX @@ CONFIG_COLLIE=y | ||
40 | CONFIG_ASPEED_SOC=y | ||
41 | CONFIG_NETDUINO2=y | ||
42 | CONFIG_NETDUINOPLUS2=y | ||
43 | +CONFIG_OLIMEX_STM32_H405=y | ||
44 | CONFIG_MPS2=y | ||
45 | CONFIG_RASPI=y | ||
46 | CONFIG_DIGIC=y | ||
47 | diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c | ||
48 | new file mode 100644 | ||
49 | index XXXXXXX..XXXXXXX | ||
50 | --- /dev/null | ||
51 | +++ b/hw/arm/olimex-stm32-h405.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | +/* | 28 | +/* |
54 | + * ST STM32VLDISCOVERY machine | 29 | + * Check for traps to Debug Comms Channel registers. If FEAT_FGT |
55 | + * Olimex STM32-H405 machine | 30 | + * is implemented then these are controlled by MDCR_EL2.TDCC for |
56 | + * | 31 | + * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by |
57 | + * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org> | 32 | + * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA. |
58 | + * | ||
59 | + * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
60 | + * of this software and associated documentation files (the "Software"), to deal | ||
61 | + * in the Software without restriction, including without limitation the rights | ||
62 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
63 | + * copies of the Software, and to permit persons to whom the Software is | ||
64 | + * furnished to do so, subject to the following conditions: | ||
65 | + * | ||
66 | + * The above copyright notice and this permission notice shall be included in | ||
67 | + * all copies or substantial portions of the Software. | ||
68 | + * | ||
69 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
70 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
71 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
72 | + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
73 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
74 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
75 | + * THE SOFTWARE. | ||
76 | + */ | 33 | + */ |
34 | +static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, | ||
35 | + bool isread) | ||
36 | +{ | ||
37 | + int el = arm_current_el(env); | ||
38 | + uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); | ||
39 | + bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || | ||
40 | + (arm_hcr_el2_eff(env) & HCR_TGE); | ||
41 | + bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) && | ||
42 | + (mdcr_el2 & MDCR_TDCC); | ||
43 | + bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) && | ||
44 | + (env->cp15.mdcr_el3 & MDCR_TDCC); | ||
77 | + | 45 | + |
78 | +#include "qemu/osdep.h" | 46 | + if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { |
79 | +#include "qapi/error.h" | 47 | + return CP_ACCESS_TRAP_EL2; |
80 | +#include "hw/boards.h" | 48 | + } |
81 | +#include "hw/qdev-properties.h" | 49 | + if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { |
82 | +#include "hw/qdev-clock.h" | 50 | + return CP_ACCESS_TRAP_EL3; |
83 | +#include "qemu/error-report.h" | 51 | + } |
84 | +#include "hw/arm/stm32f405_soc.h" | 52 | + return CP_ACCESS_OK; |
85 | +#include "hw/arm/boot.h" | ||
86 | + | ||
87 | +/* olimex-stm32-h405 implementation is derived from netduinoplus2 */ | ||
88 | + | ||
89 | +/* Main SYSCLK frequency in Hz (168MHz) */ | ||
90 | +#define SYSCLK_FRQ 168000000ULL | ||
91 | + | ||
92 | +static void olimex_stm32_h405_init(MachineState *machine) | ||
93 | +{ | ||
94 | + DeviceState *dev; | ||
95 | + Clock *sysclk; | ||
96 | + | ||
97 | + /* This clock doesn't need migration because it is fixed-frequency */ | ||
98 | + sysclk = clock_new(OBJECT(machine), "SYSCLK"); | ||
99 | + clock_set_hz(sysclk, SYSCLK_FRQ); | ||
100 | + | ||
101 | + dev = qdev_new(TYPE_STM32F405_SOC); | ||
102 | + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4")); | ||
103 | + qdev_connect_clock_in(dev, "sysclk", sysclk); | ||
104 | + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
105 | + | ||
106 | + armv7m_load_kernel(ARM_CPU(first_cpu), | ||
107 | + machine->kernel_filename, | ||
108 | + 0, FLASH_SIZE); | ||
109 | +} | 53 | +} |
110 | + | 54 | + |
111 | +static void olimex_stm32_h405_machine_init(MachineClass *mc) | 55 | static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, |
112 | +{ | 56 | uint64_t value) |
113 | + mc->desc = "Olimex STM32-H405 (Cortex-M4)"; | 57 | { |
114 | + mc->init = olimex_stm32_h405_init; | 58 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
115 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); | 59 | */ |
116 | + | 60 | { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64, |
117 | + /* SRAM pre-allocated as part of the SoC instantiation */ | 61 | .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0, |
118 | + mc->default_ram_size = 0; | 62 | - .access = PL0_R, .accessfn = access_tda, |
119 | +} | 63 | + .access = PL0_R, .accessfn = access_tdcc, |
120 | + | 64 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
121 | +DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init) | 65 | /* |
122 | diff --git a/MAINTAINERS b/MAINTAINERS | 66 | * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0. |
123 | index XXXXXXX..XXXXXXX 100644 | 67 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
124 | --- a/MAINTAINERS | 68 | */ |
125 | +++ b/MAINTAINERS | 69 | { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, |
126 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | 70 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2, |
127 | S: Maintained | 71 | - .access = PL1_RW, .accessfn = access_tda, |
128 | F: hw/arm/netduinoplus2.c | 72 | + .access = PL1_RW, .accessfn = access_tdcc, |
129 | 73 | .type = ARM_CP_CONST, .resetvalue = 0 }, | |
130 | +Olimex STM32 H405 | 74 | { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, |
131 | +M: Felipe Balbi <balbi@kernel.org> | 75 | .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, |
132 | +L: qemu-arm@nongnu.org | 76 | - .access = PL1_RW, .accessfn = access_tda, |
133 | +S: Maintained | 77 | + .access = PL1_RW, .accessfn = access_tdcc, |
134 | +F: hw/arm/olimex-stm32-h405.c | 78 | .type = ARM_CP_CONST, .resetvalue = 0 }, |
135 | + | 79 | /* |
136 | SmartFusion2 | 80 | * OSECCR_EL1 provides a mechanism for an operating system |
137 | M: Subbaraya Sundeep <sundeep.lkml@gmail.com> | 81 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = { |
138 | M: Peter Maydell <peter.maydell@linaro.org> | 82 | */ |
139 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 83 | { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, |
140 | index XXXXXXX..XXXXXXX 100644 | 84 | .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, |
141 | --- a/hw/arm/Kconfig | 85 | - .access = PL1_RW, .accessfn = access_tda, |
142 | +++ b/hw/arm/Kconfig | 86 | + .access = PL1_RW, .accessfn = access_tdcc, |
143 | @@ -XXX,XX +XXX,XX @@ config NETDUINOPLUS2 | 87 | .type = ARM_CP_NOP }, |
144 | bool | 88 | /* |
145 | select STM32F405_SOC | 89 | * Dummy DBGCLAIM registers. |
146 | |||
147 | +config OLIMEX_STM32_H405 | ||
148 | + bool | ||
149 | + select STM32F405_SOC | ||
150 | + | ||
151 | config NSERIES | ||
152 | bool | ||
153 | select OMAP | ||
154 | diff --git a/hw/arm/meson.build b/hw/arm/meson.build | ||
155 | index XXXXXXX..XXXXXXX 100644 | ||
156 | --- a/hw/arm/meson.build | ||
157 | +++ b/hw/arm/meson.build | ||
158 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) | ||
159 | arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) | ||
160 | arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) | ||
161 | arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) | ||
162 | +arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c')) | ||
163 | arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) | ||
164 | arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) | ||
165 | arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) | ||
166 | -- | 90 | -- |
167 | 2.34.1 | 91 | 2.34.1 |
168 | |||
169 | diff view generated by jsdifflib |
1 | From: Strahinja Jankovic <strahinjapjankovic@gmail.com> | 1 | Update the ID registers for TCG's '-cpu max' to report the |
---|---|---|---|
2 | presence of FEAT_FGT Fine-Grained Traps support. | ||
2 | 3 | ||
3 | Cubieboard now can boot directly from SD card, without the need to pass | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | `-kernel` parameter. Update Avocado tests to cover this functionality. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Tested-by: Fuad Tabba <tabba@google.com> | ||
7 | Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org | ||
8 | Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org | ||
9 | --- | ||
10 | docs/system/arm/emulation.rst | 1 + | ||
11 | target/arm/cpu64.c | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
5 | 13 | ||
6 | Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> | 14 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
7 | Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
8 | Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> | ||
9 | Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | tests/avocado/boot_linux_console.py | 47 +++++++++++++++++++++++++++++ | ||
13 | 1 file changed, 47 insertions(+) | ||
14 | |||
15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py | ||
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/tests/avocado/boot_linux_console.py | 16 | --- a/docs/system/arm/emulation.rst |
18 | +++ b/tests/avocado/boot_linux_console.py | 17 | +++ b/docs/system/arm/emulation.rst |
19 | @@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self): | 18 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
20 | 'sda') | 19 | - FEAT_ETS (Enhanced Translation Synchronization) |
21 | # cubieboard's reboot is not functioning; omit reboot test. | 20 | - FEAT_EVT (Enhanced Virtualization Traps) |
22 | 21 | - FEAT_FCMA (Floating-point complex number instructions) | |
23 | + @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') | 22 | +- FEAT_FGT (Fine-Grained Traps) |
24 | + def test_arm_cubieboard_openwrt_22_03_2(self): | 23 | - FEAT_FHM (Floating-point half-precision multiplication instructions) |
25 | + """ | 24 | - FEAT_FP16 (Half-precision floating-point data processing) |
26 | + :avocado: tags=arch:arm | 25 | - FEAT_FRINTTS (Floating-point to integer instructions) |
27 | + :avocado: tags=machine:cubieboard | 26 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
28 | + :avocado: tags=device:sd | 27 | index XXXXXXX..XXXXXXX 100644 |
29 | + """ | 28 | --- a/target/arm/cpu64.c |
30 | + | 29 | +++ b/target/arm/cpu64.c |
31 | + # This test download a 7.5 MiB compressed image and expand it | 30 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
32 | + # to 126 MiB. | 31 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */ |
33 | + image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/' | 32 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */ |
34 | + 'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-' | 33 | t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */ |
35 | + 'cubietech_a10-cubieboard-ext4-sdcard.img.gz') | 34 | + t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */ |
36 | + image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa' | 35 | cpu->isar.id_aa64mmfr0 = t; |
37 | + '2ac5dc2d08733d6705af9f144f39f554') | 36 | |
38 | + image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash, | 37 | t = cpu->isar.id_aa64mmfr1; |
39 | + algorithm='sha256') | ||
40 | + image_path = archive.extract(image_path_gz, self.workdir) | ||
41 | + image_pow2ceil_expand(image_path) | ||
42 | + | ||
43 | + self.vm.set_console() | ||
44 | + self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw', | ||
45 | + '-nic', 'user', | ||
46 | + '-no-reboot') | ||
47 | + self.vm.launch() | ||
48 | + | ||
49 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | ||
50 | + 'usbcore.nousb ' | ||
51 | + 'noreboot') | ||
52 | + | ||
53 | + self.wait_for_console_pattern('U-Boot SPL') | ||
54 | + | ||
55 | + interrupt_interactive_console_until_pattern( | ||
56 | + self, 'Hit any key to stop autoboot:', '=>') | ||
57 | + exec_command_and_wait_for_pattern(self, "setenv extraargs '" + | ||
58 | + kernel_command_line + "'", '=>') | ||
59 | + exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...'); | ||
60 | + | ||
61 | + self.wait_for_console_pattern( | ||
62 | + 'Please press Enter to activate this console.') | ||
63 | + | ||
64 | + exec_command_and_wait_for_pattern(self, ' ', 'root@') | ||
65 | + | ||
66 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', | ||
67 | + 'Allwinner sun4i/sun5i') | ||
68 | + # cubieboard's reboot is not functioning; omit reboot test. | ||
69 | + | ||
70 | @skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout') | ||
71 | def test_arm_quanta_gsj(self): | ||
72 | """ | ||
73 | -- | 38 | -- |
74 | 2.34.1 | 39 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Since pxa255_init() must map the device in the system memory, | ||
4 | there is no point in passing get_system_memory() by argument. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230109115316.2235-2-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/arm/pxa.h | 2 +- | ||
12 | hw/arm/gumstix.c | 3 +-- | ||
13 | hw/arm/pxa2xx.c | 4 +++- | ||
14 | hw/arm/tosa.c | 2 +- | ||
15 | 4 files changed, 6 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/pxa.h | ||
20 | +++ b/include/hw/arm/pxa.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState { | ||
22 | |||
23 | PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, | ||
24 | const char *revision); | ||
25 | -PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size); | ||
26 | +PXA2xxState *pxa255_init(unsigned int sdram_size); | ||
27 | |||
28 | #endif /* PXA_H */ | ||
29 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/gumstix.c | ||
32 | +++ b/hw/arm/gumstix.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine) | ||
34 | { | ||
35 | PXA2xxState *cpu; | ||
36 | DriveInfo *dinfo; | ||
37 | - MemoryRegion *address_space_mem = get_system_memory(); | ||
38 | |||
39 | uint32_t connex_rom = 0x01000000; | ||
40 | uint32_t connex_ram = 0x04000000; | ||
41 | |||
42 | - cpu = pxa255_init(address_space_mem, connex_ram); | ||
43 | + cpu = pxa255_init(connex_ram); | ||
44 | |||
45 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
46 | if (!dinfo && !qtest_enabled()) { | ||
47 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/arm/pxa2xx.c | ||
50 | +++ b/hw/arm/pxa2xx.c | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | #include "qemu/error-report.h" | ||
53 | #include "qemu/module.h" | ||
54 | #include "qapi/error.h" | ||
55 | +#include "exec/address-spaces.h" | ||
56 | #include "cpu.h" | ||
57 | #include "hw/sysbus.h" | ||
58 | #include "migration/vmstate.h" | ||
59 | @@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, | ||
60 | } | ||
61 | |||
62 | /* Initialise a PXA255 integrated chip (ARM based core). */ | ||
63 | -PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) | ||
64 | +PXA2xxState *pxa255_init(unsigned int sdram_size) | ||
65 | { | ||
66 | + MemoryRegion *address_space = get_system_memory(); | ||
67 | PXA2xxState *s; | ||
68 | int i; | ||
69 | DriveInfo *dinfo; | ||
70 | diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/hw/arm/tosa.c | ||
73 | +++ b/hw/arm/tosa.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static void tosa_init(MachineState *machine) | ||
75 | TC6393xbState *tmio; | ||
76 | DeviceState *scp0, *scp1; | ||
77 | |||
78 | - mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size); | ||
79 | + mpu = pxa255_init(tosa_binfo.ram_size); | ||
80 | |||
81 | memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal); | ||
82 | memory_region_add_subregion(address_space_mem, 0, rom); | ||
83 | -- | ||
84 | 2.34.1 | ||
85 | |||
86 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Since pxa270_init() must map the device in the system memory, | ||
4 | there is no point in passing get_system_memory() by argument. | ||
5 | |||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230109115316.2235-3-philmd@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/arm/pxa.h | 3 +-- | ||
12 | hw/arm/gumstix.c | 3 +-- | ||
13 | hw/arm/mainstone.c | 10 ++++------ | ||
14 | hw/arm/pxa2xx.c | 4 ++-- | ||
15 | hw/arm/spitz.c | 6 ++---- | ||
16 | hw/arm/z2.c | 3 +-- | ||
17 | 6 files changed, 11 insertions(+), 18 deletions(-) | ||
18 | |||
19 | diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/hw/arm/pxa.h | ||
22 | +++ b/include/hw/arm/pxa.h | ||
23 | @@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState { | ||
24 | |||
25 | # define PA_FMT "0x%08lx" | ||
26 | |||
27 | -PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, | ||
28 | - const char *revision); | ||
29 | +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); | ||
30 | PXA2xxState *pxa255_init(unsigned int sdram_size); | ||
31 | |||
32 | #endif /* PXA_H */ | ||
33 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/gumstix.c | ||
36 | +++ b/hw/arm/gumstix.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine) | ||
38 | { | ||
39 | PXA2xxState *cpu; | ||
40 | DriveInfo *dinfo; | ||
41 | - MemoryRegion *address_space_mem = get_system_memory(); | ||
42 | |||
43 | uint32_t verdex_rom = 0x02000000; | ||
44 | uint32_t verdex_ram = 0x10000000; | ||
45 | |||
46 | - cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type); | ||
47 | + cpu = pxa270_init(verdex_ram, machine->cpu_type); | ||
48 | |||
49 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
50 | if (!dinfo && !qtest_enabled()) { | ||
51 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/hw/arm/mainstone.c | ||
54 | +++ b/hw/arm/mainstone.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info mainstone_binfo = { | ||
56 | .ram_size = 0x04000000, | ||
57 | }; | ||
58 | |||
59 | -static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
60 | - MachineState *machine, | ||
61 | +static void mainstone_common_init(MachineState *machine, | ||
62 | enum mainstone_model_e model, int arm_id) | ||
63 | { | ||
64 | uint32_t sector_len = 256 * 1024; | ||
65 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
66 | MemoryRegion *rom = g_new(MemoryRegion, 1); | ||
67 | |||
68 | /* Setup CPU & memory */ | ||
69 | - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, | ||
70 | - machine->cpu_type); | ||
71 | + mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type); | ||
72 | memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM, | ||
73 | &error_fatal); | ||
74 | - memory_region_add_subregion(address_space_mem, 0, rom); | ||
75 | + memory_region_add_subregion(get_system_memory(), 0x00000000, rom); | ||
76 | |||
77 | /* There are two 32MiB flash devices on the board */ | ||
78 | for (i = 0; i < 2; i ++) { | ||
79 | @@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem, | ||
80 | |||
81 | static void mainstone_init(MachineState *machine) | ||
82 | { | ||
83 | - mainstone_common_init(get_system_memory(), machine, mainstone, 0x196); | ||
84 | + mainstone_common_init(machine, mainstone, 0x196); | ||
85 | } | ||
86 | |||
87 | static void mainstone2_machine_init(MachineClass *mc) | ||
88 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/hw/arm/pxa2xx.c | ||
91 | +++ b/hw/arm/pxa2xx.c | ||
92 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_reset(void *opaque, int line, int level) | ||
93 | } | ||
94 | |||
95 | /* Initialise a PXA270 integrated chip (ARM based core). */ | ||
96 | -PXA2xxState *pxa270_init(MemoryRegion *address_space, | ||
97 | - unsigned int sdram_size, const char *cpu_type) | ||
98 | +PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type) | ||
99 | { | ||
100 | + MemoryRegion *address_space = get_system_memory(); | ||
101 | PXA2xxState *s; | ||
102 | int i; | ||
103 | DriveInfo *dinfo; | ||
104 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/hw/arm/spitz.c | ||
107 | +++ b/hw/arm/spitz.c | ||
108 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine) | ||
109 | SpitzMachineState *sms = SPITZ_MACHINE(machine); | ||
110 | enum spitz_model_e model = smc->model; | ||
111 | PXA2xxState *mpu; | ||
112 | - MemoryRegion *address_space_mem = get_system_memory(); | ||
113 | MemoryRegion *rom = g_new(MemoryRegion, 1); | ||
114 | |||
115 | /* Setup CPU & memory */ | ||
116 | - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, | ||
117 | - machine->cpu_type); | ||
118 | + mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type); | ||
119 | sms->mpu = mpu; | ||
120 | |||
121 | sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | ||
122 | |||
123 | memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal); | ||
124 | - memory_region_add_subregion(address_space_mem, 0, rom); | ||
125 | + memory_region_add_subregion(get_system_memory(), 0, rom); | ||
126 | |||
127 | /* Setup peripherals */ | ||
128 | spitz_keyboard_register(mpu); | ||
129 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
130 | index XXXXXXX..XXXXXXX 100644 | ||
131 | --- a/hw/arm/z2.c | ||
132 | +++ b/hw/arm/z2.c | ||
133 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = { | ||
134 | |||
135 | static void z2_init(MachineState *machine) | ||
136 | { | ||
137 | - MemoryRegion *address_space_mem = get_system_memory(); | ||
138 | uint32_t sector_len = 0x10000; | ||
139 | PXA2xxState *mpu; | ||
140 | DriveInfo *dinfo; | ||
141 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) | ||
142 | DeviceState *wm; | ||
143 | |||
144 | /* Setup CPU & memory */ | ||
145 | - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); | ||
146 | + mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type); | ||
147 | |||
148 | dinfo = drive_get(IF_PFLASH, 0, 0); | ||
149 | if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, | ||
150 | -- | ||
151 | 2.34.1 | ||
152 | |||
153 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20230109115316.2235-5-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | --- | ||
8 | hw/arm/collie.c | 17 +++++++---------- | ||
9 | 1 file changed, 7 insertions(+), 10 deletions(-) | ||
10 | |||
11 | diff --git a/hw/arm/collie.c b/hw/arm/collie.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/arm/collie.c | ||
14 | +++ b/hw/arm/collie.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = { | ||
16 | |||
17 | static void collie_init(MachineState *machine) | ||
18 | { | ||
19 | - DriveInfo *dinfo; | ||
20 | MachineClass *mc = MACHINE_GET_CLASS(machine); | ||
21 | CollieMachineState *cms = COLLIE_MACHINE(machine); | ||
22 | |||
23 | @@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine) | ||
24 | |||
25 | memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); | ||
26 | |||
27 | - dinfo = drive_get(IF_PFLASH, 0, 0); | ||
28 | - pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE, | ||
29 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
30 | - FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0); | ||
31 | - | ||
32 | - dinfo = drive_get(IF_PFLASH, 0, 1); | ||
33 | - pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE, | ||
34 | - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
35 | - FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0); | ||
36 | + for (unsigned i = 0; i < 2; i++) { | ||
37 | + DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i); | ||
38 | + pflash_cfi01_register(i ? SA_CS1 : SA_CS0, | ||
39 | + i ? "collie.fl2" : "collie.fl1", FLASH_SIZE, | ||
40 | + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, | ||
41 | + FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0); | ||
42 | + } | ||
43 | |||
44 | sysbus_create_simple("scoop", 0x40800000, NULL); | ||
45 | |||
46 | -- | ||
47 | 2.34.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
2 | 1 | ||
3 | The total_ram_v1/total_ram_v2 definitions were never used. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20230109115316.2235-10-philmd@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/arm/omap_sx1.c | 2 -- | ||
11 | 1 file changed, 2 deletions(-) | ||
12 | |||
13 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/arm/omap_sx1.c | ||
16 | +++ b/hw/arm/omap_sx1.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = { | ||
18 | #define flash0_size (16 * 1024 * 1024) | ||
19 | #define flash1_size ( 8 * 1024 * 1024) | ||
20 | #define flash2_size (32 * 1024 * 1024) | ||
21 | -#define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE) | ||
22 | -#define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE) | ||
23 | |||
24 | static struct arm_boot_info sx1_binfo = { | ||
25 | .loader_start = OMAP_EMIFF_BASE, | ||
26 | -- | ||
27 | 2.34.1 | ||
28 | |||
29 | diff view generated by jsdifflib |