1
The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
1
The following changes since commit 38d0939b86e2eef6f6a622c6f1f7befda0146595:
2
2
3
Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2023-01-05 16:59:22 +0000)
3
Merge tag 'pull-vfio-20241226' of https://github.com/legoater/qemu into staging (2024-12-26 04:38:38 -0500)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://gitlab.com/gaosong/qemu.git pull-loongarch-20230106
7
https://gitlab.com/bibo-mao/qemu.git tags/pull-loongarch-20241227
8
8
9
for you to fetch changes up to f4d10ce8aa545266a0b6df223a7f8ea2afca18b2:
9
for you to fetch changes up to 5e360dabedb1ab1f15cce27a134ccbe4b8e18424:
10
10
11
hw/intc/loongarch_pch: Change default irq number of pch irq controller (2023-01-06 14:12:43 +0800)
11
target/loongarch: Use auto method with LASX feature (2024-12-27 11:33:06 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
14
pull-loongarch-20241227
15
Add irq number property for loongarch pch interrupt controller
15
v1 ... v2
16
1. Modify patch auther inconsistent with SOB
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
Tianrui Zhao (3):
19
Bibo Mao (5):
19
hw/intc/loongarch_pch_msi: add irq number property
20
target/loongarch: Use actual operand size with vbsrl check
20
hw/intc/loongarch_pch_pic: add irq number property
21
hw/loongarch/virt: Create fdt table on machine creation done notification
21
hw/intc/loongarch_pch: Change default irq number of pch irq controller
22
hw/loongarch/virt: Improve fdt table creation for CPU object
23
target/loongarch: Use auto method with LSX feature
24
target/loongarch: Use auto method with LASX feature
22
25
23
hw/intc/loongarch_pch_msi.c | 29 ++++++++++++++++++++++++++---
26
Guo Hongyu (1):
24
hw/intc/loongarch_pch_pic.c | 35 +++++++++++++++++++++++++++++++----
27
target/loongarch: Fix vldi inst
25
hw/loongarch/virt.c | 19 ++++++++++++-------
28
26
include/hw/intc/loongarch_pch_msi.h | 9 +++++----
29
hw/loongarch/virt.c | 142 ++++++++++++++----------
27
include/hw/intc/loongarch_pch_pic.h | 6 ++----
30
target/loongarch/cpu.c | 86 ++++++++------
28
include/hw/pci-host/ls7a.h | 2 +-
31
target/loongarch/cpu.h | 4 +
29
6 files changed, 77 insertions(+), 23 deletions(-)
32
target/loongarch/kvm/kvm.c | 107 ++++++++++++++++++
33
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 4 +-
34
5 files changed, 249 insertions(+), 94 deletions(-)
diff view generated by jsdifflib
New patch
1
From: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
1
2
3
Refer to the link below for a description of the vldi instructions:
4
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
5
Fixed errors in vldi instruction implementation.
6
7
Signed-off-by: Guo Hongyu <guohongyu24@mails.ucas.ac.cn>
8
Tested-by: Xianglai Li <lixianglai@loongson.cn>
9
Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
10
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
11
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
12
---
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
20
@@ -XXX,XX +XXX,XX @@ static uint64_t vldi_get_value(DisasContext *ctx, uint32_t imm)
21
break;
22
case 1:
23
/* data: {2{16'0, imm[7:0], 8'0}} */
24
- data = (t << 24) | (t << 8);
25
+ data = (t << 40) | (t << 8);
26
break;
27
case 2:
28
/* data: {2{8'0, imm[7:0], 16'0}} */
29
--
30
2.43.5
diff view generated by jsdifflib
New patch
1
Hardcoded 32 bytes is used for vbsrl emulation check, there is
2
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
3
in TCG mode. It injects LASX exception rather LSX exception.
1
4
5
Here actual operand size is used.
6
7
Cc: qemu-stable@nongnu.org
8
Fixes: df97f338076 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
9
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
---
13
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/target/loongarch/tcg/insn_trans/trans_vec.c.inc b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/loongarch/tcg/insn_trans/trans_vec.c.inc
19
+++ b/target/loongarch/tcg/insn_trans/trans_vec.c.inc
20
@@ -XXX,XX +XXX,XX @@ static bool do_vbsrl_v(DisasContext *ctx, arg_vv_i *a, uint32_t oprsz)
21
{
22
int i, ofs;
23
24
- if (!check_vec(ctx, 32)) {
25
+ if (!check_vec(ctx, oprsz)) {
26
return true;
27
}
28
29
--
30
2.43.5
31
32
diff view generated by jsdifflib
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
The same with ACPI table, fdt table is created on machine done
2
notification. Some objects like CPU objects can be created with cold-plug
3
method with command such as -smp x, -device la464-loongarch-cpu, so all
4
objects finish to create when machine is done.
2
5
3
With loongarch 7A1000 manual, irq number supported can be set
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
5
for loongarch_pch_pic, so that virt machine can set different
8
---
6
irq number when pch_pic intc is added.
9
hw/loongarch/virt.c | 103 ++++++++++++++++++++++++--------------------
10
1 file changed, 57 insertions(+), 46 deletions(-)
7
11
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Reviewed-by: Song Gao <gaosong@loongson.cn>
10
Message-Id: <20230104020518.2564263-3-zhaotianrui@loongson.cn>
11
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
---
13
hw/intc/loongarch_pch_pic.c | 34 +++++++++++++++++++++++++----
14
hw/loongarch/virt.c | 8 ++++---
15
include/hw/intc/loongarch_pch_pic.h | 5 ++---
16
3 files changed, 37 insertions(+), 10 deletions(-)
17
18
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/loongarch_pch_pic.c
21
+++ b/hw/intc/loongarch_pch_pic.c
22
@@ -XXX,XX +XXX,XX @@
23
*/
24
25
#include "qemu/osdep.h"
26
+#include "qemu/bitops.h"
27
#include "hw/sysbus.h"
28
#include "hw/loongarch/virt.h"
29
#include "hw/irq.h"
30
#include "hw/intc/loongarch_pch_pic.h"
31
+#include "hw/qdev-properties.h"
32
#include "migration/vmstate.h"
33
#include "trace.h"
34
+#include "qapi/error.h"
35
36
static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
37
{
38
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
39
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
40
uint64_t mask = 1ULL << irq;
41
42
- assert(irq < PCH_PIC_IRQ_NUM);
43
+ assert(irq < s->irq_num);
44
trace_loongarch_pch_pic_irq_handler(irq, level);
45
46
if (s->intedge & mask) {
47
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
val = PCH_PIC_INT_ID_VAL;
49
break;
50
case PCH_PIC_INT_ID_HI:
51
- val = PCH_PIC_INT_ID_NUM;
52
+ /*
53
+ * With 7A1000 manual
54
+ * bit 0-15 pch irqchip version
55
+ * bit 16-31 irq number supported with pch irqchip
56
+ */
57
+ val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);
58
break;
59
case PCH_PIC_INT_MASK_LO:
60
val = (uint32_t)s->int_mask;
61
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
62
s->int_polarity = 0x0;
63
}
64
65
+static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
66
+{
67
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
68
+
69
+ if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) {
70
+ error_setg(errp, "Invalid 'pic_irq_num'");
71
+ return;
72
+ }
73
+
74
+ qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
75
+ qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
76
+}
77
+
78
static void loongarch_pch_pic_init(Object *obj)
79
{
80
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
81
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_init(Object *obj)
82
sysbus_init_mmio(sbd, &s->iomem8);
83
sysbus_init_mmio(sbd, &s->iomem32_high);
84
85
- qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
86
- qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
87
}
88
89
+static Property loongarch_pch_pic_properties[] = {
90
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
91
+ DEFINE_PROP_END_OF_LIST(),
92
+};
93
+
94
static const VMStateDescription vmstate_loongarch_pch_pic = {
95
.name = TYPE_LOONGARCH_PCH_PIC,
96
.version_id = 1,
97
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
98
{
99
DeviceClass *dc = DEVICE_CLASS(klass);
100
101
+ dc->realize = loongarch_pch_pic_realize;
102
dc->reset = loongarch_pch_pic_reset;
103
dc->vmsd = &vmstate_loongarch_pch_pic;
104
+ device_class_set_props(dc, loongarch_pch_pic_properties);
105
}
106
107
static const TypeInfo loongarch_pch_pic_info = {
108
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
109
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/loongarch/virt.c
14
--- a/hw/loongarch/virt.c
111
+++ b/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
112
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
16
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(LoongArchVirtMachineState *lvms)
113
}
17
}
114
18
}
115
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
19
116
+ num = PCH_PIC_IRQ_NUM;
20
+static void virt_fdt_setup(LoongArchVirtMachineState *lvms)
117
+ qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
21
+{
118
d = SYS_BUS_DEVICE(pch_pic);
22
+ MachineState *machine = MACHINE(lvms);
119
sysbus_realize_and_unref(d, &error_fatal);
23
+ uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
120
memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
24
+ int i;
121
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
25
+
122
VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
26
+ create_fdt(lvms);
123
sysbus_mmio_get_region(d, 2));
27
+ fdt_add_cpu_nodes(lvms);
124
28
+ fdt_add_memory_nodes(machine);
125
- /* Connect 64 pch_pic irqs to extioi */
29
+ fdt_add_fw_cfg_node(lvms);
126
- for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
30
+ fdt_add_flash_node(lvms);
127
+ /* Connect pch_pic irqs to extioi */
31
+
128
+ for (int i = 0; i < num; i++) {
32
+ /* Add cpu interrupt-controller */
33
+ fdt_add_cpuic_node(lvms, &cpuintc_phandle);
34
+ /* Add Extend I/O Interrupt Controller node */
35
+ fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
36
+ /* Add PCH PIC node */
37
+ fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
38
+ /* Add PCH MSI node */
39
+ fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
40
+ /* Add pcie node */
41
+ fdt_add_pcie_node(lvms, &pch_pic_phandle, &pch_msi_phandle);
42
+
43
+ /*
44
+ * Create uart fdt node in reverse order so that they appear
45
+ * in the finished device tree lowest address first
46
+ */
47
+ for (i = VIRT_UART_COUNT; i-- > 0;) {
48
+ hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
49
+ int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
50
+ fdt_add_uart_node(lvms, &pch_pic_phandle, base, irq, i == 0);
51
+ }
52
+
53
+ fdt_add_rtc_node(lvms, &pch_pic_phandle);
54
+ fdt_add_ged_reset(lvms);
55
+ platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
56
+ VIRT_PLATFORM_BUS_BASEADDRESS,
57
+ VIRT_PLATFORM_BUS_SIZE,
58
+ VIRT_PLATFORM_BUS_IRQ);
59
+
60
+ /*
61
+ * Since lowmem region starts from 0 and Linux kernel legacy start address
62
+ * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
63
+ * access. FDT size limit with 1 MiB.
64
+ * Put the FDT into the memory map as a ROM image: this will ensure
65
+ * the FDT is copied again upon reset, even if addr points into RAM.
66
+ */
67
+ qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
68
+ rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
69
+ &address_space_memory);
70
+ qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
71
+ rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
72
+}
73
+
74
static void virt_done(Notifier *notifier, void *data)
75
{
76
LoongArchVirtMachineState *lvms = container_of(notifier,
77
LoongArchVirtMachineState, machine_done);
78
virt_build_smbios(lvms);
79
loongarch_acpi_setup(lvms);
80
+ virt_fdt_setup(lvms);
81
}
82
83
static void virt_powerdown_req(Notifier *notifier, void *opaque)
84
@@ -XXX,XX +XXX,XX @@ static DeviceState *create_platform_bus(DeviceState *pch_pic)
85
}
86
87
static void virt_devices_init(DeviceState *pch_pic,
88
- LoongArchVirtMachineState *lvms,
89
- uint32_t *pch_pic_phandle,
90
- uint32_t *pch_msi_phandle)
91
+ LoongArchVirtMachineState *lvms)
92
{
93
MachineClass *mc = MACHINE_GET_CLASS(lvms);
94
DeviceState *gpex_dev;
95
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
96
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
97
}
98
99
- /* Add pcie node */
100
- fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
101
-
102
/*
103
* Create uart fdt node in reverse order so that they appear
104
* in the finished device tree lowest address first
105
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
106
serial_mm_init(get_system_memory(), base, 0,
107
qdev_get_gpio_in(pch_pic, irq),
108
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
109
- fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
110
}
111
112
/* Network init */
113
@@ -XXX,XX +XXX,XX @@ static void virt_devices_init(DeviceState *pch_pic,
114
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
115
qdev_get_gpio_in(pch_pic,
116
VIRT_RTC_IRQ - VIRT_GSI_BASE));
117
- fdt_add_rtc_node(lvms, pch_pic_phandle);
118
- fdt_add_ged_reset(lvms);
119
120
/* acpi ged */
121
lvms->acpi_ged = create_acpi_ged(pch_pic, lvms);
122
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
123
CPULoongArchState *env;
124
CPUState *cpu_state;
125
int cpu, pin, i, start, num;
126
- uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle;
127
128
/*
129
* Extended IRQ model.
130
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
131
memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR,
132
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
133
134
- /* Add cpu interrupt-controller */
135
- fdt_add_cpuic_node(lvms, &cpuintc_phandle);
136
-
137
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
138
cpu_state = qemu_get_cpu(cpu);
139
cpudev = DEVICE(cpu_state);
140
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
141
}
142
}
143
144
- /* Add Extend I/O Interrupt Controller node */
145
- fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
146
-
147
pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
148
num = VIRT_PCH_PIC_IRQ_NUM;
149
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
150
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
129
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
151
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
130
}
152
}
131
153
154
- /* Add PCH PIC node */
155
- fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle);
156
-
132
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
157
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
133
- start = PCH_PIC_IRQ_NUM;
158
start = num;
134
+ start = num;
135
num = EXTIOI_IRQS - start;
159
num = EXTIOI_IRQS - start;
136
qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
160
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
137
qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
161
qdev_get_gpio_in(extioi, i + start));
138
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
162
}
139
index XXXXXXX..XXXXXXX 100644
163
140
--- a/include/hw/intc/loongarch_pch_pic.h
164
- /* Add PCH MSI node */
141
+++ b/include/hw/intc/loongarch_pch_pic.h
165
- fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle);
142
@@ -XXX,XX +XXX,XX @@
166
-
143
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
167
- virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle);
144
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
168
+ virt_devices_init(pch_pic, lvms);
145
169
}
146
-#define PCH_PIC_IRQ_START 0
170
147
-#define PCH_PIC_IRQ_END 63
171
static void virt_firmware_init(LoongArchVirtMachineState *lvms)
148
#define PCH_PIC_IRQ_NUM 64
172
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
149
#define PCH_PIC_INT_ID_VAL 0x7000000UL
173
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
150
-#define PCH_PIC_INT_ID_NUM 0x3f0001UL
174
}
151
+#define PCH_PIC_INT_ID_VER 0x1UL
175
152
176
- create_fdt(lvms);
153
#define PCH_PIC_INT_ID_LO 0x00
177
-
154
#define PCH_PIC_INT_ID_HI 0x04
178
/* Create IOCSR space */
155
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
179
memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL,
156
MemoryRegion iomem32_low;
180
machine, "iocsr", UINT64_MAX);
157
MemoryRegion iomem32_high;
181
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
158
MemoryRegion iomem8;
182
lacpu = LOONGARCH_CPU(cpu);
159
+ unsigned int irq_num;
183
lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id;
160
};
184
}
185
- fdt_add_cpu_nodes(lvms);
186
- fdt_add_memory_nodes(machine);
187
fw_cfg_add_memory(machine);
188
189
/* Node0 memory */
190
@@ -XXX,XX +XXX,XX @@ static void virt_init(MachineState *machine)
191
memmap_table,
192
sizeof(struct memmap_entry) * (memmap_entries));
193
}
194
- fdt_add_fw_cfg_node(lvms);
195
- fdt_add_flash_node(lvms);
196
197
/* Initialize the IO interrupt subsystem */
198
virt_irq_init(lvms);
199
- platform_bus_add_all_fdt_nodes(machine->fdt, "/platic",
200
- VIRT_PLATFORM_BUS_BASEADDRESS,
201
- VIRT_PLATFORM_BUS_SIZE,
202
- VIRT_PLATFORM_BUS_IRQ);
203
lvms->machine_done.notify = virt_done;
204
qemu_add_machine_init_done_notifier(&lvms->machine_done);
205
/* connect powerdown request */
206
lvms->powerdown_notifier.notify = virt_powerdown_req;
207
qemu_register_powerdown_notifier(&lvms->powerdown_notifier);
208
209
- /*
210
- * Since lowmem region starts from 0 and Linux kernel legacy start address
211
- * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer
212
- * access. FDT size limit with 1 MiB.
213
- * Put the FDT into the memory map as a ROM image: this will ensure
214
- * the FDT is copied again upon reset, even if addr points into RAM.
215
- */
216
- qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size);
217
- rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE,
218
- &address_space_memory);
219
- qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
220
- rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size));
221
-
222
lvms->bootinfo.ram_size = ram_size;
223
loongarch_load_kernel(machine, &lvms->bootinfo);
224
}
161
--
225
--
162
2.31.1
226
2.43.5
diff view generated by jsdifflib
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
For CPU object, possible_cpu_arch_ids() function is used rather than
2
smp.cpus. With command -smp x, -device la464-loongarch-cpu, smp.cpus
3
is not accurate for all possible CPU objects, possible_cpu_arch_ids()
4
is used here.
2
5
3
Change the default irq number of pch pic to 32, so that the irq
6
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM'
7
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
5
macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard
8
---
6
format.
9
hw/loongarch/virt.c | 39 +++++++++++++++++++++++++--------------
10
1 file changed, 25 insertions(+), 14 deletions(-)
7
11
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-Id: <20230104020518.2564263-4-zhaotianrui@loongson.cn>
11
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
---
13
hw/intc/loongarch_pch_pic.c | 3 ++-
14
hw/loongarch/virt.c | 2 +-
15
include/hw/intc/loongarch_pch_msi.h | 6 +++---
16
include/hw/intc/loongarch_pch_pic.h | 1 -
17
include/hw/pci-host/ls7a.h | 1 +
18
5 files changed, 7 insertions(+), 6 deletions(-)
19
20
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/loongarch_pch_pic.c
23
+++ b/hw/intc/loongarch_pch_pic.c
24
@@ -XXX,XX +XXX,XX @@
25
#include "qemu/bitops.h"
26
#include "hw/sysbus.h"
27
#include "hw/loongarch/virt.h"
28
+#include "hw/pci-host/ls7a.h"
29
#include "hw/irq.h"
30
#include "hw/intc/loongarch_pch_pic.h"
31
#include "hw/qdev-properties.h"
32
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
33
{
34
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
35
36
- if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) {
37
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
38
error_setg(errp, "Invalid 'pic_irq_num'");
39
return;
40
}
41
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
12
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
42
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/loongarch/virt.c
14
--- a/hw/loongarch/virt.c
44
+++ b/hw/loongarch/virt.c
15
+++ b/hw/loongarch/virt.c
45
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
16
@@ -XXX,XX +XXX,XX @@ static void create_fdt(LoongArchVirtMachineState *lvms)
17
static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
18
{
19
int num;
20
- const MachineState *ms = MACHINE(lvms);
21
- int smp_cpus = ms->smp.cpus;
22
+ MachineState *ms = MACHINE(lvms);
23
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
24
+ const CPUArchIdList *possible_cpus;
25
+ LoongArchCPU *cpu;
26
+ CPUState *cs;
27
+ char *nodename, *map_path;
28
29
qemu_fdt_add_subnode(ms->fdt, "/cpus");
30
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
31
qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
32
33
/* cpu nodes */
34
- for (num = smp_cpus - 1; num >= 0; num--) {
35
- char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
36
- LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
37
- CPUState *cs = CPU(cpu);
38
+ possible_cpus = mc->possible_cpu_arch_ids(ms);
39
+ for (num = 0; num < possible_cpus->len; num++) {
40
+ cs = possible_cpus->cpus[num].cpu;
41
+ if (cs == NULL) {
42
+ continue;
43
+ }
44
+
45
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
46
+ cpu = LOONGARCH_CPU(cs);
47
48
qemu_fdt_add_subnode(ms->fdt, nodename);
49
qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
50
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
51
cpu->dtb_compatible);
52
- if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
53
+ if (possible_cpus->cpus[num].props.has_node_id) {
54
qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
55
- ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
56
+ possible_cpus->cpus[num].props.node_id);
57
}
58
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
59
qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
60
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
61
62
/*cpu map */
63
qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
64
+ for (num = 0; num < possible_cpus->len; num++) {
65
+ cs = possible_cpus->cpus[num].cpu;
66
+ if (cs == NULL) {
67
+ continue;
68
+ }
69
70
- for (num = smp_cpus - 1; num >= 0; num--) {
71
- char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
72
- char *map_path;
73
-
74
+ nodename = g_strdup_printf("/cpus/cpu@%d", num);
75
if (ms->smp.threads > 1) {
76
map_path = g_strdup_printf(
77
"/cpus/cpu-map/socket%d/core%d/thread%d",
78
@@ -XXX,XX +XXX,XX @@ static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms)
79
num % ms->smp.cores);
80
}
81
qemu_fdt_add_path(ms->fdt, map_path);
82
- qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
83
+ qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename);
84
85
g_free(map_path);
86
- g_free(cpu_path);
87
+ g_free(nodename);
46
}
88
}
47
89
}
48
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
90
49
- num = PCH_PIC_IRQ_NUM;
50
+ num = VIRT_PCH_PIC_IRQ_NUM;
51
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
52
d = SYS_BUS_DEVICE(pch_pic);
53
sysbus_realize_and_unref(d, &error_fatal);
54
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
55
index XXXXXXX..XXXXXXX 100644
56
--- a/include/hw/intc/loongarch_pch_msi.h
57
+++ b/include/hw/intc/loongarch_pch_msi.h
58
@@ -XXX,XX +XXX,XX @@
59
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
60
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
61
62
-/* Msi irq start start from 64 to 255 */
63
-#define PCH_MSI_IRQ_START 64
64
+/* MSI irq start from 32 to 255 */
65
+#define PCH_MSI_IRQ_START 32
66
#define PCH_MSI_IRQ_END 255
67
-#define PCH_MSI_IRQ_NUM 192
68
+#define PCH_MSI_IRQ_NUM 224
69
70
struct LoongArchPCHMSI {
71
SysBusDevice parent_obj;
72
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
73
index XXXXXXX..XXXXXXX 100644
74
--- a/include/hw/intc/loongarch_pch_pic.h
75
+++ b/include/hw/intc/loongarch_pch_pic.h
76
@@ -XXX,XX +XXX,XX @@
77
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
78
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
79
80
-#define PCH_PIC_IRQ_NUM 64
81
#define PCH_PIC_INT_ID_VAL 0x7000000UL
82
#define PCH_PIC_INT_ID_VER 0x1UL
83
84
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/hw/pci-host/ls7a.h
87
+++ b/include/hw/pci-host/ls7a.h
88
@@ -XXX,XX +XXX,XX @@
89
* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
90
* used for pci device.
91
*/
92
+#define VIRT_PCH_PIC_IRQ_NUM 32
93
#define PCH_PIC_IRQ_OFFSET 64
94
#define VIRT_DEVICE_IRQS 16
95
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
96
--
91
--
97
2.31.1
92
2.43.5
98
99
diff view generated by jsdifflib
New patch
1
Like LBT feature, add type OnOffAuto for LSX feature setting. Also
2
add LSX feature detection with new VM ioctl command, fallback to old
3
method if it is not supported.
1
4
5
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
6
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
7
---
8
target/loongarch/cpu.c | 38 +++++++++++++++------------
9
target/loongarch/cpu.h | 2 ++
10
target/loongarch/kvm/kvm.c | 54 ++++++++++++++++++++++++++++++++++++++
11
3 files changed, 77 insertions(+), 17 deletions(-)
12
13
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/loongarch/cpu.c
16
+++ b/target/loongarch/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
18
{
19
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
20
CPULoongArchState *env = &cpu->env;
21
+ uint32_t data = 0;
22
int i;
23
24
for (i = 0; i < 21; i++) {
25
@@ -XXX,XX +XXX,XX @@ static void loongarch_la464_initfn(Object *obj)
26
cpu->dtb_compatible = "loongarch,Loongson-3A5000";
27
env->cpucfg[0] = 0x14c010; /* PRID */
28
29
- uint32_t data = 0;
30
data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
31
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
32
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
33
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
34
{
35
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
36
CPULoongArchState *env = &cpu->env;
37
-
38
+ uint32_t data = 0;
39
int i;
40
41
for (i = 0; i < 21; i++) {
42
@@ -XXX,XX +XXX,XX @@ static void loongarch_la132_initfn(Object *obj)
43
cpu->dtb_compatible = "loongarch,Loongson-1C103";
44
env->cpucfg[0] = 0x148042; /* PRID */
45
46
- uint32_t data = 0;
47
data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
48
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
49
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
50
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
51
52
static bool loongarch_get_lsx(Object *obj, Error **errp)
53
{
54
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
55
- bool ret;
56
-
57
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
58
- ret = true;
59
- } else {
60
- ret = false;
61
- }
62
- return ret;
63
+ return LOONGARCH_CPU(obj)->lsx != ON_OFF_AUTO_OFF;
64
}
65
66
static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
67
{
68
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
69
+ uint32_t val;
70
71
- if (value) {
72
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
73
- } else {
74
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 0);
75
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
76
+ cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
77
+ if (kvm_enabled()) {
78
+ /* kvm feature detection in function kvm_arch_init_vcpu */
79
+ return;
80
}
81
+
82
+ /* LSX feature detection in TCG mode */
83
+ val = cpu->env.cpucfg[2];
84
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
85
+ if (FIELD_EX32(val, CPUCFG2, LSX) == 0) {
86
+ error_setg(errp, "Failed to enable LSX in TCG mode");
87
+ return;
88
+ }
89
+ }
90
+
91
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
92
}
93
94
static bool loongarch_get_lasx(Object *obj, Error **errp)
95
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
96
{
97
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
98
99
+ cpu->lsx = ON_OFF_AUTO_AUTO;
100
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
101
loongarch_set_lsx);
102
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
103
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
104
105
} else {
106
cpu->lbt = ON_OFF_AUTO_OFF;
107
+ cpu->pmu = ON_OFF_AUTO_OFF;
108
}
109
}
110
111
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/loongarch/cpu.h
114
+++ b/target/loongarch/cpu.h
115
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
116
#endif
117
118
enum loongarch_features {
119
+ LOONGARCH_FEATURE_LSX,
120
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
121
LOONGARCH_FEATURE_PMU,
122
};
123
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
124
uint32_t phy_id;
125
OnOffAuto lbt;
126
OnOffAuto pmu;
127
+ OnOffAuto lsx;
128
129
/* 'compatible' string for this CPU for Linux device trees */
130
const char *dtb_compatible;
131
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/loongarch/kvm/kvm.c
134
+++ b/target/loongarch/kvm/kvm.c
135
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
136
{
137
int ret;
138
struct kvm_device_attr attr;
139
+ uint64_t val;
140
141
switch (feature) {
142
+ case LOONGARCH_FEATURE_LSX:
143
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
144
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LSX;
145
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
146
+ if (ret == 0) {
147
+ return true;
148
+ }
149
+
150
+ /* Fallback to old kernel detect interface */
151
+ val = 0;
152
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
153
+ /* Cpucfg2 */
154
+ attr.attr = 2;
155
+ attr.addr = (uint64_t)&val;
156
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
157
+ if (!ret) {
158
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
159
+ if (ret) {
160
+ return false;
161
+ }
162
+
163
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LSX);
164
+ return (ret != 0);
165
+ }
166
+ return false;
167
+
168
case LOONGARCH_FEATURE_LBT:
169
/*
170
* Return all if all the LBT features are supported such as:
171
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
172
return false;
173
}
174
175
+static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
176
+{
177
+ CPULoongArchState *env = cpu_env(cs);
178
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
179
+ bool kvm_supported;
180
+
181
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LSX);
182
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 0);
183
+ if (cpu->lsx == ON_OFF_AUTO_ON) {
184
+ if (kvm_supported) {
185
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
186
+ } else {
187
+ error_setg(errp, "'lsx' feature not supported by KVM on this host");
188
+ return -ENOTSUP;
189
+ }
190
+ } else if ((cpu->lsx == ON_OFF_AUTO_AUTO) && kvm_supported) {
191
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LSX, 1);
192
+ }
193
+
194
+ return 0;
195
+}
196
+
197
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
198
{
199
CPULoongArchState *env = cpu_env(cs);
200
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
201
brk_insn = val;
202
}
203
204
+ ret = kvm_cpu_check_lsx(cs, &local_err);
205
+ if (ret < 0) {
206
+ error_report_err(local_err);
207
+ }
208
+
209
ret = kvm_cpu_check_lbt(cs, &local_err);
210
if (ret < 0) {
211
error_report_err(local_err);
212
--
213
2.43.5
diff view generated by jsdifflib
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
Like LSX feature, add type OnOffAuto for LASX feature setting.
2
2
3
This patch adds irq number property for loongarch msi interrupt
3
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
4
controller, and remove hard coding irq number macro.
4
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
5
---
6
target/loongarch/cpu.c | 50 +++++++++++++++++++++++------------
7
target/loongarch/cpu.h | 2 ++
8
target/loongarch/kvm/kvm.c | 53 ++++++++++++++++++++++++++++++++++++++
9
3 files changed, 89 insertions(+), 16 deletions(-)
5
10
6
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
11
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
---
11
hw/intc/loongarch_pch_msi.c | 29 ++++++++++++++++++++++++++---
12
hw/loongarch/virt.c | 13 ++++++++-----
13
include/hw/intc/loongarch_pch_msi.h | 3 ++-
14
include/hw/pci-host/ls7a.h | 1 -
15
4 files changed, 36 insertions(+), 10 deletions(-)
16
17
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
18
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/loongarch_pch_msi.c
13
--- a/target/loongarch/cpu.c
20
+++ b/hw/intc/loongarch_pch_msi.c
14
+++ b/target/loongarch/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
15
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
22
*/
16
uint32_t val;
23
irq_num = (val & 0xff) - s->irq_base;
17
24
trace_loongarch_msi_set_irq(irq_num);
18
cpu->lsx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
25
- assert(irq_num < PCH_MSI_IRQ_NUM);
19
+ if (cpu->lsx == ON_OFF_AUTO_OFF) {
26
+ assert(irq_num < s->irq_num);
20
+ cpu->lasx = ON_OFF_AUTO_OFF;
27
qemu_set_irq(s->pch_msi_irq[irq_num], 1);
21
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
22
+ error_setg(errp, "Failed to disable LSX since LASX is enabled");
23
+ return;
24
+ }
25
+ }
26
+
27
if (kvm_enabled()) {
28
/* kvm feature detection in function kvm_arch_init_vcpu */
29
return;
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
31
error_setg(errp, "Failed to enable LSX in TCG mode");
32
return;
33
}
34
+ } else {
35
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, 0);
36
+ val = cpu->env.cpucfg[2];
37
}
38
39
cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LSX, value);
40
@@ -XXX,XX +XXX,XX @@ static void loongarch_set_lsx(Object *obj, bool value, Error **errp)
41
42
static bool loongarch_get_lasx(Object *obj, Error **errp)
43
{
44
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
45
- bool ret;
46
-
47
- if (FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LASX)) {
48
- ret = true;
49
- } else {
50
- ret = false;
51
- }
52
- return ret;
53
+ return LOONGARCH_CPU(obj)->lasx != ON_OFF_AUTO_OFF;
28
}
54
}
29
55
30
@@ -XXX,XX +XXX,XX @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
56
static void loongarch_set_lasx(Object *obj, bool value, Error **errp)
31
qemu_set_irq(s->pch_msi_irq[irq], level);
57
{
32
}
58
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
33
59
+ uint32_t val;
34
+static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
60
35
+{
61
- if (value) {
36
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
62
-    if (!FIELD_EX32(cpu->env.cpucfg[2], CPUCFG2, LSX)) {
37
+
63
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LSX, 1);
38
+ if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
64
-    }
39
+ error_setg(errp, "Invalid 'msi_irq_num'");
65
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 1);
66
- } else {
67
- cpu->env.cpucfg[2] = FIELD_DP32(cpu->env.cpucfg[2], CPUCFG2, LASX, 0);
68
+ cpu->lasx = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
69
+ if ((cpu->lsx == ON_OFF_AUTO_OFF) && (cpu->lasx == ON_OFF_AUTO_ON)) {
70
+ error_setg(errp, "Failed to enable LASX since lSX is disabled");
40
+ return;
71
+ return;
41
+ }
72
+ }
42
+
73
+
43
+ s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
74
+ if (kvm_enabled()) {
75
+ /* kvm feature detection in function kvm_arch_init_vcpu */
76
+ return;
77
}
44
+
78
+
45
+ qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
79
+ /* LASX feature detection in TCG mode */
46
+ qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
80
+ val = cpu->env.cpucfg[2];
81
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
82
+ if (FIELD_EX32(val, CPUCFG2, LASX) == 0) {
83
+ error_setg(errp, "Failed to enable LASX in TCG mode");
84
+ return;
85
+ }
86
+ }
87
+
88
+ cpu->env.cpucfg[2] = FIELD_DP32(val, CPUCFG2, LASX, value);
89
}
90
91
static bool loongarch_get_lbt(Object *obj, Error **errp)
92
@@ -XXX,XX +XXX,XX @@ void loongarch_cpu_post_init(Object *obj)
93
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
94
95
cpu->lsx = ON_OFF_AUTO_AUTO;
96
+ cpu->lasx = ON_OFF_AUTO_AUTO;
97
object_property_add_bool(obj, "lsx", loongarch_get_lsx,
98
loongarch_set_lsx);
99
object_property_add_bool(obj, "lasx", loongarch_get_lasx,
100
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/loongarch/cpu.h
103
+++ b/target/loongarch/cpu.h
104
@@ -XXX,XX +XXX,XX @@ typedef struct LoongArchTLB LoongArchTLB;
105
106
enum loongarch_features {
107
LOONGARCH_FEATURE_LSX,
108
+ LOONGARCH_FEATURE_LASX,
109
LOONGARCH_FEATURE_LBT, /* loongson binary translation extension */
110
LOONGARCH_FEATURE_PMU,
111
};
112
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
113
OnOffAuto lbt;
114
OnOffAuto pmu;
115
OnOffAuto lsx;
116
+ OnOffAuto lasx;
117
118
/* 'compatible' string for this CPU for Linux device trees */
119
const char *dtb_compatible;
120
diff --git a/target/loongarch/kvm/kvm.c b/target/loongarch/kvm/kvm.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/target/loongarch/kvm/kvm.c
123
+++ b/target/loongarch/kvm/kvm.c
124
@@ -XXX,XX +XXX,XX @@ static bool kvm_feature_supported(CPUState *cs, enum loongarch_features feature)
125
}
126
return false;
127
128
+ case LOONGARCH_FEATURE_LASX:
129
+ attr.group = KVM_LOONGARCH_VM_FEAT_CTRL;
130
+ attr.attr = KVM_LOONGARCH_VM_FEAT_LASX;
131
+ ret = kvm_vm_ioctl(kvm_state, KVM_HAS_DEVICE_ATTR, &attr);
132
+ if (ret == 0) {
133
+ return true;
134
+ }
135
+
136
+ /* Fallback to old kernel detect interface */
137
+ val = 0;
138
+ attr.group = KVM_LOONGARCH_VCPU_CPUCFG;
139
+ /* Cpucfg2 */
140
+ attr.attr = 2;
141
+ attr.addr = (uint64_t)&val;
142
+ ret = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, &attr);
143
+ if (!ret) {
144
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, &attr);
145
+ if (ret) {
146
+ return false;
147
+ }
148
+
149
+ ret = FIELD_EX32((uint32_t)val, CPUCFG2, LASX);
150
+ return (ret != 0);
151
+ }
152
+ return false;
153
+
154
case LOONGARCH_FEATURE_LBT:
155
/*
156
* Return all if all the LBT features are supported such as:
157
@@ -XXX,XX +XXX,XX @@ static int kvm_cpu_check_lsx(CPUState *cs, Error **errp)
158
return 0;
159
}
160
161
+static int kvm_cpu_check_lasx(CPUState *cs, Error **errp)
162
+{
163
+ CPULoongArchState *env = cpu_env(cs);
164
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
165
+ bool kvm_supported;
166
+
167
+ kvm_supported = kvm_feature_supported(cs, LOONGARCH_FEATURE_LASX);
168
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 0);
169
+ if (cpu->lasx == ON_OFF_AUTO_ON) {
170
+ if (kvm_supported) {
171
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
172
+ } else {
173
+ error_setg(errp, "'lasx' feature not supported by KVM on host");
174
+ return -ENOTSUP;
175
+ }
176
+ } else if ((cpu->lasx == ON_OFF_AUTO_AUTO) && kvm_supported) {
177
+ env->cpucfg[2] = FIELD_DP32(env->cpucfg[2], CPUCFG2, LASX, 1);
178
+ }
179
+
180
+ return 0;
47
+}
181
+}
48
+
182
+
49
+static void loongarch_pch_msi_unrealize(DeviceState *dev)
183
static int kvm_cpu_check_lbt(CPUState *cs, Error **errp)
50
+{
184
{
51
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
185
CPULoongArchState *env = cpu_env(cs);
186
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
187
error_report_err(local_err);
188
}
189
190
+ ret = kvm_cpu_check_lasx(cs, &local_err);
191
+ if (ret < 0) {
192
+ error_report_err(local_err);
193
+ }
52
+
194
+
53
+ g_free(s->pch_msi_irq);
195
ret = kvm_cpu_check_lbt(cs, &local_err);
54
+}
196
if (ret < 0) {
55
+
197
error_report_err(local_err);
56
static void loongarch_pch_msi_init(Object *obj)
57
{
58
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
59
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_msi_init(Object *obj)
60
sysbus_init_mmio(sbd, &s->msi_mmio);
61
msi_nonbroken = true;
62
63
- qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
64
- qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
65
}
66
67
static Property loongarch_msi_properties[] = {
68
DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
69
+ DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
70
DEFINE_PROP_END_OF_LIST(),
71
};
72
73
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
74
{
75
DeviceClass *dc = DEVICE_CLASS(klass);
76
77
+ dc->realize = loongarch_pch_msi_realize;
78
+ dc->unrealize = loongarch_pch_msi_unrealize;
79
device_class_set_props(dc, loongarch_msi_properties);
80
}
81
82
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/loongarch/virt.c
85
+++ b/hw/loongarch/virt.c
86
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
87
LoongArchCPU *lacpu;
88
CPULoongArchState *env;
89
CPUState *cpu_state;
90
- int cpu, pin, i;
91
+ int cpu, pin, i, start, num;
92
93
ipi = qdev_new(TYPE_LOONGARCH_IPI);
94
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
95
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
96
}
97
98
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
99
- qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
100
+ start = PCH_PIC_IRQ_NUM;
101
+ num = EXTIOI_IRQS - start;
102
+ qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
103
+ qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
104
d = SYS_BUS_DEVICE(pch_msi);
105
sysbus_realize_and_unref(d, &error_fatal);
106
sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
107
- for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
108
- /* Connect 192 pch_msi irqs to extioi */
109
+ for (i = 0; i < num; i++) {
110
+ /* Connect pch_msi irqs to extioi */
111
qdev_connect_gpio_out(DEVICE(d), i,
112
- qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
113
+ qdev_get_gpio_in(extioi, i + start));
114
}
115
116
loongarch_devices_init(pch_pic, lams);
117
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
118
index XXXXXXX..XXXXXXX 100644
119
--- a/include/hw/intc/loongarch_pch_msi.h
120
+++ b/include/hw/intc/loongarch_pch_msi.h
121
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
122
123
struct LoongArchPCHMSI {
124
SysBusDevice parent_obj;
125
- qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
126
+ qemu_irq *pch_msi_irq;
127
MemoryRegion msi_mmio;
128
/* irq base passed to upper extioi intc */
129
unsigned int irq_base;
130
+ unsigned int irq_num;
131
};
132
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
133
index XXXXXXX..XXXXXXX 100644
134
--- a/include/hw/pci-host/ls7a.h
135
+++ b/include/hw/pci-host/ls7a.h
136
@@ -XXX,XX +XXX,XX @@
137
*/
138
#define PCH_PIC_IRQ_OFFSET 64
139
#define VIRT_DEVICE_IRQS 16
140
-#define VIRT_PCI_IRQS 48
141
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
142
#define VIRT_UART_BASE 0x1fe001e0
143
#define VIRT_UART_SIZE 0X100
144
--
198
--
145
2.31.1
199
2.43.5
146
147
diff view generated by jsdifflib