[PULL 0/3] loongarch-to-apply queue
[PULL 0/1] loongarch-to-apply queue
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The following changes since commit d1852caab131ea898134fdcea8c14bc2ee75fbe9:
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The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
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Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2023-01-05 16:59:22 +0000)
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Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/gaosong/qemu.git pull-loongarch-20230106
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230605
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for you to fetch changes up to f4d10ce8aa545266a0b6df223a7f8ea2afca18b2:
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for you to fetch changes up to 8555ddc671203969b0e6eb651e538d02a9a79b3a:
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hw/intc/loongarch_pch: Change default irq number of pch irq controller (2023-01-06 14:12:43 +0800)
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hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes (2023-06-05 11:08:55 +0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
14
14
Fixes Coverity CID: 1512452, 1512453
15
Add irq number property for loongarch pch interrupt controller
15
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
16
16
17
----------------------------------------------------------------
17
----------------------------------------------------------------
18
Tianrui Zhao (3):
18
Jiaxun Yang (1):
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hw/intc/loongarch_pch_msi: add irq number property
19
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
20
hw/intc/loongarch_pch_pic: add irq number property
21
hw/intc/loongarch_pch: Change default irq number of pch irq controller
22
20
23
hw/intc/loongarch_pch_msi.c | 29 ++++++++++++++++++++++++++---
21
hw/intc/loongarch_ipi.c | 6 +++---
24
hw/intc/loongarch_pch_pic.c | 35 +++++++++++++++++++++++++++++++----
22
include/hw/intc/loongarch_ipi.h | 4 +++-
25
hw/loongarch/virt.c | 19 ++++++++++++-------
23
2 files changed, 6 insertions(+), 4 deletions(-)
26
include/hw/intc/loongarch_pch_msi.h | 9 +++++----
27
include/hw/intc/loongarch_pch_pic.h | 6 ++----
28
include/hw/pci-host/ls7a.h | 2 +-
29
6 files changed, 77 insertions(+), 23 deletions(-)
diff view generated by jsdifflib
[PULL 1/3] hw/intc/loongarch_pch_msi: add irq number property
Deleted patch
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
2
1
3
This patch adds irq number property for loongarch msi interrupt
4
controller, and remove hard coding irq number macro.
5
6
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn>
9
Signed-off-by: Song Gao <gaosong@loongson.cn>
10
---
11
hw/intc/loongarch_pch_msi.c | 29 ++++++++++++++++++++++++++---
12
hw/loongarch/virt.c | 13 ++++++++-----
13
include/hw/intc/loongarch_pch_msi.h | 3 ++-
14
include/hw/pci-host/ls7a.h | 1 -
15
4 files changed, 36 insertions(+), 10 deletions(-)
16
17
diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/loongarch_pch_msi.c
20
+++ b/hw/intc/loongarch_pch_msi.c
21
@@ -XXX,XX +XXX,XX @@ static void loongarch_msi_mem_write(void *opaque, hwaddr addr,
22
*/
23
irq_num = (val & 0xff) - s->irq_base;
24
trace_loongarch_msi_set_irq(irq_num);
25
- assert(irq_num < PCH_MSI_IRQ_NUM);
26
+ assert(irq_num < s->irq_num);
27
qemu_set_irq(s->pch_msi_irq[irq_num], 1);
28
}
29
30
@@ -XXX,XX +XXX,XX @@ static void pch_msi_irq_handler(void *opaque, int irq, int level)
31
qemu_set_irq(s->pch_msi_irq[irq], level);
32
}
33
34
+static void loongarch_pch_msi_realize(DeviceState *dev, Error **errp)
35
+{
36
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
37
+
38
+ if (!s->irq_num || s->irq_num > PCH_MSI_IRQ_NUM) {
39
+ error_setg(errp, "Invalid 'msi_irq_num'");
40
+ return;
41
+ }
42
+
43
+ s->pch_msi_irq = g_new(qemu_irq, s->irq_num);
44
+
45
+ qdev_init_gpio_out(dev, s->pch_msi_irq, s->irq_num);
46
+ qdev_init_gpio_in(dev, pch_msi_irq_handler, s->irq_num);
47
+}
48
+
49
+static void loongarch_pch_msi_unrealize(DeviceState *dev)
50
+{
51
+ LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(dev);
52
+
53
+ g_free(s->pch_msi_irq);
54
+}
55
+
56
static void loongarch_pch_msi_init(Object *obj)
57
{
58
LoongArchPCHMSI *s = LOONGARCH_PCH_MSI(obj);
59
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_msi_init(Object *obj)
60
sysbus_init_mmio(sbd, &s->msi_mmio);
61
msi_nonbroken = true;
62
63
- qdev_init_gpio_out(DEVICE(obj), s->pch_msi_irq, PCH_MSI_IRQ_NUM);
64
- qdev_init_gpio_in(DEVICE(obj), pch_msi_irq_handler, PCH_MSI_IRQ_NUM);
65
}
66
67
static Property loongarch_msi_properties[] = {
68
DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0),
69
+ DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0),
70
DEFINE_PROP_END_OF_LIST(),
71
};
72
73
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data)
74
{
75
DeviceClass *dc = DEVICE_CLASS(klass);
76
77
+ dc->realize = loongarch_pch_msi_realize;
78
+ dc->unrealize = loongarch_pch_msi_unrealize;
79
device_class_set_props(dc, loongarch_msi_properties);
80
}
81
82
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/loongarch/virt.c
85
+++ b/hw/loongarch/virt.c
86
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
87
LoongArchCPU *lacpu;
88
CPULoongArchState *env;
89
CPUState *cpu_state;
90
- int cpu, pin, i;
91
+ int cpu, pin, i, start, num;
92
93
ipi = qdev_new(TYPE_LOONGARCH_IPI);
94
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
95
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
96
}
97
98
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
99
- qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
100
+ start = PCH_PIC_IRQ_NUM;
101
+ num = EXTIOI_IRQS - start;
102
+ qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
103
+ qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
104
d = SYS_BUS_DEVICE(pch_msi);
105
sysbus_realize_and_unref(d, &error_fatal);
106
sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
107
- for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
108
- /* Connect 192 pch_msi irqs to extioi */
109
+ for (i = 0; i < num; i++) {
110
+ /* Connect pch_msi irqs to extioi */
111
qdev_connect_gpio_out(DEVICE(d), i,
112
- qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
113
+ qdev_get_gpio_in(extioi, i + start));
114
}
115
116
loongarch_devices_init(pch_pic, lams);
117
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
118
index XXXXXXX..XXXXXXX 100644
119
--- a/include/hw/intc/loongarch_pch_msi.h
120
+++ b/include/hw/intc/loongarch_pch_msi.h
121
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
122
123
struct LoongArchPCHMSI {
124
SysBusDevice parent_obj;
125
- qemu_irq pch_msi_irq[PCH_MSI_IRQ_NUM];
126
+ qemu_irq *pch_msi_irq;
127
MemoryRegion msi_mmio;
128
/* irq base passed to upper extioi intc */
129
unsigned int irq_base;
130
+ unsigned int irq_num;
131
};
132
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
133
index XXXXXXX..XXXXXXX 100644
134
--- a/include/hw/pci-host/ls7a.h
135
+++ b/include/hw/pci-host/ls7a.h
136
@@ -XXX,XX +XXX,XX @@
137
*/
138
#define PCH_PIC_IRQ_OFFSET 64
139
#define VIRT_DEVICE_IRQS 16
140
-#define VIRT_PCI_IRQS 48
141
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
142
#define VIRT_UART_BASE 0x1fe001e0
143
#define VIRT_UART_SIZE 0X100
144
--
145
2.31.1
146
147
diff view generated by jsdifflib
[PULL 2/3] hw/intc/loongarch_pch_pic: add irq number property
Deleted patch
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
2
1
3
With loongarch 7A1000 manual, irq number supported can be set
4
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
5
for loongarch_pch_pic, so that virt machine can set different
6
irq number when pch_pic intc is added.
7
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
9
Reviewed-by: Song Gao <gaosong@loongson.cn>
10
Message-Id: <20230104020518.2564263-3-zhaotianrui@loongson.cn>
11
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
---
13
hw/intc/loongarch_pch_pic.c | 34 +++++++++++++++++++++++++----
14
hw/loongarch/virt.c | 8 ++++---
15
include/hw/intc/loongarch_pch_pic.h | 5 ++---
16
3 files changed, 37 insertions(+), 10 deletions(-)
17
18
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/loongarch_pch_pic.c
21
+++ b/hw/intc/loongarch_pch_pic.c
22
@@ -XXX,XX +XXX,XX @@
23
*/
24
25
#include "qemu/osdep.h"
26
+#include "qemu/bitops.h"
27
#include "hw/sysbus.h"
28
#include "hw/loongarch/virt.h"
29
#include "hw/irq.h"
30
#include "hw/intc/loongarch_pch_pic.h"
31
+#include "hw/qdev-properties.h"
32
#include "migration/vmstate.h"
33
#include "trace.h"
34
+#include "qapi/error.h"
35
36
static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
37
{
38
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
39
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
40
uint64_t mask = 1ULL << irq;
41
42
- assert(irq < PCH_PIC_IRQ_NUM);
43
+ assert(irq < s->irq_num);
44
trace_loongarch_pch_pic_irq_handler(irq, level);
45
46
if (s->intedge & mask) {
47
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
48
val = PCH_PIC_INT_ID_VAL;
49
break;
50
case PCH_PIC_INT_ID_HI:
51
- val = PCH_PIC_INT_ID_NUM;
52
+ /*
53
+ * With 7A1000 manual
54
+ * bit 0-15 pch irqchip version
55
+ * bit 16-31 irq number supported with pch irqchip
56
+ */
57
+ val = deposit32(PCH_PIC_INT_ID_VER, 16, 16, s->irq_num - 1);
58
break;
59
case PCH_PIC_INT_MASK_LO:
60
val = (uint32_t)s->int_mask;
61
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
62
s->int_polarity = 0x0;
63
}
64
65
+static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
66
+{
67
+ LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
68
+
69
+ if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) {
70
+ error_setg(errp, "Invalid 'pic_irq_num'");
71
+ return;
72
+ }
73
+
74
+ qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
75
+ qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
76
+}
77
+
78
static void loongarch_pch_pic_init(Object *obj)
79
{
80
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
81
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_init(Object *obj)
82
sysbus_init_mmio(sbd, &s->iomem8);
83
sysbus_init_mmio(sbd, &s->iomem32_high);
84
85
- qdev_init_gpio_out(DEVICE(obj), s->parent_irq, PCH_PIC_IRQ_NUM);
86
- qdev_init_gpio_in(DEVICE(obj), pch_pic_irq_handler, PCH_PIC_IRQ_NUM);
87
}
88
89
+static Property loongarch_pch_pic_properties[] = {
90
+ DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPCHPIC, irq_num, 0),
91
+ DEFINE_PROP_END_OF_LIST(),
92
+};
93
+
94
static const VMStateDescription vmstate_loongarch_pch_pic = {
95
.name = TYPE_LOONGARCH_PCH_PIC,
96
.version_id = 1,
97
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
98
{
99
DeviceClass *dc = DEVICE_CLASS(klass);
100
101
+ dc->realize = loongarch_pch_pic_realize;
102
dc->reset = loongarch_pch_pic_reset;
103
dc->vmsd = &vmstate_loongarch_pch_pic;
104
+ device_class_set_props(dc, loongarch_pch_pic_properties);
105
}
106
107
static const TypeInfo loongarch_pch_pic_info = {
108
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/loongarch/virt.c
111
+++ b/hw/loongarch/virt.c
112
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
113
}
114
115
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
116
+ num = PCH_PIC_IRQ_NUM;
117
+ qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
118
d = SYS_BUS_DEVICE(pch_pic);
119
sysbus_realize_and_unref(d, &error_fatal);
120
memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
121
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
122
VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
123
sysbus_mmio_get_region(d, 2));
124
125
- /* Connect 64 pch_pic irqs to extioi */
126
- for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
127
+ /* Connect pch_pic irqs to extioi */
128
+ for (int i = 0; i < num; i++) {
129
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
130
}
131
132
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
133
- start = PCH_PIC_IRQ_NUM;
134
+ start = num;
135
num = EXTIOI_IRQS - start;
136
qdev_prop_set_uint32(pch_msi, "msi_irq_base", start);
137
qdev_prop_set_uint32(pch_msi, "msi_irq_num", num);
138
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
139
index XXXXXXX..XXXXXXX 100644
140
--- a/include/hw/intc/loongarch_pch_pic.h
141
+++ b/include/hw/intc/loongarch_pch_pic.h
142
@@ -XXX,XX +XXX,XX @@
143
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
144
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
145
146
-#define PCH_PIC_IRQ_START 0
147
-#define PCH_PIC_IRQ_END 63
148
#define PCH_PIC_IRQ_NUM 64
149
#define PCH_PIC_INT_ID_VAL 0x7000000UL
150
-#define PCH_PIC_INT_ID_NUM 0x3f0001UL
151
+#define PCH_PIC_INT_ID_VER 0x1UL
152
153
#define PCH_PIC_INT_ID_LO 0x00
154
#define PCH_PIC_INT_ID_HI 0x04
155
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
156
MemoryRegion iomem32_low;
157
MemoryRegion iomem32_high;
158
MemoryRegion iomem8;
159
+ unsigned int irq_num;
160
};
161
--
162
2.31.1
diff view generated by jsdifflib
[PULL 3/3] hw/intc/loongarch_pch: Change default irq number of pch irq controller
[PULL 1/1] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
1
From: Tianrui Zhao <zhaotianrui@loongson.cn>
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
2
2
3
Change the default irq number of pch pic to 32, so that the irq
3
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
4
number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM'
4
Loongson 3A5000's IPI implementation have 4 mailboxes per
5
macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard
5
core.
6
format.
7
6
8
Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
7
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
percpu device"), the number of IPI mailboxes was reduced to
10
Message-Id: <20230104020518.2564263-4-zhaotianrui@loongson.cn>
9
one, which mismatches actual hardware.
10
11
It won't affect LoongArch based system as LoongArch boot code
12
only uses the first mailbox, however MIPS based Loongson boot
13
code uses all 4 mailboxes.
14
15
Fixes Coverity CID: 1512452, 1512453
16
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
17
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
18
Reviewed-by: Song Gao <gaosong@loongson.cn>
19
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
11
Signed-off-by: Song Gao <gaosong@loongson.cn>
20
Signed-off-by: Song Gao <gaosong@loongson.cn>
12
---
21
---
13
hw/intc/loongarch_pch_pic.c | 3 ++-
22
hw/intc/loongarch_ipi.c | 6 +++---
14
hw/loongarch/virt.c | 2 +-
23
include/hw/intc/loongarch_ipi.h | 4 +++-
15
include/hw/intc/loongarch_pch_msi.h | 6 +++---
24
2 files changed, 6 insertions(+), 4 deletions(-)
16
include/hw/intc/loongarch_pch_pic.h | 1 -
17
include/hw/pci-host/ls7a.h | 1 +
18
5 files changed, 7 insertions(+), 6 deletions(-)
19
25
20
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
26
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
21
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/loongarch_pch_pic.c
28
--- a/hw/intc/loongarch_ipi.c
23
+++ b/hw/intc/loongarch_pch_pic.c
29
+++ b/hw/intc/loongarch_ipi.c
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
31
32
static const VMStateDescription vmstate_ipi_core = {
33
.name = "ipi-single",
34
- .version_id = 1,
35
- .minimum_version_id = 1,
36
+ .version_id = 2,
37
+ .minimum_version_id = 2,
38
.fields = (VMStateField[]) {
39
VMSTATE_UINT32(status, IPICore),
40
VMSTATE_UINT32(en, IPICore),
41
VMSTATE_UINT32(set, IPICore),
42
VMSTATE_UINT32(clear, IPICore),
43
- VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
44
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
45
VMSTATE_END_OF_LIST()
46
}
47
};
48
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/hw/intc/loongarch_ipi.h
51
+++ b/include/hw/intc/loongarch_ipi.h
24
@@ -XXX,XX +XXX,XX @@
52
@@ -XXX,XX +XXX,XX @@
25
#include "qemu/bitops.h"
53
#define MAIL_SEND_OFFSET 0
26
#include "hw/sysbus.h"
54
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
27
#include "hw/loongarch/virt.h"
55
28
+#include "hw/pci-host/ls7a.h"
56
+#define IPI_MBX_NUM 4
29
#include "hw/irq.h"
57
+
30
#include "hw/intc/loongarch_pch_pic.h"
58
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
31
#include "hw/qdev-properties.h"
59
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
32
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
60
33
{
61
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
34
LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
62
uint32_t set;
35
63
uint32_t clear;
36
- if (!s->irq_num || s->irq_num > PCH_PIC_IRQ_NUM) {
64
/* 64bit buf divide into 2 32bit buf */
37
+ if (!s->irq_num || s->irq_num > VIRT_PCH_PIC_IRQ_NUM) {
65
- uint32_t buf[2];
38
error_setg(errp, "Invalid 'pic_irq_num'");
66
+ uint32_t buf[IPI_MBX_NUM * 2];
39
return;
67
qemu_irq irq;
40
}
68
} IPICore;
41
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
69
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/loongarch/virt.c
44
+++ b/hw/loongarch/virt.c
45
@@ -XXX,XX +XXX,XX @@ static void loongarch_irq_init(LoongArchMachineState *lams)
46
}
47
48
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
49
- num = PCH_PIC_IRQ_NUM;
50
+ num = VIRT_PCH_PIC_IRQ_NUM;
51
qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
52
d = SYS_BUS_DEVICE(pch_pic);
53
sysbus_realize_and_unref(d, &error_fatal);
54
diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h
55
index XXXXXXX..XXXXXXX 100644
56
--- a/include/hw/intc/loongarch_pch_msi.h
57
+++ b/include/hw/intc/loongarch_pch_msi.h
58
@@ -XXX,XX +XXX,XX @@
59
#define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi"
60
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI)
61
62
-/* Msi irq start start from 64 to 255 */
63
-#define PCH_MSI_IRQ_START 64
64
+/* MSI irq start from 32 to 255 */
65
+#define PCH_MSI_IRQ_START 32
66
#define PCH_MSI_IRQ_END 255
67
-#define PCH_MSI_IRQ_NUM 192
68
+#define PCH_MSI_IRQ_NUM 224
69
70
struct LoongArchPCHMSI {
71
SysBusDevice parent_obj;
72
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
73
index XXXXXXX..XXXXXXX 100644
74
--- a/include/hw/intc/loongarch_pch_pic.h
75
+++ b/include/hw/intc/loongarch_pch_pic.h
76
@@ -XXX,XX +XXX,XX @@
77
#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
78
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
79
80
-#define PCH_PIC_IRQ_NUM 64
81
#define PCH_PIC_INT_ID_VAL 0x7000000UL
82
#define PCH_PIC_INT_ID_VER 0x1UL
83
84
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
85
index XXXXXXX..XXXXXXX 100644
86
--- a/include/hw/pci-host/ls7a.h
87
+++ b/include/hw/pci-host/ls7a.h
88
@@ -XXX,XX +XXX,XX @@
89
* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
90
* used for pci device.
91
*/
92
+#define VIRT_PCH_PIC_IRQ_NUM 32
93
#define PCH_PIC_IRQ_OFFSET 64
94
#define VIRT_DEVICE_IRQS 16
95
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
96
--
70
--
97
2.31.1
71
2.39.1
98
99
diff view generated by jsdifflib

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