Series comparison

-[PULL 00/34] target-arm queue
+[PULL 00/33] target-arm queue
-Some arm patches; my to-review queue is by no means empty, but
+The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:
 this is a big enough set of patches to be getting on with...
--- PMM
+  Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)
 The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
   .gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs (2023-01-04 18:58:33 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230105
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203
-for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
+for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:
-  hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33:00 +0000)
+  target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Implement AArch32 ARMv8-R support
+ * Fix physical address resolution for Stage2
- * Add Cortex-R52 CPU
+ * pl011: refactoring, implement reset method
- * fix handling of HLT semihosting in system mode
+ * Support GICv3 with hvf acceleration
- * hw/timer/ixm_epit: cleanup and fix bug in compare handling
+ * sbsa-ref: remove cortex-a76 from list of supported cpus
- * target/arm: Coding style fixes
+ * Correct syndrome for ATS12NSO* traps at Secure EL1
- * target/arm: Clean up includes
+ * Fix priority of HSTR_EL2 traps vs UNDEFs
- * nseries: minor code cleanups
+ * Implement FEAT_FGT for '-cpu max'
  * target/arm: align exposed ID registers with Linux
  * hw/arm/smmu-common: remove unnecessary inlines
  * i.MX7D: Handle GPT timers
  * i.MX7D: Connect IRQs to GPIO devices
  * i.MX6UL: Add a specific GPT timer instance
  * hw/net: Fix read of uninitialized memory in imx_fec
 ----------------------------------------------------------------
-Alex Bennée (1):
+Alexander Graf (3):
-      target/arm: fix handling of HLT semihosting in system mode
+      hvf: arm: Add support for GICv3
       hw/arm/virt: Consolidate GIC finalize logic
       hw/arm/virt: Make accels in GIC finalize logic explicit
-Axel Heider (8):
+Evgeny Iakovlev (4):
-      hw/timer/imx_epit: improve comments
+      hw/char/pl011: refactor FIFO depth handling code
-      hw/timer/imx_epit: cleanup CR defines
+      hw/char/pl011: add post_load hook for backwards-compatibility
-      hw/timer/imx_epit: define SR_OCIF
+      hw/char/pl011: implement a reset method
-      hw/timer/imx_epit: update interrupt state on CR write access
+      hw/char/pl011: better handling of FIFO flags on LCR reset
       hw/timer/imx_epit: hard reset initializes CR with 0
       hw/timer/imx_epit: factor out register write handlers
       hw/timer/imx_epit: remove explicit fields cnt and freq
       hw/timer/imx_epit: fix compare timer handling
-Claudio Fontana (1):
+Marcin Juszkiewicz (1):
-      target/arm: cleanup cpu includes
+      sbsa-ref: remove cortex-a76 from list of supported cpus
-Fabiano Rosas (5):
+Peter Maydell (23):
-      target/arm: Fix checkpatch comment style warnings in helper.c
+      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
-      target/arm: Fix checkpatch space errors in helper.c
+      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
-      target/arm: Fix checkpatch brace errors in helper.c
+      target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
-      target/arm: Remove unused includes from m_helper.c
+      target/arm: Move do_coproc_insn() syndrome calculation earlier
-      target/arm: Remove unused includes from helper.c
+      target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
       target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
       target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
       target/arm: Define the FEAT_FGT registers
       target/arm: Implement FGT trapping infrastructure
       target/arm: Mark up sysregs for HFGRTR bits 0..11
       target/arm: Mark up sysregs for HFGRTR bits 12..23
       target/arm: Mark up sysregs for HFGRTR bits 24..35
       target/arm: Mark up sysregs for HFGRTR bits 36..63
       target/arm: Mark up sysregs for HDFGRTR bits 0..11
       target/arm: Mark up sysregs for HDFGRTR bits 12..63
       target/arm: Mark up sysregs for HFGITR bits 0..11
       target/arm: Mark up sysregs for HFGITR bits 12..17
       target/arm: Mark up sysregs for HFGITR bits 18..47
       target/arm: Mark up sysregs for HFGITR bits 48..63
       target/arm: Implement the HFGITR_EL2.ERET trap
       target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
       target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
       target/arm: Enable FEAT_FGT on '-cpu max'
-Jean-Christophe Dubois (4):
+Richard Henderson (2):
-      i.MX7D: Connect GPT timers to IRQ
+      hw/arm: Use TYPE_ARM_SMMUV3
-      i.MX7D: Compute clock frequency for the fixed frequency clocks.
+      target/arm: Fix physical address resolution for Stage2
       i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
       i.MX7D: Connect IRQs to GPIO devices.
-Peter Maydell (1):
+ docs/system/arm/emulation.rst |   1 +
-      target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
+ include/hw/arm/virt.h         |  15 +-
+ include/hw/char/pl011.h       |   5 +-
-Philippe Mathieu-Daudé (5):
+ target/arm/cpregs.h           | 484 +++++++++++++++++++++++++++++++++++++++++-
-      hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
+ target/arm/cpu.h              |  18 ++
-      hw/arm/nseries: Constify various read-only arrays
+ target/arm/internals.h        |  20 ++
-      hw/arm/nseries: Silent -Wmissing-field-initializers warning
+ target/arm/syndrome.h         |  10 +
-      hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
+ target/arm/translate.h        |   6 +
-      hw/arm/smmu-common: Avoid using inlined functions with external linkage
+ hw/arm/sbsa-ref.c             |   4 +-
+ hw/arm/virt.c                 | 203 +++++++++---------
-Stephen Longfield (1):
+ hw/char/pl011.c               |  93 ++++++--
-      hw/net: Fix read of uninitialized memory in imx_fec.
+ hw/intc/arm_gicv3_cpuif.c     |  18 +-
+ target/arm/cpu64.c            |   1 +
-Tobias Röhmel (7):
+ target/arm/debug_helper.c     |  46 +++-
-      target/arm: Don't add all MIDR aliases for cores that implement PMSA
+ target/arm/helper.c           | 245 ++++++++++++++++++++-
-      target/arm: Make RVBAR available for all ARMv8 CPUs
+ target/arm/hvf/hvf.c          | 151 +++++++++++++
-      target/arm: Make stage_2_format for cache attributes optional
+ target/arm/op_helper.c        |  58 ++++-
-      target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
+ target/arm/ptw.c              |   2 +-
-      target/arm: Add PMSAv8r registers
+ target/arm/translate-a64.c    |  22 +-
-      target/arm: Add PMSAv8r functionality
+ target/arm/translate.c        | 125 +++++++----
-      target/arm: Add ARM Cortex-R52 CPU
+ target/arm/hvf/trace-events   |   2 +
+files changed, 1340 insertions(+), 189 deletions(-)
 Zhuojia Shen (1):
       target/arm: align exposed ID registers with Linux
  include/hw/arm/fsl-imx7.h         |  20 +
  include/hw/arm/smmu-common.h      |   3 -
  include/hw/input/tsc2xxx.h        |   4 +-
  include/hw/timer/imx_epit.h       |   8 +-
  include/hw/timer/imx_gpt.h        |   1 +
  target/arm/cpu.h                  |   6 +
  target/arm/internals.h            |   4 +
  hw/arm/fsl-imx6ul.c               |   2 +-
  hw/arm/fsl-imx7.c                 |  41 +-
  hw/arm/nseries.c                  |  28 +-
  hw/arm/smmu-common.c              |  15 +-
  hw/input/tsc2005.c                |   2 +-
  hw/input/tsc210x.c                |   3 +-
  hw/misc/imx6ul_ccm.c              |   6 -
  hw/misc/imx7_ccm.c                |  49 ++-
  hw/net/imx_fec.c                  |   8 +-
  hw/timer/imx_epit.c               | 376 +++++++++-------
  hw/timer/imx_gpt.c                |  25 ++
  target/arm/cpu.c                  |  35 +-
  target/arm/cpu64.c                |   6 -
  target/arm/cpu_tcg.c              |  42 ++
  target/arm/debug_helper.c         |   3 +
  target/arm/helper.c               | 871 +++++++++++++++++++++++++++++---------
  target/arm/m_helper.c             |  16 -
  target/arm/machine.c              |  28 ++
  target/arm/ptw.c                  | 152 +++++--
  target/arm/tlb_helper.c           |   4 +
  target/arm/translate.c            |   2 +-
  tests/tcg/aarch64/sysregs.c       |  24 +-
  tests/tcg/aarch64/Makefile.target |   7 +-
 files changed, 1330 insertions(+), 461 deletions(-)

-[PULL 29/34] hw/arm/smmu-common: Avoid using inlined functions with external linkage
+[PULL 01/33] hw/arm: Use TYPE_ARM_SMMUV3
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
+Use the macro instead of two explicit string literals.
 and building with -Wall we get:
-  hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline]
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-  hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
     void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
     ^
     static
 None of our code base require / use inlined functions with external
 linkage. Some places use internal inlining in the hot path. These
 two functions are certainly not in any hot path and don't justify
 any inlining, so these are likely oversights rather than intentional.
 Reported-by: Stefan Weil <sw@weilnetz.de>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20221216214924.4711-3-philmd@linaro.org
+Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/smmu-common.c | 13 ++++++-------
+ hw/arm/sbsa-ref.c | 3 ++-
-file changed, 6 insertions(+), 7 deletions(-)
+ hw/arm/virt.c     | 2 +-
 files changed, 3 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/smmu-common.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/hw/arm/smmu-common.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
+@@ -XXX,XX +XXX,XX @@
-     g_hash_table_insert(bs->iotlb, key, new);
+ #include "exec/hwaddr.h"
- }
+ #include "kvm_arm.h"
+ #include "hw/arm/boot.h"
--inline void smmu_iotlb_inv_all(SMMUState *s)
++#include "hw/arm/smmuv3.h"
-+void smmu_iotlb_inv_all(SMMUState *s)
+ #include "hw/block/flash.h"
- {
+ #include "hw/boards.h"
-     trace_smmu_iotlb_inv_all();
+ #include "hw/ide/internal.h"
-     g_hash_table_remove_all(s->iotlb);
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
-@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
+     DeviceState *dev;
-            ((entry->iova & ~info->mask) == info->iova);
+     int i;
- }
+-    dev = qdev_new("arm-smmuv3");
--inline void
++    dev = qdev_new(TYPE_ARM_SMMUV3);
--smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
--                    uint8_t tg, uint64_t num_pages, uint8_t ttl)
+     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
-+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
+                              &error_abort);
-+                         uint8_t tg, uint64_t num_pages, uint8_t ttl)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
- {
+index XXXXXXX..XXXXXXX 100644
-     /* if tg is not set we use 4KB range invalidation */
+--- a/hw/arm/virt.c
-     uint8_t granule = tg ? tg * 2 + 10 : 12;
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
-                                 &info);
+         return;
- }
+     }
--inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
+-    dev = qdev_new("arm-smmuv3");
-+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
++    dev = qdev_new(TYPE_ARM_SMMUV3);
- {
-     trace_smmu_iotlb_inv_asid(asid);
+     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
-     g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
+                              &error_abort);
@@ -XXX,XX +XXX,XX @@ error:
   *
   * return 0 on success
   */
 -inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 -                    SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
 +int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
 +             SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
  {
      if (!cfg->aa64) {
          /*
 --
-.25.1
+.34.1

-[PULL 04/34] target/arm: Make stage_2_format for cache attributes optional
+[PULL 02/33] target/arm: Fix physical address resolution for Stage2
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+From: Richard Henderson <richard.henderson@linaro.org>
-The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
+Conversion to probe_access_full missed applying the page offset.
 VMSAv8, the stage 2 attributes are in the same format as the stage 1
 attributes (8-bit MAIR format). Rather than converting the MAIR
 format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
 stage 2 descriptor) and then converting back to do the attribute
 combination, allow combined_attrs_nofwb() to accept s2 attributes
 that are already in the MAIR format.
-We move the assert() to combined_attrs_fwb(), because that function
+Cc: qemu-stable@nongnu.org
-really does require a VMSA stage 2 attribute format. (We will never
+Reported-by: Sid Manning <sidneym@quicinc.com>
-get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
-Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 10 ++++++++--
+ target/arm/ptw.c | 2 +-
-file changed, 8 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
- {
+         if (unlikely(flags & TLB_INVALID_MASK)) {
-     uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
+             goto fail;
+         }
--    s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+-        ptw->out_phys = full->phys_addr;
-+    if (s2.is_s2_format) {
++        ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
-+        s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+         ptw->out_rw = full->prot & PAGE_WRITE;
-+    } else {
+         pte_attrs = full->pte_attrs;
-+        s2_mair_attrs = s2.attrs;
+         pte_secure = full->attrs.secure;
 +    }
      s1lo = extract32(s1.attrs, 0, 4);
      s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
   */
  static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
  {
 +    assert(s2.is_s2_format && !s1.is_s2_format);
 +
      switch (s2.attrs) {
      case 7:
          /* Use stage 1 attributes */
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
      ARMCacheAttrs ret;
      bool tagged = false;
 -    assert(s2.is_s2_format && !s1.is_s2_format);
 +    assert(!s1.is_s2_format);
      ret.is_s2_format = false;
      if (s1.attrs == 0xf0) {
 --
-.25.1
+.34.1

-[PULL 07/34] target/arm: Add PMSAv8r functionality
+[PULL 03/33] hw/char/pl011: refactor FIFO depth handling code
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-Add PMSAv8r translation.
+PL011 can be in either of 2 modes depending guest config: FIFO and
 single register. The last mode could be viewed as a 1-element-deep FIFO.
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
 depth handling code to isolate calculating current FIFO depth.
 One functional (albeit guest-invisible) side-effect of this change is
 that previously we would always increment s->read_pos in UARTDR read
 handler even if FIFO was disabled, now we are limiting read_pos to not
 exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).
 Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
+ include/hw/char/pl011.h |  5 ++++-
-file changed, 104 insertions(+), 22 deletions(-)
+ hw/char/pl011.c         | 30 ++++++++++++++++++------------
 files changed, 22 insertions(+), 13 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/include/hw/char/pl011.h
-+++ b/target/arm/ptw.c
++++ b/include/hw/char/pl011.h
-@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
+ /* This shares the same struct (and cast macro) as the base pl011 device */
-     if (arm_feature(env, ARM_FEATURE_M)) {
+ #define TYPE_PL011_LUMINARY "pl011_luminary"
-         return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
--    } else {
++/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
--        return regime_sctlr(env, mmu_idx) & SCTLR_BR;
++#define PL011_FIFO_DEPTH 16
 +
  struct PL011State {
      SysBusDevice parent_obj;
@@ -XXX,XX +XXX,XX @@ struct PL011State {
      uint32_t dmacr;
      uint32_t int_enabled;
      uint32_t int_level;
 -    uint32_t read_fifo[16];
 +    uint32_t read_fifo[PL011_FIFO_DEPTH];
      uint32_t ilpr;
      uint32_t ibrd;
      uint32_t fbrd;
 diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/pl011.c
 +++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
      }
-+
-+    if (mmu_idx == ARMMMUIdx_Stage2) {
-+        return false;
-+    }
-+
-+    return regime_sctlr(env, mmu_idx) & SCTLR_BR;
  }
- static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
++static bool pl011_is_fifo_enabled(PL011State *s)
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
      return !(result->f.prot & (1 << access_type));
  }
 +static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
 +                             uint32_t secure)
 +{
-+    if (regime_el(env, mmu_idx) == 2) {
++    return (s->lcr & 0x10) != 0;
 +        return env->pmsav8.hprbar;
 +    } else {
 +        return env->pmsav8.rbar[secure];
 +    }
 +}
 +
-+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
++static inline unsigned pl011_get_fifo_depth(PL011State *s)
 +                             uint32_t secure)
 +{
-+    if (regime_el(env, mmu_idx) == 2) {
++    /* Note: FIFO depth is expected to be power-of-2 */
-+        return env->pmsav8.hprlar;
++    return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 +    } else {
 +        return env->pmsav8.rlar[secure];
 +    }
 +}
 +
- bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+ static uint64_t pl011_read(void *opaque, hwaddr offset,
-                        MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                            unsigned size)
-                        bool secure, GetPhysAddrResult *result,
+ {
-@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
-     bool hit = false;
+         c = s->read_fifo[s->read_pos];
-     uint32_t addr_page_base = address & TARGET_PAGE_MASK;
+         if (s->read_count > 0) {
-     uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
+             s->read_count--;
-+    int region_counter;
+-            if (++s->read_pos == 16)
-+
+-                s->read_pos = 0;
-+    if (regime_el(env, mmu_idx) == 2) {
++            s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
-+        region_counter = cpu->pmsav8r_hdregion;
+         }
-+    } else {
+         if (s->read_count == 0) {
-+        region_counter = cpu->pmsav7_dregion;
+             s->flags |= PL011_FLAG_RXFE;
-+    }
+@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
+     PL011State *s = (PL011State *)opaque;
-     result->f.lg_page_size = TARGET_PAGE_BITS;
+     int r;
-     result->f.phys_addr = address;
-@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+-    if (s->lcr & 0x10) {
-         *mregion = -1;
+-        r = s->read_count < 16;
 -    } else {
 -        r = s->read_count < 1;
 -    }
 +    r = s->read_count < pl011_get_fifo_depth(s);
      trace_pl011_can_receive(s->lcr, s->read_count, r);
      return r;
  }
@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
  {
      PL011State *s = (PL011State *)opaque;
      int slot;
 +    unsigned pipe_depth;
 -    slot = s->read_pos + s->read_count;
 -    if (slot >= 16)
 -        slot -= 16;
 +    pipe_depth = pl011_get_fifo_depth(s);
 +    slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
      s->read_fifo[slot] = value;
      s->read_count++;
      s->flags &= ~PL011_FLAG_RXFE;
      trace_pl011_put_fifo(value, s->read_count);
 -    if (!(s->lcr & 0x10) || s->read_count == 16) {
 +    if (s->read_count == pipe_depth) {
          trace_pl011_put_fifo_full();
          s->flags |= PL011_FLAG_RXFF;
      }
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
-+    if (mmu_idx == ARMMMUIdx_Stage2) {
+         VMSTATE_UINT32(dmacr, PL011State),
-+        fi->stage2 = true;
+         VMSTATE_UINT32(int_enabled, PL011State),
-+    }
+         VMSTATE_UINT32(int_level, PL011State),
-+
+-        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
-     /*
++        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
-      * Unlike the ARM ARM pseudocode, we don't need to check whether this
+         VMSTATE_UINT32(ilpr, PL011State),
-      * was an exception vector read from the vector table (which is always
+         VMSTATE_UINT32(ibrd, PL011State),
-@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
+         VMSTATE_UINT32(fbrd, PL011State),
              hit = true;
          }
 -        for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
 +        uint32_t bitmask;
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            bitmask = 0x1f;
 +        } else {
 +            bitmask = 0x3f;
 +            fi->level = 0;
 +        }
 +
 +        for (n = region_counter - 1; n >= 0; n--) {
              /* region search */
              /*
 -             * Note that the base address is bits [31:5] from the register
 -             * with bits [4:0] all zeroes, but the limit address is bits
 -             * [31:5] from the register with bits [4:0] all ones.
 +             * Note that the base address is bits [31:x] from the register
 +             * with bits [x-1:0] all zeroes, but the limit address is bits
 +             * [31:x] from the register with bits [x:0] all ones. Where x is
 +             * 5 for Cortex-M and 6 for Cortex-R
               */
 -            uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
 -            uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
 +            uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
 +            uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
 -            if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
 +            if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
                  /* Region disabled */
                  continue;
              }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                   * PMSAv7 where highest-numbered-region wins)
                   */
                  fi->type = ARMFault_Permission;
 -                fi->level = 1;
 +                if (arm_feature(env, ARM_FEATURE_M)) {
 +                    fi->level = 1;
 +                }
                  return true;
              }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      }
      if (!hit) {
 -        /* background fault */
 -        fi->type = ARMFault_Background;
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            fi->type = ARMFault_Background;
 +        } else {
 +            fi->type = ARMFault_Permission;
 +        }
          return true;
      }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
          /* hit using the background region */
          get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
      } else {
 -        uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
 -        uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
 +        uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
 +        uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
 +        uint32_t ap = extract32(matched_rbar, 1, 2);
 +        uint32_t xn = extract32(matched_rbar, 0, 1);
          bool pxn = false;
          if (arm_feature(env, ARM_FEATURE_V8_1M)) {
 -            pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
 +            pxn = extract32(matched_rlar, 4, 1);
          }
          if (m_is_system_region(env, address)) {
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
              xn = 1;
          }
 -        result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
 +        if (regime_el(env, mmu_idx) == 2) {
 +            result->f.prot = simple_ap_to_rw_prot_is_user(ap,
 +                                            mmu_idx != ARMMMUIdx_E2);
 +        } else {
 +            result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
 +        }
 +
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            uint8_t attrindx = extract32(matched_rlar, 1, 3);
 +            uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
 +            uint8_t sh = extract32(matched_rlar, 3, 2);
 +
 +            if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
 +                result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
 +                xn = 0x1;
 +            }
 +
 +            if ((regime_el(env, mmu_idx) == 1) &&
 +                regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
 +                pxn = 0x1;
 +            }
 +
 +            result->cacheattrs.is_s2_format = false;
 +            result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
 +            result->cacheattrs.shareability = sh;
 +        }
 +
          if (result->f.prot && !xn && !(pxn && !is_user)) {
              result->f.prot |= PAGE_EXEC;
          }
 -        /*
 -         * We don't need to look the attribute up in the MAIR0/MAIR1
 -         * registers because that only tells us about cacheability.
 -         */
 +
          if (mregion) {
              *mregion = matchregion;
          }
      }
      fi->type = ARMFault_Permission;
 -    fi->level = 1;
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        fi->level = 1;
 +    }
      return !(result->f.prot & (1 << access_type));
  }
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
      cacheattrs1 = result->cacheattrs;
      memset(result, 0, sizeof(*result));
 -    ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
 +    if (arm_feature(env, ARM_FEATURE_PMSA)) {
 +        ret = get_phys_addr_pmsav8(env, ipa, access_type,
 +                                   ptw->in_mmu_idx, is_secure, result, fi);
 +    } else {
 +        ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
 +                                 is_el0, result, fi);
 +    }
      fi->s2addr = ipa;
      /* Combine the S1 and S2 perms.  */
 --
-.25.1
+.34.1

-[PULL 32/34] i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
+[PULL 04/33] hw/char/pl011: add post_load hook for backwards-compatibility
-From: Jean-Christophe Dubois <jcd@tribudubois.net>
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
+Previous change slightly modified the way we handle data writes when
 FIFO is disabled. Previously we kept incrementing read_pos and were
 storing data at that position, although we only have a
 single-register-deep FIFO now. Then we changed it to always store data
 at pos 0.
-Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+If guest disables FIFO and the proceeds to read data, it will work out
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+fine, because we still read from current read_pos before setting it to
 .
 However, to make code less fragile, introduce a post_load hook for
 PL011State and move fixup read FIFO state when FIFO is disabled. Since
 we are introducing a post_load hook, also do some sanity checking on
 untrusted incoming input state.
 Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
 Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/timer/imx_gpt.h |  1 +
+ hw/char/pl011.c | 25 +++++++++++++++++++++++++
- hw/arm/fsl-imx6ul.c        |  2 +-
+file changed, 25 insertions(+)
  hw/misc/imx6ul_ccm.c       |  6 ------
  hw/timer/imx_gpt.c         | 25 +++++++++++++++++++++++++
 files changed, 27 insertions(+), 7 deletions(-)
-diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/imx_gpt.h
+--- a/hw/char/pl011.c
-+++ b/include/hw/timer/imx_gpt.h
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
  #define TYPE_IMX25_GPT "imx25.gpt"
  #define TYPE_IMX31_GPT "imx31.gpt"
  #define TYPE_IMX6_GPT "imx6.gpt"
 +#define TYPE_IMX6UL_GPT "imx6ul.gpt"
  #define TYPE_IMX7_GPT "imx7.gpt"
  #define TYPE_IMX_GPT TYPE_IMX25_GPT
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx6ul.c
 +++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
       */
      for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
          snprintf(name, NAME_SIZE, "gpt%d", i);
 -        object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
 +        object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
      }
-     /*
-diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/imx6ul_ccm.c
-+++ b/hw/misc/imx6ul_ccm.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
-     case CLK_32k:
-         freq = CKIL_FREQ;
-         break;
--    case CLK_HIGH:
--        freq = CKIH_FREQ;
--        break;
--    case CLK_HIGH_DIV:
--        freq = CKIH_FREQ / 8;
--        break;
-     default:
-         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
-                       TYPE_IMX6UL_CCM, __func__, clock);
-diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_gpt.c
-+++ b/hw/timer/imx_gpt.c
-@@ -XXX,XX +XXX,XX @@ static const IMXClk imx6_gpt_clocks[] = {
-     CLK_HIGH,      /* 111 reference clock */
  };
-+static const IMXClk imx6ul_gpt_clocks[] = {
++static int pl011_post_load(void *opaque, int version_id)
-+    CLK_NONE,      /* 000 No clock source */
++{
-+    CLK_IPG,       /* 001 ipg_clk, 532MHz*/
++    PL011State* s = opaque;
 +    CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
 +    CLK_EXT,       /* 011 External clock */
 +    CLK_32k,       /* 100 ipg_clk_32k */
 +    CLK_NONE,      /* 101 not defined */
 +    CLK_NONE,      /* 110 not defined */
 +    CLK_NONE,      /* 111 not defined */
 +};
 +
- static const IMXClk imx7_gpt_clocks[] = {
++    /* Sanity-check input state */
-     CLK_NONE,      /* 000 No clock source */
++    if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
-     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
++        s->read_count > ARRAY_SIZE(s->read_fifo)) {
-@@ -XXX,XX +XXX,XX @@ static void imx6_gpt_init(Object *obj)
++        return -1;
-     s->clocks = imx6_gpt_clocks;
++    }
  }
 +static void imx6ul_gpt_init(Object *obj)
 +{
 +    IMXGPTState *s = IMX_GPT(obj);
 +
-+    s->clocks = imx6ul_gpt_clocks;
++    if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
 +        /*
 +         * Older versions of PL011 didn't ensure that the single
 +         * character in the FIFO in FIFO-disabled mode is in
 +         * element 0 of the array; convert to follow the current
 +         * code's assumptions.
 +         */
 +        s->read_fifo[0] = s->read_fifo[s->read_pos];
 +        s->read_pos = 0;
 +    }
 +
 +    return 0;
 +}
 +
- static void imx7_gpt_init(Object *obj)
+ static const VMStateDescription vmstate_pl011 = {
- {
+     .name = "pl011",
-     IMXGPTState *s = IMX_GPT(obj);
+     .version_id = 2,
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx6_gpt_info = {
+     .minimum_version_id = 2,
-     .instance_init = imx6_gpt_init,
++    .post_load = pl011_post_load,
- };
+     .fields = (VMStateField[]) {
+         VMSTATE_UINT32(readbuff, PL011State),
-+static const TypeInfo imx6ul_gpt_info = {
+         VMSTATE_UINT32(flags, PL011State),
 +    .name = TYPE_IMX6UL_GPT,
 +    .parent = TYPE_IMX25_GPT,
 +    .instance_init = imx6ul_gpt_init,
 +};
 +
  static const TypeInfo imx7_gpt_info = {
      .name = TYPE_IMX7_GPT,
      .parent = TYPE_IMX25_GPT,
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_register_types(void)
      type_register_static(&imx25_gpt_info);
      type_register_static(&imx31_gpt_info);
      type_register_static(&imx6_gpt_info);
 +    type_register_static(&imx6ul_gpt_info);
      type_register_static(&imx7_gpt_info);
  }
 --
-.25.1
+.34.1

-[PULL 28/34] hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
+[PULL 05/33] hw/char/pl011: implement a reset method
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-This function is not used anywhere outside this file,
+PL011 currently lacks a reset method. Implement it.
 so we can make the function "static void".
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221216214924.4711-2-philmd@linaro.org
+Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/smmu-common.h | 3 ---
+ hw/char/pl011.c | 26 +++++++++++++++++++++-----
- hw/arm/smmu-common.c         | 2 +-
+file changed, 21 insertions(+), 5 deletions(-)
 files changed, 1 insertion(+), 4 deletions(-)
-diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/smmu-common.h
+--- a/hw/char/pl011.c
-+++ b/include/hw/arm/smmu-common.h
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
+@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
- /* Unmap the range of all the notifiers registered to any IOMMU mr */
+     s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
- void smmu_inv_notifiers_all(SMMUState *s);
+                                 ClockUpdate);
--/* Unmap the range of all the notifiers registered to @mr */
+-    s->read_trigger = 1;
--void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
+-    s->ifl = 0x12;
 -    s->cr = 0x300;
 -    s->flags = 0x90;
 -
- #endif /* HW_ARM_SMMU_COMMON_H */
+     s->id = pl011_id_arm;
 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/smmu-common.c
 +++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
  }
- /* Unmap all notifiers attached to @mr */
+@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
--inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
+                              pl011_event, NULL, s, NULL, true);
-+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
+ }
 +static void pl011_reset(DeviceState *dev)
 +{
 +    PL011State *s = PL011(dev);
 +
 +    s->lcr = 0;
 +    s->rsr = 0;
 +    s->dmacr = 0;
 +    s->int_enabled = 0;
 +    s->int_level = 0;
 +    s->ilpr = 0;
 +    s->ibrd = 0;
 +    s->fbrd = 0;
 +    s->read_pos = 0;
 +    s->read_count = 0;
 +    s->read_trigger = 1;
 +    s->ifl = 0x12;
 +    s->cr = 0x300;
 +    s->flags = 0x90;
 +}
 +
  static void pl011_class_init(ObjectClass *oc, void *data)
  {
-     IOMMUNotifier *n;
+     DeviceClass *dc = DEVICE_CLASS(oc);
      dc->realize = pl011_realize;
 +    dc->reset = pl011_reset;
      dc->vmsd = &vmstate_pl011;
      device_class_set_props(dc, pl011_properties);
  }
 --
-.25.1
+.34.1

-[PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0
+[PULL 06/33] hw/char/pl011: better handling of FIFO flags on LCR reset
-From: Axel Heider <axel.heider@hensoldt.net>
+From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+Current FIFO handling code does not reset RXFE/RXFF flags when guest
 resets FIFO by writing to UARTLCR register, although internal FIFO state
 is reset to 0 read count. Actual guest-visible flag update will happen
 only on next data read or write attempt. As a result of that any guest
 that expects RXFE flag to be set (and RXFF to be cleared) after resetting
 FIFO will never see that happen.
 Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/imx_epit.c | 20 ++++++++++++++------
+ hw/char/pl011.c | 18 +++++++++++++-----
-file changed, 14 insertions(+), 6 deletions(-)
+file changed, 13 insertions(+), 5 deletions(-)
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
+diff --git a/hw/char/pl011.c b/hw/char/pl011.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/hw/char/pl011.c
-+++ b/hw/timer/imx_epit.c
++++ b/hw/char/pl011.c
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
+@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
- /*
+     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
   * This is called both on hardware (device) reset and software reset.
   */
 -static void imx_epit_reset(DeviceState *dev)
 +static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
  {
 -    IMXEPITState *s = IMX_EPIT(dev);
 -
      /* Soft reset doesn't touch some bits; hard reset clears them */
 -    s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
 +    if (is_hard_reset) {
 +        s->cr = 0;
 +    } else {
 +        s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
 +    }
      s->sr = 0;
      s->lr = EPIT_TIMER_MAX;
      s->cmp = 0;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
          s->cr = value & 0x03ffffff;
          if (s->cr & CR_SWR) {
              /* handle the reset */
 -            imx_epit_reset(DEVICE(s));
 +            imx_epit_reset(s, false);
          }
          /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
      s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
  }
-+static void imx_epit_dev_reset(DeviceState *dev)
++static inline void pl011_reset_fifo(PL011State *s)
 +{
-+    IMXEPITState *s = IMX_EPIT(dev);
++    s->read_count = 0;
-+    imx_epit_reset(s, true);
++    s->read_pos = 0;
 +
 +    /* Reset FIFO flags */
 +    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
 +    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
 +}
 +
- static void imx_epit_class_init(ObjectClass *klass, void *data)
+ static uint64_t pl011_read(void *opaque, hwaddr offset,
                             unsigned size)
  {
-     DeviceClass *dc  = DEVICE_CLASS(klass);
+@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
+     case 11: /* UARTLCR_H */
-     dc->realize = imx_epit_realize;
+         /* Reset the FIFO state on FIFO enable or disable */
--    dc->reset = imx_epit_reset;
+         if ((s->lcr ^ value) & 0x10) {
-+    dc->reset = imx_epit_dev_reset;
+-            s->read_count = 0;
-     dc->vmsd = &vmstate_imx_timer_epit;
+-            s->read_pos = 0;
-     dc->desc = "i.MX periodic timer";
++            pl011_reset_fifo(s);
          }
          if ((s->lcr ^ value) & 0x1) {
              int break_enable = value & 0x1;
@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
      s->ilpr = 0;
      s->ibrd = 0;
      s->fbrd = 0;
 -    s->read_pos = 0;
 -    s->read_count = 0;
      s->read_trigger = 1;
      s->ifl = 0x12;
      s->cr = 0x300;
 -    s->flags = 0x90;
 +    s->flags = 0;
 +    pl011_reset_fifo(s);
  }
+ static void pl011_class_init(ObjectClass *oc, void *data)
 --
-.25.1
+.34.1

-[PULL 10/34] hw/timer/imx_epit: improve comments
+[PULL 07/33] hvf: arm: Add support for GICv3
-From: Axel Heider <axel.heider@hensoldt.net>
+From: Alexander Graf <agraf@csgraf.de>
-Fix typos, add background information
+We currently only support GICv2 emulation. To also support GICv3, we will
+need to pass a few system registers into their respective handler functions.
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
 This patch adds support for HVF to call into the TCG callbacks for GICv3
 system register handlers. This is safe because the GICv3 TCG code is generic
 as long as we limit ourselves to EL0 and EL1 - which are the only modes
 supported by HVF.
 To make sure nobody trips over that, we also annotate callbacks that don't
 work in HVF mode, such as EL state change hooks.
 With GICv3 support in place, we can run with more than 8 vCPUs.
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Message-id: 20230128224459.70676-1-agraf@csgraf.de
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/imx_epit.c | 20 ++++++++++++++++----
+ hw/intc/arm_gicv3_cpuif.c   |  16 +++-
-file changed, 16 insertions(+), 4 deletions(-)
+ target/arm/hvf/hvf.c        | 151 ++++++++++++++++++++++++++++++++++++
+ target/arm/hvf/trace-events |   2 +
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
+files changed, 168 insertions(+), 1 deletion(-)
 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/timer/imx_epit.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
+@@ -XXX,XX +XXX,XX @@
  #include "hw/irq.h"
  #include "cpu.h"
  #include "target/arm/cpregs.h"
 +#include "sysemu/tcg.h"
 +#include "sysemu/qtest.h"
  /*
   * Special case return value from hppvi_index(); must be larger than
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
           * which case we'd get the wrong value.
           * So instead we define the regs with no ri->opaque info, and
           * get back to the GICv3CPUState from the CPUARMState.
 +         *
 +         * These CP regs callbacks can be called from either TCG or HVF code.
           */
          define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                  define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
              }
          }
 -        arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
 +        if (tcg_enabled() || qtest_enabled()) {
 +            /*
 +             * We can only trap EL changes with TCG. However the GIC interrupt
 +             * state only changes on EL changes involving EL2 or EL3, so for
 +             * the non-TCG case this is OK, as EL2 and EL3 can't exist.
 +             */
 +            arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
 +        } else {
 +            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
 +            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
 +        }
      }
  }
+diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
-+/*
+index XXXXXXX..XXXXXXX 100644
-+ * This is called both on hardware (device) reset and software reset.
+--- a/target/arm/hvf/hvf.c
-+ */
++++ b/target/arm/hvf/hvf.c
- static void imx_epit_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@
  #define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
  #define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
 +#define SYSREG_ICC_AP0R0_EL1     SYSREG(3, 0, 12, 8, 4)
 +#define SYSREG_ICC_AP0R1_EL1     SYSREG(3, 0, 12, 8, 5)
 +#define SYSREG_ICC_AP0R2_EL1     SYSREG(3, 0, 12, 8, 6)
 +#define SYSREG_ICC_AP0R3_EL1     SYSREG(3, 0, 12, 8, 7)
 +#define SYSREG_ICC_AP1R0_EL1     SYSREG(3, 0, 12, 9, 0)
 +#define SYSREG_ICC_AP1R1_EL1     SYSREG(3, 0, 12, 9, 1)
 +#define SYSREG_ICC_AP1R2_EL1     SYSREG(3, 0, 12, 9, 2)
 +#define SYSREG_ICC_AP1R3_EL1     SYSREG(3, 0, 12, 9, 3)
 +#define SYSREG_ICC_ASGI1R_EL1    SYSREG(3, 0, 12, 11, 6)
 +#define SYSREG_ICC_BPR0_EL1      SYSREG(3, 0, 12, 8, 3)
 +#define SYSREG_ICC_BPR1_EL1      SYSREG(3, 0, 12, 12, 3)
 +#define SYSREG_ICC_CTLR_EL1      SYSREG(3, 0, 12, 12, 4)
 +#define SYSREG_ICC_DIR_EL1       SYSREG(3, 0, 12, 11, 1)
 +#define SYSREG_ICC_EOIR0_EL1     SYSREG(3, 0, 12, 8, 1)
 +#define SYSREG_ICC_EOIR1_EL1     SYSREG(3, 0, 12, 12, 1)
 +#define SYSREG_ICC_HPPIR0_EL1    SYSREG(3, 0, 12, 8, 2)
 +#define SYSREG_ICC_HPPIR1_EL1    SYSREG(3, 0, 12, 12, 2)
 +#define SYSREG_ICC_IAR0_EL1      SYSREG(3, 0, 12, 8, 0)
 +#define SYSREG_ICC_IAR1_EL1      SYSREG(3, 0, 12, 12, 0)
 +#define SYSREG_ICC_IGRPEN0_EL1   SYSREG(3, 0, 12, 12, 6)
 +#define SYSREG_ICC_IGRPEN1_EL1   SYSREG(3, 0, 12, 12, 7)
 +#define SYSREG_ICC_PMR_EL1       SYSREG(3, 0, 4, 6, 0)
 +#define SYSREG_ICC_RPR_EL1       SYSREG(3, 0, 12, 11, 3)
 +#define SYSREG_ICC_SGI0R_EL1     SYSREG(3, 0, 12, 11, 7)
 +#define SYSREG_ICC_SGI1R_EL1     SYSREG(3, 0, 12, 11, 5)
 +#define SYSREG_ICC_SRE_EL1       SYSREG(3, 0, 12, 12, 5)
 +
  #define WFX_IS_WFE (1 << 0)
  #define TMR_CTL_ENABLE  (1 << 0)
@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
             SYSREG_CRM(reg) < 8;
  }
 +static uint32_t hvf_reg2cp_reg(uint32_t reg)
 +{
 +    return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
 +                              (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
 +                              (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
 +                              (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
 +                              (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
 +                              (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
 +}
 +
 +static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
 +{
 +    ARMCPU *arm_cpu = ARM_CPU(cpu);
 +    CPUARMState *env = &arm_cpu->env;
 +    const ARMCPRegInfo *ri;
 +
 +    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
 +    if (ri) {
 +        if (ri->accessfn) {
 +            if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
 +                return false;
 +            }
 +        }
 +        if (ri->type & ARM_CP_CONST) {
 +            *val = ri->resetvalue;
 +        } else if (ri->readfn) {
 +            *val = ri->readfn(env, ri);
 +        } else {
 +            *val = CPREG_FIELD64(env, ri);
 +        }
 +        trace_hvf_vgic_read(ri->name, *val);
 +        return true;
 +    }
 +
 +    return false;
 +}
 +
  static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
  {
-     IMXEPITState *s = IMX_EPIT(dev);
+     ARMCPU *arm_cpu = ARM_CPU(cpu);
+@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
--    /*
+     case SYSREG_OSDLR_EL1:
--     * Soft reset doesn't touch some bits; hard reset clears them
+         /* Dummy register */
 -     */
 +    /* Soft reset doesn't touch some bits; hard reset clears them */
      s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
      s->sr = 0;
      s->lr = EPIT_TIMER_MAX;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
          ptimer_transaction_begin(s->timer_cmp);
          ptimer_transaction_begin(s->timer_reload);
 +        /* Update the frequency. Has been done already in case of a reset. */
          if (!(s->cr & CR_SWR)) {
              imx_epit_set_freq(s);
          }
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
          break;
++    case SYSREG_ICC_AP0R0_EL1:
-     case 1: /* SR - ACK*/
++    case SYSREG_ICC_AP0R1_EL1:
--        /* writing 1 to OCIF clear the OCIF bit */
++    case SYSREG_ICC_AP0R2_EL1:
-+        /* writing 1 to OCIF clears the OCIF bit */
++    case SYSREG_ICC_AP0R3_EL1:
-         if (value & 0x01) {
++    case SYSREG_ICC_AP1R0_EL1:
-             s->sr = 0;
++    case SYSREG_ICC_AP1R1_EL1:
-             imx_epit_update_int(s);
++    case SYSREG_ICC_AP1R2_EL1:
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
++    case SYSREG_ICC_AP1R3_EL1:
-x00001000);
++    case SYSREG_ICC_ASGI1R_EL1:
-     sysbus_init_mmio(sbd, &s->iomem);
++    case SYSREG_ICC_BPR0_EL1:
++    case SYSREG_ICC_BPR1_EL1:
-+    /*
++    case SYSREG_ICC_DIR_EL1:
-+     * The reload timer keeps running when the peripheral is enabled. It is a
++    case SYSREG_ICC_EOIR0_EL1:
-+     * kind of wall clock that does not generate any interrupts. The callback
++    case SYSREG_ICC_EOIR1_EL1:
-+     * needs to be provided, but it does nothing as the ptimer already supports
++    case SYSREG_ICC_HPPIR0_EL1:
-+     * all necessary reloading functionality.
++    case SYSREG_ICC_HPPIR1_EL1:
-+     */
++    case SYSREG_ICC_IAR0_EL1:
-     s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
++    case SYSREG_ICC_IAR1_EL1:
++    case SYSREG_ICC_IGRPEN0_EL1:
-+    /*
++    case SYSREG_ICC_IGRPEN1_EL1:
-+     * The compare timer is running only when the peripheral configuration is
++    case SYSREG_ICC_PMR_EL1:
-+     * in a state that will generate compare interrupts.
++    case SYSREG_ICC_SGI0R_EL1:
-+     */
++    case SYSREG_ICC_SGI1R_EL1:
-     s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
++    case SYSREG_ICC_SRE_EL1:
 +    case SYSREG_ICC_CTLR_EL1:
 +        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
 +        if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
 +            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
 +        }
 +        break;
      default:
          if (is_id_sysreg(reg)) {
              /* ID system registers read as RES0 */
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
      }
  }
++static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
++{
++    ARMCPU *arm_cpu = ARM_CPU(cpu);
++    CPUARMState *env = &arm_cpu->env;
++    const ARMCPRegInfo *ri;
++
++    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
++
++    if (ri) {
++        if (ri->accessfn) {
++            if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
++                return false;
++            }
++        }
++        if (ri->writefn) {
++            ri->writefn(env, ri, val);
++        } else {
++            CPREG_FIELD64(env, ri) = val;
++        }
++
++        trace_hvf_vgic_write(ri->name, val);
++        return true;
++    }
++
++    return false;
++}
++
+ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
+ {
+     ARMCPU *arm_cpu = ARM_CPU(cpu);
+@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
+     case SYSREG_OSDLR_EL1:
+         /* Dummy register */
+         break;
++    case SYSREG_ICC_AP0R0_EL1:
++    case SYSREG_ICC_AP0R1_EL1:
++    case SYSREG_ICC_AP0R2_EL1:
++    case SYSREG_ICC_AP0R3_EL1:
++    case SYSREG_ICC_AP1R0_EL1:
++    case SYSREG_ICC_AP1R1_EL1:
++    case SYSREG_ICC_AP1R2_EL1:
++    case SYSREG_ICC_AP1R3_EL1:
++    case SYSREG_ICC_ASGI1R_EL1:
++    case SYSREG_ICC_BPR0_EL1:
++    case SYSREG_ICC_BPR1_EL1:
++    case SYSREG_ICC_CTLR_EL1:
++    case SYSREG_ICC_DIR_EL1:
++    case SYSREG_ICC_EOIR0_EL1:
++    case SYSREG_ICC_EOIR1_EL1:
++    case SYSREG_ICC_HPPIR0_EL1:
++    case SYSREG_ICC_HPPIR1_EL1:
++    case SYSREG_ICC_IAR0_EL1:
++    case SYSREG_ICC_IAR1_EL1:
++    case SYSREG_ICC_IGRPEN0_EL1:
++    case SYSREG_ICC_IGRPEN1_EL1:
++    case SYSREG_ICC_PMR_EL1:
++    case SYSREG_ICC_SGI0R_EL1:
++    case SYSREG_ICC_SGI1R_EL1:
++    case SYSREG_ICC_SRE_EL1:
++        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
++        if (!hvf_sysreg_write_cp(cpu, reg, val)) {
++            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
++        }
++        break;
+     default:
+         cpu_synchronize_state(cpu);
+         trace_hvf_unhandled_sysreg_write(env->pc, reg,
+diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/hvf/trace-events
++++ b/target/arm/hvf/trace-events
+@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
+ hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
+ hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
+ hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
++hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
++hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
 --
-.25.1
+.34.1

-[PULL 17/34] hw/timer/imx_epit: fix compare timer handling
+[PULL 08/33] hw/arm/virt: Consolidate GIC finalize logic
-From: Axel Heider <axel.heider@hensoldt.net>
+From: Alexander Graf <agraf@csgraf.de>
-- fix #1263 for CR writes
+Up to now, the finalize_gic_version() code open coded what is essentially
-- rework compare time handling
+a support bitmap match between host/emulation environment and desired
-  - The compare timer has to run even if CR.OCIEN is not set,
+target GIC type.
-    as SR.OCIF must be updated.
-  - The compare timer fires exactly once when the
+This open coding leads to undesirable side effects. For example, a VM with
-    compare value is less than the current value, but the
+KVM and -smp 10 will automatically choose GICv3 while the same command
-    reload values is less than the compare value.
+line with TCG will stay on GICv2 and fail the launch.
-  - The compare timer will never fire if the reload value is
-    less than the compare value. Disable it in this case.
+This patch combines the TCG and KVM matching code paths by making
+everything a 2 pass process. First, we determine which GIC versions the
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+current environment is able to support, then we go through a single
-[PMM: fixed minor style nits]
+state machine to determine which target GIC mode that means for us.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 After this patch, the only user noticable changes should be consolidated
 error messages as well as TCG -M virt supporting -smp > 8 automatically.
 Signed-off-by: Alexander Graf <agraf@csgraf.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
 Message-id: 20221223090107.98888-2-agraf@csgraf.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------
+ include/hw/arm/virt.h |  15 ++--
-file changed, 116 insertions(+), 76 deletions(-)
+ hw/arm/virt.c         | 198 ++++++++++++++++++++++--------------------
+files changed, 112 insertions(+), 101 deletions(-)
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/include/hw/arm/virt.h
-+++ b/hw/timer/imx_epit.c
++++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
-  * Originally written by Hans Jiang
+ } VirtMSIControllerType;
-  * Updated by Peter Chubb
-  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ typedef enum VirtGICType {
-+ * Updated by Axel Heider
+-    VIRT_GIC_VERSION_MAX,
-  *
+-    VIRT_GIC_VERSION_HOST,
-  * This code is licensed under GPL version 2 or later.  See
+-    VIRT_GIC_VERSION_2,
-  * the COPYING file in the top-level directory.
+-    VIRT_GIC_VERSION_3,
-@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
+-    VIRT_GIC_VERSION_4,
-     return reg_value;
++    VIRT_GIC_VERSION_MAX = 0,
 +    VIRT_GIC_VERSION_HOST = 1,
 +    /* The concrete GIC values have to match the GIC version number */
 +    VIRT_GIC_VERSION_2 = 2,
 +    VIRT_GIC_VERSION_3 = 3,
 +    VIRT_GIC_VERSION_4 = 4,
      VIRT_GIC_VERSION_NOSEL,
  } VirtGICType;
 +#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
 +#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
 +#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
 +
  struct VirtMachineClass {
      MachineClass parent;
      bool disallow_affinity_adjustment;
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
      }
  }
--/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
++static VirtGICType finalize_gic_version_do(const char *accel_name,
--static void imx_epit_reload_compare_timer(IMXEPITState *s)
++                                           VirtGICType gic_version,
-+/*
++                                           int gics_supported,
-+ * Must be called from a ptimer_transaction_begin/commit block for
++                                           unsigned int max_cpus)
-+ * s->timer_cmp, but outside of a transaction block of s->timer_reload,
++{
-+ * so the proper counter value is read.
++    /* Convert host/max/nosel to GIC version number */
-+ */
++    switch (gic_version) {
-+static void imx_epit_update_compare_timer(IMXEPITState *s)
++    case VIRT_GIC_VERSION_HOST:
 +        if (!kvm_enabled()) {
 +            error_report("gic-version=host requires KVM");
 +            exit(1);
 +        }
 +
 +        /* For KVM, gic-version=host means gic-version=max */
 +        return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
 +                                       gics_supported, max_cpus);
 +    case VIRT_GIC_VERSION_MAX:
 +        if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
 +            gic_version = VIRT_GIC_VERSION_4;
 +        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
 +            gic_version = VIRT_GIC_VERSION_3;
 +        } else {
 +            gic_version = VIRT_GIC_VERSION_2;
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_NOSEL:
 +        if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
 +            max_cpus <= GIC_NCPU) {
 +            gic_version = VIRT_GIC_VERSION_2;
 +        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
 +            /*
 +             * in case the host does not support v2 emulation or
 +             * the end-user requested more than 8 VCPUs we now default
 +             * to v3. In any case defaulting to v2 would be broken.
 +             */
 +            gic_version = VIRT_GIC_VERSION_3;
 +        } else if (max_cpus > GIC_NCPU) {
 +            error_report("%s only supports GICv2 emulation but more than 8 "
 +                         "vcpus are requested", accel_name);
 +            exit(1);
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_2:
 +    case VIRT_GIC_VERSION_3:
 +    case VIRT_GIC_VERSION_4:
 +        break;
 +    }
 +
 +    /* Check chosen version is effectively supported */
 +    switch (gic_version) {
 +    case VIRT_GIC_VERSION_2:
 +        if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
 +            error_report("%s does not support GICv2 emulation", accel_name);
 +            exit(1);
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_3:
 +        if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
 +            error_report("%s does not support GICv3 emulation", accel_name);
 +            exit(1);
 +        }
 +        break;
 +    case VIRT_GIC_VERSION_4:
 +        if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
 +            error_report("%s does not support GICv4 emulation, is virtualization=on?",
 +                         accel_name);
 +            exit(1);
 +        }
 +        break;
 +    default:
 +        error_report("logic error in finalize_gic_version");
 +        exit(1);
 +        break;
 +    }
 +
 +    return gic_version;
 +}
 +
  /*
   * finalize_gic_version - Determines the final gic_version
   * according to the gic-version property
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
   */
  static void finalize_gic_version(VirtMachineState *vms)
  {
--    if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN))  {
++    const char *accel_name = current_accel_name();
--        /* if the compare feature is on and timers are running */
+     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
--        uint32_t tmp = ptimer_get_count(s->timer_reload);
++    int gics_supported = 0;
--        uint64_t next;
--        if (tmp > s->cmp) {
+-    if (kvm_enabled()) {
--            /* It'll fire in this round of the timer */
+-        int probe_bitmap;
--            next = tmp - s->cmp;
++    /* Determine which GIC versions the current environment supports */
--        } else { /* catch it next time around */
++    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
--            next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
++        int probe_bitmap = kvm_arm_vgic_probe();
-+    uint64_t counter = 0;
-+    bool is_oneshot = false;
+-        if (!kvm_irqchip_in_kernel()) {
-+    /*
+-            switch (vms->gic_version) {
-+     * The compare timer only has to run if the timer peripheral is active
+-            case VIRT_GIC_VERSION_HOST:
-+     * and there is an input clock, Otherwise it can be switched off.
+-                warn_report(
-+     */
+-                    "gic-version=host not relevant with kernel-irqchip=off "
-+    bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
+-                     "as only userspace GICv2 is supported. Using v2 ...");
-+    if (is_active) {
+-                return;
-+        /*
+-            case VIRT_GIC_VERSION_MAX:
-+         * Calculate next timeout for compare timer. Reading the reload
+-            case VIRT_GIC_VERSION_NOSEL:
-+         * counter returns proper results only if pending transactions
+-                vms->gic_version = VIRT_GIC_VERSION_2;
-+         * on it are committed here. Otherwise stale values are be read.
+-                return;
-+         */
+-            case VIRT_GIC_VERSION_2:
-+        counter = ptimer_get_count(s->timer_reload);
+-                return;
-+        uint64_t limit = ptimer_get_limit(s->timer_cmp);
+-            case VIRT_GIC_VERSION_3:
-+        /*
+-                error_report(
-+         * The compare timer is a periodic timer if the limit is at least
+-                    "gic-version=3 is not supported with kernel-irqchip=off");
-+         * the compare value. Otherwise it may fire at most once in the
+-                exit(1);
-+         * current round.
+-            case VIRT_GIC_VERSION_4:
-+         */
+-                error_report(
-+        bool is_oneshot = (limit >= s->cmp);
+-                    "gic-version=4 is not supported with kernel-irqchip=off");
-+        if (counter >= s->cmp) {
+-                exit(1);
 +            /* The compare timer fires in the current round. */
 +            counter -= s->cmp;
 +        } else if (!is_oneshot) {
 +            /*
 +             * The compare timer fires after a reload, as it is below the
 +             * compare value already in this round. Note that the counter
 +             * value calculated below can be above the 32-bit limit, which
 +             * is legal here because the compare timer is an internal
 +             * helper ptimer only.
 +             */
 +            counter += limit - s->cmp;
 +        } else {
 +            /*
 +             * The compare timer won't fire in this round, and the limit is
 +             * set to a value below the compare value. This practically means
 +             * it will never fire, so it can be switched off.
 +             */
 +            is_active = false;
          }
 -        ptimer_set_count(s->timer_cmp, next);
      }
 +
 +    /*
 +     * Set the compare timer and let it run, or stop it. This is agnostic
 +     * of CR.OCIEN bit, as this bit affects interrupt generation only. The
 +     * compare timer needs to run even if no interrupts are to be generated,
 +     * because the SR.OCIF bit must be updated also.
 +     * Note that the timer might already be stopped or be running with
 +     * counter values. However, finding out when an update is needed and
 +     * when not is not trivial. It's much easier applying the setting again,
 +     * as this does not harm either and the overhead is negligible.
 +     */
 +    if (is_active) {
 +        ptimer_set_count(s->timer_cmp, counter);
 +        ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
 +    } else {
 +        ptimer_stop(s->timer_cmp);
 +    }
 +
  }
  static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
  {
 -    uint32_t freq = 0;
      uint32_t oldcr = s->cr;
      s->cr = value & 0x03ffffff;
      if (s->cr & CR_SWR) {
 -        /* handle the reset */
 +        /*
 +         * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
 +         * are still stopped because the input clock is disabled.
 +         */
          imx_epit_reset(s, false);
 +    } else {
 +        uint32_t freq;
 +        uint32_t toggled_cr_bits = oldcr ^ s->cr;
 +        /* re-initialize the limits if CR.RLD has changed */
 +        bool set_limit = toggled_cr_bits & CR_RLD;
 +        /* set the counter if the timer got just enabled and CR.ENMOD is set */
 +        bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
 +        bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
 +
 +        ptimer_transaction_begin(s->timer_cmp);
 +        ptimer_transaction_begin(s->timer_reload);
 +        freq = imx_epit_get_freq(s);
 +        if (freq) {
 +            ptimer_set_freq(s->timer_reload, freq);
 +            ptimer_set_freq(s->timer_cmp, freq);
 +        }
 +
 +        if (set_limit || set_counter) {
 +            uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
 +            ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
 +            if (set_limit) {
 +                ptimer_set_limit(s->timer_cmp, limit, 0);
 +            }
 +        }
 +        /*
 +         * If there is an input clock and the peripheral is enabled, then
 +         * ensure the wall clock timer is ticking. Otherwise stop the timers.
 +         * The compare timer will be updated later.
 +         */
 +        if (freq && (s->cr & CR_EN)) {
 +            ptimer_run(s->timer_reload, 0);
 +        } else {
 +            ptimer_stop(s->timer_reload);
 +        }
 +        /* Commit changes to reload timer, so they can propagate. */
 +        ptimer_transaction_commit(s->timer_reload);
 +        /* Update compare timer based on the committed reload timer value. */
 +        imx_epit_update_compare_timer(s);
 +        ptimer_transaction_commit(s->timer_cmp);
      }
      /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
       * - write to CR.EN or CR.OCIE
       */
      imx_epit_update_int(s);
 -
 -    /*
 -     * TODO: could we 'break' here for reset? following operations appear
 -     * to duplicate the work imx_epit_reset() already did.
 -     */
 -
 -    ptimer_transaction_begin(s->timer_cmp);
 -    ptimer_transaction_begin(s->timer_reload);
 -
 -    /*
 -     * Update the frequency. In case of a reset the input clock was
 -     * switched off, so this can be skipped.
 -     */
 -    if (!(s->cr & CR_SWR)) {
 -        freq = imx_epit_get_freq(s);
 -        if (freq) {
 -            ptimer_set_freq(s->timer_reload, freq);
 -            ptimer_set_freq(s->timer_cmp, freq);
 -        }
 -    }
 -
 -    if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
 -        if (s->cr & CR_ENMOD) {
 -            if (s->cr & CR_RLD) {
 -                ptimer_set_limit(s->timer_reload, s->lr, 1);
 -                ptimer_set_limit(s->timer_cmp, s->lr, 1);
 -            } else {
 -                ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
 -                ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
 -            }
 -        }
 -
--        imx_epit_reload_compare_timer(s);
+-        probe_bitmap = kvm_arm_vgic_probe();
--        ptimer_run(s->timer_reload, 0);
+         if (!probe_bitmap) {
--        if (s->cr & CR_OCIEN) {
+             error_report("Unable to determine GIC version supported by host");
--            ptimer_run(s->timer_cmp, 0);
+             exit(1);
--        } else {
+         }
--            ptimer_stop(s->timer_cmp);
--        }
+-        switch (vms->gic_version) {
--    } else if (!(s->cr & CR_EN)) {
+-        case VIRT_GIC_VERSION_HOST:
--        /* stop both timers */
+-        case VIRT_GIC_VERSION_MAX:
--        ptimer_stop(s->timer_reload);
+-            if (probe_bitmap & KVM_ARM_VGIC_V3) {
--        ptimer_stop(s->timer_cmp);
+-                vms->gic_version = VIRT_GIC_VERSION_3;
--    } else  if (s->cr & CR_OCIEN) {
+-            } else {
--        if (!(oldcr & CR_OCIEN)) {
+-                vms->gic_version = VIRT_GIC_VERSION_2;
--            imx_epit_reload_compare_timer(s);
+-            }
--            ptimer_run(s->timer_cmp, 0);
+-            return;
--        }
+-        case VIRT_GIC_VERSION_NOSEL:
--    } else {
+-            if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
--        ptimer_stop(s->timer_cmp);
+-                vms->gic_version = VIRT_GIC_VERSION_2;
 -            } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
 -                /*
 -                 * in case the host does not support v2 in-kernel emulation or
 -                 * the end-user requested more than 8 VCPUs we now default
 -                 * to v3. In any case defaulting to v2 would be broken.
 -                 */
 -                vms->gic_version = VIRT_GIC_VERSION_3;
 -            } else if (max_cpus > GIC_NCPU) {
 -                error_report("host only supports in-kernel GICv2 emulation "
 -                             "but more than 8 vcpus are requested");
 -                exit(1);
 -            }
 -            break;
 -        case VIRT_GIC_VERSION_2:
 -        case VIRT_GIC_VERSION_3:
 -            break;
 -        case VIRT_GIC_VERSION_4:
 -            error_report("gic-version=4 is not supported with KVM");
 -            exit(1);
 +        if (probe_bitmap & KVM_ARM_VGIC_V2) {
 +            gics_supported |= VIRT_GIC_VERSION_2_MASK;
          }
 -
 -        /* Check chosen version is effectively supported by the host */
 -        if (vms->gic_version == VIRT_GIC_VERSION_2 &&
 -            !(probe_bitmap & KVM_ARM_VGIC_V2)) {
 -            error_report("host does not support in-kernel GICv2 emulation");
 -            exit(1);
 -        } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
 -                   !(probe_bitmap & KVM_ARM_VGIC_V3)) {
 -            error_report("host does not support in-kernel GICv3 emulation");
 -            exit(1);
 +        if (probe_bitmap & KVM_ARM_VGIC_V3) {
 +            gics_supported |= VIRT_GIC_VERSION_3_MASK;
          }
 -        return;
 -    }
 -
--    ptimer_transaction_commit(s->timer_cmp);
+-    /* TCG mode */
--    ptimer_transaction_commit(s->timer_reload);
+-    switch (vms->gic_version) {
 -    case VIRT_GIC_VERSION_NOSEL:
 -        vms->gic_version = VIRT_GIC_VERSION_2;
 -        break;
 -    case VIRT_GIC_VERSION_MAX:
 +    } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
 +        /* KVM w/o kernel irqchip can only deal with GICv2 */
 +        gics_supported |= VIRT_GIC_VERSION_2_MASK;
 +        accel_name = "KVM with kernel-irqchip=off";
 +    } else {
 +        gics_supported |= VIRT_GIC_VERSION_2_MASK;
          if (module_object_class_by_name("arm-gicv3")) {
 -            /* CONFIG_ARM_GICV3_TCG was set */
 +            gics_supported |= VIRT_GIC_VERSION_3_MASK;
              if (vms->virt) {
                  /* GICv4 only makes sense if CPU has EL2 */
 -                vms->gic_version = VIRT_GIC_VERSION_4;
 -            } else {
 -                vms->gic_version = VIRT_GIC_VERSION_3;
 +                gics_supported |= VIRT_GIC_VERSION_4_MASK;
              }
 -        } else {
 -            vms->gic_version = VIRT_GIC_VERSION_2;
          }
 -        break;
 -    case VIRT_GIC_VERSION_HOST:
 -        error_report("gic-version=host requires KVM");
 -        exit(1);
 -    case VIRT_GIC_VERSION_4:
 -        if (!vms->virt) {
 -            error_report("gic-version=4 requires virtualization enabled");
 -            exit(1);
 -        }
 -        break;
 -    case VIRT_GIC_VERSION_2:
 -    case VIRT_GIC_VERSION_3:
 -        break;
      }
 +
 +    /*
 +     * Then convert helpers like host/max to concrete GIC versions and ensure
 +     * the desired version is supported
 +     */
 +    vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
 +                                               gics_supported, max_cpus);
  }
- static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
+ /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
          /* If IOVW bit is set then set the timer value */
          ptimer_set_count(s->timer_reload, s->lr);
      }
 -    /*
 -     * Commit the change to s->timer_reload, so it can propagate. Otherwise
 -     * the timer interrupt may not fire properly. The commit must happen
 -     * before calling imx_epit_reload_compare_timer(), which reads
 -     * s->timer_reload internally again.
 -     */
 +    /* Commit the changes to s->timer_reload, so they can propagate. */
      ptimer_transaction_commit(s->timer_reload);
 -    imx_epit_reload_compare_timer(s);
 +    /* Update the compare timer based on the committed reload timer value. */
 +    imx_epit_update_compare_timer(s);
      ptimer_transaction_commit(s->timer_cmp);
  }
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
  {
      s->cmp = value;
 +    /* Update the compare timer based on the committed reload timer value. */
      ptimer_transaction_begin(s->timer_cmp);
 -    imx_epit_reload_compare_timer(s);
 +    imx_epit_update_compare_timer(s);
      ptimer_transaction_commit(s->timer_cmp);
  }
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
  {
      IMXEPITState *s = IMX_EPIT(opaque);
 +    /* The cmp ptimer can't be running when the peripheral is disabled */
 +    assert(s->cr & CR_EN);
 +
      DPRINTF("sr was %d\n", s->sr);
      /* Set interrupt status bit SR.OCIF and update the interrupt state */
      s->sr |= SR_OCIF;
 --
-.25.1
+.34.1

-[PULL 33/34] i.MX7D: Connect IRQs to GPIO devices.
+[PULL 09/33] hw/arm/virt: Make accels in GIC finalize logic explicit
-From: Jean-Christophe Dubois <jcd@tribudubois.net>
+From: Alexander Graf <agraf@csgraf.de>
-IRQs were not associated to the various GPIO devices inside i.MX7D.
+Let's explicitly list out all accelerators that we support when trying to
-This patch brings the i.MX7D on par with i.MX6.
+determine the supported set of GIC versions. KVM was already separate, so
 the only missing one is HVF which simply reuses all of TCG's emulation
 code and thus has the same compatibility matrix.
-Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Signed-off-by: Alexander Graf <agraf@csgraf.de>
-Message-id: 20221226101418.415170-1-jcd@tribudubois.net
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20221223090107.98888-3-agraf@csgraf.de
 [PMM: Added qtest to the list of accelerators]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx7.h | 15 +++++++++++++++
+ hw/arm/virt.c | 7 ++++++-
- hw/arm/fsl-imx7.c         | 31 ++++++++++++++++++++++++++++++-
+file changed, 6 insertions(+), 1 deletion(-)
 files changed, 45 insertions(+), 1 deletion(-)
-diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx7.h
+--- a/hw/arm/virt.c
-+++ b/include/hw/arm/fsl-imx7.h
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
+@@ -XXX,XX +XXX,XX @@
-     FSL_IMX7_GPT3_IRQ     = 53,
+ #include "sysemu/numa.h"
-     FSL_IMX7_GPT4_IRQ     = 52,
+ #include "sysemu/runstate.h"
+ #include "sysemu/tpm.h"
-+    FSL_IMX7_GPIO1_LOW_IRQ  = 64,
++#include "sysemu/tcg.h"
-+    FSL_IMX7_GPIO1_HIGH_IRQ = 65,
+ #include "sysemu/kvm.h"
-+    FSL_IMX7_GPIO2_LOW_IRQ  = 66,
+ #include "sysemu/hvf.h"
-+    FSL_IMX7_GPIO2_HIGH_IRQ = 67,
++#include "sysemu/qtest.h"
-+    FSL_IMX7_GPIO3_LOW_IRQ  = 68,
+ #include "hw/loader.h"
-+    FSL_IMX7_GPIO3_HIGH_IRQ = 69,
+ #include "qapi/error.h"
-+    FSL_IMX7_GPIO4_LOW_IRQ  = 70,
+ #include "qemu/bitops.h"
-+    FSL_IMX7_GPIO4_HIGH_IRQ = 71,
+@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
-+    FSL_IMX7_GPIO5_LOW_IRQ  = 72,
+         /* KVM w/o kernel irqchip can only deal with GICv2 */
-+    FSL_IMX7_GPIO5_HIGH_IRQ = 73,
+         gics_supported |= VIRT_GIC_VERSION_2_MASK;
-+    FSL_IMX7_GPIO6_LOW_IRQ  = 74,
+         accel_name = "KVM with kernel-irqchip=off";
-+    FSL_IMX7_GPIO6_HIGH_IRQ = 75,
+-    } else {
-+    FSL_IMX7_GPIO7_LOW_IRQ  = 76,
++    } else if (tcg_enabled() || hvf_enabled() || qtest_enabled())  {
-+    FSL_IMX7_GPIO7_HIGH_IRQ = 77,
+         gics_supported |= VIRT_GIC_VERSION_2_MASK;
-+
+         if (module_object_class_by_name("arm-gicv3")) {
-     FSL_IMX7_WDOG1_IRQ    = 78,
+             gics_supported |= VIRT_GIC_VERSION_3_MASK;
-     FSL_IMX7_WDOG2_IRQ    = 79,
+@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
-     FSL_IMX7_WDOG3_IRQ    = 10,
+                 gics_supported |= VIRT_GIC_VERSION_4_MASK;
-diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
+             }
-index XXXXXXX..XXXXXXX 100644
+         }
---- a/hw/arm/fsl-imx7.c
++    } else {
-+++ b/hw/arm/fsl-imx7.c
++        error_report("Unsupported accelerator, can not determine GIC support");
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
++        exit(1);
              FSL_IMX7_GPIO7_ADDR,
          };
 +        static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
 +            FSL_IMX7_GPIO1_LOW_IRQ,
 +            FSL_IMX7_GPIO2_LOW_IRQ,
 +            FSL_IMX7_GPIO3_LOW_IRQ,
 +            FSL_IMX7_GPIO4_LOW_IRQ,
 +            FSL_IMX7_GPIO5_LOW_IRQ,
 +            FSL_IMX7_GPIO6_LOW_IRQ,
 +            FSL_IMX7_GPIO7_LOW_IRQ,
 +        };
 +
 +        static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
 +            FSL_IMX7_GPIO1_HIGH_IRQ,
 +            FSL_IMX7_GPIO2_HIGH_IRQ,
 +            FSL_IMX7_GPIO3_HIGH_IRQ,
 +            FSL_IMX7_GPIO4_HIGH_IRQ,
 +            FSL_IMX7_GPIO5_HIGH_IRQ,
 +            FSL_IMX7_GPIO6_HIGH_IRQ,
 +            FSL_IMX7_GPIO7_HIGH_IRQ,
 +        };
 +
          sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
 -        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 +                        FSL_IMX7_GPIOn_ADDR[i]);
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 +                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                                            FSL_IMX7_GPIOn_LOW_IRQ[i]));
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 +                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                                            FSL_IMX7_GPIOn_HIGH_IRQ[i]));
      }
      /*
 --
-.25.1
+.34.1

-[PULL 24/34] hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
+[PULL 10/33] sbsa-ref: remove cortex-a76 from list of supported cpus
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-The pointed MouseTransformInfo structure is accessed read-only.
+Cortex-A76 supports 40bits of address space. sbsa-ref's memory
 starts above this limit.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221220142520.24094-2-philmd@linaro.org
+Message-id: 20230126114416.2447685-1-marcin.juszkiewicz@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/input/tsc2xxx.h | 4 ++--
+ hw/arm/sbsa-ref.c | 1 -
- hw/input/tsc2005.c         | 2 +-
+file changed, 1 deletion(-)
  hw/input/tsc210x.c         | 3 +--
 files changed, 4 insertions(+), 5 deletions(-)
-diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/input/tsc2xxx.h
+--- a/hw/arm/sbsa-ref.c
-+++ b/include/hw/input/tsc2xxx.h
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ uWireSlave *tsc2102_init(qemu_irq pint);
+@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
- uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
+ static const char * const valid_cpus[] = {
- I2SCodec *tsc210x_codec(uWireSlave *chip);
+     ARM_CPU_TYPE_NAME("cortex-a57"),
- uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
+     ARM_CPU_TYPE_NAME("cortex-a72"),
--void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
+-    ARM_CPU_TYPE_NAME("cortex-a76"),
-+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info);
+     ARM_CPU_TYPE_NAME("neoverse-n1"),
- void tsc210x_key_event(uWireSlave *chip, int key, int down);
+     ARM_CPU_TYPE_NAME("max"),
+ };
  /* tsc2005.c */
  void *tsc2005_init(qemu_irq pintdav);
  uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
 -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
 +void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info);
  #endif
 diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/input/tsc2005.c
 +++ b/hw/input/tsc2005.c
@@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav)
   * from the touchscreen.  Assuming 12-bit precision was used during
   * tslib calibration.
   */
 -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
 +void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info)
  {
      TSC2005State *s = (TSC2005State *) opaque;
 diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/input/tsc210x.c
 +++ b/hw/input/tsc210x.c
@@ -XXX,XX +XXX,XX @@ I2SCodec *tsc210x_codec(uWireSlave *chip)
   * from the touchscreen.  Assuming 12-bit precision was used during
   * tslib calibration.
   */
 -void tsc210x_set_transform(uWireSlave *chip,
 -                MouseTransformInfo *info)
 +void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info)
  {
      TSC210xState *s = (TSC210xState *) chip->opaque;
  #if 0
 --
-.25.1
+.34.1

-[PULL 27/34] target/arm: align exposed ID registers with Linux
+[PULL 11/33] target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
-From: Zhuojia Shen <chaosdefinition@hotmail.com>
+The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
 S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
 them AT S1E1R and AT S1E1W (which are entirely different
 instructions).  Fix the names.
-In CPUID registers exposed to userspace, some registers were missing
+(This has no guest-visible effect as the names are for debug purposes
-and some fields were not exposed.  This patch aligns exposed ID
+only.)
 registers and their fields with what the upstream kernel currently
 exposes.
-Specifically, the following new ID registers/fields are exposed to
-userspace:
-ID_AA64PFR1_EL1.BT:       bits 3-0
-ID_AA64PFR1_EL1.MTE:      bits 11-8
-ID_AA64PFR1_EL1.SME:      bits 27-24
-ID_AA64ZFR0_EL1.SVEver:   bits 3-0
-ID_AA64ZFR0_EL1.AES:      bits 7-4
-ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
-ID_AA64ZFR0_EL1.BF16:     bits 23-20
-ID_AA64ZFR0_EL1.SHA3:     bits 35-32
-ID_AA64ZFR0_EL1.SM4:      bits 43-40
-ID_AA64ZFR0_EL1.I8MM:     bits 47-44
-ID_AA64ZFR0_EL1.F32MM:    bits 55-52
-ID_AA64ZFR0_EL1.F64MM:    bits 59-56
-ID_AA64SMFR0_EL1.F32F32:  bit 32
-ID_AA64SMFR0_EL1.B16F32:  bit 34
-ID_AA64SMFR0_EL1.F16F32:  bit 35
-ID_AA64SMFR0_EL1.I8I32:   bits 39-36
-ID_AA64SMFR0_EL1.F64F64:  bit 48
-ID_AA64SMFR0_EL1.I16I64:  bits 55-52
-ID_AA64SMFR0_EL1.FA64:    bit 63
-ID_AA64MMFR0_EL1.ECV:     bits 63-60
-ID_AA64MMFR1_EL1.AFP:     bits 47-44
-ID_AA64MMFR2_EL1.AT:      bits 35-32
-ID_AA64ISAR0_EL1.RNDR:    bits 63-60
-ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
-ID_AA64ISAR1_EL1.BF16:    bits 47-44
-ID_AA64ISAR1_EL1.DGH:     bits 51-48
-ID_AA64ISAR1_EL1.I8MM:    bits 55-52
-ID_AA64ISAR2_EL1.WFxT:    bits 3-0
-ID_AA64ISAR2_EL1.RPRES:   bits 7-4
-ID_AA64ISAR2_EL1.GPA3:    bits 11-8
-ID_AA64ISAR2_EL1.APA3:    bits 15-12
-The code is also refactored to use symbolic names for ID register fields
-for better readability and maintainability.
-The test case in tests/tcg/aarch64/sysregs.c is also updated to match
-the intended behavior.
-Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
-Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
-that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-2-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-2-peter.maydell@linaro.org
 ---
- target/arm/helper.c               | 96 +++++++++++++++++++++++++------
+ target/arm/helper.c | 4 ++--
- tests/tcg/aarch64/sysregs.c       | 24 ++++++--
+file changed, 2 insertions(+), 2 deletions(-)
  tests/tcg/aarch64/Makefile.target |  7 ++-
 files changed, 103 insertions(+), 24 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
- #ifdef CONFIG_USER_ONLY
-         static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+ #ifndef CONFIG_USER_ONLY
-             { .name = "ID_AA64PFR0_EL1",
+ static const ARMCPRegInfo ats1e1_reginfo[] = {
--              .exported_bits = 0x000f000f00ff0000,
+-    { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
--              .fixed_bits    = 0x0000000000000011 },
++    { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
-+              .exported_bits = R_ID_AA64PFR0_FP_MASK |
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
-+                               R_ID_AA64PFR0_ADVSIMD_MASK |
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+                               R_ID_AA64PFR0_SVE_MASK |
+       .writefn = ats_write64 },
-+                               R_ID_AA64PFR0_DIT_MASK,
+-    { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
-+              .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
++    { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
-+                            (0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
-             { .name = "ID_AA64PFR1_EL1",
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
--              .exported_bits = 0x00000000000000f0 },
+       .writefn = ats_write64 },
 +              .exported_bits = R_ID_AA64PFR1_BT_MASK |
 +                               R_ID_AA64PFR1_SSBS_MASK |
 +                               R_ID_AA64PFR1_MTE_MASK |
 +                               R_ID_AA64PFR1_SME_MASK },
              { .name = "ID_AA64PFR*_EL1_RESERVED",
 -              .is_glob = true                     },
 -            { .name = "ID_AA64ZFR0_EL1"           },
 +              .is_glob = true },
 +            { .name = "ID_AA64ZFR0_EL1",
 +              .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
 +                               R_ID_AA64ZFR0_AES_MASK |
 +                               R_ID_AA64ZFR0_BITPERM_MASK |
 +                               R_ID_AA64ZFR0_BFLOAT16_MASK |
 +                               R_ID_AA64ZFR0_SHA3_MASK |
 +                               R_ID_AA64ZFR0_SM4_MASK |
 +                               R_ID_AA64ZFR0_I8MM_MASK |
 +                               R_ID_AA64ZFR0_F32MM_MASK |
 +                               R_ID_AA64ZFR0_F64MM_MASK },
 +            { .name = "ID_AA64SMFR0_EL1",
 +              .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
 +                               R_ID_AA64SMFR0_B16F32_MASK |
 +                               R_ID_AA64SMFR0_F16F32_MASK |
 +                               R_ID_AA64SMFR0_I8I32_MASK |
 +                               R_ID_AA64SMFR0_F64F64_MASK |
 +                               R_ID_AA64SMFR0_I16I64_MASK |
 +                               R_ID_AA64SMFR0_FA64_MASK },
              { .name = "ID_AA64MMFR0_EL1",
 -              .fixed_bits    = 0x00000000ff000000 },
 -            { .name = "ID_AA64MMFR1_EL1"          },
 +              .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
 +              .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
 +                            (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
 +            { .name = "ID_AA64MMFR1_EL1",
 +              .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
 +            { .name = "ID_AA64MMFR2_EL1",
 +              .exported_bits = R_ID_AA64MMFR2_AT_MASK },
              { .name = "ID_AA64MMFR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64DFR0_EL1",
 -              .fixed_bits    = 0x0000000000000006 },
 -            { .name = "ID_AA64DFR1_EL1"           },
 +              .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
 +            { .name = "ID_AA64DFR1_EL1" },
              { .name = "ID_AA64DFR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64AFR*",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64ISAR0_EL1",
 -              .exported_bits = 0x00fffffff0fffff0 },
 +              .exported_bits = R_ID_AA64ISAR0_AES_MASK |
 +                               R_ID_AA64ISAR0_SHA1_MASK |
 +                               R_ID_AA64ISAR0_SHA2_MASK |
 +                               R_ID_AA64ISAR0_CRC32_MASK |
 +                               R_ID_AA64ISAR0_ATOMIC_MASK |
 +                               R_ID_AA64ISAR0_RDM_MASK |
 +                               R_ID_AA64ISAR0_SHA3_MASK |
 +                               R_ID_AA64ISAR0_SM3_MASK |
 +                               R_ID_AA64ISAR0_SM4_MASK |
 +                               R_ID_AA64ISAR0_DP_MASK |
 +                               R_ID_AA64ISAR0_FHM_MASK |
 +                               R_ID_AA64ISAR0_TS_MASK |
 +                               R_ID_AA64ISAR0_RNDR_MASK },
              { .name = "ID_AA64ISAR1_EL1",
 -              .exported_bits = 0x000000f0ffffffff },
 +              .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
 +                               R_ID_AA64ISAR1_APA_MASK |
 +                               R_ID_AA64ISAR1_API_MASK |
 +                               R_ID_AA64ISAR1_JSCVT_MASK |
 +                               R_ID_AA64ISAR1_FCMA_MASK |
 +                               R_ID_AA64ISAR1_LRCPC_MASK |
 +                               R_ID_AA64ISAR1_GPA_MASK |
 +                               R_ID_AA64ISAR1_GPI_MASK |
 +                               R_ID_AA64ISAR1_FRINTTS_MASK |
 +                               R_ID_AA64ISAR1_SB_MASK |
 +                               R_ID_AA64ISAR1_BF16_MASK |
 +                               R_ID_AA64ISAR1_DGH_MASK |
 +                               R_ID_AA64ISAR1_I8MM_MASK },
 +            { .name = "ID_AA64ISAR2_EL1",
 +              .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
 +                               R_ID_AA64ISAR2_RPRES_MASK |
 +                               R_ID_AA64ISAR2_GPA3_MASK |
 +                               R_ID_AA64ISAR2_APA3_MASK },
              { .name = "ID_AA64ISAR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
          };
          modify_arm_cp_regs(v8_idregs, v8_user_idregs);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
  #ifdef CONFIG_USER_ONLY
          static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1",
 -              .exported_bits = 0x00000000ffffffff },
 -            { .name = "REVIDR_EL1"                },
 +              .exported_bits = R_MIDR_EL1_REVISION_MASK |
 +                               R_MIDR_EL1_PARTNUM_MASK |
 +                               R_MIDR_EL1_ARCHITECTURE_MASK |
 +                               R_MIDR_EL1_VARIANT_MASK |
 +                               R_MIDR_EL1_IMPLEMENTER_MASK },
 +            { .name = "REVIDR_EL1" },
          };
          modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
  #endif
 diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/aarch64/sysregs.c
 +++ b/tests/tcg/aarch64/sysregs.c
@@ -XXX,XX +XXX,XX @@
  #define HWCAP_CPUID (1 << 11)
  #endif
 +/*
 + * Older assemblers don't recognize newer system register names,
 + * but we can still access them by the Sn_n_Cn_Cn_n syntax.
 + */
 +#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
 +#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
 +
  int failed_bit_count;
  /* Read and print system register `id' value */
@@ -XXX,XX +XXX,XX @@ int main(void)
       * minimum valid fields - for the purposes of this check allowed
       * to have non-zero values.
       */
 -    get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
 -    get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
 +    get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
 +    get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
 +    get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
      /* TGran4 & TGran64 as pegged to -1 */
 -    get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
 -    get_cpu_reg_check_zero(id_aa64mmfr1_el1);
 +    get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
 +    get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
 +    get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
      /* EL1/EL0 reported as AA64 only */
      get_cpu_reg_check_mask(id_aa64pfr0_el1,  _m(000f,000f,00ff,0011));
 -    get_cpu_reg_check_mask(id_aa64pfr1_el1,  _m(0000,0000,0000,00f0));
 +    get_cpu_reg_check_mask(id_aa64pfr1_el1,  _m(0000,0000,0f00,0fff));
      /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
      get_cpu_reg_check_mask(id_aa64dfr0_el1,  _m(0000,0000,0000,0006));
      get_cpu_reg_check_zero(id_aa64dfr1_el1);
 -    get_cpu_reg_check_zero(id_aa64zfr0_el1);
 +    get_cpu_reg_check_mask(id_aa64zfr0_el1,  _m(0ff0,ff0f,00ff,00ff));
 +#ifdef HAS_ARMV9_SME
 +    get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
 +#endif
      get_cpu_reg_check_zero(id_aa64afr0_el1);
      get_cpu_reg_check_zero(id_aa64afr1_el1);
 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/aarch64/Makefile.target
 +++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
          $(call cc-option,-march=armv8.1-a+sve2,         CROSS_CC_HAS_SVE2); \
          $(call cc-option,-march=armv8.3-a,              CROSS_CC_HAS_ARMV8_3); \
          $(call cc-option,-mbranch-protection=standard,  CROSS_CC_HAS_ARMV8_BTI); \
 -        $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
 +        $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE); \
 +        $(call cc-option,-march=armv9-a+sme,            CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
  -include config-cc.mak
  # Pauth Tests
@@ -XXX,XX +XXX,XX @@ endif
  ifneq ($(CROSS_CC_HAS_SVE),)
  # System Registers Tests
  AARCH64_TESTS += sysregs
 +ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
 +sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
 +else
  sysregs: CFLAGS+=-march=armv8.1-a+sve
 +endif
  # SVE ioctl test
  AARCH64_TESTS += sve-ioctls
 --
-.25.1
+.34.1

-[PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA
+[PULL 12/33] target/arm: Correct syndrome for ATS12NSO* at Secure EL1
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+The AArch32 ATS12NSO* address translation operations are supposed to
 trap to either EL2 or EL3 if they're executed at Secure EL1 (which
 can only happen if EL3 is AArch64).  We implement this, but we got
 the syndrome value wrong: like other traps to EL2 or EL3 on an
 AArch32 cpreg access, they should report the 0x3 syndrome, not the
 x0 'uncategorized' syndrome.  This is clear in the access pseudocode
 for these instructions.
-Cores with PMSA have the MPUIR register which has the
+Fix the syndrome value for these operations by correcting the
-same encoding as the MIDR alias with opc2=4. So we only
+returned value from the ats_access() function.
 add that alias if we are not realizing a core that
 implements PMSA.
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
+Tested-by: Fuad Tabba <tabba@google.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230130182459.3309057-3-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 13 +++++++++----
+ target/arm/helper.c | 4 ++--
-file changed, 9 insertions(+), 4 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
-               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
+         if (arm_current_el(env) == 1) {
-               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
+             if (arm_is_secure_below_el3(env)) {
-               .readfn = midr_read },
+                 if (env->cp15.scr_el3 & SCR_EEL2) {
--            /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
+-                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
--            { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
++                    return CP_ACCESS_TRAP_EL2;
--              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+                 }
--              .access = PL1_R, .resetvalue = cpu->midr },
+-                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
-+            /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
++                return CP_ACCESS_TRAP_EL3;
-             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+             }
-               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
+             return CP_ACCESS_TRAP_UNCATEGORIZED;
                .access = PL1_R, .resetvalue = cpu->midr },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .accessfn = access_aa64_tid1,
                .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
          };
 +        ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
 +            .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
 +            .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
 +            .access = PL1_R, .resetvalue = cpu->midr
 +        };
          ARMCPRegInfo id_cp_reginfo[] = {
              /* These are common to v8 and pre-v8 */
              { .name = "CTR",
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          }
          if (arm_feature(env, ARM_FEATURE_V8)) {
              define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
 +            if (!arm_feature(env, ARM_FEATURE_PMSA)) {
 +                define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
 +            }
          } else {
              define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
          }
 --
-.25.1
+.34.1

-[PULL 31/34] i.MX7D: Compute clock frequency for the fixed frequency clocks.
+[PULL 13/33] target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
-From: Jean-Christophe Dubois <jcd@tribudubois.net>
+We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
 and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
 the ats_access() function, but doing so was incorrect (a bug fixed in
 a previous commit).  There aren't any cases where we want an access
 function to be able to request a trap to EL2 or EL3 with a zero
 syndrome value, so remove these enum values.
-CCM derived clocks will have to be added later.
+As well as cleaning up dead code, the motivation here is that
 we'd like to implement fine-grained-trap handling in
 helper_access_check_cp_reg(). Although the fine-grained traps
 to EL2 are always lower priority than trap-to-same-EL and
 higher priority than trap-to-EL3, they are in the middle of
 various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
 must always for us have the same syndrome (ie that an access
 function will return CP_ACCESS_TRAP_EL2 and there is no other
 kind of trap-to-EL2 enum value) means we don't have to try
 to choose which of the two syndrome values to report if the
 access would trap to EL2 both for the fine-grained-trap and
 because the access function requires it.
-Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
 ---
- hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++---------
+ target/arm/cpregs.h    | 4 ++--
-file changed, 40 insertions(+), 9 deletions(-)
+ target/arm/op_helper.c | 2 ++
 files changed, 4 insertions(+), 2 deletions(-)
-diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/imx7_ccm.c
+--- a/target/arm/cpregs.h
-+++ b/hw/misc/imx7_ccm.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
- #include "hw/misc/imx7_ccm.h"
+      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
- #include "migration/vmstate.h"
+      * Note that this is not a catch-all case -- the set of cases which may
+      * result in this failure is specifically defined by the architecture.
-+#include "trace.h"
++     * This trap is always to the usual target EL, never directly to a
-+
++     * specified target EL.
 +#define CKIH_FREQ 24000000 /* 24MHz crystal input */
 +
  static void imx7_analog_reset(DeviceState *dev)
  {
      IMX7AnalogState *s = IMX7_ANALOG(dev);
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx7_ccm = {
  static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
  {
      /*
 -     * This function is "consumed" by GPT emulation code, however on
 -     * i.MX7 each GPT block can have their own clock root. This means
 -     * that this functions needs somehow to know requester's identity
 -     * and the way to pass it: be it via additional IMXClk constants
 -     * or by adding another argument to this method needs to be
 -     * figured out
 +     * This function is "consumed" by GPT emulation code. Some clocks
 +     * have fixed frequencies and we can provide requested frequency
 +     * easily. However for CCM provided clocks (like IPG) each GPT
 +     * timer can have its own clock root.
 +     * This means we need additionnal information when calling this
 +     * function to know the requester's identity.
       */
--    qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
+     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
--                  TYPE_IMX7_CCM, __func__);
+-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
--    return 0;
+-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
-+    uint32_t freq = 0;
+ } CPAccessResult;
-+
-+    switch (clock) {
+ typedef struct ARMCPRegInfo ARMCPRegInfo;
-+    case CLK_NONE:
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-+        break;
+index XXXXXXX..XXXXXXX 100644
-+    case CLK_32k:
+--- a/target/arm/op_helper.c
-+        freq = CKIL_FREQ;
++++ b/target/arm/op_helper.c
-+        break;
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-+    case CLK_HIGH:
+     case CP_ACCESS_TRAP:
-+        freq = CKIH_FREQ;
+         break;
-+        break;
+     case CP_ACCESS_TRAP_UNCATEGORIZED:
-+    case CLK_IPG:
++        /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
-+    case CLK_IPG_HIGH:
++        assert((res & CP_ACCESS_EL_MASK) == 0);
-+        /*
+         if (cpu_isar_feature(aa64_ids, cpu) && isread &&
-+         * For now we don't have a way to figure out the device this
+             arm_cpreg_in_idspace(ri)) {
-+         * function is called for. Until then the IPG derived clocks
+             /*
 +         * are left unimplemented.
 +         */
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
 +                      TYPE_IMX7_CCM, __func__, clock);
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
 +                      TYPE_IMX7_CCM, __func__, clock);
 +        break;
 +    }
 +
 +    trace_ccm_clock_freq(clock, freq);
 +
 +    return freq;
  }
  static void imx7_ccm_class_init(ObjectClass *klass, void *data)
 --
-.25.1
+.34.1

-[PULL 09/34] target/arm: fix handling of HLT semihosting in system mode
+[PULL 14/33] target/arm: Move do_coproc_insn() syndrome calculation earlier
-From: Alex Bennée <alex.bennee@linaro.org>
+Rearrange the code in do_coproc_insn() so that we calculate the
 syndrome value for a potential trap early; we're about to add a
 second check that wants this value earlier than where it is currently
 determined.
-The check semihosting_enabled() wants to know if the guest is
+(Specifically, a trap to EL2 because of HSTR_EL2 should take
-currently in user mode. Unlike the other cases the test was inverted
+priority over an UNDEF to EL1, even when the UNDEF is because
-causing us to block semihosting calls in non-EL0 modes.
+the register does not exist at all or because its ri->access
 bits non-configurably fail the access. So the check we put in
 for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
 going to have to be done before the check "is the ARMCPRegInfo
 pointer NULL".)
-Cc: qemu-stable@nongnu.org
+This commit is just code motion; the change to HSTR_EL2
-Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
+handling that will use the 'syndrome' variable is in a
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+subsequent commit.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-5-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-5-peter.maydell@linaro.org
 ---
- target/arm/translate.c | 2 +-
+ target/arm/translate.c | 83 +++++++++++++++++++++---------------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 41 insertions(+), 42 deletions(-)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-      * semihosting, to provide some semblance of security
+     const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
-      * (and for consistency with our 32-bit semihosting).
+     TCGv_ptr tcg_ri = NULL;
-      */
+     bool need_exit_tb;
--    if (semihosting_enabled(s->current_el != 0) &&
++    uint32_t syndrome;
-+    if (semihosting_enabled(s->current_el == 0) &&
++
-         (imm == (s->thumb ? 0x3c : 0xf000))) {
++    /*
-         gen_exception_internal_insn(s, EXCP_SEMIHOST);
++     * Note that since we are an implementation which takes an
-         return;
++     * exception on a trapped conditional instruction only if the
 +     * instruction passes its condition code check, we can take
 +     * advantage of the clause in the ARM ARM that allows us to set
 +     * the COND field in the instruction to 0xE in all cases.
 +     * We could fish the actual condition out of the insn (ARM)
 +     * or the condexec bits (Thumb) but it isn't necessary.
 +     */
 +    switch (cpnum) {
 +    case 14:
 +        if (is64) {
 +            syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 +                                         isread, false);
 +        } else {
 +            syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 +                                        rt, isread, false);
 +        }
 +        break;
 +    case 15:
 +        if (is64) {
 +            syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 +                                         isread, false);
 +        } else {
 +            syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 +                                        rt, isread, false);
 +        }
 +        break;
 +    default:
 +        /*
 +         * ARMv8 defines that only coprocessors 14 and 15 exist,
 +         * so this can only happen if this is an ARMv7 or earlier CPU,
 +         * in which case the syndrome information won't actually be
 +         * guest visible.
 +         */
 +        assert(!arm_dc_feature(s, ARM_FEATURE_V8));
 +        syndrome = syn_uncategorized();
 +        break;
 +    }
      if (!ri) {
          /*
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
           * Note that on XScale all cp0..c13 registers do an access check
           * call in order to handle c15_cpar.
           */
 -        uint32_t syndrome;
 -
 -        /*
 -         * Note that since we are an implementation which takes an
 -         * exception on a trapped conditional instruction only if the
 -         * instruction passes its condition code check, we can take
 -         * advantage of the clause in the ARM ARM that allows us to set
 -         * the COND field in the instruction to 0xE in all cases.
 -         * We could fish the actual condition out of the insn (ARM)
 -         * or the condexec bits (Thumb) but it isn't necessary.
 -         */
 -        switch (cpnum) {
 -        case 14:
 -            if (is64) {
 -                syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 -                                             isread, false);
 -            } else {
 -                syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 -                                            rt, isread, false);
 -            }
 -            break;
 -        case 15:
 -            if (is64) {
 -                syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
 -                                             isread, false);
 -            } else {
 -                syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
 -                                            rt, isread, false);
 -            }
 -            break;
 -        default:
 -            /*
 -             * ARMv8 defines that only coprocessors 14 and 15 exist,
 -             * so this can only happen if this is an ARMv7 or earlier CPU,
 -             * in which case the syndrome information won't actually be
 -             * guest visible.
 -             */
 -            assert(!arm_dc_feature(s, ARM_FEATURE_V8));
 -            syndrome = syn_uncategorized();
 -            break;
 -        }
 -
          gen_set_condexec(s);
          gen_update_pc(s, 0);
          tcg_ri = tcg_temp_new_ptr();
 --
-.25.1
+.34.1

-[PULL 01/34] target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
+[PULL 15/33] target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
-In get_phys_addr_twostage() we set the lg_page_size of the result to
+The HSTR_EL2 register has a collection of trap bits which allow
-the maximum of the stage 1 and stage 2 page sizes.  This works for
+trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
-the case where we do want to create a TLB entry, because we know the
+registers.  The specification of these bits is that when the bit is
-common TLB code only creates entries of the TARGET_PAGE_SIZE and
+set we should trap
-asking for a size larger than that only means that invalidations
+ * EL1 accesses
-invalidate the whole larger area.  However, if lg_page_size is
+ * EL0 accesses, if the access is not UNDEFINED when the
-smaller than TARGET_PAGE_SIZE this effectively means "don't create a
+   trap bit is 0
 TLB entry"; in this case if either S1 or S2 said "this covers less
 than a page and can't go in a TLB" then the final result also should
 be marked that way.  Set the resulting page size to 0 if either
 stage asked for a less-than-a-page entry, and expand the comment
 to explain what's going on.
-This has no effect for VMSA because currently the VMSA lookup always
+In other words, all UNDEF traps from EL0 to EL1 take precedence over
-returns results that cover at least TARGET_PAGE_SIZE; however when we
+the HSTR_EL2 trap to EL2.  (Since this is all AArch32, the only kind
-add v8R support it will reuse this code path, and for v8R the S1 and
+of trap-to-EL1 is the UNDEF.)
-S2 results can be smaller than TARGET_PAGE_SIZE.
 Our implementation doesn't quite get this right -- we check for traps
 in the order:
  * no such register
  * ARMCPRegInfo::access bits
  * HSTR_EL2 trap bits
  * ARMCPRegInfo::accessfn
 So UNDEFs that happen because of the access bits or because the
 register doesn't exist at all correctly take priority over the
 HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
 accessfn we are incorrectly always taking the HSTR_EL2 trap.  There
 aren't many of these, but one example is the PMCR; if you look at the
 access pseudocode for this register you can see that UNDEFs taken
 because of the value of PMUSERENR.EN are checked before the HSTR_EL2
 bit.
 Rearrange helper_access_check_cp_reg() so that we always call the
 accessfn, and use its return value if it indicates that the access
 traps to EL0 rather than continuing to do the HSTR_EL2 check.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-6-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-6-peter.maydell@linaro.org
 ---
- target/arm/ptw.c | 16 +++++++++++++---
+ target/arm/op_helper.c | 21 ++++++++++++++++-----
-file changed, 13 insertions(+), 3 deletions(-)
+file changed, 16 insertions(+), 5 deletions(-)
-diff --git a/target/arm/ptw.c b/target/arm/ptw.c
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/ptw.c
+--- a/target/arm/op_helper.c
-+++ b/target/arm/ptw.c
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
          goto fail;
      }
++    if (ri->accessfn) {
++        res = ri->accessfn(env, ri, isread);
++    }
++
      /*
--     * Use the maximum of the S1 & S2 page size, so that invalidation
+-     * Check for an EL2 trap due to HSTR_EL2. We expect EL0 accesses
--     * of pages > TARGET_PAGE_SIZE works correctly.
+-     * to sysregs non accessible at EL0 to have UNDEF-ed already.
-+     * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
++     * If the access function indicates a trap from EL0 to EL1 then
-+     * this means "don't put this in the TLB"; in this case, return a
++     * that always takes priority over the HSTR_EL2 trap. (If it indicates
-+     * result with lg_page_size == 0 to achieve that. Otherwise,
++     * a trap to EL3, then the HSTR_EL2 trap takes priority; if it indicates
-+     * use the maximum of the S1 & S2 page size, so that invalidation
++     * a trap to EL2, then the syndrome is the same either way so we don't
-+     * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
++     * care whether technically the architecture says that HSTR_EL2 trap or
-+     * we know the combined result permissions etc only cover the minimum
++     * the other trap takes priority. So we take the "check HSTR_EL2" path
-+     * of the S1 and S2 page size, because we know that the common TLB code
++     * for all of those cases.)
 +     * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
 +     * and passing a larger page size value only affects invalidations.)
       */
--    if (result->f.lg_page_size < s1_lgpgsz) {
++    if (res != CP_ACCESS_OK && ((res & CP_ACCESS_EL_MASK) == 0) &&
-+    if (result->f.lg_page_size < TARGET_PAGE_BITS ||
++        arm_current_el(env) == 0) {
-+        s1_lgpgsz < TARGET_PAGE_BITS) {
++        goto fail;
-+        result->f.lg_page_size = 0;
++    }
-+    } else if (result->f.lg_page_size < s1_lgpgsz) {
++
-         result->f.lg_page_size = s1_lgpgsz;
+     if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
          (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
          uint32_t mask = 1 << ri->crn;
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
          }
      }
+-    if (ri->accessfn) {
+-        res = ri->accessfn(env, ri, isread);
+-    }
+     if (likely(res == CP_ACCESS_OK)) {
+         return ri;
+     }
 --
-.25.1
+.34.1

-[PULL 34/34] hw/net: Fix read of uninitialized memory in imx_fec.
+[PULL 16/33] target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
-From: Stephen Longfield <slongfield@google.com>
+The semantics of HSTR_EL2 require that it traps cpreg accesses
 to EL2 for:
  * EL1 accesses
  * EL0 accesses, if the access is not UNDEFINED when the
    trap bit is 0
-Size is used at lines 1088/1188 for the loop, which reads the last 4
+(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
-bytes from the crc_ptr so it does need to get increased, however it
+traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
-shouldn't be increased before the buffer is passed to CRC computation,
+HSTR_EL2 traps from EL0 are priority 15.)
 or the crc32 function will access uninitialized memory.
-This was pointed out to me by clg@kaod.org during the code review of
+However, we don't get this right for EL1 accesses which UNDEF because
-a similar patch to hw/net/ftgmac100.c
+the register doesn't exist at all or because its ri->access bits
 non-configurably forbid the access.  At EL1, check for the HSTR_EL2
 trap early, before either of these UNDEF reasons.
-Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
+We have to retain the HSTR_EL2 check in access_check_cp_reg(),
-Signed-off-by: Stephen Longfield <slongfield@google.com>
+because at EL0 any kind of UNDEF-to-EL1 (including "no such
-Reviewed-by: Patrick Venture <venture@google.com>
+register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
-Message-id: 20221221183202.3788132-1-slongfield@google.com
+takes precedence over the trap to EL2.  But we only need to do that
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+check for EL0 now.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
 ---
- hw/net/imx_fec.c | 8 ++++----
+ target/arm/op_helper.c |  6 +++++-
-file changed, 4 insertions(+), 4 deletions(-)
+ target/arm/translate.c | 28 +++++++++++++++++++++++++++-
 files changed, 32 insertions(+), 2 deletions(-)
-diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/imx_fec.c
+--- a/target/arm/op_helper.c
-+++ b/hw/net/imx_fec.c
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-         return 0;
+         goto fail;
      }
--    /* 4 bytes for the CRC.  */
+-    if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
--    size += 4;
++    /*
-     crc = cpu_to_be32(crc32(~0, buf, size));
++     * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
-+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
++     * we only need to check here for traps from EL0.
-+    size += 4;
++     */
-     crc_ptr = (uint8_t *) &crc;
++    if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-     /* Huge frames are truncated.  */
+         uint32_t mask = 1 << ri->crn;
-@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
-         return 0;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
          break;
      }
--    /* 4 bytes for the CRC.  */
++    if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
--    size += 4;
++        /*
-     crc = cpu_to_be32(crc32(~0, buf, size));
++         * At EL1, check for a HSTR_EL2 trap, which must take precedence
-+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
++         * over the UNDEF for "no such register" or the UNDEF for "access
-+    size += 4;
++         * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
-     crc_ptr = (uint8_t *) &crc;
++         * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
++         * access_check_cp_reg(), after the checks for whether the access
-     if (shift16) {
++         * configurably trapped to EL1.
 +         */
 +        uint32_t maskbit = is64 ? crm : crn;
 +
 +        if (maskbit != 4 && maskbit != 14) {
 +            /* T4 and T14 are RES0 so never cause traps */
 +            TCGv_i32 t;
 +            DisasLabel over = gen_disas_label(s);
 +
 +            t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
 +            tcg_gen_andi_i32(t, t, 1u << maskbit);
 +            tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
 +            tcg_temp_free_i32(t);
 +
 +            gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
 +            set_disas_label(s, over);
 +        }
 +    }
 +
      if (!ri) {
          /*
           * Unknown register; this might be a guest error or a QEMU
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
          return;
      }
 -    if (s->hstr_active || ri->accessfn ||
 +    if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
          (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
          /*
           * Emit code to perform further access permissions checks at
 --
-.25.1
+.34.1

-[PULL 20/34] target/arm: Fix checkpatch brace errors in helper.c
+[PULL 17/33] target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
-From: Fabiano Rosas <farosas@suse.de>
+The HSTR_EL2 register is not supposed to have an effect unless EL2 is
 enabled in the current security state.  We weren't checking for this,
 which meant that if the guest set up the HSTR_EL2 register we would
 incorrectly trap even for accesses from Secure EL0 and EL1.
-Fix this:
+Add the missing checks. (Other places where we look at HSTR_EL2
-ERROR: braces {} are necessary for all arms of this statement
+for the not-in-v8A bits TTEE and TJDBX are already checking that
 we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)
-Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Reviewed-by: Claudio Fontana <cfontana@suse.de>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
-Message-id: 20221213190537.511-4-farosas@suse.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-8-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-8-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 67 ++++++++++++++++++++++++++++-----------------
+ target/arm/helper.c    | 2 +-
-file changed, 42 insertions(+), 25 deletions(-)
+ target/arm/op_helper.c | 1 +
 files changed, 2 insertions(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
-         env->CF = (val >> 29) & 1;
+         DP_TBFLAG_A32(flags, VFPEN, 1);
          env->VF = (val << 3) & 0x80000000;
      }
--    if (mask & CPSR_Q)
-+    if (mask & CPSR_Q) {
+-    if (el < 2 && env->cp15.hstr_el2 &&
-         env->QF = ((val & CPSR_Q) != 0);
++    if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
--    if (mask & CPSR_T)
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-+    }
+         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
 +    if (mask & CPSR_T) {
          env->thumb = ((val & CPSR_T) != 0);
 +    }
      if (mask & CPSR_IT_0_1) {
          env->condexec_bits &= ~3;
          env->condexec_bits |= (val >> 25) & 3;
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
      int i;
      old_mode = env->uncached_cpsr & CPSR_M;
 -    if (mode == old_mode)
 +    if (mode == old_mode) {
          return;
 +    }
      if (old_mode == ARM_CPU_MODE_FIQ) {
          memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
          new_mode = ARM_CPU_MODE_UND;
          addr = 0x04;
          mask = CPSR_I;
 -        if (env->thumb)
 +        if (env->thumb) {
              offset = 2;
 -        else
 +        } else {
              offset = 4;
 +        }
          break;
      case EXCP_SWI:
          new_mode = ARM_CPU_MODE_SVC;
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_sat(uint16_t a, uint16_t b)
      res = a + b;
      if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
 -        if (a & 0x8000)
 +        if (a & 0x8000) {
              res = 0x8000;
 -        else
 +        } else {
              res = 0x7fff;
 +        }
      }
-     return res;
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
- }
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ static inline uint8_t add8_sat(uint8_t a, uint8_t b)
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
-     res = a + b;
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
+      * we only need to check here for traps from EL0.
--        if (a & 0x80)
+      */
-+        if (a & 0x80) {
+     if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
-             res = 0x80;
++        arm_is_el2_enabled(env) &&
--        else
+         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
-+        } else {
+         uint32_t mask = 1 << ri->crn;
              res = 0x7f;
 +        }
      }
      return res;
  }
@@ -XXX,XX +XXX,XX @@ static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
      res = a - b;
      if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
 -        if (a & 0x8000)
 +        if (a & 0x8000) {
              res = 0x8000;
 -        else
 +        } else {
              res = 0x7fff;
 +        }
      }
      return res;
  }
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
      res = a - b;
      if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
 -        if (a & 0x80)
 +        if (a & 0x80) {
              res = 0x80;
 -        else
 +        } else {
              res = 0x7f;
 +        }
      }
      return res;
  }
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_usat(uint16_t a, uint16_t b)
  {
      uint16_t res;
      res = a + b;
 -    if (res < a)
 +    if (res < a) {
          res = 0xffff;
 +    }
      return res;
  }
  static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
  {
 -    if (a > b)
 +    if (a > b) {
          return a - b;
 -    else
 +    } else {
          return 0;
 +    }
  }
  static inline uint8_t add8_usat(uint8_t a, uint8_t b)
  {
      uint8_t res;
      res = a + b;
 -    if (res < a)
 +    if (res < a) {
          res = 0xff;
 +    }
      return res;
  }
  static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
  {
 -    if (a > b)
 +    if (a > b) {
          return a - b;
 -    else
 +    } else {
          return 0;
 +    }
  }
  #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
  static inline uint8_t do_usad(uint8_t a, uint8_t b)
  {
 -    if (a > b)
 +    if (a > b) {
          return a - b;
 -    else
 +    } else {
          return b - a;
 +    }
  }
  /* Unsigned sum of absolute byte differences.  */
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
      uint32_t mask;
      mask = 0;
 -    if (flags & 1)
 +    if (flags & 1) {
          mask |= 0xff;
 -    if (flags & 2)
 +    }
 +    if (flags & 2) {
          mask |= 0xff00;
 -    if (flags & 4)
 +    }
 +    if (flags & 4) {
          mask |= 0xff0000;
 -    if (flags & 8)
 +    }
 +    if (flags & 8) {
          mask |= 0xff000000;
 +    }
      return (a & mask) | (b & ~mask);
  }
 --
-.25.1
+.34.1

-[PULL 25/34] hw/arm/nseries: Constify various read-only arrays
+[PULL 18/33] target/arm: Define the FEAT_FGT registers
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Define the system registers which are provided by the
+FEAT_FGT fine-grained trap architectural feature:
-Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+ HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
 All these registers are a set of bit fields, where each bit is set
 for a trap and clear to not trap on a particular system register
 access.  The R and W register pairs are for system registers,
 allowing trapping to be done separately for reads and writes; the I
 register is for system instructions where trapping is on instruction
 execution.
 The data storage in the CPU state struct is arranged as a set of
 arrays rather than separate fields so that when we're looking up the
 bits for a system register access we can just index into the array
 rather than having to use a switch to select a named struct member.
 The later FEAT_FGT2 will add extra elements to these arrays.
 The field definitions for the new registers are in cpregs.h because
 in practice the code that needs them is code that also needs
 the cpregs information; cpu.h is included in a lot more files.
 We're also going to add some FGT-specific definitions to cpregs.h
 in the next commit.
 We do not implement HAFGRTR_EL2, because we don't implement
 FEAT_AMUv1.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221220142520.24094-3-philmd@linaro.org
+Tested-by: Fuad Tabba <tabba@google.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
 ---
- hw/arm/nseries.c | 18 +++++++++---------
+ target/arm/cpregs.h | 285 ++++++++++++++++++++++++++++++++++++++++++++
-file changed, 9 insertions(+), 9 deletions(-)
+ target/arm/cpu.h    |  15 +++
+ target/arm/helper.c |  40 +++++++
-diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
+files changed, 340 insertions(+)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/nseries.c
+--- a/target/arm/cpregs.h
-+++ b/hw/arm/nseries.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s)
+@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
      CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
  } CPAccessResult;
 +/* Indexes into fgt_read[] */
 +#define FGTREG_HFGRTR 0
 +#define FGTREG_HDFGRTR 1
 +/* Indexes into fgt_write[] */
 +#define FGTREG_HFGWTR 0
 +#define FGTREG_HDFGWTR 1
 +/* Indexes into fgt_exec[] */
 +#define FGTREG_HFGITR 0
 +
 +FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
 +FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
 +FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
 +FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
 +FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
 +FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
 +FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
 +FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
 +FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
 +FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
 +FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
 +FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
 +FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
 +FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
 +FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
 +FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
 +FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
 +FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
 +FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
 +FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
 +FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
 +FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
 +FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
 +FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
 +FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
 +FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
 +FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
 +FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
 +FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
 +FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
 +FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
 +FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
 +FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
 +FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
 +FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
 +FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
 +FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
 +FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
 +FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
 +FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
 +FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
 +FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
 +FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
 +FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
 +FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
 +FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
 +FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
 +FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
 +FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
 +FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
 +FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
 +/* 51-53: RES0 */
 +FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
 +FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
 +/* 56-63: RES0 */
 +
 +/* These match HFGRTR but bits for RO registers are RES0 */
 +FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
 +FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
 +FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
 +FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
 +FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
 +FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
 +FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
 +FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
 +FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
 +FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
 +FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
 +FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
 +FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
 +FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
 +FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
 +FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
 +FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
 +FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
 +FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
 +FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
 +FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
 +FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
 +FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
 +FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
 +FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
 +FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
 +FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
 +FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
 +FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
 +FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
 +FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
 +FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
 +FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
 +FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
 +FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
 +FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
 +FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
 +FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
 +FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
 +FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
 +
 +FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
 +FIELD(HFGITR_EL2, ICIALLU, 1, 1)
 +FIELD(HFGITR_EL2, ICIVAU, 2, 1)
 +FIELD(HFGITR_EL2, DCIVAC, 3, 1)
 +FIELD(HFGITR_EL2, DCISW, 4, 1)
 +FIELD(HFGITR_EL2, DCCSW, 5, 1)
 +FIELD(HFGITR_EL2, DCCISW, 6, 1)
 +FIELD(HFGITR_EL2, DCCVAU, 7, 1)
 +FIELD(HFGITR_EL2, DCCVAP, 8, 1)
 +FIELD(HFGITR_EL2, DCCVADP, 9, 1)
 +FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
 +FIELD(HFGITR_EL2, DCZVA, 11, 1)
 +FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
 +FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
 +FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
 +FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
 +FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
 +FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
 +FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
 +FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
 +FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
 +FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
 +FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
 +FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
 +FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
 +FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
 +FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
 +FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
 +FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
 +FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
 +FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
 +FIELD(HFGITR_EL2, ERET, 51, 1)
 +FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
 +FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
 +FIELD(HFGITR_EL2, DCCVAC, 54, 1)
 +FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
 +FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
 +
 +FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
 +FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
 +FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
 +FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
 +FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
 +FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
 +FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
 +FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
 +/* 8: RES0: OSLAR_EL1 is WO */
 +FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
 +FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
 +FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
 +FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
 +FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
 +FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
 +FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
 +FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
 +FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
 +FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
 +FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
 +/* 20: RES0: PMSWINC_EL0 is WO */
 +/* 21: RES0: PMCR_EL0 is WO */
 +FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
 +FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
 +FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
 +FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
 +FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
 +FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
 +FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
 +FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
 +FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
 +FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
 +FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
 +FIELD(HDFGRTR_EL2, TRC, 33, 1)
 +FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
 +FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
 +FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
 +FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
 +/* 38, 39: RES0 */
 +FIELD(HDFGRTR_EL2, TRCID, 40, 1)
 +FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
 +/* 42: RES0: TRCOSLAR is WO */
 +FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
 +FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
 +FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
 +FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
 +FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
 +FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
 +/* 49: RES0: TRFCR_EL1 is WO */
 +FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
 +FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
 +FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
 +FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
 +FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
 +FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
 +FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
 +FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
 +FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
 +FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
 +FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
 +FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
 +FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
 +
 +/*
 + * These match HDFGRTR_EL2, but bits for RO registers are RES0.
 + * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
 + */
 +FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
 +FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
 +FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
 +FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
 +FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
 +FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
 +FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
 +FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
 +FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
 +FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
 +FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
 +FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
 +FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
 +FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
 +FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
 +FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
 +FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
 +FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
 +FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
 +FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
 +FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
 +FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
 +FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
 +FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
 +FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
 +FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
 +FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
 +FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
 +FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
 +FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
 +FIELD(HDFGWTR_EL2, TRC, 33, 1)
 +FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
 +FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
 +FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
 +FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
 +FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
 +FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
 +FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
 +FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
 +FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
 +FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
 +FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
 +FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
 +FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
 +FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
 +FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
 +FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
 +FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
 +FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
 +FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
 +FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +
  typedef struct ARMCPRegInfo ARMCPRegInfo;
  /*
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
          uint64_t disr_el1;
          uint64_t vdisr_el2;
          uint64_t vsesr_el2;
 +
 +        /*
 +         * Fine-Grained Trap registers. We store these as arrays so the
 +         * access checking code doesn't have to manually select
 +         * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
 +         * FEAT_FGT2 will add more elements to these arrays.
 +         */
 +        uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
 +        uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
 +        uint64_t fgt_exec[1]; /* HFGITR */
      } cp15;
      struct {
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
      return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
  }
- /* Touchscreen and keypad controller */
++static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
--static MouseTransformInfo n800_pointercal = {
++{
-+static const MouseTransformInfo n800_pointercal = {
++    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
-     .x = 800,
++}
-     .y = 480,
++
-     .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
+ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          if (cpu_isar_feature(aa64_hcx, cpu)) {
              valid_mask |= SCR_HXEN;
          }
 +        if (cpu_isar_feature(aa64_fgt, cpu)) {
 +            valid_mask |= SCR_FGTEN;
 +        }
      } else {
          valid_mask &= ~(SCR_RW | SCR_ST);
          if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
        .access = PL3_RW,
        .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
  };
++
--static MouseTransformInfo n810_pointercal = {
++static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
-+static const MouseTransformInfo n810_pointercal = {
++                                 bool isread)
-     .x = 800,
++{
-     .y = 480,
++    if (arm_current_el(env) == 2 &&
-     .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
++        arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
-@@ -XXX,XX +XXX,XX @@ static void n810_key_event(void *opaque, int keycode)
++        return CP_ACCESS_TRAP_EL3;
++    }
- #define M    0
++    return CP_ACCESS_OK;
++}
--static int n810_keys[0x80] = {
++
-+static const int n810_keys[0x80] = {
++static const ARMCPRegInfo fgt_reginfo[] = {
-     [0x01] = 16,    /* Q */
++    { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
-     [0x02] = 37,    /* K */
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
-     [0x03] = 24,    /* O */
++      .access = PL2_RW, .accessfn = access_fgt,
-@@ -XXX,XX +XXX,XX @@ static void n8x0_usb_setup(struct n800_s *s)
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
- /* Setup done before the main bootloader starts by some early setup code
++    { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
-  * - used when we want to run the main bootloader in emulation.  This
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
-  * isn't documented.  */
++      .access = PL2_RW, .accessfn = access_fgt,
--static uint32_t n800_pinout[104] = {
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
-+static const uint32_t n800_pinout[104] = {
++    { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
-x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
++      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
-x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
++      .access = PL2_RW, .accessfn = access_fgt,
-x08080808, 0x180800c4, 0x00b80000, 0x08080808,
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
-@@ -XXX,XX +XXX,XX @@ static void n8x0_boot_init(void *opaque)
++    { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
- #define OMAP_TAG_CBUS        0x4e03
++      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
- #define OMAP_TAG_EM_ASIC_BB5    0x4e04
++      .access = PL2_RW, .accessfn = access_fgt,
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
--static struct omap_gpiosw_info_s {
++    { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
-+static const struct omap_gpiosw_info_s {
++      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
-     const char *name;
++      .access = PL2_RW, .accessfn = access_fgt,
-     int line;
++      .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
-     int type;
++};
-@@ -XXX,XX +XXX,XX @@ static struct omap_gpiosw_info_s {
+ #endif /* TARGET_AARCH64 */
-     { NULL }
- };
+ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
--static struct omap_partition_info_s {
+     if (cpu_isar_feature(aa64_scxtnum, cpu)) {
-+static const struct omap_partition_info_s {
+         define_arm_cp_regs(cpu, scxtnum_reginfo);
-     uint32_t offset;
+     }
-     uint32_t size;
++
-     int mask;
++    if (cpu_isar_feature(aa64_fgt, cpu)) {
-@@ -XXX,XX +XXX,XX @@ static struct omap_partition_info_s {
++        define_arm_cp_regs(cpu, fgt_reginfo);
-     { 0, 0, 0, NULL }
++    }
- };
+ #endif
--static uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
+     if (cpu_isar_feature(any_predinv, cpu)) {
 +static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
  static int n8x0_atag_setup(void *p, int model)
  {
      uint8_t *b;
      uint16_t *w;
      uint32_t *l;
 -    struct omap_gpiosw_info_s *gpiosw;
 -    struct omap_partition_info_s *partition;
 +    const struct omap_gpiosw_info_s *gpiosw;
 +    const struct omap_partition_info_s *partition;
      const char *tag;
      w = p;
 --
-.25.1
+.34.1

-[PULL 15/34] hw/timer/imx_epit: factor out register write handlers
+[PULL 19/33] target/arm: Implement FGT trapping infrastructure
-From: Axel Heider <axel.heider@hensoldt.net>
+Implement the machinery for fine-grained traps on normal sysregs.
+Any sysreg with a fine-grained trap will set the new field to
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+indicate which FGT register bit it should trap on.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 FGT traps only happen when an AArch64 EL2 enables them for
 an AArch64 EL1. They therefore are only relevant for AArch32
 cpregs when the cpreg can be accessed from EL0. The logic
 in access_check_cp_reg() will check this, so it is safe to
 add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.
 The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
 which can be used to specify the FGT bit, eg
    .fgt = FGT_AFSR0_EL1
 (We assume that there is no bit name duplication across the FGT
 registers, for brevity's sake.)
 Subsequent commits will add the .fgt fields to the relevant register
 definitions and define the FGT_nnn values for them.
 Note that some of the FGT traps are for instructions that we don't
 handle via the cpregs mechanisms (mostly these are instruction traps).
 Those we will have to handle separately.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
 ---
- hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++--------------------
+ target/arm/cpregs.h        | 72 ++++++++++++++++++++++++++++++++++++++
-file changed, 117 insertions(+), 98 deletions(-)
+ target/arm/cpu.h           |  1 +
+ target/arm/internals.h     | 20 +++++++++++
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
+ target/arm/translate.h     |  2 ++
-index XXXXXXX..XXXXXXX 100644
+ target/arm/helper.c        |  9 +++++
---- a/hw/timer/imx_epit.c
+ target/arm/op_helper.c     | 30 ++++++++++++++++
-+++ b/hw/timer/imx_epit.c
+ target/arm/translate-a64.c |  3 +-
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
+ target/arm/translate.c     |  2 ++
-     }
+files changed, 138 insertions(+), 1 deletion(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
  FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
  FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 +/* Which fine-grained trap bit register to check, if any */
 +FIELD(FGT, TYPE, 10, 3)
 +FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
 +FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
 +FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
 +
 +/*
 + * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
 + * fields. We assume for brevity's sake that there are no duplicated
 + * bit names across the various FGT registers.
 + */
 +#define DO_BIT(REG, BITNAME)                                    \
 +    FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
 +
 +/* Some bits have reversed sense, so 0 means trap and 1 means not */
 +#define DO_REV_BIT(REG, BITNAME)                                        \
 +    FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
 +
 +typedef enum FGTBit {
 +    /*
 +     * These bits tell us which register arrays to use:
 +     * if FGT_R is set then reads are checked against fgt_read[];
 +     * if FGT_W is set then writes are checked against fgt_write[];
 +     * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
 +     *
 +     * For almost all bits in the R/W register pairs, the bit exists in
 +     * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
 +     * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
 +     * for a WO register. There are unfortunately a couple of exceptions
 +     * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
 +     * the FGT system only allows trapping of writes, not reads.
 +     *
 +     * Note that we arrange these bits so that a 0 FGTBit means "no trap".
 +     */
 +    FGT_R = 1 << R_FGT_TYPE_SHIFT,
 +    FGT_W = 2 << R_FGT_TYPE_SHIFT,
 +    FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
 +    FGT_RW = FGT_R | FGT_W,
 +    /* Bit to identify whether trap bit is reversed sense */
 +    FGT_REV = R_FGT_REV_MASK,
 +
 +    /*
 +     * If a bit exists in HFGRTR/HDFGRTR then either the register being
 +     * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
 +     * want to trap for both reads and writes or else it's harmless to mark
 +     * it as trap-on-writes.
 +     * If a bit exists only in HFGWTR/HDFGWTR then either the register being
 +     * trapped is WO, or else it is one of the two oddball special cases
 +     * which are RW but have only a write trap. We mark these as only
 +     * FGT_W so we get the right behaviour for those special cases.
 +     * (If a bit was added in future that provided only a read trap for an
 +     * RW register we'd need to do something special to get the FGT_R bit
 +     * only. But this seems unlikely to happen.)
 +     *
 +     * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
 +     * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
 +     */
 +    FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
 +    FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
 +    FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
 +    FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
 +    FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
 +} FGTBit;
 +
 +#undef DO_BIT
 +#undef DO_REV_BIT
 +
  typedef struct ARMCPRegInfo ARMCPRegInfo;
  /*
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
      CPAccessRights access;
      /* Security state: ARM_CP_SECSTATE_* bits/values */
      CPSecureState secure;
 +    /*
 +     * Which fine-grained trap register bit to check, if any. This
 +     * value encodes both the trap register and bit within it.
 +     */
 +    FGTBit fgt;
      /*
       * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
       * this register was defined: can be used to hand data through to the
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
  /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
  FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
  FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
 +FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
  /*
   * Bit usage when in AArch32 state, both A- and M-profile.
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
      ((1 << (1 - 1)) | (1 << (2 - 1)) |                  \
       (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
 +/*
 + * Return true if it is possible to take a fine-grained-trap to EL2.
 + */
 +static inline bool arm_fgt_active(CPUARMState *env, int el)
 +{
 +    /*
 +     * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
 +     * that can affect EL0, but it is harmless to do the test also for
 +     * traps on registers that are only accessible at EL1 because if the test
 +     * returns true then we can't be executing at EL1 anyway.
 +     * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
 +     * traps from AArch32 only happen for the EL0 is AArch32 case.
 +     */
 +    return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +        el < 2 && arm_is_el2_enabled(env) &&
 +        arm_el_is_aa64(env, 1) &&
 +        (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
 +        (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
 +}
 +
  #endif
 diff --git a/target/arm/translate.h b/target/arm/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.h
 +++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      bool is_nonstreaming;
      /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
      bool mve_no_pred;
 +    /* True if fine-grained traps are active */
 +    bool fgt_active;
      /*
       * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
       *  < 0, set by the current instruction.
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
      if (arm_singlestep_active(env)) {
          DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
      }
 +
      return flags;
  }
-+static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
-+{
+         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
-+    uint32_t oldcr = s->cr;
+     }
-+
-+    s->cr = value & 0x03ffffff;
++    if (arm_fgt_active(env, el)) {
-+
++        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
 +    if (s->cr & CR_SWR) {
 +        /* handle the reset */
 +        imx_epit_reset(s, false);
 +    }
 +
-+    /*
+     if (env->uncached_cpsr & CPSR_IL) {
-+     * The interrupt state can change due to:
+         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
-+     * - reset clears both SR.OCIF and CR.OCIE
+     }
-+     * - write to CR.EN or CR.OCIE
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
-+     */
+         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
-+    imx_epit_update_int(s);
+     }
-+
-+    /*
++    if (arm_fgt_active(env, el)) {
-+     * TODO: could we 'break' here for reset? following operations appear
++        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
 +     * to duplicate the work imx_epit_reset() already did.
 +     */
 +
 +    ptimer_transaction_begin(s->timer_cmp);
 +    ptimer_transaction_begin(s->timer_reload);
 +
 +    /* Update the frequency. Has been done already in case of a reset. */
 +    if (!(s->cr & CR_SWR)) {
 +        imx_epit_set_freq(s);
 +    }
 +
-+    if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
+     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
-+        if (s->cr & CR_ENMOD) {
+         /*
-+            if (s->cr & CR_RLD) {
+          * Set MTE_ACTIVE if any access may be Checked, and leave clear
-+                ptimer_set_limit(s->timer_reload, s->lr, 1);
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
-+                ptimer_set_limit(s->timer_cmp, s->lr, 1);
+index XXXXXXX..XXXXXXX 100644
-+            } else {
+--- a/target/arm/op_helper.c
-+                ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
++++ b/target/arm/op_helper.c
-+                ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
+@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
-+            }
+         }
      }
 +    /*
 +     * Fine-grained traps also are lower priority than undef-to-EL1,
 +     * higher priority than trap-to-EL3, and we don't care about priority
 +     * order with other EL2 traps because the syndrome value is the same.
 +     */
 +    if (arm_fgt_active(env, arm_current_el(env))) {
 +        uint64_t trapword = 0;
 +        unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
 +        unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
 +        bool rev = FIELD_EX32(ri->fgt, FGT, REV);
 +        bool trapbit;
 +
 +        if (ri->fgt & FGT_EXEC) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
 +            trapword = env->cp15.fgt_exec[idx];
 +        } else if (isread && (ri->fgt & FGT_R)) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
 +            trapword = env->cp15.fgt_read[idx];
 +        } else if (!isread && (ri->fgt & FGT_W)) {
 +            assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
 +            trapword = env->cp15.fgt_write[idx];
 +        }
 +
-+        imx_epit_reload_compare_timer(s);
++        trapbit = extract64(trapword, bitpos, 1);
-+        ptimer_run(s->timer_reload, 0);
++        if (trapbit != rev) {
-+        if (s->cr & CR_OCIEN) {
++            res = CP_ACCESS_TRAP_EL2;
-+            ptimer_run(s->timer_cmp, 0);
++            goto fail;
 +        } else {
 +            ptimer_stop(s->timer_cmp);
 +        }
-+    } else if (!(s->cr & CR_EN)) {
-+        /* stop both timers */
-+        ptimer_stop(s->timer_reload);
-+        ptimer_stop(s->timer_cmp);
-+    } else  if (s->cr & CR_OCIEN) {
-+        if (!(oldcr & CR_OCIEN)) {
-+            imx_epit_reload_compare_timer(s);
-+            ptimer_run(s->timer_cmp, 0);
-+        }
-+    } else {
-+        ptimer_stop(s->timer_cmp);
 +    }
 +
-+    ptimer_transaction_commit(s->timer_cmp);
+     if (likely(res == CP_ACCESS_OK)) {
-+    ptimer_transaction_commit(s->timer_reload);
+         return ri;
-+}
+     }
-+
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-+static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
+index XXXXXXX..XXXXXXX 100644
-+{
+--- a/target/arm/translate-a64.c
-+    /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
++++ b/target/arm/translate-a64.c
-+    if (value & SR_OCIF) {
+@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
-+        s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
+         return;
-+        imx_epit_update_int(s);
+     }
-+    }
-+}
+-    if (ri->accessfn) {
-+
++    if (ri->accessfn || (ri->fgt && s->fgt_active)) {
-+static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
+         /* Emit code to perform further access permissions checks at
-+{
+          * runtime; this may result in an exception.
-+    s->lr = value;
+          */
-+
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
-+    ptimer_transaction_begin(s->timer_cmp);
+     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
-+    ptimer_transaction_begin(s->timer_reload);
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
-+    if (s->cr & CR_RLD) {
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
-+        /* Also set the limit if the LRD bit is set */
++    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
-+        /* If IOVW bit is set then set the timer value */
+     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
-+        ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
+     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
-+        ptimer_set_limit(s->timer_cmp, s->lr, 0);
+     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
-+    } else if (s->cr & CR_IOVW) {
+diff --git a/target/arm/translate.c b/target/arm/translate.c
-+        /* If IOVW bit is set then set the timer value */
+index XXXXXXX..XXXXXXX 100644
-+        ptimer_set_count(s->timer_reload, s->lr);
+--- a/target/arm/translate.c
-+    }
++++ b/target/arm/translate.c
-+    /*
+@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
-+     * Commit the change to s->timer_reload, so it can propagate. Otherwise
+     }
-+     * the timer interrupt may not fire properly. The commit must happen
-+     * before calling imx_epit_reload_compare_timer(), which reads
+     if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
-+     * s->timer_reload internally again.
++        (ri->fgt && s->fgt_active) ||
-+     */
+         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
-+    ptimer_transaction_commit(s->timer_reload);
+         /*
-+    imx_epit_reload_compare_timer(s);
+          * Emit code to perform further access permissions checks at
-+    ptimer_transaction_commit(s->timer_cmp);
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-+}
+     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
-+
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
-+static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
-+{
++    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
-+    s->cmp = value;
-+
+     if (arm_feature(env, ARM_FEATURE_M)) {
-+    ptimer_transaction_begin(s->timer_cmp);
+         dc->vfp_enabled = 1;
 +    imx_epit_reload_compare_timer(s);
 +    ptimer_transaction_commit(s->timer_cmp);
 +}
 +
  static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
                             unsigned size)
  {
      IMXEPITState *s = IMX_EPIT(opaque);
 -    uint64_t oldcr;
      DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
              (uint32_t)value);
      switch (offset >> 2) {
      case 0: /* CR */
 -
 -        oldcr = s->cr;
 -        s->cr = value & 0x03ffffff;
 -        if (s->cr & CR_SWR) {
 -            /* handle the reset */
 -            imx_epit_reset(s, false);
 -        }
 -
 -        /*
 -         * The interrupt state can change due to:
 -         * - reset clears both SR.OCIF and CR.OCIE
 -         * - write to CR.EN or CR.OCIE
 -         */
 -        imx_epit_update_int(s);
 -
 -        /*
 -         * TODO: could we 'break' here for reset? following operations appear
 -         * to duplicate the work imx_epit_reset() already did.
 -         */
 -
 -        ptimer_transaction_begin(s->timer_cmp);
 -        ptimer_transaction_begin(s->timer_reload);
 -
 -        /* Update the frequency. Has been done already in case of a reset. */
 -        if (!(s->cr & CR_SWR)) {
 -            imx_epit_set_freq(s);
 -        }
 -
 -        if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
 -            if (s->cr & CR_ENMOD) {
 -                if (s->cr & CR_RLD) {
 -                    ptimer_set_limit(s->timer_reload, s->lr, 1);
 -                    ptimer_set_limit(s->timer_cmp, s->lr, 1);
 -                } else {
 -                    ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
 -                    ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
 -                }
 -            }
 -
 -            imx_epit_reload_compare_timer(s);
 -            ptimer_run(s->timer_reload, 0);
 -            if (s->cr & CR_OCIEN) {
 -                ptimer_run(s->timer_cmp, 0);
 -            } else {
 -                ptimer_stop(s->timer_cmp);
 -            }
 -        } else if (!(s->cr & CR_EN)) {
 -            /* stop both timers */
 -            ptimer_stop(s->timer_reload);
 -            ptimer_stop(s->timer_cmp);
 -        } else  if (s->cr & CR_OCIEN) {
 -            if (!(oldcr & CR_OCIEN)) {
 -                imx_epit_reload_compare_timer(s);
 -                ptimer_run(s->timer_cmp, 0);
 -            }
 -        } else {
 -            ptimer_stop(s->timer_cmp);
 -        }
 -
 -        ptimer_transaction_commit(s->timer_cmp);
 -        ptimer_transaction_commit(s->timer_reload);
 +        imx_epit_write_cr(s, (uint32_t)value);
          break;
 -    case 1: /* SR - ACK*/
 -        /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
 -        if (value & SR_OCIF) {
 -            s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
 -            imx_epit_update_int(s);
 -        }
 +    case 1: /* SR */
 +        imx_epit_write_sr(s, (uint32_t)value);
          break;
 -    case 2: /* LR - set ticks */
 -        s->lr = value;
 -
 -        ptimer_transaction_begin(s->timer_cmp);
 -        ptimer_transaction_begin(s->timer_reload);
 -        if (s->cr & CR_RLD) {
 -            /* Also set the limit if the LRD bit is set */
 -            /* If IOVW bit is set then set the timer value */
 -            ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
 -            ptimer_set_limit(s->timer_cmp, s->lr, 0);
 -        } else if (s->cr & CR_IOVW) {
 -            /* If IOVW bit is set then set the timer value */
 -            ptimer_set_count(s->timer_reload, s->lr);
 -        }
 -        /*
 -         * Commit the change to s->timer_reload, so it can propagate. Otherwise
 -         * the timer interrupt may not fire properly. The commit must happen
 -         * before calling imx_epit_reload_compare_timer(), which reads
 -         * s->timer_reload internally again.
 -         */
 -        ptimer_transaction_commit(s->timer_reload);
 -        imx_epit_reload_compare_timer(s);
 -        ptimer_transaction_commit(s->timer_cmp);
 +    case 2: /* LR */
 +        imx_epit_write_lr(s, (uint32_t)value);
          break;
      case 3: /* CMP */
 -        s->cmp = value;
 -
 -        ptimer_transaction_begin(s->timer_cmp);
 -        imx_epit_reload_compare_timer(s);
 -        ptimer_transaction_commit(s->timer_cmp);
 -
 +        imx_epit_write_cmp(s, (uint32_t)value);
          break;
      default:
          qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                        HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
 -
          break;
      }
  }
 +
  static void imx_epit_cmp(void *opaque)
  {
      IMXEPITState *s = IMX_EPIT(opaque);
 --
-.25.1
+.34.1

-[PULL 26/34] hw/arm/nseries: Silent -Wmissing-field-initializers warning
+[PULL 20/33] target/arm: Mark up sysregs for HFGRTR bits 0..11
-From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Mark up the sysreg definitions for the registers trapped
 by HFGRTR/HFGWTR bits 0..11.
-Silent when compiling with -Wextra:
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
 ---
  target/arm/cpregs.h | 14 ++++++++++++++
  target/arm/helper.c | 17 +++++++++++++++++
 files changed, 31 insertions(+)
-  ../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers]
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
       { NULL }
              ^
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20221220142520.24094-4-philmd@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/arm/nseries.c | 10 ++++------
 file changed, 4 insertions(+), 6 deletions(-)
 diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/nseries.c
+--- a/target/arm/cpregs.h
-+++ b/hw/arm/nseries.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-         "headphone", N8X0_HEADPHONE_GPIO,
+     FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
-         OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
+     FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
-     },
+     FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
--    { NULL }
++
-+    { /* end of list */ }
++    /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
- }, n810_gpiosw_info[] = {
++    DO_BIT(HFGRTR, AFSR0_EL1),
-     {
++    DO_BIT(HFGRTR, AFSR1_EL1),
-         "gps_reset", N810_GPS_RESET_GPIO,
++    DO_BIT(HFGRTR, AIDR_EL1),
-@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
++    DO_BIT(HFGRTR, AMAIR_EL1),
-         "slide", N810_SLIDE_GPIO,
++    DO_BIT(HFGRTR, APDAKEY),
-         OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
++    DO_BIT(HFGRTR, APDBKEY),
-     },
++    DO_BIT(HFGRTR, APGAKEY),
--    { NULL }
++    DO_BIT(HFGRTR, APIAKEY),
-+    { /* end of list */ }
++    DO_BIT(HFGRTR, APIBKEY),
 +    DO_BIT(HFGRTR, CCSIDR_EL1),
 +    DO_BIT(HFGRTR, CLIDR_EL1),
 +    DO_BIT(HFGRTR, CONTEXTIDR_EL1),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
      { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_CONTEXTIDR_EL1,
        .secure = ARM_CP_SECSTATE_NS,
        .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
        .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
        .access = PL1_R,
        .accessfn = access_tid4,
 +      .fgt = FGT_CCSIDR_EL1,
        .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
      { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
        .access = PL1_R, .type = ARM_CP_CONST,
        .accessfn = access_aa64_tid1,
 +      .fgt = FGT_AIDR_EL1,
        .resetvalue = 0 },
      /*
       * Auxiliary fault status registers: these also are IMPDEF, and we
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_AFSR0_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_AFSR1_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      /*
       * MAIR can just read-as-written because we don't implement caches
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
      { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_AMAIR_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
      { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
      { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APDAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
      { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APDAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
      { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APDBKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
      { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APDBKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
      { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APGAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
      { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APGAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
      { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APIAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
      { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APIAKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
      { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APIBKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
      { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
        .access = PL1_RW, .accessfn = access_pauth,
 +      .fgt = FGT_APIBKEY,
        .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
  };
- static const struct omap_partition_info_s {
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ static const struct omap_partition_info_s {
+             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
-     { 0x00080000, 0x00200000, 0x0, "kernel" },
+             .access = PL1_R, .type = ARM_CP_CONST,
-     { 0x00280000, 0x00200000, 0x3, "initfs" },
+             .accessfn = access_tid4,
-     { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
++            .fgt = FGT_CLIDR_EL1,
--
+             .resetvalue = cpu->clidr
--    { 0, 0, 0, NULL }
+         };
-+    { /* end of list */ }
+         define_one_arm_cp_reg(cpu, &clidr);
  }, n810_part_info[] = {
      { 0x00000000, 0x00020000, 0x3, "bootloader" },
      { 0x00020000, 0x00060000, 0x0, "config" },
      { 0x00080000, 0x00220000, 0x0, "kernel" },
      { 0x002a0000, 0x00400000, 0x0, "initfs" },
      { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
 -
 -    { 0, 0, 0, NULL }
 +    { /* end of list */ }
  };
  static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
 --
-.25.1
+.34.1

-[PULL 18/34] target/arm: Fix checkpatch comment style warnings in helper.c
+[PULL 21/33] target/arm: Mark up sysregs for HFGRTR bits 12..23
-From: Fabiano Rosas <farosas@suse.de>
+Mark up the sysreg definitions for the registers trapped
 by HFGRTR/HFGWTR bits 12..23.
-Fix these:
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
 ---
  target/arm/cpregs.h | 12 ++++++++++++
  target/arm/helper.c | 12 ++++++++++++
 files changed, 24 insertions(+)
-WARNING: Block comments use a leading /* on a separate line
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-WARNING: Block comments use * on subsequent lines
+index XXXXXXX..XXXXXXX 100644
-WARNING: Block comments use a trailing */ on a separate line
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
-Signed-off-by: Fabiano Rosas <farosas@suse.de>
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-Reviewed-by: Claudio Fontana <cfontana@suse.de>
+     DO_BIT(HFGRTR, CCSIDR_EL1),
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
+     DO_BIT(HFGRTR, CLIDR_EL1),
-Message-id: 20221213190537.511-2-farosas@suse.de
+     DO_BIT(HFGRTR, CONTEXTIDR_EL1),
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++    DO_BIT(HFGRTR, CPACR_EL1),
----
++    DO_BIT(HFGRTR, CSSELR_EL1),
- target/arm/helper.c | 323 +++++++++++++++++++++++++++++---------------
++    DO_BIT(HFGRTR, CTR_EL0),
-file changed, 215 insertions(+), 108 deletions(-)
++    DO_BIT(HFGRTR, DCZID_EL0),
++    DO_BIT(HFGRTR, ESR_EL1),
 +    DO_BIT(HFGRTR, FAR_EL1),
 +    DO_BIT(HFGRTR, ISR_EL1),
 +    DO_BIT(HFGRTR, LORC_EL1),
 +    DO_BIT(HFGRTR, LOREA_EL1),
 +    DO_BIT(HFGRTR, LORID_EL1),
 +    DO_BIT(HFGRTR, LORN_EL1),
 +    DO_BIT(HFGRTR, LORSA_EL1),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
- static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
+       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
-                              uint64_t v)
+     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
- {
+       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
--    /* Raw write of a coprocessor register (as needed for migration, etc).
++      .fgt = FGT_CPACR_EL1,
-+    /*
+       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-+     * Raw write of a coprocessor register (as needed for migration, etc).
+       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
       * Note that constant registers are treated as write-ignored; the
       * caller should check for success by whether a readback gives the
       * value written.
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
  static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
  {
 -   /* Return true if the regdef would cause an assertion if you called
 +   /*
 +    * Return true if the regdef would cause an assertion if you called
      * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
      * program bug for it not to have the NO_RAW flag).
      * NB that returning false here doesn't necessarily mean that calling
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
          if (ri->type & ARM_CP_NO_RAW) {
              continue;
          }
 -        /* Write value and confirm it reads back as written
 +        /*
 +         * Write value and confirm it reads back as written
           * (to catch read-only registers and partially read-only
           * registers where the incoming migration value doesn't match)
           */
@@ -XXX,XX +XXX,XX @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
  void init_cpreg_list(ARMCPU *cpu)
  {
 -    /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 +    /*
 +     * Initialise the cpreg_tuples[] array based on the cp_regs hash.
       * Note that we require cpreg_tuples[] to be sorted by key ID.
       */
      GList *keys;
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
      return CP_ACCESS_OK;
  }
 -/* Some secure-only AArch32 registers trap to EL3 if used from
 +/*
 + * Some secure-only AArch32 registers trap to EL3 if used from
   * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
   * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
   * We assume that the .access field is set to PL1_RW.
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
      return CP_ACCESS_TRAP_UNCATEGORIZED;
  }
 -/* Check for traps to performance monitor registers, which are controlled
 +/*
 + * Check for traps to performance monitor registers, which are controlled
   * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
   */
  static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
      ARMCPU *cpu = env_archcpu(env);
      if (raw_read(env, ri) != value) {
 -        /* Unlike real hardware the qemu TLB uses virtual addresses,
 +        /*
 +         * Unlike real hardware the qemu TLB uses virtual addresses,
           * not modified virtual addresses, so this causes a TLB flush.
           */
          tlb_flush(CPU(cpu));
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
      if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
          && !extended_addresses_enabled(env)) {
 -        /* For VMSA (when not using the LPAE long descriptor page table
 +        /*
 +         * For VMSA (when not using the LPAE long descriptor page table
           * format) this register includes the ASID, so do a TLB flush.
           * For PMSA it is purely a process ID and no action is needed.
           */
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
  }
  static const ARMCPRegInfo cp_reginfo[] = {
 -    /* Define the secure and non-secure FCSE identifier CP registers
 +    /*
 +     * Define the secure and non-secure FCSE identifier CP registers
       * separately because there is no secure bank in V8 (no _EL3).  This allows
       * the secure register to be properly reset and migrated. There is also no
       * v8 EL1 version of the register so the non-secure instance stands alone.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
        .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
        .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
        .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 -    /* Define the secure and non-secure context identifier CP registers
 +    /*
 +     * Define the secure and non-secure context identifier CP registers
       * separately because there is no secure bank in V8 (no _EL3).  This allows
       * the secure register to be properly reset and migrated.  In the
       * non-secure case, the 32-bit register will have reset and migration
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
  };
- static const ARMCPRegInfo not_v8_cp_reginfo[] = {
--    /* NB: Some of these registers exist in v8 but with more precise
-+    /*
-+     * NB: Some of these registers exist in v8 but with more precise
-      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
-      */
-     /* MMU Domain access control / MPU write buffer control */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
-       .writefn = dacr_write, .raw_writefn = raw_write,
-       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
-                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
--    /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
-+    /*
-+     * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
-      * For v6 and v5, these mappings are overly broad.
-      */
-     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
- };
- static const ARMCPRegInfo not_v6_cp_reginfo[] = {
--    /* Not all pre-v6 cores implemented this WFI, so this is slightly
-+    /*
-+     * Not all pre-v6 cores implemented this WFI, so this is slightly
-      * over-broad.
-      */
-     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
- };
- static const ARMCPRegInfo not_v7_cp_reginfo[] = {
--    /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
-+    /*
-+     * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
-      * is UNPREDICTABLE; we choose to NOP as most implementations do).
-      */
-     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
-       .access = PL1_W, .type = ARM_CP_WFI },
--    /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
-+    /*
-+     * L1 cache lockdown. Not architectural in v6 and earlier but in practice
-      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
-      * OMAPCP will override this space.
-      */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
-     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
-       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
-       .resetvalue = 0 },
--    /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
-+    /*
-+     * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
-      * implementing it as RAZ means the "debug architecture version" bits
-      * will read as a reserved value, which should cause Linux to not try
-      * to use the debug hardware.
-      */
-     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
-       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
--    /* MMU TLB control. Note that the wildcarding means we cover not just
-+    /*
-+     * MMU TLB control. Note that the wildcarding means we cover not just
-      * the unified TLB ops but also the dside/iside/inner-shareable variants.
-      */
-     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
-@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
-     if (!arm_feature(env, ARM_FEATURE_V8)) {
--        /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
-+        /*
-+         * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
-          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
-          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
-          */
-@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                 value |= R_CPACR_ASEDIS_MASK;
-             }
--            /* VFPv3 and upwards with NEON implement 32 double precision
-+            /*
-+             * VFPv3 and upwards with NEON implement 32 double precision
-              * registers (D0-D31).
-              */
-             if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
-@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
- static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
- {
--    /* Call cpacr_write() so that we reset with the correct RAO bits set
-+    /*
-+     * Call cpacr_write() so that we reset with the correct RAO bits set
-      * for our CPU features.
-      */
-     cpacr_write(env, ri, 0);
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
-     { .name = "MVA_prefetch",
-       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
-       .access = PL1_W, .type = ARM_CP_NOP },
--    /* We need to break the TB after ISB to execute self-modifying code
-+    /*
-+     * We need to break the TB after ISB to execute self-modifying code
-      * correctly and also to take any pending interrupts immediately.
-      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
-      */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
-       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
-                              offsetof(CPUARMState, cp15.ifar_ns) },
-       .resetvalue = 0, },
--    /* Watchpoint Fault Address Register : should actually only be present
-+    /*
-+     * Watchpoint Fault Address Register : should actually only be present
-      * for 1136, 1176, 11MPCore.
-      */
-     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
-@@ -XXX,XX +XXX,XX @@ static bool event_supported(uint16_t number)
- static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    bool isread)
- {
--    /* Performance monitor registers user accessibility is controlled
-+    /*
-+     * Performance monitor registers user accessibility is controlled
-      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
-      * trapping to EL2 or EL3 for other accesses.
-      */
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
-     (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
- #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
--/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
-+/*
-+ * Returns true if the counter (pass 31 for PMCCNTR) should count events using
-  * the current EL, security state, and register configuration.
-  */
- static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
-@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
- static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                          uint64_t value)
- {
--    /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
-+    /*
-+     * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
-      * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
-      * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
-      * accessed.
-@@ -XXX,XX +XXX,XX @@ static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
-         pmevcntr_op_finish(env, counter);
-     }
--    /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
-+    /*
-+     * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
-      * PMSELR value is equal to or greater than the number of implemented
-      * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
-      */
-@@ -XXX,XX +XXX,XX @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
-         }
-         return ret;
-     } else {
--      /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
--       * are CONSTRAINED UNPREDICTABLE. */
-+      /*
-+       * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
-+       * are CONSTRAINED UNPREDICTABLE.
-+       */
-         return 0;
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                        uint64_t value)
- {
--    /* Note that even though the AArch64 view of this register has bits
-+    /*
-+     * Note that even though the AArch64 view of this register has bits
-      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
-      * architectural requirements for bits which are RES0 only in some
-      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
-@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
-     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-         valid_mask &= ~SCR_HCE;
--        /* On ARMv7, SMD (or SCD as it is called in v7) is only
-+        /*
-+         * On ARMv7, SMD (or SCD as it is called in v7) is only
-          * supported if EL2 exists. The bit is UNK/SBZP when
-          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
-          * when EL2 is unavailable.
-@@ -XXX,XX +XXX,XX @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
- {
-     ARMCPU *cpu = env_archcpu(env);
--    /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
-+    /*
-+     * Acquire the CSSELR index from the bank corresponding to the CCSIDR
-      * bank
-      */
-     uint32_t index = A32_BANKED_REG_GET(env, csselr,
 @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
+       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
-     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
+       .access = PL1_RW,
-       .access = PL1_W, .type = ARM_CP_NOP },
+       .accessfn = access_tid4,
--    /* Performance monitors are implementation defined in v7,
++      .fgt = FGT_CSSELR_EL1,
 +    /*
 +     * Performance monitors are implementation defined in v7,
       * but with an ARM recommended set of registers, which we
       * follow.
       *
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .writefn = csselr_write, .resetvalue = 0,
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
                               offsetof(CPUARMState, cp15.csselr_ns) } },
--    /* Auxiliary ID register: this actually has an IMPDEF value but for now
-+    /*
-+     * Auxiliary ID register: this actually has an IMPDEF value but for now
-      * just RAZ for all cores:
-      */
-     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-       .access = PL1_R, .type = ARM_CP_CONST,
+       .resetfn = arm_cp_reset_ignore },
-       .accessfn = access_aa64_tid1,
+     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
-       .resetvalue = 0 },
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
--    /* Auxiliary fault status registers: these also are IMPDEF, and we
++      .fgt = FGT_ISR_EL1,
-+    /*
+       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
-+     * Auxiliary fault status registers: these also are IMPDEF, and we
+     /* 32 bit ITLB invalidates */
-      * choose to RAZ/WI for all cores.
+     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
-      */
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
-     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
+     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
        .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_FAR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
+       .resetvalue = 0, },
+ };
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
+     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
++      .fgt = FGT_ESR_EL1,
+       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
+     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
+       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
+     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
+       .access = PL0_R, .type = ARM_CP_NO_RAW,
++      .fgt = FGT_DCZID_EL0,
+       .readfn = aa64_dczid_read },
+     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
+     { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_lor_other,
++      .fgt = FGT_LORSA_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
--    /* MAIR can just read-as-written because we don't implement caches
+     { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
-+    /*
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
-+     * MAIR can just read-as-written because we don't implement caches
+       .access = PL1_RW, .accessfn = access_lor_other,
-      * and so don't need to care about memory attributes.
++      .fgt = FGT_LOREA_EL1,
-      */
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
+     { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
-       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_lor_other,
-       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
++      .fgt = FGT_LORN_EL1,
-       .resetvalue = 0 },
+       .type = ARM_CP_CONST, .resetvalue = 0 },
--    /* For non-long-descriptor page tables these are PRRR and NMRR;
+     { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
-+    /*
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
-+     * For non-long-descriptor page tables these are PRRR and NMRR;
+       .access = PL1_RW, .accessfn = access_lor_other,
-      * regardless they still act as reads-as-written for QEMU.
++      .fgt = FGT_LORC_EL1,
-      */
+       .type = ARM_CP_CONST, .resetvalue = 0 },
--     /* MAIR0/1 are defined separately from their 64-bit counterpart which
+     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
-+     /*
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
-+      * MAIR0/1 are defined separately from their 64-bit counterpart which
+       .access = PL1_R, .accessfn = access_lor_ns,
-       * allows them to assign the correct fieldoffset based on the endianness
++      .fgt = FGT_LORID_EL1,
-       * handled in the field definitions.
+       .type = ARM_CP_CONST, .resetvalue = 0 },
        */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
  static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                         bool isread)
  {
 -    /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
 +    /*
 +     * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
       * Writable only at the highest implemented exception level.
       */
      int el = arm_current_el(env);
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
                                         const ARMCPRegInfo *ri,
                                         bool isread)
  {
 -    /* The AArch64 register view of the secure physical timer is
 +    /*
 +     * The AArch64 register view of the secure physical timer is
       * always accessible from EL3, and configurably accessible from
       * Secure EL1.
       */
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
      ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
      if (gt->ctl & 1) {
 -        /* Timer enabled: calculate and set current ISTATUS, irq, and
 +        /*
 +         * Timer enabled: calculate and set current ISTATUS, irq, and
           * reset timer to when ISTATUS next has to change
           */
          uint64_t offset = timeridx == GTIMER_VIRT ?
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
              /* Next transition is when we hit cval */
              nexttick = gt->cval + offset;
          }
 -        /* Note that the desired next expiry time might be beyond the
 +        /*
 +         * Note that the desired next expiry time might be beyond the
           * signed-64-bit range of a QEMUTimer -- in this case we just
           * set the timer for as far in the future as possible. When the
           * timer expires we will reset the timer for any remaining period.
@@ -XXX,XX +XXX,XX @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
          /* Enable toggled */
          gt_recalc_timer(cpu, timeridx);
      } else if ((oldval ^ value) & 2) {
 -        /* IMASK toggled: don't need to recalculate,
 +        /*
 +         * IMASK toggled: don't need to recalculate,
           * just set the interrupt line based on ISTATUS
           */
          int irqstate = (oldval & 4) && !(value & 2);
@@ -XXX,XX +XXX,XX @@ static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
  }
  static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
 -    /* Note that CNTFRQ is purely reads-as-written for the benefit
 +    /*
 +     * Note that CNTFRQ is purely reads-as-written for the benefit
       * of software; writing it doesn't actually change the timer frequency.
       * Our reset value matches the fixed frequency we implement the timer at.
       */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
        .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
        .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
      },
 -    /* Secure timer -- this is actually restricted to only EL3
 +    /*
 +     * Secure timer -- this is actually restricted to only EL3
       * and configurably Secure-EL1 via the accessfn.
       */
      { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
  #else
 -/* In user-mode most of the generic timer registers are inaccessible
 +/*
 + * In user-mode most of the generic timer registers are inaccessible
   * however modern kernels (4.12+) allow access to cntvct_el0
   */
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      ARMCPU *cpu = env_archcpu(env);
 -    /* Currently we have no support for QEMUTimer in linux-user so we
 +    /*
 +     * Currently we have no support for QEMUTimer in linux-user so we
       * can't call gt_get_countervalue(env), instead we directly
       * call the lower level functions.
       */
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                   bool isread)
  {
      if (ri->opc2 & 4) {
 -        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
 +        /*
 +         * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
           * Secure EL1 (which can only happen if EL3 is AArch64).
           * They are simply UNDEF if executed from NS EL1.
           * They function normally from EL2 or EL3.
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
              }
          }
      } else {
 -        /* fsr is a DFSR/IFSR value for the short descriptor
 +        /*
 +         * fsr is a DFSR/IFSR value for the short descriptor
           * translation table format (with WnR always clear).
           * Convert it to a 32-bit PAR.
           */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
  };
- static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
--    /* Reset for all these registers is handled in arm_cpu_reset(),
-+    /*
-+     * Reset for all these registers is handled in arm_cpu_reset(),
-      * because the PMSAv7 is also used by M-profile CPUs, which do
-      * not register cpregs but still need the state to be reset.
-      */
-@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     }
-     if (arm_feature(env, ARM_FEATURE_LPAE)) {
--        /* With LPAE the TTBCR could result in a change of ASID
-+        /*
-+         * With LPAE the TTBCR could result in a change of ASID
-          * via the TTBCR.A1 bit, so do a TLB flush.
-          */
-         tlb_flush(CPU(cpu));
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
-                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
- };
--/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
-+/*
-+ * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
-  * qemu tlbs nor adjusting cached masks.
-  */
- static const ARMCPRegInfo ttbcr2_reginfo = {
-@@ -XXX,XX +XXX,XX @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                   uint64_t value)
- {
--    /* On OMAP there are registers indicating the max/min index of dcache lines
-+    /*
-+     * On OMAP there are registers indicating the max/min index of dcache lines
-      * containing a dirty line; cache flush operations have to reset these.
-      */
-     env->cp15.c15_i_max = 0x000;
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
-       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
-       .type = ARM_CP_NO_RAW,
-       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
--    /* TODO: Peripheral port remap register:
-+    /*
-+     * TODO: Peripheral port remap register:
-      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
-      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
-      * when MMU is off.
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
-       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
-       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
-       .resetvalue = 0, },
--    /* XScale specific cache-lockdown: since we have no cache we NOP these
-+    /*
-+     * XScale specific cache-lockdown: since we have no cache we NOP these
-      * and hope the guest does not really rely on cache behaviour.
-      */
-     { .name = "XSCALE_LOCK_ICACHE_LINE",
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
- };
- static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
--    /* RAZ/WI the whole crn=15 space, when we don't have a more specific
-+    /*
-+     * RAZ/WI the whole crn=15 space, when we don't have a more specific
-      * implementation of this implementation-defined space.
-      * Ideally this should eventually disappear in favour of actually
-      * implementing the correct behaviour for all cores.
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
- };
- static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
--    /* The cache test-and-clean instructions always return (1 << 30)
-+    /*
-+     * The cache test-and-clean instructions always return (1 << 30)
-      * to indicate that there are no dirty cache lines.
-      */
-     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
-@@ -XXX,XX +XXX,XX @@ static uint64_t mpidr_read_val(CPUARMState *env)
-     if (arm_feature(env, ARM_FEATURE_V7MP)) {
-         mpidr |= (1U << 31);
--        /* Cores which are uniprocessor (non-coherent)
-+        /*
-+         * Cores which are uniprocessor (non-coherent)
-          * but still implement the MP extensions set
-          * bit 30. (For instance, Cortex-R5).
-          */
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
-     return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
- }
--/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
-+/*
-+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
-  * Page D4-1736 (DDI0487A.b)
-  */
-@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
- {
--    /* Invalidate by VA, EL2
-+    /*
-+     * Invalidate by VA, EL2
-      * Currently handles both VAE2 and VALE2, since we don't support
-      * flush-last-level-only.
-      */
-@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
- {
--    /* Invalidate by VA, EL3
-+    /*
-+     * Invalidate by VA, EL3
-      * Currently handles both VAE3 and VALE3, since we don't support
-      * flush-last-level-only.
-      */
-@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
- static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                  uint64_t value)
- {
--    /* Invalidate by VA, EL1&0 (AArch64 version).
-+    /*
-+     * Invalidate by VA, EL1&0 (AArch64 version).
-      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
-      * since we don't support flush-for-specific-ASID-only or
-      * flush-last-level-only.
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                     bool isread)
- {
-     if (!(env->pstate & PSTATE_SP)) {
--        /* Access to SP_EL0 is undefined if it's being used as
-+        /*
-+         * Access to SP_EL0 is undefined if it's being used as
-          * the stack pointer.
-          */
-         return CP_ACCESS_TRAP_UNCATEGORIZED;
-@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     }
-     if (raw_read(env, ri) == value) {
--        /* Skip the TLB flush if nothing actually changed; Linux likes
-+        /*
-+         * Skip the TLB flush if nothing actually changed; Linux likes
-          * to do a lot of pointless SCTLR writes.
-          */
-         return;
-@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
- }
- static const ARMCPRegInfo v8_cp_reginfo[] = {
--    /* Minimal set of EL0-visible registers. This will need to be expanded
-+    /*
-+     * Minimal set of EL0-visible registers. This will need to be expanded
-      * significantly for system emulation of AArch64 CPUs.
-      */
-     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
-       .access = PL1_RW,
-       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
--    /* We rely on the access checks not allowing the guest to write to the
-+    /*
-+     * We rely on the access checks not allowing the guest to write to the
-      * state field when SPSel indicates that it's being used as the stack
-      * pointer.
-      */
-@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
-     if (arm_feature(env, ARM_FEATURE_EL3)) {
-         valid_mask &= ~HCR_HCD;
-     } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
--        /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
-+        /*
-+         * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
-          * However, if we're using the SMC PSCI conduit then QEMU is
-          * effectively acting like EL3 firmware and so the guest at
-          * EL2 should retain the ability to prevent EL1 from being
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = tlbi_aa64_vae2is_write },
- #ifndef CONFIG_USER_ONLY
--    /* Unlike the other EL2-related AT operations, these must
-+    /*
-+     * Unlike the other EL2-related AT operations, these must
-      * UNDEF from EL3 if EL2 is not implemented, which is why we
-      * define them here rather than with the rest of the AT ops.
-      */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-       .access = PL2_W, .accessfn = at_s1e2_access,
-       .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
-       .writefn = ats_write64 },
--    /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
-+    /*
-+     * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
-      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
-      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
-      * to behave as if SCR.NS was 1.
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
-       .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
-     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
-       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
--      /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
-+      /*
-+       * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
-        * reset values as IMPDEF. We choose to reset to 3 to comply with
-        * both ARMv7 and ARMv8.
-        */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
- static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    bool isread)
- {
--    /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
-+    /*
-+     * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
-      * At Secure EL1 it traps to EL3 or EL2.
-      */
-     if (arm_current_el(env) == 3) {
-@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
-     }
- }
--/* We don't know until after realize whether there's a GICv3
-+/*
-+ * We don't know until after realize whether there's a GICv3
-  * attached, and that is what registers the gicv3 sysregs.
-  * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
-  * at runtime.
-@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
- }
- #endif
--/* Shared logic between LORID and the rest of the LOR* registers.
-+/*
-+ * Shared logic between LORID and the rest of the LOR* registers.
-  * Secure state exclusion has already been dealt with.
-  */
- static CPAccessResult access_lor_ns(CPUARMState *env,
 @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
-     define_arm_cp_regs(cpu, cp_reginfo);
+               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
-     if (!arm_feature(env, ARM_FEATURE_V8)) {
+               .access = PL0_R, .accessfn = ctr_el0_access,
--        /* Must go early as it is full of wildcards that may be
++              .fgt = FGT_CTR_EL0,
-+        /*
+               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
-+         * Must go early as it is full of wildcards that may be
+             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
-          * overridden by later definitions.
+             { .name = "TCMTR",
           */
          define_arm_cp_regs(cpu, not_v8_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa32_tid3,
                .resetvalue = cpu->isar.id_pfr0 },
 -            /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
 +            /*
 +             * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
               * the value of the GIC field until after we define these regs.
               */
              { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, el3_regs);
      }
 -    /* The behaviour of NSACR is sufficiently various that we don't
 +    /*
 +     * The behaviour of NSACR is sufficiently various that we don't
       * try to describe it in a single reginfo:
       *  if EL3 is 64 bit, then trap to EL3 from S EL1,
       *     reads as constant 0xc00 from NS EL1 and NS EL2
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      if (cpu_isar_feature(aa32_jazelle, cpu)) {
          define_arm_cp_regs(cpu, jazelle_regs);
      }
 -    /* Slightly awkwardly, the OMAP and StrongARM cores need all of
 +    /*
 +     * Slightly awkwardly, the OMAP and StrongARM cores need all of
       * cp15 crn=0 to be writes-ignored, whereas for other cores they should
       * be read-only (ie write causes UNDEF exception).
       */
      {
          ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
 -            /* Pre-v8 MIDR space.
 +            /*
 +             * Pre-v8 MIDR space.
               * Note that the MIDR isn't a simple constant register because
               * of the TI925 behaviour where writes to another register can
               * cause the MIDR value to change.
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
              arm_feature(env, ARM_FEATURE_STRONGARM)) {
              size_t i;
 -            /* Register the blanket "writes ignored" value first to cover the
 +            /*
 +             * Register the blanket "writes ignored" value first to cover the
               * whole space. Then update the specific ID registers to allow write
               * access, so that they ignore writes rather than causing them to
               * UNDEF.
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              .raw_writefn = raw_write,
          };
          if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 -            /* Normally we would always end the TB on an SCTLR write, but Linux
 +            /*
 +             * Normally we would always end the TB on an SCTLR write, but Linux
               * arch/arm/mach-pxa/sleep.S expects two instructions following
               * an MMU enable to execute from cache.  Imitate this behaviour.
               */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
  void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                         const ARMCPRegInfo *r, void *opaque)
  {
 -    /* Define implementations of coprocessor registers.
 +    /*
 +     * Define implementations of coprocessor registers.
       * We store these in a hashtable because typically
       * there are less than 150 registers in a space which
       * is 16*16*16*8*8 = 262144 in size.
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
      default:
          g_assert_not_reached();
      }
 -    /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
 +    /*
 +     * The AArch64 pseudocode CheckSystemAccess() specifies that op1
       * encodes a minimum access level for the register. We roll this
       * runtime check into our general permission check code, so check
       * here that the reginfo's specified permissions are strict enough
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
          assert((r->access & ~mask) == 0);
      }
 -    /* Check that the register definition has enough info to handle
 +    /*
 +     * Check that the register definition has enough info to handle
       * reads and writes if they are permitted.
       */
      if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                          continue;
                      }
                      if (state == ARM_CP_STATE_AA32) {
 -                        /* Under AArch32 CP registers can be common
 +                        /*
 +                         * Under AArch32 CP registers can be common
                           * (same for secure and non-secure world) or banked.
                           */
                          char *name;
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                              g_assert_not_reached();
                          }
                      } else {
 -                        /* AArch64 registers get mapped to non-secure instance
 -                         * of AArch32 */
 +                        /*
 +                         * AArch64 registers get mapped to non-secure instance
 +                         * of AArch32
 +                         */
                          add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                 ARM_CP_SECSTATE_NS,
                                                 crm, opc1, opc2, r->name);
@@ -XXX,XX +XXX,XX @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
  static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
  {
 -    /* Return true if it is not valid for us to switch to
 +    /*
 +     * Return true if it is not valid for us to switch to
       * this CPU mode (ie all the UNPREDICTABLE cases in
       * the ARM ARM CPSRWriteByInstr pseudocode).
       */
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
      case ARM_CPU_MODE_UND:
      case ARM_CPU_MODE_IRQ:
      case ARM_CPU_MODE_FIQ:
 -        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
 +        /*
 +         * Note that we don't implement the IMPDEF NSACR.RFR which in v7
           * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
           */
 -        /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
 +        /*
 +         * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
           * and CPS are treated as illegal mode changes.
           */
          if (write_type == CPSRWriteByInstr &&
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
          env->GE = (val >> 16) & 0xf;
      }
 -    /* In a V7 implementation that includes the security extensions but does
 +    /*
 +     * In a V7 implementation that includes the security extensions but does
       * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
       * whether non-secure software is allowed to change the CPSR_F and CPSR_A
       * bits respectively.
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
          changed_daif = (env->daif ^ val) & mask;
          if (changed_daif & CPSR_A) {
 -            /* Check to see if we are allowed to change the masking of async
 +            /*
 +             * Check to see if we are allowed to change the masking of async
               * abort exceptions from a non-secure state.
               */
              if (!(env->cp15.scr_el3 & SCR_AW)) {
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
          }
          if (changed_daif & CPSR_F) {
 -            /* Check to see if we are allowed to change the masking of FIQ
 +            /*
 +             * Check to see if we are allowed to change the masking of FIQ
               * exceptions from a non-secure state.
               */
              if (!(env->cp15.scr_el3 & SCR_FW)) {
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
                  mask &= ~CPSR_F;
              }
 -            /* Check whether non-maskable FIQ (NMFI) support is enabled.
 +            /*
 +             * Check whether non-maskable FIQ (NMFI) support is enabled.
               * If this bit is set software is not allowed to mask
               * FIQs, but is allowed to set CPSR_F to 0.
               */
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
      if (write_type != CPSRWriteRaw &&
          ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
          if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
 -            /* Note that we can only get here in USR mode if this is a
 +            /*
 +             * Note that we can only get here in USR mode if this is a
               * gdb stub write; for this case we follow the architectural
               * behaviour for guest writes in USR mode of ignoring an attempt
               * to switch mode. (Those are caught by translate.c for writes
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
               */
              mask &= ~CPSR_M;
          } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
 -            /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
 +            /*
 +             * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
               * v7, and has defined behaviour in v8:
               *  + leave CPSR.M untouched
               *  + allow changes to the other CPSR fields
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
      env->regs[14] = env->banked_r14[r14_bank_number(mode)];
  }
 -/* Physical Interrupt Target EL Lookup Table
 +/*
 + * Physical Interrupt Target EL Lookup Table
   *
   * [ From ARM ARM section G1.13.4 (Table G1-15) ]
   *
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
      } else {
 -        /* Either EL2 is the highest EL (and so the EL2 register width
 +        /*
 +         * Either EL2 is the highest EL (and so the EL2 register width
           * is given by is64); or there is no EL2 or EL3, in which case
           * the value of 'rw' does not affect the table lookup anyway.
           */
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
          env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
      }
 -    /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
 +    /*
 +     * Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
       * mode, then we can copy to r8-r14.  Otherwise, we copy to the
       * FIQ bank for r8-r14.
       */
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
          /* High vectors. When enabled, base address cannot be remapped. */
          addr += 0xffff0000;
      } else {
 -        /* ARM v7 architectures provide a vector base address register to remap
 +        /*
 +         * ARM v7 architectures provide a vector base address register to remap
           * the interrupt vector table.
           * This register is only followed in non-monitor mode, and is banked.
           * Note: only bits 31:5 are valid.
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
      aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
      if (cur_el < new_el) {
 -        /* Entry vector offset depends on whether the implemented EL
 +        /*
 +         * Entry vector offset depends on whether the implemented EL
           * immediately lower than the target level is using AArch32 or AArch64
           */
          bool is_aa64;
@@ -XXX,XX +XXX,XX @@ static void handle_semihosting(CPUState *cs)
  }
  #endif
 -/* Handle a CPU exception for A and R profile CPUs.
 +/*
 + * Handle a CPU exception for A and R profile CPUs.
   * Do any appropriate logging, handle PSCI calls, and then hand off
   * to the AArch64-entry or AArch32-entry function depending on the
   * target exception level's register width.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
      }
  #endif
 -    /* Hooks may change global state so BQL should be held, also the
 +    /*
 +     * Hooks may change global state so BQL should be held, also the
       * BQL needs to be held for any modification of
       * cs->interrupt_request.
       */
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
      };
  }
 -/* Note that signed overflow is undefined in C.  The following routines are
 -   careful to use unsigned types where modulo arithmetic is required.
 -   Failure to do so _will_ break on newer gcc.  */
 +/*
 + * Note that signed overflow is undefined in C.  The following routines are
 + * careful to use unsigned types where modulo arithmetic is required.
 + * Failure to do so _will_ break on newer gcc.
 + */
  /* Signed saturating arithmetic.  */
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
      return (a & mask) | (b & ~mask);
  }
 -/* CRC helpers.
 +/*
 + * CRC helpers.
   * The upper bytes of val (above the number specified by 'bytes') must have
   * been zeroed out by the caller.
   */
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
      return crc32c(acc, buf, bytes) ^ 0xffffffff;
  }
 -/* Return the exception level to which FP-disabled exceptions should
 +/*
 + * Return the exception level to which FP-disabled exceptions should
   * be taken, or 0 if FP is enabled.
   */
  int fp_exception_el(CPUARMState *env, int cur_el)
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
  #ifndef CONFIG_USER_ONLY
      uint64_t hcr_el2;
 -    /* CPACR and the CPTR registers don't exist before v6, so FP is
 +    /*
 +     * CPACR and the CPTR registers don't exist before v6, so FP is
       * always accessible
       */
      if (!arm_feature(env, ARM_FEATURE_V6)) {
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
      hcr_el2 = arm_hcr_el2_eff(env);
 -    /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
 +    /*
 +     * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
       * 0, 2 : trap EL0 and EL1/PL1 accesses
       * 1    : trap only EL0 accesses
       * 3    : trap no accesses
 --
-.25.1
+.34.1

-[PULL 19/34] target/arm: Fix checkpatch space errors in helper.c
+[PULL 22/33] target/arm: Mark up sysregs for HFGRTR bits 24..35
-From: Fabiano Rosas <farosas@suse.de>
+Mark up the sysreg definitions for the registers trapped
 by HFGRTR/HFGWTR bits 24..35.
-Fix the following:
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
 ---
  target/arm/cpregs.h | 12 ++++++++++++
  target/arm/helper.c | 14 ++++++++++++++
 files changed, 26 insertions(+)
-ERROR: spaces required around that '|' (ctx:VxV)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
-ERROR: space required before the open parenthesis '('
+index XXXXXXX..XXXXXXX 100644
-ERROR: spaces required around that '+' (ctx:VxB)
+--- a/target/arm/cpregs.h
-ERROR: space prohibited between function name and open parenthesis '('
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-(the last two still have some occurrences in macros which I left
+     DO_BIT(HFGRTR, LORID_EL1),
-behind because it might impact readability)
+     DO_BIT(HFGRTR, LORN_EL1),
+     DO_BIT(HFGRTR, LORSA_EL1),
-Signed-off-by: Fabiano Rosas <farosas@suse.de>
++    DO_BIT(HFGRTR, MAIR_EL1),
-Reviewed-by: Claudio Fontana <cfontana@suse.de>
++    DO_BIT(HFGRTR, MIDR_EL1),
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
++    DO_BIT(HFGRTR, MPIDR_EL1),
-Message-id: 20221213190537.511-3-farosas@suse.de
++    DO_BIT(HFGRTR, PAR_EL1),
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++    DO_BIT(HFGRTR, REVIDR_EL1),
----
++    DO_BIT(HFGRTR, SCTLR_EL1),
- target/arm/helper.c | 42 +++++++++++++++++++++---------------------
++    DO_BIT(HFGRTR, SCXTNUM_EL1),
-file changed, 21 insertions(+), 21 deletions(-)
++    DO_BIT(HFGRTR, SCXTNUM_EL0),
++    DO_BIT(HFGRTR, TCR_EL1),
 +    DO_BIT(HFGRTR, TPIDR_EL1),
 +    DO_BIT(HFGRTR, TPIDRRO_EL0),
 +    DO_BIT(HFGRTR, TPIDR_EL0),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-     uint32_t regidx = (uintptr_t)key;
+     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
-     const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
--    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
++      .fgt = FGT_MAIR_EL1,
-+    if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
+       .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
-         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
+       .resetvalue = 0 },
-         /* The value array need not be initialized at this point */
+     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
          cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
      ri = g_hash_table_lookup(cpu->cp_regs, key);
 -    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 +    if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
          cpu->cpreg_array_len++;
      }
  }
 @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
+     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
+       .access = PL0_RW,
++      .fgt = FGT_TPIDR_EL0,
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
+     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
+       .access = PL0_RW,
++      .fgt = FGT_TPIDR_EL0,
+       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
+                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
        .resetfn = arm_cp_reset_ignore },
      { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
--      .access = PL0_R|PL1_W,
+       .access = PL0_R | PL1_W,
-+      .access = PL0_R | PL1_W,
++      .fgt = FGT_TPIDRRO_EL0,
        .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
        .resetvalue = 0},
      { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
--      .access = PL0_R|PL1_W,
+       .access = PL0_R | PL1_W,
-+      .access = PL0_R | PL1_W,
++      .fgt = FGT_TPIDRRO_EL0,
        .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
                               offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
        .resetfn = arm_cp_reset_ignore },
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
+     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
-       .resetvalue = 0 },
+       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
-     /* The cache ops themselves: these all NOP for QEMU */
+       .access = PL1_RW,
-     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
++      .fgt = FGT_TPIDR_EL1,
--      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
-+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
+     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
-     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
+       .access = PL1_RW,
--      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
-+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
+     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
-     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
+       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
--      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+       .access = PL1_RW, .accessfn = access_tvm_trvm,
-+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
++      .fgt = FGT_TCR_EL1,
-     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
+       .writefn = vmsa_tcr_el12_write,
--      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+       .raw_writefn = raw_write,
-+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
+       .resetvalue = 0,
-     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
--      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+       .type = ARM_CP_ALIAS,
-+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
+       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
-     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
+       .access = PL1_RW, .resetvalue = 0,
--      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
++      .fgt = FGT_PAR_EL1,
-+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
+       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
- };
+       .writefn = par_write },
+ #endif
- static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
      { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
        .access = PL0_RW, .accessfn = access_scxtnum,
 +      .fgt = FGT_SCXTNUM_EL0,
        .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
      { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
        .access = PL1_RW, .accessfn = access_scxtnum,
 +      .fgt = FGT_SCXTNUM_EL1,
        .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
      { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
 @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             ARMCPRegInfo cbar = {
+             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
-                 .name = "CBAR",
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
-                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
+               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
--                .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
++              .fgt = FGT_MIDR_EL1,
-+                .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
+               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
-                 .fieldoffset = offsetof(CPUARMState,
+               .readfn = midr_read },
-                                         cp15.c15_config_base_address)
+             /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
-             };
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
+               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
-         return;
+               .access = PL1_R,
+               .accessfn = access_aa64_tid1,
-     if (old_mode == ARM_CPU_MODE_FIQ) {
++              .fgt = FGT_REVIDR_EL1,
--        memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
+               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
--        memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
+         };
-+        memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
+         ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
-+        memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-     } else if (mode == ARM_CPU_MODE_FIQ) {
+         ARMCPRegInfo mpidr_cp_reginfo[] = {
--        memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
+             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
--        memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
+               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
-+        memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
++              .fgt = FGT_MPIDR_EL1,
-+        memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
+               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
-     }
+         };
+ #ifdef CONFIG_USER_ONLY
-     i = bank_number(old_mode);
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
+             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
-     RESULT(sum, n, 16); \
+             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
-     if (sum >= 0) \
+             .access = PL1_RW, .accessfn = access_tvm_trvm,
-         ge |= 3 << (n * 2); \
++            .fgt = FGT_SCTLR_EL1,
--    } while(0)
+             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
-+    } while (0)
+                                    offsetof(CPUARMState, cp15.sctlr_ns) },
+             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
  #define SARITH8(a, b, n, op) do { \
      int32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
      RESULT(sum, n, 8); \
      if (sum >= 0) \
          ge |= 1 << n; \
 -    } while(0)
 +    } while (0)
  #define ADD16(a, b, n) SARITH16(a, b, n, +)
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
      RESULT(sum, n, 16); \
      if ((sum >> 16) == 1) \
          ge |= 3 << (n * 2); \
 -    } while(0)
 +    } while (0)
  #define ADD8(a, b, n) do { \
      uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
      RESULT(sum, n, 8); \
      if ((sum >> 8) == 1) \
          ge |= 1 << n; \
 -    } while(0)
 +    } while (0)
  #define SUB16(a, b, n) do { \
      uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
      RESULT(sum, n, 16); \
      if ((sum >> 16) == 0) \
          ge |= 3 << (n * 2); \
 -    } while(0)
 +    } while (0)
  #define SUB8(a, b, n) do { \
      uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
      RESULT(sum, n, 8); \
      if ((sum >> 8) == 0) \
          ge |= 1 << n; \
 -    } while(0)
 +    } while (0)
  #define PFX u
  #define ARITH_GE
 --
-.25.1
+.34.1

-[PULL 30/34] i.MX7D: Connect GPT timers to IRQ
+[PULL 23/33] target/arm: Mark up sysregs for HFGRTR bits 36..63
-From: Jean-Christophe Dubois <jcd@tribudubois.net>
+Mark up the sysreg definitions for the registers trapped
 by HFGRTR/HFGWTR bits 36..63.
-So far the GPT timers were unable to raise IRQs to the processor.
+Of these, some correspond to RAS registers which we implement as
 always-UNDEF: these don't need any extra handling for FGT because the
 UNDEF-to-EL1 always takes priority over any theoretical
 FGT-trap-to-EL2.
-Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+of the FEAT_LS64_ACCDATA feature which we don't yet implement.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-14-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-14-peter.maydell@linaro.org
 ---
- include/hw/arm/fsl-imx7.h |  5 +++++
+ target/arm/cpregs.h       |  7 +++++++
- hw/arm/fsl-imx7.c         | 10 ++++++++++
+ hw/intc/arm_gicv3_cpuif.c |  2 ++
-files changed, 15 insertions(+)
+ target/arm/helper.c       | 10 ++++++++++
 files changed, 19 insertions(+)
-diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx7.h
+--- a/target/arm/cpregs.h
-+++ b/include/hw/arm/fsl-imx7.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-     FSL_IMX7_USB2_IRQ     = 42,
+     DO_BIT(HFGRTR, TPIDR_EL1),
-     FSL_IMX7_USB3_IRQ     = 40,
+     DO_BIT(HFGRTR, TPIDRRO_EL0),
+     DO_BIT(HFGRTR, TPIDR_EL0),
-+    FSL_IMX7_GPT1_IRQ     = 55,
++    DO_BIT(HFGRTR, TTBR0_EL1),
-+    FSL_IMX7_GPT2_IRQ     = 54,
++    DO_BIT(HFGRTR, TTBR1_EL1),
-+    FSL_IMX7_GPT3_IRQ     = 53,
++    DO_BIT(HFGRTR, VBAR_EL1),
-+    FSL_IMX7_GPT4_IRQ     = 52,
++    DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
-+
++    DO_BIT(HFGRTR, ERRIDR_EL1),
-     FSL_IMX7_WDOG1_IRQ    = 78,
++    DO_REV_BIT(HFGRTR, NSMPRI_EL1),
-     FSL_IMX7_WDOG2_IRQ    = 79,
++    DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
-     FSL_IMX7_WDOG3_IRQ    = 10,
+ } FGTBit;
-diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
  #undef DO_BIT
 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/fsl-imx7.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/arm/fsl-imx7.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-             FSL_IMX7_GPT4_ADDR,
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
-         };
+       .type = ARM_CP_IO | ARM_CP_NO_RAW,
+       .access = PL1_RW, .accessfn = gicv3_fiq_access,
-+        static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
++      .fgt = FGT_ICC_IGRPENN_EL1,
-+            FSL_IMX7_GPT1_IRQ,
+       .readfn = icc_igrpen_read,
-+            FSL_IMX7_GPT2_IRQ,
+       .writefn = icc_igrpen_write,
-+            FSL_IMX7_GPT3_IRQ,
+     },
-+            FSL_IMX7_GPT4_IRQ,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
-+        };
+       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
-+
+       .type = ARM_CP_IO | ARM_CP_NO_RAW,
-         s->gpt[i].ccm = IMX_CCM(&s->ccm);
+       .access = PL1_RW, .accessfn = gicv3_irq_access,
-         sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
++      .fgt = FGT_ICC_IGRPENN_EL1,
-         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
+       .readfn = icc_igrpen_read,
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
+       .writefn = icc_igrpen_write,
-+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+     },
-+                                            FSL_IMX7_GPTn_IRQ[i]));
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-     }
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
-     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
++++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
      { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_TTBR0_EL1,
        .writefn = vmsa_ttbr_write, .resetvalue = 0,
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
                               offsetof(CPUARMState, cp15.ttbr0_ns) } },
      { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .fgt = FGT_TTBR1_EL1,
        .writefn = vmsa_ttbr_write, .resetvalue = 0,
        .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                               offsetof(CPUARMState, cp15.ttbr1_ns) } },
@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
   *   ERRSELR_EL1
   * may generate UNDEFINED, which is the effect we get by not
   * listing them at all.
 + *
 + * These registers have fine-grained trap bits, but UNDEF-to-EL1
 + * is higher priority than FGT-to-EL2 so we do not need to list them
 + * in order to check for an FGT.
   */
  static const ARMCPRegInfo minimal_ras_reginfo[] = {
      { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
      { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
        .access = PL1_R, .accessfn = access_terr,
 +      .fgt = FGT_ERRIDR_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
      { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
        .access = PL0_RW, .accessfn = access_tpidr2,
 +      .fgt = FGT_NTPIDR2_EL0,
        .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
      { .name = "SVCR", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
      { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
        .access = PL1_RW, .accessfn = access_esm,
 +      .fgt = FGT_NSMPRI_EL1,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
                .access = PL1_RW, .writefn = vbar_write,
 +              .fgt = FGT_VBAR_EL1,
                .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                       offsetof(CPUARMState, cp15.vbar_ns) },
                .resetvalue = 0 },
 --
-.25.1
+.34.1

-[PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
+[PULL 24/33] target/arm: Mark up sysregs for HDFGRTR bits 0..11
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Mark up the sysreg definitons for the registers trapped
 by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
 related registers.
-ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-tough they don't have the TTBCR register.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
+Tested-by: Fuad Tabba <tabba@google.com>
-AArch32 architecture profile Version:A.c section C1.2.
+Message-id: 20230130182459.3309057-15-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-15-peter.maydell@linaro.org
 ---
  target/arm/cpregs.h       | 12 ++++++++++++
  target/arm/debug_helper.c | 11 +++++++++++
 files changed, 23 insertions(+)
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/internals.h    | 4 ++++
  target/arm/debug_helper.c | 3 +++
  target/arm/tlb_helper.c   | 4 ++++
 files changed, 11 insertions(+)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/internals.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/internals.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu);
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- static inline bool extended_addresses_enabled(CPUARMState *env)
+     DO_BIT(HFGRTR, ERRIDR_EL1),
- {
+     DO_REV_BIT(HFGRTR, NSMPRI_EL1),
-     uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
+     DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
-+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
++
-+        arm_feature(env, ARM_FEATURE_V8)) {
++    /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
-+        return true;
++    DO_BIT(HDFGRTR, DBGBCRN_EL1),
-+    }
++    DO_BIT(HDFGRTR, DBGBVRN_EL1),
-     return arm_el_is_aa64(env, 1) ||
++    DO_BIT(HDFGRTR, DBGWCRN_EL1),
-            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
++    DO_BIT(HDFGRTR, DBGWVRN_EL1),
- }
++    DO_BIT(HDFGRTR, MDSCR_EL1),
 +    DO_BIT(HDFGRTR, DBGCLAIM),
 +    DO_BIT(HDFGWTR, OSLAR_EL1),
 +    DO_BIT(HDFGRTR, OSLSR_EL1),
 +    DO_BIT(HDFGRTR, OSECCR_EL1),
 +    DO_BIT(HDFGRTR, OSDLR_EL1),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/debug_helper.c
 +++ b/target/arm/debug_helper.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
-     if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
-         using_lpae = true;
+       .access = PL1_RW, .accessfn = access_tda,
-+    } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
++      .fgt = FGT_MDSCR_EL1,
-+               arm_feature(env, ARM_FEATURE_V8)) {
+       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
-+        using_lpae = true;
+       .resetvalue = 0 },
-     } else {
+     /*
-         if (arm_feature(env, ARM_FEATURE_LPAE) &&
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-             (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
+     { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
-diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
+       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
-index XXXXXXX..XXXXXXX 100644
+       .access = PL1_RW, .accessfn = access_tda,
---- a/target/arm/tlb_helper.c
++      .fgt = FGT_OSECCR_EL1,
-+++ b/target/arm/tlb_helper.c
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-@@ -XXX,XX +XXX,XX @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
+     /*
-     if (el == 2 || arm_el_is_aa64(env, el)) {
+      * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
-         return true;
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-     }
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
-+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
+       .access = PL1_W, .type = ARM_CP_NO_RAW,
-+        arm_feature(env, ARM_FEATURE_V8)) {
+       .accessfn = access_tdosa,
-+        return true;
++      .fgt = FGT_OSLAR_EL1,
-+    }
+       .writefn = oslar_write },
-     if (arm_feature(env, ARM_FEATURE_LPAE)
+     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
-         && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
-         return true;
+       .access = PL1_R, .resetvalue = 10,
        .accessfn = access_tdosa,
 +      .fgt = FGT_OSLSR_EL1,
        .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
      /* Dummy OSDLR_EL1: 32-bit Linux will read this */
      { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
        .access = PL1_RW, .accessfn = access_tdosa,
 +      .fgt = FGT_OSDLR_EL1,
        .writefn = osdlr_write,
        .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
      /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
        .type = ARM_CP_ALIAS,
        .access = PL1_RW, .accessfn = access_tda,
 +      .fgt = FGT_DBGCLAIM,
        .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
      { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
        .access = PL1_RW, .accessfn = access_tda,
 +      .fgt = FGT_DBGCLAIM,
        .writefn = dbgclaimclr_write, .raw_writefn = raw_write,
        .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
  };
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
              { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
                .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
                .access = PL1_RW, .accessfn = access_tda,
 +              .fgt = FGT_DBGBVRN_EL1,
                .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
                .writefn = dbgbvr_write, .raw_writefn = raw_write
              },
              { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
                .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
                .access = PL1_RW, .accessfn = access_tda,
 +              .fgt = FGT_DBGBCRN_EL1,
                .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
                .writefn = dbgbcr_write, .raw_writefn = raw_write
              },
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
              { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
                .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
                .access = PL1_RW, .accessfn = access_tda,
 +              .fgt = FGT_DBGWVRN_EL1,
                .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
                .writefn = dbgwvr_write, .raw_writefn = raw_write
              },
              { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
                .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
                .access = PL1_RW, .accessfn = access_tda,
 +              .fgt = FGT_DBGWCRN_EL1,
                .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
                .writefn = dbgwcr_write, .raw_writefn = raw_write
              },
 --
-.25.1
+.34.1

-[PULL 21/34] target/arm: Remove unused includes from m_helper.c
+[PULL 25/33] target/arm: Mark up sysregs for HDFGRTR bits 12..63
-From: Fabiano Rosas <farosas@suse.de>
+Mark up the sysreg definitions for the registers trapped
+by HDFGRTR/HDFGWTR bits 12..x.
-Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Reviewed-by: Claudio Fontana <cfontana@suse.de>
+Bits 12..22 and bit 58 are for PMU registers.
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
-Message-id: 20221213190537.511-5-farosas@suse.de
+The remaining bits in HDFGRTR/HDFGWTR are for traps on
 registers that are part of features we don't implement:
 Bits 23..32 and 63 : FEAT_SPE
 Bits 33..48 : FEAT_ETE
 Bits 50..56 : FEAT_TRBE
 Bits 59..61 : FEAT_BRBE
 Bit 62 : FEAT_SPEv1p2.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-16-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-16-peter.maydell@linaro.org
 ---
- target/arm/m_helper.c | 16 ----------------
+ target/arm/cpregs.h | 12 ++++++++++++
-file changed, 16 deletions(-)
+ target/arm/helper.c | 37 +++++++++++++++++++++++++++++++++++++
+files changed, 49 insertions(+)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/target/arm/cpregs.h
-+++ b/target/arm/m_helper.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-  */
+     DO_BIT(HDFGRTR, OSLSR_EL1),
+     DO_BIT(HDFGRTR, OSECCR_EL1),
- #include "qemu/osdep.h"
+     DO_BIT(HDFGRTR, OSDLR_EL1),
--#include "qemu/units.h"
++    DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
--#include "target/arm/idau.h"
++    DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
--#include "trace.h"
++    DO_BIT(HDFGRTR, PMCCFILTR_EL0),
- #include "cpu.h"
++    DO_BIT(HDFGRTR, PMCCNTR_EL0),
- #include "internals.h"
++    DO_BIT(HDFGRTR, PMCNTEN),
--#include "exec/gdbstub.h"
++    DO_BIT(HDFGRTR, PMINTEN),
- #include "exec/helper-proto.h"
++    DO_BIT(HDFGRTR, PMOVS),
--#include "qemu/host-utils.h"
++    DO_BIT(HDFGRTR, PMSELR_EL0),
- #include "qemu/main-loop.h"
++    DO_BIT(HDFGWTR, PMSWINC_EL0),
- #include "qemu/bitops.h"
++    DO_BIT(HDFGWTR, PMCR_EL0),
--#include "qemu/crc32c.h"
++    DO_BIT(HDFGRTR, PMMIR_EL1),
--#include "qemu/qemu-print.h"
++    DO_BIT(HDFGRTR, PMCEIDN_EL0),
- #include "qemu/log.h"
+ } FGTBit;
- #include "exec/exec-all.h"
--#include <zlib.h> /* For crc32 */
+ #undef DO_BIT
--#include "semihosting/semihost.h"
+diff --git a/target/arm/helper.c b/target/arm/helper.c
--#include "sysemu/cpus.h"
+index XXXXXXX..XXXXXXX 100644
--#include "sysemu/kvm.h"
+--- a/target/arm/helper.c
--#include "qemu/range.h"
++++ b/target/arm/helper.c
--#include "qapi/qapi-commands-machine-target.h"
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
--#include "qapi/error.h"
+       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
--#include "qemu/guest-random.h"
+       .writefn = pmcntenset_write,
- #ifdef CONFIG_TCG
+       .accessfn = pmreg_access,
--#include "arm_ldst.h"
++      .fgt = FGT_PMCNTEN,
- #include "exec/cpu_ldst.h"
+       .raw_writefn = raw_write },
- #include "semihosting/common-semi.h"
+     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
- #endif
+       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMCNTEN,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
        .writefn = pmcntenset_write, .raw_writefn = raw_write },
      { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
        .access = PL0_RW,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMCNTEN,
        .writefn = pmcntenclr_write,
        .type = ARM_CP_ALIAS | ARM_CP_IO },
      { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMCNTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
        .writefn = pmcntenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .access = PL0_RW, .type = ARM_CP_IO,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .writefn = pmovsr_write,
        .raw_writefn = raw_write },
      { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsr_write,
        .raw_writefn = raw_write },
      { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
        .access = PL0_W, .accessfn = pmreg_access_swinc,
 +      .fgt = FGT_PMSWINC_EL0,
        .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .writefn = pmswinc_write },
      { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
        .access = PL0_W, .accessfn = pmreg_access_swinc,
 +      .fgt = FGT_PMSWINC_EL0,
        .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .writefn = pmswinc_write },
      { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
        .access = PL0_RW, .type = ARM_CP_ALIAS,
 +      .fgt = FGT_PMSELR_EL0,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
        .accessfn = pmreg_access_selr, .writefn = pmselr_write,
        .raw_writefn = raw_write},
      { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
        .access = PL0_RW, .accessfn = pmreg_access_selr,
 +      .fgt = FGT_PMSELR_EL0,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
        .writefn = pmselr_write, .raw_writefn = raw_write, },
      { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
        .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
 +      .fgt = FGT_PMCCNTR_EL0,
        .readfn = pmccntr_read, .writefn = pmccntr_write32,
        .accessfn = pmreg_access_ccntr },
      { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
        .access = PL0_RW, .accessfn = pmreg_access_ccntr,
 +      .fgt = FGT_PMCCNTR_EL0,
        .type = ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
        .readfn = pmccntr_read, .writefn = pmccntr_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
        .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMCCFILTR_EL0,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .resetvalue = 0, },
      { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
        .writefn = pmccfiltr_write, .raw_writefn = raw_write,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMCCFILTR_EL0,
        .type = ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
        .resetvalue = 0, },
      { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMEVTYPERN_EL0,
        .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
      { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access,
 +      .fgt = FGT_PMEVTYPERN_EL0,
        .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
      { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access_xevcntr,
 +      .fgt = FGT_PMEVCNTRN_EL0,
        .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
      { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
        .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
        .accessfn = pmreg_access_xevcntr,
 +      .fgt = FGT_PMEVCNTRN_EL0,
        .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
      { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
        .access = PL0_R | PL1_RW, .accessfn = access_tpm,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
        .writefn = pmuserenr_write, .raw_writefn = raw_write },
      { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
        .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
      { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenset_write, .raw_writefn = raw_write,
        .resetvalue = 0x0 },
      { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenclr_write, },
      { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
        .access = PL1_RW, .accessfn = access_tpm,
 +      .fgt = FGT_PMINTEN,
        .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
        .writefn = pmintenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
      /* PMOVSSET is not implemented in v7 before v7ve */
      { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
      { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
        .access = PL0_RW, .accessfn = pmreg_access,
 +      .fgt = FGT_PMOVS,
        .type = ARM_CP_ALIAS | ARM_CP_IO,
        .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
        .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
      ARMCPRegInfo pmcr = {
          .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
          .access = PL0_RW,
 +        .fgt = FGT_PMCR_EL0,
          .type = ARM_CP_IO | ARM_CP_ALIAS,
          .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
          .accessfn = pmreg_access, .writefn = pmcr_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
          .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
          .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
          .access = PL0_RW, .accessfn = pmreg_access,
 +        .fgt = FGT_PMCR_EL0,
          .type = ARM_CP_IO,
          .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
          .resetvalue = cpu->isar.reset_pmcr_el0,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              { .name = pmevcntr_name, .cp = 15, .crn = 14,
                .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
 +              .fgt = FGT_PMEVCNTRN_EL0,
                .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                .accessfn = pmreg_access_xevcntr },
              { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
                .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
                .type = ARM_CP_IO,
 +              .fgt = FGT_PMEVCNTRN_EL0,
                .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                .raw_readfn = pmevcntr_rawread,
                .raw_writefn = pmevcntr_rawwrite },
              { .name = pmevtyper_name, .cp = 15, .crn = 14,
                .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
 +              .fgt = FGT_PMEVTYPERN_EL0,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .accessfn = pmreg_access },
              { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
                .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
 +              .fgt = FGT_PMEVTYPERN_EL0,
                .type = ARM_CP_IO,
                .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                .raw_writefn = pmevtyper_rawwrite },
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid0, 32, 32) },
              { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid1, 32, 32) },
          };
          define_arm_cp_regs(cpu, v81_pmu_regs);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
              .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
              .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
              .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +            .fgt = FGT_PMMIR_EL1,
              .resetvalue = 0
          };
          define_one_arm_cp_reg(cpu, &v84_pmmir);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid0, 0, 32) },
              { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = cpu->pmceid0 },
              { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
                .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = extract64(cpu->pmceid1, 0, 32) },
              { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
                .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
                .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
 +              .fgt = FGT_PMCEIDN_EL0,
                .resetvalue = cpu->pmceid1 },
          };
  #ifdef CONFIG_USER_ONLY
 --
-.25.1
+.34.1

-[PULL 22/34] target/arm: Remove unused includes from helper.c
+[PULL 26/33] target/arm: Mark up sysregs for HFGITR bits 0..11
-From: Fabiano Rosas <farosas@suse.de>
+Mark up the sysreg definitions for the system instructions
 trapped by HFGITR bits 0..11. These bits cover various
 cache maintenance operations.
-Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Reviewed-by: Claudio Fontana <cfontana@suse.de>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
-Message-id: 20221213190537.511-6-farosas@suse.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-17-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-17-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 7 -------
+ target/arm/cpregs.h | 14 ++++++++++++++
-file changed, 7 deletions(-)
+ target/arm/helper.c | 28 ++++++++++++++++++++++++++++
 files changed, 42 insertions(+)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
+     DO_BIT(HDFGWTR, PMCR_EL0),
+     DO_BIT(HDFGRTR, PMMIR_EL1),
+     DO_BIT(HDFGRTR, PMCEIDN_EL0),
++
++    /* Trap bits in HFGITR_EL2, starting from bit 0 */
++    DO_BIT(HFGITR, ICIALLUIS),
++    DO_BIT(HFGITR, ICIALLU),
++    DO_BIT(HFGITR, ICIVAU),
++    DO_BIT(HFGITR, DCIVAC),
++    DO_BIT(HFGITR, DCISW),
++    DO_BIT(HFGITR, DCCSW),
++    DO_BIT(HFGITR, DCCISW),
++    DO_BIT(HFGITR, DCCVAU),
++    DO_BIT(HFGITR, DCCVAP),
++    DO_BIT(HFGITR, DCCVADP),
++    DO_BIT(HFGITR, DCCIVAC),
++    DO_BIT(HFGITR, DCZVA),
+ } FGTBit;
+ #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-  */
+ #ifndef CONFIG_USER_ONLY
+       /* Avoid overhead of an access check that always passes in user-mode */
- #include "qemu/osdep.h"
+       .accessfn = aa64_zva_access,
--#include "qemu/units.h"
++      .fgt = FGT_DCZVA,
  #include "qemu/log.h"
  #include "trace.h"
  #include "cpu.h"
  #include "internals.h"
  #include "exec/helper-proto.h"
 -#include "qemu/host-utils.h"
  #include "qemu/main-loop.h"
  #include "qemu/timer.h"
  #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@
  #include "exec/exec-all.h"
  #include <zlib.h> /* For crc32 */
  #include "hw/irq.h"
 -#include "semihosting/semihost.h"
 -#include "sysemu/cpus.h"
  #include "sysemu/cpu-timers.h"
  #include "sysemu/kvm.h"
 -#include "qemu/range.h"
  #include "qapi/qapi-commands-machine-target.h"
  #include "qapi/error.h"
  #include "qemu/guest-random.h"
  #ifdef CONFIG_TCG
 -#include "arm_ldst.h"
 -#include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
- #include "cpregs.h"
+     },
      { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
      { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
        .access = PL1_W, .type = ARM_CP_NOP,
 +      .fgt = FGT_ICIALLUIS,
        .accessfn = access_ticab },
      { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
        .access = PL1_W, .type = ARM_CP_NOP,
 +      .fgt = FGT_ICIALLU,
        .accessfn = access_tocu },
      { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NOP,
 +      .fgt = FGT_ICIVAU,
        .accessfn = access_tocu },
      { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
        .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
 +      .fgt = FGT_DCIVAC,
        .type = ARM_CP_NOP },
      { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
 +      .fgt = FGT_DCISW,
        .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
      { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
 +      .fgt = FGT_DCCSW,
        .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
      { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NOP,
 +      .fgt = FGT_DCCVAU,
        .accessfn = access_tocu },
      { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NOP,
 +      .fgt = FGT_DCCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
 +      .fgt = FGT_DCCISW,
        .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
      /* TLBI operations */
      { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
      { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
 +      .fgt = FGT_DCCVAP,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
  };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
      { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
        .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
 +      .fgt = FGT_DCCVADP,
        .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
  };
  #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
      { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL1_W,
 +      .fgt = FGT_DCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
 +      .fgt = FGT_DCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL1_W,
 +      .fgt = FGT_DCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
 +      .fgt = FGT_DCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
 +      .fgt = FGT_DCCSW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
 +      .fgt = FGT_DCCSW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
 +      .fgt = FGT_DCCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
      { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
 +      .fgt = FGT_DCCISW,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
  };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
      { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVAP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVAP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVADP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCVADP,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
        .type = ARM_CP_NOP, .access = PL0_W,
 +      .fgt = FGT_DCCIVAC,
        .accessfn = aa64_cacheop_poc_access },
      { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
  #ifndef CONFIG_USER_ONLY
        /* Avoid overhead of an access check that always passes in user-mode */
        .accessfn = aa64_zva_access,
 +      .fgt = FGT_DCZVA,
  #endif
      },
      { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
  #ifndef CONFIG_USER_ONLY
        /* Avoid overhead of an access check that always passes in user-mode */
        .accessfn = aa64_zva_access,
 +      .fgt = FGT_DCZVA,
  #endif
      },
  };
 --
-.25.1
+.34.1

-[PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access
+[PULL 27/33] target/arm: Mark up sysregs for HFGITR bits 12..17
-From: Axel Heider <axel.heider@hensoldt.net>
+Mark up the sysreg definitions for the system instructions
 trapped by HFGITR bits 12..17. These bits cover AT address
 translation instructions.
-The interrupt state can change due to:
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-- reset clears both SR.OCIF and CR.OCIE
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-- write to CR.EN or CR.OCIE
+Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-18-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-18-peter.maydell@linaro.org
 ---
  target/arm/cpregs.h | 6 ++++++
  target/arm/helper.c | 6 ++++++
 files changed, 12 insertions(+)
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/timer/imx_epit.c | 16 ++++++++++++----
 file changed, 12 insertions(+), 4 deletions(-)
 diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/target/arm/cpregs.h
-+++ b/hw/timer/imx_epit.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-         if (s->cr & CR_SWR) {
+     DO_BIT(HFGITR, DCCVADP),
-             /* handle the reset */
+     DO_BIT(HFGITR, DCCIVAC),
-             imx_epit_reset(DEVICE(s));
+     DO_BIT(HFGITR, DCZVA),
--            /*
++    DO_BIT(HFGITR, ATS1E1R),
--             * TODO: could we 'break' here? following operations appear
++    DO_BIT(HFGITR, ATS1E1W),
--             * to duplicate the work imx_epit_reset() already did.
++    DO_BIT(HFGITR, ATS1E0R),
--             */
++    DO_BIT(HFGITR, ATS1E0W),
-         }
++    DO_BIT(HFGITR, ATS1E1RP),
++    DO_BIT(HFGITR, ATS1E1WP),
-+        /*
+ } FGTBit;
-+         * The interrupt state can change due to:
-+         * - reset clears both SR.OCIF and CR.OCIE
+ #undef DO_BIT
-+         * - write to CR.EN or CR.OCIE
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-+         */
+index XXXXXXX..XXXXXXX 100644
-+        imx_epit_update_int(s);
+--- a/target/arm/helper.c
-+
++++ b/target/arm/helper.c
-+        /*
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-+         * TODO: could we 'break' here for reset? following operations appear
+     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
-+         * to duplicate the work imx_epit_reset() already did.
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
-+         */
+       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
-+
++      .fgt = FGT_ATS1E1R,
-         ptimer_transaction_begin(s->timer_cmp);
+       .writefn = ats_write64 },
-         ptimer_transaction_begin(s->timer_reload);
+     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
 +      .fgt = FGT_ATS1E1W,
        .writefn = ats_write64 },
      { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
 +      .fgt = FGT_ATS1E0R,
        .writefn = ats_write64 },
      { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
 +      .fgt = FGT_ATS1E0W,
        .writefn = ats_write64 },
      { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
      { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
 +      .fgt = FGT_ATS1E1RP,
        .writefn = ats_write64 },
      { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
        .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
 +      .fgt = FGT_ATS1E1WP,
        .writefn = ats_write64 },
  };
 --
-.25.1
+.34.1

-[PULL 12/34] hw/timer/imx_epit: define SR_OCIF
+[PULL 28/33] target/arm: Mark up sysregs for HFGITR bits 18..47
-From: Axel Heider <axel.heider@hensoldt.net>
+Mark up the sysreg definitions for the system instructions
 trapped by HFGITR bits 18..47. These bits cover TLBI
 TLB maintenance instructions.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+(If we implemented FEAT_XS we would need to trap some of the
 instructions added by that feature using these bits; but we don't
 yet, so will need to add the .fgt markup when we do.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-19-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-19-peter.maydell@linaro.org
 ---
- include/hw/timer/imx_epit.h |  2 ++
+ target/arm/cpregs.h | 30 ++++++++++++++++++++++++++++++
- hw/timer/imx_epit.c         | 12 ++++++------
+ target/arm/helper.c | 30 ++++++++++++++++++++++++++++++
-files changed, 8 insertions(+), 6 deletions(-)
+files changed, 60 insertions(+)
-diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/imx_epit.h
+--- a/target/arm/cpregs.h
-+++ b/include/hw/timer/imx_epit.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
- #define CR_CLKSRC_SHIFT (24)
+     DO_BIT(HFGITR, ATS1E0W),
- #define CR_CLKSRC_BITS  (2)
+     DO_BIT(HFGITR, ATS1E1RP),
+     DO_BIT(HFGITR, ATS1E1WP),
-+#define SR_OCIF     (1 << 0)
++    DO_BIT(HFGITR, TLBIVMALLE1OS),
-+
++    DO_BIT(HFGITR, TLBIVAE1OS),
- #define EPIT_TIMER_MAX  0XFFFFFFFFUL
++    DO_BIT(HFGITR, TLBIASIDE1OS),
++    DO_BIT(HFGITR, TLBIVAAE1OS),
- #define TYPE_IMX_EPIT "imx.epit"
++    DO_BIT(HFGITR, TLBIVALE1OS),
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
++    DO_BIT(HFGITR, TLBIVAALE1OS),
 +    DO_BIT(HFGITR, TLBIRVAE1OS),
 +    DO_BIT(HFGITR, TLBIRVAAE1OS),
 +    DO_BIT(HFGITR, TLBIRVALE1OS),
 +    DO_BIT(HFGITR, TLBIRVAALE1OS),
 +    DO_BIT(HFGITR, TLBIVMALLE1IS),
 +    DO_BIT(HFGITR, TLBIVAE1IS),
 +    DO_BIT(HFGITR, TLBIASIDE1IS),
 +    DO_BIT(HFGITR, TLBIVAAE1IS),
 +    DO_BIT(HFGITR, TLBIVALE1IS),
 +    DO_BIT(HFGITR, TLBIVAALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAE1IS),
 +    DO_BIT(HFGITR, TLBIRVAAE1IS),
 +    DO_BIT(HFGITR, TLBIRVALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAALE1IS),
 +    DO_BIT(HFGITR, TLBIRVAE1),
 +    DO_BIT(HFGITR, TLBIRVAAE1),
 +    DO_BIT(HFGITR, TLBIRVALE1),
 +    DO_BIT(HFGITR, TLBIRVAALE1),
 +    DO_BIT(HFGITR, TLBIVMALLE1),
 +    DO_BIT(HFGITR, TLBIVAE1),
 +    DO_BIT(HFGITR, TLBIASIDE1),
 +    DO_BIT(HFGITR, TLBIVAAE1),
 +    DO_BIT(HFGITR, TLBIVALE1),
 +    DO_BIT(HFGITR, TLBIVAALE1),
  } FGTBit;
  #undef DO_BIT
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/target/arm/helper.c
-+++ b/hw/timer/imx_epit.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static const IMXClk imx_epit_clocks[] =  {
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-  */
+     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
- static void imx_epit_update_int(IMXEPITState *s)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
- {
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
--    if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
++      .fgt = FGT_TLBIVMALLE1IS,
-+    if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
+       .writefn = tlbi_aa64_vmalle1is_write },
-         qemu_irq_raise(s->irq);
+     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
-     } else {
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
-         qemu_irq_lower(s->irq);
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
++      .fgt = FGT_TLBIVAE1IS,
-         break;
+       .writefn = tlbi_aa64_vae1is_write },
+     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
-     case 1: /* SR - ACK*/
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
--        /* writing 1 to OCIF clears the OCIF bit */
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
--        if (value & 0x01) {
++      .fgt = FGT_TLBIASIDE1IS,
--            s->sr = 0;
+       .writefn = tlbi_aa64_vmalle1is_write },
-+        /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
+     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
-+        if (value & SR_OCIF) {
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
-+            s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-             imx_epit_update_int(s);
++      .fgt = FGT_TLBIVAAE1IS,
-         }
+       .writefn = tlbi_aa64_vae1is_write },
-         break;
+     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
-     IMXEPITState *s = IMX_EPIT(opaque);
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
++      .fgt = FGT_TLBIVALE1IS,
-     DPRINTF("sr was %d\n", s->sr);
+       .writefn = tlbi_aa64_vae1is_write },
--
+     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
--    s->sr = 1;
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
-+    /* Set interrupt status bit SR.OCIF and update the interrupt state */
+       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
-+    s->sr |= SR_OCIF;
++      .fgt = FGT_TLBIVAALE1IS,
-     imx_epit_update_int(s);
+       .writefn = tlbi_aa64_vae1is_write },
- }
+     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVMALLE1,
        .writefn = tlbi_aa64_vmalle1_write },
      { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAE1,
        .writefn = tlbi_aa64_vae1_write },
      { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIASIDE1,
        .writefn = tlbi_aa64_vmalle1_write },
      { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAAE1,
        .writefn = tlbi_aa64_vae1_write },
      { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVALE1,
        .writefn = tlbi_aa64_vae1_write },
      { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAALE1,
        .writefn = tlbi_aa64_vae1_write },
      { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
      { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
        .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAE1IS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAAE1IS,
        .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVALE1IS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAALE1IS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAE1OS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAAE1OS,
        .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVALE1OS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAALE1OS,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAE1,
        .writefn = tlbi_aa64_rvae1_write },
      { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAAE1,
        .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVALE1,
        .writefn = tlbi_aa64_rvae1_write },
      { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIRVAALE1,
        .writefn = tlbi_aa64_rvae1_write },
      { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
      { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVMALLE1OS,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
 +      .fgt = FGT_TLBIVAE1OS,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIASIDE1OS,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAAE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVALE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
        .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
 +      .fgt = FGT_TLBIVAALE1OS,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 --
-.25.1
+.34.1

-[PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs
+[PULL 29/33] target/arm: Mark up sysregs for HFGITR bits 48..63
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Mark up the sysreg definitions for the system instructions
 trapped by HFGITR bits 48..63.
-RVBAR shadows RVBAR_ELx where x is the highest exception
+Some of these bits are for trapping instructions which are
-level if the highest EL is not EL3. This patch also allows
+not in the system instruction encoding (i.e. which are
-ARMv8 CPUs to change the reset address with
+not handled by the ARMCPRegInfo mechanism):
-the rvbar property.
+ * ERET, ERETAA, ERETAB
  * SVC
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+We will have to handle those separately and manually.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-20-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-20-peter.maydell@linaro.org
 ---
- target/arm/cpu.c    |  6 +++++-
+ target/arm/cpregs.h | 4 ++++
- target/arm/helper.c | 21 ++++++++++++++-------
+ target/arm/helper.c | 9 +++++++++
-files changed, 19 insertions(+), 8 deletions(-)
+files changed, 13 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/cpregs.h
-+++ b/target/arm/cpu.c
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
+@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
-         env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
+     DO_BIT(HFGITR, TLBIVAAE1),
-                                          CPACR, CP11, 3);
+     DO_BIT(HFGITR, TLBIVALE1),
- #endif
+     DO_BIT(HFGITR, TLBIVAALE1),
-+        if (arm_feature(env, ARM_FEATURE_V8)) {
++    DO_BIT(HFGITR, CFPRCTX),
-+            env->cp15.rvbar = cpu->rvbar_prop;
++    DO_BIT(HFGITR, DVPRCTX),
-+            env->regs[15] = cpu->rvbar_prop;
++    DO_BIT(HFGITR, CPPRCTX),
-+        }
++    DO_BIT(HFGITR, DCCVAC),
-     }
+ } FGTBit;
- #if defined(CONFIG_USER_ONLY)
+ #undef DO_BIT
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
          qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
      }
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +    if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
          object_property_add_uint64_ptr(obj, "rvbar",
                                         &cpu->rvbar_prop,
                                         OBJ_PROP_FLAG_READWRITE);
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-         if (!arm_feature(env, ARM_FEATURE_EL3) &&
+     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
-             !arm_feature(env, ARM_FEATURE_EL2)) {
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
-             ARMCPRegInfo rvbar = {
+       .access = PL0_W, .type = ARM_CP_NOP,
--                .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
++      .fgt = FGT_DCCVAC,
-+                .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
+       .accessfn = aa64_cacheop_poc_access },
-                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
-                 .access = PL1_R,
+       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
-                 .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+     { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
-         }
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
-         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
+       .type = ARM_CP_NOP, .access = PL0_W,
-         if (!arm_feature(env, ARM_FEATURE_EL3)) {
++      .fgt = FGT_DCCVAC,
--            ARMCPRegInfo rvbar = {
+       .accessfn = aa64_cacheop_poc_access },
--                .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+     { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
--                .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
--                .access = PL2_R,
+       .type = ARM_CP_NOP, .access = PL0_W,
--                .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
++      .fgt = FGT_DCCVAC,
-+            ARMCPRegInfo rvbar[] = {
+       .accessfn = aa64_cacheop_poc_access },
-+                {
+     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
-+                    .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
-+                    .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
-+                    .access = PL2_R,
+ static const ARMCPRegInfo predinv_reginfo[] = {
-+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+     { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
-+                },
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
-+                {   .name = "RVBAR", .type = ARM_CP_ALIAS,
++      .fgt = FGT_CFPRCTX,
-+                    .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
-+                    .access = PL2_R,
+     { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
-+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
-+                },
++      .fgt = FGT_DVPRCTX,
-             };
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
--            define_one_arm_cp_reg(cpu, &rvbar);
+     { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
-+            define_arm_cp_regs(cpu, rvbar);
+       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
-         }
++      .fgt = FGT_CPPRCTX,
-     }
+       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
      /*
       * Note the AArch32 opcodes have a different OPC1.
       */
      { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
 +      .fgt = FGT_CFPRCTX,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
      { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
 +      .fgt = FGT_DVPRCTX,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
      { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
        .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
 +      .fgt = FGT_CPPRCTX,
        .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
  };
 --
-.25.1
+.34.1

-[PULL 16/34] hw/timer/imx_epit: remove explicit fields cnt and freq
+[PULL 30/33] target/arm: Implement the HFGITR_EL2.ERET trap
-From: Axel Heider <axel.heider@hensoldt.net>
+Implement the HFGITR_EL2.ERET fine-grained trap.  This traps
 execution from AArch64 EL1 of ERET, ERETAA and ERETAB.  The trap is
 reported with a syndrome value of 0x1a.
-The CNT register is a read-only register. There is no need to
+The trap must take precedence over a possible pointer-authentication
-store it's value, it can be calculated on demand.
+trap for ERETAA and ERETAB.
 The calculated frequency is needed temporarily only.
-Note that this is a migration compatibility break for all boards
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-types that use the EPIT peripheral.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
 ---
  target/arm/cpu.h           |  1 +
  target/arm/syndrome.h      | 10 ++++++++++
  target/arm/translate.h     |  2 ++
  target/arm/helper.c        |  3 +++
  target/arm/translate-a64.c | 10 ++++++++++
 files changed, 26 insertions(+)
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/timer/imx_epit.h |  2 -
  hw/timer/imx_epit.c         | 73 ++++++++++++++-----------------------
 files changed, 28 insertions(+), 47 deletions(-)
 diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/imx_epit.h
+--- a/target/arm/cpu.h
-+++ b/include/hw/timer/imx_epit.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct IMXEPITState {
+@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
-     uint32_t sr;
+ FIELD(TBFLAG_A64, SVL, 24, 4)
-     uint32_t lr;
+ /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
-     uint32_t cmp;
+ FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
--    uint32_t cnt;
++FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
--    uint32_t freq;
+ /*
-     qemu_irq irq;
+  * Helpers for using the above.
- };
+diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
 diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
+--- a/target/arm/syndrome.h
-+++ b/hw/timer/imx_epit.c
++++ b/target/arm/syndrome.h
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s)
+@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
-     }
+     EC_AA64_SMC               = 0x17,
      EC_SYSTEMREGISTERTRAP     = 0x18,
      EC_SVEACCESSTRAP          = 0x19,
 +    EC_ERETTRAP               = 0x1a,
      EC_SMETRAP                = 0x1d,
      EC_INSNABORT              = 0x20,
      EC_INSNABORT_SAME_EL      = 0x21,
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
      return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
  }
--/*
++/*
-- * Must be called from within a ptimer_transaction_begin/commit block
++ * eret_op is bits [1:0] of the ERET instruction, so:
-- * for both s->timer_cmp and s->timer_reload.
++ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
-- */
++ */
--static void imx_epit_set_freq(IMXEPITState *s)
++static inline uint32_t syn_erettrap(int eret_op)
-+static uint32_t imx_epit_get_freq(IMXEPITState *s)
++{
 +    return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
 +}
 +
  static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
  {
--    uint32_t clksrc;
+     return (EC_SMETRAP << ARM_EL_EC_SHIFT)
--    uint32_t prescaler;
+diff --git a/target/arm/translate.h b/target/arm/translate.h
--
+index XXXXXXX..XXXXXXX 100644
--    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
+--- a/target/arm/translate.h
--    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
++++ b/target/arm/translate.h
--
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
--    s->freq = imx_ccm_get_clock_frequency(s->ccm,
+     bool mve_no_pred;
--                                imx_epit_clocks[clksrc]) / prescaler;
+     /* True if fine-grained traps are active */
--
+     bool fgt_active;
--    DPRINTF("Setting ptimer frequency to %u\n", s->freq);
++    /* True if fine-grained trap on ERET is enabled */
--
++    bool fgt_eret;
--    if (s->freq) {
+     /*
--        ptimer_set_freq(s->timer_reload, s->freq);
+      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
--        ptimer_set_freq(s->timer_cmp, s->freq);
+      *  < 0, set by the current instruction.
--    }
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-+    uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
+index XXXXXXX..XXXXXXX 100644
-+    uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
+--- a/target/arm/helper.c
-+    uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
++++ b/target/arm/helper.c
-+    uint32_t freq = f_in / prescaler;
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
-+    DPRINTF("ptimer frequency is %u\n", freq);
-+    return freq;
+     if (arm_fgt_active(env, el)) {
- }
+         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
++        if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
- /*
++            DP_TBFLAG_A64(flags, FGT_ERET, 1);
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
      s->sr = 0;
      s->lr = EPIT_TIMER_MAX;
      s->cmp = 0;
 -    s->cnt = 0;
      ptimer_transaction_begin(s->timer_cmp);
      ptimer_transaction_begin(s->timer_reload);
 -    /* stop both timers */
 +
 +    /*
 +     * The reset switches off the input clock, so even if the CR.EN is still
 +     * set, the timers are no longer running.
 +     */
 +    assert(imx_epit_get_freq(s) == 0);
      ptimer_stop(s->timer_cmp);
      ptimer_stop(s->timer_reload);
 -    /* compute new frequency */
 -    imx_epit_set_freq(s);
      /* init both timers to EPIT_TIMER_MAX */
      ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
      ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
 -    if (s->freq && (s->cr & CR_EN)) {
 -        /* if the timer is still enabled, restart it */
 -        ptimer_run(s->timer_reload, 0);
 -    }
      ptimer_transaction_commit(s->timer_cmp);
      ptimer_transaction_commit(s->timer_reload);
  }
 -static uint32_t imx_epit_update_count(IMXEPITState *s)
 -{
 -    s->cnt = ptimer_get_count(s->timer_reload);
 -
 -    return s->cnt;
 -}
 -
  static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
  {
      IMXEPITState *s = IMX_EPIT(opaque);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
          break;
      case 4: /* CNT */
 -        imx_epit_update_count(s);
 -        reg_value = s->cnt;
 +        reg_value = ptimer_get_count(s->timer_reload);
          break;
      default:
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
  {
      if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN))  {
          /* if the compare feature is on and timers are running */
 -        uint32_t tmp = imx_epit_update_count(s);
 +        uint32_t tmp = ptimer_get_count(s->timer_reload);
          uint64_t next;
          if (tmp > s->cmp) {
              /* It'll fire in this round of the timer */
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
  static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
  {
 +    uint32_t freq = 0;
      uint32_t oldcr = s->cr;
      s->cr = value & 0x03ffffff;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
      ptimer_transaction_begin(s->timer_cmp);
      ptimer_transaction_begin(s->timer_reload);
 -    /* Update the frequency. Has been done already in case of a reset. */
 +    /*
 +     * Update the frequency. In case of a reset the input clock was
 +     * switched off, so this can be skipped.
 +     */
      if (!(s->cr & CR_SWR)) {
 -        imx_epit_set_freq(s);
 +        freq = imx_epit_get_freq(s);
 +        if (freq) {
 +            ptimer_set_freq(s->timer_reload, freq);
 +            ptimer_set_freq(s->timer_cmp, freq);
 +        }
      }
--    if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
+     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
-+    if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-         if (s->cr & CR_ENMOD) {
+index XXXXXXX..XXXXXXX 100644
-             if (s->cr & CR_RLD) {
+--- a/target/arm/translate-a64.c
-                 ptimer_set_limit(s->timer_reload, s->lr, 1);
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx_epit_ops = {
+@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
+             if (op4 != 0) {
- static const VMStateDescription vmstate_imx_timer_epit = {
+                 goto do_unallocated;
-     .name = TYPE_IMX_EPIT,
+             }
--    .version_id = 2,
++            if (s->fgt_eret) {
--    .minimum_version_id = 2,
++                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
-+    .version_id = 3,
++                return;
-+    .minimum_version_id = 3,
++            }
-     .fields = (VMStateField[]) {
+             dst = tcg_temp_new_i64();
-         VMSTATE_UINT32(cr, IMXEPITState),
+             tcg_gen_ld_i64(dst, cpu_env,
-         VMSTATE_UINT32(sr, IMXEPITState),
+                            offsetof(CPUARMState, elr_el[s->current_el]));
-         VMSTATE_UINT32(lr, IMXEPITState),
+@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
-         VMSTATE_UINT32(cmp, IMXEPITState),
+             if (rn != 0x1f || op4 != 0x1f) {
--        VMSTATE_UINT32(cnt, IMXEPITState),
+                 goto do_unallocated;
--        VMSTATE_UINT32(freq, IMXEPITState),
+             }
-         VMSTATE_PTIMER(timer_reload, IMXEPITState),
++            /* The FGT trap takes precedence over an auth trap. */
-         VMSTATE_PTIMER(timer_cmp, IMXEPITState),
++            if (s->fgt_eret) {
-         VMSTATE_END_OF_LIST()
++                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
 +                return;
 +            }
              dst = tcg_temp_new_i64();
              tcg_gen_ld_i64(dst, cpu_env,
                             offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
      dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
      dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 +    dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
      dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
      dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
      dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
 --
-.25.1
+.34.1

-[PULL 06/34] target/arm: Add PMSAv8r registers
+[PULL 31/33] target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
 These trap execution of the SVC instruction from AArch32 and AArch64.
 (As usual, AArch32 can only trap from EL0, as fine grained traps are
 disabled with an AArch32 EL1.)
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
-Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
 ---
- target/arm/cpu.h     |   6 +
+ target/arm/cpu.h           |  1 +
- target/arm/cpu.c     |  28 +++-
+ target/arm/translate.h     |  2 ++
- target/arm/helper.c  | 302 +++++++++++++++++++++++++++++++++++++++++++
+ target/arm/helper.c        | 20 ++++++++++++++++++++
- target/arm/machine.c |  28 ++++
+ target/arm/translate-a64.c |  9 ++++++++-
-files changed, 360 insertions(+), 4 deletions(-)
+ target/arm/translate.c     | 12 +++++++++---
 files changed, 40 insertions(+), 4 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
-             };
+ FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
-             uint64_t sctlr_el[4];
+ FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
-         };
+ FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
-+        uint64_t vsctlr; /* Virtualization System control register. */
++FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
-         uint64_t cpacr_el1; /* Architectural feature access control register */
-         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
+ /*
-         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
+  * Bit usage when in AArch32 state, both A- and M-profile.
-@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+diff --git a/target/arm/translate.h b/target/arm/translate.h
           */
          uint32_t *rbar[M_REG_NUM_BANKS];
          uint32_t *rlar[M_REG_NUM_BANKS];
 +        uint32_t *hprbar;
 +        uint32_t *hprlar;
          uint32_t mair0[M_REG_NUM_BANKS];
          uint32_t mair1[M_REG_NUM_BANKS];
 +        uint32_t hprselr;
      } pmsav8;
      /* v8M SAU */
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      bool has_mpu;
      /* PMSAv7 MPU number of supported regions */
      uint32_t pmsav7_dregion;
 +    /* PMSAv8 MPU number of supported hyp regions */
 +    uint32_t pmsav8r_hdregion;
      /* v8M SAU number of supported regions */
      uint32_t sau_sregion;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/translate.h
-+++ b/target/arm/cpu.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
+     bool fgt_active;
-             }
+     /* True if fine-grained trap on ERET is enabled */
-         }
+     bool fgt_eret;
-+
++    /* True if fine-grained trap on SVC is enabled */
-+        if (cpu->pmsav8r_hdregion > 0) {
++    bool fgt_svc;
-+            memset(env->pmsav8.hprbar, 0,
+     /*
-+                   sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
+      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
-+            memset(env->pmsav8.hprlar, 0,
+      *  < 0, set by the current instruction.
 +                   sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
 +        }
 +
          env->pmsav7.rnr[M_REG_NS] = 0;
          env->pmsav7.rnr[M_REG_S] = 0;
          env->pmsav8.mair0[M_REG_NS] = 0;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      /* MPU can be configured out of a PMSA CPU either by setting has-mpu
       * to false or by setting pmsav7-dregion to 0.
       */
 -    if (!cpu->has_mpu) {
 -        cpu->pmsav7_dregion = 0;
 -    }
 -    if (cpu->pmsav7_dregion == 0) {
 +    if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
          cpu->has_mpu = false;
 +        cpu->pmsav7_dregion = 0;
 +        cpu->pmsav8r_hdregion = 0;
      }
      if (arm_feature(env, ARM_FEATURE_PMSA) &&
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                  env->pmsav7.dracr = g_new0(uint32_t, nr);
              }
          }
 +
 +        if (cpu->pmsav8r_hdregion > 0xff) {
 +            error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
 +                              cpu->pmsav8r_hdregion);
 +            return;
 +        }
 +
 +        if (cpu->pmsav8r_hdregion) {
 +            env->pmsav8.hprbar = g_new0(uint32_t,
 +                                        cpu->pmsav8r_hdregion);
 +            env->pmsav8.hprlar = g_new0(uint32_t,
 +                                        cpu->pmsav8r_hdregion);
 +        }
      }
      if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
-     raw_write(env, ri, value);
+     return arm_mmu_idx_el(env, arm_current_el(env));
  }
-+static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
++static inline bool fgt_svc(CPUARMState *env, int el)
 +                          uint64_t value)
 +{
-+    ARMCPU *cpu = env_archcpu(env);
++    /*
-+
++     * Assuming fine-grained-traps are active, return true if we
-+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
++     * should be trapping on SVC instructions. Only AArch64 can
-+    env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
++     * trap on an SVC at EL1, but we don't need to special-case this
 +     * because if this is AArch32 EL1 then arm_fgt_active() is false.
 +     * We also know el is 0 or 1.
 +     */
 +    return el == 0 ?
 +        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
 +        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
 +}
 +
-+static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
-+{
+                                            ARMMMUIdx mmu_idx,
-+    return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
+                                            CPUARMTBFlags flags)
-+}
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
-+
-+static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+     if (arm_fgt_active(env, el)) {
-+                          uint64_t value)
+         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
-+{
++        if (fgt_svc(env, el)) {
-+    ARMCPU *cpu = env_archcpu(env);
++            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
 +
 +    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
 +    env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
 +}
 +
 +static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
 +}
 +
 +static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                           uint64_t value)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /*
 +     * Ignore writes that would select not implemented region.
 +     * This is architecturally UNPREDICTABLE.
 +     */
 +    if (value >= cpu->pmsav7_dregion) {
 +        return;
 +    }
 +
 +    env->pmsav7.rnr[M_REG_NS] = value;
 +}
 +
 +static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                          uint64_t value)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
 +    env->pmsav8.hprbar[env->pmsav8.hprselr] = value;
 +}
 +
 +static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return env->pmsav8.hprbar[env->pmsav8.hprselr];
 +}
 +
 +static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                          uint64_t value)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
 +    env->pmsav8.hprlar[env->pmsav8.hprselr] = value;
 +}
 +
 +static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return env->pmsav8.hprlar[env->pmsav8.hprselr];
 +}
 +
 +static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                          uint64_t value)
 +{
 +    uint32_t n;
 +    uint32_t bit;
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /* Ignore writes to unimplemented regions */
 +    int rmax = MIN(cpu->pmsav8r_hdregion, 32);
 +    value &= MAKE_64BIT_MASK(0, rmax);
 +
 +    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
 +
 +    /* Register alias is only valid for first 32 indexes */
 +    for (n = 0; n < rmax; ++n) {
 +        bit = extract32(value, n, 1);
 +        env->pmsav8.hprlar[n] = deposit32(
 +                    env->pmsav8.hprlar[n], 0, 1, bit);
 +    }
 +}
 +
 +static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    uint32_t n;
 +    uint32_t result = 0x0;
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /* Register alias is only valid for first 32 indexes */
 +    for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) {
 +        if (env->pmsav8.hprlar[n] & 0x1) {
 +            result |= (0x1 << n);
 +        }
 +    }
 +    return result;
 +}
 +
 +static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                           uint64_t value)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +
 +    /*
 +     * Ignore writes that would select not implemented region.
 +     * This is architecturally UNPREDICTABLE.
 +     */
 +    if (value >= cpu->pmsav8r_hdregion) {
 +        return;
 +    }
 +
 +    env->pmsav8.hprselr = value;
 +}
 +
 +static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                          uint64_t value)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +    uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
 +                    (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
 +
 +    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
 +
 +    if (ri->opc1 & 4) {
 +        if (index >= cpu->pmsav8r_hdregion) {
 +            return;
 +        }
 +        if (ri->opc2 & 0x1) {
 +            env->pmsav8.hprlar[index] = value;
 +        } else {
 +            env->pmsav8.hprbar[index] = value;
 +        }
 +    } else {
 +        if (index >= cpu->pmsav7_dregion) {
 +            return;
 +        }
 +        if (ri->opc2 & 0x1) {
 +            env->pmsav8.rlar[M_REG_NS][index] = value;
 +        } else {
 +            env->pmsav8.rbar[M_REG_NS][index] = value;
 +        }
 +    }
 +}
 +
 +static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    ARMCPU *cpu = env_archcpu(env);
 +    uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
 +                    (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
 +
 +    if (ri->opc1 & 4) {
 +        if (index >= cpu->pmsav8r_hdregion) {
 +            return 0x0;
 +        }
 +        if (ri->opc2 & 0x1) {
 +            return env->pmsav8.hprlar[index];
 +        } else {
 +            return env->pmsav8.hprbar[index];
 +        }
 +    } else {
 +        if (index >= cpu->pmsav7_dregion) {
 +            return 0x0;
 +        }
 +        if (ri->opc2 & 0x1) {
 +            return env->pmsav8.rlar[M_REG_NS][index];
 +        } else {
 +            return env->pmsav8.rbar[M_REG_NS][index];
 +        }
 +    }
 +}
 +
 +static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
 +    { .name = "PRBAR",
 +      .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_NO_RAW,
 +      .accessfn = access_tvm_trvm,
 +      .readfn = prbar_read, .writefn = prbar_write },
 +    { .name = "PRLAR",
 +      .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_NO_RAW,
 +      .accessfn = access_tvm_trvm,
 +      .readfn = prlar_read, .writefn = prlar_write },
 +    { .name = "PRSELR", .resetvalue = 0,
 +      .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1,
 +      .access = PL1_RW, .accessfn = access_tvm_trvm,
 +      .writefn = prselr_write,
 +      .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) },
 +    { .name = "HPRBAR", .resetvalue = 0,
 +      .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
 +      .access = PL2_RW, .type = ARM_CP_NO_RAW,
 +      .readfn = hprbar_read, .writefn = hprbar_write },
 +    { .name = "HPRLAR",
 +      .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
 +      .access = PL2_RW, .type = ARM_CP_NO_RAW,
 +      .readfn = hprlar_read, .writefn = hprlar_write },
 +    { .name = "HPRSELR", .resetvalue = 0,
 +      .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1,
 +      .access = PL2_RW,
 +      .writefn = hprselr_write,
 +      .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) },
 +    { .name = "HPRENR",
 +      .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1,
 +      .access = PL2_RW, .type = ARM_CP_NO_RAW,
 +      .readfn = hprenr_read, .writefn = hprenr_write },
 +};
 +
  static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
      /* Reset for all these registers is handled in arm_cpu_reset(),
       * because the PMSAv7 is also used by M-profile CPUs, which do
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .access = PL1_R, .type = ARM_CP_CONST,
                .resetvalue = cpu->pmsav7_dregion << 8
          };
 +        /* HMPUIR is specific to PMSA V8 */
 +        ARMCPRegInfo id_hmpuir_reginfo = {
 +            .name = "HMPUIR",
 +            .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4,
 +            .access = PL2_R, .type = ARM_CP_CONST,
 +            .resetvalue = cpu->pmsav8r_hdregion
 +        };
          static const ARMCPRegInfo crn0_wi_reginfo = {
              .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
              .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          define_arm_cp_regs(cpu, id_cp_reginfo);
          if (!arm_feature(env, ARM_FEATURE_PMSA)) {
              define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
 +        } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
 +                   arm_feature(env, ARM_FEATURE_V8)) {
 +            uint32_t i = 0;
 +            char *tmp_string;
 +
 +            define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
 +            define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo);
 +            define_arm_cp_regs(cpu, pmsav8r_cp_reginfo);
 +
 +            /* Register alias is only valid for first 32 indexes */
 +            for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
 +                uint8_t crm = 0b1000 | extract32(i, 1, 3);
 +                uint8_t opc1 = extract32(i, 4, 1);
 +                uint8_t opc2 = extract32(i, 0, 1) << 2;
 +
 +                tmp_string = g_strdup_printf("PRBAR%u", i);
 +                ARMCPRegInfo tmp_prbarn_reginfo = {
 +                    .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
 +                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
 +                    .access = PL1_RW, .resetvalue = 0,
 +                    .accessfn = access_tvm_trvm,
 +                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
 +                };
 +                define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
 +                g_free(tmp_string);
 +
 +                opc2 = extract32(i, 0, 1) << 2 | 0x1;
 +                tmp_string = g_strdup_printf("PRLAR%u", i);
 +                ARMCPRegInfo tmp_prlarn_reginfo = {
 +                    .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
 +                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
 +                    .access = PL1_RW, .resetvalue = 0,
 +                    .accessfn = access_tvm_trvm,
 +                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
 +                };
 +                define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
 +                g_free(tmp_string);
 +            }
 +
 +            /* Register alias is only valid for first 32 indexes */
 +            for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) {
 +                uint8_t crm = 0b1000 | extract32(i, 1, 3);
 +                uint8_t opc1 = 0b100 | extract32(i, 4, 1);
 +                uint8_t opc2 = extract32(i, 0, 1) << 2;
 +
 +                tmp_string = g_strdup_printf("HPRBAR%u", i);
 +                ARMCPRegInfo tmp_hprbarn_reginfo = {
 +                    .name = tmp_string,
 +                    .type = ARM_CP_NO_RAW,
 +                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
 +                    .access = PL2_RW, .resetvalue = 0,
 +                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
 +                };
 +                define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo);
 +                g_free(tmp_string);
 +
 +                opc2 = extract32(i, 0, 1) << 2 | 0x1;
 +                tmp_string = g_strdup_printf("HPRLAR%u", i);
 +                ARMCPRegInfo tmp_hprlarn_reginfo = {
 +                    .name = tmp_string,
 +                    .type = ARM_CP_NO_RAW,
 +                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
 +                    .access = PL2_RW, .resetvalue = 0,
 +                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
 +                };
 +                define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo);
 +                g_free(tmp_string);
 +            }
          } else if (arm_feature(env, ARM_FEATURE_V7)) {
              define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
          }
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              sctlr.type |= ARM_CP_SUPPRESS_TB_END;
          }
          define_one_arm_cp_reg(cpu, &sctlr);
 +
 +        if (arm_feature(env, ARM_FEATURE_PMSA) &&
 +            arm_feature(env, ARM_FEATURE_V8)) {
 +            ARMCPRegInfo vsctlr = {
 +                .name = "VSCTLR", .state = ARM_CP_STATE_AA32,
 +                .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
 +                .access = PL2_RW, .resetvalue = 0x0,
 +                .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr),
 +            };
 +            define_one_arm_cp_reg(cpu, &vsctlr);
 +        }
      }
-     if (cpu_isar_feature(aa64_lor, cpu)) {
+     if (env->uncached_cpsr & CPSR_IL) {
-diff --git a/target/arm/machine.c b/target/arm/machine.c
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
          if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
              DP_TBFLAG_A64(flags, FGT_ERET, 1);
          }
 +        if (fgt_svc(env, el)) {
 +            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
 +        }
      }
      if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/machine.c
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/machine.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static bool pmsav8_needed(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
-         arm_feature(env, ARM_FEATURE_V8);
+     int opc = extract32(insn, 21, 3);
      int op2_ll = extract32(insn, 0, 5);
      int imm16 = extract32(insn, 5, 16);
 +    uint32_t syndrome;
      switch (opc) {
      case 0:
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
           */
          switch (op2_ll) {
          case 1:                                                     /* SVC */
 +            syndrome = syn_aa64_svc(imm16);
 +            if (s->fgt_svc) {
 +                gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
 +                break;
 +            }
              gen_ss_advance(s);
 -            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
 +            gen_exception_insn(s, 4, EXCP_SWI, syndrome);
              break;
          case 2:                                                     /* HVC */
              if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
      dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
      dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 +    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
      dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
      dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
      dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
          (a->imm == semihost_imm)) {
          gen_exception_internal_insn(s, EXCP_SEMIHOST);
      } else {
 -        gen_update_pc(s, curr_insn_len(s));
 -        s->svc_imm = a->imm;
 -        s->base.is_jmp = DISAS_SWI;
 +        if (s->fgt_svc) {
 +            uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
 +            gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
 +        } else {
 +            gen_update_pc(s, curr_insn_len(s));
 +            s->svc_imm = a->imm;
 +            s->base.is_jmp = DISAS_SWI;
 +        }
      }
      return true;
  }
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
-+static bool pmsav8r_needed(void *opaque)
+     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
-+{
+     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
-+    ARMCPU *cpu = opaque;
+     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
-+    CPUARMState *env = &cpu->env;
++    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
-+
-+    return arm_feature(env, ARM_FEATURE_PMSA) &&
+     if (arm_feature(env, ARM_FEATURE_M)) {
-+        arm_feature(env, ARM_FEATURE_V8) &&
+         dc->vfp_enabled = 1;
 +        !arm_feature(env, ARM_FEATURE_M);
 +}
 +
 +static const VMStateDescription vmstate_pmsav8r = {
 +    .name = "cpu/pmsav8/pmsav8r",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = pmsav8r_needed,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU,
 +                        pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
 +        VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU,
 +                        pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
  static const VMStateDescription vmstate_pmsav8 = {
      .name = "cpu/pmsav8",
      .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
          VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
          VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
          VMSTATE_END_OF_LIST()
 +    },
 +    .subsections = (const VMStateDescription * []) {
 +        &vmstate_pmsav8r,
 +        NULL
      }
  };
 --
-.25.1
+.34.1

-[PULL 08/34] target/arm: Add ARM Cortex-R52 CPU
+[PULL 32/33] target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
-From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
+FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
 MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
 Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
 MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
 AArch32 equivalents).  This trapping is independent of whether
 fine-grained traps are enabled or not.
-All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
+Implement these extra traps.  (We don't implement DBGDTR_EL0,
 DBGDTRRX_EL0 and DBGDTRTX_EL0.)
-Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Fuad Tabba <tabba@google.com>
+Message-id: 20230130182459.3309057-23-peter.maydell@linaro.org
+Message-id: 20230127175507.2895013-23-peter.maydell@linaro.org
 ---
- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
+ target/arm/debug_helper.c | 35 +++++++++++++++++++++++++++++++----
-file changed, 42 insertions(+)
+file changed, 31 insertions(+), 4 deletions(-)
-diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu_tcg.c
+--- a/target/arm/debug_helper.c
-+++ b/target/arm/cpu_tcg.c
++++ b/target/arm/debug_helper.c
-@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
-     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+     return CP_ACCESS_OK;
  }
-+static void cortex_r52_initfn(Object *obj)
++/*
 + * Check for traps to Debug Comms Channel registers. If FEAT_FGT
 + * is implemented then these are controlled by MDCR_EL2.TDCC for
 + * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
 + * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
 + */
 +static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                  bool isread)
 +{
-+    ARMCPU *cpu = ARM_CPU(obj);
++    int el = arm_current_el(env);
 +    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
 +    bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
 +        (arm_hcr_el2_eff(env) & HCR_TGE);
 +    bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +                                          (mdcr_el2 & MDCR_TDCC);
 +    bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
 +                                          (env->cp15.mdcr_el3 & MDCR_TDCC);
 +
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
++    if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
++        return CP_ACCESS_TRAP_EL2;
-+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
++    }
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
++    if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
++        return CP_ACCESS_TRAP_EL3;
-+    cpu->midr = 0x411fd133; /* r1p3 */
++    }
-+    cpu->revidr = 0x00000000;
++    return CP_ACCESS_OK;
 +    cpu->reset_fpsid = 0x41034023;
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x12111111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +    cpu->ctr = 0x8144c004;
 +    cpu->reset_sctlr = 0x30c50838;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x10111001;
 +    cpu->isar.id_dfr0 = 0x03010006;
 +    cpu->id_afr0 = 0x00000000;
 +    cpu->isar.id_mmfr0 = 0x00211040;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01200000;
 +    cpu->isar.id_mmfr3 = 0xf0102211;
 +    cpu->isar.id_mmfr4 = 0x00000010;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232142;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00010142;
 +    cpu->isar.id_isar5 = 0x00010001;
 +    cpu->isar.dbgdidr = 0x77168000;
 +    cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
 +    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
 +
 +    cpu->pmsav7_dregion = 16;
 +    cpu->pmsav8r_hdregion = 16;
 +}
 +
- static void cortex_r5f_initfn(Object *obj)
+ static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
  {
-     ARMCPU *cpu = ARM_CPU(obj);
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
+      */
-                              .class_init = arm_v7m_class_init },
+     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
-     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
+       .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
+-      .access = PL0_R, .accessfn = access_tda,
-+    { .name = "cortex-r52",  .initfn = cortex_r52_initfn },
++      .access = PL0_R, .accessfn = access_tdcc,
-     { .name = "ti925t",      .initfn = ti925t_initfn },
+       .type = ARM_CP_CONST, .resetvalue = 0 },
-     { .name = "sa1100",      .initfn = sa1100_initfn },
+     /*
-     { .name = "sa1110",      .initfn = sa1110_initfn },
+      * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       */
      { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
        .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
 -      .access = PL1_RW, .accessfn = access_tda,
 +      .access = PL1_RW, .accessfn = access_tdcc,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
        .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
 -      .access = PL1_RW, .accessfn = access_tda,
 +      .access = PL1_RW, .accessfn = access_tdcc,
        .type = ARM_CP_CONST, .resetvalue = 0 },
      /*
       * OSECCR_EL1 provides a mechanism for an operating system
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       */
      { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
        .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .accessfn = access_tda,
 +      .access = PL1_RW, .accessfn = access_tdcc,
        .type = ARM_CP_NOP },
      /*
       * Dummy DBGCLAIM registers.
 --
-.25.1
+.34.1

-[PULL 11/34] hw/timer/imx_epit: cleanup CR defines
+Deleted patch
-From: Axel Heider <axel.heider@hensoldt.net>
-remove unused defines, add needed defines
-Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/timer/imx_epit.h | 4 ++--
- hw/timer/imx_epit.c         | 4 ++--
-files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/timer/imx_epit.h
-+++ b/include/hw/timer/imx_epit.h
-@@ -XXX,XX +XXX,XX @@
- #define CR_OCIEN    (1 << 2)
- #define CR_RLD      (1 << 3)
- #define CR_PRESCALE_SHIFT (4)
--#define CR_PRESCALE_MASK  (0xfff)
-+#define CR_PRESCALE_BITS  (12)
- #define CR_SWR      (1 << 16)
- #define CR_IOVW     (1 << 17)
- #define CR_DBGEN    (1 << 18)
-@@ -XXX,XX +XXX,XX @@
- #define CR_DOZEN    (1 << 20)
- #define CR_STOPEN   (1 << 21)
- #define CR_CLKSRC_SHIFT (24)
--#define CR_CLKSRC_MASK  (0x3 << CR_CLKSRC_SHIFT)
-+#define CR_CLKSRC_BITS  (2)
- #define EPIT_TIMER_MAX  0XFFFFFFFFUL
-diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/imx_epit.c
-+++ b/hw/timer/imx_epit.c
-@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
-     uint32_t clksrc;
-     uint32_t prescaler;
--    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
--    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
-+    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
-+    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
-     s->freq = imx_ccm_get_clock_frequency(s->ccm,
-                                 imx_epit_clocks[clksrc]) / prescaler;
---
-.25.1

-[PULL 23/34] target/arm: cleanup cpu includes
+[PULL 33/33] target/arm: Enable FEAT_FGT on '-cpu max'
-From: Claudio Fontana <cfontana@suse.de>
+Update the ID registers for TCG's '-cpu max' to report the
 presence of FEAT_FGT Fine-Grained Traps support.
-Remove some unused headers.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Fuad Tabba <tabba@google.com>
 Message-id: 20230130182459.3309057-24-peter.maydell@linaro.org
 Message-id: 20230127175507.2895013-24-peter.maydell@linaro.org
 ---
  docs/system/arm/emulation.rst | 1 +
  target/arm/cpu64.c            | 1 +
 files changed, 2 insertions(+)
-Signed-off-by: Claudio Fontana <cfontana@suse.de>
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 Acked-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Claudio Fontana <cfontana@suse.de>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Message-id: 20221213190537.511-7-farosas@suse.de
 [added back some includes that are still needed at this point]
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.c   | 1 -
  target/arm/cpu64.c | 6 ------
 files changed, 7 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/docs/system/arm/emulation.rst
-+++ b/target/arm/cpu.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- #include "target/arm/idau.h"
+ - FEAT_ETS (Enhanced Translation Synchronization)
- #include "qemu/module.h"
+ - FEAT_EVT (Enhanced Virtualization Traps)
- #include "qapi/error.h"
+ - FEAT_FCMA (Floating-point complex number instructions)
--#include "qapi/visitor.h"
++- FEAT_FGT (Fine-Grained Traps)
- #include "cpu.h"
+ - FEAT_FHM (Floating-point half-precision multiplication instructions)
- #ifdef CONFIG_TCG
+ - FEAT_FP16 (Half-precision floating-point data processing)
- #include "hw/core/tcg-cpu-ops.h"
+ - FEAT_FRINTTS (Floating-point to integer instructions)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
- #include "qemu/osdep.h"
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
- #include "qapi/error.h"
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
- #include "cpu.h"
+     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2);  /*  4k stage2 supported */
--#ifdef CONFIG_TCG
++    t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1);       /* FEAT_FGT */
--#include "hw/core/tcg-cpu-ops.h"
+     cpu->isar.id_aa64mmfr0 = t;
--#endif /* CONFIG_TCG */
- #include "qemu/module.h"
+     t = cpu->isar.id_aa64mmfr1;
 -#if !defined(CONFIG_USER_ONLY)
 -#include "hw/loader.h"
 -#endif
  #include "sysemu/kvm.h"
  #include "sysemu/hvf.h"
  #include "kvm_arm.h"
 --
-.25.1
+.34.1

Some arm patches; my to-review queue is by no means empty, but
this is a big enough set of patches to be getting on with...

-- PMM

The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:

.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs (2023-01-04 18:58:33 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230105

for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:

hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33:00 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement AArch32 ARMv8-R support
 * Add Cortex-R52 CPU
 * fix handling of HLT semihosting in system mode
 * hw/timer/ixm_epit: cleanup and fix bug in compare handling
 * target/arm: Coding style fixes
 * target/arm: Clean up includes
 * nseries: minor code cleanups
 * target/arm: align exposed ID registers with Linux
 * hw/arm/smmu-common: remove unnecessary inlines
 * i.MX7D: Handle GPT timers
 * i.MX7D: Connect IRQs to GPIO devices
 * i.MX6UL: Add a specific GPT timer instance
 * hw/net: Fix read of uninitialized memory in imx_fec

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: fix handling of HLT semihosting in system mode

Axel Heider (8):
      hw/timer/imx_epit: improve comments
      hw/timer/imx_epit: cleanup CR defines
      hw/timer/imx_epit: define SR_OCIF
      hw/timer/imx_epit: update interrupt state on CR write access
      hw/timer/imx_epit: hard reset initializes CR with 0
      hw/timer/imx_epit: factor out register write handlers
      hw/timer/imx_epit: remove explicit fields cnt and freq
      hw/timer/imx_epit: fix compare timer handling

Claudio Fontana (1):
      target/arm: cleanup cpu includes

Fabiano Rosas (5):
      target/arm: Fix checkpatch comment style warnings in helper.c
      target/arm: Fix checkpatch space errors in helper.c
      target/arm: Fix checkpatch brace errors in helper.c
      target/arm: Remove unused includes from m_helper.c
      target/arm: Remove unused includes from helper.c

Jean-Christophe Dubois (4):
      i.MX7D: Connect GPT timers to IRQ
      i.MX7D: Compute clock frequency for the fixed frequency clocks.
      i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
      i.MX7D: Connect IRQs to GPIO devices.

Peter Maydell (1):
      target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it

Philippe Mathieu-Daudé (5):
      hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
      hw/arm/nseries: Constify various read-only arrays
      hw/arm/nseries: Silent -Wmissing-field-initializers warning
      hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
      hw/arm/smmu-common: Avoid using inlined functions with external linkage

Stephen Longfield (1):
      hw/net: Fix read of uninitialized memory in imx_fec.

Tobias Röhmel (7):
      target/arm: Don't add all MIDR aliases for cores that implement PMSA
      target/arm: Make RVBAR available for all ARMv8 CPUs
      target/arm: Make stage_2_format for cache attributes optional
      target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
      target/arm: Add PMSAv8r registers
      target/arm: Add PMSAv8r functionality
      target/arm: Add ARM Cortex-R52 CPU

Zhuojia Shen (1):
      target/arm: align exposed ID registers with Linux

In get_phys_addr_twostage() we set the lg_page_size of the result to
the maximum of the stage 1 and stage 2 page sizes.  This works for
the case where we do want to create a TLB entry, because we know the
common TLB code only creates entries of the TARGET_PAGE_SIZE and
asking for a size larger than that only means that invalidations
invalidate the whole larger area.  However, if lg_page_size is
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
TLB entry"; in this case if either S1 or S2 said "this covers less
than a page and can't go in a TLB" then the final result also should
be marked that way.  Set the resulting page size to 0 if either
stage asked for a less-than-a-page entry, and expand the comment
to explain what's going on.

This has no effect for VMSA because currently the VMSA lookup always
returns results that cover at least TARGET_PAGE_SIZE; however when we
add v8R support it will reuse this code path, and for v8R the S1 and
S2 results can be smaller than TARGET_PAGE_SIZE.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
---
 target/arm/ptw.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
     }
 
     /*
-     * Use the maximum of the S1 & S2 page size, so that invalidation
-     * of pages > TARGET_PAGE_SIZE works correctly.
+     * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
+     * this means "don't put this in the TLB"; in this case, return a
+     * result with lg_page_size == 0 to achieve that. Otherwise,
+     * use the maximum of the S1 & S2 page size, so that invalidation
+     * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
+     * we know the combined result permissions etc only cover the minimum
+     * of the S1 and S2 page size, because we know that the common TLB code
+     * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
+     * and passing a larger page size value only affects invalidations.)
      */
-    if (result->f.lg_page_size < s1_lgpgsz) {
+    if (result->f.lg_page_size < TARGET_PAGE_BITS ||
+        s1_lgpgsz < TARGET_PAGE_BITS) {
+        result->f.lg_page_size = 0;
+    } else if (result->f.lg_page_size < s1_lgpgsz) {
         result->f.lg_page_size = s1_lgpgsz;
     }
 
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
               .readfn = midr_read },
-            /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
-            { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
-              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
-              .access = PL1_R, .resetvalue = cpu->midr },
+            /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
               .access = PL1_R, .resetvalue = cpu->midr },
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .accessfn = access_aa64_tid1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
         };
+        ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
+            .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+            .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+            .access = PL1_R, .resetvalue = cpu->midr
+        };
         ARMCPRegInfo id_cp_reginfo[] = {
             /* These are common to v8 and pre-v8 */
             { .name = "CTR",
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
         if (arm_feature(env, ARM_FEATURE_V8)) {
             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
+            if (!arm_feature(env, ARM_FEATURE_PMSA)) {
+                define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
+            }
         } else {
             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
         }
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

RVBAR shadows RVBAR_ELx where x is the highest exception
level if the highest EL is not EL3. This patch also allows
ARMv8 CPUs to change the reset address with
the rvbar property.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c    |  6 +++++-
 target/arm/helper.c | 21 ++++++++++++++-------
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
         env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
                                          CPACR, CP11, 3);
 #endif
+        if (arm_feature(env, ARM_FEATURE_V8)) {
+            env->cp15.rvbar = cpu->rvbar_prop;
+            env->regs[15] = cpu->rvbar_prop;
+        }
     }
 
 #if defined(CONFIG_USER_ONLY)
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
     }
 
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+    if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
         object_property_add_uint64_ptr(obj, "rvbar",
                                        &cpu->rvbar_prop,
                                        OBJ_PROP_FLAG_READWRITE);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         if (!arm_feature(env, ARM_FEATURE_EL3) &&
             !arm_feature(env, ARM_FEATURE_EL2)) {
             ARMCPRegInfo rvbar = {
-                .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
+                .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
                 .access = PL1_R,
                 .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         }
         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
         if (!arm_feature(env, ARM_FEATURE_EL3)) {
-            ARMCPRegInfo rvbar = {
-                .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
-                .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
-                .access = PL2_R,
-                .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+            ARMCPRegInfo rvbar[] = {
+                {
+                    .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
+                    .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
+                    .access = PL2_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
+                {   .name = "RVBAR", .type = ARM_CP_ALIAS,
+                    .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
+                    .access = PL2_R,
+                    .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
+                },
             };
-            define_one_arm_cp_reg(cpu, &rvbar);
+            define_arm_cp_regs(cpu, rvbar);
         }
     }
 
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
VMSAv8, the stage 2 attributes are in the same format as the stage 1
attributes (8-bit MAIR format). Rather than converting the MAIR
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
stage 2 descriptor) and then converting back to do the attribute
combination, allow combined_attrs_nofwb() to accept s2 attributes
that are already in the MAIR format.

We move the assert() to combined_attrs_fwb(), because that function
really does require a VMSA stage 2 attribute format. (We will never
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
 {
     uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
 
-    s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+    if (s2.is_s2_format) {
+        s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
+    } else {
+        s2_mair_attrs = s2.attrs;
+    }
 
     s1lo = extract32(s1.attrs, 0, 4);
     s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
  */
 static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
 {
+    assert(s2.is_s2_format && !s1.is_s2_format);
+
     switch (s2.attrs) {
     case 7:
         /* Use stage 1 attributes */
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
     ARMCacheAttrs ret;
     bool tagged = false;
 
-    assert(s2.is_s2_format && !s1.is_s2_format);
+    assert(!s1.is_s2_format);
     ret.is_s2_format = false;
 
     if (s1.attrs == 0xf0) {
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 4 ++++
 target/arm/debug_helper.c | 3 +++
 target/arm/tlb_helper.c   | 4 ++++
 3 files changed, 11 insertions(+)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu);
 static inline bool extended_addresses_enabled(CPUARMState *env)
 {
     uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
+        arm_feature(env, ARM_FEATURE_V8)) {
+        return true;
+    }
     return arm_el_is_aa64(env, 1) ||
            (arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
 }
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
 
     if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
         using_lpae = true;
+    } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
+               arm_feature(env, ARM_FEATURE_V8)) {
+        using_lpae = true;
     } else {
         if (arm_feature(env, ARM_FEATURE_LPAE) &&
             (env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
     if (el == 2 || arm_el_is_aa64(env, el)) {
         return true;
     }
+    if (arm_feature(env, ARM_FEATURE_PMSA) &&
+        arm_feature(env, ARM_FEATURE_V8)) {
+        return true;
+    }
     if (arm_feature(env, ARM_FEATURE_LPAE)
         && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
         return true;
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |   6 +
 target/arm/cpu.c     |  28 +++-
 target/arm/helper.c  | 302 +++++++++++++++++++++++++++++++++++++++++++
 target/arm/machine.c |  28 ++++
 4 files changed, 360 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
             };
             uint64_t sctlr_el[4];
         };
+        uint64_t vsctlr; /* Virtualization System control register. */
         uint64_t cpacr_el1; /* Architectural feature access control register */
         uint64_t cptr_el[4];  /* ARMv8 feature trap registers */
         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
          */
         uint32_t *rbar[M_REG_NUM_BANKS];
         uint32_t *rlar[M_REG_NUM_BANKS];
+        uint32_t *hprbar;
+        uint32_t *hprlar;
         uint32_t mair0[M_REG_NUM_BANKS];
         uint32_t mair1[M_REG_NUM_BANKS];
+        uint32_t hprselr;
     } pmsav8;
 
     /* v8M SAU */
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     bool has_mpu;
     /* PMSAv7 MPU number of supported regions */
     uint32_t pmsav7_dregion;
+    /* PMSAv8 MPU number of supported hyp regions */
+    uint32_t pmsav8r_hdregion;
     /* v8M SAU number of supported regions */
     uint32_t sau_sregion;
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
             }
         }
+
+        if (cpu->pmsav8r_hdregion > 0) {
+            memset(env->pmsav8.hprbar, 0,
+                   sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
+            memset(env->pmsav8.hprlar, 0,
+                   sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
+        }
+
         env->pmsav7.rnr[M_REG_NS] = 0;
         env->pmsav7.rnr[M_REG_S] = 0;
         env->pmsav8.mair0[M_REG_NS] = 0;
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
      * to false or by setting pmsav7-dregion to 0.
      */
-    if (!cpu->has_mpu) {
-        cpu->pmsav7_dregion = 0;
-    }
-    if (cpu->pmsav7_dregion == 0) {
+    if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
         cpu->has_mpu = false;
+        cpu->pmsav7_dregion = 0;
+        cpu->pmsav8r_hdregion = 0;
     }
 
     if (arm_feature(env, ARM_FEATURE_PMSA) &&
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                 env->pmsav7.dracr = g_new0(uint32_t, nr);
             }
         }
+
+        if (cpu->pmsav8r_hdregion > 0xff) {
+            error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
+                              cpu->pmsav8r_hdregion);
+            return;
+        }
+
+        if (cpu->pmsav8r_hdregion) {
+            env->pmsav8.hprbar = g_new0(uint32_t,
+                                        cpu->pmsav8r_hdregion);
+            env->pmsav8.hprlar = g_new0(uint32_t,
+                                        cpu->pmsav8r_hdregion);
+        }
     }
 
     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
 }
 
+static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+    env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
+}
+
+static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
+}
+
+static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+    env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
+}
+
+static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
+}
+
+static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /*
+     * Ignore writes that would select not implemented region.
+     * This is architecturally UNPREDICTABLE.
+     */
+    if (value >= cpu->pmsav7_dregion) {
+        return;
+    }
+
+    env->pmsav7.rnr[M_REG_NS] = value;
+}
+
+static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+    env->pmsav8.hprbar[env->pmsav8.hprselr] = value;
+}
+
+static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pmsav8.hprbar[env->pmsav8.hprselr];
+}
+
+static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+    env->pmsav8.hprlar[env->pmsav8.hprselr] = value;
+}
+
+static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return env->pmsav8.hprlar[env->pmsav8.hprselr];
+}
+
+static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    uint32_t n;
+    uint32_t bit;
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Ignore writes to unimplemented regions */
+    int rmax = MIN(cpu->pmsav8r_hdregion, 32);
+    value &= MAKE_64BIT_MASK(0, rmax);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+
+    /* Register alias is only valid for first 32 indexes */
+    for (n = 0; n < rmax; ++n) {
+        bit = extract32(value, n, 1);
+        env->pmsav8.hprlar[n] = deposit32(
+                    env->pmsav8.hprlar[n], 0, 1, bit);
+    }
+}
+
+static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    uint32_t n;
+    uint32_t result = 0x0;
+    ARMCPU *cpu = env_archcpu(env);
+
+    /* Register alias is only valid for first 32 indexes */
+    for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) {
+        if (env->pmsav8.hprlar[n] & 0x1) {
+            result |= (0x1 << n);
+        }
+    }
+    return result;
+}
+
+static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                           uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+
+    /*
+     * Ignore writes that would select not implemented region.
+     * This is architecturally UNPREDICTABLE.
+     */
+    if (value >= cpu->pmsav8r_hdregion) {
+        return;
+    }
+
+    env->pmsav8.hprselr = value;
+}
+
+static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                          uint64_t value)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
+                    (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
+
+    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
+
+    if (ri->opc1 & 4) {
+        if (index >= cpu->pmsav8r_hdregion) {
+            return;
+        }
+        if (ri->opc2 & 0x1) {
+            env->pmsav8.hprlar[index] = value;
+        } else {
+            env->pmsav8.hprbar[index] = value;
+        }
+    } else {
+        if (index >= cpu->pmsav7_dregion) {
+            return;
+        }
+        if (ri->opc2 & 0x1) {
+            env->pmsav8.rlar[M_REG_NS][index] = value;
+        } else {
+            env->pmsav8.rbar[M_REG_NS][index] = value;
+        }
+    }
+}
+
+static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    ARMCPU *cpu = env_archcpu(env);
+    uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
+                    (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
+
+    if (ri->opc1 & 4) {
+        if (index >= cpu->pmsav8r_hdregion) {
+            return 0x0;
+        }
+        if (ri->opc2 & 0x1) {
+            return env->pmsav8.hprlar[index];
+        } else {
+            return env->pmsav8.hprbar[index];
+        }
+    } else {
+        if (index >= cpu->pmsav7_dregion) {
+            return 0x0;
+        }
+        if (ri->opc2 & 0x1) {
+            return env->pmsav8.rlar[M_REG_NS][index];
+        } else {
+            return env->pmsav8.rbar[M_REG_NS][index];
+        }
+    }
+}
+
+static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
+    { .name = "PRBAR",
+      .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_NO_RAW,
+      .accessfn = access_tvm_trvm,
+      .readfn = prbar_read, .writefn = prbar_write },
+    { .name = "PRLAR",
+      .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_NO_RAW,
+      .accessfn = access_tvm_trvm,
+      .readfn = prlar_read, .writefn = prlar_write },
+    { .name = "PRSELR", .resetvalue = 0,
+      .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .writefn = prselr_write,
+      .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) },
+    { .name = "HPRBAR", .resetvalue = 0,
+      .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
+      .access = PL2_RW, .type = ARM_CP_NO_RAW,
+      .readfn = hprbar_read, .writefn = hprbar_write },
+    { .name = "HPRLAR",
+      .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_NO_RAW,
+      .readfn = hprlar_read, .writefn = hprlar_write },
+    { .name = "HPRSELR", .resetvalue = 0,
+      .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1,
+      .access = PL2_RW,
+      .writefn = hprselr_write,
+      .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) },
+    { .name = "HPRENR",
+      .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1,
+      .access = PL2_RW, .type = ARM_CP_NO_RAW,
+      .readfn = hprenr_read, .writefn = hprenr_write },
+};
+
 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
     /* Reset for all these registers is handled in arm_cpu_reset(),
      * because the PMSAv7 is also used by M-profile CPUs, which do
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->pmsav7_dregion << 8
         };
+        /* HMPUIR is specific to PMSA V8 */
+        ARMCPRegInfo id_hmpuir_reginfo = {
+            .name = "HMPUIR",
+            .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL2_R, .type = ARM_CP_CONST,
+            .resetvalue = cpu->pmsav8r_hdregion
+        };
         static const ARMCPRegInfo crn0_wi_reginfo = {
             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         define_arm_cp_regs(cpu, id_cp_reginfo);
         if (!arm_feature(env, ARM_FEATURE_PMSA)) {
             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
+        } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
+                   arm_feature(env, ARM_FEATURE_V8)) {
+            uint32_t i = 0;
+            char *tmp_string;
+
+            define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
+            define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo);
+            define_arm_cp_regs(cpu, pmsav8r_cp_reginfo);
+
+            /* Register alias is only valid for first 32 indexes */
+            for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
+                uint8_t crm = 0b1000 | extract32(i, 1, 3);
+                uint8_t opc1 = extract32(i, 4, 1);
+                uint8_t opc2 = extract32(i, 0, 1) << 2;
+
+                tmp_string = g_strdup_printf("PRBAR%u", i);
+                ARMCPRegInfo tmp_prbarn_reginfo = {
+                    .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
+                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
+                    .access = PL1_RW, .resetvalue = 0,
+                    .accessfn = access_tvm_trvm,
+                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
+                };
+                define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
+                g_free(tmp_string);
+
+                opc2 = extract32(i, 0, 1) << 2 | 0x1;
+                tmp_string = g_strdup_printf("PRLAR%u", i);
+                ARMCPRegInfo tmp_prlarn_reginfo = {
+                    .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
+                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
+                    .access = PL1_RW, .resetvalue = 0,
+                    .accessfn = access_tvm_trvm,
+                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
+                };
+                define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
+                g_free(tmp_string);
+            }
+
+            /* Register alias is only valid for first 32 indexes */
+            for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) {
+                uint8_t crm = 0b1000 | extract32(i, 1, 3);
+                uint8_t opc1 = 0b100 | extract32(i, 4, 1);
+                uint8_t opc2 = extract32(i, 0, 1) << 2;
+
+                tmp_string = g_strdup_printf("HPRBAR%u", i);
+                ARMCPRegInfo tmp_hprbarn_reginfo = {
+                    .name = tmp_string,
+                    .type = ARM_CP_NO_RAW,
+                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
+                    .access = PL2_RW, .resetvalue = 0,
+                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
+                };
+                define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo);
+                g_free(tmp_string);
+
+                opc2 = extract32(i, 0, 1) << 2 | 0x1;
+                tmp_string = g_strdup_printf("HPRLAR%u", i);
+                ARMCPRegInfo tmp_hprlarn_reginfo = {
+                    .name = tmp_string,
+                    .type = ARM_CP_NO_RAW,
+                    .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
+                    .access = PL2_RW, .resetvalue = 0,
+                    .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
+                };
+                define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo);
+                g_free(tmp_string);
+            }
         } else if (arm_feature(env, ARM_FEATURE_V7)) {
             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
         }
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
         }
         define_one_arm_cp_reg(cpu, &sctlr);
+
+        if (arm_feature(env, ARM_FEATURE_PMSA) &&
+            arm_feature(env, ARM_FEATURE_V8)) {
+            ARMCPRegInfo vsctlr = {
+                .name = "VSCTLR", .state = ARM_CP_STATE_AA32,
+                .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
+                .access = PL2_RW, .resetvalue = 0x0,
+                .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr),
+            };
+            define_one_arm_cp_reg(cpu, &vsctlr);
+        }
     }
 
     if (cpu_isar_feature(aa64_lor, cpu)) {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static bool pmsav8_needed(void *opaque)
         arm_feature(env, ARM_FEATURE_V8);
 }
 
+static bool pmsav8r_needed(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+    CPUARMState *env = &cpu->env;
+
+    return arm_feature(env, ARM_FEATURE_PMSA) &&
+        arm_feature(env, ARM_FEATURE_V8) &&
+        !arm_feature(env, ARM_FEATURE_M);
+}
+
+static const VMStateDescription vmstate_pmsav8r = {
+    .name = "cpu/pmsav8/pmsav8r",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pmsav8r_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU,
+                        pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
+        VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU,
+                        pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
 static const VMStateDescription vmstate_pmsav8 = {
     .name = "cpu/pmsav8",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
         VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
         VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_pmsav8r,
+        NULL
     }
 };
 
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

Add PMSAv8r translation.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 104 insertions(+), 22 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
-    } else {
-        return regime_sctlr(env, mmu_idx) & SCTLR_BR;
     }
+
+    if (mmu_idx == ARMMMUIdx_Stage2) {
+        return false;
+    }
+
+    return regime_sctlr(env, mmu_idx) & SCTLR_BR;
 }
 
 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
     return !(result->f.prot & (1 << access_type));
 }
 
+static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
+                             uint32_t secure)
+{
+    if (regime_el(env, mmu_idx) == 2) {
+        return env->pmsav8.hprbar;
+    } else {
+        return env->pmsav8.rbar[secure];
+    }
+}
+
+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
+                             uint32_t secure)
+{
+    if (regime_el(env, mmu_idx) == 2) {
+        return env->pmsav8.hprlar;
+    } else {
+        return env->pmsav8.rlar[secure];
+    }
+}
+
 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                        MMUAccessType access_type, ARMMMUIdx mmu_idx,
                        bool secure, GetPhysAddrResult *result,
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
     bool hit = false;
     uint32_t addr_page_base = address & TARGET_PAGE_MASK;
     uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
+    int region_counter;
+
+    if (regime_el(env, mmu_idx) == 2) {
+        region_counter = cpu->pmsav8r_hdregion;
+    } else {
+        region_counter = cpu->pmsav7_dregion;
+    }
 
     result->f.lg_page_size = TARGET_PAGE_BITS;
     result->f.phys_addr = address;
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
         *mregion = -1;
     }
 
+    if (mmu_idx == ARMMMUIdx_Stage2) {
+        fi->stage2 = true;
+    }
+
     /*
      * Unlike the ARM ARM pseudocode, we don't need to check whether this
      * was an exception vector read from the vector table (which is always
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
             hit = true;
         }
 
-        for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
+        uint32_t bitmask;
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            bitmask = 0x1f;
+        } else {
+            bitmask = 0x3f;
+            fi->level = 0;
+        }
+
+        for (n = region_counter - 1; n >= 0; n--) {
             /* region search */
             /*
-             * Note that the base address is bits [31:5] from the register
-             * with bits [4:0] all zeroes, but the limit address is bits
-             * [31:5] from the register with bits [4:0] all ones.
+             * Note that the base address is bits [31:x] from the register
+             * with bits [x-1:0] all zeroes, but the limit address is bits
+             * [31:x] from the register with bits [x:0] all ones. Where x is
+             * 5 for Cortex-M and 6 for Cortex-R
              */
-            uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
-            uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
+            uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
+            uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
 
-            if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
+            if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
                 /* Region disabled */
                 continue;
             }
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
                  * PMSAv7 where highest-numbered-region wins)
                  */
                 fi->type = ARMFault_Permission;
-                fi->level = 1;
+                if (arm_feature(env, ARM_FEATURE_M)) {
+                    fi->level = 1;
+                }
                 return true;
             }
 
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
     }
 
     if (!hit) {
-        /* background fault */
-        fi->type = ARMFault_Background;
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            fi->type = ARMFault_Background;
+        } else {
+            fi->type = ARMFault_Permission;
+        }
         return true;
     }
 
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
         /* hit using the background region */
         get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
     } else {
-        uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
-        uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
+        uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
+        uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
+        uint32_t ap = extract32(matched_rbar, 1, 2);
+        uint32_t xn = extract32(matched_rbar, 0, 1);
         bool pxn = false;
 
         if (arm_feature(env, ARM_FEATURE_V8_1M)) {
-            pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
+            pxn = extract32(matched_rlar, 4, 1);
         }
 
         if (m_is_system_region(env, address)) {
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
             xn = 1;
         }
 
-        result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
+        if (regime_el(env, mmu_idx) == 2) {
+            result->f.prot = simple_ap_to_rw_prot_is_user(ap,
+                                            mmu_idx != ARMMMUIdx_E2);
+        } else {
+            result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
+        }
+
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            uint8_t attrindx = extract32(matched_rlar, 1, 3);
+            uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
+            uint8_t sh = extract32(matched_rlar, 3, 2);
+
+            if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
+                result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
+                xn = 0x1;
+            }
+
+            if ((regime_el(env, mmu_idx) == 1) &&
+                regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
+                pxn = 0x1;
+            }
+
+            result->cacheattrs.is_s2_format = false;
+            result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
+            result->cacheattrs.shareability = sh;
+        }
+
         if (result->f.prot && !xn && !(pxn && !is_user)) {
             result->f.prot |= PAGE_EXEC;
         }
-        /*
-         * We don't need to look the attribute up in the MAIR0/MAIR1
-         * registers because that only tells us about cacheability.
-         */
+
         if (mregion) {
             *mregion = matchregion;
         }
     }
 
     fi->type = ARMFault_Permission;
-    fi->level = 1;
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        fi->level = 1;
+    }
     return !(result->f.prot & (1 << access_type));
 }
 
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
     cacheattrs1 = result->cacheattrs;
     memset(result, 0, sizeof(*result));
 
-    ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
+    if (arm_feature(env, ARM_FEATURE_PMSA)) {
+        ret = get_phys_addr_pmsav8(env, ipa, access_type,
+                                   ptw->in_mmu_idx, is_secure, result, fi);
+    } else {
+        ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
+                                 is_el0, result, fi);
+    }
     fi->s2addr = ipa;
 
     /* Combine the S1 and S2 perms.  */
-- 
2.25.1

From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>

All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 }
 
+static void cortex_r52_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_PMSA);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    cpu->midr = 0x411fd133; /* r1p3 */
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034023;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x8144c004;
+    cpu->reset_sctlr = 0x30c50838;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x10111001;
+    cpu->isar.id_dfr0 = 0x03010006;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x00211040;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01200000;
+    cpu->isar.id_mmfr3 = 0xf0102211;
+    cpu->isar.id_mmfr4 = 0x00000010;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232142;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00010142;
+    cpu->isar.id_isar5 = 0x00010001;
+    cpu->isar.dbgdidr = 0x77168000;
+    cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
+    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+
+    cpu->pmsav7_dregion = 16;
+    cpu->pmsav8r_hdregion = 16;
+}
+
 static void cortex_r5f_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
                              .class_init = arm_v7m_class_init },
     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
+    { .name = "cortex-r52",  .initfn = cortex_r52_initfn },
     { .name = "ti925t",      .initfn = ti925t_initfn },
     { .name = "sa1100",      .initfn = sa1100_initfn },
     { .name = "sa1110",      .initfn = sa1110_initfn },
-- 
2.25.1

From: Alex Bennée <alex.bennee@linaro.org>

The check semihosting_enabled() wants to know if the guest is
currently in user mode. Unlike the other cases the test was inverted
causing us to block semihosting calls in non-EL0 modes.

Cc: qemu-stable@nongnu.org
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
      * semihosting, to provide some semblance of security
      * (and for consistency with our 32-bit semihosting).
      */
-    if (semihosting_enabled(s->current_el != 0) &&
+    if (semihosting_enabled(s->current_el == 0) &&
         (imm == (s->thumb ? 0x3c : 0xf000))) {
         gen_exception_internal_insn(s, EXCP_SEMIHOST);
         return;
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

Fix typos, add background information

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
     }
 }
 
+/*
+ * This is called both on hardware (device) reset and software reset.
+ */
 static void imx_epit_reset(DeviceState *dev)
 {
     IMXEPITState *s = IMX_EPIT(dev);
 
-    /*
-     * Soft reset doesn't touch some bits; hard reset clears them
-     */
+    /* Soft reset doesn't touch some bits; hard reset clears them */
     s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
     s->sr = 0;
     s->lr = EPIT_TIMER_MAX;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         ptimer_transaction_begin(s->timer_cmp);
         ptimer_transaction_begin(s->timer_reload);
 
+        /* Update the frequency. Has been done already in case of a reset. */
         if (!(s->cr & CR_SWR)) {
             imx_epit_set_freq(s);
         }
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         break;
 
     case 1: /* SR - ACK*/
-        /* writing 1 to OCIF clear the OCIF bit */
+        /* writing 1 to OCIF clears the OCIF bit */
         if (value & 0x01) {
             s->sr = 0;
             imx_epit_update_int(s);
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
                           0x00001000);
     sysbus_init_mmio(sbd, &s->iomem);
 
+    /*
+     * The reload timer keeps running when the peripheral is enabled. It is a
+     * kind of wall clock that does not generate any interrupts. The callback
+     * needs to be provided, but it does nothing as the ptimer already supports
+     * all necessary reloading functionality.
+     */
     s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
 
+    /*
+     * The compare timer is running only when the peripheral configuration is
+     * in a state that will generate compare interrupts.
+     */
     s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
 }
 
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

remove unused defines, add needed defines

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/imx_epit.h | 4 ++--
 hw/timer/imx_epit.c         | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/imx_epit.h
+++ b/include/hw/timer/imx_epit.h
@@ -XXX,XX +XXX,XX @@
 #define CR_OCIEN    (1 << 2)
 #define CR_RLD      (1 << 3)
 #define CR_PRESCALE_SHIFT (4)
-#define CR_PRESCALE_MASK  (0xfff)
+#define CR_PRESCALE_BITS  (12)
 #define CR_SWR      (1 << 16)
 #define CR_IOVW     (1 << 17)
 #define CR_DBGEN    (1 << 18)
@@ -XXX,XX +XXX,XX @@
 #define CR_DOZEN    (1 << 20)
 #define CR_STOPEN   (1 << 21)
 #define CR_CLKSRC_SHIFT (24)
-#define CR_CLKSRC_MASK  (0x3 << CR_CLKSRC_SHIFT)
+#define CR_CLKSRC_BITS  (2)
 
 #define EPIT_TIMER_MAX  0XFFFFFFFFUL
 
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
     uint32_t clksrc;
     uint32_t prescaler;
 
-    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
-    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
+    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
+    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
 
     s->freq = imx_ccm_get_clock_frequency(s->ccm,
                                 imx_epit_clocks[clksrc]) / prescaler;
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/imx_epit.h |  2 ++
 hw/timer/imx_epit.c         | 12 ++++++------
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/imx_epit.h
+++ b/include/hw/timer/imx_epit.h
@@ -XXX,XX +XXX,XX @@
 #define CR_CLKSRC_SHIFT (24)
 #define CR_CLKSRC_BITS  (2)
 
+#define SR_OCIF     (1 << 0)
+
 #define EPIT_TIMER_MAX  0XFFFFFFFFUL
 
 #define TYPE_IMX_EPIT "imx.epit"
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx_epit_clocks[] =  {
  */
 static void imx_epit_update_int(IMXEPITState *s)
 {
-    if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
+    if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
         qemu_irq_raise(s->irq);
     } else {
         qemu_irq_lower(s->irq);
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         break;
 
     case 1: /* SR - ACK*/
-        /* writing 1 to OCIF clears the OCIF bit */
-        if (value & 0x01) {
-            s->sr = 0;
+        /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
+        if (value & SR_OCIF) {
+            s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
             imx_epit_update_int(s);
         }
         break;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
     IMXEPITState *s = IMX_EPIT(opaque);
 
     DPRINTF("sr was %d\n", s->sr);
-
-    s->sr = 1;
+    /* Set interrupt status bit SR.OCIF and update the interrupt state */
+    s->sr |= SR_OCIF;
     imx_epit_update_int(s);
 }
 
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         if (s->cr & CR_SWR) {
             /* handle the reset */
             imx_epit_reset(DEVICE(s));
-            /*
-             * TODO: could we 'break' here? following operations appear
-             * to duplicate the work imx_epit_reset() already did.
-             */
         }
 
+        /*
+         * The interrupt state can change due to:
+         * - reset clears both SR.OCIF and CR.OCIE
+         * - write to CR.EN or CR.OCIE
+         */
+        imx_epit_update_int(s);
+
+        /*
+         * TODO: could we 'break' here for reset? following operations appear
+         * to duplicate the work imx_epit_reset() already did.
+         */
+
         ptimer_transaction_begin(s->timer_cmp);
         ptimer_transaction_begin(s->timer_reload);
 
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
 /*
  * This is called both on hardware (device) reset and software reset.
  */
-static void imx_epit_reset(DeviceState *dev)
+static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
 {
-    IMXEPITState *s = IMX_EPIT(dev);
-
     /* Soft reset doesn't touch some bits; hard reset clears them */
-    s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
+    if (is_hard_reset) {
+        s->cr = 0;
+    } else {
+        s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
+    }
     s->sr = 0;
     s->lr = EPIT_TIMER_MAX;
     s->cmp = 0;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
         s->cr = value & 0x03ffffff;
         if (s->cr & CR_SWR) {
             /* handle the reset */
-            imx_epit_reset(DEVICE(s));
+            imx_epit_reset(s, false);
         }
 
         /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
     s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
 }
 
+static void imx_epit_dev_reset(DeviceState *dev)
+{
+    IMXEPITState *s = IMX_EPIT(dev);
+    imx_epit_reset(s, true);
+}
+
 static void imx_epit_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc  = DEVICE_CLASS(klass);
 
     dc->realize = imx_epit_realize;
-    dc->reset = imx_epit_reset;
+    dc->reset = imx_epit_dev_reset;
     dc->vmsd = &vmstate_imx_timer_epit;
     dc->desc = "i.MX periodic timer";
 }
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++--------------------
 1 file changed, 117 insertions(+), 98 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
     }
 }
 
+static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
+{
+    uint32_t oldcr = s->cr;
+
+    s->cr = value & 0x03ffffff;
+
+    if (s->cr & CR_SWR) {
+        /* handle the reset */
+        imx_epit_reset(s, false);
+    }
+
+    /*
+     * The interrupt state can change due to:
+     * - reset clears both SR.OCIF and CR.OCIE
+     * - write to CR.EN or CR.OCIE
+     */
+    imx_epit_update_int(s);
+
+    /*
+     * TODO: could we 'break' here for reset? following operations appear
+     * to duplicate the work imx_epit_reset() already did.
+     */
+
+    ptimer_transaction_begin(s->timer_cmp);
+    ptimer_transaction_begin(s->timer_reload);
+
+    /* Update the frequency. Has been done already in case of a reset. */
+    if (!(s->cr & CR_SWR)) {
+        imx_epit_set_freq(s);
+    }
+
+    if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
+        if (s->cr & CR_ENMOD) {
+            if (s->cr & CR_RLD) {
+                ptimer_set_limit(s->timer_reload, s->lr, 1);
+                ptimer_set_limit(s->timer_cmp, s->lr, 1);
+            } else {
+                ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
+                ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
+            }
+        }
+
+        imx_epit_reload_compare_timer(s);
+        ptimer_run(s->timer_reload, 0);
+        if (s->cr & CR_OCIEN) {
+            ptimer_run(s->timer_cmp, 0);
+        } else {
+            ptimer_stop(s->timer_cmp);
+        }
+    } else if (!(s->cr & CR_EN)) {
+        /* stop both timers */
+        ptimer_stop(s->timer_reload);
+        ptimer_stop(s->timer_cmp);
+    } else  if (s->cr & CR_OCIEN) {
+        if (!(oldcr & CR_OCIEN)) {
+            imx_epit_reload_compare_timer(s);
+            ptimer_run(s->timer_cmp, 0);
+        }
+    } else {
+        ptimer_stop(s->timer_cmp);
+    }
+
+    ptimer_transaction_commit(s->timer_cmp);
+    ptimer_transaction_commit(s->timer_reload);
+}
+
+static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
+{
+    /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
+    if (value & SR_OCIF) {
+        s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
+        imx_epit_update_int(s);
+    }
+}
+
+static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
+{
+    s->lr = value;
+
+    ptimer_transaction_begin(s->timer_cmp);
+    ptimer_transaction_begin(s->timer_reload);
+    if (s->cr & CR_RLD) {
+        /* Also set the limit if the LRD bit is set */
+        /* If IOVW bit is set then set the timer value */
+        ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
+        ptimer_set_limit(s->timer_cmp, s->lr, 0);
+    } else if (s->cr & CR_IOVW) {
+        /* If IOVW bit is set then set the timer value */
+        ptimer_set_count(s->timer_reload, s->lr);
+    }
+    /*
+     * Commit the change to s->timer_reload, so it can propagate. Otherwise
+     * the timer interrupt may not fire properly. The commit must happen
+     * before calling imx_epit_reload_compare_timer(), which reads
+     * s->timer_reload internally again.
+     */
+    ptimer_transaction_commit(s->timer_reload);
+    imx_epit_reload_compare_timer(s);
+    ptimer_transaction_commit(s->timer_cmp);
+}
+
+static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
+{
+    s->cmp = value;
+
+    ptimer_transaction_begin(s->timer_cmp);
+    imx_epit_reload_compare_timer(s);
+    ptimer_transaction_commit(s->timer_cmp);
+}
+
 static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
 {
     IMXEPITState *s = IMX_EPIT(opaque);
-    uint64_t oldcr;
 
     DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
             (uint32_t)value);
 
     switch (offset >> 2) {
     case 0: /* CR */
-
-        oldcr = s->cr;
-        s->cr = value & 0x03ffffff;
-        if (s->cr & CR_SWR) {
-            /* handle the reset */
-            imx_epit_reset(s, false);
-        }
-
-        /*
-         * The interrupt state can change due to:
-         * - reset clears both SR.OCIF and CR.OCIE
-         * - write to CR.EN or CR.OCIE
-         */
-        imx_epit_update_int(s);
-
-        /*
-         * TODO: could we 'break' here for reset? following operations appear
-         * to duplicate the work imx_epit_reset() already did.
-         */
-
-        ptimer_transaction_begin(s->timer_cmp);
-        ptimer_transaction_begin(s->timer_reload);
-
-        /* Update the frequency. Has been done already in case of a reset. */
-        if (!(s->cr & CR_SWR)) {
-            imx_epit_set_freq(s);
-        }
-
-        if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
-            if (s->cr & CR_ENMOD) {
-                if (s->cr & CR_RLD) {
-                    ptimer_set_limit(s->timer_reload, s->lr, 1);
-                    ptimer_set_limit(s->timer_cmp, s->lr, 1);
-                } else {
-                    ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
-                    ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
-                }
-            }
-
-            imx_epit_reload_compare_timer(s);
-            ptimer_run(s->timer_reload, 0);
-            if (s->cr & CR_OCIEN) {
-                ptimer_run(s->timer_cmp, 0);
-            } else {
-                ptimer_stop(s->timer_cmp);
-            }
-        } else if (!(s->cr & CR_EN)) {
-            /* stop both timers */
-            ptimer_stop(s->timer_reload);
-            ptimer_stop(s->timer_cmp);
-        } else  if (s->cr & CR_OCIEN) {
-            if (!(oldcr & CR_OCIEN)) {
-                imx_epit_reload_compare_timer(s);
-                ptimer_run(s->timer_cmp, 0);
-            }
-        } else {
-            ptimer_stop(s->timer_cmp);
-        }
-
-        ptimer_transaction_commit(s->timer_cmp);
-        ptimer_transaction_commit(s->timer_reload);
+        imx_epit_write_cr(s, (uint32_t)value);
         break;
 
-    case 1: /* SR - ACK*/
-        /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
-        if (value & SR_OCIF) {
-            s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
-            imx_epit_update_int(s);
-        }
+    case 1: /* SR */
+        imx_epit_write_sr(s, (uint32_t)value);
         break;
 
-    case 2: /* LR - set ticks */
-        s->lr = value;
-
-        ptimer_transaction_begin(s->timer_cmp);
-        ptimer_transaction_begin(s->timer_reload);
-        if (s->cr & CR_RLD) {
-            /* Also set the limit if the LRD bit is set */
-            /* If IOVW bit is set then set the timer value */
-            ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
-            ptimer_set_limit(s->timer_cmp, s->lr, 0);
-        } else if (s->cr & CR_IOVW) {
-            /* If IOVW bit is set then set the timer value */
-            ptimer_set_count(s->timer_reload, s->lr);
-        }
-        /*
-         * Commit the change to s->timer_reload, so it can propagate. Otherwise
-         * the timer interrupt may not fire properly. The commit must happen
-         * before calling imx_epit_reload_compare_timer(), which reads
-         * s->timer_reload internally again.
-         */
-        ptimer_transaction_commit(s->timer_reload);
-        imx_epit_reload_compare_timer(s);
-        ptimer_transaction_commit(s->timer_cmp);
+    case 2: /* LR */
+        imx_epit_write_lr(s, (uint32_t)value);
         break;
 
     case 3: /* CMP */
-        s->cmp = value;
-
-        ptimer_transaction_begin(s->timer_cmp);
-        imx_epit_reload_compare_timer(s);
-        ptimer_transaction_commit(s->timer_cmp);
-
+        imx_epit_write_cmp(s, (uint32_t)value);
         break;
 
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
                       HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
-
         break;
     }
 }
+
 static void imx_epit_cmp(void *opaque)
 {
     IMXEPITState *s = IMX_EPIT(opaque);
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.

Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/imx_epit.h |  2 -
 hw/timer/imx_epit.c         | 73 ++++++++++++++-----------------------
 2 files changed, 28 insertions(+), 47 deletions(-)

diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/imx_epit.h
+++ b/include/hw/timer/imx_epit.h
@@ -XXX,XX +XXX,XX @@ struct IMXEPITState {
     uint32_t sr;
     uint32_t lr;
     uint32_t cmp;
-    uint32_t cnt;
 
-    uint32_t freq;
     qemu_irq irq;
 };
 
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s)
     }
 }
 
-/*
- * Must be called from within a ptimer_transaction_begin/commit block
- * for both s->timer_cmp and s->timer_reload.
- */
-static void imx_epit_set_freq(IMXEPITState *s)
+static uint32_t imx_epit_get_freq(IMXEPITState *s)
 {
-    uint32_t clksrc;
-    uint32_t prescaler;
-
-    clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
-    prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
-
-    s->freq = imx_ccm_get_clock_frequency(s->ccm,
-                                imx_epit_clocks[clksrc]) / prescaler;
-
-    DPRINTF("Setting ptimer frequency to %u\n", s->freq);
-
-    if (s->freq) {
-        ptimer_set_freq(s->timer_reload, s->freq);
-        ptimer_set_freq(s->timer_cmp, s->freq);
-    }
+    uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
+    uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
+    uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
+    uint32_t freq = f_in / prescaler;
+    DPRINTF("ptimer frequency is %u\n", freq);
+    return freq;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
     s->sr = 0;
     s->lr = EPIT_TIMER_MAX;
     s->cmp = 0;
-    s->cnt = 0;
     ptimer_transaction_begin(s->timer_cmp);
     ptimer_transaction_begin(s->timer_reload);
-    /* stop both timers */
+
+    /*
+     * The reset switches off the input clock, so even if the CR.EN is still
+     * set, the timers are no longer running.
+     */
+    assert(imx_epit_get_freq(s) == 0);
     ptimer_stop(s->timer_cmp);
     ptimer_stop(s->timer_reload);
-    /* compute new frequency */
-    imx_epit_set_freq(s);
     /* init both timers to EPIT_TIMER_MAX */
     ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
     ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
-    if (s->freq && (s->cr & CR_EN)) {
-        /* if the timer is still enabled, restart it */
-        ptimer_run(s->timer_reload, 0);
-    }
     ptimer_transaction_commit(s->timer_cmp);
     ptimer_transaction_commit(s->timer_reload);
 }
 
-static uint32_t imx_epit_update_count(IMXEPITState *s)
-{
-    s->cnt = ptimer_get_count(s->timer_reload);
-
-    return s->cnt;
-}
-
 static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
 {
     IMXEPITState *s = IMX_EPIT(opaque);
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
         break;
 
     case 4: /* CNT */
-        imx_epit_update_count(s);
-        reg_value = s->cnt;
+        reg_value = ptimer_get_count(s->timer_reload);
         break;
 
     default:
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
 {
     if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN))  {
         /* if the compare feature is on and timers are running */
-        uint32_t tmp = imx_epit_update_count(s);
+        uint32_t tmp = ptimer_get_count(s->timer_reload);
         uint64_t next;
         if (tmp > s->cmp) {
             /* It'll fire in this round of the timer */
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
 
 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
 {
+    uint32_t freq = 0;
     uint32_t oldcr = s->cr;
 
     s->cr = value & 0x03ffffff;
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
     ptimer_transaction_begin(s->timer_cmp);
     ptimer_transaction_begin(s->timer_reload);
 
-    /* Update the frequency. Has been done already in case of a reset. */
+    /*
+     * Update the frequency. In case of a reset the input clock was
+     * switched off, so this can be skipped.
+     */
     if (!(s->cr & CR_SWR)) {
-        imx_epit_set_freq(s);
+        freq = imx_epit_get_freq(s);
+        if (freq) {
+            ptimer_set_freq(s->timer_reload, freq);
+            ptimer_set_freq(s->timer_cmp, freq);
+        }
     }
 
-    if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
+    if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
         if (s->cr & CR_ENMOD) {
             if (s->cr & CR_RLD) {
                 ptimer_set_limit(s->timer_reload, s->lr, 1);
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx_epit_ops = {
 
 static const VMStateDescription vmstate_imx_timer_epit = {
     .name = TYPE_IMX_EPIT,
-    .version_id = 2,
-    .minimum_version_id = 2,
+    .version_id = 3,
+    .minimum_version_id = 3,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(cr, IMXEPITState),
         VMSTATE_UINT32(sr, IMXEPITState),
         VMSTATE_UINT32(lr, IMXEPITState),
         VMSTATE_UINT32(cmp, IMXEPITState),
-        VMSTATE_UINT32(cnt, IMXEPITState),
-        VMSTATE_UINT32(freq, IMXEPITState),
         VMSTATE_PTIMER(timer_reload, IMXEPITState),
         VMSTATE_PTIMER(timer_cmp, IMXEPITState),
         VMSTATE_END_OF_LIST()
-- 
2.25.1

From: Axel Heider <axel.heider@hensoldt.net>

- fix #1263 for CR writes
- rework compare time handling
  - The compare timer has to run even if CR.OCIEN is not set,
    as SR.OCIF must be updated.
  - The compare timer fires exactly once when the
    compare value is less than the current value, but the
    reload values is less than the compare value.
  - The compare timer will never fire if the reload value is
    less than the compare value. Disable it in this case.

Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
[PMM: fixed minor style nits]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------
 1 file changed, 116 insertions(+), 76 deletions(-)

diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -XXX,XX +XXX,XX @@
  * Originally written by Hans Jiang
  * Updated by Peter Chubb
  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
+ * Updated by Axel Heider
  *
  * This code is licensed under GPL version 2 or later.  See
  * the COPYING file in the top-level directory.
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
     return reg_value;
 }
 
-/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
-static void imx_epit_reload_compare_timer(IMXEPITState *s)
+/*
+ * Must be called from a ptimer_transaction_begin/commit block for
+ * s->timer_cmp, but outside of a transaction block of s->timer_reload,
+ * so the proper counter value is read.
+ */
+static void imx_epit_update_compare_timer(IMXEPITState *s)
 {
-    if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN))  {
-        /* if the compare feature is on and timers are running */
-        uint32_t tmp = ptimer_get_count(s->timer_reload);
-        uint64_t next;
-        if (tmp > s->cmp) {
-            /* It'll fire in this round of the timer */
-            next = tmp - s->cmp;
-        } else { /* catch it next time around */
-            next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
+    uint64_t counter = 0;
+    bool is_oneshot = false;
+    /*
+     * The compare timer only has to run if the timer peripheral is active
+     * and there is an input clock, Otherwise it can be switched off.
+     */
+    bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
+    if (is_active) {
+        /*
+         * Calculate next timeout for compare timer. Reading the reload
+         * counter returns proper results only if pending transactions
+         * on it are committed here. Otherwise stale values are be read.
+         */
+        counter = ptimer_get_count(s->timer_reload);
+        uint64_t limit = ptimer_get_limit(s->timer_cmp);
+        /*
+         * The compare timer is a periodic timer if the limit is at least
+         * the compare value. Otherwise it may fire at most once in the
+         * current round.
+         */
+        bool is_oneshot = (limit >= s->cmp);
+        if (counter >= s->cmp) {
+            /* The compare timer fires in the current round. */
+            counter -= s->cmp;
+        } else if (!is_oneshot) {
+            /*
+             * The compare timer fires after a reload, as it is below the
+             * compare value already in this round. Note that the counter
+             * value calculated below can be above the 32-bit limit, which
+             * is legal here because the compare timer is an internal
+             * helper ptimer only.
+             */
+            counter += limit - s->cmp;
+        } else {
+            /*
+             * The compare timer won't fire in this round, and the limit is
+             * set to a value below the compare value. This practically means
+             * it will never fire, so it can be switched off.
+             */
+            is_active = false;
         }
-        ptimer_set_count(s->timer_cmp, next);
     }
+
+    /*
+     * Set the compare timer and let it run, or stop it. This is agnostic
+     * of CR.OCIEN bit, as this bit affects interrupt generation only. The
+     * compare timer needs to run even if no interrupts are to be generated,
+     * because the SR.OCIF bit must be updated also.
+     * Note that the timer might already be stopped or be running with
+     * counter values. However, finding out when an update is needed and
+     * when not is not trivial. It's much easier applying the setting again,
+     * as this does not harm either and the overhead is negligible.
+     */
+    if (is_active) {
+        ptimer_set_count(s->timer_cmp, counter);
+        ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
+    } else {
+        ptimer_stop(s->timer_cmp);
+    }
+
 }
 
 static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
 {
-    uint32_t freq = 0;
     uint32_t oldcr = s->cr;
 
     s->cr = value & 0x03ffffff;
 
     if (s->cr & CR_SWR) {
-        /* handle the reset */
+        /*
+         * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
+         * are still stopped because the input clock is disabled.
+         */
         imx_epit_reset(s, false);
+    } else {
+        uint32_t freq;
+        uint32_t toggled_cr_bits = oldcr ^ s->cr;
+        /* re-initialize the limits if CR.RLD has changed */
+        bool set_limit = toggled_cr_bits & CR_RLD;
+        /* set the counter if the timer got just enabled and CR.ENMOD is set */
+        bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
+        bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
+
+        ptimer_transaction_begin(s->timer_cmp);
+        ptimer_transaction_begin(s->timer_reload);
+        freq = imx_epit_get_freq(s);
+        if (freq) {
+            ptimer_set_freq(s->timer_reload, freq);
+            ptimer_set_freq(s->timer_cmp, freq);
+        }
+
+        if (set_limit || set_counter) {
+            uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
+            ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
+            if (set_limit) {
+                ptimer_set_limit(s->timer_cmp, limit, 0);
+            }
+        }
+        /*
+         * If there is an input clock and the peripheral is enabled, then
+         * ensure the wall clock timer is ticking. Otherwise stop the timers.
+         * The compare timer will be updated later.
+         */
+        if (freq && (s->cr & CR_EN)) {
+            ptimer_run(s->timer_reload, 0);
+        } else {
+            ptimer_stop(s->timer_reload);
+        }
+        /* Commit changes to reload timer, so they can propagate. */
+        ptimer_transaction_commit(s->timer_reload);
+        /* Update compare timer based on the committed reload timer value. */
+        imx_epit_update_compare_timer(s);
+        ptimer_transaction_commit(s->timer_cmp);
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
      * - write to CR.EN or CR.OCIE
      */
     imx_epit_update_int(s);
-
-    /*
-     * TODO: could we 'break' here for reset? following operations appear
-     * to duplicate the work imx_epit_reset() already did.
-     */
-
-    ptimer_transaction_begin(s->timer_cmp);
-    ptimer_transaction_begin(s->timer_reload);
-
-    /*
-     * Update the frequency. In case of a reset the input clock was
-     * switched off, so this can be skipped.
-     */
-    if (!(s->cr & CR_SWR)) {
-        freq = imx_epit_get_freq(s);
-        if (freq) {
-            ptimer_set_freq(s->timer_reload, freq);
-            ptimer_set_freq(s->timer_cmp, freq);
-        }
-    }
-
-    if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
-        if (s->cr & CR_ENMOD) {
-            if (s->cr & CR_RLD) {
-                ptimer_set_limit(s->timer_reload, s->lr, 1);
-                ptimer_set_limit(s->timer_cmp, s->lr, 1);
-            } else {
-                ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
-                ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
-            }
-        }
-
-        imx_epit_reload_compare_timer(s);
-        ptimer_run(s->timer_reload, 0);
-        if (s->cr & CR_OCIEN) {
-            ptimer_run(s->timer_cmp, 0);
-        } else {
-            ptimer_stop(s->timer_cmp);
-        }
-    } else if (!(s->cr & CR_EN)) {
-        /* stop both timers */
-        ptimer_stop(s->timer_reload);
-        ptimer_stop(s->timer_cmp);
-    } else  if (s->cr & CR_OCIEN) {
-        if (!(oldcr & CR_OCIEN)) {
-            imx_epit_reload_compare_timer(s);
-            ptimer_run(s->timer_cmp, 0);
-        }
-    } else {
-        ptimer_stop(s->timer_cmp);
-    }
-
-    ptimer_transaction_commit(s->timer_cmp);
-    ptimer_transaction_commit(s->timer_reload);
 }
 
 static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
         /* If IOVW bit is set then set the timer value */
         ptimer_set_count(s->timer_reload, s->lr);
     }
-    /*
-     * Commit the change to s->timer_reload, so it can propagate. Otherwise
-     * the timer interrupt may not fire properly. The commit must happen
-     * before calling imx_epit_reload_compare_timer(), which reads
-     * s->timer_reload internally again.
-     */
+    /* Commit the changes to s->timer_reload, so they can propagate. */
     ptimer_transaction_commit(s->timer_reload);
-    imx_epit_reload_compare_timer(s);
+    /* Update the compare timer based on the committed reload timer value. */
+    imx_epit_update_compare_timer(s);
     ptimer_transaction_commit(s->timer_cmp);
 }
 
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
 {
     s->cmp = value;
 
+    /* Update the compare timer based on the committed reload timer value. */
     ptimer_transaction_begin(s->timer_cmp);
-    imx_epit_reload_compare_timer(s);
+    imx_epit_update_compare_timer(s);
     ptimer_transaction_commit(s->timer_cmp);
 }
 
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
 {
     IMXEPITState *s = IMX_EPIT(opaque);
 
+    /* The cmp ptimer can't be running when the peripheral is disabled */
+    assert(s->cr & CR_EN);
+
     DPRINTF("sr was %d\n", s->sr);
     /* Set interrupt status bit SR.OCIF and update the interrupt state */
     s->sr |= SR_OCIF;
-- 
2.25.1

From: Fabiano Rosas <farosas@suse.de>

Fix these:

WARNING: Block comments use a leading /* on a separate line
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-2-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 323 +++++++++++++++++++++++++++++---------------
 1 file changed, 215 insertions(+), 108 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
                              uint64_t v)
 {
-    /* Raw write of a coprocessor register (as needed for migration, etc).
+    /*
+     * Raw write of a coprocessor register (as needed for migration, etc).
      * Note that constant registers are treated as write-ignored; the
      * caller should check for success by whether a readback gives the
      * value written.
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 {
-   /* Return true if the regdef would cause an assertion if you called
+   /*
+    * Return true if the regdef would cause an assertion if you called
     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
     * program bug for it not to have the NO_RAW flag).
     * NB that returning false here doesn't necessarily mean that calling
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
         if (ri->type & ARM_CP_NO_RAW) {
             continue;
         }
-        /* Write value and confirm it reads back as written
+        /*
+         * Write value and confirm it reads back as written
          * (to catch read-only registers and partially read-only
          * registers where the incoming migration value doesn't match)
          */
@@ -XXX,XX +XXX,XX @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 
 void init_cpreg_list(ARMCPU *cpu)
 {
-    /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
+    /*
+     * Initialise the cpreg_tuples[] array based on the cp_regs hash.
      * Note that we require cpreg_tuples[] to be sorted by key ID.
      */
     GList *keys;
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
     return CP_ACCESS_OK;
 }
 
-/* Some secure-only AArch32 registers trap to EL3 if used from
+/*
+ * Some secure-only AArch32 registers trap to EL3 if used from
  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
  * We assume that the .access field is set to PL1_RW.
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
     return CP_ACCESS_TRAP_UNCATEGORIZED;
 }
 
-/* Check for traps to performance monitor registers, which are controlled
+/*
+ * Check for traps to performance monitor registers, which are controlled
  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
  */
 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     ARMCPU *cpu = env_archcpu(env);
 
     if (raw_read(env, ri) != value) {
-        /* Unlike real hardware the qemu TLB uses virtual addresses,
+        /*
+         * Unlike real hardware the qemu TLB uses virtual addresses,
          * not modified virtual addresses, so this causes a TLB flush.
          */
         tlb_flush(CPU(cpu));
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
         && !extended_addresses_enabled(env)) {
-        /* For VMSA (when not using the LPAE long descriptor page table
+        /*
+         * For VMSA (when not using the LPAE long descriptor page table
          * format) this register includes the ASID, so do a TLB flush.
          * For PMSA it is purely a process ID and no action is needed.
          */
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 static const ARMCPRegInfo cp_reginfo[] = {
-    /* Define the secure and non-secure FCSE identifier CP registers
+    /*
+     * Define the secure and non-secure FCSE identifier CP registers
      * separately because there is no secure bank in V8 (no _EL3).  This allows
      * the secure register to be properly reset and migrated. There is also no
      * v8 EL1 version of the register so the non-secure instance stands alone.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
-    /* Define the secure and non-secure context identifier CP registers
+    /*
+     * Define the secure and non-secure context identifier CP registers
      * separately because there is no secure bank in V8 (no _EL3).  This allows
      * the secure register to be properly reset and migrated.  In the
      * non-secure case, the 32-bit register will have reset and migration
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
-    /* NB: Some of these registers exist in v8 but with more precise
+    /*
+     * NB: Some of these registers exist in v8 but with more precise
      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
      */
     /* MMU Domain access control / MPU write buffer control */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
       .writefn = dacr_write, .raw_writefn = raw_write,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
-    /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
+    /*
+     * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
      * For v6 and v5, these mappings are overly broad.
      */
     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
-    /* Not all pre-v6 cores implemented this WFI, so this is slightly
+    /*
+     * Not all pre-v6 cores implemented this WFI, so this is slightly
      * over-broad.
      */
     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
-    /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
+    /*
+     * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
      * is UNPREDICTABLE; we choose to NOP as most implementations do).
      */
     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
       .access = PL1_W, .type = ARM_CP_WFI },
-    /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
+    /*
+     * L1 cache lockdown. Not architectural in v6 and earlier but in practice
      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
      * OMAPCP will override this space.
      */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
       .resetvalue = 0 },
-    /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
+    /*
+     * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
      * implementing it as RAZ means the "debug architecture version" bits
      * will read as a reserved value, which should cause Linux to not try
      * to use the debug hardware.
      */
     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
-    /* MMU TLB control. Note that the wildcarding means we cover not just
+    /*
+     * MMU TLB control. Note that the wildcarding means we cover not just
      * the unified TLB ops but also the dside/iside/inner-shareable variants.
      */
     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
     if (!arm_feature(env, ARM_FEATURE_V8)) {
-        /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
+        /*
+         * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
          */
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                 value |= R_CPACR_ASEDIS_MASK;
             }
 
-            /* VFPv3 and upwards with NEON implement 32 double precision
+            /*
+             * VFPv3 and upwards with NEON implement 32 double precision
              * registers (D0-D31).
              */
             if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 
 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    /* Call cpacr_write() so that we reset with the correct RAO bits set
+    /*
+     * Call cpacr_write() so that we reset with the correct RAO bits set
      * for our CPU features.
      */
     cpacr_write(env, ri, 0);
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { .name = "MVA_prefetch",
       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NOP },
-    /* We need to break the TB after ISB to execute self-modifying code
+    /*
+     * We need to break the TB after ISB to execute self-modifying code
      * correctly and also to take any pending interrupts immediately.
      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
      */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
                              offsetof(CPUARMState, cp15.ifar_ns) },
       .resetvalue = 0, },
-    /* Watchpoint Fault Address Register : should actually only be present
+    /*
+     * Watchpoint Fault Address Register : should actually only be present
      * for 1136, 1176, 11MPCore.
      */
     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static bool event_supported(uint16_t number)
 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
-    /* Performance monitor registers user accessibility is controlled
+    /*
+     * Performance monitor registers user accessibility is controlled
      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
      * trapping to EL2 or EL3 for other accesses.
      */
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
     (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
 
-/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
+/*
+ * Returns true if the counter (pass 31 for PMCCNTR) should count events using
  * the current EL, security state, and register configuration.
  */
 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                          uint64_t value)
 {
-    /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
+    /*
+     * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
      * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
      * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
      * accessed.
@@ -XXX,XX +XXX,XX @@ static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
         env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
         pmevcntr_op_finish(env, counter);
     }
-    /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
+    /*
+     * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
      * PMSELR value is equal to or greater than the number of implemented
      * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
      */
@@ -XXX,XX +XXX,XX @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
         }
         return ret;
     } else {
-      /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
-       * are CONSTRAINED UNPREDICTABLE. */
+      /*
+       * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
+       * are CONSTRAINED UNPREDICTABLE.
+       */
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                        uint64_t value)
 {
-    /* Note that even though the AArch64 view of this register has bits
+    /*
+     * Note that even though the AArch64 view of this register has bits
      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
      * architectural requirements for bits which are RES0 only in some
      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
         valid_mask &= ~SCR_HCE;
 
-        /* On ARMv7, SMD (or SCD as it is called in v7) is only
+        /*
+         * On ARMv7, SMD (or SCD as it is called in v7) is only
          * supported if EL2 exists. The bit is UNK/SBZP when
          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
          * when EL2 is unavailable.
@@ -XXX,XX +XXX,XX @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
 
-    /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
+    /*
+     * Acquire the CSSELR index from the bank corresponding to the CCSIDR
      * bank
      */
     uint32_t index = A32_BANKED_REG_GET(env, csselr,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
       .access = PL1_W, .type = ARM_CP_NOP },
-    /* Performance monitors are implementation defined in v7,
+    /*
+     * Performance monitors are implementation defined in v7,
      * but with an ARM recommended set of registers, which we
      * follow.
      *
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .writefn = csselr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
                              offsetof(CPUARMState, cp15.csselr_ns) } },
-    /* Auxiliary ID register: this actually has an IMPDEF value but for now
+    /*
+     * Auxiliary ID register: this actually has an IMPDEF value but for now
      * just RAZ for all cores:
      */
     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST,
       .accessfn = access_aa64_tid1,
       .resetvalue = 0 },
-    /* Auxiliary fault status registers: these also are IMPDEF, and we
+    /*
+     * Auxiliary fault status registers: these also are IMPDEF, and we
      * choose to RAZ/WI for all cores.
      */
     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
       .type = ARM_CP_CONST, .resetvalue = 0 },
-    /* MAIR can just read-as-written because we don't implement caches
+    /*
+     * MAIR can just read-as-written because we don't implement caches
      * and so don't need to care about memory attributes.
      */
     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
       .resetvalue = 0 },
-    /* For non-long-descriptor page tables these are PRRR and NMRR;
+    /*
+     * For non-long-descriptor page tables these are PRRR and NMRR;
      * regardless they still act as reads-as-written for QEMU.
      */
-     /* MAIR0/1 are defined separately from their 64-bit counterpart which
+     /*
+      * MAIR0/1 are defined separately from their 64-bit counterpart which
       * allows them to assign the correct fieldoffset based on the endianness
       * handled in the field definitions.
       */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                        bool isread)
 {
-    /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
+    /*
+     * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
      * Writable only at the highest implemented exception level.
      */
     int el = arm_current_el(env);
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
                                        const ARMCPRegInfo *ri,
                                        bool isread)
 {
-    /* The AArch64 register view of the secure physical timer is
+    /*
+     * The AArch64 register view of the secure physical timer is
      * always accessible from EL3, and configurably accessible from
      * Secure EL1.
      */
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 
     if (gt->ctl & 1) {
-        /* Timer enabled: calculate and set current ISTATUS, irq, and
+        /*
+         * Timer enabled: calculate and set current ISTATUS, irq, and
          * reset timer to when ISTATUS next has to change
          */
         uint64_t offset = timeridx == GTIMER_VIRT ?
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
             /* Next transition is when we hit cval */
             nexttick = gt->cval + offset;
         }
-        /* Note that the desired next expiry time might be beyond the
+        /*
+         * Note that the desired next expiry time might be beyond the
          * signed-64-bit range of a QEMUTimer -- in this case we just
          * set the timer for as far in the future as possible. When the
          * timer expires we will reset the timer for any remaining period.
@@ -XXX,XX +XXX,XX @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
         /* Enable toggled */
         gt_recalc_timer(cpu, timeridx);
     } else if ((oldval ^ value) & 2) {
-        /* IMASK toggled: don't need to recalculate,
+        /*
+         * IMASK toggled: don't need to recalculate,
          * just set the interrupt line based on ISTATUS
          */
         int irqstate = (oldval & 4) && !(value & 2);
@@ -XXX,XX +XXX,XX @@ static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
 }
 
 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
-    /* Note that CNTFRQ is purely reads-as-written for the benefit
+    /*
+     * Note that CNTFRQ is purely reads-as-written for the benefit
      * of software; writing it doesn't actually change the timer frequency.
      * Our reset value matches the fixed frequency we implement the timer at.
      */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       .readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
       .writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
     },
-    /* Secure timer -- this is actually restricted to only EL3
+    /*
+     * Secure timer -- this is actually restricted to only EL3
      * and configurably Secure-EL1 via the accessfn.
      */
     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
 
 #else
 
-/* In user-mode most of the generic timer registers are inaccessible
+/*
+ * In user-mode most of the generic timer registers are inaccessible
  * however modern kernels (4.12+) allow access to cntvct_el0
  */
 
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
 
-    /* Currently we have no support for QEMUTimer in linux-user so we
+    /*
+     * Currently we have no support for QEMUTimer in linux-user so we
      * can't call gt_get_countervalue(env), instead we directly
      * call the lower level functions.
      */
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                  bool isread)
 {
     if (ri->opc2 & 4) {
-        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
+        /*
+         * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
          * Secure EL1 (which can only happen if EL3 is AArch64).
          * They are simply UNDEF if executed from NS EL1.
          * They function normally from EL2 or EL3.
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
             }
         }
     } else {
-        /* fsr is a DFSR/IFSR value for the short descriptor
+        /*
+         * fsr is a DFSR/IFSR value for the short descriptor
          * translation table format (with WnR always clear).
          * Convert it to a 32-bit PAR.
          */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
-    /* Reset for all these registers is handled in arm_cpu_reset(),
+    /*
+     * Reset for all these registers is handled in arm_cpu_reset(),
      * because the PMSAv7 is also used by M-profile CPUs, which do
      * not register cpregs but still need the state to be reset.
      */
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 
     if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        /* With LPAE the TTBCR could result in a change of ASID
+        /*
+         * With LPAE the TTBCR could result in a change of ASID
          * via the TTBCR.A1 bit, so do a TLB flush.
          */
         tlb_flush(CPU(cpu));
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
 };
 
-/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
+/*
+ * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
  * qemu tlbs nor adjusting cached masks.
  */
 static const ARMCPRegInfo ttbcr2_reginfo = {
@@ -XXX,XX +XXX,XX @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                   uint64_t value)
 {
-    /* On OMAP there are registers indicating the max/min index of dcache lines
+    /*
+     * On OMAP there are registers indicating the max/min index of dcache lines
      * containing a dirty line; cache flush operations have to reset these.
      */
     env->cp15.c15_i_max = 0x000;
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
       .type = ARM_CP_NO_RAW,
       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
-    /* TODO: Peripheral port remap register:
+    /*
+     * TODO: Peripheral port remap register:
      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
      * when MMU is off.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
       .resetvalue = 0, },
-    /* XScale specific cache-lockdown: since we have no cache we NOP these
+    /*
+     * XScale specific cache-lockdown: since we have no cache we NOP these
      * and hope the guest does not really rely on cache behaviour.
      */
     { .name = "XSCALE_LOCK_ICACHE_LINE",
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
-    /* RAZ/WI the whole crn=15 space, when we don't have a more specific
+    /*
+     * RAZ/WI the whole crn=15 space, when we don't have a more specific
      * implementation of this implementation-defined space.
      * Ideally this should eventually disappear in favour of actually
      * implementing the correct behaviour for all cores.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
 };
 
 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
-    /* The cache test-and-clean instructions always return (1 << 30)
+    /*
+     * The cache test-and-clean instructions always return (1 << 30)
      * to indicate that there are no dirty cache lines.
      */
     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static uint64_t mpidr_read_val(CPUARMState *env)
 
     if (arm_feature(env, ARM_FEATURE_V7MP)) {
         mpidr |= (1U << 31);
-        /* Cores which are uniprocessor (non-coherent)
+        /*
+         * Cores which are uniprocessor (non-coherent)
          * but still implement the MP extensions set
          * bit 30. (For instance, Cortex-R5).
          */
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
     return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
 }
 
-/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
+/*
+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
  * Page D4-1736 (DDI0487A.b)
  */
 
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
-    /* Invalidate by VA, EL2
+    /*
+     * Invalidate by VA, EL2
      * Currently handles both VAE2 and VALE2, since we don't support
      * flush-last-level-only.
      */
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
-    /* Invalidate by VA, EL3
+    /*
+     * Invalidate by VA, EL3
      * Currently handles both VAE3 and VALE3, since we don't support
      * flush-last-level-only.
      */
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                  uint64_t value)
 {
-    /* Invalidate by VA, EL1&0 (AArch64 version).
+    /*
+     * Invalidate by VA, EL1&0 (AArch64 version).
      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
      * since we don't support flush-for-specific-ASID-only or
      * flush-last-level-only.
@@ -XXX,XX +XXX,XX @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                     bool isread)
 {
     if (!(env->pstate & PSTATE_SP)) {
-        /* Access to SP_EL0 is undefined if it's being used as
+        /*
+         * Access to SP_EL0 is undefined if it's being used as
          * the stack pointer.
          */
         return CP_ACCESS_TRAP_UNCATEGORIZED;
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     }
 
     if (raw_read(env, ri) == value) {
-        /* Skip the TLB flush if nothing actually changed; Linux likes
+        /*
+         * Skip the TLB flush if nothing actually changed; Linux likes
          * to do a lot of pointless SCTLR writes.
          */
         return;
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 static const ARMCPRegInfo v8_cp_reginfo[] = {
-    /* Minimal set of EL0-visible registers. This will need to be expanded
+    /*
+     * Minimal set of EL0-visible registers. This will need to be expanded
      * significantly for system emulation of AArch64 CPUs.
      */
     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
       .access = PL1_RW,
       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
-    /* We rely on the access checks not allowing the guest to write to the
+    /*
+     * We rely on the access checks not allowing the guest to write to the
      * state field when SPSel indicates that it's being used as the stack
      * pointer.
      */
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         valid_mask &= ~HCR_HCD;
     } else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
-        /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
+        /*
+         * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
          * However, if we're using the SMC PSCI conduit then QEMU is
          * effectively acting like EL3 firmware and so the guest at
          * EL2 should retain the ability to prevent EL1 from being
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = tlbi_aa64_vae2is_write },
 #ifndef CONFIG_USER_ONLY
-    /* Unlike the other EL2-related AT operations, these must
+    /*
+     * Unlike the other EL2-related AT operations, these must
      * UNDEF from EL3 if EL2 is not implemented, which is why we
      * define them here rather than with the rest of the AT ops.
      */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .access = PL2_W, .accessfn = at_s1e2_access,
       .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
       .writefn = ats_write64 },
-    /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
+    /*
+     * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
      * to behave as if SCR.NS was 1.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       .writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
-      /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
+      /*
+       * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
        * reset values as IMPDEF. We choose to reset to 3 to comply with
        * both ARMv7 and ARMv8.
        */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
-    /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
+    /*
+     * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
      * At Secure EL1 it traps to EL3 or EL2.
      */
     if (arm_current_el(env) == 3) {
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     }
 }
 
-/* We don't know until after realize whether there's a GICv3
+/*
+ * We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
  * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
  * at runtime.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 }
 #endif
 
-/* Shared logic between LORID and the rest of the LOR* registers.
+/*
+ * Shared logic between LORID and the rest of the LOR* registers.
  * Secure state exclusion has already been dealt with.
  */
 static CPAccessResult access_lor_ns(CPUARMState *env,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 
     define_arm_cp_regs(cpu, cp_reginfo);
     if (!arm_feature(env, ARM_FEATURE_V8)) {
-        /* Must go early as it is full of wildcards that may be
+        /*
+         * Must go early as it is full of wildcards that may be
          * overridden by later definitions.
          */
         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
               .resetvalue = cpu->isar.id_pfr0 },
-            /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
+            /*
+             * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
              * the value of the GIC field until after we define these regs.
              */
             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 
         define_arm_cp_regs(cpu, el3_regs);
     }
-    /* The behaviour of NSACR is sufficiently various that we don't
+    /*
+     * The behaviour of NSACR is sufficiently various that we don't
      * try to describe it in a single reginfo:
      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
      *     reads as constant 0xc00 from NS EL1 and NS EL2
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa32_jazelle, cpu)) {
         define_arm_cp_regs(cpu, jazelle_regs);
     }
-    /* Slightly awkwardly, the OMAP and StrongARM cores need all of
+    /*
+     * Slightly awkwardly, the OMAP and StrongARM cores need all of
      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
      * be read-only (ie write causes UNDEF exception).
      */
     {
         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
-            /* Pre-v8 MIDR space.
+            /*
+             * Pre-v8 MIDR space.
              * Note that the MIDR isn't a simple constant register because
              * of the TI925 behaviour where writes to another register can
              * cause the MIDR value to change.
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
             arm_feature(env, ARM_FEATURE_STRONGARM)) {
             size_t i;
-            /* Register the blanket "writes ignored" value first to cover the
+            /*
+             * Register the blanket "writes ignored" value first to cover the
              * whole space. Then update the specific ID registers to allow write
              * access, so that they ignore writes rather than causing them to
              * UNDEF.
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .raw_writefn = raw_write,
         };
         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-            /* Normally we would always end the TB on an SCTLR write, but Linux
+            /*
+             * Normally we would always end the TB on an SCTLR write, but Linux
              * arch/arm/mach-pxa/sleep.S expects two instructions following
              * an MMU enable to execute from cache.  Imitate this behaviour.
              */
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                                        const ARMCPRegInfo *r, void *opaque)
 {
-    /* Define implementations of coprocessor registers.
+    /*
+     * Define implementations of coprocessor registers.
      * We store these in a hashtable because typically
      * there are less than 150 registers in a space which
      * is 16*16*16*8*8 = 262144 in size.
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
     default:
         g_assert_not_reached();
     }
-    /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
+    /*
+     * The AArch64 pseudocode CheckSystemAccess() specifies that op1
      * encodes a minimum access level for the register. We roll this
      * runtime check into our general permission check code, so check
      * here that the reginfo's specified permissions are strict enough
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
         assert((r->access & ~mask) == 0);
     }
 
-    /* Check that the register definition has enough info to handle
+    /*
+     * Check that the register definition has enough info to handle
      * reads and writes if they are permitted.
      */
     if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                         continue;
                     }
                     if (state == ARM_CP_STATE_AA32) {
-                        /* Under AArch32 CP registers can be common
+                        /*
+                         * Under AArch32 CP registers can be common
                          * (same for secure and non-secure world) or banked.
                          */
                         char *name;
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
                             g_assert_not_reached();
                         }
                     } else {
-                        /* AArch64 registers get mapped to non-secure instance
-                         * of AArch32 */
+                        /*
+                         * AArch64 registers get mapped to non-secure instance
+                         * of AArch32
+                         */
                         add_cpreg_to_hashtable(cpu, r, opaque, state,
                                                ARM_CP_SECSTATE_NS,
                                                crm, opc1, opc2, r->name);
@@ -XXX,XX +XXX,XX @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
 
 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
 {
-    /* Return true if it is not valid for us to switch to
+    /*
+     * Return true if it is not valid for us to switch to
      * this CPU mode (ie all the UNPREDICTABLE cases in
      * the ARM ARM CPSRWriteByInstr pseudocode).
      */
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
     case ARM_CPU_MODE_UND:
     case ARM_CPU_MODE_IRQ:
     case ARM_CPU_MODE_FIQ:
-        /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
+        /*
+         * Note that we don't implement the IMPDEF NSACR.RFR which in v7
          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
          */
-        /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
+        /*
+         * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
          * and CPS are treated as illegal mode changes.
          */
         if (write_type == CPSRWriteByInstr &&
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
         env->GE = (val >> 16) & 0xf;
     }
 
-    /* In a V7 implementation that includes the security extensions but does
+    /*
+     * In a V7 implementation that includes the security extensions but does
      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
      * bits respectively.
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
         changed_daif = (env->daif ^ val) & mask;
 
         if (changed_daif & CPSR_A) {
-            /* Check to see if we are allowed to change the masking of async
+            /*
+             * Check to see if we are allowed to change the masking of async
              * abort exceptions from a non-secure state.
              */
             if (!(env->cp15.scr_el3 & SCR_AW)) {
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
         }
 
         if (changed_daif & CPSR_F) {
-            /* Check to see if we are allowed to change the masking of FIQ
+            /*
+             * Check to see if we are allowed to change the masking of FIQ
              * exceptions from a non-secure state.
              */
             if (!(env->cp15.scr_el3 & SCR_FW)) {
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
                 mask &= ~CPSR_F;
             }
 
-            /* Check whether non-maskable FIQ (NMFI) support is enabled.
+            /*
+             * Check whether non-maskable FIQ (NMFI) support is enabled.
              * If this bit is set software is not allowed to mask
              * FIQs, but is allowed to set CPSR_F to 0.
              */
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
     if (write_type != CPSRWriteRaw &&
         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
         if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
-            /* Note that we can only get here in USR mode if this is a
+            /*
+             * Note that we can only get here in USR mode if this is a
              * gdb stub write; for this case we follow the architectural
              * behaviour for guest writes in USR mode of ignoring an attempt
              * to switch mode. (Those are caught by translate.c for writes
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
              */
             mask &= ~CPSR_M;
         } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
-            /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
+            /*
+             * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
              * v7, and has defined behaviour in v8:
              *  + leave CPSR.M untouched
              *  + allow changes to the other CPSR fields
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 }
 
-/* Physical Interrupt Target EL Lookup Table
+/*
+ * Physical Interrupt Target EL Lookup Table
  *
  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
  *
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
     } else {
-        /* Either EL2 is the highest EL (and so the EL2 register width
+        /*
+         * Either EL2 is the highest EL (and so the EL2 register width
          * is given by is64); or there is no EL2 or EL3, in which case
          * the value of 'rw' does not affect the table lookup anyway.
          */
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
     }
 
-    /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
+    /*
+     * Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
      * FIQ bank for r8-r14.
      */
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         /* High vectors. When enabled, base address cannot be remapped. */
         addr += 0xffff0000;
     } else {
-        /* ARM v7 architectures provide a vector base address register to remap
+        /*
+         * ARM v7 architectures provide a vector base address register to remap
          * the interrupt vector table.
          * This register is only followed in non-monitor mode, and is banked.
          * Note: only bits 31:5 are valid.
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
 
     if (cur_el < new_el) {
-        /* Entry vector offset depends on whether the implemented EL
+        /*
+         * Entry vector offset depends on whether the implemented EL
          * immediately lower than the target level is using AArch32 or AArch64
          */
         bool is_aa64;
@@ -XXX,XX +XXX,XX @@ static void handle_semihosting(CPUState *cs)
 }
 #endif
 
-/* Handle a CPU exception for A and R profile CPUs.
+/*
+ * Handle a CPU exception for A and R profile CPUs.
  * Do any appropriate logging, handle PSCI calls, and then hand off
  * to the AArch64-entry or AArch32-entry function depending on the
  * target exception level's register width.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
     }
 #endif
 
-    /* Hooks may change global state so BQL should be held, also the
+    /*
+     * Hooks may change global state so BQL should be held, also the
      * BQL needs to be held for any modification of
      * cs->interrupt_request.
      */
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
     };
 }
 
-/* Note that signed overflow is undefined in C.  The following routines are
-   careful to use unsigned types where modulo arithmetic is required.
-   Failure to do so _will_ break on newer gcc.  */
+/*
+ * Note that signed overflow is undefined in C.  The following routines are
+ * careful to use unsigned types where modulo arithmetic is required.
+ * Failure to do so _will_ break on newer gcc.
+ */
 
 /* Signed saturating arithmetic.  */
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
     return (a & mask) | (b & ~mask);
 }
 
-/* CRC helpers.
+/*
+ * CRC helpers.
  * The upper bytes of val (above the number specified by 'bytes') must have
  * been zeroed out by the caller.
  */
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
     return crc32c(acc, buf, bytes) ^ 0xffffffff;
 }
 
-/* Return the exception level to which FP-disabled exceptions should
+/*
+ * Return the exception level to which FP-disabled exceptions should
  * be taken, or 0 if FP is enabled.
  */
 int fp_exception_el(CPUARMState *env, int cur_el)
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
 #ifndef CONFIG_USER_ONLY
     uint64_t hcr_el2;
 
-    /* CPACR and the CPTR registers don't exist before v6, so FP is
+    /*
+     * CPACR and the CPTR registers don't exist before v6, so FP is
      * always accessible
      */
     if (!arm_feature(env, ARM_FEATURE_V6)) {
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
 
     hcr_el2 = arm_hcr_el2_eff(env);
 
-    /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
+    /*
+     * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
      * 0, 2 : trap EL0 and EL1/PL1 accesses
      * 1    : trap only EL0 accesses
      * 3    : trap no accesses
-- 
2.25.1

From: Fabiano Rosas <farosas@suse.de>

Fix the following:

ERROR: spaces required around that '|' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '+' (ctx:VxB)
ERROR: space prohibited between function name and open parenthesis '('

(the last two still have some occurrences in macros which I left
behind because it might impact readability)

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-3-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
     uint32_t regidx = (uintptr_t)key;
     const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 
-    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
+    if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
         /* The value array need not be initialized at this point */
         cpu->cpreg_array_len++;
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
 
     ri = g_hash_table_lookup(cpu->cp_regs, key);
 
-    if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
+    if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
         cpu->cpreg_array_len++;
     }
 }
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
       .resetfn = arm_cp_reset_ignore },
     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
-      .access = PL0_R|PL1_W,
+      .access = PL0_R | PL1_W,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
       .resetvalue = 0},
     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
-      .access = PL0_R|PL1_W,
+      .access = PL0_R | PL1_W,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
       .resetfn = arm_cp_reset_ignore },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
       .resetvalue = 0 },
     /* The cache ops themselves: these all NOP for QEMU */
     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
-      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
-      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
-      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
-      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
-      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
-      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+      .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
 };
 
 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             ARMCPRegInfo cbar = {
                 .name = "CBAR",
                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
-                .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
+                .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
                 .fieldoffset = offsetof(CPUARMState,
                                         cp15.c15_config_base_address)
             };
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
         return;
 
     if (old_mode == ARM_CPU_MODE_FIQ) {
-        memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
-        memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
+        memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
+        memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
     } else if (mode == ARM_CPU_MODE_FIQ) {
-        memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
-        memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
+        memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
+        memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
     }
 
     i = bank_number(old_mode);
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 16); \
     if (sum >= 0) \
         ge |= 3 << (n * 2); \
-    } while(0)
+    } while (0)
 
 #define SARITH8(a, b, n, op) do { \
     int32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 8); \
     if (sum >= 0) \
         ge |= 1 << n; \
-    } while(0)
+    } while (0)
 
 
 #define ADD16(a, b, n) SARITH16(a, b, n, +)
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 16); \
     if ((sum >> 16) == 1) \
         ge |= 3 << (n * 2); \
-    } while(0)
+    } while (0)
 
 #define ADD8(a, b, n) do { \
     uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 8); \
     if ((sum >> 8) == 1) \
         ge |= 1 << n; \
-    } while(0)
+    } while (0)
 
 #define SUB16(a, b, n) do { \
     uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 16); \
     if ((sum >> 16) == 0) \
         ge |= 3 << (n * 2); \
-    } while(0)
+    } while (0)
 
 #define SUB8(a, b, n) do { \
     uint32_t sum; \
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
     RESULT(sum, n, 8); \
     if ((sum >> 8) == 0) \
         ge |= 1 << n; \
-    } while(0)
+    } while (0)
 
 #define PFX u
 #define ARITH_GE
-- 
2.25.1

From: Fabiano Rosas <farosas@suse.de>

Fix this:
ERROR: braces {} are necessary for all arms of this statement

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-4-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 67 ++++++++++++++++++++++++++++-----------------
 1 file changed, 42 insertions(+), 25 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
         env->CF = (val >> 29) & 1;
         env->VF = (val << 3) & 0x80000000;
     }
-    if (mask & CPSR_Q)
+    if (mask & CPSR_Q) {
         env->QF = ((val & CPSR_Q) != 0);
-    if (mask & CPSR_T)
+    }
+    if (mask & CPSR_T) {
         env->thumb = ((val & CPSR_T) != 0);
+    }
     if (mask & CPSR_IT_0_1) {
         env->condexec_bits &= ~3;
         env->condexec_bits |= (val >> 25) & 3;
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
     int i;
 
     old_mode = env->uncached_cpsr & CPSR_M;
-    if (mode == old_mode)
+    if (mode == old_mode) {
         return;
+    }
 
     if (old_mode == ARM_CPU_MODE_FIQ) {
         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         new_mode = ARM_CPU_MODE_UND;
         addr = 0x04;
         mask = CPSR_I;
-        if (env->thumb)
+        if (env->thumb) {
             offset = 2;
-        else
+        } else {
             offset = 4;
+        }
         break;
     case EXCP_SWI:
         new_mode = ARM_CPU_MODE_SVC;
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_sat(uint16_t a, uint16_t b)
 
     res = a + b;
     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
-        if (a & 0x8000)
+        if (a & 0x8000) {
             res = 0x8000;
-        else
+        } else {
             res = 0x7fff;
+        }
     }
     return res;
 }
@@ -XXX,XX +XXX,XX @@ static inline uint8_t add8_sat(uint8_t a, uint8_t b)
 
     res = a + b;
     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
-        if (a & 0x80)
+        if (a & 0x80) {
             res = 0x80;
-        else
+        } else {
             res = 0x7f;
+        }
     }
     return res;
 }
@@ -XXX,XX +XXX,XX @@ static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
 
     res = a - b;
     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
-        if (a & 0x8000)
+        if (a & 0x8000) {
             res = 0x8000;
-        else
+        } else {
             res = 0x7fff;
+        }
     }
     return res;
 }
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
 
     res = a - b;
     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
-        if (a & 0x80)
+        if (a & 0x80) {
             res = 0x80;
-        else
+        } else {
             res = 0x7f;
+        }
     }
     return res;
 }
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_usat(uint16_t a, uint16_t b)
 {
     uint16_t res;
     res = a + b;
-    if (res < a)
+    if (res < a) {
         res = 0xffff;
+    }
     return res;
 }
 
 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
 {
-    if (a > b)
+    if (a > b) {
         return a - b;
-    else
+    } else {
         return 0;
+    }
 }
 
 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
 {
     uint8_t res;
     res = a + b;
-    if (res < a)
+    if (res < a) {
         res = 0xff;
+    }
     return res;
 }
 
 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
 {
-    if (a > b)
+    if (a > b) {
         return a - b;
-    else
+    } else {
         return 0;
+    }
 }
 
 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
 
 static inline uint8_t do_usad(uint8_t a, uint8_t b)
 {
-    if (a > b)
+    if (a > b) {
         return a - b;
-    else
+    } else {
         return b - a;
+    }
 }
 
 /* Unsigned sum of absolute byte differences.  */
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
     uint32_t mask;
 
     mask = 0;
-    if (flags & 1)
+    if (flags & 1) {
         mask |= 0xff;
-    if (flags & 2)
+    }
+    if (flags & 2) {
         mask |= 0xff00;
-    if (flags & 4)
+    }
+    if (flags & 4) {
         mask |= 0xff0000;
-    if (flags & 8)
+    }
+    if (flags & 8) {
         mask |= 0xff000000;
+    }
     return (a & mask) | (b & ~mask);
 }
 
-- 
2.25.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-5-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/units.h"
-#include "target/arm/idau.h"
-#include "trace.h"
 #include "cpu.h"
 #include "internals.h"
-#include "exec/gdbstub.h"
 #include "exec/helper-proto.h"
-#include "qemu/host-utils.h"
 #include "qemu/main-loop.h"
 #include "qemu/bitops.h"
-#include "qemu/crc32c.h"
-#include "qemu/qemu-print.h"
 #include "qemu/log.h"
 #include "exec/exec-all.h"
-#include <zlib.h> /* For crc32 */
-#include "semihosting/semihost.h"
-#include "sysemu/cpus.h"
-#include "sysemu/kvm.h"
-#include "qemu/range.h"
-#include "qapi/qapi-commands-machine-target.h"
-#include "qapi/error.h"
-#include "qemu/guest-random.h"
 #ifdef CONFIG_TCG
-#include "arm_ldst.h"
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
-- 
2.25.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20221213190537.511-6-farosas@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/units.h"
 #include "qemu/log.h"
 #include "trace.h"
 #include "cpu.h"
 #include "internals.h"
 #include "exec/helper-proto.h"
-#include "qemu/host-utils.h"
 #include "qemu/main-loop.h"
 #include "qemu/timer.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@
 #include "exec/exec-all.h"
 #include <zlib.h> /* For crc32 */
 #include "hw/irq.h"
-#include "semihosting/semihost.h"
-#include "sysemu/cpus.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/kvm.h"
-#include "qemu/range.h"
 #include "qapi/qapi-commands-machine-target.h"
 #include "qapi/error.h"
 #include "qemu/guest-random.h"
 #ifdef CONFIG_TCG
-#include "arm_ldst.h"
-#include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
 #include "cpregs.h"
-- 
2.25.1

From: Claudio Fontana <cfontana@suse.de>

Remove some unused headers.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20221213190537.511-7-farosas@suse.de
[added back some includes that are still needed at this point]
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c   | 1 -
 target/arm/cpu64.c | 6 ------
 2 files changed, 7 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "target/arm/idau.h"
 #include "qemu/module.h"
 #include "qapi/error.h"
-#include "qapi/visitor.h"
 #include "cpu.h"
 #ifdef CONFIG_TCG
 #include "hw/core/tcg-cpu-ops.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "cpu.h"
-#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
-#endif /* CONFIG_TCG */
 #include "qemu/module.h"
-#if !defined(CONFIG_USER_ONLY)
-#include "hw/loader.h"
-#endif
 #include "sysemu/kvm.h"
 #include "sysemu/hvf.h"
 #include "kvm_arm.h"
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The pointed MouseTransformInfo structure is accessed read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221220142520.24094-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/input/tsc2xxx.h | 4 ++--
 hw/input/tsc2005.c         | 2 +-
 hw/input/tsc210x.c         | 3 +--
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/input/tsc2xxx.h
+++ b/include/hw/input/tsc2xxx.h
@@ -XXX,XX +XXX,XX @@ uWireSlave *tsc2102_init(qemu_irq pint);
 uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
 I2SCodec *tsc210x_codec(uWireSlave *chip);
 uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
-void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info);
 void tsc210x_key_event(uWireSlave *chip, int key, int down);
 
 /* tsc2005.c */
 void *tsc2005_init(qemu_irq pintdav);
 uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info);
 
 #endif
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/input/tsc2005.c
+++ b/hw/input/tsc2005.c
@@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav)
  * from the touchscreen.  Assuming 12-bit precision was used during
  * tslib calibration.
  */
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info)
 {
     TSC2005State *s = (TSC2005State *) opaque;
 
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/input/tsc210x.c
+++ b/hw/input/tsc210x.c
@@ -XXX,XX +XXX,XX @@ I2SCodec *tsc210x_codec(uWireSlave *chip)
  * from the touchscreen.  Assuming 12-bit precision was used during
  * tslib calibration.
  */
-void tsc210x_set_transform(uWireSlave *chip,
-                MouseTransformInfo *info)
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info)
 {
     TSC210xState *s = (TSC210xState *) chip->opaque;
 #if 0
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221220142520.24094-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/nseries.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s)
 }
 
 /* Touchscreen and keypad controller */
-static MouseTransformInfo n800_pointercal = {
+static const MouseTransformInfo n800_pointercal = {
     .x = 800,
     .y = 480,
     .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
 };
 
-static MouseTransformInfo n810_pointercal = {
+static const MouseTransformInfo n810_pointercal = {
     .x = 800,
     .y = 480,
     .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
@@ -XXX,XX +XXX,XX @@ static void n810_key_event(void *opaque, int keycode)
 
 #define M	0
 
-static int n810_keys[0x80] = {
+static const int n810_keys[0x80] = {
     [0x01] = 16,	/* Q */
     [0x02] = 37,	/* K */
     [0x03] = 24,	/* O */
@@ -XXX,XX +XXX,XX @@ static void n8x0_usb_setup(struct n800_s *s)
 /* Setup done before the main bootloader starts by some early setup code
  * - used when we want to run the main bootloader in emulation.  This
  * isn't documented.  */
-static uint32_t n800_pinout[104] = {
+static const uint32_t n800_pinout[104] = {
     0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
     0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
     0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
@@ -XXX,XX +XXX,XX @@ static void n8x0_boot_init(void *opaque)
 #define OMAP_TAG_CBUS		0x4e03
 #define OMAP_TAG_EM_ASIC_BB5	0x4e04
 
-static struct omap_gpiosw_info_s {
+static const struct omap_gpiosw_info_s {
     const char *name;
     int line;
     int type;
@@ -XXX,XX +XXX,XX @@ static struct omap_gpiosw_info_s {
     { NULL }
 };
 
-static struct omap_partition_info_s {
+static const struct omap_partition_info_s {
     uint32_t offset;
     uint32_t size;
     int mask;
@@ -XXX,XX +XXX,XX @@ static struct omap_partition_info_s {
     { 0, 0, 0, NULL }
 };
 
-static uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
+static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
 
 static int n8x0_atag_setup(void *p, int model)
 {
     uint8_t *b;
     uint16_t *w;
     uint32_t *l;
-    struct omap_gpiosw_info_s *gpiosw;
-    struct omap_partition_info_s *partition;
+    const struct omap_gpiosw_info_s *gpiosw;
+    const struct omap_partition_info_s *partition;
     const char *tag;
 
     w = p;
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Silent when compiling with -Wextra:

../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers]
      { NULL }
             ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221220142520.24094-4-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/nseries.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
         "headphone", N8X0_HEADPHONE_GPIO,
         OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
     },
-    { NULL }
+    { /* end of list */ }
 }, n810_gpiosw_info[] = {
     {
         "gps_reset", N810_GPS_RESET_GPIO,
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
         "slide", N810_SLIDE_GPIO,
         OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
     },
-    { NULL }
+    { /* end of list */ }
 };
 
 static const struct omap_partition_info_s {
@@ -XXX,XX +XXX,XX @@ static const struct omap_partition_info_s {
     { 0x00080000, 0x00200000, 0x0, "kernel" },
     { 0x00280000, 0x00200000, 0x3, "initfs" },
     { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
-
-    { 0, 0, 0, NULL }
+    { /* end of list */ }
 }, n810_part_info[] = {
     { 0x00000000, 0x00020000, 0x3, "bootloader" },
     { 0x00020000, 0x00060000, 0x0, "config" },
     { 0x00080000, 0x00220000, 0x0, "kernel" },
     { 0x002a0000, 0x00400000, 0x0, "initfs" },
     { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
-
-    { 0, 0, 0, NULL }
+    { /* end of list */ }
 };
 
 static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
-- 
2.25.1

From: Zhuojia Shen <chaosdefinition@hotmail.com>

In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed.  This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.

Specifically, the following new ID registers/fields are exposed to
userspace:

ID_AA64PFR1_EL1.BT:       bits 3-0
ID_AA64PFR1_EL1.MTE:      bits 11-8
ID_AA64PFR1_EL1.SME:      bits 27-24

ID_AA64ZFR0_EL1.SVEver:   bits 3-0
ID_AA64ZFR0_EL1.AES:      bits 7-4
ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
ID_AA64ZFR0_EL1.BF16:     bits 23-20
ID_AA64ZFR0_EL1.SHA3:     bits 35-32
ID_AA64ZFR0_EL1.SM4:      bits 43-40
ID_AA64ZFR0_EL1.I8MM:     bits 47-44
ID_AA64ZFR0_EL1.F32MM:    bits 55-52
ID_AA64ZFR0_EL1.F64MM:    bits 59-56

ID_AA64SMFR0_EL1.F32F32:  bit 32
ID_AA64SMFR0_EL1.B16F32:  bit 34
ID_AA64SMFR0_EL1.F16F32:  bit 35
ID_AA64SMFR0_EL1.I8I32:   bits 39-36
ID_AA64SMFR0_EL1.F64F64:  bit 48
ID_AA64SMFR0_EL1.I16I64:  bits 55-52
ID_AA64SMFR0_EL1.FA64:    bit 63

ID_AA64MMFR0_EL1.ECV:     bits 63-60

ID_AA64MMFR1_EL1.AFP:     bits 47-44

ID_AA64MMFR2_EL1.AT:      bits 35-32

ID_AA64ISAR0_EL1.RNDR:    bits 63-60

ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
ID_AA64ISAR1_EL1.BF16:    bits 47-44
ID_AA64ISAR1_EL1.DGH:     bits 51-48
ID_AA64ISAR1_EL1.I8MM:    bits 55-52

ID_AA64ISAR2_EL1.WFxT:    bits 3-0
ID_AA64ISAR2_EL1.RPRES:   bits 7-4
ID_AA64ISAR2_EL1.GPA3:    bits 11-8
ID_AA64ISAR2_EL1.APA3:    bits 15-12

The code is also refactored to use symbolic names for ID register fields
for better readability and maintainability.

The test case in tests/tcg/aarch64/sysregs.c is also updated to match
the intended behavior.

Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c               | 96 +++++++++++++++++++++++++------
 tests/tcg/aarch64/sysregs.c       | 24 ++++++--
 tests/tcg/aarch64/Makefile.target |  7 ++-
 3 files changed, 103 insertions(+), 24 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 #ifdef CONFIG_USER_ONLY
         static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
-              .exported_bits = 0x000f000f00ff0000,
-              .fixed_bits    = 0x0000000000000011 },
+              .exported_bits = R_ID_AA64PFR0_FP_MASK |
+                               R_ID_AA64PFR0_ADVSIMD_MASK |
+                               R_ID_AA64PFR0_SVE_MASK |
+                               R_ID_AA64PFR0_DIT_MASK,
+              .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
+                            (0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
             { .name = "ID_AA64PFR1_EL1",
-              .exported_bits = 0x00000000000000f0 },
+              .exported_bits = R_ID_AA64PFR1_BT_MASK |
+                               R_ID_AA64PFR1_SSBS_MASK |
+                               R_ID_AA64PFR1_MTE_MASK |
+                               R_ID_AA64PFR1_SME_MASK },
             { .name = "ID_AA64PFR*_EL1_RESERVED",
-              .is_glob = true                     },
-            { .name = "ID_AA64ZFR0_EL1"           },
+              .is_glob = true },
+            { .name = "ID_AA64ZFR0_EL1",
+              .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
+                               R_ID_AA64ZFR0_AES_MASK |
+                               R_ID_AA64ZFR0_BITPERM_MASK |
+                               R_ID_AA64ZFR0_BFLOAT16_MASK |
+                               R_ID_AA64ZFR0_SHA3_MASK |
+                               R_ID_AA64ZFR0_SM4_MASK |
+                               R_ID_AA64ZFR0_I8MM_MASK |
+                               R_ID_AA64ZFR0_F32MM_MASK |
+                               R_ID_AA64ZFR0_F64MM_MASK },
+            { .name = "ID_AA64SMFR0_EL1",
+              .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
+                               R_ID_AA64SMFR0_B16F32_MASK |
+                               R_ID_AA64SMFR0_F16F32_MASK |
+                               R_ID_AA64SMFR0_I8I32_MASK |
+                               R_ID_AA64SMFR0_F64F64_MASK |
+                               R_ID_AA64SMFR0_I16I64_MASK |
+                               R_ID_AA64SMFR0_FA64_MASK },
             { .name = "ID_AA64MMFR0_EL1",
-              .fixed_bits    = 0x00000000ff000000 },
-            { .name = "ID_AA64MMFR1_EL1"          },
+              .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
+              .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
+                            (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
+            { .name = "ID_AA64MMFR1_EL1",
+              .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
+            { .name = "ID_AA64MMFR2_EL1",
+              .exported_bits = R_ID_AA64MMFR2_AT_MASK },
             { .name = "ID_AA64MMFR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64DFR0_EL1",
-              .fixed_bits    = 0x0000000000000006 },
-            { .name = "ID_AA64DFR1_EL1"           },
+              .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
+            { .name = "ID_AA64DFR1_EL1" },
             { .name = "ID_AA64DFR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64AFR*",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64ISAR0_EL1",
-              .exported_bits = 0x00fffffff0fffff0 },
+              .exported_bits = R_ID_AA64ISAR0_AES_MASK |
+                               R_ID_AA64ISAR0_SHA1_MASK |
+                               R_ID_AA64ISAR0_SHA2_MASK |
+                               R_ID_AA64ISAR0_CRC32_MASK |
+                               R_ID_AA64ISAR0_ATOMIC_MASK |
+                               R_ID_AA64ISAR0_RDM_MASK |
+                               R_ID_AA64ISAR0_SHA3_MASK |
+                               R_ID_AA64ISAR0_SM3_MASK |
+                               R_ID_AA64ISAR0_SM4_MASK |
+                               R_ID_AA64ISAR0_DP_MASK |
+                               R_ID_AA64ISAR0_FHM_MASK |
+                               R_ID_AA64ISAR0_TS_MASK |
+                               R_ID_AA64ISAR0_RNDR_MASK },
             { .name = "ID_AA64ISAR1_EL1",
-              .exported_bits = 0x000000f0ffffffff },
+              .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
+                               R_ID_AA64ISAR1_APA_MASK |
+                               R_ID_AA64ISAR1_API_MASK |
+                               R_ID_AA64ISAR1_JSCVT_MASK |
+                               R_ID_AA64ISAR1_FCMA_MASK |
+                               R_ID_AA64ISAR1_LRCPC_MASK |
+                               R_ID_AA64ISAR1_GPA_MASK |
+                               R_ID_AA64ISAR1_GPI_MASK |
+                               R_ID_AA64ISAR1_FRINTTS_MASK |
+                               R_ID_AA64ISAR1_SB_MASK |
+                               R_ID_AA64ISAR1_BF16_MASK |
+                               R_ID_AA64ISAR1_DGH_MASK |
+                               R_ID_AA64ISAR1_I8MM_MASK },
+            { .name = "ID_AA64ISAR2_EL1",
+              .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
+                               R_ID_AA64ISAR2_RPRES_MASK |
+                               R_ID_AA64ISAR2_GPA3_MASK |
+                               R_ID_AA64ISAR2_APA3_MASK },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
         };
         modify_arm_cp_regs(v8_idregs, v8_user_idregs);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 #ifdef CONFIG_USER_ONLY
         static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
-              .exported_bits = 0x00000000ffffffff },
-            { .name = "REVIDR_EL1"                },
+              .exported_bits = R_MIDR_EL1_REVISION_MASK |
+                               R_MIDR_EL1_PARTNUM_MASK |
+                               R_MIDR_EL1_ARCHITECTURE_MASK |
+                               R_MIDR_EL1_VARIANT_MASK |
+                               R_MIDR_EL1_IMPLEMENTER_MASK },
+            { .name = "REVIDR_EL1" },
         };
         modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
 #endif
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/sysregs.c
+++ b/tests/tcg/aarch64/sysregs.c
@@ -XXX,XX +XXX,XX @@
 #define HWCAP_CPUID (1 << 11)
 #endif
 
+/*
+ * Older assemblers don't recognize newer system register names,
+ * but we can still access them by the Sn_n_Cn_Cn_n syntax.
+ */
+#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
+#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+
 int failed_bit_count;
 
 /* Read and print system register `id' value */
@@ -XXX,XX +XXX,XX @@ int main(void)
      * minimum valid fields - for the purposes of this check allowed
      * to have non-zero values.
      */
-    get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
-    get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
+    get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
+    get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
+    get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
     /* TGran4 & TGran64 as pegged to -1 */
-    get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
-    get_cpu_reg_check_zero(id_aa64mmfr1_el1);
+    get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
+    get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
+    get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
     /* EL1/EL0 reported as AA64 only */
     get_cpu_reg_check_mask(id_aa64pfr0_el1,  _m(000f,000f,00ff,0011));
-    get_cpu_reg_check_mask(id_aa64pfr1_el1,  _m(0000,0000,0000,00f0));
+    get_cpu_reg_check_mask(id_aa64pfr1_el1,  _m(0000,0000,0f00,0fff));
     /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
     get_cpu_reg_check_mask(id_aa64dfr0_el1,  _m(0000,0000,0000,0006));
     get_cpu_reg_check_zero(id_aa64dfr1_el1);
-    get_cpu_reg_check_zero(id_aa64zfr0_el1);
+    get_cpu_reg_check_mask(id_aa64zfr0_el1,  _m(0ff0,ff0f,00ff,00ff));
+#ifdef HAS_ARMV9_SME
+    get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
+#endif
 
     get_cpu_reg_check_zero(id_aa64afr0_el1);
     get_cpu_reg_check_zero(id_aa64afr1_el1);
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
 	    $(call cc-option,-march=armv8.1-a+sve2,         CROSS_CC_HAS_SVE2); \
 	    $(call cc-option,-march=armv8.3-a,              CROSS_CC_HAS_ARMV8_3); \
 	    $(call cc-option,-mbranch-protection=standard,  CROSS_CC_HAS_ARMV8_BTI); \
-	    $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
+	    $(call cc-option,-march=armv8.5-a+memtag,       CROSS_CC_HAS_ARMV8_MTE); \
+	    $(call cc-option,-march=armv9-a+sme,            CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
 -include config-cc.mak
 
 # Pauth Tests
@@ -XXX,XX +XXX,XX @@ endif
 ifneq ($(CROSS_CC_HAS_SVE),)
 # System Registers Tests
 AARCH64_TESTS += sysregs
+ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
+sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
+else
 sysregs: CFLAGS+=-march=armv8.1-a+sve
+endif
 
 # SVE ioctl test
 AARCH64_TESTS += sve-ioctls
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

This function is not used anywhere outside this file,
so we can make the function "static void".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221216214924.4711-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 3 ---
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 void smmu_inv_notifiers_all(SMMUState *s);
 
-/* Unmap the range of all the notifiers registered to @mr */
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
-
 #endif /* HW_ARM_SMMU_COMMON_H */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
 }
 
 /* Unmap all notifiers attached to @mr */
-inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
 {
     IOMMUNotifier *n;
 
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
and building with -Wall we get:

hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline]
  hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage
    void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
    ^
    static

None of our code base require / use inlined functions with external
linkage. Some places use internal inlining in the hot path. These
two functions are certainly not in any hot path and don't justify
any inlining, so these are likely oversights rather than intentional.

Reported-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221216214924.4711-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-common.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
     g_hash_table_insert(bs->iotlb, key, new);
 }
 
-inline void smmu_iotlb_inv_all(SMMUState *s)
+void smmu_iotlb_inv_all(SMMUState *s)
 {
     trace_smmu_iotlb_inv_all();
     g_hash_table_remove_all(s->iotlb);
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
            ((entry->iova & ~info->mask) == info->iova);
 }
 
-inline void
-smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
-                    uint8_t tg, uint64_t num_pages, uint8_t ttl)
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
+                         uint8_t tg, uint64_t num_pages, uint8_t ttl)
 {
     /* if tg is not set we use 4KB range invalidation */
     uint8_t granule = tg ? tg * 2 + 10 : 12;
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
                                 &info);
 }
 
-inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
 {
     trace_smmu_iotlb_inv_asid(asid);
     g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
@@ -XXX,XX +XXX,XX @@ error:
  *
  * return 0 on success
  */
-inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
-                    SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
+int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
+             SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
 {
     if (!cfg->aa64) {
         /*
-- 
2.25.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

So far the GPT timers were unable to raise IRQs to the processor.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  5 +++++
 hw/arm/fsl-imx7.c         | 10 ++++++++++
 2 files changed, 15 insertions(+)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

CCM derived clocks will have to be added later.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 40 insertions(+), 9 deletions(-)

diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx7_ccm.c
+++ b/hw/misc/imx7_ccm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "migration/vmstate.h"
 
+#include "trace.h"
+
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
+
 static void imx7_analog_reset(DeviceState *dev)
 {
     IMX7AnalogState *s = IMX7_ANALOG(dev);
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx7_ccm = {
 static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
 {
     /*
-     * This function is "consumed" by GPT emulation code, however on
-     * i.MX7 each GPT block can have their own clock root. This means
-     * that this functions needs somehow to know requester's identity
-     * and the way to pass it: be it via additional IMXClk constants
-     * or by adding another argument to this method needs to be
-     * figured out
+     * This function is "consumed" by GPT emulation code. Some clocks
+     * have fixed frequencies and we can provide requested frequency
+     * easily. However for CCM provided clocks (like IPG) each GPT
+     * timer can have its own clock root.
+     * This means we need additionnal information when calling this
+     * function to know the requester's identity.
      */
-    qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
-                  TYPE_IMX7_CCM, __func__);
-    return 0;
+    uint32_t freq = 0;
+
+    switch (clock) {
+    case CLK_NONE:
+        break;
+    case CLK_32k:
+        freq = CKIL_FREQ;
+        break;
+    case CLK_HIGH:
+        freq = CKIH_FREQ;
+        break;
+    case CLK_IPG:
+    case CLK_IPG_HIGH:
+        /*
+         * For now we don't have a way to figure out the device this
+         * function is called for. Until then the IPG derived clocks
+         * are left unimplemented.
+         */
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
+                      TYPE_IMX7_CCM, __func__, clock);
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
+                      TYPE_IMX7_CCM, __func__, clock);
+        break;
+    }
+
+    trace_ccm_clock_freq(clock, freq);
+
+    return freq;
 }
 
 static void imx7_ccm_class_init(ObjectClass *klass, void *data)
-- 
2.25.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/imx_gpt.h |  1 +
 hw/arm/fsl-imx6ul.c        |  2 +-
 hw/misc/imx6ul_ccm.c       |  6 ------
 hw/timer/imx_gpt.c         | 25 +++++++++++++++++++++++++
 4 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/imx_gpt.h
+++ b/include/hw/timer/imx_gpt.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_IMX25_GPT "imx25.gpt"
 #define TYPE_IMX31_GPT "imx31.gpt"
 #define TYPE_IMX6_GPT "imx6.gpt"
+#define TYPE_IMX6UL_GPT "imx6ul.gpt"
 #define TYPE_IMX7_GPT "imx7.gpt"
 
 #define TYPE_IMX_GPT TYPE_IMX25_GPT
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
-        object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
+        object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
     }
 
     /*
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx6ul_ccm.c
+++ b/hw/misc/imx6ul_ccm.c
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
     case CLK_32k:
         freq = CKIL_FREQ;
         break;
-    case CLK_HIGH:
-        freq = CKIH_FREQ;
-        break;
-    case CLK_HIGH_DIV:
-        freq = CKIH_FREQ / 8;
-        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
                       TYPE_IMX6UL_CCM, __func__, clock);
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx6_gpt_clocks[] = {
     CLK_HIGH,      /* 111 reference clock */
 };
 
+static const IMXClk imx6ul_gpt_clocks[] = {
+    CLK_NONE,      /* 000 No clock source */
+    CLK_IPG,       /* 001 ipg_clk, 532MHz*/
+    CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
+    CLK_EXT,       /* 011 External clock */
+    CLK_32k,       /* 100 ipg_clk_32k */
+    CLK_NONE,      /* 101 not defined */
+    CLK_NONE,      /* 110 not defined */
+    CLK_NONE,      /* 111 not defined */
+};
+
 static const IMXClk imx7_gpt_clocks[] = {
     CLK_NONE,      /* 000 No clock source */
     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
@@ -XXX,XX +XXX,XX @@ static void imx6_gpt_init(Object *obj)
     s->clocks = imx6_gpt_clocks;
 }
 
+static void imx6ul_gpt_init(Object *obj)
+{
+    IMXGPTState *s = IMX_GPT(obj);
+
+    s->clocks = imx6ul_gpt_clocks;
+}
+
 static void imx7_gpt_init(Object *obj)
 {
     IMXGPTState *s = IMX_GPT(obj);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx6_gpt_info = {
     .instance_init = imx6_gpt_init,
 };
 
+static const TypeInfo imx6ul_gpt_info = {
+    .name = TYPE_IMX6UL_GPT,
+    .parent = TYPE_IMX25_GPT,
+    .instance_init = imx6ul_gpt_init,
+};
+
 static const TypeInfo imx7_gpt_info = {
     .name = TYPE_IMX7_GPT,
     .parent = TYPE_IMX25_GPT,
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_register_types(void)
     type_register_static(&imx25_gpt_info);
     type_register_static(&imx31_gpt_info);
     type_register_static(&imx6_gpt_info);
+    type_register_static(&imx6ul_gpt_info);
     type_register_static(&imx7_gpt_info);
 }
 
-- 
2.25.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

IRQs were not associated to the various GPIO devices inside i.MX7D.
This patch brings the i.MX7D on par with i.MX6.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 20221226101418.415170-1-jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 15 +++++++++++++++
 hw/arm/fsl-imx7.c         | 31 ++++++++++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
     FSL_IMX7_GPT3_IRQ     = 53,
     FSL_IMX7_GPT4_IRQ     = 52,
 
+    FSL_IMX7_GPIO1_LOW_IRQ  = 64,
+    FSL_IMX7_GPIO1_HIGH_IRQ = 65,
+    FSL_IMX7_GPIO2_LOW_IRQ  = 66,
+    FSL_IMX7_GPIO2_HIGH_IRQ = 67,
+    FSL_IMX7_GPIO3_LOW_IRQ  = 68,
+    FSL_IMX7_GPIO3_HIGH_IRQ = 69,
+    FSL_IMX7_GPIO4_LOW_IRQ  = 70,
+    FSL_IMX7_GPIO4_HIGH_IRQ = 71,
+    FSL_IMX7_GPIO5_LOW_IRQ  = 72,
+    FSL_IMX7_GPIO5_HIGH_IRQ = 73,
+    FSL_IMX7_GPIO6_LOW_IRQ  = 74,
+    FSL_IMX7_GPIO6_HIGH_IRQ = 75,
+    FSL_IMX7_GPIO7_LOW_IRQ  = 76,
+    FSL_IMX7_GPIO7_HIGH_IRQ = 77,
+
     FSL_IMX7_WDOG1_IRQ    = 78,
     FSL_IMX7_WDOG2_IRQ    = 79,
     FSL_IMX7_WDOG3_IRQ    = 10,
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
             FSL_IMX7_GPIO7_ADDR,
         };
 
+        static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
+            FSL_IMX7_GPIO1_LOW_IRQ,
+            FSL_IMX7_GPIO2_LOW_IRQ,
+            FSL_IMX7_GPIO3_LOW_IRQ,
+            FSL_IMX7_GPIO4_LOW_IRQ,
+            FSL_IMX7_GPIO5_LOW_IRQ,
+            FSL_IMX7_GPIO6_LOW_IRQ,
+            FSL_IMX7_GPIO7_LOW_IRQ,
+        };
+
+        static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
+            FSL_IMX7_GPIO1_HIGH_IRQ,
+            FSL_IMX7_GPIO2_HIGH_IRQ,
+            FSL_IMX7_GPIO3_HIGH_IRQ,
+            FSL_IMX7_GPIO4_HIGH_IRQ,
+            FSL_IMX7_GPIO5_HIGH_IRQ,
+            FSL_IMX7_GPIO6_HIGH_IRQ,
+            FSL_IMX7_GPIO7_HIGH_IRQ,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
-        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+                        FSL_IMX7_GPIOn_ADDR[i]);
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                            FSL_IMX7_GPIOn_LOW_IRQ[i]));
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                            FSL_IMX7_GPIOn_HIGH_IRQ[i]));
     }
 
     /*
-- 
2.25.1

From: Stephen Longfield <slongfield@google.com>

Size is used at lines 1088/1188 for the loop, which reads the last 4
bytes from the crc_ptr so it does need to get increased, however it
shouldn't be increased before the buffer is passed to CRC computation,
or the crc32 function will access uninitialized memory.

This was pointed out to me by clg@kaod.org during the code review of
a similar patch to hw/net/ftgmac100.c

Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
Signed-off-by: Stephen Longfield <slongfield@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20221221183202.3788132-1-slongfield@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/imx_fec.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
         return 0;
     }
 
-    /* 4 bytes for the CRC.  */
-    size += 4;
     crc = cpu_to_be32(crc32(~0, buf, size));
+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
+    size += 4;
     crc_ptr = (uint8_t *) &crc;
 
     /* Huge frames are truncated.  */
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
         return 0;
     }
 
-    /* 4 bytes for the CRC.  */
-    size += 4;
     crc = cpu_to_be32(crc32(~0, buf, size));
+    /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
+    size += 4;
     crc_ptr = (uint8_t *) &crc;
 
     if (shift16) {
-- 
2.25.1

The following changes since commit bf4460a8d9a86f6cfe05d7a7f470c48e3a93d8b2:

Merge tag 'pull-tcg-20230123' of https://gitlab.com/rth7680/qemu into staging (2023-02-03 09:30:45 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230203

for you to fetch changes up to bb18151d8bd9bedc497ee9d4e8d81b39a4e5bbf6:

target/arm: Enable FEAT_FGT on '-cpu max' (2023-02-03 12:59:24 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix physical address resolution for Stage2
 * pl011: refactoring, implement reset method
 * Support GICv3 with hvf acceleration
 * sbsa-ref: remove cortex-a76 from list of supported cpus
 * Correct syndrome for ATS12NSO* traps at Secure EL1
 * Fix priority of HSTR_EL2 traps vs UNDEFs
 * Implement FEAT_FGT for '-cpu max'

----------------------------------------------------------------
Alexander Graf (3):
      hvf: arm: Add support for GICv3
      hw/arm/virt: Consolidate GIC finalize logic
      hw/arm/virt: Make accels in GIC finalize logic explicit

Evgeny Iakovlev (4):
      hw/char/pl011: refactor FIFO depth handling code
      hw/char/pl011: add post_load hook for backwards-compatibility
      hw/char/pl011: implement a reset method
      hw/char/pl011: better handling of FIFO flags on LCR reset

Marcin Juszkiewicz (1):
      sbsa-ref: remove cortex-a76 from list of supported cpus

Peter Maydell (23):
      target/arm: Name AT_S1E1RP and AT_S1E1WP cpregs correctly
      target/arm: Correct syndrome for ATS12NSO* at Secure EL1
      target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3}
      target/arm: Move do_coproc_insn() syndrome calculation earlier
      target/arm: All UNDEF-at-EL0 traps take priority over HSTR_EL2 traps
      target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1
      target/arm: Disable HSTR_EL2 traps if EL2 is not enabled
      target/arm: Define the FEAT_FGT registers
      target/arm: Implement FGT trapping infrastructure
      target/arm: Mark up sysregs for HFGRTR bits 0..11
      target/arm: Mark up sysregs for HFGRTR bits 12..23
      target/arm: Mark up sysregs for HFGRTR bits 24..35
      target/arm: Mark up sysregs for HFGRTR bits 36..63
      target/arm: Mark up sysregs for HDFGRTR bits 0..11
      target/arm: Mark up sysregs for HDFGRTR bits 12..63
      target/arm: Mark up sysregs for HFGITR bits 0..11
      target/arm: Mark up sysregs for HFGITR bits 12..17
      target/arm: Mark up sysregs for HFGITR bits 18..47
      target/arm: Mark up sysregs for HFGITR bits 48..63
      target/arm: Implement the HFGITR_EL2.ERET trap
      target/arm: Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 traps
      target/arm: Implement MDCR_EL2.TDCC and MDCR_EL3.TDCC traps
      target/arm: Enable FEAT_FGT on '-cpu max'

Richard Henderson (2):
      hw/arm: Use TYPE_ARM_SMMUV3
      target/arm: Fix physical address resolution for Stage2

From: Richard Henderson <richard.henderson@linaro.org>

Use the macro instead of two explicit string literals.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230124232059.4017615-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 3 ++-
 hw/arm/virt.c     | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "kvm_arm.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/smmuv3.h"
 #include "hw/block/flash.h"
 #include "hw/boards.h"
 #include "hw/ide/internal.h"
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
     DeviceState *dev;
     int i;
 
-    dev = qdev_new("arm-smmuv3");
+    dev = qdev_new(TYPE_ARM_SMMUV3);
 
     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
                              &error_abort);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
         return;
     }
 
-    dev = qdev_new("arm-smmuv3");
+    dev = qdev_new(TYPE_ARM_SMMUV3);
 
     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
                              &error_abort);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Conversion to probe_access_full missed applying the page offset.

Cc: qemu-stable@nongnu.org
Reported-by: Sid Manning <sidneym@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230126233134.103193-1-richard.henderson@linaro.org
Fixes: f3639a64f602 ("target/arm: Use softmmu tlbs for page table walking")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
         if (unlikely(flags & TLB_INVALID_MASK)) {
             goto fail;
         }
-        ptw->out_phys = full->phys_addr;
+        ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK);
         ptw->out_rw = full->prot & PAGE_WRITE;
         pte_attrs = full->pte_attrs;
         pte_secure = full->attrs.secure;
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

PL011 can be in either of 2 modes depending guest config: FIFO and
single register. The last mode could be viewed as a 1-element-deep FIFO.

Current code open-codes a bunch of depth-dependent logic. Refactor FIFO
depth handling code to isolate calculating current FIFO depth.

One functional (albeit guest-invisible) side-effect of this change is
that previously we would always increment s->read_pos in UARTDR read
handler even if FIFO was disabled, now we are limiting read_pos to not
exceed FIFO depth (read_pos itself is reset to 0 if user disables FIFO).

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-2-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/char/pl011.h |  5 ++++-
 hw/char/pl011.c         | 30 ++++++++++++++++++------------
 2 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/char/pl011.h
+++ b/include/hw/char/pl011.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(PL011State, PL011)
 /* This shares the same struct (and cast macro) as the base pl011 device */
 #define TYPE_PL011_LUMINARY "pl011_luminary"
 
+/* Depth of UART FIFO in bytes, when FIFO mode is enabled (else depth == 1) */
+#define PL011_FIFO_DEPTH 16
+
 struct PL011State {
     SysBusDevice parent_obj;
 
@@ -XXX,XX +XXX,XX @@ struct PL011State {
     uint32_t dmacr;
     uint32_t int_enabled;
     uint32_t int_level;
-    uint32_t read_fifo[16];
+    uint32_t read_fifo[PL011_FIFO_DEPTH];
     uint32_t ilpr;
     uint32_t ibrd;
     uint32_t fbrd;
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static void pl011_update(PL011State *s)
     }
 }
 
+static bool pl011_is_fifo_enabled(PL011State *s)
+{
+    return (s->lcr & 0x10) != 0;
+}
+
+static inline unsigned pl011_get_fifo_depth(PL011State *s)
+{
+    /* Note: FIFO depth is expected to be power-of-2 */
+    return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
         c = s->read_fifo[s->read_pos];
         if (s->read_count > 0) {
             s->read_count--;
-            if (++s->read_pos == 16)
-                s->read_pos = 0;
+            s->read_pos = (s->read_pos + 1) & (pl011_get_fifo_depth(s) - 1);
         }
         if (s->read_count == 0) {
             s->flags |= PL011_FLAG_RXFE;
@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
     PL011State *s = (PL011State *)opaque;
     int r;
 
-    if (s->lcr & 0x10) {
-        r = s->read_count < 16;
-    } else {
-        r = s->read_count < 1;
-    }
+    r = s->read_count < pl011_get_fifo_depth(s);
     trace_pl011_can_receive(s->lcr, s->read_count, r);
     return r;
 }
@@ -XXX,XX +XXX,XX @@ static void pl011_put_fifo(void *opaque, uint32_t value)
 {
     PL011State *s = (PL011State *)opaque;
     int slot;
+    unsigned pipe_depth;
 
-    slot = s->read_pos + s->read_count;
-    if (slot >= 16)
-        slot -= 16;
+    pipe_depth = pl011_get_fifo_depth(s);
+    slot = (s->read_pos + s->read_count) & (pipe_depth - 1);
     s->read_fifo[slot] = value;
     s->read_count++;
     s->flags &= ~PL011_FLAG_RXFE;
     trace_pl011_put_fifo(value, s->read_count);
-    if (!(s->lcr & 0x10) || s->read_count == 16) {
+    if (s->read_count == pipe_depth) {
         trace_pl011_put_fifo_full();
         s->flags |= PL011_FLAG_RXFF;
     }
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011 = {
         VMSTATE_UINT32(dmacr, PL011State),
         VMSTATE_UINT32(int_enabled, PL011State),
         VMSTATE_UINT32(int_level, PL011State),
-        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
+        VMSTATE_UINT32_ARRAY(read_fifo, PL011State, PL011_FIFO_DEPTH),
         VMSTATE_UINT32(ilpr, PL011State),
         VMSTATE_UINT32(ibrd, PL011State),
         VMSTATE_UINT32(fbrd, PL011State),
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Previous change slightly modified the way we handle data writes when
FIFO is disabled. Previously we kept incrementing read_pos and were
storing data at that position, although we only have a
single-register-deep FIFO now. Then we changed it to always store data
at pos 0.

If guest disables FIFO and the proceeds to read data, it will work out
fine, because we still read from current read_pos before setting it to
0.

However, to make code less fragile, introduce a post_load hook for
PL011State and move fixup read FIFO state when FIFO is disabled. Since
we are introducing a post_load hook, also do some sanity checking on
untrusted incoming input state.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Message-id: 20230123162304.26254-3-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl011_clock = {
     }
 };
 
+static int pl011_post_load(void *opaque, int version_id)
+{
+    PL011State* s = opaque;
+
+    /* Sanity-check input state */
+    if (s->read_pos >= ARRAY_SIZE(s->read_fifo) ||
+        s->read_count > ARRAY_SIZE(s->read_fifo)) {
+        return -1;
+    }
+
+    if (!pl011_is_fifo_enabled(s) && s->read_count > 0 && s->read_pos > 0) {
+        /*
+         * Older versions of PL011 didn't ensure that the single
+         * character in the FIFO in FIFO-disabled mode is in
+         * element 0 of the array; convert to follow the current
+         * code's assumptions.
+         */
+        s->read_fifo[0] = s->read_fifo[s->read_pos];
+        s->read_pos = 0;
+    }
+
+    return 0;
+}
+
 static const VMStateDescription vmstate_pl011 = {
     .name = "pl011",
     .version_id = 2,
     .minimum_version_id = 2,
+    .post_load = pl011_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32(readbuff, PL011State),
         VMSTATE_UINT32(flags, PL011State),
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

PL011 currently lacks a reset method. Implement it.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230123162304.26254-4-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static void pl011_init(Object *obj)
     s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s,
                                 ClockUpdate);
 
-    s->read_trigger = 1;
-    s->ifl = 0x12;
-    s->cr = 0x300;
-    s->flags = 0x90;
-
     s->id = pl011_id_arm;
 }
 
@@ -XXX,XX +XXX,XX @@ static void pl011_realize(DeviceState *dev, Error **errp)
                              pl011_event, NULL, s, NULL, true);
 }
 
+static void pl011_reset(DeviceState *dev)
+{
+    PL011State *s = PL011(dev);
+
+    s->lcr = 0;
+    s->rsr = 0;
+    s->dmacr = 0;
+    s->int_enabled = 0;
+    s->int_level = 0;
+    s->ilpr = 0;
+    s->ibrd = 0;
+    s->fbrd = 0;
+    s->read_pos = 0;
+    s->read_count = 0;
+    s->read_trigger = 1;
+    s->ifl = 0x12;
+    s->cr = 0x300;
+    s->flags = 0x90;
+}
+
 static void pl011_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
     dc->realize = pl011_realize;
+    dc->reset = pl011_reset;
     dc->vmsd = &vmstate_pl011;
     device_class_set_props(dc, pl011_properties);
 }
-- 
2.34.1

From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>

Current FIFO handling code does not reset RXFE/RXFF flags when guest
resets FIFO by writing to UARTLCR register, although internal FIFO state
is reset to 0 read count. Actual guest-visible flag update will happen
only on next data read or write attempt. As a result of that any guest
that expects RXFE flag to be set (and RXFF to be cleared) after resetting
FIFO will never see that happen.

Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230123162304.26254-5-eiakovlev@linux.microsoft.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -XXX,XX +XXX,XX @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
     return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
 }
 
+static inline void pl011_reset_fifo(PL011State *s)
+{
+    s->read_count = 0;
+    s->read_pos = 0;
+
+    /* Reset FIFO flags */
+    s->flags &= ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF);
+    s->flags |= PL011_FLAG_RXFE | PL011_FLAG_TXFE;
+}
+
 static uint64_t pl011_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void pl011_write(void *opaque, hwaddr offset,
     case 11: /* UARTLCR_H */
         /* Reset the FIFO state on FIFO enable or disable */
         if ((s->lcr ^ value) & 0x10) {
-            s->read_count = 0;
-            s->read_pos = 0;
+            pl011_reset_fifo(s);
         }
         if ((s->lcr ^ value) & 0x1) {
             int break_enable = value & 0x1;
@@ -XXX,XX +XXX,XX @@ static void pl011_reset(DeviceState *dev)
     s->ilpr = 0;
     s->ibrd = 0;
     s->fbrd = 0;
-    s->read_pos = 0;
-    s->read_count = 0;
     s->read_trigger = 1;
     s->ifl = 0x12;
     s->cr = 0x300;
-    s->flags = 0x90;
+    s->flags = 0;
+    pl011_reset_fifo(s);
 }
 
 static void pl011_class_init(ObjectClass *oc, void *data)
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

We currently only support GICv2 emulation. To also support GICv3, we will
need to pass a few system registers into their respective handler functions.

This patch adds support for HVF to call into the TCG callbacks for GICv3
system register handlers. This is safe because the GICv3 TCG code is generic
as long as we limit ourselves to EL0 and EL1 - which are the only modes
supported by HVF.

To make sure nobody trips over that, we also annotate callbacks that don't
work in HVF mode, such as EL state change hooks.

With GICv3 support in place, we can run with more than 8 vCPUs.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-id: 20230128224459.70676-1-agraf@csgraf.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c   |  16 +++-
 target/arm/hvf/hvf.c        | 151 ++++++++++++++++++++++++++++++++++++
 target/arm/hvf/trace-events |   2 +
 3 files changed, 168 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "cpu.h"
 #include "target/arm/cpregs.h"
+#include "sysemu/tcg.h"
+#include "sysemu/qtest.h"
 
 /*
  * Special case return value from hppvi_index(); must be larger than
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
          * which case we'd get the wrong value.
          * So instead we define the regs with no ri->opaque info, and
          * get back to the GICv3CPUState from the CPUARMState.
+         *
+         * These CP regs callbacks can be called from either TCG or HVF code.
          */
         define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
 
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
                 define_arm_cp_regs(cpu, gicv3_cpuif_ich_apxr23_reginfo);
             }
         }
-        arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
+        if (tcg_enabled() || qtest_enabled()) {
+            /*
+             * We can only trap EL changes with TCG. However the GIC interrupt
+             * state only changes on EL changes involving EL2 or EL3, so for
+             * the non-TCG case this is OK, as EL2 and EL3 can't exist.
+             */
+            arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs);
+        } else {
+            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2));
+            assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3));
+        }
     }
 }
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -XXX,XX +XXX,XX @@
 #define SYSREG_PMCCNTR_EL0    SYSREG(3, 3, 9, 13, 0)
 #define SYSREG_PMCCFILTR_EL0  SYSREG(3, 3, 14, 15, 7)
 
+#define SYSREG_ICC_AP0R0_EL1     SYSREG(3, 0, 12, 8, 4)
+#define SYSREG_ICC_AP0R1_EL1     SYSREG(3, 0, 12, 8, 5)
+#define SYSREG_ICC_AP0R2_EL1     SYSREG(3, 0, 12, 8, 6)
+#define SYSREG_ICC_AP0R3_EL1     SYSREG(3, 0, 12, 8, 7)
+#define SYSREG_ICC_AP1R0_EL1     SYSREG(3, 0, 12, 9, 0)
+#define SYSREG_ICC_AP1R1_EL1     SYSREG(3, 0, 12, 9, 1)
+#define SYSREG_ICC_AP1R2_EL1     SYSREG(3, 0, 12, 9, 2)
+#define SYSREG_ICC_AP1R3_EL1     SYSREG(3, 0, 12, 9, 3)
+#define SYSREG_ICC_ASGI1R_EL1    SYSREG(3, 0, 12, 11, 6)
+#define SYSREG_ICC_BPR0_EL1      SYSREG(3, 0, 12, 8, 3)
+#define SYSREG_ICC_BPR1_EL1      SYSREG(3, 0, 12, 12, 3)
+#define SYSREG_ICC_CTLR_EL1      SYSREG(3, 0, 12, 12, 4)
+#define SYSREG_ICC_DIR_EL1       SYSREG(3, 0, 12, 11, 1)
+#define SYSREG_ICC_EOIR0_EL1     SYSREG(3, 0, 12, 8, 1)
+#define SYSREG_ICC_EOIR1_EL1     SYSREG(3, 0, 12, 12, 1)
+#define SYSREG_ICC_HPPIR0_EL1    SYSREG(3, 0, 12, 8, 2)
+#define SYSREG_ICC_HPPIR1_EL1    SYSREG(3, 0, 12, 12, 2)
+#define SYSREG_ICC_IAR0_EL1      SYSREG(3, 0, 12, 8, 0)
+#define SYSREG_ICC_IAR1_EL1      SYSREG(3, 0, 12, 12, 0)
+#define SYSREG_ICC_IGRPEN0_EL1   SYSREG(3, 0, 12, 12, 6)
+#define SYSREG_ICC_IGRPEN1_EL1   SYSREG(3, 0, 12, 12, 7)
+#define SYSREG_ICC_PMR_EL1       SYSREG(3, 0, 4, 6, 0)
+#define SYSREG_ICC_RPR_EL1       SYSREG(3, 0, 12, 11, 3)
+#define SYSREG_ICC_SGI0R_EL1     SYSREG(3, 0, 12, 11, 7)
+#define SYSREG_ICC_SGI1R_EL1     SYSREG(3, 0, 12, 11, 5)
+#define SYSREG_ICC_SRE_EL1       SYSREG(3, 0, 12, 12, 5)
+
 #define WFX_IS_WFE (1 << 0)
 
 #define TMR_CTL_ENABLE  (1 << 0)
@@ -XXX,XX +XXX,XX @@ static bool is_id_sysreg(uint32_t reg)
            SYSREG_CRM(reg) < 8;
 }
 
+static uint32_t hvf_reg2cp_reg(uint32_t reg)
+{
+    return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
+                              (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK,
+                              (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK,
+                              (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK,
+                              (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK,
+                              (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK);
+}
+
+static bool hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg, uint64_t *val)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    const ARMCPRegInfo *ri;
+
+    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+    if (ri) {
+        if (ri->accessfn) {
+            if (ri->accessfn(env, ri, true) != CP_ACCESS_OK) {
+                return false;
+            }
+        }
+        if (ri->type & ARM_CP_CONST) {
+            *val = ri->resetvalue;
+        } else if (ri->readfn) {
+            *val = ri->readfn(env, ri);
+        } else {
+            *val = CPREG_FIELD64(env, ri);
+        }
+        trace_hvf_vgic_read(ri->name, *val);
+        return true;
+    }
+
+    return false;
+}
+
 static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint32_t rt)
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         break;
+    case SYSREG_ICC_AP0R0_EL1:
+    case SYSREG_ICC_AP0R1_EL1:
+    case SYSREG_ICC_AP0R2_EL1:
+    case SYSREG_ICC_AP0R3_EL1:
+    case SYSREG_ICC_AP1R0_EL1:
+    case SYSREG_ICC_AP1R1_EL1:
+    case SYSREG_ICC_AP1R2_EL1:
+    case SYSREG_ICC_AP1R3_EL1:
+    case SYSREG_ICC_ASGI1R_EL1:
+    case SYSREG_ICC_BPR0_EL1:
+    case SYSREG_ICC_BPR1_EL1:
+    case SYSREG_ICC_DIR_EL1:
+    case SYSREG_ICC_EOIR0_EL1:
+    case SYSREG_ICC_EOIR1_EL1:
+    case SYSREG_ICC_HPPIR0_EL1:
+    case SYSREG_ICC_HPPIR1_EL1:
+    case SYSREG_ICC_IAR0_EL1:
+    case SYSREG_ICC_IAR1_EL1:
+    case SYSREG_ICC_IGRPEN0_EL1:
+    case SYSREG_ICC_IGRPEN1_EL1:
+    case SYSREG_ICC_PMR_EL1:
+    case SYSREG_ICC_SGI0R_EL1:
+    case SYSREG_ICC_SGI1R_EL1:
+    case SYSREG_ICC_SRE_EL1:
+    case SYSREG_ICC_CTLR_EL1:
+        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
+        if (!hvf_sysreg_read_cp(cpu, reg, &val)) {
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
+        break;
     default:
         if (is_id_sysreg(reg)) {
             /* ID system registers read as RES0 */
@@ -XXX,XX +XXX,XX @@ static void pmswinc_write(CPUARMState *env, uint64_t value)
     }
 }
 
+static bool hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val)
+{
+    ARMCPU *arm_cpu = ARM_CPU(cpu);
+    CPUARMState *env = &arm_cpu->env;
+    const ARMCPRegInfo *ri;
+
+    ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg));
+
+    if (ri) {
+        if (ri->accessfn) {
+            if (ri->accessfn(env, ri, false) != CP_ACCESS_OK) {
+                return false;
+            }
+        }
+        if (ri->writefn) {
+            ri->writefn(env, ri, val);
+        } else {
+            CPREG_FIELD64(env, ri) = val;
+        }
+
+        trace_hvf_vgic_write(ri->name, val);
+        return true;
+    }
+
+    return false;
+}
+
 static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
 {
     ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -XXX,XX +XXX,XX @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
     case SYSREG_OSDLR_EL1:
         /* Dummy register */
         break;
+    case SYSREG_ICC_AP0R0_EL1:
+    case SYSREG_ICC_AP0R1_EL1:
+    case SYSREG_ICC_AP0R2_EL1:
+    case SYSREG_ICC_AP0R3_EL1:
+    case SYSREG_ICC_AP1R0_EL1:
+    case SYSREG_ICC_AP1R1_EL1:
+    case SYSREG_ICC_AP1R2_EL1:
+    case SYSREG_ICC_AP1R3_EL1:
+    case SYSREG_ICC_ASGI1R_EL1:
+    case SYSREG_ICC_BPR0_EL1:
+    case SYSREG_ICC_BPR1_EL1:
+    case SYSREG_ICC_CTLR_EL1:
+    case SYSREG_ICC_DIR_EL1:
+    case SYSREG_ICC_EOIR0_EL1:
+    case SYSREG_ICC_EOIR1_EL1:
+    case SYSREG_ICC_HPPIR0_EL1:
+    case SYSREG_ICC_HPPIR1_EL1:
+    case SYSREG_ICC_IAR0_EL1:
+    case SYSREG_ICC_IAR1_EL1:
+    case SYSREG_ICC_IGRPEN0_EL1:
+    case SYSREG_ICC_IGRPEN1_EL1:
+    case SYSREG_ICC_PMR_EL1:
+    case SYSREG_ICC_SGI0R_EL1:
+    case SYSREG_ICC_SGI1R_EL1:
+    case SYSREG_ICC_SRE_EL1:
+        /* Call the TCG sysreg handler. This is only safe for GICv3 regs. */
+        if (!hvf_sysreg_write_cp(cpu, reg, val)) {
+            hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized());
+        }
+        break;
     default:
         cpu_synchronize_state(cpu);
         trace_hvf_unhandled_sysreg_write(env->pc, reg,
diff --git a/target/arm/hvf/trace-events b/target/arm/hvf/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/hvf/trace-events
+++ b/target/arm/hvf/trace-events
@@ -XXX,XX +XXX,XX @@ hvf_unknown_hvc(uint64_t x0) "unknown HVC! 0x%016"PRIx64
 hvf_unknown_smc(uint64_t x0) "unknown SMC! 0x%016"PRIx64
 hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
 hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=0x%016"PRIx64" x1=0x%016"PRIx64" x2=0x%016"PRIx64" x3=0x%016"PRIx64" cpu=0x%x"
+hvf_vgic_write(const char *name, uint64_t val) "vgic write to %s [val=0x%016"PRIx64"]"
+hvf_vgic_read(const char *name, uint64_t val) "vgic read from %s [val=0x%016"PRIx64"]"
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

Up to now, the finalize_gic_version() code open coded what is essentially
a support bitmap match between host/emulation environment and desired
target GIC type.

This open coding leads to undesirable side effects. For example, a VM with
KVM and -smp 10 will automatically choose GICv3 while the same command
line with TCG will stay on GICv2 and fail the launch.

This patch combines the TCG and KVM matching code paths by making
everything a 2 pass process. First, we determine which GIC versions the
current environment is able to support, then we go through a single
state machine to determine which target GIC mode that means for us.

After this patch, the only user noticable changes should be consolidated
error messages as well as TCG -M virt supporting -smp > 8 automatically.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Message-id: 20221223090107.98888-2-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  15 ++--
 hw/arm/virt.c         | 198 ++++++++++++++++++++++--------------------
 2 files changed, 112 insertions(+), 101 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef enum VirtMSIControllerType {
 } VirtMSIControllerType;
 
 typedef enum VirtGICType {
-    VIRT_GIC_VERSION_MAX,
-    VIRT_GIC_VERSION_HOST,
-    VIRT_GIC_VERSION_2,
-    VIRT_GIC_VERSION_3,
-    VIRT_GIC_VERSION_4,
+    VIRT_GIC_VERSION_MAX = 0,
+    VIRT_GIC_VERSION_HOST = 1,
+    /* The concrete GIC values have to match the GIC version number */
+    VIRT_GIC_VERSION_2 = 2,
+    VIRT_GIC_VERSION_3 = 3,
+    VIRT_GIC_VERSION_4 = 4,
     VIRT_GIC_VERSION_NOSEL,
 } VirtGICType;
 
+#define VIRT_GIC_VERSION_2_MASK BIT(VIRT_GIC_VERSION_2)
+#define VIRT_GIC_VERSION_3_MASK BIT(VIRT_GIC_VERSION_3)
+#define VIRT_GIC_VERSION_4_MASK BIT(VIRT_GIC_VERSION_4)
+
 struct VirtMachineClass {
     MachineClass parent;
     bool disallow_affinity_adjustment;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
     }
 }
 
+static VirtGICType finalize_gic_version_do(const char *accel_name,
+                                           VirtGICType gic_version,
+                                           int gics_supported,
+                                           unsigned int max_cpus)
+{
+    /* Convert host/max/nosel to GIC version number */
+    switch (gic_version) {
+    case VIRT_GIC_VERSION_HOST:
+        if (!kvm_enabled()) {
+            error_report("gic-version=host requires KVM");
+            exit(1);
+        }
+
+        /* For KVM, gic-version=host means gic-version=max */
+        return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
+                                       gics_supported, max_cpus);
+    case VIRT_GIC_VERSION_MAX:
+        if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
+            gic_version = VIRT_GIC_VERSION_4;
+        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
+            gic_version = VIRT_GIC_VERSION_3;
+        } else {
+            gic_version = VIRT_GIC_VERSION_2;
+        }
+        break;
+    case VIRT_GIC_VERSION_NOSEL:
+        if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
+            max_cpus <= GIC_NCPU) {
+            gic_version = VIRT_GIC_VERSION_2;
+        } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
+            /*
+             * in case the host does not support v2 emulation or
+             * the end-user requested more than 8 VCPUs we now default
+             * to v3. In any case defaulting to v2 would be broken.
+             */
+            gic_version = VIRT_GIC_VERSION_3;
+        } else if (max_cpus > GIC_NCPU) {
+            error_report("%s only supports GICv2 emulation but more than 8 "
+                         "vcpus are requested", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_2:
+    case VIRT_GIC_VERSION_3:
+    case VIRT_GIC_VERSION_4:
+        break;
+    }
+
+    /* Check chosen version is effectively supported */
+    switch (gic_version) {
+    case VIRT_GIC_VERSION_2:
+        if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
+            error_report("%s does not support GICv2 emulation", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_3:
+        if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
+            error_report("%s does not support GICv3 emulation", accel_name);
+            exit(1);
+        }
+        break;
+    case VIRT_GIC_VERSION_4:
+        if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
+            error_report("%s does not support GICv4 emulation, is virtualization=on?",
+                         accel_name);
+            exit(1);
+        }
+        break;
+    default:
+        error_report("logic error in finalize_gic_version");
+        exit(1);
+        break;
+    }
+
+    return gic_version;
+}
+
 /*
  * finalize_gic_version - Determines the final gic_version
  * according to the gic-version property
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
  */
 static void finalize_gic_version(VirtMachineState *vms)
 {
+    const char *accel_name = current_accel_name();
     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
+    int gics_supported = 0;
 
-    if (kvm_enabled()) {
-        int probe_bitmap;
+    /* Determine which GIC versions the current environment supports */
+    if (kvm_enabled() && kvm_irqchip_in_kernel()) {
+        int probe_bitmap = kvm_arm_vgic_probe();
 
-        if (!kvm_irqchip_in_kernel()) {
-            switch (vms->gic_version) {
-            case VIRT_GIC_VERSION_HOST:
-                warn_report(
-                    "gic-version=host not relevant with kernel-irqchip=off "
-                     "as only userspace GICv2 is supported. Using v2 ...");
-                return;
-            case VIRT_GIC_VERSION_MAX:
-            case VIRT_GIC_VERSION_NOSEL:
-                vms->gic_version = VIRT_GIC_VERSION_2;
-                return;
-            case VIRT_GIC_VERSION_2:
-                return;
-            case VIRT_GIC_VERSION_3:
-                error_report(
-                    "gic-version=3 is not supported with kernel-irqchip=off");
-                exit(1);
-            case VIRT_GIC_VERSION_4:
-                error_report(
-                    "gic-version=4 is not supported with kernel-irqchip=off");
-                exit(1);
-            }
-        }
-
-        probe_bitmap = kvm_arm_vgic_probe();
         if (!probe_bitmap) {
             error_report("Unable to determine GIC version supported by host");
             exit(1);
         }
 
-        switch (vms->gic_version) {
-        case VIRT_GIC_VERSION_HOST:
-        case VIRT_GIC_VERSION_MAX:
-            if (probe_bitmap & KVM_ARM_VGIC_V3) {
-                vms->gic_version = VIRT_GIC_VERSION_3;
-            } else {
-                vms->gic_version = VIRT_GIC_VERSION_2;
-            }
-            return;
-        case VIRT_GIC_VERSION_NOSEL:
-            if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
-                vms->gic_version = VIRT_GIC_VERSION_2;
-            } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
-                /*
-                 * in case the host does not support v2 in-kernel emulation or
-                 * the end-user requested more than 8 VCPUs we now default
-                 * to v3. In any case defaulting to v2 would be broken.
-                 */
-                vms->gic_version = VIRT_GIC_VERSION_3;
-            } else if (max_cpus > GIC_NCPU) {
-                error_report("host only supports in-kernel GICv2 emulation "
-                             "but more than 8 vcpus are requested");
-                exit(1);
-            }
-            break;
-        case VIRT_GIC_VERSION_2:
-        case VIRT_GIC_VERSION_3:
-            break;
-        case VIRT_GIC_VERSION_4:
-            error_report("gic-version=4 is not supported with KVM");
-            exit(1);
+        if (probe_bitmap & KVM_ARM_VGIC_V2) {
+            gics_supported |= VIRT_GIC_VERSION_2_MASK;
         }
-
-        /* Check chosen version is effectively supported by the host */
-        if (vms->gic_version == VIRT_GIC_VERSION_2 &&
-            !(probe_bitmap & KVM_ARM_VGIC_V2)) {
-            error_report("host does not support in-kernel GICv2 emulation");
-            exit(1);
-        } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
-                   !(probe_bitmap & KVM_ARM_VGIC_V3)) {
-            error_report("host does not support in-kernel GICv3 emulation");
-            exit(1);
+        if (probe_bitmap & KVM_ARM_VGIC_V3) {
+            gics_supported |= VIRT_GIC_VERSION_3_MASK;
         }
-        return;
-    }
-
-    /* TCG mode */
-    switch (vms->gic_version) {
-    case VIRT_GIC_VERSION_NOSEL:
-        vms->gic_version = VIRT_GIC_VERSION_2;
-        break;
-    case VIRT_GIC_VERSION_MAX:
+    } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
+        /* KVM w/o kernel irqchip can only deal with GICv2 */
+        gics_supported |= VIRT_GIC_VERSION_2_MASK;
+        accel_name = "KVM with kernel-irqchip=off";
+    } else {
+        gics_supported |= VIRT_GIC_VERSION_2_MASK;
         if (module_object_class_by_name("arm-gicv3")) {
-            /* CONFIG_ARM_GICV3_TCG was set */
+            gics_supported |= VIRT_GIC_VERSION_3_MASK;
             if (vms->virt) {
                 /* GICv4 only makes sense if CPU has EL2 */
-                vms->gic_version = VIRT_GIC_VERSION_4;
-            } else {
-                vms->gic_version = VIRT_GIC_VERSION_3;
+                gics_supported |= VIRT_GIC_VERSION_4_MASK;
             }
-        } else {
-            vms->gic_version = VIRT_GIC_VERSION_2;
         }
-        break;
-    case VIRT_GIC_VERSION_HOST:
-        error_report("gic-version=host requires KVM");
-        exit(1);
-    case VIRT_GIC_VERSION_4:
-        if (!vms->virt) {
-            error_report("gic-version=4 requires virtualization enabled");
-            exit(1);
-        }
-        break;
-    case VIRT_GIC_VERSION_2:
-    case VIRT_GIC_VERSION_3:
-        break;
     }
+
+    /*
+     * Then convert helpers like host/max to concrete GIC versions and ensure
+     * the desired version is supported
+     */
+    vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
+                                               gics_supported, max_cpus);
 }
 
 /*
-- 
2.34.1

From: Alexander Graf <agraf@csgraf.de>

Let's explicitly list out all accelerators that we support when trying to
determine the supported set of GIC versions. KVM was already separate, so
the only missing one is HVF which simply reuses all of TCG's emulation
code and thus has the same compatibility matrix.

Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221223090107.98888-3-agraf@csgraf.de
[PMM: Added qtest to the list of accelerators]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/numa.h"
 #include "sysemu/runstate.h"
 #include "sysemu/tpm.h"
+#include "sysemu/tcg.h"
 #include "sysemu/kvm.h"
 #include "sysemu/hvf.h"
+#include "sysemu/qtest.h"
 #include "hw/loader.h"
 #include "qapi/error.h"
 #include "qemu/bitops.h"
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
         /* KVM w/o kernel irqchip can only deal with GICv2 */
         gics_supported |= VIRT_GIC_VERSION_2_MASK;
         accel_name = "KVM with kernel-irqchip=off";
-    } else {
+    } else if (tcg_enabled() || hvf_enabled() || qtest_enabled())  {
         gics_supported |= VIRT_GIC_VERSION_2_MASK;
         if (module_object_class_by_name("arm-gicv3")) {
             gics_supported |= VIRT_GIC_VERSION_3_MASK;
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
                 gics_supported |= VIRT_GIC_VERSION_4_MASK;
             }
         }
+    } else {
+        error_report("Unsupported accelerator, can not determine GIC support");
+        exit(1);
     }
 
     /*
-- 
2.34.1

The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions).  Fix the names.

(This has no guest-visible effect as the names are for debug purposes
only.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = {
 
 #ifndef CONFIG_USER_ONLY
 static const ARMCPRegInfo ats1e1_reginfo[] = {
-    { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
+    { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-    { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
+    { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
       .writefn = ats_write64 },
-- 
2.34.1

The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64).  We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should report the 0x3 syndrome, not the
0x0 'uncategorized' syndrome.  This is clear in the access pseudocode
for these instructions.

Fix the syndrome value for these operations by correcting the
returned value from the ats_access() function.

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
         if (arm_current_el(env) == 1) {
             if (arm_is_secure_below_el3(env)) {
                 if (env->cp15.scr_el3 & SCR_EEL2) {
-                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+                    return CP_ACCESS_TRAP_EL2;
                 }
-                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+                return CP_ACCESS_TRAP_EL3;
             }
             return CP_ACCESS_TRAP_UNCATEGORIZED;
         }
-- 
2.34.1

We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
the ats_access() function, but doing so was incorrect (a bug fixed in
a previous commit).  There aren't any cases where we want an access
function to be able to request a trap to EL2 or EL3 with a zero
syndrome value, so remove these enum values.

As well as cleaning up dead code, the motivation here is that
we'd like to implement fine-grained-trap handling in
helper_access_check_cp_reg(). Although the fine-grained traps
to EL2 are always lower priority than trap-to-same-EL and
higher priority than trap-to-EL3, they are in the middle of
various other kinds of trap-to-EL2. Knowing that a trap-to-EL2
must always for us have the same syndrome (ie that an access
function will return CP_ACCESS_TRAP_EL2 and there is no other
kind of trap-to-EL2 enum value) means we don't have to try
to choose which of the two syndrome values to report if the
access would trap to EL2 both for the fine-grained-trap and
because the access function requires it.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
      * Access fails and results in an exception syndrome 0x0 ("uncategorized").
      * Note that this is not a catch-all case -- the set of cases which may
      * result in this failure is specifically defined by the architecture.
+     * This trap is always to the usual target EL, never directly to a
+     * specified target EL.
      */
     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
-    CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
 } CPAccessResult;
 
 typedef struct ARMCPRegInfo ARMCPRegInfo;
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
     case CP_ACCESS_TRAP:
         break;
     case CP_ACCESS_TRAP_UNCATEGORIZED:
+        /* Only CP_ACCESS_TRAP traps are direct to a specified EL */
+        assert((res & CP_ACCESS_EL_MASK) == 0);
         if (cpu_isar_feature(aa64_ids, cpu) && isread &&
             arm_cpreg_in_idspace(ri)) {
             /*
-- 
2.34.1

Rearrange the code in do_coproc_insn() so that we calculate the
syndrome value for a potential trap early; we're about to add a
second check that wants this value earlier than where it is currently
determined.

(Specifically, a trap to EL2 because of HSTR_EL2 should take
priority over an UNDEF to EL1, even when the UNDEF is because
the register does not exist at all or because its ri->access
bits non-configurably fail the access. So the check we put in
for HSTR_EL2 trapping at EL1 (which needs the syndrome) is
going to have to be done before the check "is the ARMCPRegInfo
pointer NULL".)

This commit is just code motion; the change to HSTR_EL2
handling that will use the 'syndrome' variable is in a
subsequent commit.

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
     const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key);
     TCGv_ptr tcg_ri = NULL;
     bool need_exit_tb;
+    uint32_t syndrome;
+
+    /*
+     * Note that since we are an implementation which takes an
+     * exception on a trapped conditional instruction only if the
+     * instruction passes its condition code check, we can take
+     * advantage of the clause in the ARM ARM that allows us to set
+     * the COND field in the instruction to 0xE in all cases.
+     * We could fish the actual condition out of the insn (ARM)
+     * or the condexec bits (Thumb) but it isn't necessary.
+     */
+    switch (cpnum) {
+    case 14:
+        if (is64) {
+            syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
+                                         isread, false);
+        } else {
+            syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
+                                        rt, isread, false);
+        }
+        break;
+    case 15:
+        if (is64) {
+            syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
+                                         isread, false);
+        } else {
+            syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
+                                        rt, isread, false);
+        }
+        break;
+    default:
+        /*
+         * ARMv8 defines that only coprocessors 14 and 15 exist,
+         * so this can only happen if this is an ARMv7 or earlier CPU,
+         * in which case the syndrome information won't actually be
+         * guest visible.
+         */
+        assert(!arm_dc_feature(s, ARM_FEATURE_V8));
+        syndrome = syn_uncategorized();
+        break;
+    }
 
     if (!ri) {
         /*
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
          * Note that on XScale all cp0..c13 registers do an access check
          * call in order to handle c15_cpar.
          */
-        uint32_t syndrome;
-
-        /*
-         * Note that since we are an implementation which takes an
-         * exception on a trapped conditional instruction only if the
-         * instruction passes its condition code check, we can take
-         * advantage of the clause in the ARM ARM that allows us to set
-         * the COND field in the instruction to 0xE in all cases.
-         * We could fish the actual condition out of the insn (ARM)
-         * or the condexec bits (Thumb) but it isn't necessary.
-         */
-        switch (cpnum) {
-        case 14:
-            if (is64) {
-                syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
-                                             isread, false);
-            } else {
-                syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
-                                            rt, isread, false);
-            }
-            break;
-        case 15:
-            if (is64) {
-                syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
-                                             isread, false);
-            } else {
-                syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
-                                            rt, isread, false);
-            }
-            break;
-        default:
-            /*
-             * ARMv8 defines that only coprocessors 14 and 15 exist,
-             * so this can only happen if this is an ARMv7 or earlier CPU,
-             * in which case the syndrome information won't actually be
-             * guest visible.
-             */
-            assert(!arm_dc_feature(s, ARM_FEATURE_V8));
-            syndrome = syn_uncategorized();
-            break;
-        }
-
         gen_set_condexec(s);
         gen_update_pc(s, 0);
         tcg_ri = tcg_temp_new_ptr();
-- 
2.34.1

The HSTR_EL2 register has a collection of trap bits which allow
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
registers.  The specification of these bits is that when the bit is
set we should trap
 * EL1 accesses
 * EL0 accesses, if the access is not UNDEFINED when the
   trap bit is 0

In other words, all UNDEF traps from EL0 to EL1 take precedence over
the HSTR_EL2 trap to EL2.  (Since this is all AArch32, the only kind
of trap-to-EL1 is the UNDEF.)

Our implementation doesn't quite get this right -- we check for traps
in the order:
 * no such register
 * ARMCPRegInfo::access bits
 * HSTR_EL2 trap bits
 * ARMCPRegInfo::accessfn

So UNDEFs that happen because of the access bits or because the
register doesn't exist at all correctly take priority over the
HSTR_EL2 trap, but where a register can UNDEF at EL0 because of the
accessfn we are incorrectly always taking the HSTR_EL2 trap.  There
aren't many of these, but one example is the PMCR; if you look at the
access pseudocode for this register you can see that UNDEFs taken
because of the value of PMUSERENR.EN are checked before the HSTR_EL2
bit.

Rearrange helper_access_check_cp_reg() so that we always call the
accessfn, and use its return value if it indicates that the access
traps to EL0 rather than continuing to do the HSTR_EL2 check.

The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
 * EL1 accesses
 * EL0 accesses, if the access is not UNDEFINED when the
   trap bit is 0

(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
HSTR_EL2 traps from EL0 are priority 15.)

However, we don't get this right for EL1 accesses which UNDEF because
the register doesn't exist at all or because its ri->access bits
non-configurably forbid the access.  At EL1, check for the HSTR_EL2
trap early, before either of these UNDEF reasons.

We have to retain the HSTR_EL2 check in access_check_cp_reg(),
because at EL0 any kind of UNDEF-to-EL1 (including "no such
register", "bad ri->access" and "ri->accessfn returns 'trap to EL1'")
takes precedence over the trap to EL2.  But we only need to do that
check for EL0 now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230130182459.3309057-7-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-7-peter.maydell@linaro.org
---
 target/arm/op_helper.c |  6 +++++-
 target/arm/translate.c | 28 +++++++++++++++++++++++++++-
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
         goto fail;
     }
 
-    if (!is_a64(env) && arm_current_el(env) < 2 && ri->cp == 15 &&
+    /*
+     * HSTR_EL2 traps from EL1 are checked earlier, in generated code;
+     * we only need to check here for traps from EL0.
+     */
+    if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         uint32_t mask = 1 << ri->crn;
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         break;
     }
 
+    if (s->hstr_active && cpnum == 15 && s->current_el == 1) {
+        /*
+         * At EL1, check for a HSTR_EL2 trap, which must take precedence
+         * over the UNDEF for "no such register" or the UNDEF for "access
+         * permissions forbid this EL1 access". HSTR_EL2 traps from EL0
+         * only happen if the cpreg doesn't UNDEF at EL0, so we do those in
+         * access_check_cp_reg(), after the checks for whether the access
+         * configurably trapped to EL1.
+         */
+        uint32_t maskbit = is64 ? crm : crn;
+
+        if (maskbit != 4 && maskbit != 14) {
+            /* T4 and T14 are RES0 so never cause traps */
+            TCGv_i32 t;
+            DisasLabel over = gen_disas_label(s);
+
+            t = load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2));
+            tcg_gen_andi_i32(t, t, 1u << maskbit);
+            tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
+            tcg_temp_free_i32(t);
+
+            gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
+            set_disas_label(s, over);
+        }
+    }
+
     if (!ri) {
         /*
          * Unknown register; this might be a guest error or a QEMU
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
         return;
     }
 
-    if (s->hstr_active || ri->accessfn ||
+    if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
         /*
          * Emit code to perform further access permissions checks at
-- 
2.34.1

The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state.  We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.

Add the missing checks. (Other places where we look at HSTR_EL2
for the not-in-v8A bits TTEE and TJDBX are already checking that
we are in NS EL0 or EL1, so there we alredy know EL2 is enabled.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
         DP_TBFLAG_A32(flags, VFPEN, 1);
     }
 
-    if (el < 2 && env->cp15.hstr_el2 &&
+    if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
     }
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
      * we only need to check here for traps from EL0.
      */
     if (!is_a64(env) && arm_current_el(env) == 0 && ri->cp == 15 &&
+        arm_is_el2_enabled(env) &&
         (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
         uint32_t mask = 1 << ri->crn;
 
-- 
2.34.1

Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
 HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2

All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
access.  The R and W register pairs are for system registers,
allowing trapping to be done separately for reads and writes; the I
register is for system instructions where trapping is on instruction
execution.

The data storage in the CPU state struct is arranged as a set of
arrays rather than separate fields so that when we're looking up the
bits for a system register access we can just index into the array
rather than having to use a switch to select a named struct member.
The later FEAT_FGT2 will add extra elements to these arrays.

The field definitions for the new registers are in cpregs.h because
in practice the code that needs them is code that also needs
the cpregs information; cpu.h is included in a lot more files.
We're also going to add some FGT-specific definitions to cpregs.h
in the next commit.

We do not implement HAFGRTR_EL2, because we don't implement
FEAT_AMUv1.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum CPAccessResult {
     CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
 } CPAccessResult;
 
+/* Indexes into fgt_read[] */
+#define FGTREG_HFGRTR 0
+#define FGTREG_HDFGRTR 1
+/* Indexes into fgt_write[] */
+#define FGTREG_HFGWTR 0
+#define FGTREG_HDFGWTR 1
+/* Indexes into fgt_exec[] */
+#define FGTREG_HFGITR 0
+
+FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
+FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
+FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
+FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
+FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
+FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
+FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
+FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
+FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
+FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
+FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
+FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
+FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
+FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
+FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
+FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
+FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
+FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
+FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
+FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
+FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
+FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
+FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
+FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
+FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
+FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
+FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
+FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
+FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
+FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
+FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
+FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
+FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
+FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
+FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
+FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
+FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
+FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
+FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
+FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
+FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
+FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
+FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
+FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
+FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
+FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
+FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
+FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
+FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
+FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
+FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
+/* 51-53: RES0 */
+FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
+FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
+/* 56-63: RES0 */
+
+/* These match HFGRTR but bits for RO registers are RES0 */
+FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
+FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
+FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
+FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
+FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
+FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
+FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
+FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
+FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
+FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
+FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
+FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
+FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
+FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
+FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
+FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
+FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
+FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
+FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
+FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
+FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
+FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
+FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
+FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
+FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
+FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
+FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
+FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
+FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
+FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
+FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
+FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
+FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
+FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
+FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
+FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
+FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
+FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
+FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
+FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
+
+FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
+FIELD(HFGITR_EL2, ICIALLU, 1, 1)
+FIELD(HFGITR_EL2, ICIVAU, 2, 1)
+FIELD(HFGITR_EL2, DCIVAC, 3, 1)
+FIELD(HFGITR_EL2, DCISW, 4, 1)
+FIELD(HFGITR_EL2, DCCSW, 5, 1)
+FIELD(HFGITR_EL2, DCCISW, 6, 1)
+FIELD(HFGITR_EL2, DCCVAU, 7, 1)
+FIELD(HFGITR_EL2, DCCVAP, 8, 1)
+FIELD(HFGITR_EL2, DCCVADP, 9, 1)
+FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
+FIELD(HFGITR_EL2, DCZVA, 11, 1)
+FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
+FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
+FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
+FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
+FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
+FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
+FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
+FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
+FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
+FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
+FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
+FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
+FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
+FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
+FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
+FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
+FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
+FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
+FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
+FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
+FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
+FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
+FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
+FIELD(HFGITR_EL2, ERET, 51, 1)
+FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
+FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
+FIELD(HFGITR_EL2, DCCVAC, 54, 1)
+FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
+FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
+
+FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
+FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
+FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
+FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
+FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
+FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
+FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
+FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
+/* 8: RES0: OSLAR_EL1 is WO */
+FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
+FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
+FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
+FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
+FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
+FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
+FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
+FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
+FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
+FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
+FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
+/* 20: RES0: PMSWINC_EL0 is WO */
+/* 21: RES0: PMCR_EL0 is WO */
+FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
+FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
+FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
+FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
+FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
+FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
+FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
+FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
+FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
+FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
+FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
+FIELD(HDFGRTR_EL2, TRC, 33, 1)
+FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
+FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
+FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
+FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
+/* 38, 39: RES0 */
+FIELD(HDFGRTR_EL2, TRCID, 40, 1)
+FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
+/* 42: RES0: TRCOSLAR is WO */
+FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
+FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
+FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
+FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
+FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
+FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
+/* 49: RES0: TRFCR_EL1 is WO */
+FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
+FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
+FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
+FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
+FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
+FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
+FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
+FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
+FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
+FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
+FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
+FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
+FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
+FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
+
+/*
+ * These match HDFGRTR_EL2, but bits for RO registers are RES0.
+ * A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
+ */
+FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
+FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
+FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
+FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
+FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
+FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
+FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
+FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
+FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
+FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
+FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
+FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
+FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
+FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
+FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
+FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
+FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
+FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
+FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
+FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
+FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
+FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
+FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
+FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
+FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
+FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
+FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
+FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
+FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
+FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
+FIELD(HDFGWTR_EL2, TRC, 33, 1)
+FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
+FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
+FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
+FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
+FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
+FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
+FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
+FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
+FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
+FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
+FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
+FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
+FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
+FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
+FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
+FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
+FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
+FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
+FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
+FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
+
 typedef struct ARMCPRegInfo ARMCPRegInfo;
 
 /*
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
         uint64_t disr_el1;
         uint64_t vdisr_el2;
         uint64_t vsesr_el2;
+
+        /*
+         * Fine-Grained Trap registers. We store these as arrays so the
+         * access checking code doesn't have to manually select
+         * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
+         * FEAT_FGT2 will add more elements to these arrays.
+         */
+        uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
+        uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
+        uint64_t fgt_exec[1]; /* HFGITR */
     } cp15;
 
     struct {
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
     return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
 }
 
+static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
+}
+
 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_hcx, cpu)) {
             valid_mask |= SCR_HXEN;
         }
+        if (cpu_isar_feature(aa64_fgt, cpu)) {
+            valid_mask |= SCR_FGTEN;
+        }
     } else {
         valid_mask &= ~(SCR_RW | SCR_ST);
         if (cpu_isar_feature(aa32_ras, cpu)) {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
       .access = PL3_RW,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
 };
+
+static CPAccessResult access_fgt(CPUARMState *env, const ARMCPRegInfo *ri,
+                                 bool isread)
+{
+    if (arm_current_el(env) == 2 &&
+        arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_FGTEN)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
+static const ARMCPRegInfo fgt_reginfo[] = {
+    { .name = "HFGRTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR]) },
+    { .name = "HFGWTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 5,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]) },
+    { .name = "HDFGRTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 4,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]) },
+    { .name = "HDFGWTR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 1, .opc2 = 5,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR]) },
+    { .name = "HFGITR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 6,
+      .access = PL2_RW, .accessfn = access_fgt,
+      .fieldoffset = offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR]) },
+};
 #endif /* TARGET_AARCH64 */
 
 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (cpu_isar_feature(aa64_scxtnum, cpu)) {
         define_arm_cp_regs(cpu, scxtnum_reginfo);
     }
+
+    if (cpu_isar_feature(aa64_fgt, cpu)) {
+        define_arm_cp_regs(cpu, fgt_reginfo);
+    }
 #endif
 
     if (cpu_isar_feature(any_predinv, cpu)) {
-- 
2.34.1

Implement the machinery for fine-grained traps on normal sysregs.
Any sysreg with a fine-grained trap will set the new field to
indicate which FGT register bit it should trap on.

FGT traps only happen when an AArch64 EL2 enables them for
an AArch64 EL1. They therefore are only relevant for AArch32
cpregs when the cpreg can be accessed from EL0. The logic
in access_check_cp_reg() will check this, so it is safe to
add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo.

The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname
which can be used to specify the FGT bit, eg
   .fgt = FGT_AFSR0_EL1
(We assume that there is no bit name duplication across the FGT
registers, for brevity's sake.)

Subsequent commits will add the .fgt fields to the relevant register
definitions and define the FGT_nnn values for them.

Note that some of the FGT traps are for instructions that we don't
handle via the cpregs mechanisms (mostly these are instruction traps).
Those we will have to handle separately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
---
 target/arm/cpregs.h        | 72 ++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h           |  1 +
 target/arm/internals.h     | 20 +++++++++++
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        |  9 +++++
 target/arm/op_helper.c     | 30 ++++++++++++++++
 target/arm/translate-a64.c |  3 +-
 target/arm/translate.c     |  2 ++
 8 files changed, 138 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
 FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
 FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
 
+/* Which fine-grained trap bit register to check, if any */
+FIELD(FGT, TYPE, 10, 3)
+FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
+FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
+FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
+
+/*
+ * Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
+ * fields. We assume for brevity's sake that there are no duplicated
+ * bit names across the various FGT registers.
+ */
+#define DO_BIT(REG, BITNAME)                                    \
+    FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
+
+/* Some bits have reversed sense, so 0 means trap and 1 means not */
+#define DO_REV_BIT(REG, BITNAME)                                        \
+    FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
+
+typedef enum FGTBit {
+    /*
+     * These bits tell us which register arrays to use:
+     * if FGT_R is set then reads are checked against fgt_read[];
+     * if FGT_W is set then writes are checked against fgt_write[];
+     * if FGT_EXEC is set then all accesses are checked against fgt_exec[].
+     *
+     * For almost all bits in the R/W register pairs, the bit exists in
+     * both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
+     * with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
+     * for a WO register. There are unfortunately a couple of exceptions
+     * (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
+     * the FGT system only allows trapping of writes, not reads.
+     *
+     * Note that we arrange these bits so that a 0 FGTBit means "no trap".
+     */
+    FGT_R = 1 << R_FGT_TYPE_SHIFT,
+    FGT_W = 2 << R_FGT_TYPE_SHIFT,
+    FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
+    FGT_RW = FGT_R | FGT_W,
+    /* Bit to identify whether trap bit is reversed sense */
+    FGT_REV = R_FGT_REV_MASK,
+
+    /*
+     * If a bit exists in HFGRTR/HDFGRTR then either the register being
+     * trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
+     * want to trap for both reads and writes or else it's harmless to mark
+     * it as trap-on-writes.
+     * If a bit exists only in HFGWTR/HDFGWTR then either the register being
+     * trapped is WO, or else it is one of the two oddball special cases
+     * which are RW but have only a write trap. We mark these as only
+     * FGT_W so we get the right behaviour for those special cases.
+     * (If a bit was added in future that provided only a read trap for an
+     * RW register we'd need to do something special to get the FGT_R bit
+     * only. But this seems unlikely to happen.)
+     *
+     * So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
+     * the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
+     */
+    FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
+    FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
+    FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
+    FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
+    FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
+} FGTBit;
+
+#undef DO_BIT
+#undef DO_REV_BIT
+
 typedef struct ARMCPRegInfo ARMCPRegInfo;
 
 /*
@@ -XXX,XX +XXX,XX @@ struct ARMCPRegInfo {
     CPAccessRights access;
     /* Security state: ARM_CP_SECSTATE_* bits/values */
     CPSecureState secure;
+    /*
+     * Which fine-grained trap register bit to check, if any. This
+     * value encodes both the trap register and bit within it.
+     */
+    FGTBit fgt;
     /*
      * The opaque pointer passed to define_arm_cp_regs_with_opaque() when
      * this register was defined: can be used to hand data through to the
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
+FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
     ((1 << (1 - 1)) | (1 << (2 - 1)) |                  \
      (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1)))
 
+/*
+ * Return true if it is possible to take a fine-grained-trap to EL2.
+ */
+static inline bool arm_fgt_active(CPUARMState *env, int el)
+{
+    /*
+     * The Arm ARM only requires the "{E2H,TGE} != {1,1}" test for traps
+     * that can affect EL0, but it is harmless to do the test also for
+     * traps on registers that are only accessible at EL1 because if the test
+     * returns true then we can't be executing at EL1 anyway.
+     * FGT traps only happen when EL2 is enabled and EL1 is AArch64;
+     * traps from AArch32 only happen for the EL0 is AArch32 case.
+     */
+    return cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+        el < 2 && arm_is_el2_enabled(env) &&
+        arm_el_is_aa64(env, 1) &&
+        (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE) &&
+        (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN));
+}
+
 #endif
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool is_nonstreaming;
     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
     bool mve_no_pred;
+    /* True if fine-grained traps are active */
+    bool fgt_active;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
     if (arm_singlestep_active(env)) {
         DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
     }
+
     return flags;
 }
 
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
         DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
     }
 
+    if (arm_fgt_active(env, el)) {
+        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+    }
+
     if (env->uncached_cpsr & CPSR_IL) {
         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
     }
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         DP_TBFLAG_ANY(flags, PSTATE__IL, 1);
     }
 
+    if (arm_fgt_active(env, el)) {
+        DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+    }
+
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
         /*
          * Set MTE_ACTIVE if any access may be Checked, and leave clear
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ const void *HELPER(access_check_cp_reg)(CPUARMState *env, uint32_t key,
         }
     }
 
+    /*
+     * Fine-grained traps also are lower priority than undef-to-EL1,
+     * higher priority than trap-to-EL3, and we don't care about priority
+     * order with other EL2 traps because the syndrome value is the same.
+     */
+    if (arm_fgt_active(env, arm_current_el(env))) {
+        uint64_t trapword = 0;
+        unsigned int idx = FIELD_EX32(ri->fgt, FGT, IDX);
+        unsigned int bitpos = FIELD_EX32(ri->fgt, FGT, BITPOS);
+        bool rev = FIELD_EX32(ri->fgt, FGT, REV);
+        bool trapbit;
+
+        if (ri->fgt & FGT_EXEC) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_exec));
+            trapword = env->cp15.fgt_exec[idx];
+        } else if (isread && (ri->fgt & FGT_R)) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_read));
+            trapword = env->cp15.fgt_read[idx];
+        } else if (!isread && (ri->fgt & FGT_W)) {
+            assert(idx < ARRAY_SIZE(env->cp15.fgt_write));
+            trapword = env->cp15.fgt_write[idx];
+        }
+
+        trapbit = extract64(trapword, bitpos, 1);
+        if (trapbit != rev) {
+            res = CP_ACCESS_TRAP_EL2;
+            goto fail;
+        }
+    }
+
     if (likely(res == CP_ACCESS_OK)) {
         return ri;
     }
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         return;
     }
 
-    if (ri->accessfn) {
+    if (ri->accessfn || (ri->fgt && s->fgt_active)) {
         /* Emit code to perform further access permissions checks at
          * runtime; this may result in an exception.
          */
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
+    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
     }
 
     if ((s->hstr_active && s->current_el == 0) || ri->accessfn ||
+        (ri->fgt && s->fgt_active) ||
         (arm_dc_feature(s, ARM_FEATURE_XSCALE) && cpnum < 14)) {
         /*
          * Emit code to perform further access permissions checks at
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
+    dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         dc->vfp_enabled = 1;
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
     FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
     FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
+
+    /* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
+    DO_BIT(HFGRTR, AFSR0_EL1),
+    DO_BIT(HFGRTR, AFSR1_EL1),
+    DO_BIT(HFGRTR, AIDR_EL1),
+    DO_BIT(HFGRTR, AMAIR_EL1),
+    DO_BIT(HFGRTR, APDAKEY),
+    DO_BIT(HFGRTR, APDBKEY),
+    DO_BIT(HFGRTR, APGAKEY),
+    DO_BIT(HFGRTR, APIAKEY),
+    DO_BIT(HFGRTR, APIBKEY),
+    DO_BIT(HFGRTR, CCSIDR_EL1),
+    DO_BIT(HFGRTR, CLIDR_EL1),
+    DO_BIT(HFGRTR, CONTEXTIDR_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_CONTEXTIDR_EL1,
       .secure = ARM_CP_SECSTATE_NS,
       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
       .access = PL1_R,
       .accessfn = access_tid4,
+      .fgt = FGT_CCSIDR_EL1,
       .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
       .access = PL1_R, .type = ARM_CP_CONST,
       .accessfn = access_aa64_tid1,
+      .fgt = FGT_AIDR_EL1,
       .resetvalue = 0 },
     /*
      * Auxiliary fault status registers: these also are IMPDEF, and we
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AFSR0_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AFSR1_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * MAIR can just read-as-written because we don't implement caches
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_AMAIR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
     { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apda.lo) },
     { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apda.hi) },
     { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apdb.lo) },
     { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APDBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apdb.hi) },
     { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APGAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apga.lo) },
     { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APGAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apga.hi) },
     { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apia.lo) },
     { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIAKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apia.hi) },
     { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apib.lo) },
     { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_pauth,
+      .fgt = FGT_APIBKEY,
       .fieldoffset = offsetof(CPUARMState, keys.apib.hi) },
 };
 
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
             .access = PL1_R, .type = ARM_CP_CONST,
             .accessfn = access_tid4,
+            .fgt = FGT_CLIDR_EL1,
             .resetvalue = cpu->clidr
         };
         define_one_arm_cp_reg(cpu, &clidr);
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 12..23.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, CCSIDR_EL1),
     DO_BIT(HFGRTR, CLIDR_EL1),
     DO_BIT(HFGRTR, CONTEXTIDR_EL1),
+    DO_BIT(HFGRTR, CPACR_EL1),
+    DO_BIT(HFGRTR, CSSELR_EL1),
+    DO_BIT(HFGRTR, CTR_EL0),
+    DO_BIT(HFGRTR, DCZID_EL0),
+    DO_BIT(HFGRTR, ESR_EL1),
+    DO_BIT(HFGRTR, FAR_EL1),
+    DO_BIT(HFGRTR, ISR_EL1),
+    DO_BIT(HFGRTR, LORC_EL1),
+    DO_BIT(HFGRTR, LOREA_EL1),
+    DO_BIT(HFGRTR, LORID_EL1),
+    DO_BIT(HFGRTR, LORN_EL1),
+    DO_BIT(HFGRTR, LORSA_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
+      .fgt = FGT_CPACR_EL1,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
       .resetfn = cpacr_reset, .writefn = cpacr_write, .readfn = cpacr_read },
 };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
       .access = PL1_RW,
       .accessfn = access_tid4,
+      .fgt = FGT_CSSELR_EL1,
       .writefn = csselr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
                              offsetof(CPUARMState, cp15.csselr_ns) } },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .resetfn = arm_cp_reset_ignore },
     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
+      .fgt = FGT_ISR_EL1,
       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
     /* 32 bit ITLB invalidates */
     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_FAR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
       .resetvalue = 0, },
 };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_ESR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
       .access = PL0_R, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_DCZID_EL0,
       .readfn = aa64_dczid_read },
     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
     { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORSA_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LOREA_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORN_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
       .access = PL1_RW, .accessfn = access_lor_other,
+      .fgt = FGT_LORC_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
       .access = PL1_R, .accessfn = access_lor_ns,
+      .fgt = FGT_LORID_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
 };
 
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
               .access = PL0_R, .accessfn = ctr_el0_access,
+              .fgt = FGT_CTR_EL0,
               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
             { .name = "TCMTR",
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 24..35.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, LORID_EL1),
     DO_BIT(HFGRTR, LORN_EL1),
     DO_BIT(HFGRTR, LORSA_EL1),
+    DO_BIT(HFGRTR, MAIR_EL1),
+    DO_BIT(HFGRTR, MIDR_EL1),
+    DO_BIT(HFGRTR, MPIDR_EL1),
+    DO_BIT(HFGRTR, PAR_EL1),
+    DO_BIT(HFGRTR, REVIDR_EL1),
+    DO_BIT(HFGRTR, SCTLR_EL1),
+    DO_BIT(HFGRTR, SCXTNUM_EL1),
+    DO_BIT(HFGRTR, SCXTNUM_EL0),
+    DO_BIT(HFGRTR, TCR_EL1),
+    DO_BIT(HFGRTR, TPIDR_EL1),
+    DO_BIT(HFGRTR, TPIDRRO_EL0),
+    DO_BIT(HFGRTR, TPIDR_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_MAIR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
       .resetvalue = 0 },
     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
       .access = PL0_RW,
+      .fgt = FGT_TPIDR_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW,
+      .fgt = FGT_TPIDR_EL0,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
       .resetfn = arm_cp_reset_ignore },
     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
       .access = PL0_R | PL1_W,
+      .fgt = FGT_TPIDRRO_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
       .resetvalue = 0},
     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
       .access = PL0_R | PL1_W,
+      .fgt = FGT_TPIDRRO_EL0,
       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
       .resetfn = arm_cp_reset_ignore },
     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
       .access = PL1_RW,
+      .fgt = FGT_TPIDR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
       .access = PL1_RW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TCR_EL1,
       .writefn = vmsa_tcr_el12_write,
       .raw_writefn = raw_write,
       .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .type = ARM_CP_ALIAS,
       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
       .access = PL1_RW, .resetvalue = 0,
+      .fgt = FGT_PAR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
       .writefn = par_write },
 #endif
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo scxtnum_reginfo[] = {
     { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
       .access = PL0_RW, .accessfn = access_scxtnum,
+      .fgt = FGT_SCXTNUM_EL0,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
     { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
       .access = PL1_RW, .accessfn = access_scxtnum,
+      .fgt = FGT_SCXTNUM_EL1,
       .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
     { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
+              .fgt = FGT_MIDR_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
               .readfn = midr_read },
             /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
               .access = PL1_R,
               .accessfn = access_aa64_tid1,
+              .fgt = FGT_REVIDR_EL1,
               .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
         };
         ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
         ARMCPRegInfo mpidr_cp_reginfo[] = {
             { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
+              .fgt = FGT_MPIDR_EL1,
               .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
         };
 #ifdef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
             .access = PL1_RW, .accessfn = access_tvm_trvm,
+            .fgt = FGT_SCTLR_EL1,
             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
                                    offsetof(CPUARMState, cp15.sctlr_ns) },
             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.

Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.

Bit 50 (NACCDATA_EL1) is for the ACCDATA_EL1 register which is part
of the FEAT_LS64_ACCDATA feature which we don't yet implement.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, TPIDR_EL1),
     DO_BIT(HFGRTR, TPIDRRO_EL0),
     DO_BIT(HFGRTR, TPIDR_EL0),
+    DO_BIT(HFGRTR, TTBR0_EL1),
+    DO_BIT(HFGRTR, TTBR1_EL1),
+    DO_BIT(HFGRTR, VBAR_EL1),
+    DO_BIT(HFGRTR, ICC_IGRPENN_EL1),
+    DO_BIT(HFGRTR, ERRIDR_EL1),
+    DO_REV_BIT(HFGRTR, NSMPRI_EL1),
+    DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 6,
       .type = ARM_CP_IO | ARM_CP_NO_RAW,
       .access = PL1_RW, .accessfn = gicv3_fiq_access,
+      .fgt = FGT_ICC_IGRPENN_EL1,
       .readfn = icc_igrpen_read,
       .writefn = icc_igrpen_write,
     },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7,
       .type = ARM_CP_IO | ARM_CP_NO_RAW,
       .access = PL1_RW, .accessfn = gicv3_irq_access,
+      .fgt = FGT_ICC_IGRPENN_EL1,
       .readfn = icc_igrpen_read,
       .writefn = icc_igrpen_write,
     },
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TTBR0_EL1,
       .writefn = vmsa_ttbr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tvm_trvm,
+      .fgt = FGT_TTBR1_EL1,
       .writefn = vmsa_ttbr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
@@ -XXX,XX +XXX,XX @@ static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
  *   ERRSELR_EL1
  * may generate UNDEFINED, which is the effect we get by not
  * listing them at all.
+ *
+ * These registers have fine-grained trap bits, but UNDEF-to-EL1
+ * is higher priority than FGT-to-EL2 so we do not need to list them
+ * in order to check for an FGT.
  */
 static const ARMCPRegInfo minimal_ras_reginfo[] = {
     { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
     { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
       .access = PL1_R, .accessfn = access_terr,
+      .fgt = FGT_ERRIDR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
     { .name = "TPIDR2_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 5,
       .access = PL0_RW, .accessfn = access_tpidr2,
+      .fgt = FGT_NTPIDR2_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.tpidr2_el0) },
     { .name = "SVCR", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo sme_reginfo[] = {
     { .name = "SMPRI_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 4,
       .access = PL1_RW, .accessfn = access_esm,
+      .fgt = FGT_NSMPRI_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "SMPRIMAP_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 5,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
               .access = PL1_RW, .writefn = vbar_write,
+              .fgt = FGT_VBAR_EL1,
               .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
                                      offsetof(CPUARMState, cp15.vbar_ns) },
               .resetvalue = 0 },
-- 
2.34.1

Mark up the sysreg definitons for the registers trapped
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
related registers.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGRTR, ERRIDR_EL1),
     DO_REV_BIT(HFGRTR, NSMPRI_EL1),
     DO_REV_BIT(HFGRTR, NTPIDR2_EL0),
+
+    /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */
+    DO_BIT(HDFGRTR, DBGBCRN_EL1),
+    DO_BIT(HDFGRTR, DBGBVRN_EL1),
+    DO_BIT(HDFGRTR, DBGWCRN_EL1),
+    DO_BIT(HDFGRTR, DBGWVRN_EL1),
+    DO_BIT(HDFGRTR, MDSCR_EL1),
+    DO_BIT(HDFGRTR, DBGCLAIM),
+    DO_BIT(HDFGWTR, OSLAR_EL1),
+    DO_BIT(HDFGRTR, OSLSR_EL1),
+    DO_BIT(HDFGRTR, OSECCR_EL1),
+    DO_BIT(HDFGRTR, OSDLR_EL1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_MDSCR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
       .resetvalue = 0 },
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "OSECCR_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_OSECCR_EL1,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
       .access = PL1_W, .type = ARM_CP_NO_RAW,
       .accessfn = access_tdosa,
+      .fgt = FGT_OSLAR_EL1,
       .writefn = oslar_write },
     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
       .access = PL1_R, .resetvalue = 10,
       .accessfn = access_tdosa,
+      .fgt = FGT_OSLSR_EL1,
       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
       .access = PL1_RW, .accessfn = access_tdosa,
+      .fgt = FGT_OSDLR_EL1,
       .writefn = osdlr_write,
       .fieldoffset = offsetof(CPUARMState, cp15.osdlr_el1) },
     /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 6,
       .type = ARM_CP_ALIAS,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_DBGCLAIM,
       .writefn = dbgclaimset_write, .readfn = dbgclaimset_read },
     { .name = "DBGCLAIMCLR_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_tda,
+      .fgt = FGT_DBGCLAIM,
       .writefn = dbgclaimclr_write, .raw_writefn = raw_write,
       .fieldoffset = offsetof(CPUARMState, cp15.dbgclaim) },
 };
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
             { .name = dbgbvr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGBVRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
               .writefn = dbgbvr_write, .raw_writefn = raw_write
             },
             { .name = dbgbcr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGBCRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
               .writefn = dbgbcr_write, .raw_writefn = raw_write
             },
@@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu)
             { .name = dbgwvr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGWVRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
               .writefn = dbgwvr_write, .raw_writefn = raw_write
             },
             { .name = dbgwcr_el1_name, .state = ARM_CP_STATE_BOTH,
               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
               .access = PL1_RW, .accessfn = access_tda,
+              .fgt = FGT_DBGWCRN_EL1,
               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
               .writefn = dbgwcr_write, .raw_writefn = raw_write
             },
-- 
2.34.1

Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.

Bits 12..22 and bit 58 are for PMU registers.

The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:

Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ETE
Bits 50..56 : FEAT_TRBE
Bits 59..61 : FEAT_BRBE
Bit 62 : FEAT_SPEv1p2.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HDFGRTR, OSLSR_EL1),
     DO_BIT(HDFGRTR, OSECCR_EL1),
     DO_BIT(HDFGRTR, OSDLR_EL1),
+    DO_BIT(HDFGRTR, PMEVCNTRN_EL0),
+    DO_BIT(HDFGRTR, PMEVTYPERN_EL0),
+    DO_BIT(HDFGRTR, PMCCFILTR_EL0),
+    DO_BIT(HDFGRTR, PMCCNTR_EL0),
+    DO_BIT(HDFGRTR, PMCNTEN),
+    DO_BIT(HDFGRTR, PMINTEN),
+    DO_BIT(HDFGRTR, PMOVS),
+    DO_BIT(HDFGRTR, PMSELR_EL0),
+    DO_BIT(HDFGWTR, PMSWINC_EL0),
+    DO_BIT(HDFGWTR, PMCR_EL0),
+    DO_BIT(HDFGRTR, PMMIR_EL1),
+    DO_BIT(HDFGRTR, PMCEIDN_EL0),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenset_write,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .raw_writefn = raw_write },
     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
       .writefn = pmcntenset_write, .raw_writefn = raw_write },
     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
       .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .writefn = pmcntenclr_write,
       .type = ARM_CP_ALIAS | ARM_CP_IO },
     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCNTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
       .writefn = pmcntenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .access = PL0_RW, .type = ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
       .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .writefn = pmovsr_write,
       .raw_writefn = raw_write },
     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsr_write,
       .raw_writefn = raw_write },
     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
       .access = PL0_W, .accessfn = pmreg_access_swinc,
+      .fgt = FGT_PMSWINC_EL0,
       .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .writefn = pmswinc_write },
     { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
       .access = PL0_W, .accessfn = pmreg_access_swinc,
+      .fgt = FGT_PMSWINC_EL0,
       .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .writefn = pmswinc_write },
     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
       .access = PL0_RW, .type = ARM_CP_ALIAS,
+      .fgt = FGT_PMSELR_EL0,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
       .accessfn = pmreg_access_selr, .writefn = pmselr_write,
       .raw_writefn = raw_write},
     { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
       .access = PL0_RW, .accessfn = pmreg_access_selr,
+      .fgt = FGT_PMSELR_EL0,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
       .writefn = pmselr_write, .raw_writefn = raw_write, },
     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_ALIAS | ARM_CP_IO,
+      .fgt = FGT_PMCCNTR_EL0,
       .readfn = pmccntr_read, .writefn = pmccntr_write32,
       .accessfn = pmreg_access_ccntr },
     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
       .access = PL0_RW, .accessfn = pmreg_access_ccntr,
+      .fgt = FGT_PMCCNTR_EL0,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
       .readfn = pmccntr_read, .writefn = pmccntr_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
       .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCCFILTR_EL0,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .resetvalue = 0, },
     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
       .writefn = pmccfiltr_write, .raw_writefn = raw_write,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMCCFILTR_EL0,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
       .resetvalue = 0, },
     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMEVTYPERN_EL0,
       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
     { .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access,
+      .fgt = FGT_PMEVTYPERN_EL0,
       .writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access_xevcntr,
+      .fgt = FGT_PMEVCNTRN_EL0,
       .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
     { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
       .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
       .accessfn = pmreg_access_xevcntr,
+      .fgt = FGT_PMEVCNTRN_EL0,
       .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .writefn = pmuserenr_write, .raw_writefn = raw_write },
     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "PMINTENSET_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 1,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenset_write, .raw_writefn = raw_write,
       .resetvalue = 0x0 },
     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenclr_write, },
     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
       .access = PL1_RW, .accessfn = access_tpm,
+      .fgt = FGT_PMINTEN,
       .type = ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .writefn = pmintenclr_write },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
     /* PMOVSSET is not implemented in v7 before v7ve */
     { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
     { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
       .access = PL0_RW, .accessfn = pmreg_access,
+      .fgt = FGT_PMOVS,
       .type = ARM_CP_ALIAS | ARM_CP_IO,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
       .writefn = pmovsset_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     ARMCPRegInfo pmcr = {
         .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
         .access = PL0_RW,
+        .fgt = FGT_PMCR_EL0,
         .type = ARM_CP_IO | ARM_CP_ALIAS,
         .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
         .accessfn = pmreg_access, .writefn = pmcr_write,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
         .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
         .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
         .access = PL0_RW, .accessfn = pmreg_access,
+        .fgt = FGT_PMCR_EL0,
         .type = ARM_CP_IO,
         .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
         .resetvalue = cpu->isar.reset_pmcr_el0,
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             { .name = pmevcntr_name, .cp = 15, .crn = 14,
               .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .fgt = FGT_PMEVCNTRN_EL0,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .accessfn = pmreg_access_xevcntr },
             { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
               .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr,
               .type = ARM_CP_IO,
+              .fgt = FGT_PMEVCNTRN_EL0,
               .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
               .raw_readfn = pmevcntr_rawread,
               .raw_writefn = pmevcntr_rawwrite },
             { .name = pmevtyper_name, .cp = 15, .crn = 14,
               .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
               .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
+              .fgt = FGT_PMEVTYPERN_EL0,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .accessfn = pmreg_access },
             { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
               .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
+              .fgt = FGT_PMEVTYPERN_EL0,
               .type = ARM_CP_IO,
               .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
               .raw_writefn = pmevtyper_rawwrite },
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid0, 32, 32) },
             { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid1, 32, 32) },
         };
         define_arm_cp_regs(cpu, v81_pmu_regs);
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
             .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6,
             .access = PL1_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+            .fgt = FGT_PMMIR_EL1,
             .resetvalue = 0
         };
         define_one_arm_cp_reg(cpu, &v84_pmmir);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid0, 0, 32) },
             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = cpu->pmceid0 },
             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = extract64(cpu->pmceid1, 0, 32) },
             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+              .fgt = FGT_PMCEIDN_EL0,
               .resetvalue = cpu->pmceid1 },
         };
 #ifdef CONFIG_USER_ONLY
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HDFGWTR, PMCR_EL0),
     DO_BIT(HDFGRTR, PMMIR_EL1),
     DO_BIT(HDFGRTR, PMCEIDN_EL0),
+
+    /* Trap bits in HFGITR_EL2, starting from bit 0 */
+    DO_BIT(HFGITR, ICIALLUIS),
+    DO_BIT(HFGITR, ICIALLU),
+    DO_BIT(HFGITR, ICIVAU),
+    DO_BIT(HFGITR, DCIVAC),
+    DO_BIT(HFGITR, DCISW),
+    DO_BIT(HFGITR, DCCSW),
+    DO_BIT(HFGITR, DCCISW),
+    DO_BIT(HFGITR, DCCVAU),
+    DO_BIT(HFGITR, DCCVAP),
+    DO_BIT(HFGITR, DCCVADP),
+    DO_BIT(HFGITR, DCCIVAC),
+    DO_BIT(HFGITR, DCZVA),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIALLUIS,
       .accessfn = access_ticab },
     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIALLU,
       .accessfn = access_tocu },
     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_ICIVAU,
       .accessfn = access_tocu },
     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
+      .fgt = FGT_DCIVAC,
       .type = ARM_CP_NOP },
     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
+      .fgt = FGT_DCISW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
+      .fgt = FGT_DCCSW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCVAU,
       .accessfn = access_tocu },
     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
+      .fgt = FGT_DCCISW,
       .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP },
     /* TLBI operations */
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpop_reg[] = {
     { .name = "DC_CVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 };
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo dcpodp_reg[] = {
     { .name = "DC_CVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
 };
 #endif /*CONFIG_USER_ONLY*/
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
     { .name = "DC_IGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL1_W,
+      .fgt = FGT_DCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_IGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 4,
+      .fgt = FGT_DCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_IGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL1_W,
+      .fgt = FGT_DCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_IGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 6,
+      .fgt = FGT_DCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 4,
+      .fgt = FGT_DCCSW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 6,
+      .fgt = FGT_DCCSW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CIGSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 4,
+      .fgt = FGT_DCCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DC_CIGDSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 6,
+      .fgt = FGT_DCCISW,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
 };
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVADP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 13, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVADP,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CIGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CIGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCIVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_GVA", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
     { .name = "DC_GZVA", .state = ARM_CP_STATE_AA64,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
       /* Avoid overhead of an access check that always passes in user-mode */
       .accessfn = aa64_zva_access,
+      .fgt = FGT_DCZVA,
 #endif
     },
 };
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, DCCVADP),
     DO_BIT(HFGITR, DCCIVAC),
     DO_BIT(HFGITR, DCZVA),
+    DO_BIT(HFGITR, ATS1E1R),
+    DO_BIT(HFGITR, ATS1E1W),
+    DO_BIT(HFGITR, ATS1E0R),
+    DO_BIT(HFGITR, ATS1E0W),
+    DO_BIT(HFGITR, ATS1E1RP),
+    DO_BIT(HFGITR, ATS1E1WP),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1R,
       .writefn = ats_write64 },
     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1W,
       .writefn = ats_write64 },
     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E0R,
       .writefn = ats_write64 },
     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E0W,
       .writefn = ats_write64 },
     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ats1e1_reginfo[] = {
     { .name = "AT_S1E1RP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1RP,
       .writefn = ats_write64 },
     { .name = "AT_S1E1WP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1,
       .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC,
+      .fgt = FGT_ATS1E1WP,
       .writefn = ats_write64 },
 };
 
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 18..47. These bits cover TLBI
TLB maintenance instructions.

(If we implemented FEAT_XS we would need to trap some of the
instructions added by that feature using these bits; but we don't
yet, so will need to add the .fgt markup when we do.)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, ATS1E0W),
     DO_BIT(HFGITR, ATS1E1RP),
     DO_BIT(HFGITR, ATS1E1WP),
+    DO_BIT(HFGITR, TLBIVMALLE1OS),
+    DO_BIT(HFGITR, TLBIVAE1OS),
+    DO_BIT(HFGITR, TLBIASIDE1OS),
+    DO_BIT(HFGITR, TLBIVAAE1OS),
+    DO_BIT(HFGITR, TLBIVALE1OS),
+    DO_BIT(HFGITR, TLBIVAALE1OS),
+    DO_BIT(HFGITR, TLBIRVAE1OS),
+    DO_BIT(HFGITR, TLBIRVAAE1OS),
+    DO_BIT(HFGITR, TLBIRVALE1OS),
+    DO_BIT(HFGITR, TLBIRVAALE1OS),
+    DO_BIT(HFGITR, TLBIVMALLE1IS),
+    DO_BIT(HFGITR, TLBIVAE1IS),
+    DO_BIT(HFGITR, TLBIASIDE1IS),
+    DO_BIT(HFGITR, TLBIVAAE1IS),
+    DO_BIT(HFGITR, TLBIVALE1IS),
+    DO_BIT(HFGITR, TLBIVAALE1IS),
+    DO_BIT(HFGITR, TLBIRVAE1IS),
+    DO_BIT(HFGITR, TLBIRVAAE1IS),
+    DO_BIT(HFGITR, TLBIRVALE1IS),
+    DO_BIT(HFGITR, TLBIRVAALE1IS),
+    DO_BIT(HFGITR, TLBIRVAE1),
+    DO_BIT(HFGITR, TLBIRVAAE1),
+    DO_BIT(HFGITR, TLBIRVALE1),
+    DO_BIT(HFGITR, TLBIRVAALE1),
+    DO_BIT(HFGITR, TLBIVMALLE1),
+    DO_BIT(HFGITR, TLBIVAE1),
+    DO_BIT(HFGITR, TLBIASIDE1),
+    DO_BIT(HFGITR, TLBIVAAE1),
+    DO_BIT(HFGITR, TLBIVALE1),
+    DO_BIT(HFGITR, TLBIVAALE1),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1IS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1IS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1IS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1,
       .writefn = tlbi_aa64_vmalle1_write },
     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1,
       .writefn = tlbi_aa64_vmalle1_write },
     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1,
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1IS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1OS,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAAE1,
       .writefn = tlbi_aa64_rvae1_write },
    { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVALE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIRVAALE1,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
     { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVMALLE1OS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
+      .fgt = FGT_TLBIVAE1OS,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIASIDE1OS,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAAE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVALE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
       .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
+      .fgt = FGT_TLBIVAALE1OS,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-- 
2.34.1

Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.

Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
 * ERET, ERETAA, ERETAB
 * SVC

We will have to handle those separately and manually.

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ typedef enum FGTBit {
     DO_BIT(HFGITR, TLBIVAAE1),
     DO_BIT(HFGITR, TLBIVALE1),
     DO_BIT(HFGITR, TLBIVAALE1),
+    DO_BIT(HFGITR, CFPRCTX),
+    DO_BIT(HFGITR, DVPRCTX),
+    DO_BIT(HFGITR, CPPRCTX),
+    DO_BIT(HFGITR, DCCVAC),
 } FGTBit;
 
 #undef DO_BIT
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
     { .name = "DC_CGVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 3,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGDVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 5,
       .type = ARM_CP_NOP, .access = PL0_W,
+      .fgt = FGT_DCCVAC,
       .accessfn = aa64_cacheop_poc_access },
     { .name = "DC_CGVAP", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 12, .opc2 = 3,
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
 static const ARMCPRegInfo predinv_reginfo[] = {
     { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
+      .fgt = FGT_CFPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
+      .fgt = FGT_DVPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
+      .fgt = FGT_CPPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     /*
      * Note the AArch32 opcodes have a different OPC1.
      */
     { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
+      .fgt = FGT_CFPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
+      .fgt = FGT_DVPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
     { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
+      .fgt = FGT_CPPRCTX,
       .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
 };
 
-- 
2.34.1

Implement the HFGITR_EL2.ERET fine-grained trap.  This traps
execution from AArch64 EL1 of ERET, ERETAA and ERETAB.  The trap is
reported with a syndrome value of 0x1a.

The trap must take precedence over a possible pointer-authentication
trap for ERETAA and ERETAB.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-21-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-21-peter.maydell@linaro.org
---
 target/arm/cpu.h           |  1 +
 target/arm/syndrome.h      | 10 ++++++++++
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        |  3 +++
 target/arm/translate-a64.c | 10 ++++++++++
 5 files changed, 26 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
 FIELD(TBFLAG_A64, SVL, 24, 4)
 /* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
 FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
+FIELD(TBFLAG_A64, FGT_ERET, 29, 1)
 
 /*
  * Helpers for using the above.
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
     EC_AA64_SMC               = 0x17,
     EC_SYSTEMREGISTERTRAP     = 0x18,
     EC_SVEACCESSTRAP          = 0x19,
+    EC_ERETTRAP               = 0x1a,
     EC_SMETRAP                = 0x1d,
     EC_INSNABORT              = 0x20,
     EC_INSNABORT_SAME_EL      = 0x21,
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
     return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
 }
 
+/*
+ * eret_op is bits [1:0] of the ERET instruction, so:
+ * 0 for ERET, 2 for ERETAA, 3 for ERETAB.
+ */
+static inline uint32_t syn_erettrap(int eret_op)
+{
+    return (EC_ERETTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL | eret_op;
+}
+
 static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit)
 {
     return (EC_SMETRAP << ARM_EL_EC_SHIFT)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool mve_no_pred;
     /* True if fine-grained traps are active */
     bool fgt_active;
+    /* True if fine-grained trap on ERET is enabled */
+    bool fgt_eret;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
 
     if (arm_fgt_active(env, el)) {
         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+        if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
+            DP_TBFLAG_A64(flags, FGT_ERET, 1);
+        }
     }
 
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
             if (op4 != 0) {
                 goto do_unallocated;
             }
+            if (s->fgt_eret) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
+                return;
+            }
             dst = tcg_temp_new_i64();
             tcg_gen_ld_i64(dst, cpu_env,
                            offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
             if (rn != 0x1f || op4 != 0x1f) {
                 goto do_unallocated;
             }
+            /* The FGT trap takes precedence over an auth trap. */
+            if (s->fgt_eret) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
+                return;
+            }
             dst = tcg_temp_new_i64();
             tcg_gen_ld_i64(dst, cpu_env,
                            offsetof(CPUARMState, elr_el[s->current_el]));
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
     dc->vl = (EX_TBFLAG_A64(tb_flags, VL) + 1) * 16;
-- 
2.34.1

Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Fuad Tabba <tabba@google.com>
Message-id: 20230130182459.3309057-22-peter.maydell@linaro.org
Message-id: 20230127175507.2895013-22-peter.maydell@linaro.org
---
 target/arm/cpu.h           |  1 +
 target/arm/translate.h     |  2 ++
 target/arm/helper.c        | 20 ++++++++++++++++++++
 target/arm/translate-a64.c |  9 ++++++++-
 target/arm/translate.c     | 12 +++++++++---
 5 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
 FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
 FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
 FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
+FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     bool fgt_active;
     /* True if fine-grained trap on ERET is enabled */
     bool fgt_eret;
+    /* True if fine-grained trap on SVC is enabled */
+    bool fgt_svc;
     /*
      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
      *  < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
     return arm_mmu_idx_el(env, arm_current_el(env));
 }
 
+static inline bool fgt_svc(CPUARMState *env, int el)
+{
+    /*
+     * Assuming fine-grained-traps are active, return true if we
+     * should be trapping on SVC instructions. Only AArch64 can
+     * trap on an SVC at EL1, but we don't need to special-case this
+     * because if this is AArch32 EL1 then arm_fgt_active() is false.
+     * We also know el is 0 or 1.
+     */
+    return el == 0 ?
+        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) :
+        FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1);
+}
+
 static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
                                            ARMMMUIdx mmu_idx,
                                            CPUARMTBFlags flags)
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
 
     if (arm_fgt_active(env, el)) {
         DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1);
+        if (fgt_svc(env, el)) {
+            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
+        }
     }
 
     if (env->uncached_cpsr & CPSR_IL) {
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
         if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) {
             DP_TBFLAG_A64(flags, FGT_ERET, 1);
         }
+        if (fgt_svc(env, el)) {
+            DP_TBFLAG_ANY(flags, FGT_SVC, 1);
+        }
     }
 
     if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
     int opc = extract32(insn, 21, 3);
     int op2_ll = extract32(insn, 0, 5);
     int imm16 = extract32(insn, 5, 16);
+    uint32_t syndrome;
 
     switch (opc) {
     case 0:
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
          */
         switch (op2_ll) {
         case 1:                                                     /* SVC */
+            syndrome = syn_aa64_svc(imm16);
+            if (s->fgt_svc) {
+                gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
+                break;
+            }
             gen_ss_advance(s);
-            gen_exception_insn(s, 4, EXCP_SWI, syn_aa64_svc(imm16));
+            gen_exception_insn(s, 4, EXCP_SWI, syndrome);
             break;
         case 2:                                                     /* HVC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
     dc->fgt_eret = EX_TBFLAG_A64(tb_flags, FGT_ERET);
     dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
     dc->sme_excp_el = EX_TBFLAG_A64(tb_flags, SMEEXC_EL);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
         (a->imm == semihost_imm)) {
         gen_exception_internal_insn(s, EXCP_SEMIHOST);
     } else {
-        gen_update_pc(s, curr_insn_len(s));
-        s->svc_imm = a->imm;
-        s->base.is_jmp = DISAS_SWI;
+        if (s->fgt_svc) {
+            uint32_t syndrome = syn_aa32_svc(a->imm, s->thumb);
+            gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
+        } else {
+            gen_update_pc(s, curr_insn_len(s));
+            s->svc_imm = a->imm;
+            s->base.is_jmp = DISAS_SWI;
+        }
     }
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
     dc->pstate_il = EX_TBFLAG_ANY(tb_flags, PSTATE__IL);
     dc->fgt_active = EX_TBFLAG_ANY(tb_flags, FGT_ACTIVE);
+    dc->fgt_svc = EX_TBFLAG_ANY(tb_flags, FGT_SVC);
 
     if (arm_feature(env, ARM_FEATURE_M)) {
         dc->vfp_enabled = 1;
-- 
2.34.1

FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents).  This trapping is independent of whether
fine-grained traps are enabled or not.

Implement these extra traps.  (We don't implement DBGDTR_EL0,
DBGDTRRX_EL0 and DBGDTRTX_EL0.)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
     return CP_ACCESS_OK;
 }
 
+/*
+ * Check for traps to Debug Comms Channel registers. If FEAT_FGT
+ * is implemented then these are controlled by MDCR_EL2.TDCC for
+ * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by
+ * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA.
+ */
+static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    int el = arm_current_el(env);
+    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
+    bool mdcr_el2_tda = (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) ||
+        (arm_hcr_el2_eff(env) & HCR_TGE);
+    bool mdcr_el2_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+                                          (mdcr_el2 & MDCR_TDCC);
+    bool mdcr_el3_tdcc = cpu_isar_feature(aa64_fgt, env_archcpu(env)) &&
+                                          (env->cp15.mdcr_el3 & MDCR_TDCC);
+
+    if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    if (el < 3 && ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) {
+        return CP_ACCESS_TRAP_EL3;
+    }
+    return CP_ACCESS_OK;
+}
+
 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
                         uint64_t value)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-      .access = PL0_R, .accessfn = access_tda,
+      .access = PL0_R, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0.
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "OSDTRTX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14,
       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * OSECCR_EL1 provides a mechanism for an operating system
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
      */
     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .accessfn = access_tda,
+      .access = PL1_RW, .accessfn = access_tdcc,
       .type = ARM_CP_NOP },
     /*
      * Dummy DBGCLAIM registers.
-- 
2.34.1

Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_ETS (Enhanced Translation Synchronization)
 - FEAT_EVT (Enhanced Virtualization Traps)
 - FEAT_FCMA (Floating-point complex number instructions)
+- FEAT_FGT (Fine-Grained Traps)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP16 (Half-precision floating-point data processing)
 - FEAT_FRINTTS (Floating-point to integer instructions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
     t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2);  /*  4k stage2 supported */
+    t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1);       /* FEAT_FGT */
     cpu->isar.id_aa64mmfr0 = t;
 
     t = cpu->isar.id_aa64mmfr1;
-- 
2.34.1