1 | First arm pullreq of the 8.0 series... | 1 | The following changes since commit 3214bec13d8d4c40f707d21d8350d04e4123ae97: |
---|---|---|---|
2 | 2 | ||
3 | The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873: | 3 | Merge tag 'migration-20250110-pull-request' of https://gitlab.com/farosas/qemu into staging (2025-01-10 13:39:19 -0500) |
4 | |||
5 | Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000) | ||
6 | 4 | ||
7 | are available in the Git repository at: | 5 | are available in the Git repository at: |
8 | 6 | ||
9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250113 |
10 | 8 | ||
11 | for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af: | 9 | for you to fetch changes up to 435d260e7ec5ff9c79e3e62f1d66ec82d2d691ae: |
12 | 10 | ||
13 | target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +0000) | 11 | docs/system/arm/virt: mention specific migration information (2025-01-13 12:35:35 +0000) |
14 | 12 | ||
15 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
16 | target-arm queue: | 14 | target-arm queue: |
17 | * hw/arm/virt: Add properties to allow more granular | 15 | * hw/arm_sysctl: fix extracting 31th bit of val |
18 | configuration of use of highmem space | 16 | * hw/misc: cast rpm to uint64_t |
19 | * target/arm: Add Cortex-A55 CPU | 17 | * tests/qtest/boot-serial-test: Improve ASM |
20 | * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement | 18 | * target/arm: Move minor arithmetic helpers out of helper.c |
21 | * Implement FEAT_EVT | 19 | * target/arm: change default pauth algorithm to impdef |
22 | * Some 3-phase-reset conversions for Arm GIC, SMMU | ||
23 | * hw/arm/boot: set initrd with #address-cells type in fdt | ||
24 | * align user-mode exposed ID registers with Linux | ||
25 | * hw/misc: Move some arm-related files from specific_ss into softmmu_ss | ||
26 | * Restrict arm_cpu_exec_interrupt() to TCG accelerator | ||
27 | 20 | ||
28 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
29 | Gavin Shan (7): | 22 | Anastasia Belova (1): |
30 | hw/arm/virt: Introduce virt_set_high_memmap() helper | 23 | hw/arm_sysctl: fix extracting 31th bit of val |
31 | hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap() | ||
32 | hw/arm/virt: Introduce variable region_base in virt_set_high_memmap() | ||
33 | hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper | ||
34 | hw/arm/virt: Improve high memory region address assignment | ||
35 | hw/arm/virt: Add 'compact-highmem' property | ||
36 | hw/arm/virt: Add properties to disable high memory regions | ||
37 | 24 | ||
38 | Luke Starrett (1): | 25 | Peter Maydell (2): |
39 | hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement | 26 | target/arm: Move minor arithmetic helpers out of helper.c |
27 | tests/tcg/aarch64: force qarma5 for pauth-3 test | ||
40 | 28 | ||
41 | Mihai Carabas (1): | 29 | Philippe Mathieu-Daudé (4): |
42 | hw/arm/virt: build SMBIOS 19 table | 30 | tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests |
31 | tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests | ||
32 | tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test | ||
33 | tests/qtest/boot-serial-test: Initialize PL011 Control register | ||
43 | 34 | ||
44 | Peter Maydell (15): | 35 | Pierrick Bouvier (3): |
45 | target/arm: Allow relevant HCR bits to be written for FEAT_EVT | 36 | target/arm: add new property to select pauth-qarma5 |
46 | target/arm: Implement HCR_EL2.TTLBIS traps | 37 | target/arm: change default pauth algorithm to impdef |
47 | target/arm: Implement HCR_EL2.TTLBOS traps | 38 | docs/system/arm/virt: mention specific migration information |
48 | target/arm: Implement HCR_EL2.TICAB,TOCU traps | ||
49 | target/arm: Implement HCR_EL2.TID4 traps | ||
50 | target/arm: Report FEAT_EVT for TCG '-cpu max' | ||
51 | hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset | ||
52 | hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset | ||
53 | hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset | ||
54 | hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset | ||
55 | hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset | ||
56 | hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset | ||
57 | hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset | ||
58 | hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset | ||
59 | hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset | ||
60 | 39 | ||
61 | Philippe Mathieu-Daudé (1): | 40 | Tigran Sogomonian (1): |
62 | target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator | 41 | hw/misc: cast rpm to uint64_t |
63 | 42 | ||
64 | Schspa Shi (1): | 43 | docs/system/arm/cpu-features.rst | 7 +- |
65 | hw/arm/boot: set initrd with #address-cells type in fdt | 44 | docs/system/arm/virt.rst | 4 + |
45 | docs/system/introduction.rst | 2 +- | ||
46 | target/arm/cpu.h | 4 + | ||
47 | hw/core/machine.c | 4 +- | ||
48 | hw/misc/arm_sysctl.c | 2 +- | ||
49 | hw/misc/npcm7xx_mft.c | 5 +- | ||
50 | target/arm/arm-qmp-cmds.c | 2 +- | ||
51 | target/arm/cpu.c | 2 + | ||
52 | target/arm/cpu64.c | 38 ++- | ||
53 | target/arm/helper.c | 285 ----------------------- | ||
54 | target/arm/tcg/arith_helper.c | 296 ++++++++++++++++++++++++ | ||
55 | tests/qtest/arm-cpu-features.c | 15 +- | ||
56 | tests/qtest/boot-serial-test.c | 23 +- | ||
57 | target/arm/{op_addsub.h => tcg/op_addsub.c.inc} | 0 | ||
58 | target/arm/tcg/meson.build | 1 + | ||
59 | tests/tcg/aarch64/Makefile.softmmu-target | 3 + | ||
60 | 17 files changed, 377 insertions(+), 316 deletions(-) | ||
61 | create mode 100644 target/arm/tcg/arith_helper.c | ||
62 | rename target/arm/{op_addsub.h => tcg/op_addsub.c.inc} (100%) | ||
66 | 63 | ||
67 | Thomas Huth (1): | ||
68 | hw/misc: Move some arm-related files from specific_ss into softmmu_ss | ||
69 | |||
70 | Timofey Kutergin (1): | ||
71 | target/arm: Add Cortex-A55 CPU | ||
72 | |||
73 | Zhuojia Shen (1): | ||
74 | target/arm: align exposed ID registers with Linux | ||
75 | |||
76 | docs/system/arm/emulation.rst | 1 + | ||
77 | docs/system/arm/virt.rst | 18 +++ | ||
78 | include/hw/arm/smmuv3.h | 2 +- | ||
79 | include/hw/arm/virt.h | 2 + | ||
80 | include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- | ||
81 | target/arm/cpu.h | 30 +++++ | ||
82 | target/arm/kvm-consts.h | 8 +- | ||
83 | hw/arm/boot.c | 10 +- | ||
84 | hw/arm/smmu-common.c | 7 +- | ||
85 | hw/arm/smmuv3.c | 12 +- | ||
86 | hw/arm/virt.c | 202 +++++++++++++++++++++++----- | ||
87 | hw/intc/arm_gic_common.c | 7 +- | ||
88 | hw/intc/arm_gic_kvm.c | 14 +- | ||
89 | hw/intc/arm_gicv3_common.c | 7 +- | ||
90 | hw/intc/arm_gicv3_dist.c | 4 +- | ||
91 | hw/intc/arm_gicv3_its.c | 14 +- | ||
92 | hw/intc/arm_gicv3_its_common.c | 7 +- | ||
93 | hw/intc/arm_gicv3_its_kvm.c | 14 +- | ||
94 | hw/intc/arm_gicv3_kvm.c | 14 +- | ||
95 | hw/misc/imx6_src.c | 2 +- | ||
96 | hw/misc/iotkit-sysctl.c | 1 - | ||
97 | target/arm/cpu.c | 5 +- | ||
98 | target/arm/cpu64.c | 70 ++++++++++ | ||
99 | target/arm/cpu_tcg.c | 1 + | ||
100 | target/arm/helper.c | 231 ++++++++++++++++++++++++--------- | ||
101 | hw/misc/meson.build | 11 +- | ||
102 | 26 files changed, 538 insertions(+), 158 deletions(-) | ||
103 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | This introduces virt_set_high_memmap() helper. The logic of high | ||
4 | memory region address assignment is moved to the helper. The intention | ||
5 | is to make the subsequent optimization for high memory region address | ||
6 | assignment easier. | ||
7 | |||
8 | No functional change intended. | ||
9 | |||
10 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
11 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
12 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
13 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
14 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
15 | Message-id: 20221029224307.138822-2-gshan@redhat.com | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | hw/arm/virt.c | 74 ++++++++++++++++++++++++++++----------------------- | ||
19 | 1 file changed, 41 insertions(+), 33 deletions(-) | ||
20 | |||
21 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/arm/virt.c | ||
24 | +++ b/hw/arm/virt.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | ||
26 | return arm_cpu_mp_affinity(idx, clustersz); | ||
27 | } | ||
28 | |||
29 | +static void virt_set_high_memmap(VirtMachineState *vms, | ||
30 | + hwaddr base, int pa_bits) | ||
31 | +{ | ||
32 | + int i; | ||
33 | + | ||
34 | + for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
35 | + hwaddr size = extended_memmap[i].size; | ||
36 | + bool fits; | ||
37 | + | ||
38 | + base = ROUND_UP(base, size); | ||
39 | + vms->memmap[i].base = base; | ||
40 | + vms->memmap[i].size = size; | ||
41 | + | ||
42 | + /* | ||
43 | + * Check each device to see if they fit in the PA space, | ||
44 | + * moving highest_gpa as we go. | ||
45 | + * | ||
46 | + * For each device that doesn't fit, disable it. | ||
47 | + */ | ||
48 | + fits = (base + size) <= BIT_ULL(pa_bits); | ||
49 | + if (fits) { | ||
50 | + vms->highest_gpa = base + size - 1; | ||
51 | + } | ||
52 | + | ||
53 | + switch (i) { | ||
54 | + case VIRT_HIGH_GIC_REDIST2: | ||
55 | + vms->highmem_redists &= fits; | ||
56 | + break; | ||
57 | + case VIRT_HIGH_PCIE_ECAM: | ||
58 | + vms->highmem_ecam &= fits; | ||
59 | + break; | ||
60 | + case VIRT_HIGH_PCIE_MMIO: | ||
61 | + vms->highmem_mmio &= fits; | ||
62 | + break; | ||
63 | + } | ||
64 | + | ||
65 | + base += size; | ||
66 | + } | ||
67 | +} | ||
68 | + | ||
69 | static void virt_set_memmap(VirtMachineState *vms, int pa_bits) | ||
70 | { | ||
71 | MachineState *ms = MACHINE(vms); | ||
72 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits) | ||
73 | /* We know for sure that at least the memory fits in the PA space */ | ||
74 | vms->highest_gpa = memtop - 1; | ||
75 | |||
76 | - for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
77 | - hwaddr size = extended_memmap[i].size; | ||
78 | - bool fits; | ||
79 | - | ||
80 | - base = ROUND_UP(base, size); | ||
81 | - vms->memmap[i].base = base; | ||
82 | - vms->memmap[i].size = size; | ||
83 | - | ||
84 | - /* | ||
85 | - * Check each device to see if they fit in the PA space, | ||
86 | - * moving highest_gpa as we go. | ||
87 | - * | ||
88 | - * For each device that doesn't fit, disable it. | ||
89 | - */ | ||
90 | - fits = (base + size) <= BIT_ULL(pa_bits); | ||
91 | - if (fits) { | ||
92 | - vms->highest_gpa = base + size - 1; | ||
93 | - } | ||
94 | - | ||
95 | - switch (i) { | ||
96 | - case VIRT_HIGH_GIC_REDIST2: | ||
97 | - vms->highmem_redists &= fits; | ||
98 | - break; | ||
99 | - case VIRT_HIGH_PCIE_ECAM: | ||
100 | - vms->highmem_ecam &= fits; | ||
101 | - break; | ||
102 | - case VIRT_HIGH_PCIE_MMIO: | ||
103 | - vms->highmem_mmio &= fits; | ||
104 | - break; | ||
105 | - } | ||
106 | - | ||
107 | - base += size; | ||
108 | - } | ||
109 | + virt_set_high_memmap(vms, base, pa_bits); | ||
110 | |||
111 | if (device_memory_size > 0) { | ||
112 | ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); | ||
113 | -- | ||
114 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | This renames variable 'size' to 'region_size' in virt_set_high_memmap(). | ||
4 | Its counterpart ('region_base') will be introduced in next patch. | ||
5 | |||
6 | No functional change intended. | ||
7 | |||
8 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
9 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
11 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
12 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
13 | Message-id: 20221029224307.138822-3-gshan@redhat.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/arm/virt.c | 15 ++++++++------- | ||
17 | 1 file changed, 8 insertions(+), 7 deletions(-) | ||
18 | |||
19 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/arm/virt.c | ||
22 | +++ b/hw/arm/virt.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | ||
24 | static void virt_set_high_memmap(VirtMachineState *vms, | ||
25 | hwaddr base, int pa_bits) | ||
26 | { | ||
27 | + hwaddr region_size; | ||
28 | + bool fits; | ||
29 | int i; | ||
30 | |||
31 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
32 | - hwaddr size = extended_memmap[i].size; | ||
33 | - bool fits; | ||
34 | + region_size = extended_memmap[i].size; | ||
35 | |||
36 | - base = ROUND_UP(base, size); | ||
37 | + base = ROUND_UP(base, region_size); | ||
38 | vms->memmap[i].base = base; | ||
39 | - vms->memmap[i].size = size; | ||
40 | + vms->memmap[i].size = region_size; | ||
41 | |||
42 | /* | ||
43 | * Check each device to see if they fit in the PA space, | ||
44 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
45 | * | ||
46 | * For each device that doesn't fit, disable it. | ||
47 | */ | ||
48 | - fits = (base + size) <= BIT_ULL(pa_bits); | ||
49 | + fits = (base + region_size) <= BIT_ULL(pa_bits); | ||
50 | if (fits) { | ||
51 | - vms->highest_gpa = base + size - 1; | ||
52 | + vms->highest_gpa = base + region_size - 1; | ||
53 | } | ||
54 | |||
55 | switch (i) { | ||
56 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
57 | break; | ||
58 | } | ||
59 | |||
60 | - base += size; | ||
61 | + base += region_size; | ||
62 | } | ||
63 | } | ||
64 | |||
65 | -- | ||
66 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | This introduces variable 'region_base' for the base address of the | ||
4 | specific high memory region. It's the preparatory work to optimize | ||
5 | high memory region address assignment. | ||
6 | |||
7 | No functional change intended. | ||
8 | |||
9 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
12 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
13 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
14 | Message-id: 20221029224307.138822-4-gshan@redhat.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/arm/virt.c | 12 ++++++------ | ||
18 | 1 file changed, 6 insertions(+), 6 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/virt.c | ||
23 | +++ b/hw/arm/virt.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | ||
25 | static void virt_set_high_memmap(VirtMachineState *vms, | ||
26 | hwaddr base, int pa_bits) | ||
27 | { | ||
28 | - hwaddr region_size; | ||
29 | + hwaddr region_base, region_size; | ||
30 | bool fits; | ||
31 | int i; | ||
32 | |||
33 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
34 | + region_base = ROUND_UP(base, extended_memmap[i].size); | ||
35 | region_size = extended_memmap[i].size; | ||
36 | |||
37 | - base = ROUND_UP(base, region_size); | ||
38 | - vms->memmap[i].base = base; | ||
39 | + vms->memmap[i].base = region_base; | ||
40 | vms->memmap[i].size = region_size; | ||
41 | |||
42 | /* | ||
43 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
44 | * | ||
45 | * For each device that doesn't fit, disable it. | ||
46 | */ | ||
47 | - fits = (base + region_size) <= BIT_ULL(pa_bits); | ||
48 | + fits = (region_base + region_size) <= BIT_ULL(pa_bits); | ||
49 | if (fits) { | ||
50 | - vms->highest_gpa = base + region_size - 1; | ||
51 | + vms->highest_gpa = region_base + region_size - 1; | ||
52 | } | ||
53 | |||
54 | switch (i) { | ||
55 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
56 | break; | ||
57 | } | ||
58 | |||
59 | - base += region_size; | ||
60 | + base = region_base + region_size; | ||
61 | } | ||
62 | } | ||
63 | |||
64 | -- | ||
65 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | This introduces virt_get_high_memmap_enabled() helper, which returns | ||
4 | the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will | ||
5 | be used in the subsequent patches. | ||
6 | |||
7 | No functional change intended. | ||
8 | |||
9 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
12 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
13 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
14 | Message-id: 20221029224307.138822-5-gshan@redhat.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/arm/virt.c | 32 +++++++++++++++++++------------- | ||
18 | 1 file changed, 19 insertions(+), 13 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/virt.c | ||
23 | +++ b/hw/arm/virt.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | ||
25 | return arm_cpu_mp_affinity(idx, clustersz); | ||
26 | } | ||
27 | |||
28 | +static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, | ||
29 | + int index) | ||
30 | +{ | ||
31 | + bool *enabled_array[] = { | ||
32 | + &vms->highmem_redists, | ||
33 | + &vms->highmem_ecam, | ||
34 | + &vms->highmem_mmio, | ||
35 | + }; | ||
36 | + | ||
37 | + assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST == | ||
38 | + ARRAY_SIZE(enabled_array)); | ||
39 | + assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array)); | ||
40 | + | ||
41 | + return enabled_array[index - VIRT_LOWMEMMAP_LAST]; | ||
42 | +} | ||
43 | + | ||
44 | static void virt_set_high_memmap(VirtMachineState *vms, | ||
45 | hwaddr base, int pa_bits) | ||
46 | { | ||
47 | hwaddr region_base, region_size; | ||
48 | - bool fits; | ||
49 | + bool *region_enabled, fits; | ||
50 | int i; | ||
51 | |||
52 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
53 | + region_enabled = virt_get_high_memmap_enabled(vms, i); | ||
54 | region_base = ROUND_UP(base, extended_memmap[i].size); | ||
55 | region_size = extended_memmap[i].size; | ||
56 | |||
57 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
58 | vms->highest_gpa = region_base + region_size - 1; | ||
59 | } | ||
60 | |||
61 | - switch (i) { | ||
62 | - case VIRT_HIGH_GIC_REDIST2: | ||
63 | - vms->highmem_redists &= fits; | ||
64 | - break; | ||
65 | - case VIRT_HIGH_PCIE_ECAM: | ||
66 | - vms->highmem_ecam &= fits; | ||
67 | - break; | ||
68 | - case VIRT_HIGH_PCIE_MMIO: | ||
69 | - vms->highmem_mmio &= fits; | ||
70 | - break; | ||
71 | - } | ||
72 | - | ||
73 | + *region_enabled &= fits; | ||
74 | base = region_base + region_size; | ||
75 | } | ||
76 | } | ||
77 | -- | ||
78 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | There are three high memory regions, which are VIRT_HIGH_REDIST2, | ||
4 | VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses | ||
5 | are floating on highest RAM address. However, they can be disabled | ||
6 | in several cases. | ||
7 | |||
8 | (1) One specific high memory region is likely to be disabled by | ||
9 | code by toggling vms->highmem_{redists, ecam, mmio}. | ||
10 | |||
11 | (2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is | ||
12 | 'virt-2.12' or ealier than it. | ||
13 | |||
14 | (3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded | ||
15 | on 32-bits system. | ||
16 | |||
17 | (4) One specific high memory region is disabled when it breaks the | ||
18 | PA space limit. | ||
19 | |||
20 | The current implementation of virt_set_{memmap, high_memmap}() isn't | ||
21 | optimized because the high memory region's PA space is always reserved, | ||
22 | regardless of whatever the actual state in the corresponding | ||
23 | vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and | ||
24 | 'vms->highest_gpa' are always increased for case (1), (2) and (3). | ||
25 | It's unnecessary since the assigned PA space for the disabled high | ||
26 | memory region won't be used afterwards. | ||
27 | |||
28 | Improve the address assignment for those three high memory region by | ||
29 | skipping the address assignment for one specific high memory region if | ||
30 | it has been disabled in case (1), (2) and (3). The memory layout may | ||
31 | be changed after the improvement is applied, which leads to potential | ||
32 | migration breakage. So 'vms->highmem_compact' is added to control if | ||
33 | the improvement should be applied. For now, 'vms->highmem_compact' is | ||
34 | set to false, meaning that we don't have memory layout change until it | ||
35 | becomes configurable through property 'compact-highmem' in next patch. | ||
36 | |||
37 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
38 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
39 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
40 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
41 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
42 | Message-id: 20221029224307.138822-6-gshan@redhat.com | ||
43 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
44 | --- | ||
45 | include/hw/arm/virt.h | 1 + | ||
46 | hw/arm/virt.c | 15 ++++++++++----- | ||
47 | 2 files changed, 11 insertions(+), 5 deletions(-) | ||
48 | |||
49 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/include/hw/arm/virt.h | ||
52 | +++ b/include/hw/arm/virt.h | ||
53 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { | ||
54 | PFlashCFI01 *flash[2]; | ||
55 | bool secure; | ||
56 | bool highmem; | ||
57 | + bool highmem_compact; | ||
58 | bool highmem_ecam; | ||
59 | bool highmem_mmio; | ||
60 | bool highmem_redists; | ||
61 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/arm/virt.c | ||
64 | +++ b/hw/arm/virt.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms, | ||
66 | vms->memmap[i].size = region_size; | ||
67 | |||
68 | /* | ||
69 | - * Check each device to see if they fit in the PA space, | ||
70 | - * moving highest_gpa as we go. | ||
71 | + * Check each device to see if it fits in the PA space, | ||
72 | + * moving highest_gpa as we go. For compatibility, move | ||
73 | + * highest_gpa for disabled fitting devices as well, if | ||
74 | + * the compact layout has been disabled. | ||
75 | * | ||
76 | * For each device that doesn't fit, disable it. | ||
77 | */ | ||
78 | fits = (region_base + region_size) <= BIT_ULL(pa_bits); | ||
79 | - if (fits) { | ||
80 | - vms->highest_gpa = region_base + region_size - 1; | ||
81 | + *region_enabled &= fits; | ||
82 | + if (vms->highmem_compact && !*region_enabled) { | ||
83 | + continue; | ||
84 | } | ||
85 | |||
86 | - *region_enabled &= fits; | ||
87 | base = region_base + region_size; | ||
88 | + if (fits) { | ||
89 | + vms->highest_gpa = base - 1; | ||
90 | + } | ||
91 | } | ||
92 | } | ||
93 | |||
94 | -- | ||
95 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Anastasia Belova <abelova@astralinux.ru> |
---|---|---|---|
2 | 2 | ||
3 | The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as | 3 | 1 << 31 is casted to uint64_t while bitwise and with val. |
4 | poisoned in common code, so the files that include this header have to | 4 | So this value may become 0xffffffff80000000 but only |
5 | be added to specific_ss and recompiled for each, qemu-system-arm and | 5 | 31th "start" bit is required. |
6 | qemu-system-aarch64. However, since the kvm headers are only optionally | ||
7 | used in kvm-constants.h for some sanity checks, we can additionally | ||
8 | check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro, | ||
9 | so kvm-constants.h can also be used from "common" files (without the | ||
10 | sanity checks - which should be OK since they are still done from other | ||
11 | target-specific files instead). This way, and by adjusting some other | ||
12 | include statements in the related files here and there, we can move some | ||
13 | files from specific_ss into softmmu_ss, so that they only need to be | ||
14 | compiled once during the build process. | ||
15 | 6 | ||
16 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 7 | This is not possible in practice because the MemoryRegionOps |
17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | uses the default max access size of 4 bytes and so none |
18 | Message-id: 20221202154023.293614-1-thuth@redhat.com | 9 | of the upper bytes of val will be set, but the bitfield |
10 | extract API is clearer anyway. | ||
11 | |||
12 | Use the bitfield extract() API instead. | ||
13 | |||
14 | Found by Linux Verification Center (linuxtesting.org) with SVACE. | ||
15 | |||
16 | Signed-off-by: Anastasia Belova <abelova@astralinux.ru> | ||
17 | Message-id: 20241220125429.7552-1-abelova@astralinux.ru | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | [PMM: add clarification to commit message] | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 21 | --- |
21 | include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +- | 22 | hw/misc/arm_sysctl.c | 2 +- |
22 | target/arm/kvm-consts.h | 8 ++++---- | 23 | 1 file changed, 1 insertion(+), 1 deletion(-) |
23 | hw/misc/imx6_src.c | 2 +- | ||
24 | hw/misc/iotkit-sysctl.c | 1 - | ||
25 | hw/misc/meson.build | 11 +++++------ | ||
26 | 5 files changed, 11 insertions(+), 13 deletions(-) | ||
27 | 24 | ||
28 | diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 25 | diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c |
29 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 27 | --- a/hw/misc/arm_sysctl.c |
31 | +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 28 | +++ b/hw/misc/arm_sysctl.c |
32 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ static void arm_sysctl_write(void *opaque, hwaddr offset, |
33 | 30 | * as zero. | |
34 | #include "hw/sysbus.h" | 31 | */ |
35 | #include "hw/register.h" | 32 | s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31)); |
36 | -#include "target/arm/cpu.h" | 33 | - if (val & (1 << 31)) { |
37 | +#include "target/arm/cpu-qom.h" | 34 | + if (extract64(val, 31, 1)) { |
38 | 35 | /* Start bit set -- actually do something */ | |
39 | #define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" | 36 | unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4); |
40 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL) | 37 | unsigned int function = extract32(s->sys_cfgctrl, 20, 6); |
41 | diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/kvm-consts.h | ||
44 | +++ b/target/arm/kvm-consts.h | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | #ifndef ARM_KVM_CONSTS_H | ||
47 | #define ARM_KVM_CONSTS_H | ||
48 | |||
49 | +#ifdef NEED_CPU_H | ||
50 | #ifdef CONFIG_KVM | ||
51 | #include <linux/kvm.h> | ||
52 | #include <linux/psci.h> | ||
53 | - | ||
54 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y) | ||
55 | +#endif | ||
56 | +#endif | ||
57 | |||
58 | -#else | ||
59 | - | ||
60 | +#ifndef MISMATCH_CHECK | ||
61 | #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0) | ||
62 | - | ||
63 | #endif | ||
64 | |||
65 | #define CP_REG_SIZE_SHIFT 52 | ||
66 | diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/hw/misc/imx6_src.c | ||
69 | +++ b/hw/misc/imx6_src.c | ||
70 | @@ -XXX,XX +XXX,XX @@ | ||
71 | #include "qemu/log.h" | ||
72 | #include "qemu/main-loop.h" | ||
73 | #include "qemu/module.h" | ||
74 | -#include "arm-powerctl.h" | ||
75 | +#include "target/arm/arm-powerctl.h" | ||
76 | #include "hw/core/cpu.h" | ||
77 | |||
78 | #ifndef DEBUG_IMX6_SRC | ||
79 | diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/hw/misc/iotkit-sysctl.c | ||
82 | +++ b/hw/misc/iotkit-sysctl.c | ||
83 | @@ -XXX,XX +XXX,XX @@ | ||
84 | #include "hw/qdev-properties.h" | ||
85 | #include "hw/arm/armsse-version.h" | ||
86 | #include "target/arm/arm-powerctl.h" | ||
87 | -#include "target/arm/cpu.h" | ||
88 | |||
89 | REG32(SECDBGSTAT, 0x0) | ||
90 | REG32(SECDBGSET, 0x4) | ||
91 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/hw/misc/meson.build | ||
94 | +++ b/hw/misc/meson.build | ||
95 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files( | ||
96 | 'imx25_ccm.c', | ||
97 | 'imx31_ccm.c', | ||
98 | 'imx6_ccm.c', | ||
99 | + 'imx6_src.c', | ||
100 | 'imx6ul_ccm.c', | ||
101 | 'imx7_ccm.c', | ||
102 | 'imx7_gpr.c', | ||
103 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | ||
104 | )) | ||
105 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
106 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) | ||
107 | -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | ||
108 | -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | ||
109 | +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) | ||
110 | +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) | ||
111 | specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) | ||
112 | softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( | ||
113 | 'xlnx-versal-xramc.c', | ||
114 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c')) | ||
115 | softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c')) | ||
116 | softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c')) | ||
117 | softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c')) | ||
118 | +softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c')) | ||
119 | softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c')) | ||
120 | softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c')) | ||
121 | softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c')) | ||
122 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c')) | ||
123 | |||
124 | specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c')) | ||
125 | |||
126 | -specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c')) | ||
127 | -specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c')) | ||
128 | - | ||
129 | specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c')) | ||
130 | |||
131 | specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c')) | ||
132 | specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) | ||
133 | |||
134 | -specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) | ||
135 | +softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) | ||
136 | |||
137 | # HPPA devices | ||
138 | softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c')) | ||
139 | -- | 38 | -- |
140 | 2.25.1 | 39 | 2.34.1 |
141 | |||
142 | diff view generated by jsdifflib |
1 | From: Schspa Shi <schspa@gmail.com> | 1 | From: Tigran Sogomonian <tsogomonian@astralinux.ru> |
---|---|---|---|
2 | 2 | ||
3 | We use 32bit value for linux,initrd-[start/end], when we have | 3 | The value of an arithmetic expression |
4 | loader_start > 4GB, there will be a wrong initrd_start passed | 4 | 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject |
5 | to the kernel, and the kernel will report the following warning. | 5 | to overflow because its operands are not cast to |
6 | a larger data type before performing arithmetic. Thus, need | ||
7 | to cast rpm to uint64_t. | ||
6 | 8 | ||
7 | [ 0.000000] ------------[ cut here ]------------ | 9 | Found by Linux Verification Center (linuxtesting.org) with SVACE. |
8 | [ 0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ... | ||
9 | [ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244 | ||
10 | [ 0.000000] Modules linked in: | ||
11 | [ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 6.1.0-rc3-13250-g30a0b95b1335-dirty #28 | ||
12 | [ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT) | ||
13 | [ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) | ||
14 | [ 0.000000] pc : arm64_memblock_init+0x158/0x244 | ||
15 | [ 0.000000] lr : arm64_memblock_init+0x158/0x244 | ||
16 | [ 0.000000] sp : ffff800009273df0 | ||
17 | [ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000 | ||
18 | [ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000 | ||
19 | [ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000 | ||
20 | [ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020 | ||
21 | [ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261 | ||
22 | [ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000 | ||
23 | [ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000 | ||
24 | [ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69 | ||
25 | [ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88 | ||
26 | [ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056 | ||
27 | [ 0.000000] Call trace: | ||
28 | [ 0.000000] arm64_memblock_init+0x158/0x244 | ||
29 | [ 0.000000] setup_arch+0x164/0x1cc | ||
30 | [ 0.000000] start_kernel+0x94/0x4ac | ||
31 | [ 0.000000] __primary_switched+0xb4/0xbc | ||
32 | [ 0.000000] ---[ end trace 0000000000000000 ]--- | ||
33 | [ 0.000000] Zone ranges: | ||
34 | [ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff] | ||
35 | 10 | ||
36 | This doesn't affect any machine types we currently support, because | 11 | Signed-off-by: Tigran Sogomonian <tsogomonian@astralinux.ru> |
37 | for all of our machine types the RAM starts well below the 4GB | 12 | Reviewed-by: Patrick Leis <venture@google.com> |
38 | mark, but it does demonstrate that we're not currently writing | 13 | Reviewed-by: Hao Wu <wuhaotsh@google.com> |
39 | the device-tree properties quite as intended. | 14 | Message-id: 20241226130311.1349-1-tsogomonian@astralinux.ru |
40 | |||
41 | To fix it, we can change it to write these values to the dtb using a | ||
42 | type width matching #address-cells. This is the intended size for | ||
43 | these dtb properties, and is how u-boot, for instance, writes them, | ||
44 | although in practice the Linux kernel will cope with them being any | ||
45 | width as long as they're big enough to fit the value. | ||
46 | |||
47 | Signed-off-by: Schspa Shi <schspa@gmail.com> | ||
48 | Message-id: 20221129160724.75667-1-schspa@gmail.com | ||
49 | [PMM: tweaked commit message] | ||
50 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
51 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
52 | --- | 16 | --- |
53 | hw/arm/boot.c | 10 ++++++---- | 17 | hw/misc/npcm7xx_mft.c | 5 +++-- |
54 | 1 file changed, 6 insertions(+), 4 deletions(-) | 18 | 1 file changed, 3 insertions(+), 2 deletions(-) |
55 | 19 | ||
56 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 20 | diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c |
57 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
58 | --- a/hw/arm/boot.c | 22 | --- a/hw/misc/npcm7xx_mft.c |
59 | +++ b/hw/arm/boot.c | 23 | +++ b/hw/misc/npcm7xx_mft.c |
60 | @@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | 24 | @@ -XXX,XX +XXX,XX @@ static NPCM7xxMFTCaptureState npcm7xx_mft_compute_cnt( |
25 | * RPM = revolution/min. The time for one revlution (in ns) is | ||
26 | * MINUTE_TO_NANOSECOND / RPM. | ||
27 | */ | ||
28 | - count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) / | ||
29 | - (rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION)); | ||
30 | + count = clock_ns_to_ticks(clock, | ||
31 | + (uint64_t)(60 * NANOSECONDS_PER_SECOND) / | ||
32 | + ((uint64_t)rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION)); | ||
61 | } | 33 | } |
62 | 34 | ||
63 | if (binfo->initrd_size) { | 35 | if (count > NPCM7XX_MFT_MAX_CNT) { |
64 | - rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", | ||
65 | - binfo->initrd_start); | ||
66 | + rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start", | ||
67 | + acells, binfo->initrd_start); | ||
68 | if (rc < 0) { | ||
69 | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); | ||
70 | goto fail; | ||
71 | } | ||
72 | |||
73 | - rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", | ||
74 | - binfo->initrd_start + binfo->initrd_size); | ||
75 | + rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end", | ||
76 | + acells, | ||
77 | + binfo->initrd_start + | ||
78 | + binfo->initrd_size); | ||
79 | if (rc < 0) { | ||
80 | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); | ||
81 | goto fail; | ||
82 | -- | 36 | -- |
83 | 2.25.1 | 37 | 2.34.1 | diff view generated by jsdifflib |
1 | Convert the TYPE_KVM_ARM_ITS device to 3-phase reset. | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Re-indent ASM comments adding the 'loop:' label. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++----- | 10 | tests/qtest/boot-serial-test.c | 18 +++++++++--------- |
9 | 1 file changed, 9 insertions(+), 5 deletions(-) | 11 | 1 file changed, 9 insertions(+), 9 deletions(-) |
10 | 12 | ||
11 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | 13 | diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c |
12 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/arm_gicv3_its_kvm.c | 15 | --- a/tests/qtest/boot-serial-test.c |
14 | +++ b/hw/intc/arm_gicv3_its_kvm.c | 16 | +++ b/tests/qtest/boot-serial-test.c |
15 | @@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass, | 17 | @@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = { |
16 | |||
17 | struct KVMARMITSClass { | ||
18 | GICv3ITSCommonClass parent_class; | ||
19 | - void (*parent_reset)(DeviceState *dev); | ||
20 | + ResettablePhases parent_phases; | ||
21 | }; | 18 | }; |
22 | 19 | ||
23 | 20 | static const uint8_t bios_raspi2[] = { | |
24 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s) | 21 | - 0x08, 0x30, 0x9f, 0xe5, /* ldr r3,[pc,#8] Get base */ |
25 | GITS_CTLR, &s->ctlr, true, &error_abort); | 22 | - 0x54, 0x20, 0xa0, 0xe3, /* mov r2,#'T' */ |
26 | } | 23 | - 0x00, 0x20, 0xc3, 0xe5, /* strb r2,[r3] */ |
27 | 24 | - 0xfb, 0xff, 0xff, 0xea, /* b loop */ | |
28 | -static void kvm_arm_its_reset(DeviceState *dev) | 25 | - 0x00, 0x10, 0x20, 0x3f, /* 0x3f201000 = UART0 base addr */ |
29 | +static void kvm_arm_its_reset_hold(Object *obj) | 26 | + 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */ |
30 | { | 27 | + 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ |
31 | - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | 28 | + 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */ |
32 | + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | 29 | + 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */ |
33 | KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s); | 30 | + 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ |
34 | int i; | 31 | }; |
35 | 32 | ||
36 | - c->parent_reset(dev); | 33 | static const uint8_t kernel_aarch64[] = { |
37 | + if (c->parent_phases.hold) { | 34 | - 0x81, 0x0a, 0x80, 0x52, /* mov w1, #0x54 */ |
38 | + c->parent_phases.hold(obj); | 35 | - 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 */ |
39 | + } | 36 | - 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] */ |
40 | 37 | - 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ | |
41 | if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, | 38 | + 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */ |
42 | KVM_DEV_ARM_ITS_CTRL_RESET)) { | 39 | + 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ |
43 | @@ -XXX,XX +XXX,XX @@ static Property kvm_arm_its_props[] = { | 40 | + 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */ |
44 | static void kvm_arm_its_class_init(ObjectClass *klass, void *data) | 41 | + 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ |
45 | { | 42 | }; |
46 | DeviceClass *dc = DEVICE_CLASS(klass); | 43 | |
47 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | 44 | static const uint8_t kernel_nrf51[] = { |
48 | GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); | ||
49 | KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass); | ||
50 | |||
51 | dc->realize = kvm_arm_its_realize; | ||
52 | device_class_set_props(dc, kvm_arm_its_props); | ||
53 | - device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset); | ||
54 | + resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL, | ||
55 | + &ic->parent_phases); | ||
56 | icc->send_msi = kvm_its_send_msi; | ||
57 | icc->pre_save = kvm_arm_its_pre_save; | ||
58 | icc->post_load = kvm_arm_its_post_load; | ||
59 | -- | 45 | -- |
60 | 2.25.1 | 46 | 2.34.1 |
61 | 47 | ||
62 | 48 | diff view generated by jsdifflib |
1 | Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset. | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Since registers are not modified, we don't need | ||
4 | to refill their values. Directly jump to the previous | ||
5 | store instruction to keep filling the TXDAT register. | ||
6 | |||
7 | The equivalent C code remains: | ||
8 | |||
9 | while (true) { | ||
10 | *UART_DATA = 'T'; | ||
11 | } | ||
12 | |||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org | ||
7 | --- | 17 | --- |
8 | hw/intc/arm_gicv3_its.c | 14 +++++++++----- | 18 | tests/qtest/boot-serial-test.c | 12 ++++++------ |
9 | 1 file changed, 9 insertions(+), 5 deletions(-) | 19 | 1 file changed, 6 insertions(+), 6 deletions(-) |
10 | 20 | ||
11 | diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c | 21 | diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c |
12 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/arm_gicv3_its.c | 23 | --- a/tests/qtest/boot-serial-test.c |
14 | +++ b/hw/intc/arm_gicv3_its.c | 24 | +++ b/tests/qtest/boot-serial-test.c |
15 | @@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass, | 25 | @@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = { |
16 | |||
17 | struct GICv3ITSClass { | ||
18 | GICv3ITSCommonClass parent_class; | ||
19 | - void (*parent_reset)(DeviceState *dev); | ||
20 | + ResettablePhases parent_phases; | ||
21 | }; | 26 | }; |
22 | 27 | ||
23 | /* | 28 | static const uint8_t bios_raspi2[] = { |
24 | @@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) | 29 | - 0x08, 0x30, 0x9f, 0xe5, /* loop: ldr r3, [pc, #8] Get &UART0 */ |
25 | } | 30 | + 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */ |
26 | } | 31 | 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ |
27 | 32 | - 0x00, 0x20, 0xc3, 0xe5, /* strb r2, [r3] *TXDAT = 'T' */ | |
28 | -static void gicv3_its_reset(DeviceState *dev) | 33 | - 0xfb, 0xff, 0xff, 0xea, /* b -12 (loop) */ |
29 | +static void gicv3_its_reset_hold(Object *obj) | 34 | + 0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */ |
30 | { | 35 | + 0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */ |
31 | - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | 36 | 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ |
32 | + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | 37 | }; |
33 | GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s); | 38 | |
34 | 39 | static const uint8_t kernel_aarch64[] = { | |
35 | - c->parent_reset(dev); | 40 | - 0x81, 0x0a, 0x80, 0x52, /* loop: mov w1, #'T' */ |
36 | + if (c->parent_phases.hold) { | 41 | + 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ |
37 | + c->parent_phases.hold(obj); | 42 | 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ |
38 | + } | 43 | - 0x41, 0x00, 0x00, 0x39, /* strb w1, [x2] *TXDAT = 'T' */ |
39 | 44 | - 0xfd, 0xff, 0xff, 0x17, /* b -12 (loop) */ | |
40 | /* Quiescent bit reset to 1 */ | 45 | + 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ |
41 | s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1); | 46 | + 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ |
42 | @@ -XXX,XX +XXX,XX @@ static Property gicv3_its_props[] = { | 47 | }; |
43 | static void gicv3_its_class_init(ObjectClass *klass, void *data) | 48 | |
44 | { | 49 | static const uint8_t kernel_nrf51[] = { |
45 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
46 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
47 | GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass); | ||
48 | GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass); | ||
49 | |||
50 | dc->realize = gicv3_arm_its_realize; | ||
51 | device_class_set_props(dc, gicv3_its_props); | ||
52 | - device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset); | ||
53 | + resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL, | ||
54 | + &ic->parent_phases); | ||
55 | icc->post_load = gicv3_its_post_load; | ||
56 | } | ||
57 | |||
58 | -- | 50 | -- |
59 | 2.25.1 | 51 | 2.34.1 |
60 | 52 | ||
61 | 53 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When building with --disable-tcg on Darwin we get: | 3 | In the next commit we are going to use a different value |
4 | 4 | for the $w1 register, maintaining the same $x2 value. In | |
5 | target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps' | 5 | order to keep the next commit trivial to review, set $x2 |
6 | cc->tcg_ops->do_interrupt(cs); | 6 | before $w1. |
7 | ~~~~~~~~~~~^ | ||
8 | |||
9 | Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt() | ||
10 | handler to sysemu") limited this block to system emulation, | ||
11 | but neglected to also limit it to TCG. | ||
12 | 7 | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | 10 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
15 | Message-id: 20221209110823.59495-1-philmd@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 12 | --- |
18 | target/arm/cpu.c | 5 +++-- | 13 | tests/qtest/boot-serial-test.c | 2 +- |
19 | 1 file changed, 3 insertions(+), 2 deletions(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
20 | 15 | ||
21 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 16 | diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/cpu.c | 18 | --- a/tests/qtest/boot-serial-test.c |
24 | +++ b/target/arm/cpu.c | 19 | +++ b/tests/qtest/boot-serial-test.c |
25 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev) | 20 | @@ -XXX,XX +XXX,XX @@ static const uint8_t bios_raspi2[] = { |
26 | arm_rebuild_hflags(env); | 21 | }; |
27 | } | 22 | |
28 | 23 | static const uint8_t kernel_aarch64[] = { | |
29 | -#ifndef CONFIG_USER_ONLY | 24 | - 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ |
30 | +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) | 25 | 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ |
31 | 26 | + 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ | |
32 | static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, | 27 | 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ |
33 | unsigned int target_el, | 28 | 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ |
34 | @@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | 29 | }; |
35 | cc->tcg_ops->do_interrupt(cs); | ||
36 | return true; | ||
37 | } | ||
38 | -#endif /* !CONFIG_USER_ONLY */ | ||
39 | + | ||
40 | +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ | ||
41 | |||
42 | void arm_cpu_update_virq(ARMCPU *cpu) | ||
43 | { | ||
44 | -- | 30 | -- |
45 | 2.25.1 | 31 | 2.34.1 |
46 | 32 | ||
47 | 33 | diff view generated by jsdifflib |
1 | Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset. | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The tests using the PL011 UART of the virt and raspi machines | ||
4 | weren't properly enabling the UART and its transmitter previous | ||
5 | to sending characters. Follow the PL011 manual initialization | ||
6 | recommendation by setting the proper bits of the control register. | ||
7 | |||
8 | Update the ASM code prefixing: | ||
9 | |||
10 | *UART_CTRL = UART_ENABLE | TX_ENABLE; | ||
11 | |||
12 | to: | ||
13 | |||
14 | while (true) { | ||
15 | *UART_DATA = 'T'; | ||
16 | } | ||
17 | |||
18 | Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using | ||
19 | disabled transmitter") incomplete PL011 initialization can be | ||
20 | logged using the '-d guest_errors' command line option. | ||
21 | |||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org | ||
7 | --- | 25 | --- |
8 | hw/intc/arm_gicv3_kvm.c | 14 +++++++++----- | 26 | tests/qtest/boot-serial-test.c | 7 ++++++- |
9 | 1 file changed, 9 insertions(+), 5 deletions(-) | 27 | 1 file changed, 6 insertions(+), 1 deletion(-) |
10 | 28 | ||
11 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 29 | diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c |
12 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/intc/arm_gicv3_kvm.c | 31 | --- a/tests/qtest/boot-serial-test.c |
14 | +++ b/hw/intc/arm_gicv3_kvm.c | 32 | +++ b/tests/qtest/boot-serial-test.c |
15 | @@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class, | 33 | @@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_plml605[] = { |
16 | struct KVMARMGICv3Class { | ||
17 | ARMGICv3CommonClass parent_class; | ||
18 | DeviceRealize parent_realize; | ||
19 | - void (*parent_reset)(DeviceState *dev); | ||
20 | + ResettablePhases parent_phases; | ||
21 | }; | 34 | }; |
22 | 35 | ||
23 | static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level) | 36 | static const uint8_t bios_raspi2[] = { |
24 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) | 37 | - 0x08, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #8] Get &UART0 */ |
25 | c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS]; | 38 | + 0x10, 0x30, 0x9f, 0xe5, /* ldr r3, [pc, #16] Get &UART0 */ |
26 | } | 39 | + 0x10, 0x20, 0x9f, 0xe5, /* ldr r2, [pc, #16] Get &CR */ |
27 | 40 | + 0xb0, 0x23, 0xc3, 0xe1, /* strh r2, [r3, #48] Set CR */ | |
28 | -static void kvm_arm_gicv3_reset(DeviceState *dev) | 41 | 0x54, 0x20, 0xa0, 0xe3, /* mov r2, #'T' */ |
29 | +static void kvm_arm_gicv3_reset_hold(Object *obj) | 42 | 0x00, 0x20, 0xc3, 0xe5, /* loop: strb r2, [r3] *TXDAT = 'T' */ |
30 | { | 43 | 0xff, 0xff, 0xff, 0xea, /* b -4 (loop) */ |
31 | - GICv3State *s = ARM_GICV3_COMMON(dev); | 44 | 0x00, 0x10, 0x20, 0x3f, /* UART0: 0x3f201000 */ |
32 | + GICv3State *s = ARM_GICV3_COMMON(obj); | 45 | + 0x01, 0x01, 0x00, 0x00, /* CR: 0x101 = UARTEN|TXE */ |
33 | KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s); | 46 | }; |
34 | 47 | ||
35 | DPRINTF("Reset\n"); | 48 | static const uint8_t kernel_aarch64[] = { |
36 | 49 | 0x02, 0x20, 0xa1, 0xd2, /* mov x2, #0x9000000 Load UART0 */ | |
37 | - kgc->parent_reset(dev); | 50 | + 0x21, 0x20, 0x80, 0x52, /* mov w1, 0x101 CR = UARTEN|TXE */ |
38 | + if (kgc->parent_phases.hold) { | 51 | + 0x41, 0x60, 0x00, 0x79, /* strh w1, [x2, #48] Set CR */ |
39 | + kgc->parent_phases.hold(obj); | 52 | 0x81, 0x0a, 0x80, 0x52, /* mov w1, #'T' */ |
40 | + } | 53 | 0x41, 0x00, 0x00, 0x39, /* loop: strb w1, [x2] *TXDAT = 'T' */ |
41 | 54 | 0xff, 0xff, 0xff, 0x17, /* b -4 (loop) */ | |
42 | if (s->migration_blocker) { | ||
43 | DPRINTF("Cannot put kernel gic state, no kernel interface\n"); | ||
44 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
45 | static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) | ||
46 | { | ||
47 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
48 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
49 | ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass); | ||
50 | KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass); | ||
51 | |||
52 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data) | ||
53 | agcc->post_load = kvm_arm_gicv3_put; | ||
54 | device_class_set_parent_realize(dc, kvm_arm_gicv3_realize, | ||
55 | &kgc->parent_realize); | ||
56 | - device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset); | ||
57 | + resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL, | ||
58 | + &kgc->parent_phases); | ||
59 | } | ||
60 | |||
61 | static const TypeInfo kvm_arm_gicv3_info = { | ||
62 | -- | 55 | -- |
63 | 2.25.1 | 56 | 2.34.1 |
64 | 57 | ||
65 | 58 | diff view generated by jsdifflib |
1 | For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of | 1 | helper.c includes some small TCG helper functions used for mostly |
---|---|---|---|
2 | TLB maintenance instructions that operate on the inner shareable | 2 | arithmetic instructions. These are TCG only and there's no need for |
3 | domain: | 3 | them to be in the large and unwieldy helper.c. Move them out to |
4 | their own source file in the tcg/ subdirectory, together with the | ||
5 | op_addsub.h multiply-included template header that they use. | ||
4 | 6 | ||
5 | AArch64: | 7 | Since we are moving op_addsub.h, we take the opportunity to |
6 | TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS, | 8 | give it a name which matches our convention for files which |
7 | TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS, | 9 | are not true header files but which are #included from other |
8 | TLBI RVALE1IS, and TLBI RVAALE1IS. | 10 | C files: op_addsub.c.inc. |
9 | 11 | ||
10 | AArch32: | 12 | (Ironically, this means that helper.c no longer contains |
11 | TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS, | 13 | any TCG helper function definitions at all.) |
12 | and TLBIMVAALIS. | ||
13 | |||
14 | Add the trapping support. | ||
15 | 14 | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20250110131211.2546314-1-peter.maydell@linaro.org | ||
18 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
18 | --- | 19 | --- |
19 | target/arm/helper.c | 43 +++++++++++++++++++++++++++---------------- | 20 | target/arm/helper.c | 285 ----------------- |
20 | 1 file changed, 27 insertions(+), 16 deletions(-) | 21 | target/arm/tcg/arith_helper.c | 296 ++++++++++++++++++ |
22 | .../arm/{op_addsub.h => tcg/op_addsub.c.inc} | 0 | ||
23 | target/arm/tcg/meson.build | 1 + | ||
24 | 4 files changed, 297 insertions(+), 285 deletions(-) | ||
25 | create mode 100644 target/arm/tcg/arith_helper.c | ||
26 | rename target/arm/{op_addsub.h => tcg/op_addsub.c.inc} (100%) | ||
21 | 27 | ||
22 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
23 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/helper.c | 30 | --- a/target/arm/helper.c |
25 | +++ b/target/arm/helper.c | 31 | +++ b/target/arm/helper.c |
26 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, | 32 | @@ -XXX,XX +XXX,XX @@ |
27 | return CP_ACCESS_OK; | 33 | #include "qemu/main-loop.h" |
34 | #include "qemu/timer.h" | ||
35 | #include "qemu/bitops.h" | ||
36 | -#include "qemu/crc32c.h" | ||
37 | #include "qemu/qemu-print.h" | ||
38 | #include "exec/exec-all.h" | ||
39 | #include "exec/translation-block.h" | ||
40 | -#include <zlib.h> /* for crc32 */ | ||
41 | #include "hw/irq.h" | ||
42 | #include "system/cpu-timers.h" | ||
43 | #include "system/kvm.h" | ||
44 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
45 | }; | ||
28 | } | 46 | } |
29 | 47 | ||
30 | +/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */ | 48 | -/* |
31 | +static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, | 49 | - * Note that signed overflow is undefined in C. The following routines are |
32 | + bool isread) | 50 | - * careful to use unsigned types where modulo arithmetic is required. |
33 | +{ | 51 | - * Failure to do so _will_ break on newer gcc. |
34 | + if (arm_current_el(env) == 1 && | 52 | - */ |
35 | + (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) { | 53 | - |
36 | + return CP_ACCESS_TRAP_EL2; | 54 | -/* Signed saturating arithmetic. */ |
37 | + } | 55 | - |
38 | + return CP_ACCESS_OK; | 56 | -/* Perform 16-bit signed saturating addition. */ |
39 | +} | 57 | -static inline uint16_t add16_sat(uint16_t a, uint16_t b) |
40 | + | 58 | -{ |
41 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | 59 | - uint16_t res; |
42 | { | 60 | - |
43 | ARMCPU *cpu = env_archcpu(env); | 61 | - res = a + b; |
44 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | 62 | - if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { |
45 | static const ARMCPRegInfo v7mp_cp_reginfo[] = { | 63 | - if (a & 0x8000) { |
46 | /* 32 bit TLB invalidates, Inner Shareable */ | 64 | - res = 0x8000; |
47 | { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | 65 | - } else { |
48 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 66 | - res = 0x7fff; |
49 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 67 | - } |
50 | .writefn = tlbiall_is_write }, | 68 | - } |
51 | { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | 69 | - return res; |
52 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 70 | -} |
53 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 71 | - |
54 | .writefn = tlbimva_is_write }, | 72 | -/* Perform 8-bit signed saturating addition. */ |
55 | { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | 73 | -static inline uint8_t add8_sat(uint8_t a, uint8_t b) |
56 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 74 | -{ |
57 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 75 | - uint8_t res; |
58 | .writefn = tlbiasid_is_write }, | 76 | - |
59 | { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | 77 | - res = a + b; |
60 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 78 | - if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { |
61 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 79 | - if (a & 0x80) { |
62 | .writefn = tlbimvaa_is_write }, | 80 | - res = 0x80; |
63 | }; | 81 | - } else { |
64 | 82 | - res = 0x7f; | |
65 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 83 | - } |
66 | /* TLBI operations */ | 84 | - } |
67 | { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, | 85 | - return res; |
68 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, | 86 | -} |
69 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 87 | - |
70 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 88 | -/* Perform 16-bit signed saturating subtraction. */ |
71 | .writefn = tlbi_aa64_vmalle1is_write }, | 89 | -static inline uint16_t sub16_sat(uint16_t a, uint16_t b) |
72 | { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64, | 90 | -{ |
73 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1, | 91 | - uint16_t res; |
74 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 92 | - |
75 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 93 | - res = a - b; |
76 | .writefn = tlbi_aa64_vae1is_write }, | 94 | - if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { |
77 | { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64, | 95 | - if (a & 0x8000) { |
78 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2, | 96 | - res = 0x8000; |
79 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 97 | - } else { |
80 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 98 | - res = 0x7fff; |
81 | .writefn = tlbi_aa64_vmalle1is_write }, | 99 | - } |
82 | { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64, | 100 | - } |
83 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3, | 101 | - return res; |
84 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 102 | -} |
85 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 103 | - |
86 | .writefn = tlbi_aa64_vae1is_write }, | 104 | -/* Perform 8-bit signed saturating subtraction. */ |
87 | { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64, | 105 | -static inline uint8_t sub8_sat(uint8_t a, uint8_t b) |
88 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | 106 | -{ |
89 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 107 | - uint8_t res; |
90 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 108 | - |
91 | .writefn = tlbi_aa64_vae1is_write }, | 109 | - res = a - b; |
92 | { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64, | 110 | - if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { |
93 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | 111 | - if (a & 0x80) { |
94 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 112 | - res = 0x80; |
95 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 113 | - } else { |
96 | .writefn = tlbi_aa64_vae1is_write }, | 114 | - res = 0x7f; |
97 | { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64, | 115 | - } |
98 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0, | 116 | - } |
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 117 | - return res; |
100 | #endif | 118 | -} |
101 | /* TLB invalidate last level of translation table walk */ | 119 | - |
102 | { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5, | 120 | -#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); |
103 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 121 | -#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); |
104 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 122 | -#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); |
105 | .writefn = tlbimva_is_write }, | 123 | -#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); |
106 | { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7, | 124 | -#define PFX q |
107 | - .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 125 | - |
108 | + .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis, | 126 | -#include "op_addsub.h" |
109 | .writefn = tlbimvaa_is_write }, | 127 | - |
110 | { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5, | 128 | -/* Unsigned saturating arithmetic. */ |
111 | .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb, | 129 | -static inline uint16_t add16_usat(uint16_t a, uint16_t b) |
112 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = { | 130 | -{ |
113 | static const ARMCPRegInfo tlbirange_reginfo[] = { | 131 | - uint16_t res; |
114 | { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, | 132 | - res = a + b; |
115 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, | 133 | - if (res < a) { |
116 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 134 | - res = 0xffff; |
117 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 135 | - } |
118 | .writefn = tlbi_aa64_rvae1is_write }, | 136 | - return res; |
119 | { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, | 137 | -} |
120 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, | 138 | - |
121 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 139 | -static inline uint16_t sub16_usat(uint16_t a, uint16_t b) |
122 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 140 | -{ |
123 | .writefn = tlbi_aa64_rvae1is_write }, | 141 | - if (a > b) { |
124 | { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, | 142 | - return a - b; |
125 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, | 143 | - } else { |
126 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 144 | - return 0; |
127 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 145 | - } |
128 | .writefn = tlbi_aa64_rvae1is_write }, | 146 | -} |
129 | { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, | 147 | - |
130 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, | 148 | -static inline uint8_t add8_usat(uint8_t a, uint8_t b) |
131 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | 149 | -{ |
132 | + .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW, | 150 | - uint8_t res; |
133 | .writefn = tlbi_aa64_rvae1is_write }, | 151 | - res = a + b; |
134 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | 152 | - if (res < a) { |
135 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | 153 | - res = 0xff; |
154 | - } | ||
155 | - return res; | ||
156 | -} | ||
157 | - | ||
158 | -static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | ||
159 | -{ | ||
160 | - if (a > b) { | ||
161 | - return a - b; | ||
162 | - } else { | ||
163 | - return 0; | ||
164 | - } | ||
165 | -} | ||
166 | - | ||
167 | -#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | ||
168 | -#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | ||
169 | -#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | ||
170 | -#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | ||
171 | -#define PFX uq | ||
172 | - | ||
173 | -#include "op_addsub.h" | ||
174 | - | ||
175 | -/* Signed modulo arithmetic. */ | ||
176 | -#define SARITH16(a, b, n, op) do { \ | ||
177 | - int32_t sum; \ | ||
178 | - sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ | ||
179 | - RESULT(sum, n, 16); \ | ||
180 | - if (sum >= 0) \ | ||
181 | - ge |= 3 << (n * 2); \ | ||
182 | - } while (0) | ||
183 | - | ||
184 | -#define SARITH8(a, b, n, op) do { \ | ||
185 | - int32_t sum; \ | ||
186 | - sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ | ||
187 | - RESULT(sum, n, 8); \ | ||
188 | - if (sum >= 0) \ | ||
189 | - ge |= 1 << n; \ | ||
190 | - } while (0) | ||
191 | - | ||
192 | - | ||
193 | -#define ADD16(a, b, n) SARITH16(a, b, n, +) | ||
194 | -#define SUB16(a, b, n) SARITH16(a, b, n, -) | ||
195 | -#define ADD8(a, b, n) SARITH8(a, b, n, +) | ||
196 | -#define SUB8(a, b, n) SARITH8(a, b, n, -) | ||
197 | -#define PFX s | ||
198 | -#define ARITH_GE | ||
199 | - | ||
200 | -#include "op_addsub.h" | ||
201 | - | ||
202 | -/* Unsigned modulo arithmetic. */ | ||
203 | -#define ADD16(a, b, n) do { \ | ||
204 | - uint32_t sum; \ | ||
205 | - sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | ||
206 | - RESULT(sum, n, 16); \ | ||
207 | - if ((sum >> 16) == 1) \ | ||
208 | - ge |= 3 << (n * 2); \ | ||
209 | - } while (0) | ||
210 | - | ||
211 | -#define ADD8(a, b, n) do { \ | ||
212 | - uint32_t sum; \ | ||
213 | - sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | ||
214 | - RESULT(sum, n, 8); \ | ||
215 | - if ((sum >> 8) == 1) \ | ||
216 | - ge |= 1 << n; \ | ||
217 | - } while (0) | ||
218 | - | ||
219 | -#define SUB16(a, b, n) do { \ | ||
220 | - uint32_t sum; \ | ||
221 | - sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | ||
222 | - RESULT(sum, n, 16); \ | ||
223 | - if ((sum >> 16) == 0) \ | ||
224 | - ge |= 3 << (n * 2); \ | ||
225 | - } while (0) | ||
226 | - | ||
227 | -#define SUB8(a, b, n) do { \ | ||
228 | - uint32_t sum; \ | ||
229 | - sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | ||
230 | - RESULT(sum, n, 8); \ | ||
231 | - if ((sum >> 8) == 0) \ | ||
232 | - ge |= 1 << n; \ | ||
233 | - } while (0) | ||
234 | - | ||
235 | -#define PFX u | ||
236 | -#define ARITH_GE | ||
237 | - | ||
238 | -#include "op_addsub.h" | ||
239 | - | ||
240 | -/* Halved signed arithmetic. */ | ||
241 | -#define ADD16(a, b, n) \ | ||
242 | - RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | ||
243 | -#define SUB16(a, b, n) \ | ||
244 | - RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | ||
245 | -#define ADD8(a, b, n) \ | ||
246 | - RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | ||
247 | -#define SUB8(a, b, n) \ | ||
248 | - RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | ||
249 | -#define PFX sh | ||
250 | - | ||
251 | -#include "op_addsub.h" | ||
252 | - | ||
253 | -/* Halved unsigned arithmetic. */ | ||
254 | -#define ADD16(a, b, n) \ | ||
255 | - RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | ||
256 | -#define SUB16(a, b, n) \ | ||
257 | - RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | ||
258 | -#define ADD8(a, b, n) \ | ||
259 | - RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | ||
260 | -#define SUB8(a, b, n) \ | ||
261 | - RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | ||
262 | -#define PFX uh | ||
263 | - | ||
264 | -#include "op_addsub.h" | ||
265 | - | ||
266 | -static inline uint8_t do_usad(uint8_t a, uint8_t b) | ||
267 | -{ | ||
268 | - if (a > b) { | ||
269 | - return a - b; | ||
270 | - } else { | ||
271 | - return b - a; | ||
272 | - } | ||
273 | -} | ||
274 | - | ||
275 | -/* Unsigned sum of absolute byte differences. */ | ||
276 | -uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | ||
277 | -{ | ||
278 | - uint32_t sum; | ||
279 | - sum = do_usad(a, b); | ||
280 | - sum += do_usad(a >> 8, b >> 8); | ||
281 | - sum += do_usad(a >> 16, b >> 16); | ||
282 | - sum += do_usad(a >> 24, b >> 24); | ||
283 | - return sum; | ||
284 | -} | ||
285 | - | ||
286 | -/* For ARMv6 SEL instruction. */ | ||
287 | -uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | ||
288 | -{ | ||
289 | - uint32_t mask; | ||
290 | - | ||
291 | - mask = 0; | ||
292 | - if (flags & 1) { | ||
293 | - mask |= 0xff; | ||
294 | - } | ||
295 | - if (flags & 2) { | ||
296 | - mask |= 0xff00; | ||
297 | - } | ||
298 | - if (flags & 4) { | ||
299 | - mask |= 0xff0000; | ||
300 | - } | ||
301 | - if (flags & 8) { | ||
302 | - mask |= 0xff000000; | ||
303 | - } | ||
304 | - return (a & mask) | (b & ~mask); | ||
305 | -} | ||
306 | - | ||
307 | -/* | ||
308 | - * CRC helpers. | ||
309 | - * The upper bytes of val (above the number specified by 'bytes') must have | ||
310 | - * been zeroed out by the caller. | ||
311 | - */ | ||
312 | -uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) | ||
313 | -{ | ||
314 | - uint8_t buf[4]; | ||
315 | - | ||
316 | - stl_le_p(buf, val); | ||
317 | - | ||
318 | - /* zlib crc32 converts the accumulator and output to one's complement. */ | ||
319 | - return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | ||
320 | -} | ||
321 | - | ||
322 | -uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | ||
323 | -{ | ||
324 | - uint8_t buf[4]; | ||
325 | - | ||
326 | - stl_le_p(buf, val); | ||
327 | - | ||
328 | - /* Linux crc32c converts the output to one's complement. */ | ||
329 | - return crc32c(acc, buf, bytes) ^ 0xffffffff; | ||
330 | -} | ||
331 | |||
332 | /* | ||
333 | * Return the exception level to which FP-disabled exceptions should | ||
334 | diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c | ||
335 | new file mode 100644 | ||
336 | index XXXXXXX..XXXXXXX | ||
337 | --- /dev/null | ||
338 | +++ b/target/arm/tcg/arith_helper.c | ||
339 | @@ -XXX,XX +XXX,XX @@ | ||
340 | +/* | ||
341 | + * ARM generic helpers for various arithmetical operations. | ||
342 | + * | ||
343 | + * This code is licensed under the GNU GPL v2 or later. | ||
344 | + * | ||
345 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
346 | + */ | ||
347 | +#include "qemu/osdep.h" | ||
348 | +#include "cpu.h" | ||
349 | +#include "exec/helper-proto.h" | ||
350 | +#include "qemu/crc32c.h" | ||
351 | +#include <zlib.h> /* for crc32 */ | ||
352 | + | ||
353 | +/* | ||
354 | + * Note that signed overflow is undefined in C. The following routines are | ||
355 | + * careful to use unsigned types where modulo arithmetic is required. | ||
356 | + * Failure to do so _will_ break on newer gcc. | ||
357 | + */ | ||
358 | + | ||
359 | +/* Signed saturating arithmetic. */ | ||
360 | + | ||
361 | +/* Perform 16-bit signed saturating addition. */ | ||
362 | +static inline uint16_t add16_sat(uint16_t a, uint16_t b) | ||
363 | +{ | ||
364 | + uint16_t res; | ||
365 | + | ||
366 | + res = a + b; | ||
367 | + if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { | ||
368 | + if (a & 0x8000) { | ||
369 | + res = 0x8000; | ||
370 | + } else { | ||
371 | + res = 0x7fff; | ||
372 | + } | ||
373 | + } | ||
374 | + return res; | ||
375 | +} | ||
376 | + | ||
377 | +/* Perform 8-bit signed saturating addition. */ | ||
378 | +static inline uint8_t add8_sat(uint8_t a, uint8_t b) | ||
379 | +{ | ||
380 | + uint8_t res; | ||
381 | + | ||
382 | + res = a + b; | ||
383 | + if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { | ||
384 | + if (a & 0x80) { | ||
385 | + res = 0x80; | ||
386 | + } else { | ||
387 | + res = 0x7f; | ||
388 | + } | ||
389 | + } | ||
390 | + return res; | ||
391 | +} | ||
392 | + | ||
393 | +/* Perform 16-bit signed saturating subtraction. */ | ||
394 | +static inline uint16_t sub16_sat(uint16_t a, uint16_t b) | ||
395 | +{ | ||
396 | + uint16_t res; | ||
397 | + | ||
398 | + res = a - b; | ||
399 | + if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) { | ||
400 | + if (a & 0x8000) { | ||
401 | + res = 0x8000; | ||
402 | + } else { | ||
403 | + res = 0x7fff; | ||
404 | + } | ||
405 | + } | ||
406 | + return res; | ||
407 | +} | ||
408 | + | ||
409 | +/* Perform 8-bit signed saturating subtraction. */ | ||
410 | +static inline uint8_t sub8_sat(uint8_t a, uint8_t b) | ||
411 | +{ | ||
412 | + uint8_t res; | ||
413 | + | ||
414 | + res = a - b; | ||
415 | + if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) { | ||
416 | + if (a & 0x80) { | ||
417 | + res = 0x80; | ||
418 | + } else { | ||
419 | + res = 0x7f; | ||
420 | + } | ||
421 | + } | ||
422 | + return res; | ||
423 | +} | ||
424 | + | ||
425 | +#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16); | ||
426 | +#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16); | ||
427 | +#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8); | ||
428 | +#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8); | ||
429 | +#define PFX q | ||
430 | + | ||
431 | +#include "op_addsub.c.inc" | ||
432 | + | ||
433 | +/* Unsigned saturating arithmetic. */ | ||
434 | +static inline uint16_t add16_usat(uint16_t a, uint16_t b) | ||
435 | +{ | ||
436 | + uint16_t res; | ||
437 | + res = a + b; | ||
438 | + if (res < a) { | ||
439 | + res = 0xffff; | ||
440 | + } | ||
441 | + return res; | ||
442 | +} | ||
443 | + | ||
444 | +static inline uint16_t sub16_usat(uint16_t a, uint16_t b) | ||
445 | +{ | ||
446 | + if (a > b) { | ||
447 | + return a - b; | ||
448 | + } else { | ||
449 | + return 0; | ||
450 | + } | ||
451 | +} | ||
452 | + | ||
453 | +static inline uint8_t add8_usat(uint8_t a, uint8_t b) | ||
454 | +{ | ||
455 | + uint8_t res; | ||
456 | + res = a + b; | ||
457 | + if (res < a) { | ||
458 | + res = 0xff; | ||
459 | + } | ||
460 | + return res; | ||
461 | +} | ||
462 | + | ||
463 | +static inline uint8_t sub8_usat(uint8_t a, uint8_t b) | ||
464 | +{ | ||
465 | + if (a > b) { | ||
466 | + return a - b; | ||
467 | + } else { | ||
468 | + return 0; | ||
469 | + } | ||
470 | +} | ||
471 | + | ||
472 | +#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16); | ||
473 | +#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16); | ||
474 | +#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8); | ||
475 | +#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8); | ||
476 | +#define PFX uq | ||
477 | + | ||
478 | +#include "op_addsub.c.inc" | ||
479 | + | ||
480 | +/* Signed modulo arithmetic. */ | ||
481 | +#define SARITH16(a, b, n, op) do { \ | ||
482 | + int32_t sum; \ | ||
483 | + sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \ | ||
484 | + RESULT(sum, n, 16); \ | ||
485 | + if (sum >= 0) \ | ||
486 | + ge |= 3 << (n * 2); \ | ||
487 | + } while (0) | ||
488 | + | ||
489 | +#define SARITH8(a, b, n, op) do { \ | ||
490 | + int32_t sum; \ | ||
491 | + sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \ | ||
492 | + RESULT(sum, n, 8); \ | ||
493 | + if (sum >= 0) \ | ||
494 | + ge |= 1 << n; \ | ||
495 | + } while (0) | ||
496 | + | ||
497 | + | ||
498 | +#define ADD16(a, b, n) SARITH16(a, b, n, +) | ||
499 | +#define SUB16(a, b, n) SARITH16(a, b, n, -) | ||
500 | +#define ADD8(a, b, n) SARITH8(a, b, n, +) | ||
501 | +#define SUB8(a, b, n) SARITH8(a, b, n, -) | ||
502 | +#define PFX s | ||
503 | +#define ARITH_GE | ||
504 | + | ||
505 | +#include "op_addsub.c.inc" | ||
506 | + | ||
507 | +/* Unsigned modulo arithmetic. */ | ||
508 | +#define ADD16(a, b, n) do { \ | ||
509 | + uint32_t sum; \ | ||
510 | + sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ | ||
511 | + RESULT(sum, n, 16); \ | ||
512 | + if ((sum >> 16) == 1) \ | ||
513 | + ge |= 3 << (n * 2); \ | ||
514 | + } while (0) | ||
515 | + | ||
516 | +#define ADD8(a, b, n) do { \ | ||
517 | + uint32_t sum; \ | ||
518 | + sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ | ||
519 | + RESULT(sum, n, 8); \ | ||
520 | + if ((sum >> 8) == 1) \ | ||
521 | + ge |= 1 << n; \ | ||
522 | + } while (0) | ||
523 | + | ||
524 | +#define SUB16(a, b, n) do { \ | ||
525 | + uint32_t sum; \ | ||
526 | + sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \ | ||
527 | + RESULT(sum, n, 16); \ | ||
528 | + if ((sum >> 16) == 0) \ | ||
529 | + ge |= 3 << (n * 2); \ | ||
530 | + } while (0) | ||
531 | + | ||
532 | +#define SUB8(a, b, n) do { \ | ||
533 | + uint32_t sum; \ | ||
534 | + sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ | ||
535 | + RESULT(sum, n, 8); \ | ||
536 | + if ((sum >> 8) == 0) \ | ||
537 | + ge |= 1 << n; \ | ||
538 | + } while (0) | ||
539 | + | ||
540 | +#define PFX u | ||
541 | +#define ARITH_GE | ||
542 | + | ||
543 | +#include "op_addsub.c.inc" | ||
544 | + | ||
545 | +/* Halved signed arithmetic. */ | ||
546 | +#define ADD16(a, b, n) \ | ||
547 | + RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16) | ||
548 | +#define SUB16(a, b, n) \ | ||
549 | + RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16) | ||
550 | +#define ADD8(a, b, n) \ | ||
551 | + RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8) | ||
552 | +#define SUB8(a, b, n) \ | ||
553 | + RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8) | ||
554 | +#define PFX sh | ||
555 | + | ||
556 | +#include "op_addsub.c.inc" | ||
557 | + | ||
558 | +/* Halved unsigned arithmetic. */ | ||
559 | +#define ADD16(a, b, n) \ | ||
560 | + RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16) | ||
561 | +#define SUB16(a, b, n) \ | ||
562 | + RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16) | ||
563 | +#define ADD8(a, b, n) \ | ||
564 | + RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8) | ||
565 | +#define SUB8(a, b, n) \ | ||
566 | + RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8) | ||
567 | +#define PFX uh | ||
568 | + | ||
569 | +#include "op_addsub.c.inc" | ||
570 | + | ||
571 | +static inline uint8_t do_usad(uint8_t a, uint8_t b) | ||
572 | +{ | ||
573 | + if (a > b) { | ||
574 | + return a - b; | ||
575 | + } else { | ||
576 | + return b - a; | ||
577 | + } | ||
578 | +} | ||
579 | + | ||
580 | +/* Unsigned sum of absolute byte differences. */ | ||
581 | +uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | ||
582 | +{ | ||
583 | + uint32_t sum; | ||
584 | + sum = do_usad(a, b); | ||
585 | + sum += do_usad(a >> 8, b >> 8); | ||
586 | + sum += do_usad(a >> 16, b >> 16); | ||
587 | + sum += do_usad(a >> 24, b >> 24); | ||
588 | + return sum; | ||
589 | +} | ||
590 | + | ||
591 | +/* For ARMv6 SEL instruction. */ | ||
592 | +uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) | ||
593 | +{ | ||
594 | + uint32_t mask; | ||
595 | + | ||
596 | + mask = 0; | ||
597 | + if (flags & 1) { | ||
598 | + mask |= 0xff; | ||
599 | + } | ||
600 | + if (flags & 2) { | ||
601 | + mask |= 0xff00; | ||
602 | + } | ||
603 | + if (flags & 4) { | ||
604 | + mask |= 0xff0000; | ||
605 | + } | ||
606 | + if (flags & 8) { | ||
607 | + mask |= 0xff000000; | ||
608 | + } | ||
609 | + return (a & mask) | (b & ~mask); | ||
610 | +} | ||
611 | + | ||
612 | +/* | ||
613 | + * CRC helpers. | ||
614 | + * The upper bytes of val (above the number specified by 'bytes') must have | ||
615 | + * been zeroed out by the caller. | ||
616 | + */ | ||
617 | +uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes) | ||
618 | +{ | ||
619 | + uint8_t buf[4]; | ||
620 | + | ||
621 | + stl_le_p(buf, val); | ||
622 | + | ||
623 | + /* zlib crc32 converts the accumulator and output to one's complement. */ | ||
624 | + return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; | ||
625 | +} | ||
626 | + | ||
627 | +uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) | ||
628 | +{ | ||
629 | + uint8_t buf[4]; | ||
630 | + | ||
631 | + stl_le_p(buf, val); | ||
632 | + | ||
633 | + /* Linux crc32c converts the output to one's complement. */ | ||
634 | + return crc32c(acc, buf, bytes) ^ 0xffffffff; | ||
635 | +} | ||
636 | diff --git a/target/arm/op_addsub.h b/target/arm/tcg/op_addsub.c.inc | ||
637 | similarity index 100% | ||
638 | rename from target/arm/op_addsub.h | ||
639 | rename to target/arm/tcg/op_addsub.c.inc | ||
640 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build | ||
641 | index XXXXXXX..XXXXXXX 100644 | ||
642 | --- a/target/arm/tcg/meson.build | ||
643 | +++ b/target/arm/tcg/meson.build | ||
644 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
645 | 'tlb_helper.c', | ||
646 | 'vec_helper.c', | ||
647 | 'tlb-insns.c', | ||
648 | + 'arith_helper.c', | ||
649 | )) | ||
650 | |||
651 | arm_ss.add(when: 'TARGET_AARCH64', if_true: files( | ||
136 | -- | 652 | -- |
137 | 2.25.1 | 653 | 2.34.1 |
654 | |||
655 | diff view generated by jsdifflib |
1 | Now we have converted TYPE_ARM_GIC_COMMON, we can convert the | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
---|---|---|---|
2 | TYPE_ARM_GIC_KVM subclass to 3-phase reset. | ||
3 | 2 | ||
3 | Before changing default pauth algorithm, we need to make sure current | ||
4 | default one (QARMA5) can still be selected. | ||
5 | |||
6 | $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... | ||
7 | |||
8 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org | ||
8 | --- | 12 | --- |
9 | hw/intc/arm_gic_kvm.c | 14 +++++++++----- | 13 | docs/system/arm/cpu-features.rst | 5 ++++- |
10 | 1 file changed, 9 insertions(+), 5 deletions(-) | 14 | target/arm/cpu.h | 1 + |
15 | target/arm/arm-qmp-cmds.c | 2 +- | ||
16 | target/arm/cpu64.c | 20 ++++++++++++++------ | ||
17 | tests/qtest/arm-cpu-features.c | 15 +++++++++++---- | ||
18 | 5 files changed, 31 insertions(+), 12 deletions(-) | ||
11 | 19 | ||
12 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | 20 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
13 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/intc/arm_gic_kvm.c | 22 | --- a/docs/system/arm/cpu-features.rst |
15 | +++ b/hw/intc/arm_gic_kvm.c | 23 | +++ b/docs/system/arm/cpu-features.rst |
16 | @@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass, | 24 | @@ -XXX,XX +XXX,XX @@ Below is the list of TCG VCPU features and their descriptions. |
17 | struct KVMARMGICClass { | 25 | ``pauth-qarma3`` |
18 | ARMGICCommonClass parent_class; | 26 | When ``pauth`` is enabled, select the architected QARMA3 algorithm. |
19 | DeviceRealize parent_realize; | 27 | |
20 | - void (*parent_reset)(DeviceState *dev); | 28 | -Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled, |
21 | + ResettablePhases parent_phases; | 29 | +``pauth-qarma5`` |
30 | + When ``pauth`` is enabled, select the architected QARMA5 algorithm. | ||
31 | + | ||
32 | +Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, | ||
33 | the architected QARMA5 algorithm is used. The architected QARMA5 | ||
34 | and QARMA3 algorithms have good cryptographic properties, but can | ||
35 | be quite slow to emulate. The impdef algorithm used by QEMU is | ||
36 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/cpu.h | ||
39 | +++ b/target/arm/cpu.h | ||
40 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
41 | bool prop_pauth; | ||
42 | bool prop_pauth_impdef; | ||
43 | bool prop_pauth_qarma3; | ||
44 | + bool prop_pauth_qarma5; | ||
45 | bool prop_lpa2; | ||
46 | |||
47 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ | ||
48 | diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/arm-qmp-cmds.c | ||
51 | +++ b/target/arm/arm-qmp-cmds.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = { | ||
53 | "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", | ||
54 | "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", | ||
55 | "kvm-no-adjvtime", "kvm-steal-time", | ||
56 | - "pauth", "pauth-impdef", "pauth-qarma3", | ||
57 | + "pauth", "pauth-impdef", "pauth-qarma3", "pauth-qarma5", | ||
58 | NULL | ||
22 | }; | 59 | }; |
23 | 60 | ||
24 | void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level) | 61 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
25 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s) | 62 | index XXXXXXX..XXXXXXX 100644 |
63 | --- a/target/arm/cpu64.c | ||
64 | +++ b/target/arm/cpu64.c | ||
65 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) | ||
66 | } | ||
67 | |||
68 | if (cpu->prop_pauth) { | ||
69 | - if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { | ||
70 | + if ((cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) || | ||
71 | + (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma5) || | ||
72 | + (cpu->prop_pauth_qarma3 && cpu->prop_pauth_qarma5)) { | ||
73 | error_setg(errp, | ||
74 | - "cannot enable both pauth-impdef and pauth-qarma3"); | ||
75 | + "cannot enable pauth-impdef, pauth-qarma3 and " | ||
76 | + "pauth-qarma5 at the same time"); | ||
77 | return; | ||
78 | } | ||
79 | |||
80 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) | ||
81 | } else if (cpu->prop_pauth_qarma3) { | ||
82 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); | ||
83 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); | ||
84 | - } else { | ||
85 | + } else { /* default is pauth-qarma5 */ | ||
86 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); | ||
87 | isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); | ||
88 | } | ||
89 | - } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { | ||
90 | - error_setg(errp, "cannot enable pauth-impdef or " | ||
91 | - "pauth-qarma3 without pauth"); | ||
92 | + } else if (cpu->prop_pauth_impdef || | ||
93 | + cpu->prop_pauth_qarma3 || | ||
94 | + cpu->prop_pauth_qarma5) { | ||
95 | + error_setg(errp, "cannot enable pauth-impdef, pauth-qarma3 or " | ||
96 | + "pauth-qarma5 without pauth"); | ||
97 | error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); | ||
98 | } | ||
99 | } | ||
100 | @@ -XXX,XX +XXX,XX @@ static const Property arm_cpu_pauth_impdef_property = | ||
101 | DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); | ||
102 | static const Property arm_cpu_pauth_qarma3_property = | ||
103 | DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); | ||
104 | +static Property arm_cpu_pauth_qarma5_property = | ||
105 | + DEFINE_PROP_BOOL("pauth-qarma5", ARMCPU, prop_pauth_qarma5, false); | ||
106 | |||
107 | void aarch64_add_pauth_properties(Object *obj) | ||
108 | { | ||
109 | @@ -XXX,XX +XXX,XX @@ void aarch64_add_pauth_properties(Object *obj) | ||
110 | } else { | ||
111 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); | ||
112 | qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); | ||
113 | + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma5_property); | ||
26 | } | 114 | } |
27 | } | 115 | } |
28 | 116 | ||
29 | -static void kvm_arm_gic_reset(DeviceState *dev) | 117 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c |
30 | +static void kvm_arm_gic_reset_hold(Object *obj) | 118 | index XXXXXXX..XXXXXXX 100644 |
31 | { | 119 | --- a/tests/qtest/arm-cpu-features.c |
32 | - GICState *s = ARM_GIC_COMMON(dev); | 120 | +++ b/tests/qtest/arm-cpu-features.c |
33 | + GICState *s = ARM_GIC_COMMON(obj); | 121 | @@ -XXX,XX +XXX,XX @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type) |
34 | KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s); | 122 | assert_has_feature_enabled(qts, cpu_type, "pauth"); |
35 | 123 | assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); | |
36 | - kgc->parent_reset(dev); | 124 | assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3"); |
37 | + if (kgc->parent_phases.hold) { | 125 | + assert_has_feature_disabled(qts, cpu_type, "pauth-qarma5"); |
38 | + kgc->parent_phases.hold(obj); | 126 | assert_set_feature(qts, cpu_type, "pauth", false); |
39 | + } | 127 | assert_set_feature(qts, cpu_type, "pauth", true); |
40 | 128 | assert_set_feature(qts, cpu_type, "pauth-impdef", true); | |
41 | if (kvm_arm_gic_can_save_restore(s)) { | 129 | assert_set_feature(qts, cpu_type, "pauth-impdef", false); |
42 | kvm_arm_gic_put(s); | 130 | assert_set_feature(qts, cpu_type, "pauth-qarma3", true); |
43 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | 131 | assert_set_feature(qts, cpu_type, "pauth-qarma3", false); |
44 | static void kvm_arm_gic_class_init(ObjectClass *klass, void *data) | 132 | + assert_set_feature(qts, cpu_type, "pauth-qarma5", true); |
45 | { | 133 | + assert_set_feature(qts, cpu_type, "pauth-qarma5", false); |
46 | DeviceClass *dc = DEVICE_CLASS(klass); | 134 | assert_error(qts, cpu_type, |
47 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | 135 | - "cannot enable pauth-impdef or pauth-qarma3 without pauth", |
48 | ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass); | 136 | + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", |
49 | KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass); | 137 | "{ 'pauth': false, 'pauth-impdef': true }"); |
50 | 138 | assert_error(qts, cpu_type, | |
51 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data) | 139 | - "cannot enable pauth-impdef or pauth-qarma3 without pauth", |
52 | agcc->post_load = kvm_arm_gic_put; | 140 | + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", |
53 | device_class_set_parent_realize(dc, kvm_arm_gic_realize, | 141 | "{ 'pauth': false, 'pauth-qarma3': true }"); |
54 | &kgc->parent_realize); | 142 | assert_error(qts, cpu_type, |
55 | - device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset); | 143 | - "cannot enable both pauth-impdef and pauth-qarma3", |
56 | + resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL, | 144 | - "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true }"); |
57 | + &kgc->parent_phases); | 145 | + "cannot enable pauth-impdef, pauth-qarma3 or pauth-qarma5 without pauth", |
146 | + "{ 'pauth': false, 'pauth-qarma5': true }"); | ||
147 | + assert_error(qts, cpu_type, | ||
148 | + "cannot enable pauth-impdef, pauth-qarma3 and pauth-qarma5 at the same time", | ||
149 | + "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true," | ||
150 | + " 'pauth-qarma5': true }"); | ||
58 | } | 151 | } |
59 | 152 | ||
60 | static const TypeInfo kvm_arm_gic_info = { | 153 | static void test_query_cpu_model_expansion(const void *data) |
61 | -- | 154 | -- |
62 | 2.25.1 | 155 | 2.34.1 |
63 | |||
64 | diff view generated by jsdifflib |
1 | From: Zhuojia Shen <chaosdefinition@hotmail.com> | 1 | The pauth-3 test explicitly tests that a computation of the |
---|---|---|---|
2 | pointer-authentication produces the expected result. This means that | ||
3 | it must be run with the QARMA5 algorithm. | ||
2 | 4 | ||
3 | In CPUID registers exposed to userspace, some registers were missing | 5 | Explicitly set the pauth algorithm when running this test, so that it |
4 | and some fields were not exposed. This patch aligns exposed ID | 6 | doesn't break when we change the default algorithm the 'max' CPU |
5 | registers and their fields with what the upstream kernel currently | 7 | uses. |
6 | exposes. | ||
7 | 8 | ||
8 | Specifically, the following new ID registers/fields are exposed to | ||
9 | userspace: | ||
10 | |||
11 | ID_AA64PFR1_EL1.BT: bits 3-0 | ||
12 | ID_AA64PFR1_EL1.MTE: bits 11-8 | ||
13 | ID_AA64PFR1_EL1.SME: bits 27-24 | ||
14 | |||
15 | ID_AA64ZFR0_EL1.SVEver: bits 3-0 | ||
16 | ID_AA64ZFR0_EL1.AES: bits 7-4 | ||
17 | ID_AA64ZFR0_EL1.BitPerm: bits 19-16 | ||
18 | ID_AA64ZFR0_EL1.BF16: bits 23-20 | ||
19 | ID_AA64ZFR0_EL1.SHA3: bits 35-32 | ||
20 | ID_AA64ZFR0_EL1.SM4: bits 43-40 | ||
21 | ID_AA64ZFR0_EL1.I8MM: bits 47-44 | ||
22 | ID_AA64ZFR0_EL1.F32MM: bits 55-52 | ||
23 | ID_AA64ZFR0_EL1.F64MM: bits 59-56 | ||
24 | |||
25 | ID_AA64SMFR0_EL1.F32F32: bit 32 | ||
26 | ID_AA64SMFR0_EL1.B16F32: bit 34 | ||
27 | ID_AA64SMFR0_EL1.F16F32: bit 35 | ||
28 | ID_AA64SMFR0_EL1.I8I32: bits 39-36 | ||
29 | ID_AA64SMFR0_EL1.F64F64: bit 48 | ||
30 | ID_AA64SMFR0_EL1.I16I64: bits 55-52 | ||
31 | ID_AA64SMFR0_EL1.FA64: bit 63 | ||
32 | |||
33 | ID_AA64MMFR0_EL1.ECV: bits 63-60 | ||
34 | |||
35 | ID_AA64MMFR1_EL1.AFP: bits 47-44 | ||
36 | |||
37 | ID_AA64MMFR2_EL1.AT: bits 35-32 | ||
38 | |||
39 | ID_AA64ISAR0_EL1.RNDR: bits 63-60 | ||
40 | |||
41 | ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 | ||
42 | ID_AA64ISAR1_EL1.BF16: bits 47-44 | ||
43 | ID_AA64ISAR1_EL1.DGH: bits 51-48 | ||
44 | ID_AA64ISAR1_EL1.I8MM: bits 55-52 | ||
45 | |||
46 | ID_AA64ISAR2_EL1.WFxT: bits 3-0 | ||
47 | ID_AA64ISAR2_EL1.RPRES: bits 7-4 | ||
48 | ID_AA64ISAR2_EL1.GPA3: bits 11-8 | ||
49 | ID_AA64ISAR2_EL1.APA3: bits 15-12 | ||
50 | |||
51 | The code is also refactored to use symbolic names for ID register fields | ||
52 | for better readability and maintainability. | ||
53 | |||
54 | Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com> | ||
55 | Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com | ||
56 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
57 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
58 | --- | 10 | --- |
59 | target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++-------- | 11 | tests/tcg/aarch64/Makefile.softmmu-target | 3 +++ |
60 | 1 file changed, 79 insertions(+), 17 deletions(-) | 12 | 1 file changed, 3 insertions(+) |
61 | 13 | ||
62 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target |
63 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
64 | --- a/target/arm/helper.c | 16 | --- a/tests/tcg/aarch64/Makefile.softmmu-target |
65 | +++ b/target/arm/helper.c | 17 | +++ b/tests/tcg/aarch64/Makefile.softmmu-target |
66 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | 18 | @@ -XXX,XX +XXX,XX @@ EXTRA_RUNS+=run-memory-replay |
67 | #ifdef CONFIG_USER_ONLY | 19 | |
68 | static const ARMCPRegUserSpaceInfo v8_user_idregs[] = { | 20 | ifneq ($(CROSS_CC_HAS_ARMV8_3),) |
69 | { .name = "ID_AA64PFR0_EL1", | 21 | pauth-3: CFLAGS += $(CROSS_CC_HAS_ARMV8_3) |
70 | - .exported_bits = 0x000f000f00ff0000, | 22 | +# This test explicitly checks the output of the pauth operation so we |
71 | - .fixed_bits = 0x0000000000000011 }, | 23 | +# must force the use of the QARMA5 algorithm for it. |
72 | + .exported_bits = R_ID_AA64PFR0_FP_MASK | | 24 | +run-pauth-3: QEMU_BASE_MACHINE=-M virt -cpu max,pauth-qarma5=on -display none |
73 | + R_ID_AA64PFR0_ADVSIMD_MASK | | 25 | else |
74 | + R_ID_AA64PFR0_SVE_MASK | | 26 | pauth-3: |
75 | + R_ID_AA64PFR0_DIT_MASK, | 27 | $(call skip-test, "BUILD of $@", "missing compiler support") |
76 | + .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) | | ||
77 | + (0x1 << R_ID_AA64PFR0_EL1_SHIFT) }, | ||
78 | { .name = "ID_AA64PFR1_EL1", | ||
79 | - .exported_bits = 0x00000000000000f0 }, | ||
80 | + .exported_bits = R_ID_AA64PFR1_BT_MASK | | ||
81 | + R_ID_AA64PFR1_SSBS_MASK | | ||
82 | + R_ID_AA64PFR1_MTE_MASK | | ||
83 | + R_ID_AA64PFR1_SME_MASK }, | ||
84 | { .name = "ID_AA64PFR*_EL1_RESERVED", | ||
85 | - .is_glob = true }, | ||
86 | - { .name = "ID_AA64ZFR0_EL1" }, | ||
87 | + .is_glob = true }, | ||
88 | + { .name = "ID_AA64ZFR0_EL1", | ||
89 | + .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK | | ||
90 | + R_ID_AA64ZFR0_AES_MASK | | ||
91 | + R_ID_AA64ZFR0_BITPERM_MASK | | ||
92 | + R_ID_AA64ZFR0_BFLOAT16_MASK | | ||
93 | + R_ID_AA64ZFR0_SHA3_MASK | | ||
94 | + R_ID_AA64ZFR0_SM4_MASK | | ||
95 | + R_ID_AA64ZFR0_I8MM_MASK | | ||
96 | + R_ID_AA64ZFR0_F32MM_MASK | | ||
97 | + R_ID_AA64ZFR0_F64MM_MASK }, | ||
98 | + { .name = "ID_AA64SMFR0_EL1", | ||
99 | + .exported_bits = R_ID_AA64SMFR0_F32F32_MASK | | ||
100 | + R_ID_AA64SMFR0_B16F32_MASK | | ||
101 | + R_ID_AA64SMFR0_F16F32_MASK | | ||
102 | + R_ID_AA64SMFR0_I8I32_MASK | | ||
103 | + R_ID_AA64SMFR0_F64F64_MASK | | ||
104 | + R_ID_AA64SMFR0_I16I64_MASK | | ||
105 | + R_ID_AA64SMFR0_FA64_MASK }, | ||
106 | { .name = "ID_AA64MMFR0_EL1", | ||
107 | - .fixed_bits = 0x00000000ff000000 }, | ||
108 | - { .name = "ID_AA64MMFR1_EL1" }, | ||
109 | + .exported_bits = R_ID_AA64MMFR0_ECV_MASK, | ||
110 | + .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) | | ||
111 | + (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) }, | ||
112 | + { .name = "ID_AA64MMFR1_EL1", | ||
113 | + .exported_bits = R_ID_AA64MMFR1_AFP_MASK }, | ||
114 | + { .name = "ID_AA64MMFR2_EL1", | ||
115 | + .exported_bits = R_ID_AA64MMFR2_AT_MASK }, | ||
116 | { .name = "ID_AA64MMFR*_EL1_RESERVED", | ||
117 | - .is_glob = true }, | ||
118 | + .is_glob = true }, | ||
119 | { .name = "ID_AA64DFR0_EL1", | ||
120 | - .fixed_bits = 0x0000000000000006 }, | ||
121 | - { .name = "ID_AA64DFR1_EL1" }, | ||
122 | + .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) }, | ||
123 | + { .name = "ID_AA64DFR1_EL1" }, | ||
124 | { .name = "ID_AA64DFR*_EL1_RESERVED", | ||
125 | - .is_glob = true }, | ||
126 | + .is_glob = true }, | ||
127 | { .name = "ID_AA64AFR*", | ||
128 | - .is_glob = true }, | ||
129 | + .is_glob = true }, | ||
130 | { .name = "ID_AA64ISAR0_EL1", | ||
131 | - .exported_bits = 0x00fffffff0fffff0 }, | ||
132 | + .exported_bits = R_ID_AA64ISAR0_AES_MASK | | ||
133 | + R_ID_AA64ISAR0_SHA1_MASK | | ||
134 | + R_ID_AA64ISAR0_SHA2_MASK | | ||
135 | + R_ID_AA64ISAR0_CRC32_MASK | | ||
136 | + R_ID_AA64ISAR0_ATOMIC_MASK | | ||
137 | + R_ID_AA64ISAR0_RDM_MASK | | ||
138 | + R_ID_AA64ISAR0_SHA3_MASK | | ||
139 | + R_ID_AA64ISAR0_SM3_MASK | | ||
140 | + R_ID_AA64ISAR0_SM4_MASK | | ||
141 | + R_ID_AA64ISAR0_DP_MASK | | ||
142 | + R_ID_AA64ISAR0_FHM_MASK | | ||
143 | + R_ID_AA64ISAR0_TS_MASK | | ||
144 | + R_ID_AA64ISAR0_RNDR_MASK }, | ||
145 | { .name = "ID_AA64ISAR1_EL1", | ||
146 | - .exported_bits = 0x000000f0ffffffff }, | ||
147 | + .exported_bits = R_ID_AA64ISAR1_DPB_MASK | | ||
148 | + R_ID_AA64ISAR1_APA_MASK | | ||
149 | + R_ID_AA64ISAR1_API_MASK | | ||
150 | + R_ID_AA64ISAR1_JSCVT_MASK | | ||
151 | + R_ID_AA64ISAR1_FCMA_MASK | | ||
152 | + R_ID_AA64ISAR1_LRCPC_MASK | | ||
153 | + R_ID_AA64ISAR1_GPA_MASK | | ||
154 | + R_ID_AA64ISAR1_GPI_MASK | | ||
155 | + R_ID_AA64ISAR1_FRINTTS_MASK | | ||
156 | + R_ID_AA64ISAR1_SB_MASK | | ||
157 | + R_ID_AA64ISAR1_BF16_MASK | | ||
158 | + R_ID_AA64ISAR1_DGH_MASK | | ||
159 | + R_ID_AA64ISAR1_I8MM_MASK }, | ||
160 | + { .name = "ID_AA64ISAR2_EL1", | ||
161 | + .exported_bits = R_ID_AA64ISAR2_WFXT_MASK | | ||
162 | + R_ID_AA64ISAR2_RPRES_MASK | | ||
163 | + R_ID_AA64ISAR2_GPA3_MASK | | ||
164 | + R_ID_AA64ISAR2_APA3_MASK }, | ||
165 | { .name = "ID_AA64ISAR*_EL1_RESERVED", | ||
166 | - .is_glob = true }, | ||
167 | + .is_glob = true }, | ||
168 | }; | ||
169 | modify_arm_cp_regs(v8_idregs, v8_user_idregs); | ||
170 | #endif | ||
171 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
172 | #ifdef CONFIG_USER_ONLY | ||
173 | static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { | ||
174 | { .name = "MIDR_EL1", | ||
175 | - .exported_bits = 0x00000000ffffffff }, | ||
176 | - { .name = "REVIDR_EL1" }, | ||
177 | + .exported_bits = R_MIDR_EL1_REVISION_MASK | | ||
178 | + R_MIDR_EL1_PARTNUM_MASK | | ||
179 | + R_MIDR_EL1_ARCHITECTURE_MASK | | ||
180 | + R_MIDR_EL1_VARIANT_MASK | | ||
181 | + R_MIDR_EL1_IMPLEMENTER_MASK }, | ||
182 | + { .name = "REVIDR_EL1" }, | ||
183 | }; | ||
184 | modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); | ||
185 | #endif | ||
186 | -- | 28 | -- |
187 | 2.25.1 | 29 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Timofey Kutergin <tkutergin@gmail.com> | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular | 3 | Pointer authentication on aarch64 is pretty expensive (up to 50% of |
4 | it supports the Privileged Access Never (PAN) feature. Add | 4 | execution time) when running a virtual machine with tcg and -cpu max |
5 | a model of this CPU, so you can use a CPU type on the virt | 5 | (which enables pauth=on). |
6 | board that models a specific real hardware CPU, rather than | ||
7 | having to use the QEMU-specific "max" CPU type. | ||
8 | 6 | ||
9 | Signed-off-by: Timofey Kutergin <tkutergin@gmail.com> | 7 | The advice is always: use pauth-impdef=on. |
10 | Message-id: 20221121150819.2782817-1-tkutergin@gmail.com | 8 | Our documentation even mentions it "by default" in |
11 | [PMM: tweaked commit message] | 9 | docs/system/introduction.rst. |
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | |
11 | Thus, we change the default to use impdef by default. This does not | ||
12 | affect kvm or hvf acceleration, since pauth algorithm used is the one | ||
13 | from host cpu. | ||
14 | |||
15 | This change is retro compatible, in terms of cli, with previous | ||
16 | versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu | ||
17 | max,pauth-qarma3=on is preserved. | ||
18 | The new option introduced in previous patch and matching old default is | ||
19 | -cpu max,pauth-qarma5=on. | ||
20 | It is retro compatible with migration as well, by defining a backcompat | ||
21 | property, that will use qarma5 by default for virt machine <= 9.2. | ||
22 | Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master | ||
23 | (10.0) for cpus neoverse-n2 and max. | ||
24 | |||
25 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | ||
26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
27 | Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 29 | --- |
15 | docs/system/arm/virt.rst | 1 + | 30 | docs/system/arm/cpu-features.rst | 2 +- |
16 | hw/arm/virt.c | 1 + | 31 | docs/system/introduction.rst | 2 +- |
17 | target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++ | 32 | target/arm/cpu.h | 3 +++ |
18 | 3 files changed, 71 insertions(+) | 33 | hw/core/machine.c | 4 +++- |
34 | target/arm/cpu.c | 2 ++ | ||
35 | target/arm/cpu64.c | 22 ++++++++++++++++------ | ||
36 | 6 files changed, 26 insertions(+), 9 deletions(-) | ||
19 | 37 | ||
20 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 38 | diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst |
21 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/docs/system/arm/virt.rst | 40 | --- a/docs/system/arm/cpu-features.rst |
23 | +++ b/docs/system/arm/virt.rst | 41 | +++ b/docs/system/arm/cpu-features.rst |
24 | @@ -XXX,XX +XXX,XX @@ Supported guest CPU types: | 42 | @@ -XXX,XX +XXX,XX @@ Below is the list of TCG VCPU features and their descriptions. |
25 | - ``cortex-a15`` (32-bit; the default) | 43 | When ``pauth`` is enabled, select the architected QARMA5 algorithm. |
26 | - ``cortex-a35`` (64-bit) | 44 | |
27 | - ``cortex-a53`` (64-bit) | 45 | Without ``pauth-impdef``, ``pauth-qarma3`` or ``pauth-qarma5`` enabled, |
28 | +- ``cortex-a55`` (64-bit) | 46 | -the architected QARMA5 algorithm is used. The architected QARMA5 |
29 | - ``cortex-a57`` (64-bit) | 47 | +the QEMU impdef algorithm is used. The architected QARMA5 |
30 | - ``cortex-a72`` (64-bit) | 48 | and QARMA3 algorithms have good cryptographic properties, but can |
31 | - ``cortex-a76`` (64-bit) | 49 | be quite slow to emulate. The impdef algorithm used by QEMU is |
32 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 50 | non-cryptographic but significantly faster. |
51 | diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst | ||
33 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/arm/virt.c | 53 | --- a/docs/system/introduction.rst |
35 | +++ b/hw/arm/virt.c | 54 | +++ b/docs/system/introduction.rst |
36 | @@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = { | 55 | @@ -XXX,XX +XXX,XX @@ would default to it anyway. |
37 | ARM_CPU_TYPE_NAME("cortex-a15"), | 56 | |
38 | ARM_CPU_TYPE_NAME("cortex-a35"), | 57 | .. code:: |
39 | ARM_CPU_TYPE_NAME("cortex-a53"), | 58 | |
40 | + ARM_CPU_TYPE_NAME("cortex-a55"), | 59 | - -cpu max,pauth-impdef=on \ |
41 | ARM_CPU_TYPE_NAME("cortex-a57"), | 60 | + -cpu max \ |
42 | ARM_CPU_TYPE_NAME("cortex-a72"), | 61 | -smp 4 \ |
43 | ARM_CPU_TYPE_NAME("cortex-a76"), | 62 | -accel tcg \ |
63 | |||
64 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/cpu.h | ||
67 | +++ b/target/arm/cpu.h | ||
68 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
69 | /* QOM property to indicate we should use the back-compat CNTFRQ default */ | ||
70 | bool backcompat_cntfrq; | ||
71 | |||
72 | + /* QOM property to indicate we should use the back-compat QARMA5 default */ | ||
73 | + bool backcompat_pauth_default_use_qarma5; | ||
74 | + | ||
75 | /* Specify the number of cores in this CPU cluster. Used for the L2CTLR | ||
76 | * register. | ||
77 | */ | ||
78 | diff --git a/hw/core/machine.c b/hw/core/machine.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/core/machine.c | ||
81 | +++ b/hw/core/machine.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | ||
83 | #include "hw/virtio/virtio-iommu.h" | ||
84 | #include "audio/audio.h" | ||
85 | |||
86 | -GlobalProperty hw_compat_9_2[] = {}; | ||
87 | +GlobalProperty hw_compat_9_2[] = { | ||
88 | + {"arm-cpu", "backcompat-pauth-default-use-qarma5", "true"}, | ||
89 | +}; | ||
90 | const size_t hw_compat_9_2_len = G_N_ELEMENTS(hw_compat_9_2); | ||
91 | |||
92 | GlobalProperty hw_compat_9_1[] = { | ||
93 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/cpu.c | ||
96 | +++ b/target/arm/cpu.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static const Property arm_cpu_properties[] = { | ||
98 | DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), | ||
99 | /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ | ||
100 | DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), | ||
101 | + DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, | ||
102 | + backcompat_pauth_default_use_qarma5, false), | ||
103 | }; | ||
104 | |||
105 | static const gchar *arm_gdb_arch_name(CPUState *cs) | ||
44 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 106 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
45 | index XXXXXXX..XXXXXXX 100644 | 107 | index XXXXXXX..XXXXXXX 100644 |
46 | --- a/target/arm/cpu64.c | 108 | --- a/target/arm/cpu64.c |
47 | +++ b/target/arm/cpu64.c | 109 | +++ b/target/arm/cpu64.c |
48 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | 110 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) |
49 | define_cortex_a72_a57_a53_cp_reginfo(cpu); | 111 | return; |
50 | } | 112 | } |
51 | 113 | ||
52 | +static void aarch64_a55_initfn(Object *obj) | 114 | - if (cpu->prop_pauth_impdef) { |
53 | +{ | 115 | - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); |
54 | + ARMCPU *cpu = ARM_CPU(obj); | 116 | - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); |
117 | + bool use_default = !cpu->prop_pauth_qarma5 && | ||
118 | + !cpu->prop_pauth_qarma3 && | ||
119 | + !cpu->prop_pauth_impdef; | ||
55 | + | 120 | + |
56 | + cpu->dtb_compatible = "arm,cortex-a55"; | 121 | + if (cpu->prop_pauth_qarma5 || |
57 | + set_feature(&cpu->env, ARM_FEATURE_V8); | 122 | + (use_default && |
58 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | 123 | + cpu->backcompat_pauth_default_use_qarma5)) { |
59 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | 124 | + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); |
60 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | 125 | + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); |
61 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | 126 | } else if (cpu->prop_pauth_qarma3) { |
62 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | 127 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); |
63 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | 128 | isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); |
64 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | 129 | - } else { /* default is pauth-qarma5 */ |
65 | + | 130 | - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); |
66 | + /* Ordered by B2.4 AArch64 registers by functional group */ | 131 | - isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); |
67 | + cpu->clidr = 0x82000023; | 132 | + } else if (cpu->prop_pauth_impdef || |
68 | + cpu->ctr = 0x84448004; /* L1Ip = VIPT */ | 133 | + (use_default && |
69 | + cpu->dcz_blocksize = 4; /* 64 bytes */ | 134 | + !cpu->backcompat_pauth_default_use_qarma5)) { |
70 | + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; | 135 | + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); |
71 | + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; | 136 | + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); |
72 | + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; | 137 | + } else { |
73 | + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; | 138 | + g_assert_not_reached(); |
74 | + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; | 139 | } |
75 | + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; | 140 | } else if (cpu->prop_pauth_impdef || |
76 | + cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; | 141 | cpu->prop_pauth_qarma3 || |
77 | + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; | ||
78 | + cpu->id_afr0 = 0x00000000; | ||
79 | + cpu->isar.id_dfr0 = 0x04010088; | ||
80 | + cpu->isar.id_isar0 = 0x02101110; | ||
81 | + cpu->isar.id_isar1 = 0x13112111; | ||
82 | + cpu->isar.id_isar2 = 0x21232042; | ||
83 | + cpu->isar.id_isar3 = 0x01112131; | ||
84 | + cpu->isar.id_isar4 = 0x00011142; | ||
85 | + cpu->isar.id_isar5 = 0x01011121; | ||
86 | + cpu->isar.id_isar6 = 0x00000010; | ||
87 | + cpu->isar.id_mmfr0 = 0x10201105; | ||
88 | + cpu->isar.id_mmfr1 = 0x40000000; | ||
89 | + cpu->isar.id_mmfr2 = 0x01260000; | ||
90 | + cpu->isar.id_mmfr3 = 0x02122211; | ||
91 | + cpu->isar.id_mmfr4 = 0x00021110; | ||
92 | + cpu->isar.id_pfr0 = 0x10010131; | ||
93 | + cpu->isar.id_pfr1 = 0x00011011; | ||
94 | + cpu->isar.id_pfr2 = 0x00000011; | ||
95 | + cpu->midr = 0x412FD050; /* r2p0 */ | ||
96 | + cpu->revidr = 0; | ||
97 | + | ||
98 | + /* From B2.23 CCSIDR_EL1 */ | ||
99 | + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ | ||
100 | + cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ | ||
101 | + cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ | ||
102 | + | ||
103 | + /* From B2.96 SCTLR_EL3 */ | ||
104 | + cpu->reset_sctlr = 0x30c50838; | ||
105 | + | ||
106 | + /* From B4.45 ICH_VTR_EL2 */ | ||
107 | + cpu->gic_num_lrs = 4; | ||
108 | + cpu->gic_vpribits = 5; | ||
109 | + cpu->gic_vprebits = 5; | ||
110 | + cpu->gic_pribits = 5; | ||
111 | + | ||
112 | + cpu->isar.mvfr0 = 0x10110222; | ||
113 | + cpu->isar.mvfr1 = 0x13211111; | ||
114 | + cpu->isar.mvfr2 = 0x00000043; | ||
115 | + | ||
116 | + /* From D5.4 AArch64 PMU register summary */ | ||
117 | + cpu->isar.reset_pmcr_el0 = 0x410b3000; | ||
118 | +} | ||
119 | + | ||
120 | static void aarch64_a72_initfn(Object *obj) | ||
121 | { | ||
122 | ARMCPU *cpu = ARM_CPU(obj); | ||
123 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = { | ||
124 | { .name = "cortex-a35", .initfn = aarch64_a35_initfn }, | ||
125 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
126 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
127 | + { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, | ||
128 | { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
129 | { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, | ||
130 | { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, | ||
131 | -- | 142 | -- |
132 | 2.25.1 | 143 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Gavin Shan <gshan@redhat.com> | 1 | From: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | After the improvement to high memory region address assignment is | 3 | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> |
4 | applied, the memory layout can be changed, introducing possible | 4 | Message-id: 20241219183211.3493974-4-pierrick.bouvier@linaro.org |
5 | migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region | 5 | [PMM: Removed a paragraph about using non-versioned models.] |
6 | is disabled or enabled when the optimization is applied or not, with | ||
7 | the following configuration. The configuration is only achievable by | ||
8 | modifying the source code until more properties are added to allow | ||
9 | users selectively disable those high memory regions. | ||
10 | |||
11 | pa_bits = 40; | ||
12 | vms->highmem_redists = false; | ||
13 | vms->highmem_ecam = false; | ||
14 | vms->highmem_mmio = true; | ||
15 | |||
16 | # qemu-system-aarch64 -accel kvm -cpu host \ | ||
17 | -machine virt-7.2,compact-highmem={on, off} \ | ||
18 | -m 4G,maxmem=511G -monitor stdio | ||
19 | |||
20 | Region compact-highmem=off compact-highmem=on | ||
21 | ---------------------------------------------------------------- | ||
22 | MEM [1GB 512GB] [1GB 512GB] | ||
23 | HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled] | ||
24 | HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled] | ||
25 | HIGH_PCIE_MMIO [disabled] [512GB 1TB] | ||
26 | |||
27 | In order to keep backwords compatibility, we need to disable the | ||
28 | optimization on machine, which is virt-7.1 or ealier than it. It | ||
29 | means the optimization is enabled by default from virt-7.2. Besides, | ||
30 | 'compact-highmem' property is added so that the optimization can be | ||
31 | explicitly enabled or disabled on all machine types by users. | ||
32 | |||
33 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
34 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
35 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
36 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
37 | Tested-by: Zhenyu Zhang <zhenyzha@redhat.com> | ||
38 | Message-id: 20221029224307.138822-7-gshan@redhat.com | ||
39 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
40 | --- | 7 | --- |
41 | docs/system/arm/virt.rst | 4 ++++ | 8 | docs/system/arm/virt.rst | 4 ++++ |
42 | include/hw/arm/virt.h | 1 + | 9 | 1 file changed, 4 insertions(+) |
43 | hw/arm/virt.c | 32 ++++++++++++++++++++++++++++++++ | ||
44 | 3 files changed, 37 insertions(+) | ||
45 | 10 | ||
46 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | 11 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst |
47 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
48 | --- a/docs/system/arm/virt.rst | 13 | --- a/docs/system/arm/virt.rst |
49 | +++ b/docs/system/arm/virt.rst | 14 | +++ b/docs/system/arm/virt.rst |
50 | @@ -XXX,XX +XXX,XX @@ highmem | 15 | @@ -XXX,XX +XXX,XX @@ of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration |
51 | address space above 32 bits. The default is ``on`` for machine types | 16 | is not guaranteed to work between different QEMU releases for |
52 | later than ``virt-2.12``. | 17 | the non-versioned ``virt`` machine type. |
53 | 18 | ||
54 | +compact-highmem | 19 | +VM migration is not guaranteed when using ``-cpu max``, as features |
55 | + Set ``on``/``off`` to enable/disable the compact layout for high memory regions. | 20 | +supported may change between QEMU versions. To ensure your VM can be |
56 | + The default is ``on`` for machine types later than ``virt-7.2``. | 21 | +migrated, it is recommended to use another cpu model instead. |
57 | + | 22 | + |
58 | gic-version | 23 | Supported devices |
59 | Specify the version of the Generic Interrupt Controller (GIC) to provide. | 24 | """"""""""""""""" |
60 | Valid values are: | ||
61 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/include/hw/arm/virt.h | ||
64 | +++ b/include/hw/arm/virt.h | ||
65 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineClass { | ||
66 | bool no_pmu; | ||
67 | bool claim_edge_triggered_timers; | ||
68 | bool smbios_old_sys_ver; | ||
69 | + bool no_highmem_compact; | ||
70 | bool no_highmem_ecam; | ||
71 | bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */ | ||
72 | bool kvm_no_adjvtime; | ||
73 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/arm/virt.c | ||
76 | +++ b/hw/arm/virt.c | ||
77 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = { | ||
78 | * Note the extended_memmap is sized so that it eventually also includes the | ||
79 | * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last | ||
80 | * index of base_memmap). | ||
81 | + * | ||
82 | + * The memory map for these Highmem IO Regions can be in legacy or compact | ||
83 | + * layout, depending on 'compact-highmem' property. With legacy layout, the | ||
84 | + * PA space for one specific region is always reserved, even if the region | ||
85 | + * has been disabled or doesn't fit into the PA space. However, the PA space | ||
86 | + * for the region won't be reserved in these circumstances with compact layout. | ||
87 | */ | ||
88 | static MemMapEntry extended_memmap[] = { | ||
89 | /* Additional 64 MB redist region (can contain up to 512 redistributors) */ | ||
90 | @@ -XXX,XX +XXX,XX @@ static void virt_set_highmem(Object *obj, bool value, Error **errp) | ||
91 | vms->highmem = value; | ||
92 | } | ||
93 | |||
94 | +static bool virt_get_compact_highmem(Object *obj, Error **errp) | ||
95 | +{ | ||
96 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
97 | + | ||
98 | + return vms->highmem_compact; | ||
99 | +} | ||
100 | + | ||
101 | +static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) | ||
102 | +{ | ||
103 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
104 | + | ||
105 | + vms->highmem_compact = value; | ||
106 | +} | ||
107 | + | ||
108 | static bool virt_get_its(Object *obj, Error **errp) | ||
109 | { | ||
110 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
111 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
112 | "Set on/off to enable/disable using " | ||
113 | "physical address space above 32 bits"); | ||
114 | |||
115 | + object_class_property_add_bool(oc, "compact-highmem", | ||
116 | + virt_get_compact_highmem, | ||
117 | + virt_set_compact_highmem); | ||
118 | + object_class_property_set_description(oc, "compact-highmem", | ||
119 | + "Set on/off to enable/disable compact " | ||
120 | + "layout for high memory regions"); | ||
121 | + | ||
122 | object_class_property_add_str(oc, "gic-version", virt_get_gic_version, | ||
123 | virt_set_gic_version); | ||
124 | object_class_property_set_description(oc, "gic-version", | ||
125 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | ||
126 | |||
127 | /* High memory is enabled by default */ | ||
128 | vms->highmem = true; | ||
129 | + vms->highmem_compact = !vmc->no_highmem_compact; | ||
130 | vms->gic_version = VIRT_GIC_VERSION_NOSEL; | ||
131 | |||
132 | vms->highmem_ecam = !vmc->no_highmem_ecam; | ||
133 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2) | ||
134 | |||
135 | static void virt_machine_7_1_options(MachineClass *mc) | ||
136 | { | ||
137 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
138 | + | ||
139 | virt_machine_7_2_options(mc); | ||
140 | compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len); | ||
141 | + /* Compact layout for high memory regions was introduced with 7.2 */ | ||
142 | + vmc->no_highmem_compact = true; | ||
143 | } | ||
144 | DEFINE_VIRT_MACHINE(7, 1) | ||
145 | 25 | ||
146 | -- | 26 | -- |
147 | 2.25.1 | 27 | 2.34.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Gavin Shan <gshan@redhat.com> | ||
2 | 1 | ||
3 | The 3 high memory regions are usually enabled by default, but they may | ||
4 | be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2. | ||
5 | This leads to waste in the PA space. | ||
6 | |||
7 | Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to | ||
8 | allow users selectively disable them if needed. After that, the high | ||
9 | memory region for GICv3 or GICv4 redistributor can be disabled by user, | ||
10 | the number of maximal supported CPUs needs to be calculated based on | ||
11 | 'vms->highmem_redists'. The follow-up error message is also improved | ||
12 | to indicate if the high memory region for GICv3 and GICv4 has been | ||
13 | enabled or not. | ||
14 | |||
15 | Suggested-by: Marc Zyngier <maz@kernel.org> | ||
16 | Signed-off-by: Gavin Shan <gshan@redhat.com> | ||
17 | Reviewed-by: Marc Zyngier <maz@kernel.org> | ||
18 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
19 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
20 | Message-id: 20221029224307.138822-8-gshan@redhat.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | docs/system/arm/virt.rst | 13 +++++++ | ||
24 | hw/arm/virt.c | 75 ++++++++++++++++++++++++++++++++++++++-- | ||
25 | 2 files changed, 86 insertions(+), 2 deletions(-) | ||
26 | |||
27 | diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/docs/system/arm/virt.rst | ||
30 | +++ b/docs/system/arm/virt.rst | ||
31 | @@ -XXX,XX +XXX,XX @@ compact-highmem | ||
32 | Set ``on``/``off`` to enable/disable the compact layout for high memory regions. | ||
33 | The default is ``on`` for machine types later than ``virt-7.2``. | ||
34 | |||
35 | +highmem-redists | ||
36 | + Set ``on``/``off`` to enable/disable the high memory region for GICv3 or | ||
37 | + GICv4 redistributor. The default is ``on``. Setting this to ``off`` will | ||
38 | + limit the maximum number of CPUs when GICv3 or GICv4 is used. | ||
39 | + | ||
40 | +highmem-ecam | ||
41 | + Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM. | ||
42 | + The default is ``on`` for machine types later than ``virt-3.0``. | ||
43 | + | ||
44 | +highmem-mmio | ||
45 | + Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO. | ||
46 | + The default is ``on``. | ||
47 | + | ||
48 | gic-version | ||
49 | Specify the version of the Generic Interrupt Controller (GIC) to provide. | ||
50 | Valid values are: | ||
51 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/hw/arm/virt.c | ||
54 | +++ b/hw/arm/virt.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
56 | if (vms->gic_version == VIRT_GIC_VERSION_2) { | ||
57 | virt_max_cpus = GIC_NCPU; | ||
58 | } else { | ||
59 | - virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + | ||
60 | - virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); | ||
61 | + virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST); | ||
62 | + if (vms->highmem_redists) { | ||
63 | + virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); | ||
64 | + } | ||
65 | } | ||
66 | |||
67 | if (max_cpus > virt_max_cpus) { | ||
68 | error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " | ||
69 | "supported by machine 'mach-virt' (%d)", | ||
70 | max_cpus, virt_max_cpus); | ||
71 | + if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) { | ||
72 | + error_printf("Try 'highmem-redists=on' for more CPUs\n"); | ||
73 | + } | ||
74 | + | ||
75 | exit(1); | ||
76 | } | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp) | ||
79 | vms->highmem_compact = value; | ||
80 | } | ||
81 | |||
82 | +static bool virt_get_highmem_redists(Object *obj, Error **errp) | ||
83 | +{ | ||
84 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
85 | + | ||
86 | + return vms->highmem_redists; | ||
87 | +} | ||
88 | + | ||
89 | +static void virt_set_highmem_redists(Object *obj, bool value, Error **errp) | ||
90 | +{ | ||
91 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
92 | + | ||
93 | + vms->highmem_redists = value; | ||
94 | +} | ||
95 | + | ||
96 | +static bool virt_get_highmem_ecam(Object *obj, Error **errp) | ||
97 | +{ | ||
98 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
99 | + | ||
100 | + return vms->highmem_ecam; | ||
101 | +} | ||
102 | + | ||
103 | +static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp) | ||
104 | +{ | ||
105 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
106 | + | ||
107 | + vms->highmem_ecam = value; | ||
108 | +} | ||
109 | + | ||
110 | +static bool virt_get_highmem_mmio(Object *obj, Error **errp) | ||
111 | +{ | ||
112 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
113 | + | ||
114 | + return vms->highmem_mmio; | ||
115 | +} | ||
116 | + | ||
117 | +static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp) | ||
118 | +{ | ||
119 | + VirtMachineState *vms = VIRT_MACHINE(obj); | ||
120 | + | ||
121 | + vms->highmem_mmio = value; | ||
122 | +} | ||
123 | + | ||
124 | + | ||
125 | static bool virt_get_its(Object *obj, Error **errp) | ||
126 | { | ||
127 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
128 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
129 | "Set on/off to enable/disable compact " | ||
130 | "layout for high memory regions"); | ||
131 | |||
132 | + object_class_property_add_bool(oc, "highmem-redists", | ||
133 | + virt_get_highmem_redists, | ||
134 | + virt_set_highmem_redists); | ||
135 | + object_class_property_set_description(oc, "highmem-redists", | ||
136 | + "Set on/off to enable/disable high " | ||
137 | + "memory region for GICv3 or GICv4 " | ||
138 | + "redistributor"); | ||
139 | + | ||
140 | + object_class_property_add_bool(oc, "highmem-ecam", | ||
141 | + virt_get_highmem_ecam, | ||
142 | + virt_set_highmem_ecam); | ||
143 | + object_class_property_set_description(oc, "highmem-ecam", | ||
144 | + "Set on/off to enable/disable high " | ||
145 | + "memory region for PCI ECAM"); | ||
146 | + | ||
147 | + object_class_property_add_bool(oc, "highmem-mmio", | ||
148 | + virt_get_highmem_mmio, | ||
149 | + virt_set_highmem_mmio); | ||
150 | + object_class_property_set_description(oc, "highmem-mmio", | ||
151 | + "Set on/off to enable/disable high " | ||
152 | + "memory region for PCI MMIO"); | ||
153 | + | ||
154 | object_class_property_add_str(oc, "gic-version", virt_get_gic_version, | ||
155 | virt_set_gic_version); | ||
156 | object_class_property_set_description(oc, "gic-version", | ||
157 | -- | ||
158 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Mihai Carabas <mihai.carabas@oracle.com> | ||
2 | 1 | ||
3 | Use the base_memmap to build the SMBIOS 19 table which provides the address | ||
4 | mapping for a Physical Memory Array (from spec [1] chapter 7.20). | ||
5 | |||
6 | This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5 | ||
7 | ("SMBIOS: Build aggregate smbios tables and entry point"). | ||
8 | |||
9 | [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf | ||
10 | |||
11 | The absence of this table is a breach of the specs and is | ||
12 | detected by the FirmwareTestSuite (FWTS), but it doesn't | ||
13 | cause any known problems for guest OSes. | ||
14 | |||
15 | Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com> | ||
16 | Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | hw/arm/virt.c | 8 +++++++- | ||
21 | 1 file changed, 7 insertions(+), 1 deletion(-) | ||
22 | |||
23 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/hw/arm/virt.c | ||
26 | +++ b/hw/arm/virt.c | ||
27 | @@ -XXX,XX +XXX,XX @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) | ||
28 | static void virt_build_smbios(VirtMachineState *vms) | ||
29 | { | ||
30 | MachineClass *mc = MACHINE_GET_CLASS(vms); | ||
31 | + MachineState *ms = MACHINE(vms); | ||
32 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | ||
33 | uint8_t *smbios_tables, *smbios_anchor; | ||
34 | size_t smbios_tables_len, smbios_anchor_len; | ||
35 | + struct smbios_phys_mem_area mem_array; | ||
36 | const char *product = "QEMU Virtual Machine"; | ||
37 | |||
38 | if (kvm_enabled()) { | ||
39 | @@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(VirtMachineState *vms) | ||
40 | vmc->smbios_old_sys_ver ? "1.0" : mc->name, false, | ||
41 | true, SMBIOS_ENTRY_POINT_TYPE_64); | ||
42 | |||
43 | - smbios_get_tables(MACHINE(vms), NULL, 0, | ||
44 | + /* build the array of physical mem area from base_memmap */ | ||
45 | + mem_array.address = vms->memmap[VIRT_MEM].base; | ||
46 | + mem_array.length = ms->ram_size; | ||
47 | + | ||
48 | + smbios_get_tables(ms, &mem_array, 1, | ||
49 | &smbios_tables, &smbios_tables_len, | ||
50 | &smbios_anchor, &smbios_anchor_len, | ||
51 | &error_fatal); | ||
52 | -- | ||
53 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Luke Starrett <lukes@xsightlabs.com> | ||
2 | 1 | ||
3 | The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER | ||
4 | register: | ||
5 | |||
6 | "indicates the maximum SPI INTID that the GIC implementation supports" | ||
7 | |||
8 | As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted | ||
9 | for the internal 16x SGI's and 16x PPI's. However, the original GICv3 | ||
10 | model subtracted off the SGI/PPI. Cosmetically this can be seen at OS | ||
11 | boot (Linux) showing 32 shy of what should be there, i.e.: | ||
12 | |||
13 | [ 0.000000] GICv3: 224 SPIs implemented | ||
14 | |||
15 | Though in hw/arm/virt.c, the machine is configured for 256 SPI's. ARM | ||
16 | virt machine likely doesn't have a problem with this because the upper | ||
17 | 32 IRQ's don't actually have anything meaningful wired. But, this does | ||
18 | become a functional issue on a custom use case which wants to make use | ||
19 | of these IRQ's. Additionally, boot code (i.e. TF-A) will only init up | ||
20 | to the number (blocks of 32) that it believes to actually be there. | ||
21 | |||
22 | Signed-off-by: Luke Starrett <lukes@xsightlabs.com> | ||
23 | Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
26 | --- | ||
27 | hw/intc/arm_gicv3_dist.c | 4 ++-- | ||
28 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
29 | |||
30 | diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/intc/arm_gicv3_dist.c | ||
33 | +++ b/hw/intc/arm_gicv3_dist.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset, | ||
35 | * MBIS == 0 (message-based SPIs not supported) | ||
36 | * SecurityExtn == 1 if security extns supported | ||
37 | * CPUNumber == 0 since for us ARE is always 1 | ||
38 | - * ITLinesNumber == (num external irqs / 32) - 1 | ||
39 | + * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1) | ||
40 | */ | ||
41 | - int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1; | ||
42 | + int itlinesnumber = (s->num_irq / 32) - 1; | ||
43 | /* | ||
44 | * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and | ||
45 | * "security extensions not supported" always implies DS == 1, | ||
46 | -- | ||
47 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS, | ||
2 | TICAB, TOCU and TID4. These allow the guest to enable trapping of | ||
3 | various EL1 instructions to EL2. In this commit, add the necessary | ||
4 | code to allow the guest to set these bits if the feature is present; | ||
5 | because the bit is always zero when the feature isn't present we | ||
6 | won't need to use explicit feature checks in the "trap on condition" | ||
7 | tests in the following commits. | ||
8 | 1 | ||
9 | Note that although full implementation of the feature (mandatory from | ||
10 | Armv8.5 onward) requires all five trap bits, the ID registers permit | ||
11 | a value indicating that only TICAB, TOCU and TID4 are implemented, | ||
12 | which might be the case for CPUs between Armv8.2 and Armv8.5. | ||
13 | |||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | --- | ||
17 | target/arm/cpu.h | 30 ++++++++++++++++++++++++++++++ | ||
18 | target/arm/helper.c | 6 ++++++ | ||
19 | 2 files changed, 36 insertions(+) | ||
20 | |||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/cpu.h | ||
24 | +++ b/target/arm/cpu.h | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) | ||
26 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; | ||
27 | } | ||
28 | |||
29 | +static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id) | ||
30 | +{ | ||
31 | + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1; | ||
32 | +} | ||
33 | + | ||
34 | +static inline bool isar_feature_aa32_evt(const ARMISARegisters *id) | ||
35 | +{ | ||
36 | + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2; | ||
37 | +} | ||
38 | + | ||
39 | static inline bool isar_feature_aa32_dit(const ARMISARegisters *id) | ||
40 | { | ||
41 | return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0; | ||
42 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id) | ||
43 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0; | ||
44 | } | ||
45 | |||
46 | +static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id) | ||
47 | +{ | ||
48 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1; | ||
49 | +} | ||
50 | + | ||
51 | +static inline bool isar_feature_aa64_evt(const ARMISARegisters *id) | ||
52 | +{ | ||
53 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2; | ||
54 | +} | ||
55 | + | ||
56 | static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | ||
57 | { | ||
58 | return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id) | ||
60 | return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); | ||
61 | } | ||
62 | |||
63 | +static inline bool isar_feature_any_half_evt(const ARMISARegisters *id) | ||
64 | +{ | ||
65 | + return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id); | ||
66 | +} | ||
67 | + | ||
68 | +static inline bool isar_feature_any_evt(const ARMISARegisters *id) | ||
69 | +{ | ||
70 | + return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id); | ||
71 | +} | ||
72 | + | ||
73 | /* | ||
74 | * Forward to the above feature tests given an ARMCPU pointer. | ||
75 | */ | ||
76 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/helper.c | ||
79 | +++ b/target/arm/helper.c | ||
80 | @@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) | ||
81 | } | ||
82 | } | ||
83 | |||
84 | + if (cpu_isar_feature(any_evt, cpu)) { | ||
85 | + valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4; | ||
86 | + } else if (cpu_isar_feature(any_half_evt, cpu)) { | ||
87 | + valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4; | ||
88 | + } | ||
89 | + | ||
90 | /* Clear RES0 bits. */ | ||
91 | value &= valid_mask; | ||
92 | |||
93 | -- | ||
94 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1 | ||
2 | use of TLB maintenance instructions that operate on the | ||
3 | outer shareable domain: | ||
4 | 1 | ||
5 | TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS, | ||
6 | TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS, | ||
7 | TLBI RVALE1OS, and TLBI RVAALE1OS. | ||
8 | |||
9 | (There are no AArch32 outer-shareable TLB maintenance ops.) | ||
10 | |||
11 | Implement the trapping. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | --- | ||
16 | target/arm/helper.c | 33 +++++++++++++++++++++++---------- | ||
17 | 1 file changed, 23 insertions(+), 10 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/helper.c | ||
22 | +++ b/target/arm/helper.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri, | ||
24 | return CP_ACCESS_OK; | ||
25 | } | ||
26 | |||
27 | +#ifdef TARGET_AARCH64 | ||
28 | +/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */ | ||
29 | +static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri, | ||
30 | + bool isread) | ||
31 | +{ | ||
32 | + if (arm_current_el(env) == 1 && | ||
33 | + (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) { | ||
34 | + return CP_ACCESS_TRAP_EL2; | ||
35 | + } | ||
36 | + return CP_ACCESS_OK; | ||
37 | +} | ||
38 | +#endif | ||
39 | + | ||
40 | static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) | ||
41 | { | ||
42 | ARMCPU *cpu = env_archcpu(env); | ||
43 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
44 | .writefn = tlbi_aa64_rvae1is_write }, | ||
45 | { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, | ||
46 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, | ||
47 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
48 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
49 | .writefn = tlbi_aa64_rvae1is_write }, | ||
50 | { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, | ||
51 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, | ||
52 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
53 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
54 | .writefn = tlbi_aa64_rvae1is_write }, | ||
55 | { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, | ||
56 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, | ||
57 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
58 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
59 | .writefn = tlbi_aa64_rvae1is_write }, | ||
60 | { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, | ||
61 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, | ||
62 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
63 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
64 | .writefn = tlbi_aa64_rvae1is_write }, | ||
65 | { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, | ||
66 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, | ||
67 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = { | ||
68 | static const ARMCPRegInfo tlbios_reginfo[] = { | ||
69 | { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, | ||
70 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, | ||
71 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
72 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
73 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
74 | { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64, | ||
75 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1, | ||
76 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
77 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
78 | .writefn = tlbi_aa64_vae1is_write }, | ||
79 | { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, | ||
80 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, | ||
81 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
82 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
83 | .writefn = tlbi_aa64_vmalle1is_write }, | ||
84 | { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64, | ||
85 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3, | ||
86 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
87 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
88 | .writefn = tlbi_aa64_vae1is_write }, | ||
89 | { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64, | ||
90 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5, | ||
91 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
92 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
93 | .writefn = tlbi_aa64_vae1is_write }, | ||
94 | { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64, | ||
95 | .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7, | ||
96 | - .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW, | ||
97 | + .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW, | ||
98 | .writefn = tlbi_aa64_vae1is_write }, | ||
99 | { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, | ||
100 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, | ||
101 | -- | ||
102 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS | ||
2 | and IC IALLUIS cache maintenance instructions. | ||
3 | 1 | ||
4 | The HCR_EL2.TOCU bit traps all the other cache maintenance | ||
5 | instructions that operate to the point of unification: | ||
6 | AArch64 IC IVAU, IC IALLU, DC CVAU | ||
7 | AArch32 ICIMVAU, ICIALLU, DCCMVAU | ||
8 | |||
9 | The two trap bits between them cover all of the cache maintenance | ||
10 | instructions which must also check the HCR_TPU flag. Turn the old | ||
11 | aa64_cacheop_pou_access() function into a helper function which takes | ||
12 | the set of HCR_EL2 flags to check as an argument, and call it from | ||
13 | new access_ticab() and access_tocu() functions as appropriate for | ||
14 | each cache op. | ||
15 | |||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
18 | --- | ||
19 | target/arm/helper.c | 36 +++++++++++++++++++++++------------- | ||
20 | 1 file changed, 23 insertions(+), 13 deletions(-) | ||
21 | |||
22 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/helper.c | ||
25 | +++ b/target/arm/helper.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, | ||
27 | return CP_ACCESS_OK; | ||
28 | } | ||
29 | |||
30 | -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, | ||
31 | - const ARMCPRegInfo *ri, | ||
32 | - bool isread) | ||
33 | +static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags) | ||
34 | { | ||
35 | /* Cache invalidate/clean to Point of Unification... */ | ||
36 | switch (arm_current_el(env)) { | ||
37 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, | ||
38 | } | ||
39 | /* fall through */ | ||
40 | case 1: | ||
41 | - /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ | ||
42 | - if (arm_hcr_el2_eff(env) & HCR_TPU) { | ||
43 | + /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */ | ||
44 | + if (arm_hcr_el2_eff(env) & hcrflags) { | ||
45 | return CP_ACCESS_TRAP_EL2; | ||
46 | } | ||
47 | break; | ||
48 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, | ||
49 | return CP_ACCESS_OK; | ||
50 | } | ||
51 | |||
52 | +static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri, | ||
53 | + bool isread) | ||
54 | +{ | ||
55 | + return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU); | ||
56 | +} | ||
57 | + | ||
58 | +static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri, | ||
59 | + bool isread) | ||
60 | +{ | ||
61 | + return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU); | ||
62 | +} | ||
63 | + | ||
64 | /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions | ||
65 | * Page D4-1736 (DDI0487A.b) | ||
66 | */ | ||
67 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
68 | { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, | ||
69 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | ||
70 | .access = PL1_W, .type = ARM_CP_NOP, | ||
71 | - .accessfn = aa64_cacheop_pou_access }, | ||
72 | + .accessfn = access_ticab }, | ||
73 | { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, | ||
74 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | ||
75 | .access = PL1_W, .type = ARM_CP_NOP, | ||
76 | - .accessfn = aa64_cacheop_pou_access }, | ||
77 | + .accessfn = access_tocu }, | ||
78 | { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, | ||
80 | .access = PL0_W, .type = ARM_CP_NOP, | ||
81 | - .accessfn = aa64_cacheop_pou_access }, | ||
82 | + .accessfn = access_tocu }, | ||
83 | { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, | ||
84 | .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, | ||
85 | .access = PL1_W, .accessfn = aa64_cacheop_poc_access, | ||
86 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
87 | { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, | ||
88 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, | ||
89 | .access = PL0_W, .type = ARM_CP_NOP, | ||
90 | - .accessfn = aa64_cacheop_pou_access }, | ||
91 | + .accessfn = access_tocu }, | ||
92 | { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, | ||
93 | .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, | ||
94 | .access = PL0_W, .type = ARM_CP_NOP, | ||
95 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
96 | .writefn = tlbiipas2is_hyp_write }, | ||
97 | /* 32 bit cache operations */ | ||
98 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | ||
99 | - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
100 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab }, | ||
101 | { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6, | ||
102 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
103 | { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, | ||
104 | - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
105 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, | ||
106 | { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1, | ||
107 | - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
108 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, | ||
109 | { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6, | ||
110 | .type = ARM_CP_NOP, .access = PL1_W }, | ||
111 | { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7, | ||
112 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
113 | { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, | ||
114 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, | ||
115 | { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, | ||
116 | - .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
117 | + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu }, | ||
118 | { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, | ||
119 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access }, | ||
120 | { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, | ||
121 | -- | ||
122 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID | ||
2 | registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and | ||
3 | their AArch32 equivalents). This is a subset of the registers | ||
4 | trapped by HCR_EL2.TID2, which includes all of these and also the | ||
5 | CTR_EL0 register. | ||
6 | 1 | ||
7 | Our implementation already uses a separate access function for | ||
8 | CTR_EL0 (ctr_el0_access()), so all of the registers currently using | ||
9 | access_aa64_tid2() should also be checking TID4. Make that function | ||
10 | check both TID2 and TID4, and rename it appropriately. | ||
11 | |||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | --- | ||
15 | target/arm/helper.c | 17 +++++++++-------- | ||
16 | 1 file changed, 9 insertions(+), 8 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper.c | ||
21 | +++ b/target/arm/helper.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
23 | scr_write(env, ri, 0); | ||
24 | } | ||
25 | |||
26 | -static CPAccessResult access_aa64_tid2(CPUARMState *env, | ||
27 | - const ARMCPRegInfo *ri, | ||
28 | - bool isread) | ||
29 | +static CPAccessResult access_tid4(CPUARMState *env, | ||
30 | + const ARMCPRegInfo *ri, | ||
31 | + bool isread) | ||
32 | { | ||
33 | - if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) { | ||
34 | + if (arm_current_el(env) == 1 && | ||
35 | + (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) { | ||
36 | return CP_ACCESS_TRAP_EL2; | ||
37 | } | ||
38 | |||
39 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
40 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, | ||
41 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, | ||
42 | .access = PL1_R, | ||
43 | - .accessfn = access_aa64_tid2, | ||
44 | + .accessfn = access_tid4, | ||
45 | .readfn = ccsidr_read, .type = ARM_CP_NO_RAW }, | ||
46 | { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, | ||
48 | .access = PL1_RW, | ||
49 | - .accessfn = access_aa64_tid2, | ||
50 | + .accessfn = access_tid4, | ||
51 | .writefn = csselr_write, .resetvalue = 0, | ||
52 | .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), | ||
53 | offsetof(CPUARMState, cp15.csselr_ns) } }, | ||
54 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = { | ||
55 | { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | ||
56 | .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | ||
57 | .access = PL1_R, | ||
58 | - .accessfn = access_aa64_tid2, | ||
59 | + .accessfn = access_tid4, | ||
60 | .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | ||
61 | }; | ||
62 | |||
63 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
64 | .name = "CLIDR", .state = ARM_CP_STATE_BOTH, | ||
65 | .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1, | ||
66 | .access = PL1_R, .type = ARM_CP_CONST, | ||
67 | - .accessfn = access_aa64_tid2, | ||
68 | + .accessfn = access_tid4, | ||
69 | .resetvalue = cpu->clidr | ||
70 | }; | ||
71 | define_one_arm_cp_reg(cpu, &clidr); | ||
72 | -- | ||
73 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Update the ID registers for TCG's '-cpu max' to report the | ||
2 | FEAT_EVT Enhanced Virtualization Traps support. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | --- | ||
7 | docs/system/arm/emulation.rst | 1 + | ||
8 | target/arm/cpu64.c | 1 + | ||
9 | target/arm/cpu_tcg.c | 1 + | ||
10 | 3 files changed, 3 insertions(+) | ||
11 | |||
12 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/docs/system/arm/emulation.rst | ||
15 | +++ b/docs/system/arm/emulation.rst | ||
16 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: | ||
17 | - FEAT_DoubleFault (Double Fault Extension) | ||
18 | - FEAT_E0PD (Preventing EL0 access to halves of address maps) | ||
19 | - FEAT_ETS (Enhanced Translation Synchronization) | ||
20 | +- FEAT_EVT (Enhanced Virtualization Traps) | ||
21 | - FEAT_FCMA (Floating-point complex number instructions) | ||
22 | - FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
23 | - FEAT_FP16 (Half-precision floating-point data processing) | ||
24 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/cpu64.c | ||
27 | +++ b/target/arm/cpu64.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
29 | t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ | ||
30 | t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ | ||
31 | t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ | ||
32 | + t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */ | ||
33 | t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ | ||
34 | cpu->isar.id_aa64mmfr2 = t; | ||
35 | |||
36 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/cpu_tcg.c | ||
39 | +++ b/target/arm/cpu_tcg.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) | ||
41 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
42 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
43 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ | ||
44 | + t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */ | ||
45 | cpu->isar.id_mmfr4 = t; | ||
46 | |||
47 | t = cpu->isar.id_mmfr5; | ||
48 | -- | ||
49 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method | ||
2 | doesn't do anything that's invalid in the hold phase, so the | ||
3 | conversion is simple and not a behaviour change. | ||
4 | 1 | ||
5 | Note that we must convert this base class before we can convert the | ||
6 | TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable | ||
7 | handles "chain to parent class reset" when the base class is 3-phase | ||
8 | and the subclass is still using legacy reset, but not the other way | ||
9 | around. | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
15 | Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org | ||
16 | --- | ||
17 | hw/arm/smmu-common.c | 7 ++++--- | ||
18 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/smmu-common.c | ||
23 | +++ b/hw/arm/smmu-common.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp) | ||
25 | } | ||
26 | } | ||
27 | |||
28 | -static void smmu_base_reset(DeviceState *dev) | ||
29 | +static void smmu_base_reset_hold(Object *obj) | ||
30 | { | ||
31 | - SMMUState *s = ARM_SMMU(dev); | ||
32 | + SMMUState *s = ARM_SMMU(obj); | ||
33 | |||
34 | g_hash_table_remove_all(s->configs); | ||
35 | g_hash_table_remove_all(s->iotlb); | ||
36 | @@ -XXX,XX +XXX,XX @@ static Property smmu_dev_properties[] = { | ||
37 | static void smmu_base_class_init(ObjectClass *klass, void *data) | ||
38 | { | ||
39 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
40 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
41 | SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass); | ||
42 | |||
43 | device_class_set_props(dc, smmu_dev_properties); | ||
44 | device_class_set_parent_realize(dc, smmu_base_realize, | ||
45 | &sbc->parent_realize); | ||
46 | - dc->reset = smmu_base_reset; | ||
47 | + rc->phases.hold = smmu_base_reset_hold; | ||
48 | } | ||
49 | |||
50 | static const TypeInfo smmu_base_info = { | ||
51 | -- | ||
52 | 2.25.1 | ||
53 | |||
54 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy | ||
2 | reset method doesn't do anything that's invalid in the hold phase, so | ||
3 | the conversion only requires changing it to a hold phase method, and | ||
4 | using the 3-phase versions of the "save the parent reset method and | ||
5 | chain to it" code. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/arm/smmuv3.h | 2 +- | ||
14 | hw/arm/smmuv3.c | 12 ++++++++---- | ||
15 | 2 files changed, 9 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/hw/arm/smmuv3.h | ||
20 | +++ b/include/hw/arm/smmuv3.h | ||
21 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3Class { | ||
22 | /*< public >*/ | ||
23 | |||
24 | DeviceRealize parent_realize; | ||
25 | - DeviceReset parent_reset; | ||
26 | + ResettablePhases parent_phases; | ||
27 | }; | ||
28 | |||
29 | #define TYPE_ARM_SMMUV3 "arm-smmuv3" | ||
30 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/arm/smmuv3.c | ||
33 | +++ b/hw/arm/smmuv3.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev) | ||
35 | } | ||
36 | } | ||
37 | |||
38 | -static void smmu_reset(DeviceState *dev) | ||
39 | +static void smmu_reset_hold(Object *obj) | ||
40 | { | ||
41 | - SMMUv3State *s = ARM_SMMUV3(dev); | ||
42 | + SMMUv3State *s = ARM_SMMUV3(obj); | ||
43 | SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s); | ||
44 | |||
45 | - c->parent_reset(dev); | ||
46 | + if (c->parent_phases.hold) { | ||
47 | + c->parent_phases.hold(obj); | ||
48 | + } | ||
49 | |||
50 | smmuv3_init_regs(s); | ||
51 | } | ||
52 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_instance_init(Object *obj) | ||
53 | static void smmuv3_class_init(ObjectClass *klass, void *data) | ||
54 | { | ||
55 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
56 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
57 | SMMUv3Class *c = ARM_SMMUV3_CLASS(klass); | ||
58 | |||
59 | dc->vmsd = &vmstate_smmuv3; | ||
60 | - device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset); | ||
61 | + resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL, | ||
62 | + &c->parent_phases); | ||
63 | c->parent_realize = dc->realize; | ||
64 | dc->realize = smmu_realize; | ||
65 | } | ||
66 | -- | ||
67 | 2.25.1 | ||
68 | |||
69 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a | ||
2 | simple no-behaviour-change conversion. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/intc/arm_gic_common.c | 7 ++++--- | ||
10 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/intc/arm_gic_common.c | ||
15 | +++ b/hw/intc/arm_gic_common.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu, | ||
17 | } | ||
18 | } | ||
19 | |||
20 | -static void arm_gic_common_reset(DeviceState *dev) | ||
21 | +static void arm_gic_common_reset_hold(Object *obj) | ||
22 | { | ||
23 | - GICState *s = ARM_GIC_COMMON(dev); | ||
24 | + GICState *s = ARM_GIC_COMMON(obj); | ||
25 | int i, j; | ||
26 | int resetprio; | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = { | ||
29 | static void arm_gic_common_class_init(ObjectClass *klass, void *data) | ||
30 | { | ||
31 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
32 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
33 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); | ||
34 | |||
35 | - dc->reset = arm_gic_common_reset; | ||
36 | + rc->phases.hold = arm_gic_common_reset_hold; | ||
37 | dc->realize = arm_gic_common_realize; | ||
38 | device_class_set_props(dc, arm_gic_common_properties); | ||
39 | dc->vmsd = &vmstate_gic; | ||
40 | -- | ||
41 | 2.25.1 | ||
42 | |||
43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/intc/arm_gicv3_common.c | 7 ++++--- | ||
9 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
10 | |||
11 | diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/intc/arm_gicv3_common.c | ||
14 | +++ b/hw/intc/arm_gicv3_common.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj) | ||
16 | g_free(s->redist_region_count); | ||
17 | } | ||
18 | |||
19 | -static void arm_gicv3_common_reset(DeviceState *dev) | ||
20 | +static void arm_gicv3_common_reset_hold(Object *obj) | ||
21 | { | ||
22 | - GICv3State *s = ARM_GICV3_COMMON(dev); | ||
23 | + GICv3State *s = ARM_GICV3_COMMON(obj); | ||
24 | int i; | ||
25 | |||
26 | for (i = 0; i < s->num_cpu; i++) { | ||
27 | @@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = { | ||
28 | static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) | ||
29 | { | ||
30 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
31 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
32 | ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass); | ||
33 | |||
34 | - dc->reset = arm_gicv3_common_reset; | ||
35 | + rc->phases.hold = arm_gicv3_common_reset_hold; | ||
36 | dc->realize = arm_gicv3_common_realize; | ||
37 | device_class_set_props(dc, arm_gicv3_common_properties); | ||
38 | dc->vmsd = &vmstate_gicv3; | ||
39 | -- | ||
40 | 2.25.1 | ||
41 | |||
42 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/intc/arm_gicv3_its_common.c | 7 ++++--- | ||
9 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
10 | |||
11 | diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/intc/arm_gicv3_its_common.c | ||
14 | +++ b/hw/intc/arm_gicv3_its_common.c | ||
15 | @@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops, | ||
16 | msi_nonbroken = true; | ||
17 | } | ||
18 | |||
19 | -static void gicv3_its_common_reset(DeviceState *dev) | ||
20 | +static void gicv3_its_common_reset_hold(Object *obj) | ||
21 | { | ||
22 | - GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev); | ||
23 | + GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj); | ||
24 | |||
25 | s->ctlr = 0; | ||
26 | s->cbaser = 0; | ||
27 | @@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev) | ||
28 | static void gicv3_its_common_class_init(ObjectClass *klass, void *data) | ||
29 | { | ||
30 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
31 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
32 | |||
33 | - dc->reset = gicv3_its_common_reset; | ||
34 | + rc->phases.hold = gicv3_its_common_reset_hold; | ||
35 | dc->vmsd = &vmstate_its; | ||
36 | } | ||
37 | |||
38 | -- | ||
39 | 2.25.1 | ||
40 | |||
41 | diff view generated by jsdifflib |