[PULL 00/29] target-arm queue
[PULL 00/72] target-arm queue
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First arm pullreq of the 8.0 series...
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First arm pullreq of the cycle; this is mostly my softfloat NaN
2
handling series. (Lots more in my to-review queue, but I don't
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like pullreqs growing too close to a hundred patches at a time :-))
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4
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The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
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thanks
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-- PMM
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Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
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The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +0000)
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MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
16
target-arm queue:
21
target-arm queue:
17
* hw/arm/virt: Add properties to allow more granular
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
18
configuration of use of highmem space
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
19
* target/arm: Add Cortex-A55 CPU
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
20
* hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
25
* fpu: Minor NaN-related cleanups
21
* Implement FEAT_EVT
26
* MAINTAINERS: email address updates
22
* Some 3-phase-reset conversions for Arm GIC, SMMU
23
* hw/arm/boot: set initrd with #address-cells type in fdt
24
* align user-mode exposed ID registers with Linux
25
* hw/misc: Move some arm-related files from specific_ss into softmmu_ss
26
* Restrict arm_cpu_exec_interrupt() to TCG accelerator
27
27
28
----------------------------------------------------------------
28
----------------------------------------------------------------
29
Gavin Shan (7):
29
Bernhard Beschow (5):
30
hw/arm/virt: Introduce virt_set_high_memmap() helper
30
hw/net/lan9118: Extract lan9118_phy
31
hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
32
hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
33
hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
33
hw/net/lan9118_phy: Reuse MII constants
34
hw/arm/virt: Improve high memory region address assignment
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
35
hw/arm/virt: Add 'compact-highmem' property
36
hw/arm/virt: Add properties to disable high memory regions
37
35
38
Luke Starrett (1):
36
Leif Lindholm (1):
39
hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
37
MAINTAINERS: update email address for Leif Lindholm
40
38
41
Mihai Carabas (1):
39
Peter Maydell (54):
42
hw/arm/virt: build SMBIOS 19 table
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
43
94
44
Peter Maydell (15):
95
Richard Henderson (11):
45
target/arm: Allow relevant HCR bits to be written for FEAT_EVT
96
target/arm: Copy entire float_status in is_ebf
46
target/arm: Implement HCR_EL2.TTLBIS traps
97
softfloat: Inline pickNaNMulAdd
47
target/arm: Implement HCR_EL2.TTLBOS traps
98
softfloat: Use goto for default nan case in pick_nan_muladd
48
target/arm: Implement HCR_EL2.TICAB,TOCU traps
99
softfloat: Remove which from parts_pick_nan_muladd
49
target/arm: Implement HCR_EL2.TID4 traps
100
softfloat: Pad array size in pick_nan_muladd
50
target/arm: Report FEAT_EVT for TCG '-cpu max'
101
softfloat: Move propagateFloatx80NaN to softfloat.c
51
hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
52
hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
103
softfloat: Inline pickNaN
53
hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
104
softfloat: Share code between parts_pick_nan cases
54
hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
55
hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
106
softfloat: Replace WHICH with RET in parts_pick_nan
56
hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
57
hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
58
hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
59
hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
60
107
61
Philippe Mathieu-Daudé (1):
108
Vikram Garhwal (1):
62
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
109
MAINTAINERS: Add correct email address for Vikram Garhwal
63
110
64
Schspa Shi (1):
111
MAINTAINERS | 4 +-
65
hw/arm/boot: set initrd with #address-cells type in fdt
112
include/fpu/softfloat-helpers.h | 38 +++-
66
113
include/fpu/softfloat-types.h | 89 +++++++-
67
Thomas Huth (1):
114
include/hw/net/imx_fec.h | 9 +-
68
hw/misc: Move some arm-related files from specific_ss into softmmu_ss
115
include/hw/net/lan9118_phy.h | 37 ++++
69
116
include/hw/net/mii.h | 6 +
70
Timofey Kutergin (1):
117
target/mips/fpu_helper.h | 20 ++
71
target/arm: Add Cortex-A55 CPU
118
target/sparc/helper.h | 4 +-
72
119
fpu/softfloat.c | 19 ++
73
Zhuojia Shen (1):
120
hw/net/imx_fec.c | 146 ++------------
74
target/arm: align exposed ID registers with Linux
121
hw/net/lan9118.c | 137 ++-----------
75
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
76
docs/system/arm/emulation.rst | 1 +
123
linux-user/arm/nwfpe/fpa11.c | 5 +
77
docs/system/arm/virt.rst | 18 +++
124
target/alpha/cpu.c | 2 +
78
include/hw/arm/smmuv3.h | 2 +-
125
target/arm/cpu.c | 10 +
79
include/hw/arm/virt.h | 2 +
126
target/arm/tcg/vec_helper.c | 20 +-
80
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
127
target/hexagon/cpu.c | 2 +
81
target/arm/cpu.h | 30 +++++
128
target/hppa/fpu_helper.c | 12 ++
82
target/arm/kvm-consts.h | 8 +-
129
target/i386/tcg/fpu_helper.c | 12 ++
83
hw/arm/boot.c | 10 +-
130
target/loongarch/tcg/fpu_helper.c | 14 +-
84
hw/arm/smmu-common.c | 7 +-
131
target/m68k/cpu.c | 14 +-
85
hw/arm/smmuv3.c | 12 +-
132
target/m68k/fpu_helper.c | 6 +-
86
hw/arm/virt.c | 202 +++++++++++++++++++++++-----
133
target/m68k/helper.c | 6 +-
87
hw/intc/arm_gic_common.c | 7 +-
134
target/microblaze/cpu.c | 2 +
88
hw/intc/arm_gic_kvm.c | 14 +-
135
target/mips/msa.c | 10 +
89
hw/intc/arm_gicv3_common.c | 7 +-
136
target/openrisc/cpu.c | 2 +
90
hw/intc/arm_gicv3_dist.c | 4 +-
137
target/ppc/cpu_init.c | 19 ++
91
hw/intc/arm_gicv3_its.c | 14 +-
138
target/ppc/fpu_helper.c | 3 +-
92
hw/intc/arm_gicv3_its_common.c | 7 +-
139
target/riscv/cpu.c | 2 +
93
hw/intc/arm_gicv3_its_kvm.c | 14 +-
140
target/rx/cpu.c | 2 +
94
hw/intc/arm_gicv3_kvm.c | 14 +-
141
target/s390x/cpu.c | 5 +
95
hw/misc/imx6_src.c | 2 +-
142
target/sh4/cpu.c | 2 +
96
hw/misc/iotkit-sysctl.c | 1 -
143
target/sparc/cpu.c | 6 +
97
target/arm/cpu.c | 5 +-
144
target/sparc/fop_helper.c | 8 +-
98
target/arm/cpu64.c | 70 ++++++++++
145
target/sparc/translate.c | 4 +-
99
target/arm/cpu_tcg.c | 1 +
146
target/tricore/helper.c | 2 +
100
target/arm/helper.c | 231 ++++++++++++++++++++++++---------
147
target/xtensa/cpu.c | 4 +
101
hw/misc/meson.build | 11 +-
148
target/xtensa/fpu_helper.c | 3 +-
102
26 files changed, 538 insertions(+), 158 deletions(-)
149
tests/fp/fp-bench.c | 7 +
103
150
tests/fp/fp-test-log2.c | 1 +
151
tests/fp/fp-test.c | 7 +
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
154
.mailmap | 5 +-
155
hw/net/Kconfig | 5 +
156
hw/net/meson.build | 1 +
157
hw/net/trace-events | 10 +-
158
47 files changed, 778 insertions(+), 730 deletions(-)
159
create mode 100644 include/hw/net/lan9118_phy.h
160
create mode 100644 hw/net/lan9118_phy.c
diff view generated by jsdifflib
[PULL 01/29] hw/arm/virt: Introduce virt_set_high_memmap() helper
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Gavin Shan <gshan@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
This introduces virt_set_high_memmap() helper. The logic of high
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
memory region address assignment is moved to the helper. The intention
4
a common implementation by extracting a device model into its own files.
5
is to make the subsequent optimization for high memory region address
6
assignment easier.
7
5
8
No functional change intended.
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
9
13
10
Signed-off-by: Gavin Shan <gshan@redhat.com>
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
as defined by IEEE 802.3u.
12
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
16
13
Reviewed-by: Marc Zyngier <maz@kernel.org>
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
14
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Message-id: 20221029224307.138822-2-gshan@redhat.com
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
22
---
18
hw/arm/virt.c | 74 ++++++++++++++++++++++++++++-----------------------
23
include/hw/net/lan9118_phy.h | 37 ++++++++
19
1 file changed, 41 insertions(+), 33 deletions(-)
24
hw/net/lan9118.c | 137 +++++-----------------------
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
20
31
21
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
22
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/virt.c
77
--- a/hw/net/lan9118.c
24
+++ b/hw/arm/virt.c
78
+++ b/hw/net/lan9118.c
25
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
79
@@ -XXX,XX +XXX,XX @@
26
return arm_cpu_mp_affinity(idx, clustersz);
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
27
}
141
}
28
142
29
+static void virt_set_high_memmap(VirtMachineState *vms,
143
-static void phy_update_irq(lan9118_state *s)
30
+ hwaddr base, int pa_bits)
144
+static void lan9118_update_irq(void *opaque, int n, int level)
31
+{
145
{
32
+ int i;
146
- if (s->phy_int & s->phy_int_mask) {
33
+
147
+ lan9118_state *s = opaque;
34
+ for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
148
+
35
+ hwaddr size = extended_memmap[i].size;
149
+ if (level) {
36
+ bool fits;
150
s->int_sts |= PHY_INT;
37
+
151
} else {
38
+ base = ROUND_UP(base, size);
152
s->int_sts &= ~PHY_INT;
39
+ vms->memmap[i].base = base;
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
40
+ vms->memmap[i].size = size;
154
lan9118_update(s);
41
+
155
}
42
+ /*
156
43
+ * Check each device to see if they fit in the PA space,
157
-static void phy_update_link(lan9118_state *s)
44
+ * moving highest_gpa as we go.
158
-{
45
+ *
159
- /* Autonegotiation status mirrors link status. */
46
+ * For each device that doesn't fit, disable it.
160
- if (qemu_get_queue(s->nic)->link_down) {
47
+ */
161
- s->phy_status &= ~0x0024;
48
+ fits = (base + size) <= BIT_ULL(pa_bits);
162
- s->phy_int |= PHY_INT_DOWN;
49
+ if (fits) {
163
- } else {
50
+ vms->highest_gpa = base + size - 1;
164
- s->phy_status |= 0x0024;
51
+ }
165
- s->phy_int |= PHY_INT_ENERGYON;
52
+
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
53
+ switch (i) {
167
- }
54
+ case VIRT_HIGH_GIC_REDIST2:
168
- phy_update_irq(s);
55
+ vms->highmem_redists &= fits;
169
-}
56
+ break;
170
-
57
+ case VIRT_HIGH_PCIE_ECAM:
171
static void lan9118_set_link(NetClientState *nc)
58
+ vms->highmem_ecam &= fits;
172
{
59
+ break;
173
- phy_update_link(qemu_get_nic_opaque(nc));
60
+ case VIRT_HIGH_PCIE_MMIO:
174
-}
61
+ vms->highmem_mmio &= fits;
175
-
176
-static void phy_reset(lan9118_state *s)
177
-{
178
- s->phy_status = 0x7809;
179
- s->phy_control = 0x3000;
180
- s->phy_advertise = 0x01e1;
181
- s->phy_int_mask = 0;
182
- s->phy_int = 0;
183
- phy_update_link(s);
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
185
+ nc->link_down);
186
}
187
188
static void lan9118_reset(DeviceState *d)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
208
}
209
}
210
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
212
-{
213
- uint32_t val;
214
-
215
- switch (reg) {
216
- case 0: /* Basic Control */
217
- return s->phy_control;
218
- case 1: /* Basic Status */
219
- return s->phy_status;
220
- case 2: /* ID1 */
221
- return 0x0007;
222
- case 3: /* ID2 */
223
- return 0xc0d1;
224
- case 4: /* Auto-neg advertisement */
225
- return s->phy_advertise;
226
- case 5: /* Auto-neg Link Partner Ability */
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
242
- }
243
-}
244
-
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
246
-{
247
- switch (reg) {
248
- case 0: /* Basic Control */
249
- if (val & 0x8000) {
250
- phy_reset(s);
251
- break;
252
- }
253
- s->phy_control = val & 0x7980;
254
- /* Complete autonegotiation immediately. */
255
- if (val & 0x1000) {
256
- s->phy_status |= 0x0020;
257
- }
258
- break;
259
- case 4: /* Auto-neg advertisement */
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
270
- }
271
-}
272
-
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
274
{
275
switch (reg) {
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
277
if (val & 2) {
278
DPRINTF("PHY write %d = 0x%04x\n",
279
(val >> 6) & 0x1f, s->mac_mii_data);
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
282
} else {
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
285
DPRINTF("PHY read %d = 0x%04x\n",
286
(val >> 6) & 0x1f, s->mac_mii_data);
287
}
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
289
break;
290
case CSR_PMT_CTRL:
291
if (val & 0x400) {
292
- phy_reset(s);
293
+ lan9118_phy_reset(&s->mii);
294
}
295
s->pmt_ctrl &= ~0x34e;
296
s->pmt_ctrl |= (val & 0x34e);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
298
const MemoryRegionOps *mem_ops =
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
300
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
304
+ return;
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
62
+ break;
389
+ break;
63
+ }
390
+ }
64
+
391
+ s->control = val & 0x7980;
65
+ base += size;
392
+ /* Complete autonegotiation immediately. */
393
+ if (val & 0x1000) {
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
66
+ }
408
+ }
67
+}
409
+}
68
+
410
+
69
static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
70
{
412
+{
71
MachineState *ms = MACHINE(vms);
413
+ s->link_down = link_down;
72
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
414
+
73
/* We know for sure that at least the memory fits in the PA space */
415
+ /* Autonegotiation status mirrors link status. */
74
vms->highest_gpa = memtop - 1;
416
+ if (link_down) {
75
417
+ s->status &= ~0x0024;
76
- for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
418
+ s->ints |= PHY_INT_DOWN;
77
- hwaddr size = extended_memmap[i].size;
419
+ } else {
78
- bool fits;
420
+ s->status |= 0x0024;
79
-
421
+ s->ints |= PHY_INT_ENERGYON;
80
- base = ROUND_UP(base, size);
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
81
- vms->memmap[i].base = base;
423
+ }
82
- vms->memmap[i].size = size;
424
+ lan9118_phy_update_irq(s);
83
-
425
+}
84
- /*
426
+
85
- * Check each device to see if they fit in the PA space,
427
+void lan9118_phy_reset(Lan9118PhyState *s)
86
- * moving highest_gpa as we go.
428
+{
87
- *
429
+ s->control = 0x3000;
88
- * For each device that doesn't fit, disable it.
430
+ s->status = 0x7809;
89
- */
431
+ s->advertise = 0x01e1;
90
- fits = (base + size) <= BIT_ULL(pa_bits);
432
+ s->int_mask = 0;
91
- if (fits) {
433
+ s->ints = 0;
92
- vms->highest_gpa = base + size - 1;
434
+ lan9118_phy_update_link(s, s->link_down);
93
- }
435
+}
94
-
436
+
95
- switch (i) {
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
96
- case VIRT_HIGH_GIC_REDIST2:
438
+{
97
- vms->highmem_redists &= fits;
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
98
- break;
440
+
99
- case VIRT_HIGH_PCIE_ECAM:
441
+ lan9118_phy_reset(s);
100
- vms->highmem_ecam &= fits;
442
+}
101
- break;
443
+
102
- case VIRT_HIGH_PCIE_MMIO:
444
+static void lan9118_phy_init(Object *obj)
103
- vms->highmem_mmio &= fits;
445
+{
104
- break;
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
105
- }
447
+
106
-
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
107
- base += size;
449
+}
108
- }
450
+
109
+ virt_set_high_memmap(vms, base, pa_bits);
451
+static const VMStateDescription vmstate_lan9118_phy = {
110
452
+ .name = "lan9118-phy",
111
if (device_memory_size > 0) {
453
+ .version_id = 1,
112
ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
113
--
515
--
114
2.25.1
516
2.34.1
diff view generated by jsdifflib
[PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Gavin Shan <gshan@redhat.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
This introduces virt_get_high_memmap_enabled() helper, which returns
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
4
imx_fec having more logging and tracing. Merge these improvements into
5
be used in the subsequent patches.
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
6
7
No functional change intended.
7
Some migration state how resides in the new device model which breaks migration
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
8
13
9
Signed-off-by: Gavin Shan <gshan@redhat.com>
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Marc Zyngier <maz@kernel.org>
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
13
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
14
Message-id: 20221029224307.138822-5-gshan@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
19
---
17
hw/arm/virt.c | 32 +++++++++++++++++++-------------
20
include/hw/net/imx_fec.h | 9 ++-
18
1 file changed, 19 insertions(+), 13 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
19
26
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
21
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt.c
29
--- a/include/hw/net/imx_fec.h
23
+++ b/hw/arm/virt.c
30
+++ b/include/hw/net/imx_fec.h
24
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
25
return arm_cpu_mp_affinity(idx, clustersz);
32
#define TYPE_IMX_ENET "imx.enet"
26
}
33
27
34
#include "hw/sysbus.h"
28
+static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
35
+#include "hw/net/lan9118_phy.h"
29
+ int index)
36
+#include "hw/irq.h"
30
+{
37
#include "net/net.h"
31
+ bool *enabled_array[] = {
38
32
+ &vms->highmem_redists,
39
#define ENET_EIR 1
33
+ &vms->highmem_ecam,
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
34
+ &vms->highmem_mmio,
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
35
+ };
42
uint32_t tx_ring_num;
36
+
43
37
+ assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
44
- uint32_t phy_status;
38
+ ARRAY_SIZE(enabled_array));
45
- uint32_t phy_control;
39
+ assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
46
- uint32_t phy_advertise;
40
+
47
- uint32_t phy_int;
41
+ return enabled_array[index - VIRT_LOWMEMMAP_LAST];
48
- uint32_t phy_int_mask;
42
+}
49
+ Lan9118PhyState mii;
43
+
50
+ IRQState mii_irq;
44
static void virt_set_high_memmap(VirtMachineState *vms,
51
uint32_t phy_num;
45
hwaddr base, int pa_bits)
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
92
/*
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
96
*/
97
-static void imx_phy_update_irq(IMXFECState *s)
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
46
{
99
{
47
hwaddr region_base, region_size;
100
- imx_eth_update(s);
48
- bool fits;
101
-}
49
+ bool *region_enabled, fits;
102
-
50
int i;
103
-static void imx_phy_update_link(IMXFECState *s)
51
104
-{
52
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
105
- /* Autonegotiation status mirrors link status. */
53
+ region_enabled = virt_get_high_memmap_enabled(vms, i);
106
- if (qemu_get_queue(s->nic)->link_down) {
54
region_base = ROUND_UP(base, extended_memmap[i].size);
107
- trace_imx_phy_update_link("down");
55
region_size = extended_memmap[i].size;
108
- s->phy_status &= ~0x0024;
56
109
- s->phy_int |= PHY_INT_DOWN;
57
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
110
- } else {
58
vms->highest_gpa = region_base + region_size - 1;
111
- trace_imx_phy_update_link("up");
59
}
112
- s->phy_status |= 0x0024;
60
113
- s->phy_int |= PHY_INT_ENERGYON;
61
- switch (i) {
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
62
- case VIRT_HIGH_GIC_REDIST2:
115
- }
63
- vms->highmem_redists &= fits;
116
- imx_phy_update_irq(s);
64
- break;
117
+ imx_eth_update(opaque);
65
- case VIRT_HIGH_PCIE_ECAM:
118
}
66
- vms->highmem_ecam &= fits;
119
67
- break;
120
static void imx_eth_set_link(NetClientState *nc)
68
- case VIRT_HIGH_PCIE_MMIO:
121
{
69
- vms->highmem_mmio &= fits;
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
140
{
141
- uint32_t val;
142
uint32_t phy = reg / 32;
143
144
if (!s->phy_connected) {
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
146
147
reg %= 32;
148
149
- switch (reg) {
150
- case 0: /* Basic Control */
151
- val = s->phy_control;
152
- break;
153
- case 1: /* Basic Status */
154
- val = s->phy_status;
155
- break;
156
- case 2: /* ID1 */
157
- val = 0x0007;
158
- break;
159
- case 3: /* ID2 */
160
- val = 0xc0d1;
161
- break;
162
- case 4: /* Auto-neg advertisement */
163
- val = s->phy_advertise;
164
- break;
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
259
+ return;
260
+ }
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
262
+
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
264
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
267
index XXXXXXX..XXXXXXX 100644
268
--- a/hw/net/lan9118_phy.c
269
+++ b/hw/net/lan9118_phy.c
270
@@ -XXX,XX +XXX,XX @@
271
* Copyright (c) 2009 CodeSourcery, LLC.
272
* Written by Paul Brook
273
*
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
275
+ *
276
* This code is licensed under the GNU GPL v2
277
*
278
* Contributions after 2012-01-13 are licensed under the terms of the
279
@@ -XXX,XX +XXX,XX @@
280
#include "hw/resettable.h"
281
#include "migration/vmstate.h"
282
#include "qemu/log.h"
283
+#include "trace.h"
284
285
#define PHY_INT_ENERGYON (1 << 7)
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
288
289
switch (reg) {
290
case 0: /* Basic Control */
291
- return s->control;
292
+ val = s->control;
293
+ break;
294
case 1: /* Basic Status */
295
- return s->status;
296
+ val = s->status;
297
+ break;
298
case 2: /* ID1 */
299
- return 0x0007;
300
+ val = 0x0007;
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
353
{
354
+ trace_lan9118_phy_write(val, reg);
355
+
356
switch (reg) {
357
case 0: /* Basic Control */
358
if (val & 0x8000) {
359
lan9118_phy_reset(s);
70
- break;
360
- break;
71
- }
361
- }
72
-
362
- s->control = val & 0x7980;
73
+ *region_enabled &= fits;
363
- /* Complete autonegotiation immediately. */
74
base = region_base + region_size;
364
- if (val & 0x1000) {
365
- s->status |= 0x0020;
366
+ } else {
367
+ s->control = val & 0x7980;
368
+ /* Complete autonegotiation immediately. */
369
+ if (val & 0x1000) {
370
+ s->status |= 0x0020;
371
+ }
372
}
373
break;
374
case 4: /* Auto-neg advertisement */
375
s->advertise = (val & 0x2d7f) | 0x80;
376
break;
377
- /* TODO 17, 18, 27, 31 */
378
case 30: /* Interrupt mask */
379
s->int_mask = val & 0xff;
380
lan9118_phy_update_irq(s);
381
break;
382
+ case 17:
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
75
}
395
}
76
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
77
--
471
--
78
2.25.1
472
2.34.1
diff view generated by jsdifflib
New patch
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
6
Fixes: 2a424990170b "LAN9118 emulation"
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/net/lan9118_phy.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/net/lan9118_phy.c
19
+++ b/hw/net/lan9118_phy.c
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
21
val = s->advertise;
22
break;
23
case 5: /* Auto-neg Link Partner Ability */
24
- val = 0x0f71;
25
+ val = 0x0fe1;
26
break;
27
case 6: /* Auto-neg Expansion */
28
val = 1;
29
--
30
2.34.1
diff view generated by jsdifflib
New patch
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Bernhard Beschow <shentey@gmail.com>
1
2
3
Prefer named constants over magic values for better readability.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/net/mii.h | 6 +++++
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
14
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/net/mii.h
18
+++ b/include/hw/net/mii.h
19
@@ -XXX,XX +XXX,XX @@
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
22
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
26
#define MII_ANAR_TXFD (1 << 8)
27
@@ -XXX,XX +XXX,XX @@
28
#define MII_ANAR_10FD (1 << 6)
29
#define MII_ANAR_10 (1 << 5)
30
#define MII_ANAR_CSMACD (1 << 0)
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
32
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
117
}
118
}
119
break;
120
- case 4: /* Auto-neg advertisement */
121
- s->advertise = (val & 0x2d7f) | 0x80;
122
+ case MII_ANAR:
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
125
+ MII_ANAR_SELECT))
126
+ | MII_ANAR_TX;
127
break;
128
case 30: /* Interrupt mask */
129
s->int_mask = val & 0xff;
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
131
/* Autonegotiation status mirrors link status. */
132
if (link_down) {
133
trace_lan9118_phy_update_link("down");
134
- s->status &= ~0x0024;
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
136
s->ints |= PHY_INT_DOWN;
137
} else {
138
trace_lan9118_phy_update_link("up");
139
- s->status |= 0x0024;
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
141
s->ints |= PHY_INT_ENERGYON;
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
143
}
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
145
{
146
trace_lan9118_phy_reset();
147
148
- s->control = 0x3000;
149
- s->status = 0x7809;
150
- s->advertise = 0x01e1;
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
152
+ s->status = MII_BMSR_100TX_FD
153
+ | MII_BMSR_100TX_HD
154
+ | MII_BMSR_10T_FD
155
+ | MII_BMSR_10T_HD
156
+ | MII_BMSR_AUTONEG
157
+ | MII_BMSR_EXTCAP;
158
+ s->advertise = MII_ANAR_TXFD
159
+ | MII_ANAR_TX
160
+ | MII_ANAR_10FD
161
+ | MII_ANAR_10
162
+ | MII_ANAR_CSMACD;
163
s->int_mask = 0;
164
s->ints = 0;
165
lan9118_phy_update_link(s, s->link_down);
166
--
167
2.34.1
diff view generated by jsdifflib
[PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Luke Starrett <lukes@xsightlabs.com>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
3
The real device advertises this mode and the device model already advertises
4
register:
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
make the model more realistic.
5
6
6
"indicates the maximum SPI INTID that the GIC implementation supports"
7
8
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
9
for the internal 16x SGI's and 16x PPI's. However, the original GICv3
10
model subtracted off the SGI/PPI. Cosmetically this can be seen at OS
11
boot (Linux) showing 32 shy of what should be there, i.e.:
12
13
[ 0.000000] GICv3: 224 SPIs implemented
14
15
Though in hw/arm/virt.c, the machine is configured for 256 SPI's. ARM
16
virt machine likely doesn't have a problem with this because the upper
17
32 IRQ's don't actually have anything meaningful wired. But, this does
18
become a functional issue on a custom use case which wants to make use
19
of these IRQ's. Additionally, boot code (i.e. TF-A) will only init up
20
to the number (blocks of 32) that it believes to actually be there.
21
22
Signed-off-by: Luke Starrett <lukes@xsightlabs.com>
23
Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
12
---
27
hw/intc/arm_gicv3_dist.c | 4 ++--
13
hw/net/lan9118_phy.c | 4 ++--
28
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
29
15
30
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
31
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_dist.c
18
--- a/hw/net/lan9118_phy.c
33
+++ b/hw/intc/arm_gicv3_dist.c
19
+++ b/hw/net/lan9118_phy.c
34
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
35
* MBIS == 0 (message-based SPIs not supported)
21
break;
36
* SecurityExtn == 1 if security extns supported
22
case MII_ANAR:
37
* CPUNumber == 0 since for us ARE is always 1
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
38
- * ITLinesNumber == (num external irqs / 32) - 1
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
39
+ * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
25
- MII_ANAR_SELECT))
40
*/
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
41
- int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
42
+ int itlinesnumber = (s->num_irq / 32) - 1;
28
| MII_ANAR_TX;
43
/*
29
break;
44
* SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
30
case 30: /* Interrupt mask */
45
* "security extensions not supported" always implies DS == 1,
46
--
31
--
47
2.25.1
32
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
1
6
7
For the cases where the infzero test in pickNaNMulAdd was
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
13
14
For Arm, this looks like it might be a behaviour change because we
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
37
---
38
fpu/softfloat-parts.c.inc | 13 +++++++------
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
41
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
43
index XXXXXXX..XXXXXXX 100644
44
--- a/fpu/softfloat-parts.c.inc
45
+++ b/fpu/softfloat-parts.c.inc
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
47
int ab_mask, int abc_mask)
48
{
49
int which;
50
+ bool infzero = (ab_mask == float_cmask_infzero);
51
52
if (unlikely(abc_mask & float_cmask_snan)) {
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
54
}
55
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
57
- ab_mask == float_cmask_infzero, s);
58
+ if (infzero) {
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
61
+ }
62
+
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
64
65
if (s->default_nan_mode || which == 3) {
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
112
+
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
114
if (is_snan(c_cls)) {
115
return 2;
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
117
* to return an input NaN if we have one (ie c) rather than generating
118
* a default NaN
119
*/
120
- if (infzero) {
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
122
- return 2;
123
- }
124
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
128
return 1;
129
}
130
#elif defined(TARGET_RISCV)
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
132
- if (infzero) {
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
134
- }
135
return 3; /* default NaN */
136
#elif defined(TARGET_S390X)
137
if (infzero) {
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
165
--
166
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
architectures thus do different things:
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
33
---
34
include/fpu/softfloat-helpers.h | 11 ++++
35
include/fpu/softfloat-types.h | 23 +++++++++
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/include/fpu/softfloat-helpers.h
42
+++ b/include/fpu/softfloat-helpers.h
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
44
status->float_2nan_prop_rule = rule;
45
}
46
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
49
+{
50
+ status->float_infzeronan_rule = rule;
51
+}
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
98
/*
99
* Floating Point Status. Individual architectures may maintain
100
* several versions of float_status for different functions. The
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
102
FloatRoundMode float_rounding_mode;
103
FloatX80RoundPrec floatx80_rounding_precision;
104
Float2NaNPropRule float_2nan_prop_rule;
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
106
bool tininess_before_rounding;
107
/* should denormalised results go to zero and set the inexact flag? */
108
bool flush_to_zero;
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
110
index XXXXXXX..XXXXXXX 100644
111
--- a/fpu/softfloat-specialize.c.inc
112
+++ b/fpu/softfloat-specialize.c.inc
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
115
bool infzero, float_status *status)
116
{
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
118
+
119
/*
120
* We guarantee not to require the target to tell us how to
121
* pick a NaN if we're always returning the default NaN.
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
123
* specify.
124
*/
125
assert(!status->default_nan_mode);
126
+
127
+ if (rule == float_infzeronan_none) {
128
+ /*
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
188
+ }
189
+ }
190
+
191
+#if defined(TARGET_ARM)
192
+
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
195
*/
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
197
}
198
#elif defined(TARGET_MIPS)
199
if (snan_bit_is_one(status)) {
200
- /*
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
202
- * case sets InvalidOp and returns the default NaN
203
- */
204
- if (infzero) {
205
- return 3;
206
- }
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
208
if (is_snan(a_cls)) {
209
return 0;
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
256
--
257
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 3 +++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 4 insertions(+), 7 deletions(-)
11
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
21
+ * and the input NaN if it is signalling
22
*/
23
static void arm_set_default_fp_behaviours(float_status *s)
24
{
25
set_float_detect_tininess(float_tininess_before_rounding, s);
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
/*
37
* Temporarily fall back to ifdef ladder
38
*/
39
-#if defined(TARGET_ARM)
40
- /*
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
42
- * but (inf,zero,snan) returns the input NaN.
43
- */
44
- rule = float_infzeronan_dnan_if_qnan;
45
-#elif defined(TARGET_MIPS)
46
+#if defined(TARGET_MIPS)
47
if (snan_bit_is_one(status)) {
48
/*
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
50
--
51
2.34.1
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
New patch
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
{
20
int which;
21
bool infzero = (ab_mask == float_cmask_infzero);
22
+ bool have_snan = (abc_mask & float_cmask_snan);
23
24
- if (unlikely(abc_mask & float_cmask_snan)) {
25
+ if (unlikely(have_snan)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
if (s->default_nan_mode) {
31
which = 3;
32
} else {
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
35
}
36
37
if (which == 3) {
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
51
--
52
2.34.1
diff view generated by jsdifflib
[PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
TICAB, TOCU and TID4. These allow the guest to enable trapping of
2
result if both operands of a 3-operand fused multiply-add operation
3
various EL1 instructions to EL2. In this commit, add the necessary
3
are NaNs. As a result different architectures have ended up with
4
code to allow the guest to set these bits if the feature is present;
4
different rules for propagating NaNs.
5
because the bit is always zero when the feature isn't present we
5
6
won't need to use explicit feature checks in the "trap on condition"
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
tests in the following commits.
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
8
We want to make the propagation rule instead be selectable at
9
Note that although full implementation of the feature (mandatory from
9
runtime, because:
10
Armv8.5 onward) requires all five trap bits, the ID registers permit
10
* this will let us have multiple targets in one QEMU binary
11
a value indicating that only TICAB, TOCU and TID4 are implemented,
11
* the Arm FEAT_AFP architectural feature includes letting
12
which might be the case for CPUs between Armv8.2 and Armv8.5.
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
13
23
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
16
---
27
---
17
target/arm/cpu.h | 30 ++++++++++++++++++++++++++++++
28
include/fpu/softfloat-helpers.h | 11 +++
18
target/arm/helper.c | 6 ++++++
29
include/fpu/softfloat-types.h | 55 +++++++++++
19
2 files changed, 36 insertions(+)
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
20
31
3 files changed, 107 insertions(+), 126 deletions(-)
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
22
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
35
--- a/include/fpu/softfloat-helpers.h
24
+++ b/target/arm/cpu.h
36
+++ b/include/fpu/softfloat-helpers.h
25
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
26
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
38
status->float_2nan_prop_rule = rule;
27
}
39
}
28
40
29
+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
42
+ float_status *status)
30
+{
43
+{
31
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
44
+ status->float_3nan_prop_rule = rule;
32
+}
45
+}
33
+
46
+
34
+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
float_status *status)
49
{
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
51
return status->float_2nan_prop_rule;
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
35
+{
55
+{
36
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
56
+ return status->float_3nan_prop_rule;
37
+}
57
+}
38
+
58
+
39
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
40
{
60
{
41
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
61
return status->float_infzeronan_rule;
42
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
43
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
63
index XXXXXXX..XXXXXXX 100644
44
}
64
--- a/include/fpu/softfloat-types.h
45
65
+++ b/include/fpu/softfloat-types.h
46
+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
47
+{
67
#ifndef SOFTFLOAT_TYPES_H
48
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
68
#define SOFTFLOAT_TYPES_H
49
+}
69
50
+
70
+#include "hw/registerfields.h"
51
+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
71
+
52
+{
72
/*
53
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
73
* Software IEC/IEEE floating-point types.
54
+}
74
*/
55
+
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
56
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
57
{
149
{
58
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
59
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id)
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
60
return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
152
+ int which;
61
}
153
+
62
154
/*
63
+static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
155
* We guarantee not to require the target to tell us how to
64
+{
156
* pick a NaN if we're always returning the default NaN.
65
+ return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
66
+}
67
+
68
+static inline bool isar_feature_any_evt(const ARMISARegisters *id)
69
+{
70
+ return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
71
+}
72
+
73
/*
74
* Forward to the above feature tests given an ARMCPU pointer.
75
*/
76
diff --git a/target/arm/helper.c b/target/arm/helper.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/helper.c
79
+++ b/target/arm/helper.c
80
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
81
}
158
}
82
}
159
}
83
160
84
+ if (cpu_isar_feature(any_evt, cpu)) {
161
+ if (rule == float_3nan_prop_none) {
85
+ valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4;
162
#if defined(TARGET_ARM)
86
+ } else if (cpu_isar_feature(any_half_evt, cpu)) {
163
-
87
+ valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
88
+ }
321
+ }
89
+
322
+
90
/* Clear RES0 bits. */
323
+ assert(rule != float_3nan_prop_none);
91
value &= valid_mask;
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
92
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
337
}
338
339
/*----------------------------------------------------------------------------
93
--
340
--
94
2.25.1
341
2.34.1
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
When building with --disable-tcg on Darwin we get:
4
5
target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps'
6
cc->tcg_ops->do_interrupt(cs);
7
~~~~~~~~~~~^
8
9
Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
10
handler to sysemu") limited this block to system emulation,
11
but neglected to also limit it to TCG.
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Fabiano Rosas <farosas@suse.de>
15
Message-id: 20221209110823.59495-1-philmd@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
17
---
7
---
18
target/arm/cpu.c | 5 +++--
8
target/arm/cpu.c | 5 +++++
19
1 file changed, 3 insertions(+), 2 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
20
11
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
26
arm_rebuild_hflags(env);
17
* * tininess-before-rounding
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
27
}
33
}
28
34
29
-#ifndef CONFIG_USER_ONLY
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
36
index XXXXXXX..XXXXXXX 100644
31
37
--- a/fpu/softfloat-specialize.c.inc
32
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
38
+++ b/fpu/softfloat-specialize.c.inc
33
unsigned int target_el,
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
40
}
35
cc->tcg_ops->do_interrupt(cs);
41
36
return true;
42
if (rule == float_3nan_prop_none) {
37
}
43
-#if defined(TARGET_ARM)
38
-#endif /* !CONFIG_USER_ONLY */
44
- /*
39
+
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
40
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
41
47
- */
42
void arm_cpu_update_virq(ARMCPU *cpu)
48
- rule = float_3nan_prop_s_cab;
43
{
49
-#elif defined(TARGET_MIPS)
50
+#if defined(TARGET_MIPS)
51
if (snan_bit_is_one(status)) {
52
rule = float_3nan_prop_s_abc;
53
} else {
44
--
54
--
45
2.25.1
55
2.34.1
46
47
diff view generated by jsdifflib
New patch
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/tcg/fpu_helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
21
}
22
23
int ieee_ex_to_loongarch(int xcpt)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_LOONGARCH64)
33
- rule = float_3nan_prop_s_cab;
34
#elif defined(TARGET_PPC)
35
/*
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 4 ++++
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
{
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
20
FloatInfZeroNaNRule izn_rule;
21
+ Float3NaNPropRule nan3_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
31
+
32
}
33
34
static inline void restore_fp_status(CPUMIPSState *env)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/mips/msa.c
38
+++ b/target/mips/msa.c
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
41
&env->active_tc.msa_fp_status);
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
46
/* clear float_status exception flags */
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
index XXXXXXX..XXXXXXX 100644
51
--- a/fpu/softfloat-specialize.c.inc
52
+++ b/fpu/softfloat-specialize.c.inc
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
}
55
56
if (rule == float_3nan_prop_none) {
57
-#if defined(TARGET_MIPS)
58
- if (snan_bit_is_one(status)) {
59
- rule = float_3nan_prop_s_abc;
60
- } else {
61
- rule = float_3nan_prop_s_cab;
62
- }
63
-#elif defined(TARGET_XTENSA)
64
+#if defined(TARGET_XTENSA)
65
if (status->use_first_nan) {
66
rule = float_3nan_prop_abc;
67
} else {
68
--
69
2.34.1
diff view generated by jsdifflib
[PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
2
ifdef from pickNaNMulAdd().
3
their AArch32 equivalents). This is a subset of the registers
4
trapped by HCR_EL2.TID2, which includes all of these and also the
5
CTR_EL0 register.
6
7
Our implementation already uses a separate access function for
8
CTR_EL0 (ctr_el0_access()), so all of the registers currently using
9
access_aa64_tid2() should also be checking TID4. Make that function
10
check both TID2 and TID4, and rename it appropriately.
11
3
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
14
---
7
---
15
target/arm/helper.c | 17 +++++++++--------
8
target/xtensa/fpu_helper.c | 2 ++
16
1 file changed, 9 insertions(+), 8 deletions(-)
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
17
11
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
14
--- a/target/xtensa/fpu_helper.c
21
+++ b/target/arm/helper.c
15
+++ b/target/xtensa/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
23
scr_write(env, ri, 0);
17
set_use_first_nan(use_first, &env->fp_status);
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
19
&env->fp_status);
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
21
+ &env->fp_status);
24
}
22
}
25
23
26
-static CPAccessResult access_aa64_tid2(CPUARMState *env,
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
27
- const ARMCPRegInfo *ri,
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
- bool isread)
26
index XXXXXXX..XXXXXXX 100644
29
+static CPAccessResult access_tid4(CPUARMState *env,
27
--- a/fpu/softfloat-specialize.c.inc
30
+ const ARMCPRegInfo *ri,
28
+++ b/fpu/softfloat-specialize.c.inc
31
+ bool isread)
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
{
33
- if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
34
+ if (arm_current_el(env) == 1 &&
35
+ (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
36
return CP_ACCESS_TRAP_EL2;
37
}
30
}
38
31
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
32
if (rule == float_3nan_prop_none) {
40
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
33
-#if defined(TARGET_XTENSA)
41
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
34
- if (status->use_first_nan) {
42
.access = PL1_R,
35
- rule = float_3nan_prop_abc;
43
- .accessfn = access_aa64_tid2,
36
- } else {
44
+ .accessfn = access_tid4,
37
- rule = float_3nan_prop_cba;
45
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
38
- }
46
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
39
-#else
47
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
40
rule = float_3nan_prop_abc;
48
.access = PL1_RW,
41
-#endif
49
- .accessfn = access_aa64_tid2,
42
}
50
+ .accessfn = access_tid4,
43
51
.writefn = csselr_write, .resetvalue = 0,
44
assert(rule != float_3nan_prop_none);
52
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
53
offsetof(CPUARMState, cp15.csselr_ns) } },
54
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
55
{ .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
56
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
57
.access = PL1_R,
58
- .accessfn = access_aa64_tid2,
59
+ .accessfn = access_tid4,
60
.readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
61
};
62
63
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
64
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
65
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
66
.access = PL1_R, .type = ARM_CP_CONST,
67
- .accessfn = access_aa64_tid2,
68
+ .accessfn = access_tid4,
69
.resetvalue = cpu->clidr
70
};
71
define_one_arm_cp_reg(cpu, &clidr);
72
--
45
--
73
2.25.1
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
12
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/i386/tcg/fpu_helper.c
16
+++ b/target/i386/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
18
* there are multiple input NaNs they are selected in the order a, b, c.
19
*/
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
}
23
24
static inline uint8_t save_exception_flags(CPUX86State *env)
25
--
26
2.34.1
diff view generated by jsdifflib
New patch
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
HPPA is the only target that was using the default branch of the
5
ifdef ladder (other targets either do not use muladd or set
6
default_nan_mode), so we can remove the ifdef fallback entirely now
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
9
10
We add a TODO note that the HPPA rule is probably wrong; this is
11
not a behavioural change for this refactoring.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
16
---
17
target/hppa/fpu_helper.c | 8 ++++++++
18
fpu/softfloat-specialize.c.inc | 4 ----
19
2 files changed, 8 insertions(+), 4 deletions(-)
20
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/hppa/fpu_helper.c
24
+++ b/target/hppa/fpu_helper.c
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
26
* HPPA does note implement a CPU reset method at all...
27
*/
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
29
+ /*
30
+ * TODO: The HPPA architecture reference only documents its NaN
31
+ * propagation rule for 2-operand operations. Testing on real hardware
32
+ * might be necessary to confirm whether this order for muladd is correct.
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
41
index XXXXXXX..XXXXXXX 100644
42
--- a/fpu/softfloat-specialize.c.inc
43
+++ b/fpu/softfloat-specialize.c.inc
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
}
46
}
47
48
- if (rule == float_3nan_prop_none) {
49
- rule = float_3nan_prop_abc;
50
- }
51
-
52
assert(rule != float_3nan_prop_none);
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
54
/* We have at least one SNaN input and should prefer it */
55
--
56
2.34.1
diff view generated by jsdifflib
New patch
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
15
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/fpu/softfloat-helpers.h
19
+++ b/include/fpu/softfloat-helpers.h
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
21
status->snan_bit_is_one = val;
22
}
23
24
-static inline void set_use_first_nan(bool val, float_status *status)
25
-{
26
- status->use_first_nan = val;
27
-}
28
-
29
static inline void set_no_signaling_nans(bool val, float_status *status)
30
{
31
status->no_signaling_nans = val;
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/fpu/softfloat-types.h
35
+++ b/include/fpu/softfloat-types.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
37
* softfloat-specialize.inc.c)
38
*/
39
bool snan_bit_is_one;
40
- bool use_first_nan;
41
bool no_signaling_nans;
42
/* should overflowed results subtract re_bias to its exponent? */
43
bool rebias_overflow;
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/xtensa/fpu_helper.c
47
+++ b/target/xtensa/fpu_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const struct {
49
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
51
{
52
- set_use_first_nan(use_first, &env->fp_status);
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
54
&env->fp_status);
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
New patch
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
1
4
5
floatx80 is used only by:
6
i386
7
m68k
8
arm nwfpe old floating-point emulation emulation support
9
(which is essentially dead, especially the parts involving floatx80)
10
PPC (only in the xsrqpxp instruction, which just rounds an input
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
13
14
The floatx80 default NaN as currently implemented is:
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
40
---
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
42
1 file changed, 10 insertions(+), 10 deletions(-)
43
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/fpu/softfloat-specialize.c.inc
47
+++ b/fpu/softfloat-specialize.c.inc
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
49
floatx80 floatx80_default_nan(float_status *status)
50
{
51
floatx80 r;
52
+ /*
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
54
+ * in the floatx80 format. We assume that floatx80's explicit
55
+ * integer bit is always set (this is true for i386 and m68k,
56
+ * which are the only real users of this format).
57
+ */
58
+ FloatParts64 p64;
59
+ parts64_default_nan(&p64, status);
60
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
74
}
75
76
--
77
2.34.1
diff view generated by jsdifflib
New patch
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
1
5
6
This pattern appears to have been copied from target/riscv, where it
7
is used because the functions there do not have ready access to the
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
21
---
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
23
1 file changed, 2 insertions(+), 4 deletions(-)
24
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/loongarch/tcg/fpu_helper.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
30
} else if (float32_is_zero_or_denormal(f)) {
31
return sign ? 1 << 4 : 1 << 8;
32
} else if (float32_is_any_nan(f)) {
33
- float_status s = { }; /* for snan_bit_is_one */
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
36
} else {
37
return sign ? 1 << 3 : 1 << 7;
38
}
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
40
} else if (float64_is_zero_or_denormal(f)) {
41
return sign ? 1 << 4 : 1 << 8;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
48
}
49
--
50
2.34.1
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
13
---
14
target/m68k/helper.c | 6 ++++--
15
1 file changed, 4 insertions(+), 2 deletions(-)
16
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/helper.c
20
+++ b/target/m68k/helper.c
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
22
CPUM68KState *env = &cpu->env;
23
24
if (n < 8) {
25
- float_status s = {};
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
27
+ float_status s = env->fp_status;
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
29
}
30
switch (n) {
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
32
CPUM68KState *env = &cpu->env;
33
34
if (n < 8) {
35
- float_status s = {};
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
37
+ float_status s = env->fp_status;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
39
return 8;
40
}
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
TYPE_ARM_GIC_KVM subclass to 3-phase reset.
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
7
8
To do this we need to pass the CPU env pointer in to the helper.
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
7
Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org
8
---
13
---
9
hw/intc/arm_gic_kvm.c | 14 +++++++++-----
14
target/sparc/helper.h | 4 ++--
10
1 file changed, 9 insertions(+), 5 deletions(-)
15
target/sparc/fop_helper.c | 8 ++++----
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
11
18
12
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
13
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/intc/arm_gic_kvm.c
21
--- a/target/sparc/helper.h
15
+++ b/hw/intc/arm_gic_kvm.c
22
+++ b/target/sparc/helper.h
16
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
17
struct KVMARMGICClass {
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
18
ARMGICCommonClass parent_class;
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
19
DeviceRealize parent_realize;
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
20
- void (*parent_reset)(DeviceState *dev);
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
21
+ ResettablePhases parent_phases;
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
22
};
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
23
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
24
void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
25
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s)
32
26
}
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/sparc/fop_helper.c
37
+++ b/target/sparc/fop_helper.c
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
39
return finish_fcmp(env, r, GETPC());
27
}
40
}
28
41
29
-static void kvm_arm_gic_reset(DeviceState *dev)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
30
+static void kvm_arm_gic_reset_hold(Object *obj)
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
31
{
44
{
32
- GICState *s = ARM_GIC_COMMON(dev);
45
/*
33
+ GICState *s = ARM_GIC_COMMON(obj);
46
* FLCMP never raises an exception nor modifies any FSR fields.
34
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
47
* Perform the comparison with a dummy fp environment.
35
48
*/
36
- kgc->parent_reset(dev);
49
- float_status discard = { };
37
+ if (kgc->parent_phases.hold) {
50
+ float_status discard = env->fp_status;
38
+ kgc->parent_phases.hold(obj);
51
FloatRelation r;
39
+ }
52
40
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
41
if (kvm_arm_gic_can_save_restore(s)) {
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
42
kvm_arm_gic_put(s);
55
g_assert_not_reached();
43
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
56
}
44
static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
57
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
45
{
60
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
61
- float_status discard = { };
47
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
62
+ float_status discard = env->fp_status;
48
ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
63
FloatRelation r;
49
KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
64
50
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
51
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
52
agcc->post_load = kvm_arm_gic_put;
67
index XXXXXXX..XXXXXXX 100644
53
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
68
--- a/target/sparc/translate.c
54
&kgc->parent_realize);
69
+++ b/target/sparc/translate.c
55
- device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
56
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL,
71
57
+ &kgc->parent_phases);
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
58
}
77
}
59
78
60
static const TypeInfo kvm_arm_gic_info = {
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
80
81
src1 = gen_load_fpr_D(dc, a->rs1);
82
src2 = gen_load_fpr_D(dc, a->rs2);
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
85
return advance_pc(dc);
86
}
87
61
--
88
--
62
2.25.1
89
2.34.1
63
64
diff view generated by jsdifflib
New patch
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
1
8
9
Use env->fp_status instead of the dummy fp_status.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
14
---
15
target/ppc/fpu_helper.c | 3 +--
16
1 file changed, 1 insertion(+), 2 deletions(-)
17
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/ppc/fpu_helper.c
21
+++ b/target/ppc/fpu_helper.c
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
23
} else if (tp##_is_infinity(arg)) { \
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
25
} else { \
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
29
fprf = 0x00 << FPSCR_FPRF; \
30
} else { \
31
fprf = 0x11 << FPSCR_FPRF; \
32
--
33
2.34.1
diff view generated by jsdifflib
[PULL 05/29] hw/arm/virt: Improve high memory region address assignment
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
There are three high memory regions, which are VIRT_HIGH_REDIST2,
3
Now that float_status has a bunch of fp parameters,
4
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
4
it is easier to copy an existing structure than create
5
are floating on highest RAM address. However, they can be disabled
5
one from scratch. Begin by copying the structure that
6
in several cases.
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
7
8
8
(1) One specific high memory region is likely to be disabled by
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
code by toggling vms->highmem_{redists, ecam, mmio}.
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
12
'virt-2.12' or ealier than it.
13
14
(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
15
on 32-bits system.
16
17
(4) One specific high memory region is disabled when it breaks the
18
PA space limit.
19
20
The current implementation of virt_set_{memmap, high_memmap}() isn't
21
optimized because the high memory region's PA space is always reserved,
22
regardless of whatever the actual state in the corresponding
23
vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and
24
'vms->highest_gpa' are always increased for case (1), (2) and (3).
25
It's unnecessary since the assigned PA space for the disabled high
26
memory region won't be used afterwards.
27
28
Improve the address assignment for those three high memory region by
29
skipping the address assignment for one specific high memory region if
30
it has been disabled in case (1), (2) and (3). The memory layout may
31
be changed after the improvement is applied, which leads to potential
32
migration breakage. So 'vms->highmem_compact' is added to control if
33
the improvement should be applied. For now, 'vms->highmem_compact' is
34
set to false, meaning that we don't have memory layout change until it
35
becomes configurable through property 'compact-highmem' in next patch.
36
37
Signed-off-by: Gavin Shan <gshan@redhat.com>
38
Reviewed-by: Eric Auger <eric.auger@redhat.com>
39
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
40
Reviewed-by: Marc Zyngier <maz@kernel.org>
41
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
42
Message-id: 20221029224307.138822-6-gshan@redhat.com
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
---
14
---
45
include/hw/arm/virt.h | 1 +
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
46
hw/arm/virt.c | 15 ++++++++++-----
16
1 file changed, 7 insertions(+), 13 deletions(-)
47
2 files changed, 11 insertions(+), 5 deletions(-)
48
17
49
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
50
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
51
--- a/include/hw/arm/virt.h
20
--- a/target/arm/tcg/vec_helper.c
52
+++ b/include/hw/arm/virt.h
21
+++ b/target/arm/tcg/vec_helper.c
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
54
PFlashCFI01 *flash[2];
23
* no effect on AArch32 instructions.
55
bool secure;
24
*/
56
bool highmem;
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
57
+ bool highmem_compact;
26
- *statusp = (float_status){
58
bool highmem_ecam;
27
- .tininess_before_rounding = float_tininess_before_rounding,
59
bool highmem_mmio;
28
- .float_rounding_mode = float_round_to_odd_inf,
60
bool highmem_redists;
29
- .flush_to_zero = true,
61
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
30
- .flush_inputs_to_zero = true,
62
index XXXXXXX..XXXXXXX 100644
31
- .default_nan_mode = true,
63
--- a/hw/arm/virt.c
32
- };
64
+++ b/hw/arm/virt.c
33
+
65
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
34
+ *statusp = env->vfp.fp_status;
66
vms->memmap[i].size = region_size;
35
+ set_default_nan_mode(true, statusp);
67
36
68
/*
37
if (ebf) {
69
- * Check each device to see if they fit in the PA space,
38
- float_status *fpst = &env->vfp.fp_status;
70
- * moving highest_gpa as we go.
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
71
+ * Check each device to see if it fits in the PA space,
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
72
+ * moving highest_gpa as we go. For compatibility, move
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
73
+ * highest_gpa for disabled fitting devices as well, if
42
-
74
+ * the compact layout has been disabled.
43
/* EBF=1 needs to do a step with round-to-odd semantics */
75
*
44
*oddstatusp = *statusp;
76
* For each device that doesn't fit, disable it.
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
77
*/
46
+ } else {
78
fits = (region_base + region_size) <= BIT_ULL(pa_bits);
47
+ set_flush_to_zero(true, statusp);
79
- if (fits) {
48
+ set_flush_inputs_to_zero(true, statusp);
80
- vms->highest_gpa = region_base + region_size - 1;
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
81
+ *region_enabled &= fits;
82
+ if (vms->highmem_compact && !*region_enabled) {
83
+ continue;
84
}
85
86
- *region_enabled &= fits;
87
base = region_base + region_size;
88
+ if (fits) {
89
+ vms->highest_gpa = base - 1;
90
+ }
91
}
50
}
51
-
52
return ebf;
92
}
53
}
93
54
94
--
55
--
95
2.25.1
56
2.34.1
57
58
diff view generated by jsdifflib
[PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
and IC IALLUIS cache maintenance instructions.
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
3
6
4
The HCR_EL2.TOCU bit traps all the other cache maintenance
7
Add a field to float_status to specify the default NaN value; fall
5
instructions that operate to the point of unification:
8
back to the old ifdef behaviour if these are not set.
6
AArch64 IC IVAU, IC IALLU, DC CVAU
7
AArch32 ICIMVAU, ICIALLU, DCCMVAU
8
9
9
The two trap bits between them cover all of the cache maintenance
10
The default NaN value is specified by setting a uint8_t to a
10
instructions which must also check the HCR_TPU flag. Turn the old
11
pattern corresponding to the sign and upper fraction parts of
11
aa64_cacheop_pou_access() function into a helper function which takes
12
the NaN; the lower bits of the fraction are set from bit 0 of
12
the set of HCR_EL2 flags to check as an argument, and call it from
13
the pattern.
13
new access_ticab() and access_tocu() functions as appropriate for
14
each cache op.
15
14
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
18
---
18
---
19
target/arm/helper.c | 36 +++++++++++++++++++++++-------------
19
include/fpu/softfloat-helpers.h | 11 +++++++
20
1 file changed, 23 insertions(+), 13 deletions(-)
20
include/fpu/softfloat-types.h | 10 ++++++
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
21
23
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
23
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
26
--- a/include/fpu/softfloat-helpers.h
25
+++ b/target/arm/helper.c
27
+++ b/include/fpu/softfloat-helpers.h
26
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
27
return CP_ACCESS_OK;
29
status->float_infzeronan_rule = rule;
28
}
30
}
29
31
30
-static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
31
- const ARMCPRegInfo *ri,
33
+ float_status *status)
32
- bool isread)
33
+static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
34
{
35
/* Cache invalidate/clean to Point of Unification... */
36
switch (arm_current_el(env)) {
37
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
38
}
39
/* fall through */
40
case 1:
41
- /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
42
- if (arm_hcr_el2_eff(env) & HCR_TPU) {
43
+ /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
44
+ if (arm_hcr_el2_eff(env) & hcrflags) {
45
return CP_ACCESS_TRAP_EL2;
46
}
47
break;
48
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
49
return CP_ACCESS_OK;
50
}
51
52
+static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
34
+{
55
+ return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
35
+ status->default_nan_pattern = dnan_pattern;
56
+}
36
+}
57
+
37
+
58
+static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
38
static inline void set_flush_to_zero(bool val, float_status *status)
59
+ bool isread)
39
{
40
status->flush_to_zero = val;
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
42
return status->float_infzeronan_rule;
43
}
44
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
60
+{
46
+{
61
+ return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
47
+ return status->default_nan_pattern;
62
+}
48
+}
63
+
49
+
64
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
50
static inline bool get_flush_to_zero(float_status *status)
65
* Page D4-1736 (DDI0487A.b)
51
{
66
*/
52
return status->flush_to_zero;
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
68
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
54
index XXXXXXX..XXXXXXX 100644
69
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
55
--- a/include/fpu/softfloat-types.h
70
.access = PL1_W, .type = ARM_CP_NOP,
56
+++ b/include/fpu/softfloat-types.h
71
- .accessfn = aa64_cacheop_pou_access },
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
72
+ .accessfn = access_ticab },
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
73
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
59
bool flush_inputs_to_zero;
74
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
60
bool default_nan_mode;
75
.access = PL1_W, .type = ARM_CP_NOP,
61
+ /*
76
- .accessfn = aa64_cacheop_pou_access },
62
+ * The pattern to use for the default NaN. Here the high bit specifies
77
+ .accessfn = access_tocu },
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
78
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
79
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
80
.access = PL0_W, .type = ARM_CP_NOP,
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
81
- .accessfn = aa64_cacheop_pou_access },
67
+ * this to the correct non-zero value, or we will assert when trying to
82
+ .accessfn = access_tocu },
68
+ * create a default NaN.
83
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
69
+ */
84
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
70
+ uint8_t default_nan_pattern;
85
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
71
/*
86
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
72
* The flags below are not used on all specializations and may
87
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
88
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
89
.access = PL0_W, .type = ARM_CP_NOP,
75
index XXXXXXX..XXXXXXX 100644
90
- .accessfn = aa64_cacheop_pou_access },
76
--- a/fpu/softfloat-specialize.c.inc
91
+ .accessfn = access_tocu },
77
+++ b/fpu/softfloat-specialize.c.inc
92
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
93
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
79
{
94
.access = PL0_W, .type = ARM_CP_NOP,
80
bool sign = 0;
95
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
81
uint64_t frac;
96
.writefn = tlbiipas2is_hyp_write },
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
97
/* 32 bit cache operations */
83
98
{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
84
+ if (dnan_pattern == 0) {
99
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
100
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
86
- /* !snan_bit_is_one, set all bits */
101
{ .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
102
.type = ARM_CP_NOP, .access = PL1_W },
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
103
{ .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
89
+ /* Sign bit clear, all frac bits set */
104
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
90
+ dnan_pattern = 0b01111111;
105
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
106
{ .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
92
|| defined(TARGET_MICROBLAZE)
107
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
93
- /* !snan_bit_is_one, set sign and msb */
108
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
109
{ .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
95
- sign = 1;
110
.type = ARM_CP_NOP, .access = PL1_W },
96
+ /* Sign bit set, most significant frac bit set */
111
{ .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
97
+ dnan_pattern = 0b11000000;
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
98
#elif defined(TARGET_HPPA)
113
{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
99
- /* snan_bit_is_one, set msb-1. */
114
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
115
{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
101
+ /* Sign bit clear, msb-1 frac bit set */
116
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
102
+ dnan_pattern = 0b00100000;
117
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
103
#elif defined(TARGET_HEXAGON)
118
{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
104
- sign = 1;
119
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
105
- frac = ~0ULL;
120
{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
106
+ /* Sign bit set, all frac bits set. */
107
+ dnan_pattern = 0b11111111;
108
#else
109
- /*
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
112
- * do not have floating-point.
113
- */
114
- if (snan_bit_is_one(status)) {
115
- /* set all bits other than msb */
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
117
- } else {
118
- /* set msb */
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
120
- }
121
+ /*
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
124
+ * do not have floating-point.
125
+ */
126
+ if (snan_bit_is_one(status)) {
127
+ /* sign bit clear, set all frac bits other than msb */
128
+ dnan_pattern = 0b00111111;
129
+ } else {
130
+ /* sign bit clear, set frac msb */
131
+ dnan_pattern = 0b01000000;
132
+ }
133
#endif
134
+ }
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
121
--
147
--
122
2.25.1
148
2.34.1
diff view generated by jsdifflib
[PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max'
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Update the ID registers for TCG's '-cpu max' to report the
1
Set the default NaN pattern explicitly for the tests/fp code.
2
FEAT_EVT Enhanced Virtualization Traps support.
3
2
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
6
---
7
docs/system/arm/emulation.rst | 1 +
7
tests/fp/fp-bench.c | 1 +
8
target/arm/cpu64.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
target/arm/cpu_tcg.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
10
3 files changed, 3 insertions(+)
11
11
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/emulation.rst
14
--- a/tests/fp/fp-bench.c
15
+++ b/docs/system/arm/emulation.rst
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
- FEAT_DoubleFault (Double Fault Extension)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
- FEAT_ETS (Enhanced Translation Synchronization)
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+- FEAT_EVT (Enhanced Virtualization Traps)
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
- FEAT_FCMA (Floating-point complex number instructions)
21
22
- FEAT_FHM (Floating-point half-precision multiplication instructions)
22
f = bench_funcs[operation][precision];
23
- FEAT_FP16 (Half-precision floating-point data processing)
23
g_assert(f);
24
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpu64.c
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/target/arm/cpu64.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
29
int i;
30
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
30
31
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
cpu->isar.id_aa64mmfr2 = t;
34
35
35
test.d = 0.0;
36
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu_tcg.c
38
--- a/tests/fp/fp-test.c
39
+++ b/target/arm/cpu_tcg.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
41
*/
42
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
cpu->isar.id_mmfr4 = t;
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
46
47
t = cpu->isar.id_mmfr5;
47
genCases_setLevel(test_level);
48
--
48
--
49
2.25.1
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
11
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/i386/tcg/fpu_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
17
*/
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
24
}
25
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
41
--
42
2.34.1
diff view generated by jsdifflib
New patch
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
11
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/hppa/fpu_helper.c
15
+++ b/target/hppa/fpu_helper.c
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
22
}
23
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_HPPA)
34
- /* Sign bit clear, msb-1 frac bit set */
35
- dnan_pattern = 0b00100000;
36
#elif defined(TARGET_HEXAGON)
37
/* Sign bit set, all frac bits set. */
38
dnan_pattern = 0b11111111;
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
6
Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org
7
---
9
---
8
hw/intc/arm_gicv3_kvm.c | 14 +++++++++-----
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
9
1 file changed, 9 insertions(+), 5 deletions(-)
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
10
13
11
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_kvm.c
16
--- a/linux-user/arm/nwfpe/fpa11.c
14
+++ b/hw/intc/arm_gicv3_kvm.c
17
+++ b/linux-user/arm/nwfpe/fpa11.c
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
16
struct KVMARMGICv3Class {
19
* this late date.
17
ARMGICv3CommonClass parent_class;
20
*/
18
DeviceRealize parent_realize;
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
19
- void (*parent_reset)(DeviceState *dev);
22
+ /*
20
+ ResettablePhases parent_phases;
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
21
};
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
22
25
+ */
23
static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
24
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
25
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
26
}
27
}
27
28
28
-static void kvm_arm_gicv3_reset(DeviceState *dev)
29
void SetRoundingMode(const unsigned int opcode)
29
+static void kvm_arm_gicv3_reset_hold(Object *obj)
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
35
* the pseudocode function the arguments are in the order c, a, b.
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
37
* and the input NaN if it is signalling
38
+ * * Default NaN has sign bit clear, msb frac bit set
39
*/
40
static void arm_set_default_fp_behaviours(float_status *s)
30
{
41
{
31
- GICv3State *s = ARM_GICV3_COMMON(dev);
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
32
+ GICv3State *s = ARM_GICV3_COMMON(obj);
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
33
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
34
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
35
DPRINTF("Reset\n");
46
+ set_float_default_nan_pattern(0b01000000, s);
36
37
- kgc->parent_reset(dev);
38
+ if (kgc->parent_phases.hold) {
39
+ kgc->parent_phases.hold(obj);
40
+ }
41
42
if (s->migration_blocker) {
43
DPRINTF("Cannot put kernel gic state, no kernel interface\n");
44
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
45
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
46
{
47
DeviceClass *dc = DEVICE_CLASS(klass);
48
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
49
ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
50
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
51
52
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
53
agcc->post_load = kvm_arm_gicv3_put;
54
device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
55
&kgc->parent_realize);
56
- device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
57
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL,
58
+ &kgc->parent_phases);
59
}
47
}
60
48
61
static const TypeInfo kvm_arm_gicv3_info = {
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
62
--
50
--
63
2.25.1
51
2.34.1
64
65
diff view generated by jsdifflib
New patch
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for loongarch.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/loongarch/tcg/fpu_helper.c
13
+++ b/target/loongarch/tcg/fpu_helper.c
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
15
*/
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
}
21
22
int ieee_ex_to_loongarch(int xcpt)
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
6
Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org
7
---
9
---
8
hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++-----
10
target/mips/fpu_helper.h | 7 +++++++
9
1 file changed, 9 insertions(+), 5 deletions(-)
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
10
13
11
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_its_kvm.c
16
--- a/target/mips/fpu_helper.h
14
+++ b/hw/intc/arm_gicv3_its_kvm.c
17
+++ b/target/mips/fpu_helper.h
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
16
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
17
struct KVMARMITSClass {
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
18
GICv3ITSCommonClass parent_class;
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
19
- void (*parent_reset)(DeviceState *dev);
22
+ /*
20
+ ResettablePhases parent_phases;
23
+ * With nan2008, the default NaN value has the sign bit clear and the
21
};
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
22
25
+ * frac bits except the msb are set.
23
26
+ */
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
25
GITS_CTLR, &s->ctlr, true, &error_abort);
28
+ &env->active_fpu.fp_status);
29
26
}
30
}
27
31
28
-static void kvm_arm_its_reset(DeviceState *dev)
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
29
+static void kvm_arm_its_reset_hold(Object *obj)
33
index XXXXXXX..XXXXXXX 100644
30
{
34
--- a/target/mips/msa.c
31
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
35
+++ b/target/mips/msa.c
32
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
33
KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
37
/* Inf * 0 + NaN returns the input NaN */
34
int i;
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
35
39
&env->active_tc.msa_fp_status);
36
- c->parent_reset(dev);
40
+ /* Default NaN: sign bit clear, frac msb set */
37
+ if (c->parent_phases.hold) {
41
+ set_float_default_nan_pattern(0b01000000,
38
+ c->parent_phases.hold(obj);
42
+ &env->active_tc.msa_fp_status);
39
+ }
43
}
40
41
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
42
KVM_DEV_ARM_ITS_CTRL_RESET)) {
43
@@ -XXX,XX +XXX,XX @@ static Property kvm_arm_its_props[] = {
44
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
48
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
49
KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
50
51
dc->realize = kvm_arm_its_realize;
52
device_class_set_props(dc, kvm_arm_its_props);
53
- device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
54
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
55
+ &ic->parent_phases);
56
icc->send_msi = kvm_its_send_msi;
57
icc->pre_save = kvm_arm_its_pre_save;
58
icc->post_load = kvm_arm_its_post_load;
59
--
44
--
60
2.25.1
45
2.34.1
61
62
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.
1
Set the default NaN pattern explicitly for ppc.
2
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
6
Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org
7
---
6
---
8
hw/intc/arm_gicv3_its.c | 14 +++++++++-----
7
target/ppc/cpu_init.c | 4 ++++
9
1 file changed, 9 insertions(+), 5 deletions(-)
8
1 file changed, 4 insertions(+)
10
9
11
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_its.c
12
--- a/target/ppc/cpu_init.c
14
+++ b/hw/intc/arm_gicv3_its.c
13
+++ b/target/ppc/cpu_init.c
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
16
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
struct GICv3ITSClass {
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
18
GICv3ITSCommonClass parent_class;
17
19
- void (*parent_reset)(DeviceState *dev);
18
+ /* Default NaN: sign bit clear, set frac msb */
20
+ ResettablePhases parent_phases;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
};
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
22
21
+
23
/*
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
24
@@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
23
ppc_spr_t *spr = &env->spr_cb[i];
25
}
26
}
27
28
-static void gicv3_its_reset(DeviceState *dev)
29
+static void gicv3_its_reset_hold(Object *obj)
30
{
31
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
32
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
33
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
34
35
- c->parent_reset(dev);
36
+ if (c->parent_phases.hold) {
37
+ c->parent_phases.hold(obj);
38
+ }
39
40
/* Quiescent bit reset to 1 */
41
s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
42
@@ -XXX,XX +XXX,XX @@ static Property gicv3_its_props[] = {
43
static void gicv3_its_class_init(ObjectClass *klass, void *data)
44
{
45
DeviceClass *dc = DEVICE_CLASS(klass);
46
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
47
GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
48
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
49
50
dc->realize = gicv3_arm_its_realize;
51
device_class_set_props(dc, gicv3_its_props);
52
- device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
53
+ resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL,
54
+ &ic->parent_phases);
55
icc->post_load = gicv3_its_post_load;
56
}
57
24
58
--
25
--
59
2.25.1
26
2.34.1
60
61
diff view generated by jsdifflib
[PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
6
Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org
7
---
8
---
8
hw/intc/arm_gicv3_common.c | 7 ++++---
9
target/sh4/cpu.c | 2 ++
9
1 file changed, 4 insertions(+), 3 deletions(-)
10
1 file changed, 2 insertions(+)
10
11
11
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_common.c
14
--- a/target/sh4/cpu.c
14
+++ b/hw/intc/arm_gicv3_common.c
15
+++ b/target/sh4/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj)
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
16
g_free(s->redist_region_count);
17
set_flush_to_zero(1, &env->fp_status);
18
#endif
19
set_default_nan_mode(1, &env->fp_status);
20
+ /* sign bit clear, set all frac bits other than msb */
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
17
}
22
}
18
23
19
-static void arm_gicv3_common_reset(DeviceState *dev)
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
20
+static void arm_gicv3_common_reset_hold(Object *obj)
21
{
22
- GICv3State *s = ARM_GICV3_COMMON(dev);
23
+ GICv3State *s = ARM_GICV3_COMMON(obj);
24
int i;
25
26
for (i = 0; i < s->num_cpu; i++) {
27
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
28
static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
29
{
30
DeviceClass *dc = DEVICE_CLASS(klass);
31
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
32
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
33
34
- dc->reset = arm_gicv3_common_reset;
35
+ rc->phases.hold = arm_gicv3_common_reset_hold;
36
dc->realize = arm_gicv3_common_realize;
37
device_class_set_props(dc, arm_gicv3_common_properties);
38
dc->vmsd = &vmstate_gicv3;
39
--
25
--
40
2.25.1
26
2.34.1
41
42
diff view generated by jsdifflib
[PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy
1
Set the default NaN pattern explicitly for rx.
2
reset method doesn't do anything that's invalid in the hold phase, so
3
the conversion only requires changing it to a hold phase method, and
4
using the 3-phase versions of the "save the parent reset method and
5
chain to it" code.
6
2
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
12
---
6
---
13
include/hw/arm/smmuv3.h | 2 +-
7
target/rx/cpu.c | 2 ++
14
hw/arm/smmuv3.c | 12 ++++++++----
8
1 file changed, 2 insertions(+)
15
2 files changed, 9 insertions(+), 5 deletions(-)
16
9
17
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
18
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/smmuv3.h
12
--- a/target/rx/cpu.c
20
+++ b/include/hw/arm/smmuv3.h
13
+++ b/target/rx/cpu.c
21
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
22
/*< public >*/
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
23
16
*/
24
DeviceRealize parent_realize;
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
25
- DeviceReset parent_reset;
18
+ /* Default NaN value: sign bit clear, set frac msb */
26
+ ResettablePhases parent_phases;
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
27
};
28
29
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
30
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/smmuv3.c
33
+++ b/hw/arm/smmuv3.c
34
@@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
35
}
36
}
20
}
37
21
38
-static void smmu_reset(DeviceState *dev)
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
39
+static void smmu_reset_hold(Object *obj)
40
{
41
- SMMUv3State *s = ARM_SMMUV3(dev);
42
+ SMMUv3State *s = ARM_SMMUV3(obj);
43
SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
44
45
- c->parent_reset(dev);
46
+ if (c->parent_phases.hold) {
47
+ c->parent_phases.hold(obj);
48
+ }
49
50
smmuv3_init_regs(s);
51
}
52
@@ -XXX,XX +XXX,XX @@ static void smmuv3_instance_init(Object *obj)
53
static void smmuv3_class_init(ObjectClass *klass, void *data)
54
{
55
DeviceClass *dc = DEVICE_CLASS(klass);
56
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
57
SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
58
59
dc->vmsd = &vmstate_smmuv3;
60
- device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
61
+ resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
62
+ &c->parent_phases);
63
c->parent_realize = dc->realize;
64
dc->realize = smmu_realize;
65
}
66
--
23
--
67
2.25.1
24
2.34.1
68
69
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
1
Set the default NaN pattern explicitly for xtensa.
2
use of TLB maintenance instructions that operate on the
3
outer shareable domain:
4
5
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
6
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
7
TLBI RVALE1OS, and TLBI RVAALE1OS.
8
9
(There are no AArch32 outer-shareable TLB maintenance ops.)
10
11
Implement the trapping.
12
2
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
15
---
6
---
16
target/arm/helper.c | 33 +++++++++++++++++++++++----------
7
target/xtensa/cpu.c | 2 ++
17
1 file changed, 23 insertions(+), 10 deletions(-)
8
1 file changed, 2 insertions(+)
18
9
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
12
--- a/target/xtensa/cpu.c
22
+++ b/target/arm/helper.c
13
+++ b/target/xtensa/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
24
return CP_ACCESS_OK;
15
/* For inf * 0 + NaN, return the input NaN */
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
set_no_signaling_nans(!dfpu, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, set frac msb */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
xtensa_use_first_nan(env, !dfpu);
25
}
21
}
26
22
27
+#ifdef TARGET_AARCH64
28
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
29
+static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
30
+ bool isread)
31
+{
32
+ if (arm_current_el(env) == 1 &&
33
+ (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
34
+ return CP_ACCESS_TRAP_EL2;
35
+ }
36
+ return CP_ACCESS_OK;
37
+}
38
+#endif
39
+
40
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
41
{
42
ARMCPU *cpu = env_archcpu(env);
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
44
.writefn = tlbi_aa64_rvae1is_write },
45
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
46
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
47
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
48
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
49
.writefn = tlbi_aa64_rvae1is_write },
50
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
51
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
52
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
53
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
54
.writefn = tlbi_aa64_rvae1is_write },
55
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
56
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
57
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
58
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
59
.writefn = tlbi_aa64_rvae1is_write },
60
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
62
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
63
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
64
.writefn = tlbi_aa64_rvae1is_write },
65
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
66
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
68
static const ARMCPRegInfo tlbios_reginfo[] = {
69
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
70
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
71
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
72
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
73
.writefn = tlbi_aa64_vmalle1is_write },
74
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
75
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
76
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
77
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
78
.writefn = tlbi_aa64_vae1is_write },
79
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
80
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
81
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
82
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
83
.writefn = tlbi_aa64_vmalle1is_write },
84
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
85
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
86
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
87
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
88
.writefn = tlbi_aa64_vae1is_write },
89
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
90
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
91
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
92
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
93
.writefn = tlbi_aa64_vae1is_write },
94
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
95
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
96
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
97
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
98
.writefn = tlbi_aa64_vae1is_write },
99
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
100
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
101
--
23
--
102
2.25.1
24
2.34.1
diff view generated by jsdifflib
[PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
7
---
8
---
8
hw/intc/arm_gicv3_its_common.c | 7 ++++---
9
target/hexagon/cpu.c | 2 ++
9
1 file changed, 4 insertions(+), 3 deletions(-)
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
10
12
11
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/intc/arm_gicv3_its_common.c
15
--- a/target/hexagon/cpu.c
14
+++ b/hw/intc/arm_gicv3_its_common.c
16
+++ b/target/hexagon/cpu.c
15
@@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
16
msi_nonbroken = true;
18
19
set_default_nan_mode(1, &env->fp_status);
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
21
+ /* Default NaN value: sign bit set, all frac bits set */
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
17
}
23
}
18
24
19
-static void gicv3_its_common_reset(DeviceState *dev)
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
20
+static void gicv3_its_common_reset_hold(Object *obj)
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
21
{
27
index XXXXXXX..XXXXXXX 100644
22
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
28
--- a/fpu/softfloat-specialize.c.inc
23
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
29
+++ b/fpu/softfloat-specialize.c.inc
24
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
25
s->ctlr = 0;
31
uint8_t dnan_pattern = status->default_nan_pattern;
26
s->cbaser = 0;
32
27
@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
33
if (dnan_pattern == 0) {
28
static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
34
-#if defined(TARGET_HEXAGON)
29
{
35
- /* Sign bit set, all frac bits set. */
30
DeviceClass *dc = DEVICE_CLASS(klass);
36
- dnan_pattern = 0b11111111;
31
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
37
-#else
32
38
/*
33
- dc->reset = gicv3_its_common_reset;
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
34
+ rc->phases.hold = gicv3_its_common_reset_hold;
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
35
dc->vmsd = &vmstate_its;
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
36
}
42
/* sign bit clear, set frac msb */
43
dnan_pattern = 0b01000000;
44
}
45
-#endif
46
}
47
assert(dnan_pattern != 0);
37
48
38
--
49
--
39
2.25.1
50
2.34.1
40
41
diff view generated by jsdifflib
New patch
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for riscv.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/cpu.c
13
+++ b/target/riscv/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
15
cs->exception_index = RISCV_EXCP_NONE;
16
env->load_res = -1;
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
env->vill = true;
21
22
#ifndef CONFIG_USER_ONLY
23
--
24
2.34.1
diff view generated by jsdifflib
[PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
1
Set the default NaN pattern explicitly for tricore.
2
TLB maintenance instructions that operate on the inner shareable
3
domain:
4
5
AArch64:
6
TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
7
TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
8
TLBI RVALE1IS, and TLBI RVAALE1IS.
9
10
AArch32:
11
TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
12
and TLBIMVAALIS.
13
14
Add the trapping support.
15
2
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
18
---
6
---
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++----------------
7
target/tricore/helper.c | 2 ++
20
1 file changed, 27 insertions(+), 16 deletions(-)
8
1 file changed, 2 insertions(+)
21
9
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
23
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
12
--- a/target/tricore/helper.c
25
+++ b/target/arm/helper.c
13
+++ b/target/tricore/helper.c
26
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
27
return CP_ACCESS_OK;
15
set_flush_to_zero(1, &env->fp_status);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
17
set_default_nan_mode(1, &env->fp_status);
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
28
}
20
}
29
21
30
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
22
uint32_t psw_read(CPUTriCoreState *env)
31
+static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
32
+ bool isread)
33
+{
34
+ if (arm_current_el(env) == 1 &&
35
+ (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
36
+ return CP_ACCESS_TRAP_EL2;
37
+ }
38
+ return CP_ACCESS_OK;
39
+}
40
+
41
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
42
{
43
ARMCPU *cpu = env_archcpu(env);
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
45
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
46
/* 32 bit TLB invalidates, Inner Shareable */
47
{ .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
48
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
49
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
50
.writefn = tlbiall_is_write },
51
{ .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
52
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
53
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
54
.writefn = tlbimva_is_write },
55
{ .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
56
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
57
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
58
.writefn = tlbiasid_is_write },
59
{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
60
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
61
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
62
.writefn = tlbimvaa_is_write },
63
};
64
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
66
/* TLBI operations */
67
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
68
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
69
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
70
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
71
.writefn = tlbi_aa64_vmalle1is_write },
72
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
73
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
74
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
75
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
76
.writefn = tlbi_aa64_vae1is_write },
77
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
78
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
79
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
80
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
81
.writefn = tlbi_aa64_vmalle1is_write },
82
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
83
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
84
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
85
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
86
.writefn = tlbi_aa64_vae1is_write },
87
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
88
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
89
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
90
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
91
.writefn = tlbi_aa64_vae1is_write },
92
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
93
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
94
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
95
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
96
.writefn = tlbi_aa64_vae1is_write },
97
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
98
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
100
#endif
101
/* TLB invalidate last level of translation table walk */
102
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
103
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
104
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
105
.writefn = tlbimva_is_write },
106
{ .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
107
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
108
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
109
.writefn = tlbimvaa_is_write },
110
{ .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
111
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
113
static const ARMCPRegInfo tlbirange_reginfo[] = {
114
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
115
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
116
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
117
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
118
.writefn = tlbi_aa64_rvae1is_write },
119
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
120
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
121
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
122
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
123
.writefn = tlbi_aa64_rvae1is_write },
124
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
125
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
126
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
127
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
128
.writefn = tlbi_aa64_rvae1is_write },
129
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
130
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
131
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
132
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
133
.writefn = tlbi_aa64_rvae1is_write },
134
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
135
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
136
--
23
--
137
2.25.1
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
8
---
9
fpu/softfloat-specialize.c.inc | 14 --------------
10
1 file changed, 14 deletions(-)
11
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
13
index XXXXXXX..XXXXXXX 100644
14
--- a/fpu/softfloat-specialize.c.inc
15
+++ b/fpu/softfloat-specialize.c.inc
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
17
uint64_t frac;
18
uint8_t dnan_pattern = status->default_nan_pattern;
19
20
- if (dnan_pattern == 0) {
21
- /*
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
- * do not have floating-point.
25
- */
26
- if (snan_bit_is_one(status)) {
27
- /* sign bit clear, set all frac bits other than msb */
28
- dnan_pattern = 0b00111111;
29
- } else {
30
- /* sign bit clear, set frac msb */
31
- dnan_pattern = 0b01000000;
32
- }
33
- }
34
assert(dnan_pattern != 0);
35
36
sign = dnan_pattern >> 7;
37
--
38
2.34.1
diff view generated by jsdifflib
[PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a
1
From: Richard Henderson <richard.henderson@linaro.org>
2
simple no-behaviour-change conversion.
3
2
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org
8
---
11
---
9
hw/intc/arm_gic_common.c | 7 ++++---
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
10
1 file changed, 4 insertions(+), 3 deletions(-)
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
14
2 files changed, 40 insertions(+), 55 deletions(-)
11
15
12
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/intc/arm_gic_common.c
18
--- a/fpu/softfloat-parts.c.inc
15
+++ b/hw/intc/arm_gic_common.c
19
+++ b/fpu/softfloat-parts.c.inc
16
@@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
21
}
22
23
if (s->default_nan_mode) {
24
+ /*
25
+ * We guarantee not to require the target to tell us how to
26
+ * pick a NaN if we're always returning the default NaN.
27
+ * But if we're not in default-NaN mode then the target must
28
+ * specify.
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
53
+
54
+ assert(rule != float_3nan_prop_none);
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
56
+ /* We have at least one SNaN input and should prefer it */
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
71
index XXXXXXX..XXXXXXX 100644
72
--- a/fpu/softfloat-specialize.c.inc
73
+++ b/fpu/softfloat-specialize.c.inc
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
17
}
75
}
18
}
76
}
19
77
20
-static void arm_gic_common_reset(DeviceState *dev)
78
-/*----------------------------------------------------------------------------
21
+static void arm_gic_common_reset_hold(Object *obj)
79
-| Select which NaN to propagate for a three-input operation.
22
{
80
-| For the moment we assume that no CPU needs the 'larger significand'
23
- GICState *s = ARM_GIC_COMMON(dev);
81
-| information.
24
+ GICState *s = ARM_GIC_COMMON(obj);
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
25
int i, j;
83
-*----------------------------------------------------------------------------*/
26
int resetprio;
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
27
85
- bool infzero, bool have_snan, float_status *status)
28
@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {
86
-{
29
static void arm_gic_common_class_init(ObjectClass *klass, void *data)
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
30
{
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
31
DeviceClass *dc = DEVICE_CLASS(klass);
89
- int which;
32
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
90
-
33
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
91
- /*
34
92
- * We guarantee not to require the target to tell us how to
35
- dc->reset = arm_gic_common_reset;
93
- * pick a NaN if we're always returning the default NaN.
36
+ rc->phases.hold = arm_gic_common_reset_hold;
94
- * But if we're not in default-NaN mode then the target must
37
dc->realize = arm_gic_common_realize;
95
- * specify.
38
device_class_set_props(dc, arm_gic_common_properties);
96
- */
39
dc->vmsd = &vmstate_gic;
97
- assert(!status->default_nan_mode);
98
-
99
- if (infzero) {
100
- /*
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
106
- return 2;
107
- case float_infzeronan_dnan_always:
108
- return 3;
109
- case float_infzeronan_dnan_if_qnan:
110
- return is_qnan(c_cls) ? 3 : 2;
111
- default:
112
- g_assert_not_reached();
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
123
- } else {
124
- do {
125
- which = rule & R_3NAN_1ST_MASK;
126
- rule >>= R_3NAN_1ST_LENGTH;
127
- } while (!is_nan(cls[which]));
128
- }
129
- return which;
130
-}
131
-
132
/*----------------------------------------------------------------------------
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
134
| NaN; otherwise returns 0.
40
--
135
--
41
2.25.1
136
2.34.1
42
137
43
138
diff view generated by jsdifflib
[PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method
1
From: Richard Henderson <richard.henderson@linaro.org>
2
doesn't do anything that's invalid in the hold phase, so the
3
conversion is simple and not a behaviour change.
4
2
5
Note that we must convert this base class before we can convert the
3
Remove "3" as a special case for which and simply
6
TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable
4
branch to return the desired value.
7
handles "chain to parent class reset" when the base class is 3-phase
8
and the subclass is still using legacy reset, but not the other way
9
around.
10
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
16
---
10
---
17
hw/arm/smmu-common.c | 7 ++++---
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
18
1 file changed, 4 insertions(+), 3 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
19
13
20
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/smmu-common.c
16
--- a/fpu/softfloat-parts.c.inc
23
+++ b/hw/arm/smmu-common.c
17
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
* But if we're not in default-NaN mode then the target must
20
* specify.
21
*/
22
- which = 3;
23
+ goto default_nan;
24
} else if (infzero) {
25
/*
26
* Inf * 0 + NaN -- some implementations return the
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
28
*/
29
switch (s->float_infzeronan_rule) {
30
case float_infzeronan_dnan_never:
31
- which = 2;
32
break;
33
case float_infzeronan_dnan_always:
34
- which = 3;
35
- break;
36
+ goto default_nan;
37
case float_infzeronan_dnan_if_qnan:
38
- which = is_qnan(c->cls) ? 3 : 2;
39
+ if (is_qnan(c->cls)) {
40
+ goto default_nan;
41
+ }
42
break;
43
default:
44
g_assert_not_reached();
45
}
46
+ which = 2;
47
} else {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
51
}
25
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
58
-
59
switch (which) {
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
66
+
67
+ default_nan:
68
+ parts_default_nan(a, s);
69
+ return a;
26
}
70
}
27
71
28
-static void smmu_base_reset(DeviceState *dev)
72
/*
29
+static void smmu_base_reset_hold(Object *obj)
30
{
31
- SMMUState *s = ARM_SMMU(dev);
32
+ SMMUState *s = ARM_SMMU(obj);
33
34
g_hash_table_remove_all(s->configs);
35
g_hash_table_remove_all(s->iotlb);
36
@@ -XXX,XX +XXX,XX @@ static Property smmu_dev_properties[] = {
37
static void smmu_base_class_init(ObjectClass *klass, void *data)
38
{
39
DeviceClass *dc = DEVICE_CLASS(klass);
40
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
41
SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
42
43
device_class_set_props(dc, smmu_dev_properties);
44
device_class_set_parent_realize(dc, smmu_base_realize,
45
&sbc->parent_realize);
46
- dc->reset = smmu_base_reset;
47
+ rc->phases.hold = smmu_base_reset_hold;
48
}
49
50
static const TypeInfo smmu_base_info = {
51
--
73
--
52
2.25.1
74
2.34.1
53
75
54
76
diff view generated by jsdifflib
New patch
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Assign the pointer return value to 'a' directly,
4
rather than going through an intermediary index.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
12
1 file changed, 10 insertions(+), 22 deletions(-)
13
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
FloatPartsN *c, float_status *s,
20
int ab_mask, int abc_mask)
21
{
22
- int which;
23
bool infzero = (ab_mask == float_cmask_infzero);
24
bool have_snan = (abc_mask & float_cmask_snan);
25
+ FloatPartsN *ret;
26
27
if (unlikely(have_snan)) {
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
30
default:
31
g_assert_not_reached();
32
}
33
- which = 2;
34
+ ret = c;
35
} else {
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
37
+ FloatPartsN *val[3] = { a, b, c };
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
40
assert(rule != float_3nan_prop_none);
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
42
/* We have at least one SNaN input and should prefer it */
43
do {
44
- which = rule & R_3NAN_1ST_MASK;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
56
}
57
}
58
59
- switch (which) {
60
- case 0:
61
- break;
62
- case 1:
63
- a = b;
64
- break;
65
- case 2:
66
- a = c;
67
- break;
68
- default:
69
- g_assert_not_reached();
70
+ if (is_snan(ret->cls)) {
71
+ parts_silence_nan(ret, s);
72
}
73
- if (is_snan(a->cls)) {
74
- parts_silence_nan(a, s);
75
- }
76
- return a;
77
+ return ret;
78
79
default_nan:
80
parts_default_nan(a, s);
81
--
82
2.34.1
83
84
diff view generated by jsdifflib
[PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Thomas Huth <thuth@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
3
While all indices into val[] should be in [0-2], the mask
4
poisoned in common code, so the files that include this header have to
4
applied is two bits. To help static analysis see there is
5
be added to specific_ss and recompiled for each, qemu-system-arm and
5
no possibility of read beyond the end of the array, pad the
6
qemu-system-aarch64. However, since the kvm headers are only optionally
6
array to 4 entries, with the final being (implicitly) NULL.
7
used in kvm-constants.h for some sanity checks, we can additionally
8
check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro,
9
so kvm-constants.h can also be used from "common" files (without the
10
sanity checks - which should be OK since they are still done from other
11
target-specific files instead). This way, and by adjusting some other
12
include statements in the related files here and there, we can move some
13
files from specific_ss into softmmu_ss, so that they only need to be
14
compiled once during the build process.
15
7
16
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20221202154023.293614-1-thuth@redhat.com
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
12
---
21
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
13
fpu/softfloat-parts.c.inc | 2 +-
22
target/arm/kvm-consts.h | 8 ++++----
14
1 file changed, 1 insertion(+), 1 deletion(-)
23
hw/misc/imx6_src.c | 2 +-
24
hw/misc/iotkit-sysctl.c | 1 -
25
hw/misc/meson.build | 11 +++++------
26
5 files changed, 11 insertions(+), 13 deletions(-)
27
15
28
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
29
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
18
--- a/fpu/softfloat-parts.c.inc
31
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
19
+++ b/fpu/softfloat-parts.c.inc
32
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
33
21
}
34
#include "hw/sysbus.h"
22
ret = c;
35
#include "hw/register.h"
23
} else {
36
-#include "target/arm/cpu.h"
24
- FloatPartsN *val[3] = { a, b, c };
37
+#include "target/arm/cpu-qom.h"
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
38
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
39
#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
27
40
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
28
assert(rule != float_3nan_prop_none);
41
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/kvm-consts.h
44
+++ b/target/arm/kvm-consts.h
45
@@ -XXX,XX +XXX,XX @@
46
#ifndef ARM_KVM_CONSTS_H
47
#define ARM_KVM_CONSTS_H
48
49
+#ifdef NEED_CPU_H
50
#ifdef CONFIG_KVM
51
#include <linux/kvm.h>
52
#include <linux/psci.h>
53
-
54
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
55
+#endif
56
+#endif
57
58
-#else
59
-
60
+#ifndef MISMATCH_CHECK
61
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
62
-
63
#endif
64
65
#define CP_REG_SIZE_SHIFT 52
66
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/misc/imx6_src.c
69
+++ b/hw/misc/imx6_src.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "qemu/log.h"
72
#include "qemu/main-loop.h"
73
#include "qemu/module.h"
74
-#include "arm-powerctl.h"
75
+#include "target/arm/arm-powerctl.h"
76
#include "hw/core/cpu.h"
77
78
#ifndef DEBUG_IMX6_SRC
79
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/misc/iotkit-sysctl.c
82
+++ b/hw/misc/iotkit-sysctl.c
83
@@ -XXX,XX +XXX,XX @@
84
#include "hw/qdev-properties.h"
85
#include "hw/arm/armsse-version.h"
86
#include "target/arm/arm-powerctl.h"
87
-#include "target/arm/cpu.h"
88
89
REG32(SECDBGSTAT, 0x0)
90
REG32(SECDBGSET, 0x4)
91
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/meson.build
94
+++ b/hw/misc/meson.build
95
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
96
'imx25_ccm.c',
97
'imx31_ccm.c',
98
'imx6_ccm.c',
99
+ 'imx6_src.c',
100
'imx6ul_ccm.c',
101
'imx7_ccm.c',
102
'imx7_gpr.c',
103
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
104
))
105
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
106
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
107
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
108
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
109
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
110
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
111
specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
112
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
113
'xlnx-versal-xramc.c',
114
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c'))
115
softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
116
softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
117
softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
118
+softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
119
softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
120
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
121
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
122
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
123
124
specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
125
126
-specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c'))
127
-specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
128
-
129
specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
130
131
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
132
specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
133
134
-specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
135
+softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
136
137
# HPPA devices
138
softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
139
--
29
--
140
2.25.1
30
2.34.1
141
31
142
32
diff view generated by jsdifflib
[PULL 09/29] target/arm: Add Cortex-A55 CPU
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Timofey Kutergin <tkutergin@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
3
This function is part of the public interface and
4
it supports the Privileged Access Never (PAN) feature. Add
4
is not "specialized" to any target in any way.
5
a model of this CPU, so you can use a CPU type on the virt
6
board that models a specific real hardware CPU, rather than
7
having to use the QEMU-specific "max" CPU type.
8
5
9
Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20221121150819.2782817-1-tkutergin@gmail.com
11
[PMM: tweaked commit message]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
docs/system/arm/virt.rst | 1 +
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
16
hw/arm/virt.c | 1 +
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
17
target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++
13
2 files changed, 52 insertions(+), 52 deletions(-)
18
3 files changed, 71 insertions(+)
19
14
20
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/docs/system/arm/virt.rst
17
--- a/fpu/softfloat.c
23
+++ b/docs/system/arm/virt.rst
18
+++ b/fpu/softfloat.c
24
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
25
- ``cortex-a15`` (32-bit; the default)
20
*zExpPtr = 1 - shiftCount;
26
- ``cortex-a35`` (64-bit)
27
- ``cortex-a53`` (64-bit)
28
+- ``cortex-a55`` (64-bit)
29
- ``cortex-a57`` (64-bit)
30
- ``cortex-a72`` (64-bit)
31
- ``cortex-a76`` (64-bit)
32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/virt.c
35
+++ b/hw/arm/virt.c
36
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
37
ARM_CPU_TYPE_NAME("cortex-a15"),
38
ARM_CPU_TYPE_NAME("cortex-a35"),
39
ARM_CPU_TYPE_NAME("cortex-a53"),
40
+ ARM_CPU_TYPE_NAME("cortex-a55"),
41
ARM_CPU_TYPE_NAME("cortex-a57"),
42
ARM_CPU_TYPE_NAME("cortex-a72"),
43
ARM_CPU_TYPE_NAME("cortex-a76"),
44
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu64.c
47
+++ b/target/arm/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
49
define_cortex_a72_a57_a53_cp_reginfo(cpu);
50
}
21
}
51
22
52
+static void aarch64_a55_initfn(Object *obj)
23
+/*----------------------------------------------------------------------------
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+*----------------------------------------------------------------------------*/
28
+
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
53
+{
30
+{
54
+ ARMCPU *cpu = ARM_CPU(obj);
31
+ bool aIsLargerSignificand;
32
+ FloatClass a_cls, b_cls;
55
+
33
+
56
+ cpu->dtb_compatible = "arm,cortex-a55";
34
+ /* This is not complete, but is good enough for pickNaN. */
57
+ set_feature(&cpu->env, ARM_FEATURE_V8);
35
+ a_cls = (!floatx80_is_any_nan(a)
58
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
36
+ ? float_class_normal
59
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
37
+ : floatx80_is_signaling_nan(a, status)
60
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
38
+ ? float_class_snan
61
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
39
+ : float_class_qnan);
62
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
40
+ b_cls = (!floatx80_is_any_nan(b)
63
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
41
+ ? float_class_normal
64
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
65
+
45
+
66
+ /* Ordered by B2.4 AArch64 registers by functional group */
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
67
+ cpu->clidr = 0x82000023;
47
+ float_raise(float_flag_invalid, status);
68
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
48
+ }
69
+ cpu->dcz_blocksize = 4; /* 64 bytes */
70
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
71
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
72
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
73
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
74
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
75
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
76
+ cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
77
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
78
+ cpu->id_afr0 = 0x00000000;
79
+ cpu->isar.id_dfr0 = 0x04010088;
80
+ cpu->isar.id_isar0 = 0x02101110;
81
+ cpu->isar.id_isar1 = 0x13112111;
82
+ cpu->isar.id_isar2 = 0x21232042;
83
+ cpu->isar.id_isar3 = 0x01112131;
84
+ cpu->isar.id_isar4 = 0x00011142;
85
+ cpu->isar.id_isar5 = 0x01011121;
86
+ cpu->isar.id_isar6 = 0x00000010;
87
+ cpu->isar.id_mmfr0 = 0x10201105;
88
+ cpu->isar.id_mmfr1 = 0x40000000;
89
+ cpu->isar.id_mmfr2 = 0x01260000;
90
+ cpu->isar.id_mmfr3 = 0x02122211;
91
+ cpu->isar.id_mmfr4 = 0x00021110;
92
+ cpu->isar.id_pfr0 = 0x10010131;
93
+ cpu->isar.id_pfr1 = 0x00011011;
94
+ cpu->isar.id_pfr2 = 0x00000011;
95
+ cpu->midr = 0x412FD050; /* r2p0 */
96
+ cpu->revidr = 0;
97
+
49
+
98
+ /* From B2.23 CCSIDR_EL1 */
50
+ if (status->default_nan_mode) {
99
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
51
+ return floatx80_default_nan(status);
100
+ cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
52
+ }
101
+ cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
102
+
53
+
103
+ /* From B2.96 SCTLR_EL3 */
54
+ if (a.low < b.low) {
104
+ cpu->reset_sctlr = 0x30c50838;
55
+ aIsLargerSignificand = 0;
56
+ } else if (b.low < a.low) {
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
105
+
61
+
106
+ /* From B4.45 ICH_VTR_EL2 */
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
107
+ cpu->gic_num_lrs = 4;
63
+ if (is_snan(b_cls)) {
108
+ cpu->gic_vpribits = 5;
64
+ return floatx80_silence_nan(b, status);
109
+ cpu->gic_vprebits = 5;
65
+ }
110
+ cpu->gic_pribits = 5;
66
+ return b;
111
+
67
+ } else {
112
+ cpu->isar.mvfr0 = 0x10110222;
68
+ if (is_snan(a_cls)) {
113
+ cpu->isar.mvfr1 = 0x13211111;
69
+ return floatx80_silence_nan(a, status);
114
+ cpu->isar.mvfr2 = 0x00000043;
70
+ }
115
+
71
+ return a;
116
+ /* From D5.4 AArch64 PMU register summary */
72
+ }
117
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
118
+}
73
+}
119
+
74
+
120
static void aarch64_a72_initfn(Object *obj)
75
/*----------------------------------------------------------------------------
121
{
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
122
ARMCPU *cpu = ARM_CPU(obj);
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
123
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
124
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
79
index XXXXXXX..XXXXXXX 100644
125
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
80
--- a/fpu/softfloat-specialize.c.inc
126
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
81
+++ b/fpu/softfloat-specialize.c.inc
127
+ { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
128
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
83
return a;
129
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
84
}
130
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
85
86
-/*----------------------------------------------------------------------------
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
93
-{
94
- bool aIsLargerSignificand;
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
131
--
141
--
132
2.25.1
142
2.34.1
diff view generated by jsdifflib
[PULL 07/29] hw/arm/virt: Add properties to disable high memory regions
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The 3 high memory regions are usually enabled by default, but they may
3
Unpacking and repacking the parts may be slightly more work
4
be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
4
than we did before, but we get to reuse more code. For a
5
This leads to waste in the PA space.
5
code path handling exceptional values, this is an improvement.
6
6
7
Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
allow users selectively disable them if needed. After that, the high
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
memory region for GICv3 or GICv4 redistributor can be disabled by user,
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
the number of maximal supported CPUs needs to be calculated based on
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
'vms->highmem_redists'. The follow-up error message is also improved
11
---
12
to indicate if the high memory region for GICv3 and GICv4 has been
12
fpu/softfloat.c | 43 +++++--------------------------------------
13
enabled or not.
13
1 file changed, 5 insertions(+), 38 deletions(-)
14
14
15
Suggested-by: Marc Zyngier <maz@kernel.org>
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Marc Zyngier <maz@kernel.org>
18
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
19
Reviewed-by: Eric Auger <eric.auger@redhat.com>
20
Message-id: 20221029224307.138822-8-gshan@redhat.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
docs/system/arm/virt.rst | 13 +++++++
24
hw/arm/virt.c | 75 ++++++++++++++++++++++++++++++++++++++--
25
2 files changed, 86 insertions(+), 2 deletions(-)
26
27
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
28
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
29
--- a/docs/system/arm/virt.rst
17
--- a/fpu/softfloat.c
30
+++ b/docs/system/arm/virt.rst
18
+++ b/fpu/softfloat.c
31
@@ -XXX,XX +XXX,XX @@ compact-highmem
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
32
Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
20
33
The default is ``on`` for machine types later than ``virt-7.2``.
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
34
22
{
35
+highmem-redists
23
- bool aIsLargerSignificand;
36
+ Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
24
- FloatClass a_cls, b_cls;
37
+ GICv4 redistributor. The default is ``on``. Setting this to ``off`` will
25
+ FloatParts128 pa, pb, *pr;
38
+ limit the maximum number of CPUs when GICv3 or GICv4 is used.
26
39
+
27
- /* This is not complete, but is good enough for pickNaN. */
40
+highmem-ecam
28
- a_cls = (!floatx80_is_any_nan(a)
41
+ Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
29
- ? float_class_normal
42
+ The default is ``on`` for machine types later than ``virt-3.0``.
30
- : floatx80_is_signaling_nan(a, status)
43
+
31
- ? float_class_snan
44
+highmem-mmio
32
- : float_class_qnan);
45
+ Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
33
- b_cls = (!floatx80_is_any_nan(b)
46
+ The default is ``on``.
34
- ? float_class_normal
47
+
35
- : floatx80_is_signaling_nan(b, status)
48
gic-version
36
- ? float_class_snan
49
Specify the version of the Generic Interrupt Controller (GIC) to provide.
37
- : float_class_qnan);
50
Valid values are:
38
-
51
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
52
index XXXXXXX..XXXXXXX 100644
40
- float_raise(float_flag_invalid, status);
53
--- a/hw/arm/virt.c
41
- }
54
+++ b/hw/arm/virt.c
42
-
55
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
43
- if (status->default_nan_mode) {
56
if (vms->gic_version == VIRT_GIC_VERSION_2) {
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
57
virt_max_cpus = GIC_NCPU;
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
58
} else {
46
return floatx80_default_nan(status);
59
- virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
60
- virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
61
+ virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
62
+ if (vms->highmem_redists) {
63
+ virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
64
+ }
65
}
47
}
66
48
67
if (max_cpus > virt_max_cpus) {
49
- if (a.low < b.low) {
68
error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
50
- aIsLargerSignificand = 0;
69
"supported by machine 'mach-virt' (%d)",
51
- } else if (b.low < a.low) {
70
max_cpus, virt_max_cpus);
52
- aIsLargerSignificand = 1;
71
+ if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
53
- } else {
72
+ error_printf("Try 'highmem-redists=on' for more CPUs\n");
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
73
+ }
55
- }
74
+
56
-
75
exit(1);
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
76
}
58
- if (is_snan(b_cls)) {
77
59
- return floatx80_silence_nan(b, status);
78
@@ -XXX,XX +XXX,XX @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
60
- }
79
vms->highmem_compact = value;
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
67
- }
68
+ pr = parts_pick_nan(&pa, &pb, status);
69
+ return floatx80_round_pack_canonical(pr, status);
80
}
70
}
81
71
82
+static bool virt_get_highmem_redists(Object *obj, Error **errp)
72
/*----------------------------------------------------------------------------
83
+{
84
+ VirtMachineState *vms = VIRT_MACHINE(obj);
85
+
86
+ return vms->highmem_redists;
87
+}
88
+
89
+static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
90
+{
91
+ VirtMachineState *vms = VIRT_MACHINE(obj);
92
+
93
+ vms->highmem_redists = value;
94
+}
95
+
96
+static bool virt_get_highmem_ecam(Object *obj, Error **errp)
97
+{
98
+ VirtMachineState *vms = VIRT_MACHINE(obj);
99
+
100
+ return vms->highmem_ecam;
101
+}
102
+
103
+static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
104
+{
105
+ VirtMachineState *vms = VIRT_MACHINE(obj);
106
+
107
+ vms->highmem_ecam = value;
108
+}
109
+
110
+static bool virt_get_highmem_mmio(Object *obj, Error **errp)
111
+{
112
+ VirtMachineState *vms = VIRT_MACHINE(obj);
113
+
114
+ return vms->highmem_mmio;
115
+}
116
+
117
+static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
118
+{
119
+ VirtMachineState *vms = VIRT_MACHINE(obj);
120
+
121
+ vms->highmem_mmio = value;
122
+}
123
+
124
+
125
static bool virt_get_its(Object *obj, Error **errp)
126
{
127
VirtMachineState *vms = VIRT_MACHINE(obj);
128
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
129
"Set on/off to enable/disable compact "
130
"layout for high memory regions");
131
132
+ object_class_property_add_bool(oc, "highmem-redists",
133
+ virt_get_highmem_redists,
134
+ virt_set_highmem_redists);
135
+ object_class_property_set_description(oc, "highmem-redists",
136
+ "Set on/off to enable/disable high "
137
+ "memory region for GICv3 or GICv4 "
138
+ "redistributor");
139
+
140
+ object_class_property_add_bool(oc, "highmem-ecam",
141
+ virt_get_highmem_ecam,
142
+ virt_set_highmem_ecam);
143
+ object_class_property_set_description(oc, "highmem-ecam",
144
+ "Set on/off to enable/disable high "
145
+ "memory region for PCI ECAM");
146
+
147
+ object_class_property_add_bool(oc, "highmem-mmio",
148
+ virt_get_highmem_mmio,
149
+ virt_set_highmem_mmio);
150
+ object_class_property_set_description(oc, "highmem-mmio",
151
+ "Set on/off to enable/disable high "
152
+ "memory region for PCI MMIO");
153
+
154
object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
155
virt_set_gic_version);
156
object_class_property_set_description(oc, "gic-version",
157
--
73
--
158
2.25.1
74
2.34.1
diff view generated by jsdifflib
[PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
[PULL 67/72] softfloat: Inline pickNaN
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This introduces variable 'region_base' for the base address of the
3
Inline pickNaN into its only caller. This makes one assert
4
specific high memory region. It's the preparatory work to optimize
4
redundant with the immediately preceding IF.
5
high memory region address assignment.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
No functional change intended.
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
9
Signed-off-by: Gavin Shan <gshan@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
Reviewed-by: Marc Zyngier <maz@kernel.org>
13
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
14
Message-id: 20221029224307.138822-4-gshan@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
hw/arm/virt.c | 12 ++++++------
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
18
1 file changed, 6 insertions(+), 6 deletions(-)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
19
13
2 files changed, 73 insertions(+), 105 deletions(-)
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt.c
17
--- a/fpu/softfloat-parts.c.inc
23
+++ b/hw/arm/virt.c
18
+++ b/fpu/softfloat-parts.c.inc
24
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
25
static void virt_set_high_memmap(VirtMachineState *vms,
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
26
hwaddr base, int pa_bits)
21
float_status *s)
27
{
22
{
28
- hwaddr region_size;
23
+ int cmp, which;
29
+ hwaddr region_base, region_size;
24
+
30
bool fits;
25
if (is_snan(a->cls) || is_snan(b->cls)) {
31
int i;
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
32
27
}
33
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
28
34
+ region_base = ROUND_UP(base, extended_memmap[i].size);
29
if (s->default_nan_mode) {
35
region_size = extended_memmap[i].size;
30
parts_default_nan(a, s);
36
31
- } else {
37
- base = ROUND_UP(base, region_size);
32
- int cmp = frac_cmp(a, b);
38
- vms->memmap[i].base = base;
33
- if (cmp == 0) {
39
+ vms->memmap[i].base = region_base;
34
- cmp = a->sign < b->sign;
40
vms->memmap[i].size = region_size;
35
- }
41
36
+ return a;
42
/*
37
+ }
43
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
38
44
*
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
45
* For each device that doesn't fit, disable it.
40
- a = b;
46
*/
41
- }
47
- fits = (base + region_size) <= BIT_ULL(pa_bits);
42
+ cmp = frac_cmp(a, b);
48
+ fits = (region_base + region_size) <= BIT_ULL(pa_bits);
43
+ if (cmp == 0) {
49
if (fits) {
44
+ cmp = a->sign < b->sign;
50
- vms->highest_gpa = base + region_size - 1;
45
+ }
51
+ vms->highest_gpa = region_base + region_size - 1;
46
+
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
52
}
58
}
53
59
+ break;
54
switch (i) {
60
+ case float_2nan_prop_s_ba:
55
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
61
+ if (is_snan(b->cls)) {
56
break;
62
+ which = 1;
57
}
63
+ } else if (is_snan(a->cls)) {
58
64
+ which = 0;
59
- base += region_size;
65
+ } else if (is_qnan(b->cls)) {
60
+ base = region_base + region_size;
66
+ which = 1;
67
+ } else {
68
+ which = 0;
69
+ }
70
+ break;
71
+ case float_2nan_prop_ab:
72
+ which = is_nan(a->cls) ? 0 : 1;
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
103
+ }
104
+ break;
105
+ default:
106
+ g_assert_not_reached();
107
+ }
108
+
109
+ if (which) {
110
+ a = b;
111
+ }
112
+ if (is_snan(a->cls)) {
113
+ parts_silence_nan(a, s);
114
}
115
return a;
116
}
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
118
index XXXXXXX..XXXXXXX 100644
119
--- a/fpu/softfloat-specialize.c.inc
120
+++ b/fpu/softfloat-specialize.c.inc
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
61
}
122
}
62
}
123
}
63
124
125
-/*----------------------------------------------------------------------------
126
-| Select which NaN to propagate for a two-input operation.
127
-| IEEE754 doesn't specify all the details of this, so the
128
-| algorithm is target-specific.
129
-| The routine is passed various bits of information about the
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
144
-{
145
- /*
146
- * We guarantee not to require the target to tell us how to
147
- * pick a NaN if we're always returning the default NaN.
148
- * But if we're not in default-NaN mode then the target must
149
- * specify via set_float_2nan_prop_rule().
150
- */
151
- assert(!status->default_nan_mode);
152
-
153
- switch (status->float_2nan_prop_rule) {
154
- case float_2nan_prop_s_ab:
155
- if (is_snan(a_cls)) {
156
- return 0;
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
64
--
224
--
65
2.25.1
225
2.34.1
226
227
diff view generated by jsdifflib
[PULL 06/29] hw/arm/virt: Add 'compact-highmem' property
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
After the improvement to high memory region address assignment is
3
Remember if there was an SNaN, and use that to simplify
4
applied, the memory layout can be changed, introducing possible
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
5
Then, fall through to the corresponding
6
is disabled or enabled when the optimization is applied or not, with
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
the following configuration. The configuration is only achievable by
7
nans, which must be quiet.
8
modifying the source code until more properties are added to allow
9
users selectively disable those high memory regions.
10
8
11
pa_bits = 40;
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
vms->highmem_redists = false;
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
vms->highmem_ecam = false;
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
14
vms->highmem_mmio = true;
15
16
# qemu-system-aarch64 -accel kvm -cpu host \
17
-machine virt-7.2,compact-highmem={on, off} \
18
-m 4G,maxmem=511G -monitor stdio
19
20
Region compact-highmem=off compact-highmem=on
21
----------------------------------------------------------------
22
MEM [1GB 512GB] [1GB 512GB]
23
HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled]
24
HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled]
25
HIGH_PCIE_MMIO [disabled] [512GB 1TB]
26
27
In order to keep backwords compatibility, we need to disable the
28
optimization on machine, which is virt-7.1 or ealier than it. It
29
means the optimization is enabled by default from virt-7.2. Besides,
30
'compact-highmem' property is added so that the optimization can be
31
explicitly enabled or disabled on all machine types by users.
32
33
Signed-off-by: Gavin Shan <gshan@redhat.com>
34
Reviewed-by: Eric Auger <eric.auger@redhat.com>
35
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
36
Reviewed-by: Marc Zyngier <maz@kernel.org>
37
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
38
Message-id: 20221029224307.138822-7-gshan@redhat.com
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
---
13
---
41
docs/system/arm/virt.rst | 4 ++++
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
42
include/hw/arm/virt.h | 1 +
15
1 file changed, 12 insertions(+), 20 deletions(-)
43
hw/arm/virt.c | 32 ++++++++++++++++++++++++++++++++
44
3 files changed, 37 insertions(+)
45
16
46
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
47
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
48
--- a/docs/system/arm/virt.rst
19
--- a/fpu/softfloat-parts.c.inc
49
+++ b/docs/system/arm/virt.rst
20
+++ b/fpu/softfloat-parts.c.inc
50
@@ -XXX,XX +XXX,XX @@ highmem
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
51
address space above 32 bits. The default is ``on`` for machine types
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
52
later than ``virt-2.12``.
23
float_status *s)
53
54
+compact-highmem
55
+ Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
56
+ The default is ``on`` for machine types later than ``virt-7.2``.
57
+
58
gic-version
59
Specify the version of the Generic Interrupt Controller (GIC) to provide.
60
Valid values are:
61
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/hw/arm/virt.h
64
+++ b/include/hw/arm/virt.h
65
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
66
bool no_pmu;
67
bool claim_edge_triggered_timers;
68
bool smbios_old_sys_ver;
69
+ bool no_highmem_compact;
70
bool no_highmem_ecam;
71
bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
72
bool kvm_no_adjvtime;
73
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/arm/virt.c
76
+++ b/hw/arm/virt.c
77
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
78
* Note the extended_memmap is sized so that it eventually also includes the
79
* base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
80
* index of base_memmap).
81
+ *
82
+ * The memory map for these Highmem IO Regions can be in legacy or compact
83
+ * layout, depending on 'compact-highmem' property. With legacy layout, the
84
+ * PA space for one specific region is always reserved, even if the region
85
+ * has been disabled or doesn't fit into the PA space. However, the PA space
86
+ * for the region won't be reserved in these circumstances with compact layout.
87
*/
88
static MemMapEntry extended_memmap[] = {
89
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
90
@@ -XXX,XX +XXX,XX @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
91
vms->highmem = value;
92
}
93
94
+static bool virt_get_compact_highmem(Object *obj, Error **errp)
95
+{
96
+ VirtMachineState *vms = VIRT_MACHINE(obj);
97
+
98
+ return vms->highmem_compact;
99
+}
100
+
101
+static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
102
+{
103
+ VirtMachineState *vms = VIRT_MACHINE(obj);
104
+
105
+ vms->highmem_compact = value;
106
+}
107
+
108
static bool virt_get_its(Object *obj, Error **errp)
109
{
24
{
110
VirtMachineState *vms = VIRT_MACHINE(obj);
25
+ bool have_snan = false;
111
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
26
int cmp, which;
112
"Set on/off to enable/disable using "
27
113
"physical address space above 32 bits");
28
if (is_snan(a->cls) || is_snan(b->cls)) {
114
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
115
+ object_class_property_add_bool(oc, "compact-highmem",
30
+ have_snan = true;
116
+ virt_get_compact_highmem,
31
}
117
+ virt_set_compact_highmem);
32
118
+ object_class_property_set_description(oc, "compact-highmem",
33
if (s->default_nan_mode) {
119
+ "Set on/off to enable/disable compact "
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
120
+ "layout for high memory regions");
35
121
+
36
switch (s->float_2nan_prop_rule) {
122
object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
37
case float_2nan_prop_s_ab:
123
virt_set_gic_version);
38
- if (is_snan(a->cls)) {
124
object_class_property_set_description(oc, "gic-version",
39
- which = 0;
125
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
40
- } else if (is_snan(b->cls)) {
126
41
- which = 1;
127
/* High memory is enabled by default */
42
- } else if (is_qnan(a->cls)) {
128
vms->highmem = true;
43
- which = 0;
129
+ vms->highmem_compact = !vmc->no_highmem_compact;
44
- } else {
130
vms->gic_version = VIRT_GIC_VERSION_NOSEL;
45
- which = 1;
131
46
+ if (have_snan) {
132
vms->highmem_ecam = !vmc->no_highmem_ecam;
47
+ which = is_snan(a->cls) ? 0 : 1;
133
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
48
+ break;
134
49
}
135
static void virt_machine_7_1_options(MachineClass *mc)
50
- break;
136
{
51
- case float_2nan_prop_s_ba:
137
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
52
- if (is_snan(b->cls)) {
138
+
53
- which = 1;
139
virt_machine_7_2_options(mc);
54
- } else if (is_snan(a->cls)) {
140
compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
55
- which = 0;
141
+ /* Compact layout for high memory regions was introduced with 7.2 */
56
- } else if (is_qnan(b->cls)) {
142
+ vmc->no_highmem_compact = true;
57
- which = 1;
143
}
58
- } else {
144
DEFINE_VIRT_MACHINE(7, 1)
59
- which = 0;
145
60
- }
61
- break;
62
+ /* fall through */
63
case float_2nan_prop_ab:
64
which = is_nan(a->cls) ? 0 : 1;
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
146
--
75
--
147
2.25.1
76
2.34.1
diff view generated by jsdifflib
[PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Schspa Shi <schspa@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We use 32bit value for linux,initrd-[start/end], when we have
3
Move the fractional comparison to the end of the
4
loader_start > 4GB, there will be a wrong initrd_start passed
4
float_2nan_prop_x87 case. This is not required for
5
to the kernel, and the kernel will report the following warning.
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
6
8
7
[ 0.000000] ------------[ cut here ]------------
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
[ 0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ...
9
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244
10
[ 0.000000] Modules linked in:
11
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 6.1.0-rc3-13250-g30a0b95b1335-dirty #28
12
[ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT)
13
[ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
14
[ 0.000000] pc : arm64_memblock_init+0x158/0x244
15
[ 0.000000] lr : arm64_memblock_init+0x158/0x244
16
[ 0.000000] sp : ffff800009273df0
17
[ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000
18
[ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000
19
[ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000
20
[ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020
21
[ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261
22
[ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000
23
[ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000
24
[ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69
25
[ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88
26
[ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056
27
[ 0.000000] Call trace:
28
[ 0.000000] arm64_memblock_init+0x158/0x244
29
[ 0.000000] setup_arch+0x164/0x1cc
30
[ 0.000000] start_kernel+0x94/0x4ac
31
[ 0.000000] __primary_switched+0xb4/0xbc
32
[ 0.000000] ---[ end trace 0000000000000000 ]---
33
[ 0.000000] Zone ranges:
34
[ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff]
35
36
This doesn't affect any machine types we currently support, because
37
for all of our machine types the RAM starts well below the 4GB
38
mark, but it does demonstrate that we're not currently writing
39
the device-tree properties quite as intended.
40
41
To fix it, we can change it to write these values to the dtb using a
42
type width matching #address-cells. This is the intended size for
43
these dtb properties, and is how u-boot, for instance, writes them,
44
although in practice the Linux kernel will cope with them being any
45
width as long as they're big enough to fit the value.
46
47
Signed-off-by: Schspa Shi <schspa@gmail.com>
48
Message-id: 20221129160724.75667-1-schspa@gmail.com
49
[PMM: tweaked commit message]
50
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
52
---
13
---
53
hw/arm/boot.c | 10 ++++++----
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
54
1 file changed, 6 insertions(+), 4 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
55
16
56
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
57
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/arm/boot.c
19
--- a/fpu/softfloat-parts.c.inc
59
+++ b/hw/arm/boot.c
20
+++ b/fpu/softfloat-parts.c.inc
60
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
22
return a;
61
}
23
}
62
24
63
if (binfo->initrd_size) {
25
- cmp = frac_cmp(a, b);
64
- rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
26
- if (cmp == 0) {
65
- binfo->initrd_start);
27
- cmp = a->sign < b->sign;
66
+ rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
28
- }
67
+ acells, binfo->initrd_start);
29
-
68
if (rc < 0) {
30
switch (s->float_2nan_prop_rule) {
69
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
31
case float_2nan_prop_s_ab:
70
goto fail;
32
if (have_snan) {
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
34
* return the NaN with the positive sign bit (if any).
35
*/
36
if (is_snan(a->cls)) {
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
53
+ break;
71
}
54
}
72
55
+ cmp = frac_cmp(a, b);
73
- rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
56
+ if (cmp == 0) {
74
- binfo->initrd_start + binfo->initrd_size);
57
+ cmp = a->sign < b->sign;
75
+ rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
58
+ }
76
+ acells,
59
+ which = cmp > 0 ? 0 : 1;
77
+ binfo->initrd_start +
60
break;
78
+ binfo->initrd_size);
61
default:
79
if (rc < 0) {
62
g_assert_not_reached();
80
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
81
goto fail;
82
--
63
--
83
2.25.1
64
2.34.1
diff view generated by jsdifflib
[PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Gavin Shan <gshan@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
3
Replace the "index" selecting between A and B with a result variable
4
Its counterpart ('region_base') will be introduced in next patch.
4
of the proper type. This improves clarity within the function.
5
5
6
No functional change intended.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Gavin Shan <gshan@redhat.com>
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
11
Reviewed-by: Marc Zyngier <maz@kernel.org>
12
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
13
Message-id: 20221029224307.138822-3-gshan@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
hw/arm/virt.c | 15 ++++++++-------
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
17
1 file changed, 8 insertions(+), 7 deletions(-)
12
1 file changed, 13 insertions(+), 15 deletions(-)
18
13
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
16
--- a/fpu/softfloat-parts.c.inc
22
+++ b/hw/arm/virt.c
17
+++ b/fpu/softfloat-parts.c.inc
23
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
24
static void virt_set_high_memmap(VirtMachineState *vms,
19
float_status *s)
25
hwaddr base, int pa_bits)
26
{
20
{
27
+ hwaddr region_size;
21
bool have_snan = false;
28
+ bool fits;
22
- int cmp, which;
29
int i;
23
+ FloatPartsN *ret;
30
24
+ int cmp;
31
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
25
32
- hwaddr size = extended_memmap[i].size;
26
if (is_snan(a->cls) || is_snan(b->cls)) {
33
- bool fits;
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
34
+ region_size = extended_memmap[i].size;
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
35
29
switch (s->float_2nan_prop_rule) {
36
- base = ROUND_UP(base, size);
30
case float_2nan_prop_s_ab:
37
+ base = ROUND_UP(base, region_size);
31
if (have_snan) {
38
vms->memmap[i].base = base;
32
- which = is_snan(a->cls) ? 0 : 1;
39
- vms->memmap[i].size = size;
33
+ ret = is_snan(a->cls) ? a : b;
40
+ vms->memmap[i].size = region_size;
41
42
/*
43
* Check each device to see if they fit in the PA space,
44
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
45
*
46
* For each device that doesn't fit, disable it.
47
*/
48
- fits = (base + size) <= BIT_ULL(pa_bits);
49
+ fits = (base + region_size) <= BIT_ULL(pa_bits);
50
if (fits) {
51
- vms->highest_gpa = base + size - 1;
52
+ vms->highest_gpa = base + region_size - 1;
53
}
54
55
switch (i) {
56
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
57
break;
34
break;
58
}
35
}
59
36
/* fall through */
60
- base += size;
37
case float_2nan_prop_ab:
61
+ base += region_size;
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
68
} else {
69
- which = 1;
70
+ ret = b;
71
break;
72
}
73
cmp = frac_cmp(a, b);
74
if (cmp == 0) {
75
cmp = a->sign < b->sign;
76
}
77
- which = cmp > 0 ? 0 : 1;
78
+ ret = cmp > 0 ? a : b;
79
break;
80
default:
81
g_assert_not_reached();
62
}
82
}
83
84
- if (which) {
85
- a = b;
86
+ if (is_snan(ret->cls)) {
87
+ parts_silence_nan(ret, s);
88
}
89
- if (is_snan(a->cls)) {
90
- parts_silence_nan(a, s);
91
- }
92
- return a;
93
+ return ret;
63
}
94
}
64
95
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
65
--
97
--
66
2.25.1
98
2.34.1
99
100
diff view generated by jsdifflib
[PULL 27/29] target/arm: align exposed ID registers with Linux
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Zhuojia Shen <chaosdefinition@hotmail.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
In CPUID registers exposed to userspace, some registers were missing
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
and some fields were not exposed. This patch aligns exposed ID
4
update my email address, and update the mailmap to match.
5
registers and their fields with what the upstream kernel currently
6
exposes.
7
5
8
Specifically, the following new ID registers/fields are exposed to
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
9
userspace:
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
10
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
11
ID_AA64PFR1_EL1.BT: bits 3-0
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
ID_AA64PFR1_EL1.MTE: bits 11-8
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
ID_AA64PFR1_EL1.SME: bits 27-24
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
14
15
ID_AA64ZFR0_EL1.SVEver: bits 3-0
16
ID_AA64ZFR0_EL1.AES: bits 7-4
17
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
18
ID_AA64ZFR0_EL1.BF16: bits 23-20
19
ID_AA64ZFR0_EL1.SHA3: bits 35-32
20
ID_AA64ZFR0_EL1.SM4: bits 43-40
21
ID_AA64ZFR0_EL1.I8MM: bits 47-44
22
ID_AA64ZFR0_EL1.F32MM: bits 55-52
23
ID_AA64ZFR0_EL1.F64MM: bits 59-56
24
25
ID_AA64SMFR0_EL1.F32F32: bit 32
26
ID_AA64SMFR0_EL1.B16F32: bit 34
27
ID_AA64SMFR0_EL1.F16F32: bit 35
28
ID_AA64SMFR0_EL1.I8I32: bits 39-36
29
ID_AA64SMFR0_EL1.F64F64: bit 48
30
ID_AA64SMFR0_EL1.I16I64: bits 55-52
31
ID_AA64SMFR0_EL1.FA64: bit 63
32
33
ID_AA64MMFR0_EL1.ECV: bits 63-60
34
35
ID_AA64MMFR1_EL1.AFP: bits 47-44
36
37
ID_AA64MMFR2_EL1.AT: bits 35-32
38
39
ID_AA64ISAR0_EL1.RNDR: bits 63-60
40
41
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
42
ID_AA64ISAR1_EL1.BF16: bits 47-44
43
ID_AA64ISAR1_EL1.DGH: bits 51-48
44
ID_AA64ISAR1_EL1.I8MM: bits 55-52
45
46
ID_AA64ISAR2_EL1.WFxT: bits 3-0
47
ID_AA64ISAR2_EL1.RPRES: bits 7-4
48
ID_AA64ISAR2_EL1.GPA3: bits 11-8
49
ID_AA64ISAR2_EL1.APA3: bits 15-12
50
51
The code is also refactored to use symbolic names for ID register fields
52
for better readability and maintainability.
53
54
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
55
Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com
56
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
58
---
13
---
59
target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++--------
14
MAINTAINERS | 2 +-
60
1 file changed, 79 insertions(+), 17 deletions(-)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
61
17
62
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
63
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/helper.c
20
--- a/MAINTAINERS
65
+++ b/target/arm/helper.c
21
+++ b/MAINTAINERS
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
67
#ifdef CONFIG_USER_ONLY
23
SBSA-REF
68
static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
24
M: Radoslaw Biernacki <rad@semihalf.com>
69
{ .name = "ID_AA64PFR0_EL1",
25
M: Peter Maydell <peter.maydell@linaro.org>
70
- .exported_bits = 0x000f000f00ff0000,
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
71
- .fixed_bits = 0x0000000000000011 },
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
72
+ .exported_bits = R_ID_AA64PFR0_FP_MASK |
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
73
+ R_ID_AA64PFR0_ADVSIMD_MASK |
29
L: qemu-arm@nongnu.org
74
+ R_ID_AA64PFR0_SVE_MASK |
30
S: Maintained
75
+ R_ID_AA64PFR0_DIT_MASK,
31
diff --git a/.mailmap b/.mailmap
76
+ .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) |
32
index XXXXXXX..XXXXXXX 100644
77
+ (0x1 << R_ID_AA64PFR0_EL1_SHIFT) },
33
--- a/.mailmap
78
{ .name = "ID_AA64PFR1_EL1",
34
+++ b/.mailmap
79
- .exported_bits = 0x00000000000000f0 },
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
80
+ .exported_bits = R_ID_AA64PFR1_BT_MASK |
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
81
+ R_ID_AA64PFR1_SSBS_MASK |
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
82
+ R_ID_AA64PFR1_MTE_MASK |
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
83
+ R_ID_AA64PFR1_SME_MASK },
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
84
{ .name = "ID_AA64PFR*_EL1_RESERVED",
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
85
- .is_glob = true },
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
86
- { .name = "ID_AA64ZFR0_EL1" },
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
87
+ .is_glob = true },
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
88
+ { .name = "ID_AA64ZFR0_EL1",
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
89
+ .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
90
+ R_ID_AA64ZFR0_AES_MASK |
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
91
+ R_ID_AA64ZFR0_BITPERM_MASK |
92
+ R_ID_AA64ZFR0_BFLOAT16_MASK |
93
+ R_ID_AA64ZFR0_SHA3_MASK |
94
+ R_ID_AA64ZFR0_SM4_MASK |
95
+ R_ID_AA64ZFR0_I8MM_MASK |
96
+ R_ID_AA64ZFR0_F32MM_MASK |
97
+ R_ID_AA64ZFR0_F64MM_MASK },
98
+ { .name = "ID_AA64SMFR0_EL1",
99
+ .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
100
+ R_ID_AA64SMFR0_B16F32_MASK |
101
+ R_ID_AA64SMFR0_F16F32_MASK |
102
+ R_ID_AA64SMFR0_I8I32_MASK |
103
+ R_ID_AA64SMFR0_F64F64_MASK |
104
+ R_ID_AA64SMFR0_I16I64_MASK |
105
+ R_ID_AA64SMFR0_FA64_MASK },
106
{ .name = "ID_AA64MMFR0_EL1",
107
- .fixed_bits = 0x00000000ff000000 },
108
- { .name = "ID_AA64MMFR1_EL1" },
109
+ .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
110
+ .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
111
+ (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
112
+ { .name = "ID_AA64MMFR1_EL1",
113
+ .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
114
+ { .name = "ID_AA64MMFR2_EL1",
115
+ .exported_bits = R_ID_AA64MMFR2_AT_MASK },
116
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
117
- .is_glob = true },
118
+ .is_glob = true },
119
{ .name = "ID_AA64DFR0_EL1",
120
- .fixed_bits = 0x0000000000000006 },
121
- { .name = "ID_AA64DFR1_EL1" },
122
+ .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
123
+ { .name = "ID_AA64DFR1_EL1" },
124
{ .name = "ID_AA64DFR*_EL1_RESERVED",
125
- .is_glob = true },
126
+ .is_glob = true },
127
{ .name = "ID_AA64AFR*",
128
- .is_glob = true },
129
+ .is_glob = true },
130
{ .name = "ID_AA64ISAR0_EL1",
131
- .exported_bits = 0x00fffffff0fffff0 },
132
+ .exported_bits = R_ID_AA64ISAR0_AES_MASK |
133
+ R_ID_AA64ISAR0_SHA1_MASK |
134
+ R_ID_AA64ISAR0_SHA2_MASK |
135
+ R_ID_AA64ISAR0_CRC32_MASK |
136
+ R_ID_AA64ISAR0_ATOMIC_MASK |
137
+ R_ID_AA64ISAR0_RDM_MASK |
138
+ R_ID_AA64ISAR0_SHA3_MASK |
139
+ R_ID_AA64ISAR0_SM3_MASK |
140
+ R_ID_AA64ISAR0_SM4_MASK |
141
+ R_ID_AA64ISAR0_DP_MASK |
142
+ R_ID_AA64ISAR0_FHM_MASK |
143
+ R_ID_AA64ISAR0_TS_MASK |
144
+ R_ID_AA64ISAR0_RNDR_MASK },
145
{ .name = "ID_AA64ISAR1_EL1",
146
- .exported_bits = 0x000000f0ffffffff },
147
+ .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
148
+ R_ID_AA64ISAR1_APA_MASK |
149
+ R_ID_AA64ISAR1_API_MASK |
150
+ R_ID_AA64ISAR1_JSCVT_MASK |
151
+ R_ID_AA64ISAR1_FCMA_MASK |
152
+ R_ID_AA64ISAR1_LRCPC_MASK |
153
+ R_ID_AA64ISAR1_GPA_MASK |
154
+ R_ID_AA64ISAR1_GPI_MASK |
155
+ R_ID_AA64ISAR1_FRINTTS_MASK |
156
+ R_ID_AA64ISAR1_SB_MASK |
157
+ R_ID_AA64ISAR1_BF16_MASK |
158
+ R_ID_AA64ISAR1_DGH_MASK |
159
+ R_ID_AA64ISAR1_I8MM_MASK },
160
+ { .name = "ID_AA64ISAR2_EL1",
161
+ .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
162
+ R_ID_AA64ISAR2_RPRES_MASK |
163
+ R_ID_AA64ISAR2_GPA3_MASK |
164
+ R_ID_AA64ISAR2_APA3_MASK },
165
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
166
- .is_glob = true },
167
+ .is_glob = true },
168
};
169
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
170
#endif
171
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
172
#ifdef CONFIG_USER_ONLY
173
static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
174
{ .name = "MIDR_EL1",
175
- .exported_bits = 0x00000000ffffffff },
176
- { .name = "REVIDR_EL1" },
177
+ .exported_bits = R_MIDR_EL1_REVISION_MASK |
178
+ R_MIDR_EL1_PARTNUM_MASK |
179
+ R_MIDR_EL1_ARCHITECTURE_MASK |
180
+ R_MIDR_EL1_VARIANT_MASK |
181
+ R_MIDR_EL1_IMPLEMENTER_MASK },
182
+ { .name = "REVIDR_EL1" },
183
};
184
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
185
#endif
186
--
47
--
187
2.25.1
48
2.34.1
49
50
diff view generated by jsdifflib
[PULL 08/29] hw/arm/virt: build SMBIOS 19 table
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Use the base_memmap to build the SMBIOS 19 table which provides the address
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
mapping for a Physical Memory Array (from spec [1] chapter 7.20).
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
5
6
This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
7
("SMBIOS: Build aggregate smbios tables and entry point").
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
9
[1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf
10
11
The absence of this table is a breach of the specs and is
12
detected by the FirmwareTestSuite (FWTS), but it doesn't
13
cause any known problems for guest OSes.
14
15
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
16
Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
10
---
20
hw/arm/virt.c | 8 +++++++-
11
MAINTAINERS | 2 ++
21
1 file changed, 7 insertions(+), 1 deletion(-)
12
1 file changed, 2 insertions(+)
22
13
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
diff --git a/MAINTAINERS b/MAINTAINERS
24
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
16
--- a/MAINTAINERS
26
+++ b/hw/arm/virt.c
17
+++ b/MAINTAINERS
27
@@ -XXX,XX +XXX,XX @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
28
static void virt_build_smbios(VirtMachineState *vms)
19
29
{
20
Xilinx CAN
30
MachineClass *mc = MACHINE_GET_CLASS(vms);
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
31
+ MachineState *ms = MACHINE(vms);
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
32
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
23
S: Maintained
33
uint8_t *smbios_tables, *smbios_anchor;
24
F: hw/net/can/xlnx-*
34
size_t smbios_tables_len, smbios_anchor_len;
25
F: include/hw/net/xlnx-*
35
+ struct smbios_phys_mem_area mem_array;
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
36
const char *product = "QEMU Virtual Machine";
27
CAN bus subsystem and hardware
37
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
38
if (kvm_enabled()) {
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
39
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(VirtMachineState *vms)
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
40
vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
31
S: Maintained
41
true, SMBIOS_ENTRY_POINT_TYPE_64);
32
W: https://canbus.pages.fel.cvut.cz/
42
33
F: net/can/*
43
- smbios_get_tables(MACHINE(vms), NULL, 0,
44
+ /* build the array of physical mem area from base_memmap */
45
+ mem_array.address = vms->memmap[VIRT_MEM].base;
46
+ mem_array.length = ms->ram_size;
47
+
48
+ smbios_get_tables(ms, &mem_array, 1,
49
&smbios_tables, &smbios_tables_len,
50
&smbios_anchor, &smbios_anchor_len,
51
&error_fatal);
52
--
34
--
53
2.25.1
35
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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