Series comparison

-[PULL 00/29] target-arm queue
+[PULL 00/35] target-arm queue
-First arm pullreq of the 8.0 series...
+The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:
-The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
+  Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)
   Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215
-for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af:
+for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:
-  target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +0000)
+  docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/arm/virt: Add properties to allow more granular
+ * hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
-   configuration of use of highmem space
+ * linux-user/aarch64: Choose SYNC as the preferred MTE mode
- * target/arm: Add Cortex-A55 CPU
+ * Fix some errors in SVE/SME handling of MTE tags
- * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
+ * hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
- * Implement FEAT_EVT
+ * hw/block/tc58128: Don't emit deprecation warning under qtest
- * Some 3-phase-reset conversions for Arm GIC, SMMU
+ * tests/qtest: Fix handling of npcm7xx and GMAC tests
- * hw/arm/boot: set initrd with #address-cells type in fdt
+ * hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
- * align user-mode exposed ID registers with Linux
+ * tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
- * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
+ * Don't assert on vmload/vmsave of M-profile CPUs
- * Restrict arm_cpu_exec_interrupt() to TCG accelerator
+ * hw/arm/smmuv3: add support for stage 1 access fault
  * hw/arm/stellaris: QOM cleanups
  * Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
  * Improve Cortex_R52 IMPDEF sysreg modelling
  * Allow access to SPSR_hyp from hyp mode
  * New board model mps3-an536 (Cortex-R52)
 ----------------------------------------------------------------
-Gavin Shan (7):
+Luc Michel (1):
-      hw/arm/virt: Introduce virt_set_high_memmap() helper
+      hw/arm/smmuv3: add support for stage 1 access fault
       hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
       hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
       hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
       hw/arm/virt: Improve high memory region address assignment
       hw/arm/virt: Add 'compact-highmem' property
       hw/arm/virt: Add properties to disable high memory regions
-Luke Starrett (1):
+Nabih Estefan (1):
-      hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
+      tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
-Mihai Carabas (1):
+Peter Maydell (22):
-      hw/arm/virt: build SMBIOS 19 table
+      hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
       hw/block/tc58128: Don't emit deprecation warning under qtest
       tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
       tests/qtest/bios-tables-test: Allow changes to virt GTDT
       hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
       tests/qtest/bios-tables-tests: Update virt golden reference
       hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
       tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
       target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
       target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
       target/arm: The Cortex-R52 has a read-only CBAR
       target/arm: Add Cortex-R52 IMPDEF sysregs
       target/arm: Allow access to SPSR_hyp from hyp mode
       hw/misc/mps2-scc: Fix condition for CFG3 register
       hw/misc/mps2-scc: Factor out which-board conditionals
       hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
       hw/arm/mps3r: Initial skeleton for mps3-an536 board
       hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
       hw/arm/mps3r: Add UARTs
       hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
       hw/arm/mps3r: Add remaining devices
       docs: Add documentation for the mps3-an536 board
-Peter Maydell (15):
+Philippe Mathieu-Daudé (5):
-      target/arm: Allow relevant HCR bits to be written for FEAT_EVT
+      hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
-      target/arm: Implement HCR_EL2.TTLBIS traps
+      hw/arm/stellaris: Convert ADC controller to Resettable interface
-      target/arm: Implement HCR_EL2.TTLBOS traps
+      hw/arm/stellaris: Convert I2C controller to Resettable interface
-      target/arm: Implement HCR_EL2.TICAB,TOCU traps
+      hw/arm/stellaris: Add missing QOM 'machine' parent
-      target/arm: Implement HCR_EL2.TID4 traps
+      hw/arm/stellaris: Add missing QOM 'SoC' parent
       target/arm: Report FEAT_EVT for TCG '-cpu max'
       hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
       hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
       hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
       hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
       hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
       hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
       hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
       hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
       hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
-Philippe Mathieu-Daudé (1):
+Richard Henderson (6):
-      target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
+      linux-user/aarch64: Choose SYNC as the preferred MTE mode
       target/arm: Fix nregs computation in do_{ld,st}_zpa
       target/arm: Adjust and validate mtedesc sizem1
       target/arm: Split out make_svemte_desc
       target/arm: Handle mte in do_ldrq, do_ldro
       target/arm: Fix SVE/SME gross MTE suppression checks
-Schspa Shi (1):
+ MAINTAINERS                             |   3 +-
-      hw/arm/boot: set initrd with #address-cells type in fdt
+ docs/system/arm/mps2.rst                |  37 +-
  configs/devices/arm-softmmu/default.mak |   1 +
  hw/arm/smmuv3-internal.h                |   1 +
  include/hw/arm/smmu-common.h            |   1 +
  include/hw/arm/virt.h                   |   2 +
  include/hw/misc/mps2-scc.h              |   1 +
  linux-user/aarch64/target_prctl.h       |  29 +-
  target/arm/internals.h                  |   2 +-
  target/arm/tcg/translate-a64.h          |   2 +
  hw/arm/mps3r.c                          | 640 ++++++++++++++++++++++++++++++++
  hw/arm/npcm7xx.c                        |   1 +
  hw/arm/smmu-common.c                    |  11 +
  hw/arm/smmuv3.c                         |   1 +
  hw/arm/stellaris.c                      |  47 ++-
  hw/arm/virt-acpi-build.c                |  20 +-
  hw/arm/virt.c                           |  60 ++-
  hw/arm/xilinx_zynq.c                    |   2 +
  hw/block/tc58128.c                      |   4 +-
  hw/misc/mps2-scc.c                      | 138 ++++++-
  hw/pci-host/raven.c                     |   1 +
  target/arm/helper.c                     |  14 +-
  target/arm/tcg/cpu32.c                  | 109 ++++++
  target/arm/tcg/op_helper.c              |  43 ++-
  target/arm/tcg/sme_helper.c             |   8 +-
  target/arm/tcg/sve_helper.c             |  12 +-
  target/arm/tcg/translate-sme.c          |  15 +-
  target/arm/tcg/translate-sve.c          |  83 +++--
  target/arm/tcg/translate.c              |  19 +-
  tests/qtest/npcm7xx_emc-test.c          |   5 +-
  tests/qtest/npcm_gmac-test.c            |  84 +----
  hw/arm/Kconfig                          |   5 +
  hw/arm/meson.build                      |   1 +
  tests/data/acpi/virt/FACP               | Bin 276 -> 276 bytes
  tests/data/acpi/virt/GTDT               | Bin 96 -> 104 bytes
  tests/qtest/meson.build                 |   4 +-
 files changed, 1184 insertions(+), 222 deletions(-)
  create mode 100644 hw/arm/mps3r.c
-Thomas Huth (1):
-      hw/misc: Move some arm-related files from specific_ss into softmmu_ss
-Timofey Kutergin (1):
-      target/arm: Add Cortex-A55 CPU
-Zhuojia Shen (1):
-      target/arm: align exposed ID registers with Linux
- docs/system/arm/emulation.rst          |   1 +
- docs/system/arm/virt.rst               |  18 +++
- include/hw/arm/smmuv3.h                |   2 +-
- include/hw/arm/virt.h                  |   2 +
- include/hw/misc/xlnx-zynqmp-apu-ctrl.h |   2 +-
- target/arm/cpu.h                       |  30 +++++
- target/arm/kvm-consts.h                |   8 +-
- hw/arm/boot.c                          |  10 +-
- hw/arm/smmu-common.c                   |   7 +-
- hw/arm/smmuv3.c                        |  12 +-
- hw/arm/virt.c                          | 202 +++++++++++++++++++++++-----
- hw/intc/arm_gic_common.c               |   7 +-
- hw/intc/arm_gic_kvm.c                  |  14 +-
- hw/intc/arm_gicv3_common.c             |   7 +-
- hw/intc/arm_gicv3_dist.c               |   4 +-
- hw/intc/arm_gicv3_its.c                |  14 +-
- hw/intc/arm_gicv3_its_common.c         |   7 +-
- hw/intc/arm_gicv3_its_kvm.c            |  14 +-
- hw/intc/arm_gicv3_kvm.c                |  14 +-
- hw/misc/imx6_src.c                     |   2 +-
- hw/misc/iotkit-sysctl.c                |   1 -
- target/arm/cpu.c                       |   5 +-
- target/arm/cpu64.c                     |  70 ++++++++++
- target/arm/cpu_tcg.c                   |   1 +
- target/arm/helper.c                    | 231 ++++++++++++++++++++++++---------
- hw/misc/meson.build                    |  11 +-
-files changed, 538 insertions(+), 158 deletions(-)

-[PULL 08/29] hw/arm/virt: build SMBIOS 19 table
+[PULL 01/35] hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
-From: Mihai Carabas <mihai.carabas@oracle.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Use the base_memmap to build the SMBIOS 19 table which provides the address
+Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
-mapping for a Physical Memory Array (from spec [1] chapter 7.20).
+connect FIQ output of the GIC CPU interfaces to the CPU.
-This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-("SMBIOS: Build aggregate smbios tables and entry point").
+Message-id: 20240130152548.17855-1-philmd@linaro.org
 [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf
 The absence of this table is a breach of the specs and is
 detected by the FirmwareTestSuite (FWTS), but it doesn't
 cause any known problems for guest OSes.
 Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
 Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 8 +++++++-
+ hw/arm/xilinx_zynq.c | 2 ++
-file changed, 7 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/arm/xilinx_zynq.c
-+++ b/hw/arm/virt.c
++++ b/hw/arm/xilinx_zynq.c
-@@ -XXX,XX +XXX,XX @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
+@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
- static void virt_build_smbios(VirtMachineState *vms)
+     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
- {
+     sysbus_connect_irq(busdev, 0,
-     MachineClass *mc = MACHINE_GET_CLASS(vms);
+                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
-+    MachineState *ms = MACHINE(vms);
++    sysbus_connect_irq(busdev, 1,
-     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
++                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
-     uint8_t *smbios_tables, *smbios_anchor;
-     size_t smbios_tables_len, smbios_anchor_len;
+     for (n = 0; n < 64; n++) {
-+    struct smbios_phys_mem_area mem_array;
+         pic[n] = qdev_get_gpio_in(dev, n);
      const char *product = "QEMU Virtual Machine";
      if (kvm_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(VirtMachineState *vms)
                          vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
                          true, SMBIOS_ENTRY_POINT_TYPE_64);
 -    smbios_get_tables(MACHINE(vms), NULL, 0,
 +    /* build the array of physical mem area from base_memmap */
 +    mem_array.address = vms->memmap[VIRT_MEM].base;
 +    mem_array.length = ms->ram_size;
 +
 +    smbios_get_tables(ms, &mem_array, 1,
                        &smbios_tables, &smbios_tables_len,
                        &smbios_anchor, &smbios_anchor_len,
                        &error_fatal);
 --
-.25.1
+.34.1

-[PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
+[PULL 02/35] linux-user/aarch64: Choose SYNC as the preferred MTE mode
-From: Gavin Shan <gshan@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-This introduces virt_get_high_memmap_enabled() helper, which returns
+The API does not generate an error for setting ASYNC | SYNC; that merely
-the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
+constrains the selection vs the per-cpu default.  For qemu linux-user,
-be used in the subsequent patches.
+choose SYNC as the default.
-No functional change intended.
+Cc: qemu-stable@nongnu.org
+Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
+Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
 Reviewed-by: Marc Zyngier <maz@kernel.org>
 Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
 Message-id: 20221029224307.138822-5-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 32 +++++++++++++++++++-------------
+ linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
-file changed, 19 insertions(+), 13 deletions(-)
+file changed, 17 insertions(+), 12 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/linux-user/aarch64/target_prctl.h
-+++ b/hw/arm/virt.c
++++ b/linux-user/aarch64/target_prctl.h
-@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
+@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
-     return arm_cpu_mp_affinity(idx, clustersz);
+     env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
- }
+     if (cpu_isar_feature(aa64_mte, cpu)) {
-+static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
+-        switch (arg2 & PR_MTE_TCF_MASK) {
-+                                                 int index)
+-        case PR_MTE_TCF_NONE:
-+{
+-        case PR_MTE_TCF_SYNC:
-+    bool *enabled_array[] = {
+-        case PR_MTE_TCF_ASYNC:
 +        &vms->highmem_redists,
 +        &vms->highmem_ecam,
 +        &vms->highmem_mmio,
 +    };
 +
 +    assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
 +           ARRAY_SIZE(enabled_array));
 +    assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
 +
 +    return enabled_array[index - VIRT_LOWMEMMAP_LAST];
 +}
 +
  static void virt_set_high_memmap(VirtMachineState *vms,
                                   hwaddr base, int pa_bits)
  {
      hwaddr region_base, region_size;
 -    bool fits;
 +    bool *region_enabled, fits;
      int i;
      for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
 +        region_enabled = virt_get_high_memmap_enabled(vms, i);
          region_base = ROUND_UP(base, extended_memmap[i].size);
          region_size = extended_memmap[i].size;
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
              vms->highest_gpa = region_base + region_size - 1;
          }
 -        switch (i) {
 -        case VIRT_HIGH_GIC_REDIST2:
 -            vms->highmem_redists &= fits;
 -            break;
--        case VIRT_HIGH_PCIE_ECAM:
+-        default:
--            vms->highmem_ecam &= fits;
+-            return -EINVAL;
 -            break;
 -        case VIRT_HIGH_PCIE_MMIO:
 -            vms->highmem_mmio &= fits;
 -            break;
 -        }
 -
-+        *region_enabled &= fits;
+         /*
-         base = region_base + region_size;
+          * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
-     }
+-         * Note that the syscall values are consistent with hw.
- }
++         *
 +         * The kernel has a per-cpu configuration for the sysadmin,
 +         * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
 +         * which qemu does not implement.
 +         *
 +         * Because there is no performance difference between the modes, and
 +         * because SYNC is most useful for debugging MTE errors, choose SYNC
 +         * as the preferred mode.  With this preference, and the way the API
 +         * uses only two bits, there is no way for the program to select
 +         * ASYMM mode.
           */
 -        env->cp15.sctlr_el[1] =
 -            deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
 +        unsigned tcf = 0;
 +        if (arg2 & PR_MTE_TCF_SYNC) {
 +            tcf = 1;
 +        } else if (arg2 & PR_MTE_TCF_ASYNC) {
 +            tcf = 2;
 +        }
 +        env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
          /*
           * Write PR_MTE_TAG to GCR_EL1[Exclude].
 --
-.25.1
+.34.1

-[PULL 09/29] target/arm: Add Cortex-A55 CPU
+[PULL 03/35] target/arm: Fix nregs computation in do_{ld,st}_zpa
-From: Timofey Kutergin <tkutergin@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
+The field is encoded as [0-3], which is convenient for
-it supports the Privileged Access Never (PAN) feature. Add
+indexing our array of function pointers, but the true
-a model of this CPU, so you can use a CPU type on the virt
+value is [1-4].  Adjust before calling do_mem_zpa.
 board that models a specific real hardware CPU, rather than
 having to use the QEMU-specific "max" CPU type.
-Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
+Add an assert, and move the comment re passing ZT to
-Message-id: 20221121150819.2782817-1-tkutergin@gmail.com
+the helper back next to the relevant code.
-[PMM: tweaked commit message]
 Cc: qemu-stable@nongnu.org
 Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
 Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- docs/system/arm/virt.rst |  1 +
+ target/arm/tcg/translate-sve.c | 16 ++++++++--------
- hw/arm/virt.c            |  1 +
+file changed, 8 insertions(+), 8 deletions(-)
  target/arm/cpu64.c       | 69 ++++++++++++++++++++++++++++++++++++++++
 files changed, 71 insertions(+)
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/target/arm/tcg/translate-sve.c
-+++ b/docs/system/arm/virt.rst
++++ b/target/arm/tcg/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
+@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
- - ``cortex-a15`` (32-bit; the default)
+     TCGv_ptr t_pg;
- - ``cortex-a35`` (64-bit)
+     int desc = 0;
- - ``cortex-a53`` (64-bit)
-+- ``cortex-a55`` (64-bit)
+-    /*
- - ``cortex-a57`` (64-bit)
+-     * For e.g. LD4, there are not enough arguments to pass all 4
- - ``cortex-a72`` (64-bit)
+-     * registers as pointers, so encode the regno into the data field.
- - ``cortex-a76`` (64-bit)
+-     * For consistency, do this even for LD1.
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+-     */
-index XXXXXXX..XXXXXXX 100644
++    assert(mte_n >= 1 && mte_n <= 4);
---- a/hw/arm/virt.c
+     if (s->mte_active[0]) {
-+++ b/hw/arm/virt.c
+         int msz = dtype_msz(dtype);
-@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
-     ARM_CPU_TYPE_NAME("cortex-a15"),
+@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
-     ARM_CPU_TYPE_NAME("cortex-a35"),
+         addr = clean_data_tbi(s, addr);
-     ARM_CPU_TYPE_NAME("cortex-a53"),
+     }
-+    ARM_CPU_TYPE_NAME("cortex-a55"),
-     ARM_CPU_TYPE_NAME("cortex-a57"),
++    /*
-     ARM_CPU_TYPE_NAME("cortex-a72"),
++     * For e.g. LD4, there are not enough arguments to pass all 4
-     ARM_CPU_TYPE_NAME("cortex-a76"),
++     * registers as pointers, so encode the regno into the data field.
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++     * For consistency, do this even for LD1.
-index XXXXXXX..XXXXXXX 100644
++     */
---- a/target/arm/cpu64.c
+     desc = simd_desc(vsz, vsz, zt | desc);
-+++ b/target/arm/cpu64.c
+     t_pg = tcg_temp_new_ptr();
-@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
-     define_cortex_a72_a57_a53_cp_reginfo(cpu);
+@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
       * accessible via the instruction encoding.
       */
      assert(fn != NULL);
 -    do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
 +    do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
  }
-+static void aarch64_a55_initfn(Object *obj)
+ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
-+{
+@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
-+    ARMCPU *cpu = ARM_CPU(obj);
+     if (nreg == 0) {
-+
+         /* ST1 */
-+    cpu->dtb_compatible = "arm,cortex-a55";
+         fn = fn_single[s->mte_active[0]][be][msz][esz];
-+    set_feature(&cpu->env, ARM_FEATURE_V8);
+-        nreg = 1;
-+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+     } else {
-+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+         /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
-+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+         assert(msz == esz);
-+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+         fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
-+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+     }
-+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+     assert(fn != NULL);
-+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+-    do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
-+
++    do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
-+    /* Ordered by B2.4 AArch64 registers by functional group */
+ }
-+    cpu->clidr = 0x82000023;
-+    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
 +    cpu->dcz_blocksize = 4; /* 64 bytes */
 +    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
 +    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
 +    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
 +    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
 +    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
 +    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
 +    cpu->isar.id_aa64pfr0  = 0x0000000010112222ull;
 +    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
 +    cpu->id_afr0       = 0x00000000;
 +    cpu->isar.id_dfr0  = 0x04010088;
 +    cpu->isar.id_isar0 = 0x02101110;
 +    cpu->isar.id_isar1 = 0x13112111;
 +    cpu->isar.id_isar2 = 0x21232042;
 +    cpu->isar.id_isar3 = 0x01112131;
 +    cpu->isar.id_isar4 = 0x00011142;
 +    cpu->isar.id_isar5 = 0x01011121;
 +    cpu->isar.id_isar6 = 0x00000010;
 +    cpu->isar.id_mmfr0 = 0x10201105;
 +    cpu->isar.id_mmfr1 = 0x40000000;
 +    cpu->isar.id_mmfr2 = 0x01260000;
 +    cpu->isar.id_mmfr3 = 0x02122211;
 +    cpu->isar.id_mmfr4 = 0x00021110;
 +    cpu->isar.id_pfr0  = 0x10010131;
 +    cpu->isar.id_pfr1  = 0x00011011;
 +    cpu->isar.id_pfr2  = 0x00000011;
 +    cpu->midr = 0x412FD050;          /* r2p0 */
 +    cpu->revidr = 0;
 +
 +    /* From B2.23 CCSIDR_EL1 */
 +    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
 +    cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
 +    cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
 +
 +    /* From B2.96 SCTLR_EL3 */
 +    cpu->reset_sctlr = 0x30c50838;
 +
 +    /* From B4.45 ICH_VTR_EL2 */
 +    cpu->gic_num_lrs = 4;
 +    cpu->gic_vpribits = 5;
 +    cpu->gic_vprebits = 5;
 +    cpu->gic_pribits = 5;
 +
 +    cpu->isar.mvfr0 = 0x10110222;
 +    cpu->isar.mvfr1 = 0x13211111;
 +    cpu->isar.mvfr2 = 0x00000043;
 +
 +    /* From D5.4 AArch64 PMU register summary */
 +    cpu->isar.reset_pmcr_el0 = 0x410b3000;
 +}
 +
  static void aarch64_a72_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
      { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
      { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
      { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
 +    { .name = "cortex-a55",         .initfn = aarch64_a55_initfn },
      { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
      { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
      { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
 --
-.25.1
+.34.1

-[PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
+[PULL 04/35] target/arm: Adjust and validate mtedesc sizem1
-From: Luke Starrett <lukes@xsightlabs.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
+When we added SVE_MTEDESC_SHIFT, we effectively limited the
-register:
+maximum size of MTEDESC.  Adjust SIZEM1 to consume the remaining
 bits (32 - 10 - 5 - 12 == 5).  Assert that the data to be stored
 fits within the field (expecting 8 * 4 - 1 == 31, exact fit).
-"indicates the maximum SPI INTID that the GIC implementation supports"
+Cc: qemu-stable@nongnu.org
 As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
 for the internal 16x SGI's and 16x PPI's.  However, the original GICv3
 model subtracted off the SGI/PPI.  Cosmetically this can be seen at OS
 boot (Linux) showing 32 shy of what should be there, i.e.:
     [    0.000000] GICv3: 224 SPIs implemented
 Though in hw/arm/virt.c, the machine is configured for 256 SPI's.  ARM
 virt machine likely doesn't have a problem with this because the upper
 IRQ's don't actually have anything meaningful wired. But, this does
 become a functional issue on a custom use case which wants to make use
 of these IRQ's.  Additionally, boot code (i.e. TF-A) will only init up
 to the number (blocks of 32) that it believes to actually be there.
 Signed-off-by: Luke Starrett <lukes@xsightlabs.com>
 Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
+Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_dist.c | 4 ++--
+ target/arm/internals.h         | 2 +-
-file changed, 2 insertions(+), 2 deletions(-)
+ target/arm/tcg/translate-sve.c | 7 ++++---
 files changed, 5 insertions(+), 4 deletions(-)
-diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
+diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_dist.c
+--- a/target/arm/internals.h
-+++ b/hw/intc/arm_gicv3_dist.c
++++ b/target/arm/internals.h
-@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI,   4, 2)
-          * MBIS == 0 (message-based SPIs not supported)
+ FIELD(MTEDESC, TCMA,  6, 2)
-          * SecurityExtn == 1 if security extns supported
+ FIELD(MTEDESC, WRITE, 8, 1)
-          * CPUNumber == 0 since for us ARE is always 1
+ FIELD(MTEDESC, ALIGN, 9, 3)
--         * ITLinesNumber == (num external irqs / 32) - 1
+-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12)  /* size - 1 */
-+         * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
++FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12)  /* size - 1 */
-          */
--        int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
+ bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
-+        int itlinesnumber = (s->num_irq / 32) - 1;
+ uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
-         /*
+diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
-          * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
+index XXXXXXX..XXXXXXX 100644
-          * "security extensions not supported" always implies DS == 1,
+--- a/target/arm/tcg/translate-sve.c
 +++ b/target/arm/tcg/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
  {
      unsigned vsz = vec_full_reg_size(s);
      TCGv_ptr t_pg;
 +    uint32_t sizem1;
      int desc = 0;
      assert(mte_n >= 1 && mte_n <= 4);
 +    sizem1 = (mte_n << dtype_msz(dtype)) - 1;
 +    assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
      if (s->mte_active[0]) {
 -        int msz = dtype_msz(dtype);
 -
          desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
          desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
          desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
          desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
 -        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
 +        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
          desc <<= SVE_MTEDESC_SHIFT;
      } else {
          addr = clean_data_tbi(s, addr);
 --
-.25.1
+.34.1

-[PULL 05/29] hw/arm/virt: Improve high memory region address assignment
+[PULL 05/35] target/arm: Split out make_svemte_desc
-From: Gavin Shan <gshan@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-There are three high memory regions, which are VIRT_HIGH_REDIST2,
+Share code that creates mtedesc and embeds within simd_desc.
 VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
 are floating on highest RAM address. However, they can be disabled
 in several cases.
-(1) One specific high memory region is likely to be disabled by
+Cc: qemu-stable@nongnu.org
-    code by toggling vms->highmem_{redists, ecam, mmio}.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
+Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
-    'virt-2.12' or ealier than it.
+Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
 (3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
     on 32-bits system.
 (4) One specific high memory region is disabled when it breaks the
     PA space limit.
 The current implementation of virt_set_{memmap, high_memmap}() isn't
 optimized because the high memory region's PA space is always reserved,
 regardless of whatever the actual state in the corresponding
 vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and
 'vms->highest_gpa' are always increased for case (1), (2) and (3).
 It's unnecessary since the assigned PA space for the disabled high
 memory region won't be used afterwards.
 Improve the address assignment for those three high memory region by
 skipping the address assignment for one specific high memory region if
 it has been disabled in case (1), (2) and (3). The memory layout may
 be changed after the improvement is applied, which leads to potential
 migration breakage. So 'vms->highmem_compact' is added to control if
 the improvement should be applied. For now, 'vms->highmem_compact' is
 set to false, meaning that we don't have memory layout change until it
 becomes configurable through property 'compact-highmem' in next patch.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Marc Zyngier <maz@kernel.org>
 Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
 Message-id: 20221029224307.138822-6-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/virt.h |  1 +
+ target/arm/tcg/translate-a64.h |  2 ++
- hw/arm/virt.c         | 15 ++++++++++-----
+ target/arm/tcg/translate-sme.c | 15 +++--------
-files changed, 11 insertions(+), 5 deletions(-)
+ target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
 files changed, 31 insertions(+), 33 deletions(-)
-diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
+diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/virt.h
+--- a/target/arm/tcg/translate-a64.h
-+++ b/include/hw/arm/virt.h
++++ b/target/arm/tcg/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
+@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
-     PFlashCFI01 *flash[2];
+ bool sve_access_check(DisasContext *s);
-     bool secure;
+ bool sme_enabled_check(DisasContext *s);
-     bool highmem;
+ bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
-+    bool highmem_compact;
++uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
-     bool highmem_ecam;
++                          uint32_t msz, bool is_write, uint32_t data);
-     bool highmem_mmio;
-     bool highmem_redists;
+ /* This function corresponds to CheckStreamingSVEEnabled. */
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+ static inline bool sme_sm_enabled_check(DisasContext *s)
 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/tcg/translate-sme.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/tcg/translate-sme.c
-@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
-         vms->memmap[i].size = region_size;
+     TCGv_ptr t_za, t_pg;
-         /*
+     TCGv_i64 addr;
--         * Check each device to see if they fit in the PA space,
+-    int svl, desc = 0;
--         * moving highest_gpa as we go.
++    uint32_t desc;
-+         * Check each device to see if it fits in the PA space,
+     bool be = s->be_data == MO_BE;
-+         * moving highest_gpa as we go. For compatibility, move
+     bool mte = s->mte_active[0];
-+         * highest_gpa for disabled fitting devices as well, if
-+         * the compact layout has been disabled.
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
-          *
+     tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
-          * For each device that doesn't fit, disable it.
+     tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
-          */
-         fits = (region_base + region_size) <= BIT_ULL(pa_bits);
+-    if (mte) {
--        if (fits) {
+-        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
--            vms->highest_gpa = region_base + region_size - 1;
+-        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
-+        *region_enabled &= fits;
+-        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
-+        if (vms->highmem_compact && !*region_enabled) {
+-        desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
-+            continue;
+-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
-         }
+-        desc <<= SVE_MTEDESC_SHIFT;
+-    } else {
--        *region_enabled &= fits;
++    if (!mte) {
-         base = region_base + region_size;
+         addr = clean_data_tbi(s, addr);
 +        if (fits) {
 +            vms->highest_gpa = base - 1;
 +        }
      }
+-    svl = streaming_vec_reg_size(s);
+-    desc = simd_desc(svl, svl, desc);
++
++    desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
+     fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
+                                       tcg_constant_i32(desc));
+diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/translate-sve.c
++++ b/target/arm/tcg/translate-sve.c
+@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
+, 2, 1, 3
+ };
+-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
+-                       int dtype, uint32_t mte_n, bool is_write,
+-                       gen_helper_gvec_mem *fn)
++uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
++                          uint32_t msz, bool is_write, uint32_t data)
+ {
+-    unsigned vsz = vec_full_reg_size(s);
+-    TCGv_ptr t_pg;
+     uint32_t sizem1;
+-    int desc = 0;
++    uint32_t desc = 0;
+-    assert(mte_n >= 1 && mte_n <= 4);
+-    sizem1 = (mte_n << dtype_msz(dtype)) - 1;
++    /* Assert all of the data fits, with or without MTE enabled. */
++    assert(nregs >= 1 && nregs <= 4);
++    sizem1 = (nregs << msz) - 1;
+     assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
++    assert(data < 1u << SVE_MTEDESC_SHIFT);
++
+     if (s->mte_active[0]) {
+         desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
+         desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
+@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
+         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
+         desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
+         desc <<= SVE_MTEDESC_SHIFT;
+-    } else {
++    }
++    return simd_desc(vsz, vsz, desc | data);
++}
++
++static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
++                       int dtype, uint32_t nregs, bool is_write,
++                       gen_helper_gvec_mem *fn)
++{
++    TCGv_ptr t_pg;
++    uint32_t desc;
++
++    if (!s->mte_active[0]) {
+         addr = clean_data_tbi(s, addr);
+     }
+@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
+      * registers as pointers, so encode the regno into the data field.
+      * For consistency, do this even for LD1.
+      */
+-    desc = simd_desc(vsz, vsz, zt | desc);
++    desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
++                            dtype_msz(dtype), is_write, zt);
+     t_pg = tcg_temp_new_ptr();
+     tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
+@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
+                        int scale, TCGv_i64 scalar, int msz, bool is_write,
+                        gen_helper_gvec_mem_scatter *fn)
+ {
+-    unsigned vsz = vec_full_reg_size(s);
+     TCGv_ptr t_zm = tcg_temp_new_ptr();
+     TCGv_ptr t_pg = tcg_temp_new_ptr();
+     TCGv_ptr t_zt = tcg_temp_new_ptr();
+-    int desc = 0;
+-
+-    if (s->mte_active[0]) {
+-        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
+-        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
+-        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
+-        desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
+-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
+-        desc <<= SVE_MTEDESC_SHIFT;
+-    }
+-    desc = simd_desc(vsz, vsz, desc | scale);
++    uint32_t desc;
+     tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
+     tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
+     tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
++
++    desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
+     fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
  }
 --
-.25.1
+.34.1

-[PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt
+[PULL 06/35] target/arm: Handle mte in do_ldrq, do_ldro
-From: Schspa Shi <schspa@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-We use 32bit value for linux,initrd-[start/end], when we have
+These functions "use the standard load helpers", but
-loader_start > 4GB, there will be a wrong initrd_start passed
+fail to clean_data_tbi or populate mtedesc.
 to the kernel, and the kernel will report the following warning.
-[    0.000000] ------------[ cut here ]------------
+Cc: qemu-stable@nongnu.org
 [    0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ...
 [    0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244
 [    0.000000] Modules linked in:
 [    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G        W          6.1.0-rc3-13250-g30a0b95b1335-dirty #28
 [    0.000000] Hardware name: Horizon Sigi Virtual development board (DT)
 [    0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
 [    0.000000] pc : arm64_memblock_init+0x158/0x244
 [    0.000000] lr : arm64_memblock_init+0x158/0x244
 [    0.000000] sp : ffff800009273df0
 [    0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000
 [    0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000
 [    0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000
 [    0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020
 [    0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261
 [    0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000
 [    0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000
 [    0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69
 [    0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88
 [    0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056
 [    0.000000] Call trace:
 [    0.000000]  arm64_memblock_init+0x158/0x244
 [    0.000000]  setup_arch+0x164/0x1cc
 [    0.000000]  start_kernel+0x94/0x4ac
 [    0.000000]  __primary_switched+0xb4/0xbc
 [    0.000000] ---[ end trace 0000000000000000 ]---
 [    0.000000] Zone ranges:
 [    0.000000]   DMA      [mem 0x0000001000000000-0x0000001007ffffff]
 This doesn't affect any machine types we currently support, because
 for all of our machine types the RAM starts well below the 4GB
 mark, but it does demonstrate that we're not currently writing
 the device-tree properties quite as intended.
 To fix it, we can change it to write these values to the dtb using a
 type width matching #address-cells.  This is the intended size for
 these dtb properties, and is how u-boot, for instance, writes them,
 although in practice the Linux kernel will cope with them being any
 width as long as they're big enough to fit the value.
 Signed-off-by: Schspa Shi <schspa@gmail.com>
 Message-id: 20221129160724.75667-1-schspa@gmail.com
 [PMM: tweaked commit message]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
+Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 10 ++++++----
+ target/arm/tcg/translate-sve.c | 15 +++++++++++++--
-file changed, 6 insertions(+), 4 deletions(-)
+file changed, 13 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/target/arm/tcg/translate-sve.c
-+++ b/hw/arm/boot.c
++++ b/target/arm/tcg/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
+@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
      unsigned vsz = vec_full_reg_size(s);
      TCGv_ptr t_pg;
      int poff;
 +    uint32_t desc;
      /* Load the first quadword using the normal predicated load helpers.  */
 +    if (!s->mte_active[0]) {
 +        addr = clean_data_tbi(s, addr);
 +    }
 +
      poff = pred_full_reg_offset(s, pg);
      if (vsz > 16) {
          /*
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
      gen_helper_gvec_mem *fn
          = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
 -    fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
 +    desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
 +    fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
      /* Replicate that first quadword.  */
      if (vsz > 16) {
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
      unsigned vsz_r32;
      TCGv_ptr t_pg;
      int poff, doff;
 +    uint32_t desc;
      if (vsz < 32) {
          /*
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
      }
-     if (binfo->initrd_size) {
+     /* Load the first octaword using the normal predicated load helpers.  */
--        rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
++    if (!s->mte_active[0]) {
--                                   binfo->initrd_start);
++        addr = clean_data_tbi(s, addr);
-+        rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
++    }
-+                                          acells, binfo->initrd_start);
-         if (rc < 0) {
+     poff = pred_full_reg_offset(s, pg);
-             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
+     if (vsz > 32) {
-             goto fail;
+@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
-         }
+     gen_helper_gvec_mem *fn
--        rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+         = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
--                                   binfo->initrd_start + binfo->initrd_size);
+-    fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
-+        rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
++    desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
-+                                          acells,
++    fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
-+                                          binfo->initrd_start +
-+                                          binfo->initrd_size);
+     /*
-         if (rc < 0) {
+      * Replicate that first octaword.
              fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
              goto fail;
 --
-.25.1
+.34.1

-[PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
+[PULL 07/35] target/arm: Fix SVE/SME gross MTE suppression checks
-From: Gavin Shan <gshan@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-This introduces variable 'region_base' for the base address of the
+The TBI and TCMA bits are located within mtedesc, not desc.
 specific high memory region. It's the preparatory work to optimize
 high memory region address assignment.
-No functional change intended.
+Cc: qemu-stable@nongnu.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
+Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
 Reviewed-by: Marc Zyngier <maz@kernel.org>
 Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
 Message-id: 20221029224307.138822-4-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 12 ++++++------
+ target/arm/tcg/sme_helper.c |  8 ++++----
-file changed, 6 insertions(+), 6 deletions(-)
+ target/arm/tcg/sve_helper.c | 12 ++++++------
 files changed, 10 insertions(+), 10 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/tcg/sme_helper.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/tcg/sme_helper.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
+@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
- static void virt_set_high_memmap(VirtMachineState *vms,
+     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
-                                  hwaddr base, int pa_bits)
- {
+     /* Perform gross MTE suppression early. */
--    hwaddr region_size;
+-    if (!tbi_check(desc, bit55) ||
-+    hwaddr region_base, region_size;
+-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
-     bool fits;
++    if (!tbi_check(mtedesc, bit55) ||
-     int i;
++        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
+         mtedesc = 0;
      for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
 +        region_base = ROUND_UP(base, extended_memmap[i].size);
          region_size = extended_memmap[i].size;
 -        base = ROUND_UP(base, region_size);
 -        vms->memmap[i].base = base;
 +        vms->memmap[i].base = region_base;
          vms->memmap[i].size = region_size;
          /*
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
           *
           * For each device that doesn't fit, disable it.
           */
 -        fits = (base + region_size) <= BIT_ULL(pa_bits);
 +        fits = (region_base + region_size) <= BIT_ULL(pa_bits);
          if (fits) {
 -            vms->highest_gpa = base + region_size - 1;
 +            vms->highest_gpa = region_base + region_size - 1;
          }
          switch (i) {
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
              break;
          }
 -        base += region_size;
 +        base = region_base + region_size;
      }
- }
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
      desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
      /* Perform gross MTE suppression early. */
 -    if (!tbi_check(desc, bit55) ||
 -        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +    if (!tbi_check(mtedesc, bit55) ||
 +        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
          mtedesc = 0;
      }
 diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/sve_helper.c
 +++ b/target/arm/tcg/sve_helper.c
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
      desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
      /* Perform gross MTE suppression early. */
 -    if (!tbi_check(desc, bit55) ||
 -        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +    if (!tbi_check(mtedesc, bit55) ||
 +        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
          mtedesc = 0;
      }
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
      desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
      /* Perform gross MTE suppression early. */
 -    if (!tbi_check(desc, bit55) ||
 -        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +    if (!tbi_check(mtedesc, bit55) ||
 +        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
          mtedesc = 0;
      }
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
      desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
      /* Perform gross MTE suppression early. */
 -    if (!tbi_check(desc, bit55) ||
 -        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
 +    if (!tbi_check(mtedesc, bit55) ||
 +        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
          mtedesc = 0;
      }
 --
-.25.1
+.34.1

-New patch
+[PULL 08/35] hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
+The raven_io_ops MemoryRegionOps is the only one in the source tree
+which sets .valid.unaligned to indicate that it should support
+unaligned accesses and which does not also set .impl.unaligned to
+indicate that its read and write functions can do the unaligned
+handling themselves.  This is a problem, because at the moment the
+core memory system does not implement the support for handling
+unaligned accesses by doing a series of aligned accesses and
+combining them (system/memory.c:access_with_adjusted_size() has a
+TODO comment noting this).
+Fortunately raven_io_read() and raven_io_write() will correctly deal
+with the case of being passed an unaligned address, so we can fix the
+missing unaligned access support by setting .impl.unaligned in the
+MemoryRegionOps struct.
+Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Tested-by: Cédric Le Goater <clg@redhat.com>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
+Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
+---
+ hw/pci-host/raven.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/pci-host/raven.c
++++ b/hw/pci-host/raven.c
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
+     .write = raven_io_write,
+     .endianness = DEVICE_LITTLE_ENDIAN,
+     .impl.max_access_size = 4,
++    .impl.unaligned = true,
+     .valid.unaligned = true,
+ };
+--
+.34.1

-[PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
+[PULL 09/35] hw/block/tc58128: Don't emit deprecation warning under qtest
-Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.
+Suppress the deprecation warning when we're running under qtest,
 to avoid "make check" including warning messages in its output.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org
+Message-id: 20240206154151.155620-1-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_common.c | 7 ++++---
+ hw/block/tc58128.c | 4 +++-
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
+diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_common.c
+--- a/hw/block/tc58128.c
-+++ b/hw/intc/arm_gicv3_common.c
++++ b/hw/block/tc58128.c
-@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = {
-     g_free(s->redist_region_count);
- }
+ int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
 -static void arm_gicv3_common_reset(DeviceState *dev)
 +static void arm_gicv3_common_reset_hold(Object *obj)
  {
--    GICv3State *s = ARM_GICV3_COMMON(dev);
+-    warn_report_once("The TC58128 flash device is deprecated");
-+    GICv3State *s = ARM_GICV3_COMMON(obj);
++    if (!qtest_enabled()) {
-     int i;
++        warn_report_once("The TC58128 flash device is deprecated");
++    }
-     for (i = 0; i < s->num_cpu; i++) {
+     init_dev(&tc58128_devs[0], zone1);
-@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
+     init_dev(&tc58128_devs[1], zone2);
- static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
+     return sh7750_register_io_device(s, &tc58128);
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
      ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 -    dc->reset = arm_gicv3_common_reset;
 +    rc->phases.hold = arm_gicv3_common_reset_hold;
      dc->realize = arm_gicv3_common_realize;
      device_class_set_props(dc, arm_gicv3_common_properties);
      dc->vmsd = &vmstate_gicv3;
 --
-.25.1
+.34.1

-New patch
+[PULL 10/35] tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
+We deliberately don't include qtests_npcm7xx in qtests_aarch64,
+because we already get the coverage of those tests via qtests_arm,
+and we don't want to use extra CI minutes testing them twice.
+In commit 327b680877b79c4b we added it to qtests_aarch64; revert
+that change.
+Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
+---
+ tests/qtest/meson.build | 1 -
+file changed, 1 deletion(-)
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/meson.build
++++ b/tests/qtest/meson.build
+@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
+   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
+   (config_all_accel.has_key('CONFIG_TCG') and                                            \
+    config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
+-  (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
+   ['arm-cpu-features',
+    'numa-test',
+    'boot-serial-test',
+--
+.34.1

-New patch
+[PULL 11/35] tests/qtest/bios-tables-test: Allow changes to virt GTDT
+Allow changes to the virt GTDT -- we are going to add the IRQ
+entry for a new timer to it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
+Message-id: 20240122143537.233498-2-peter.maydell@linaro.org
+---
+ tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
+file changed, 2 insertions(+)
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
+@@ -1 +1,3 @@
+ /* List of comma-separated changed AML files to ignore */
++"tests/data/acpi/virt/FACP",
++"tests/data/acpi/virt/GTDT",
+--
+.34.1

-[PULL 06/29] hw/arm/virt: Add 'compact-highmem' property
+[PULL 12/35] hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
-From: Gavin Shan <gshan@redhat.com>
+Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
+non-secure EL2 virtual timer.  We implemented the timer itself in the
-After the improvement to high memory region address assignment is
+CPU model, but never wired up its IRQ line to the GIC.
-applied, the memory layout can be changed, introducing possible
-migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
+Wire up the IRQ line (this is always safe whether the CPU has the
-is disabled or enabled when the optimization is applied or not, with
+interrupt or not, since it always creates the outbound IRQ line).
-the following configuration. The configuration is only achievable by
+Report it to the guest via dtb and ACPI if the CPU has the feature.
-modifying the source code until more properties are added to allow
-users selectively disable those high memory regions.
+The DTB binding is documented in the kernel's
+Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
-  pa_bits              = 40;
+and the ACPI table entries are documented in the ACPI specification
-  vms->highmem_redists = false;
+version 6.3 or later.
-  vms->highmem_ecam    = false;
-  vms->highmem_mmio    = true;
+Because the IRQ line ACPI binding is new in 6.3, we need to bump the
+FADT table rev to show that we might be using 6.3 features.
-  # qemu-system-aarch64 -accel kvm -cpu host    \
-    -machine virt-7.2,compact-highmem={on, off} \
+Note that exposing this IRQ in the DTB will trigger a bug in EDK2
-    -m 4G,maxmem=511G -monitor stdio
+versions prior to edk2-stable202311, for users who use the virt board
+with 'virtualization=on' to enable EL2 emulation and are booting an
-  Region             compact-highmem=off         compact-highmem=on
+EDK2 guest BIOS, if that EDK2 has assertions enabled.  The effect is
-  ----------------------------------------------------------------
+that EDK2 will assert on bootup:
-  MEM                [1GB         512GB]        [1GB         512GB]
-  HIGH_GIC_REDISTS2  [512GB       512GB+64MB]   [disabled]
+ ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48
-  HIGH_PCIE_ECAM     [512GB+256MB 512GB+512MB]  [disabled]
-  HIGH_PCIE_MMIO     [disabled]                 [512GB       1TB]
+If you see that assertion you should do one of:
+ * update your EDK2 binaries to edk2-stable202311 or newer
-In order to keep backwords compatibility, we need to disable the
+ * use the 'virt-8.2' versioned machine type
-optimization on machine, which is virt-7.1 or ealier than it. It
+ * not use 'virtualization=on'
-means the optimization is enabled by default from virt-7.2. Besides,
-'compact-highmem' property is added so that the optimization can be
+(The versions shipped with QEMU itself have the fix.)
-explicitly enabled or disabled on all machine types by users.
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Marc Zyngier <maz@kernel.org>
 Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
 Message-id: 20221029224307.138822-7-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
+Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst |  4 ++++
+ include/hw/arm/virt.h    |  2 ++
- include/hw/arm/virt.h    |  1 +
+ hw/arm/virt-acpi-build.c | 20 ++++++++++----
- hw/arm/virt.c            | 32 ++++++++++++++++++++++++++++++++
+ hw/arm/virt.c            | 60 ++++++++++++++++++++++++++++++++++------
-files changed, 37 insertions(+)
+files changed, 67 insertions(+), 15 deletions(-)
 diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/virt.rst
 +++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ highmem
    address space above 32 bits. The default is ``on`` for machine types
    later than ``virt-2.12``.
 +compact-highmem
 +  Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
 +  The default is ``on`` for machine types later than ``virt-7.2``.
 +
  gic-version
    Specify the version of the Generic Interrupt Controller (GIC) to provide.
    Valid values are:
 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/virt.h
 +++ b/include/hw/arm/virt.h
 @@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
-     bool no_pmu;
+     /* Machines < 6.2 have no support for describing cpu topology to guest */
-     bool claim_edge_triggered_timers;
+     bool no_cpu_topology;
-     bool smbios_old_sys_ver;
+     bool no_tcg_lpa2;
-+    bool no_highmem_compact;
++    bool no_ns_el2_virt_timer_irq;
-     bool no_highmem_ecam;
+ };
-     bool no_ged;   /* Machines < 4.2 have no support for ACPI GED device */
-     bool kvm_no_adjvtime;
+ struct VirtMachineState {
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
      PCIBus *bus;
      char *oem_id;
      char *oem_table_id;
 +    bool ns_el2_virt_timer_irq;
  };
  #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt-acpi-build.c
 +++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
  }
  /*
 - * ACPI spec, Revision 5.1
 - * 5.2.24 Generic Timer Description Table (GTDT)
 + * ACPI spec, Revision 6.5
 + * 5.2.25 Generic Timer Description Table (GTDT)
   */
  static void
  build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
      uint32_t irqflags = vmc->claim_edge_triggered_timers ?
 : /* Interrupt is Edge triggered */
 ;  /* Interrupt is Level triggered  */
 -    AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
 +    AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
                          .oem_table_id = vms->oem_table_id };
      acpi_table_begin(&table, table_data);
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
      build_append_int_noprefix(table_data, 0, 4);
      /* Platform Timer Offset */
      build_append_int_noprefix(table_data, 0, 4);
 -
 +    if (vms->ns_el2_virt_timer_irq) {
 +        /* Virtual EL2 Timer GSIV */
 +        build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
 +        /* Virtual EL2 Timer Flags */
 +        build_append_int_noprefix(table_data, irqflags, 4);
 +    } else {
 +        build_append_int_noprefix(table_data, 0, 4);
 +        build_append_int_noprefix(table_data, 0, 4);
 +    }
      acpi_table_end(linker, &table);
  }
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
  static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
                              VirtMachineState *vms, unsigned dsdt_tbl_offset)
  {
 -    /* ACPI v6.0 */
 +    /* ACPI v6.3 */
      AcpiFadtData fadt = {
          .rev = 6,
 -        .minor_ver = 0,
 +        .minor_ver = 3,
          .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
          .xdsdt_tbl_offset = &dsdt_tbl_offset,
      };
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
+@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
-  * Note the extended_memmap is sized so that it eventually also includes the
+     qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
-  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
+ }
-  * index of base_memmap).
-+ *
++/*
-+ * The memory map for these Highmem IO Regions can be in legacy or compact
++ * The CPU object always exposes the NS EL2 virt timer IRQ line,
-+ * layout, depending on 'compact-highmem' property. With legacy layout, the
++ * but we don't want to advertise it to the guest in the dtb or ACPI
-+ * PA space for one specific region is always reserved, even if the region
++ * table unless it's really going to do something.
-+ * has been disabled or doesn't fit into the PA space. However, the PA space
++ */
-+ * for the region won't be reserved in these circumstances with compact layout.
++static bool ns_el2_virt_timer_present(void)
   */
  static MemMapEntry extended_memmap[] = {
      /* Additional 64 MB redist region (can contain up to 512 redistributors) */
@@ -XXX,XX +XXX,XX @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
      vms->highmem = value;
  }
 +static bool virt_get_compact_highmem(Object *obj, Error **errp)
 +{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++    ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
-+
++    CPUARMState *env = &cpu->env;
-+    return vms->highmem_compact;
++
 +    return arm_feature(env, ARM_FEATURE_AARCH64) &&
 +        arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
 +}
 +
-+static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
+ static void create_fdt(VirtMachineState *vms)
 +{
 +    VirtMachineState *vms = VIRT_MACHINE(obj);
 +
 +    vms->highmem_compact = value;
 +}
 +
  static bool virt_get_its(Object *obj, Error **errp)
  {
-     VirtMachineState *vms = VIRT_MACHINE(obj);
+     MachineState *ms = MACHINE(vms);
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
-                                           "Set on/off to enable/disable using "
+                                 "arm,armv7-timer");
-                                           "physical address space above 32 bits");
+     }
+     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
-+    object_class_property_add_bool(oc, "compact-highmem",
+-    qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
-+                                   virt_get_compact_highmem,
+-                           GIC_FDT_IRQ_TYPE_PPI,
-+                                   virt_set_compact_highmem);
+-                           INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
-+    object_class_property_set_description(oc, "compact-highmem",
+-                           GIC_FDT_IRQ_TYPE_PPI,
-+                                          "Set on/off to enable/disable compact "
+-                           INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
-+                                          "layout for high memory regions");
+-                           GIC_FDT_IRQ_TYPE_PPI,
-+
+-                           INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
-     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
+-                           GIC_FDT_IRQ_TYPE_PPI,
-                                   virt_set_gic_version);
+-                           INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
-     object_class_property_set_description(oc, "gic-version",
++    if (vms->ns_el2_virt_timer_irq) {
-@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
++        qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
++                               GIC_FDT_IRQ_TYPE_PPI,
-     /* High memory is enabled by default */
++                               INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
-     vms->highmem = true;
++                               GIC_FDT_IRQ_TYPE_PPI,
-+    vms->highmem_compact = !vmc->no_highmem_compact;
++                               INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
-     vms->gic_version = VIRT_GIC_VERSION_NOSEL;
++                               GIC_FDT_IRQ_TYPE_PPI,
++                               INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
-     vms->highmem_ecam = !vmc->no_highmem_ecam;
++                               GIC_FDT_IRQ_TYPE_PPI,
-@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
++                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
++                               GIC_FDT_IRQ_TYPE_PPI,
- static void virt_machine_7_1_options(MachineClass *mc)
++                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
 +    } else {
 +        qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
 +                               GIC_FDT_IRQ_TYPE_PPI,
 +                               INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
 +                               GIC_FDT_IRQ_TYPE_PPI,
 +                               INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
 +                               GIC_FDT_IRQ_TYPE_PPI,
 +                               INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
 +                               GIC_FDT_IRQ_TYPE_PPI,
 +                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
 +    }
  }
  static void fdt_add_cpu_nodes(const VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
              [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
              [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
              [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
 +            [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
          };
          for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
          qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
          object_unref(cpuobj);
      }
 +
 +    /* Now we've created the CPUs we can see if they have the hypvirt timer */
 +    vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
 +        !vmc->no_ns_el2_virt_timer_irq;
 +
      fdt_add_timer_nodes(vms);
      fdt_add_cpu_nodes(vms);
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
  static void virt_machine_8_2_options(MachineClass *mc)
  {
 +    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
 +
-     virt_machine_7_2_options(mc);
+     virt_machine_9_0_options(mc);
-     compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
+     compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
-+    /* Compact layout for high memory regions was introduced with 7.2 */
++    /*
-+    vmc->no_highmem_compact = true;
++     * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
- }
++     * earlier machines. (Exposing it tickles a bug in older EDK2
- DEFINE_VIRT_MACHINE(7, 1)
++     * guest BIOS binaries.)
 +     */
 +    vmc->no_ns_el2_virt_timer_irq = true;
  }
  DEFINE_VIRT_MACHINE(8, 2)
 --
-.25.1
+.34.1

-New patch
+[PULL 13/35] tests/qtest/bios-tables-tests: Update virt golden reference
+Update the virt golden reference files to say that the FACP is ACPI
 v6.3, and the GTDT table is a revision 3 table with space for the
 virtual EL2 timer.
 Diffs from iasl:
@@ -XXX,XX +XXX,XX @@
  /*
   * Intel ACPI Component Architecture
   * AML/ASL+ Disassembler version 20200925 (64-bit version)
   * Copyright (c) 2000 - 2020 Intel Corporation
   *
 - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
 + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
   *
   * ACPI Data Table [FACP]
   *
   * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
   */
  [000h 0000   4]                    Signature : "FACP"    [Fixed ACPI Description Table (FADT)]
  [004h 0004   4]                 Table Length : 00000114
  [008h 0008   1]                     Revision : 06
 -[009h 0009   1]                     Checksum : 15
 +[009h 0009   1]                     Checksum : 12
  [00Ah 0010   6]                       Oem ID : "BOCHS "
  [010h 0016   8]                 Oem Table ID : "BXPC    "
  [018h 0024   4]                 Oem Revision : 00000001
  [01Ch 0028   4]              Asl Compiler ID : "BXPC"
  [020h 0032   4]        Asl Compiler Revision : 00000001
  [024h 0036   4]                 FACS Address : 00000000
  [028h 0040   4]                 DSDT Address : 00000000
  [02Ch 0044   1]                        Model : 00
  [02Dh 0045   1]                   PM Profile : 00 [Unspecified]
  [02Eh 0046   2]                SCI Interrupt : 0000
  [030h 0048   4]             SMI Command Port : 00000000
  [034h 0052   1]            ACPI Enable Value : 00
  [035h 0053   1]           ACPI Disable Value : 00
  [036h 0054   1]               S4BIOS Command : 00
  [037h 0055   1]              P-State Control : 00
@@ -XXX,XX +XXX,XX @@
       Use APIC Physical Destination Mode (V4) : 0
                         Hardware Reduced (V5) : 1
                        Low Power S0 Idle (V5) : 0
  [074h 0116  12]               Reset Register : [Generic Address Structure]
  [074h 0116   1]                     Space ID : 00 [SystemMemory]
  [075h 0117   1]                    Bit Width : 00
  [076h 0118   1]                   Bit Offset : 00
  [077h 0119   1]         Encoded Access Width : 00 [Undefined/Legacy]
  [078h 0120   8]                      Address : 0000000000000000
  [080h 0128   1]         Value to cause reset : 00
  [081h 0129   2]    ARM Flags (decoded below) : 0003
                                PSCI Compliant : 1
                         Must use HVC for PSCI : 1
 -[083h 0131   1]          FADT Minor Revision : 00
 +[083h 0131   1]          FADT Minor Revision : 03
  [084h 0132   8]                 FACS Address : 0000000000000000
  [08Ch 0140   8]                 DSDT Address : 0000000000000000
  [094h 0148  12]             PM1A Event Block : [Generic Address Structure]
  [094h 0148   1]                     Space ID : 00 [SystemMemory]
  [095h 0149   1]                    Bit Width : 00
  [096h 0150   1]                   Bit Offset : 00
  [097h 0151   1]         Encoded Access Width : 00 [Undefined/Legacy]
  [098h 0152   8]                      Address : 0000000000000000
  [0A0h 0160  12]             PM1B Event Block : [Generic Address Structure]
  [0A0h 0160   1]                     Space ID : 00 [SystemMemory]
  [0A1h 0161   1]                    Bit Width : 00
  [0A2h 0162   1]                   Bit Offset : 00
  [0A3h 0163   1]         Encoded Access Width : 00 [Undefined/Legacy]
  [0A4h 0164   8]                      Address : 0000000000000000
@@ -XXX,XX +XXX,XX @@
  [0F5h 0245   1]                    Bit Width : 00
  [0F6h 0246   1]                   Bit Offset : 00
  [0F7h 0247   1]         Encoded Access Width : 00 [Undefined/Legacy]
  [0F8h 0248   8]                      Address : 0000000000000000
  [100h 0256  12]        Sleep Status Register : [Generic Address Structure]
  [100h 0256   1]                     Space ID : 00 [SystemMemory]
  [101h 0257   1]                    Bit Width : 00
  [102h 0258   1]                   Bit Offset : 00
  [103h 0259   1]         Encoded Access Width : 00 [Undefined/Legacy]
  [104h 0260   8]                      Address : 0000000000000000
  [10Ch 0268   8]                Hypervisor ID : 00000000554D4551
  Raw Table Data: Length 276 (0x114)
 -    0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20  // FACP......BOCHS
 +    0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20  // FACP......BOCHS
 : 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
 : 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 -    0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 +    0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 : 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55  // ............QEMU
 : 00 00 00 00                                      // ....
@@ -XXX,XX +XXX,XX @@
  /*
   * Intel ACPI Component Architecture
   * AML/ASL+ Disassembler version 20200925 (64-bit version)
   * Copyright (c) 2000 - 2020 Intel Corporation
   *
 - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
 + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
   *
   * ACPI Data Table [GTDT]
   *
   * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
   */
  [000h 0000   4]                    Signature : "GTDT"    [Generic Timer Description Table]
 -[004h 0004   4]                 Table Length : 00000060
 -[008h 0008   1]                     Revision : 02
 -[009h 0009   1]                     Checksum : 9C
 +[004h 0004   4]                 Table Length : 00000068
 +[008h 0008   1]                     Revision : 03
 +[009h 0009   1]                     Checksum : 93
  [00Ah 0010   6]                       Oem ID : "BOCHS "
  [010h 0016   8]                 Oem Table ID : "BXPC    "
  [018h 0024   4]                 Oem Revision : 00000001
  [01Ch 0028   4]              Asl Compiler ID : "BXPC"
  [020h 0032   4]        Asl Compiler Revision : 00000001
  [024h 0036   8]        Counter Block Address : FFFFFFFFFFFFFFFF
  [02Ch 0044   4]                     Reserved : 00000000
  [030h 0048   4]         Secure EL1 Interrupt : 0000001D
  [034h 0052   4]    EL1 Flags (decoded below) : 00000000
                                  Trigger Mode : 0
                                      Polarity : 0
                                     Always On : 0
  [038h 0056   4]     Non-Secure EL1 Interrupt : 0000001E
@@ -XXX,XX +XXX,XX @@
  [040h 0064   4]      Virtual Timer Interrupt : 0000001B
  [044h 0068   4]     VT Flags (decoded below) : 00000000
                                  Trigger Mode : 0
                                      Polarity : 0
                                     Always On : 0
  [048h 0072   4]     Non-Secure EL2 Interrupt : 0000001A
  [04Ch 0076   4]   NEL2 Flags (decoded below) : 00000000
                                  Trigger Mode : 0
                                      Polarity : 0
                                     Always On : 0
  [050h 0080   8]   Counter Read Block Address : FFFFFFFFFFFFFFFF
  [058h 0088   4]         Platform Timer Count : 00000000
  [05Ch 0092   4]        Platform Timer Offset : 00000000
 +[060h 0096   4]       Virtual EL2 Timer GSIV : 00000000
 +[064h 0100   4]      Virtual EL2 Timer Flags : 00000000
 -Raw Table Data: Length 96 (0x60)
 +Raw Table Data: Length 104 (0x68)
 -    0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20  // GTDT`.....BOCHS
 +    0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20  // GTDTh.....BOCHS
 : 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
 : 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00  // ................
 : 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00  // ................
 : 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00  // ................
 : FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00  // ................
 +    0060: 00 00 00 00 00 00 00 00                          // ........
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
 Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
 ---
  tests/qtest/bios-tables-test-allowed-diff.h |   2 --
  tests/data/acpi/virt/FACP                   | Bin 276 -> 276 bytes
  tests/data/acpi/virt/GTDT                   | Bin 96 -> 104 bytes
 files changed, 2 deletions(-)
 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/bios-tables-test-allowed-diff.h
 +++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
  /* List of comma-separated changed AML files to ignore */
 -"tests/data/acpi/virt/FACP",
 -"tests/data/acpi/virt/GTDT",
 diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
 index XXXXXXX..XXXXXXX 100644
 GIT binary patch
 delta 25
 gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh
 delta 28
 kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20
 diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
 index XXXXXXX..XXXXXXX 100644
 GIT binary patch
 delta 25
 bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L
 delta 16
 Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u
 --
 .34.1

-New patch
+[PULL 14/35] hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
+The patchset adding the GMAC ethernet to this SoC crossed in the
+mail with the patchset cleaning up the NIC handling. When we
+create the GMAC modules we must call qemu_configure_nic_device()
+so that the user has the opportunity to use the -nic commandline
+option to create a network backend and connect it to the GMACs.
+Add the missing call.
+Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
+Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
+---
+ hw/arm/npcm7xx.c | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/npcm7xx.c
++++ b/hw/arm/npcm7xx.c
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
+         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
++        qemu_configure_nic_device(DEVICE(sbd), false, NULL);
+         /*
+          * The device exists regardless of whether it's connected to a QEMU
+          * netdev backend. So always instantiate it even if there is no
+--
+.34.1

-New patch
+[PULL 15/35] tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
+Currently QEMU will warn if there is a NIC on the board that
+is not connected to a backend. By default the '-nic user' will
+get used for all NICs, but if you manually connect a specific
+NIC to a specific backend, then the other NICs on the board
+have no backend and will be warned about:
+qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
+qemu-system-arm: warning: nic npcm-gmac.0 has no peer
+qemu-system-arm: warning: nic npcm-gmac.1 has no peer
+So suppress those warnings by manually connecting every NIC
+on the board to some backend.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
+---
+ tests/qtest/npcm7xx_emc-test.c | 5 ++++-
+file changed, 4 insertions(+), 1 deletion(-)
+diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/npcm7xx_emc-test.c
++++ b/tests/qtest/npcm7xx_emc-test.c
+@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
+      * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
+      * in the 'model' field to specify the device to match.
+      */
+-    g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
++    g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
++                           "-nic user,model=npcm7xx-emc "
++                           "-nic user,model=npcm-gmac "
++                           "-nic user,model=npcm-gmac",
+                            test_sockets[1], module_num);
+     g_test_queue_destroy(packet_test_clear, test_sockets);
+--
+.34.1

-[PULL 27/29] target/arm: align exposed ID registers with Linux
+[PULL 16/35] target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
-From: Zhuojia Shen <chaosdefinition@hotmail.com>
+It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
 CPU, and in fact if you try to do it we will assert:
-In CPUID registers exposed to userspace, some registers were missing
+#6  0x00007ffff4b95e96 in __GI___assert_fail
-and some fields were not exposed.  This patch aligns exposed ID
+    (assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
-registers and their fields with what the upstream kernel currently
+#7  0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
-exposes.
+#8  0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
 #9  0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512
-Specifically, the following new ID registers/fields are exposed to
+We might call pmu_counter_enabled() on an M-profile CPU (for example
-userspace:
+from the migration pre/post hooks in machine.c); this should always
 return false because these CPUs don't set ARM_FEATURE_PMU.
-ID_AA64PFR1_EL1.BT:       bits 3-0
+Avoid the assertion by not calling arm_mdcr_el2_eff() before we
-ID_AA64PFR1_EL1.MTE:      bits 11-8
+have done the early return for "PMU not present".
 ID_AA64PFR1_EL1.SME:      bits 27-24
-ID_AA64ZFR0_EL1.SVEver:   bits 3-0
+This fixes an assertion failure if you try to do a loadvm or
-ID_AA64ZFR0_EL1.AES:      bits 7-4
+savevm for an M-profile board.
 ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
 ID_AA64ZFR0_EL1.BF16:     bits 23-20
 ID_AA64ZFR0_EL1.SHA3:     bits 35-32
 ID_AA64ZFR0_EL1.SM4:      bits 43-40
 ID_AA64ZFR0_EL1.I8MM:     bits 47-44
 ID_AA64ZFR0_EL1.F32MM:    bits 55-52
 ID_AA64ZFR0_EL1.F64MM:    bits 59-56
-ID_AA64SMFR0_EL1.F32F32:  bit 32
+Cc: qemu-stable@nongnu.org
-ID_AA64SMFR0_EL1.B16F32:  bit 34
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
 ID_AA64SMFR0_EL1.F16F32:  bit 35
 ID_AA64SMFR0_EL1.I8I32:   bits 39-36
 ID_AA64SMFR0_EL1.F64F64:  bit 48
 ID_AA64SMFR0_EL1.I16I64:  bits 55-52
 ID_AA64SMFR0_EL1.FA64:    bit 63
 ID_AA64MMFR0_EL1.ECV:     bits 63-60
 ID_AA64MMFR1_EL1.AFP:     bits 47-44
 ID_AA64MMFR2_EL1.AT:      bits 35-32
 ID_AA64ISAR0_EL1.RNDR:    bits 63-60
 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
 ID_AA64ISAR1_EL1.BF16:    bits 47-44
 ID_AA64ISAR1_EL1.DGH:     bits 51-48
 ID_AA64ISAR1_EL1.I8MM:    bits 55-52
 ID_AA64ISAR2_EL1.WFxT:    bits 3-0
 ID_AA64ISAR2_EL1.RPRES:   bits 7-4
 ID_AA64ISAR2_EL1.GPA3:    bits 11-8
 ID_AA64ISAR2_EL1.APA3:    bits 15-12
 The code is also refactored to use symbolic names for ID register fields
 for better readability and maintainability.
 Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
 Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++--------
+ target/arm/helper.c | 12 ++++++++++--
-file changed, 79 insertions(+), 17 deletions(-)
+file changed, 10 insertions(+), 2 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
- #ifdef CONFIG_USER_ONLY
+     bool enabled, prohibited = false, filtered;
-         static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
+     bool secure = arm_is_secure(env);
-             { .name = "ID_AA64PFR0_EL1",
+     int el = arm_current_el(env);
--              .exported_bits = 0x000f000f00ff0000,
+-    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
--              .fixed_bits    = 0x0000000000000011 },
+-    uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
-+              .exported_bits = R_ID_AA64PFR0_FP_MASK |
++    uint64_t mdcr_el2;
-+                               R_ID_AA64PFR0_ADVSIMD_MASK |
++    uint8_t hpmn;
-+                               R_ID_AA64PFR0_SVE_MASK |
-+                               R_ID_AA64PFR0_DIT_MASK,
++    /*
-+              .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) |
++     * We might be called for M-profile cores where MDCR_EL2 doesn't
-+                            (0x1 << R_ID_AA64PFR0_EL1_SHIFT) },
++     * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
-             { .name = "ID_AA64PFR1_EL1",
++     * must be before we read that value.
--              .exported_bits = 0x00000000000000f0 },
++     */
-+              .exported_bits = R_ID_AA64PFR1_BT_MASK |
+     if (!arm_feature(env, ARM_FEATURE_PMU)) {
-+                               R_ID_AA64PFR1_SSBS_MASK |
+         return false;
-+                               R_ID_AA64PFR1_MTE_MASK |
+     }
-+                               R_ID_AA64PFR1_SME_MASK },
-             { .name = "ID_AA64PFR*_EL1_RESERVED",
++    mdcr_el2 = arm_mdcr_el2_eff(env);
--              .is_glob = true                     },
++    hpmn = mdcr_el2 & MDCR_HPMN;
--            { .name = "ID_AA64ZFR0_EL1"           },
++
-+              .is_glob = true },
+     if (!arm_feature(env, ARM_FEATURE_EL2) ||
-+            { .name = "ID_AA64ZFR0_EL1",
+             (counter < hpmn || counter == 31)) {
-+              .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
+         e = env->cp15.c9_pmcr & PMCRE;
 +                               R_ID_AA64ZFR0_AES_MASK |
 +                               R_ID_AA64ZFR0_BITPERM_MASK |
 +                               R_ID_AA64ZFR0_BFLOAT16_MASK |
 +                               R_ID_AA64ZFR0_SHA3_MASK |
 +                               R_ID_AA64ZFR0_SM4_MASK |
 +                               R_ID_AA64ZFR0_I8MM_MASK |
 +                               R_ID_AA64ZFR0_F32MM_MASK |
 +                               R_ID_AA64ZFR0_F64MM_MASK },
 +            { .name = "ID_AA64SMFR0_EL1",
 +              .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
 +                               R_ID_AA64SMFR0_B16F32_MASK |
 +                               R_ID_AA64SMFR0_F16F32_MASK |
 +                               R_ID_AA64SMFR0_I8I32_MASK |
 +                               R_ID_AA64SMFR0_F64F64_MASK |
 +                               R_ID_AA64SMFR0_I16I64_MASK |
 +                               R_ID_AA64SMFR0_FA64_MASK },
              { .name = "ID_AA64MMFR0_EL1",
 -              .fixed_bits    = 0x00000000ff000000 },
 -            { .name = "ID_AA64MMFR1_EL1"          },
 +              .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
 +              .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
 +                            (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
 +            { .name = "ID_AA64MMFR1_EL1",
 +              .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
 +            { .name = "ID_AA64MMFR2_EL1",
 +              .exported_bits = R_ID_AA64MMFR2_AT_MASK },
              { .name = "ID_AA64MMFR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64DFR0_EL1",
 -              .fixed_bits    = 0x0000000000000006 },
 -            { .name = "ID_AA64DFR1_EL1"           },
 +              .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
 +            { .name = "ID_AA64DFR1_EL1" },
              { .name = "ID_AA64DFR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64AFR*",
 -              .is_glob = true                     },
 +              .is_glob = true },
              { .name = "ID_AA64ISAR0_EL1",
 -              .exported_bits = 0x00fffffff0fffff0 },
 +              .exported_bits = R_ID_AA64ISAR0_AES_MASK |
 +                               R_ID_AA64ISAR0_SHA1_MASK |
 +                               R_ID_AA64ISAR0_SHA2_MASK |
 +                               R_ID_AA64ISAR0_CRC32_MASK |
 +                               R_ID_AA64ISAR0_ATOMIC_MASK |
 +                               R_ID_AA64ISAR0_RDM_MASK |
 +                               R_ID_AA64ISAR0_SHA3_MASK |
 +                               R_ID_AA64ISAR0_SM3_MASK |
 +                               R_ID_AA64ISAR0_SM4_MASK |
 +                               R_ID_AA64ISAR0_DP_MASK |
 +                               R_ID_AA64ISAR0_FHM_MASK |
 +                               R_ID_AA64ISAR0_TS_MASK |
 +                               R_ID_AA64ISAR0_RNDR_MASK },
              { .name = "ID_AA64ISAR1_EL1",
 -              .exported_bits = 0x000000f0ffffffff },
 +              .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
 +                               R_ID_AA64ISAR1_APA_MASK |
 +                               R_ID_AA64ISAR1_API_MASK |
 +                               R_ID_AA64ISAR1_JSCVT_MASK |
 +                               R_ID_AA64ISAR1_FCMA_MASK |
 +                               R_ID_AA64ISAR1_LRCPC_MASK |
 +                               R_ID_AA64ISAR1_GPA_MASK |
 +                               R_ID_AA64ISAR1_GPI_MASK |
 +                               R_ID_AA64ISAR1_FRINTTS_MASK |
 +                               R_ID_AA64ISAR1_SB_MASK |
 +                               R_ID_AA64ISAR1_BF16_MASK |
 +                               R_ID_AA64ISAR1_DGH_MASK |
 +                               R_ID_AA64ISAR1_I8MM_MASK },
 +            { .name = "ID_AA64ISAR2_EL1",
 +              .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
 +                               R_ID_AA64ISAR2_RPRES_MASK |
 +                               R_ID_AA64ISAR2_GPA3_MASK |
 +                               R_ID_AA64ISAR2_APA3_MASK },
              { .name = "ID_AA64ISAR*_EL1_RESERVED",
 -              .is_glob = true                     },
 +              .is_glob = true },
          };
          modify_arm_cp_regs(v8_idregs, v8_user_idregs);
  #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
  #ifdef CONFIG_USER_ONLY
          static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
              { .name = "MIDR_EL1",
 -              .exported_bits = 0x00000000ffffffff },
 -            { .name = "REVIDR_EL1"                },
 +              .exported_bits = R_MIDR_EL1_REVISION_MASK |
 +                               R_MIDR_EL1_PARTNUM_MASK |
 +                               R_MIDR_EL1_ARCHITECTURE_MASK |
 +                               R_MIDR_EL1_VARIANT_MASK |
 +                               R_MIDR_EL1_IMPLEMENTER_MASK },
 +            { .name = "REVIDR_EL1" },
          };
          modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
  #endif
 --
-.25.1
+.34.1

-[PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
+[PULL 17/35] tests/qtest: Fix GMAC test to run on a machine in upstream QEMU
-From: Gavin Shan <gshan@redhat.com>
+From: Nabih Estefan <nabihestefan@google.com>
-This renames variable 'size' to 'region_size' in virt_set_high_memmap().
+Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
-Its counterpart ('region_base') will be introduced in next patch.
+of 8xx. Also fix comments referencing this and values expecting 8xx.
-No functional change intended.
+Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
+Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
-Signed-off-by: Gavin Shan <gshan@redhat.com>
+Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20240208194759.2858582-2-nabihestefan@google.com
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Marc Zyngier <maz@kernel.org>
+[PMM: commit message tweaks]
 Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
 Message-id: 20221029224307.138822-3-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 15 ++++++++-------
+ tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
-file changed, 8 insertions(+), 7 deletions(-)
+ tests/qtest/meson.build      |  3 +-
 files changed, 4 insertions(+), 83 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/tests/qtest/npcm_gmac-test.c
-+++ b/hw/arm/virt.c
++++ b/tests/qtest/npcm_gmac-test.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
+@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
- static void virt_set_high_memmap(VirtMachineState *vms,
+     const GMACModule *module;
-                                  hwaddr base, int pa_bits)
+ } TestData;
 -/* Values extracted from hw/arm/npcm8xx.c */
 +/* Values extracted from hw/arm/npcm7xx.c */
  static const GMACModule gmac_module_list[] = {
      {
          .irq        = 14,
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
          .irq        = 15,
          .base_addr  = 0xf0804000
      },
 -    {
 -        .irq        = 16,
 -        .base_addr  = 0xf0806000
 -    },
 -    {
 -        .irq        = 17,
 -        .base_addr  = 0xf0808000
 -    }
  };
  /* Returns the index of the GMAC module. */
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
      return qtest_readl(qts, mod->base_addr + regno);
  }
 -static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
 -                          NPCMRegister regno)
 -{
 -    uint32_t write_value = (regno & 0x3ffe00) >> 9;
 -    qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
 -    uint32_t read_offset = regno & 0x1ff;
 -    return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
 -}
 -
  /* Check that GMAC registers are reset to default value */
  static void test_init(gconstpointer test_data)
  {
-+    hwaddr region_size;
+     const TestData *td = test_data;
-+    bool fits;
+     const GMACModule *mod = td->module;
-     int i;
+-    QTestState *qts = qtest_init("-machine npcm845-evb");
++    QTestState *qts = qtest_init("-machine npcm750-evb");
-     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
--        hwaddr size = extended_memmap[i].size;
+ #define CHECK_REG32(regno, value) \
--        bool fits;
+     do { \
-+        region_size = extended_memmap[i].size;
+         g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
+     } while (0)
--        base = ROUND_UP(base, size);
-+        base = ROUND_UP(base, region_size);
+-#define CHECK_REG_PCS(regno, value) \
-         vms->memmap[i].base = base;
+-    do { \
--        vms->memmap[i].size = size;
+-        g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
-+        vms->memmap[i].size = region_size;
+-    } while (0)
+-
-         /*
+     CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
-          * Check each device to see if they fit in the PA space,
+     CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
-@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
+     CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
-          *
+@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
-          * For each device that doesn't fit, disable it.
+     CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
-          */
+     CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
--        fits = (base + size) <= BIT_ULL(pa_bits);
-+        fits = (base + region_size) <= BIT_ULL(pa_bits);
+-    /* TODO Add registers PCS */
-         if (fits) {
+-    if (mod->base_addr == 0xf0802000) {
--            vms->highest_gpa = base + size - 1;
+-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
-+            vms->highest_gpa = base + region_size - 1;
+-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
-         }
+-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
+-
-         switch (i) {
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
-@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
-             break;
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
-         }
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
--        base += size;
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
-+        base += region_size;
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
-     }
+-        CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
 -
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
 -        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
 -
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
 -        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
 -    }
 -
      qtest_quit(qts);
  }
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/meson.build
++++ b/tests/qtest/meson.build
+@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
+    'npcm7xx_sdhci-test',
+    'npcm7xx_smbus-test',
+    'npcm7xx_timer-test',
+-   'npcm7xx_watchdog_timer-test'] + \
++   'npcm7xx_watchdog_timer-test',
++   'npcm_gmac-test'] + \
+    (slirp.found() ? ['npcm7xx_emc-test'] : [])
+ qtests_aspeed = \
+   ['aspeed_hace-test',
 --
-.25.1
+.34.1

-[PULL 01/29] hw/arm/virt: Introduce virt_set_high_memmap() helper
+[PULL 18/35] hw/arm/smmuv3: add support for stage 1 access fault
-From: Gavin Shan <gshan@redhat.com>
+From: Luc Michel <luc.michel@amd.com>
-This introduces virt_set_high_memmap() helper. The logic of high
+An access fault is raised when the Access Flag is not set in the
-memory region address assignment is moved to the helper. The intention
+looked-up PTE and the AFFD field is not set in the corresponding context
-is to make the subsequent optimization for high memory region address
+descriptor. This was already implemented for stage 2. Implement it for
-assignment easier.
+stage 1 as well.
-No functional change intended.
+Signed-off-by: Luc Michel <luc.michel@amd.com>
+Reviewed-by: Mostafa Saleh <smostafa@google.com>
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Reviewed-by: Cornelia Huck <cohuck@redhat.com>
+Tested-by: Mostafa Saleh <smostafa@google.com>
-Reviewed-by: Marc Zyngier <maz@kernel.org>
+Message-id: 20240213082211.3330400-1-luc.michel@amd.com
-Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
+[PMM: tweaked comment text]
 Message-id: 20221029224307.138822-2-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 74 ++++++++++++++++++++++++++++-----------------------
+ hw/arm/smmuv3-internal.h     |  1 +
-file changed, 41 insertions(+), 33 deletions(-)
+ include/hw/arm/smmu-common.h |  1 +
  hw/arm/smmu-common.c         | 11 +++++++++++
  hw/arm/smmuv3.c              |  1 +
 files changed, 14 insertions(+)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/hw/arm/smmuv3-internal.h
-+++ b/hw/arm/virt.c
++++ b/hw/arm/smmuv3-internal.h
-@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
+@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
-     return arm_cpu_mp_affinity(idx, clustersz);
+ #define CD_EPD(x, sel)   extract32((x)->word[0], (16 * (sel)) + 14, 1)
- }
+ #define CD_ENDI(x)       extract32((x)->word[0], 15, 1)
+ #define CD_IPS(x)        extract32((x)->word[1], 0 , 3)
-+static void virt_set_high_memmap(VirtMachineState *vms,
++#define CD_AFFD(x)       extract32((x)->word[1], 3 , 1)
-+                                 hwaddr base, int pa_bits)
+ #define CD_TBI(x)        extract32((x)->word[1], 6 , 2)
-+{
+ #define CD_HD(x)         extract32((x)->word[1], 10 , 1)
-+    int i;
+ #define CD_HA(x)         extract32((x)->word[1], 11 , 1)
-+
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
-+    for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+index XXXXXXX..XXXXXXX 100644
-+        hwaddr size = extended_memmap[i].size;
+--- a/include/hw/arm/smmu-common.h
-+        bool fits;
++++ b/include/hw/arm/smmu-common.h
-+
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
-+        base = ROUND_UP(base, size);
+     bool disabled;             /* smmu is disabled */
-+        vms->memmap[i].base = base;
+     bool bypassed;             /* translation is bypassed */
-+        vms->memmap[i].size = size;
+     bool aborted;              /* translation is aborted */
 +    bool affd;                 /* AF fault disable */
      uint32_t iotlb_hits;       /* counts IOTLB hits */
      uint32_t iotlb_misses;     /* counts IOTLB misses*/
      /* Used by stage-1 only. */
 diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/smmu-common.c
 +++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
                                       pte_addr, pte, iova, gpa,
                                       block_size >> 20);
          }
 +
 +        /*
-+         * Check each device to see if they fit in the PA space,
++         * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
-+         * moving highest_gpa as we go.
++         * are 0 we take an Access flag fault. (5.4. Context Descriptor)
-+         *
++         * An Access flag fault takes priority over a Permission fault.
 +         * For each device that doesn't fit, disable it.
 +         */
-+        fits = (base + size) <= BIT_ULL(pa_bits);
++        if (!PTE_AF(pte) && !cfg->affd) {
-+        if (fits) {
++            info->type = SMMU_PTW_ERR_ACCESS;
-+            vms->highest_gpa = base + size - 1;
++            goto error;
 +        }
 +
-+        switch (i) {
+         ap = PTE_AP(pte);
-+        case VIRT_HIGH_GIC_REDIST2:
+         if (is_permission_fault(ap, perm)) {
-+            vms->highmem_redists &= fits;
+             info->type = SMMU_PTW_ERR_PERMISSION;
-+            break;
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
-+        case VIRT_HIGH_PCIE_ECAM:
+index XXXXXXX..XXXXXXX 100644
-+            vms->highmem_ecam &= fits;
+--- a/hw/arm/smmuv3.c
-+            break;
++++ b/hw/arm/smmuv3.c
-+        case VIRT_HIGH_PCIE_MMIO:
+@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
-+            vms->highmem_mmio &= fits;
+     cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
-+            break;
+     cfg->tbi = CD_TBI(cd);
-+        }
+     cfg->asid = CD_ASID(cd);
-+
++    cfg->affd = CD_AFFD(cd);
-+        base += size;
-+    }
+     trace_smmuv3_decode_cd(cfg->oas);
-+}
 +
  static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
  {
      MachineState *ms = MACHINE(vms);
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
      /* We know for sure that at least the memory fits in the PA space */
      vms->highest_gpa = memtop - 1;
 -    for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
 -        hwaddr size = extended_memmap[i].size;
 -        bool fits;
 -
 -        base = ROUND_UP(base, size);
 -        vms->memmap[i].base = base;
 -        vms->memmap[i].size = size;
 -
 -        /*
 -         * Check each device to see if they fit in the PA space,
 -         * moving highest_gpa as we go.
 -         *
 -         * For each device that doesn't fit, disable it.
 -         */
 -        fits = (base + size) <= BIT_ULL(pa_bits);
 -        if (fits) {
 -            vms->highest_gpa = base + size - 1;
 -        }
 -
 -        switch (i) {
 -        case VIRT_HIGH_GIC_REDIST2:
 -            vms->highmem_redists &= fits;
 -            break;
 -        case VIRT_HIGH_PCIE_ECAM:
 -            vms->highmem_ecam &= fits;
 -            break;
 -        case VIRT_HIGH_PCIE_MMIO:
 -            vms->highmem_mmio &= fits;
 -            break;
 -        }
 -
 -        base += size;
 -    }
 +    virt_set_high_memmap(vms, base, pa_bits);
      if (device_memory_size > 0) {
          ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
 --
-.25.1
+.34.1

-[PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
+[PULL 19/35] hw/arm/stellaris: Convert ADC controller to Resettable interface
-Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20240213155214.13619-2-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_its.c | 14 +++++++++-----
+ hw/arm/stellaris.c | 6 ++++--
-file changed, 9 insertions(+), 5 deletions(-)
+file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_its.c
+--- a/hw/arm/stellaris.c
-+++ b/hw/intc/arm_gicv3_its.c
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
  struct GICv3ITSClass {
      GICv3ITSCommonClass parent_class;
 -    void (*parent_reset)(DeviceState *dev);
 +    ResettablePhases parent_phases;
  };
  /*
@@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
      }
  }
--static void gicv3_its_reset(DeviceState *dev)
+-static void stellaris_adc_reset(StellarisADCState *s)
-+static void gicv3_its_reset_hold(Object *obj)
++static void stellaris_adc_reset_hold(Object *obj)
  {
--    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
++    StellarisADCState *s = STELLARIS_ADC(obj);
-+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
+     int n;
-     GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
+     for (n = 0; n < 4; n++) {
--    c->parent_reset(dev);
+@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
-+    if (c->parent_phases.hold) {
+     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
-+        c->parent_phases.hold(obj);
+                           "adc", 0x1000);
-+    }
+     sysbus_init_mmio(sbd, &s->iomem);
+-    stellaris_adc_reset(s);
-     /* Quiescent bit reset to 1 */
+     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
-     s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
+ }
-@@ -XXX,XX +XXX,XX @@ static Property gicv3_its_props[] = {
- static void gicv3_its_class_init(ObjectClass *klass, void *data)
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
  static void stellaris_adc_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
-     GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
-     GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
++    rc->phases.hold = stellaris_adc_reset_hold;
+     dc->vmsd = &vmstate_stellaris_adc;
      dc->realize = gicv3_arm_its_realize;
      device_class_set_props(dc, gicv3_its_props);
 -    device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
 +    resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL,
 +                                       &ic->parent_phases);
      icc->post_load = gicv3_its_post_load;
  }
 --
-.25.1
+.34.1

-[PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
+[PULL 20/35] hw/arm/stellaris: Convert I2C controller to Resettable interface
-Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20240213155214.13619-3-philmd@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_its_common.c | 7 ++++---
+ hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 22 insertions(+), 4 deletions(-)
-diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_its_common.c
+--- a/hw/arm/stellaris.c
-+++ b/hw/intc/arm_gicv3_its_common.c
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
+@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
-     msi_nonbroken = true;
+     s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
  }
--static void gicv3_its_common_reset(DeviceState *dev)
+-/* I2C controller.  */
-+static void gicv3_its_common_reset_hold(Object *obj)
++/*
 + * I2C controller.
 + * ??? For now we only implement the master interface.
 + */
  #define TYPE_STELLARIS_I2C "stellaris-i2c"
  OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
      stellaris_i2c_update(s);
  }
 -static void stellaris_i2c_reset(stellaris_i2c_state *s)
 +static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
  {
--    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
++    stellaris_i2c_state *s = STELLARIS_I2C(obj);
-+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
++
+     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
-     s->ctlr = 0;
+         i2c_end_transfer(s->bus);
-     s->cbaser = 0;
++}
-@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
++
- static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
++static void stellaris_i2c_reset_hold(Object *obj)
 +{
 +    stellaris_i2c_state *s = STELLARIS_I2C(obj);
      s->msa = 0;
      s->mcs = 0;
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
      s->mimr = 0;
      s->mris = 0;
      s->mcr = 0;
 +}
 +
 +static void stellaris_i2c_reset_exit(Object *obj)
 +{
 +    stellaris_i2c_state *s = STELLARIS_I2C(obj);
 +
      stellaris_i2c_update(s);
  }
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
      memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
                            "i2c", 0x1000);
      sysbus_init_mmio(sbd, &s->iomem);
 -    /* ??? For now we only implement the master interface.  */
 -    stellaris_i2c_reset(s);
  }
  /* Analogue to Digital Converter.  This is only partially implemented,
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
  static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
--    dc->reset = gicv3_its_common_reset;
++    rc->phases.enter = stellaris_i2c_reset_enter;
-+    rc->phases.hold = gicv3_its_common_reset_hold;
++    rc->phases.hold = stellaris_i2c_reset_hold;
-     dc->vmsd = &vmstate_its;
++    rc->phases.exit = stellaris_i2c_reset_exit;
      dc->vmsd = &vmstate_stellaris_i2c;
  }
 --
-.25.1
+.34.1

-[PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
+[PULL 21/35] hw/arm/stellaris: Add missing QOM 'machine' parent
 From: Philippe Mathieu-Daudé <philmd@linaro.org>
-When building with --disable-tcg on Darwin we get:
+QDev objects created with qdev_new() need to manually add
 their parent relationship with object_property_add_child().
-  target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps'
+This commit plug the devices which aren't part of the SoC;
-    cc->tcg_ops->do_interrupt(cs);
+they will be plugged into a SoC container in the next one.
     ~~~~~~~~~~~^
 Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
 handler to sysemu") limited this block to system emulation,
 but neglected to also limit it to TCG.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20221209110823.59495-1-philmd@linaro.org
+Message-id: 20240213155214.13619-4-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c | 5 +++--
+ hw/arm/stellaris.c | 4 ++++
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 4 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/arm/stellaris.c
-+++ b/target/arm/cpu.c
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-     arm_rebuild_hflags(env);
+                                    &error_fatal);
- }
+             ssddev = qdev_new("ssd0323");
--#ifndef CONFIG_USER_ONLY
++            object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
-+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+             qdev_prop_set_uint8(ssddev, "cs", 1);
+             qdev_realize_and_unref(ssddev, bus, &error_fatal);
- static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
-                                      unsigned int target_el,
+             gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
-@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
++            object_property_add_child(OBJECT(ms), "splitter",
-     cc->tcg_ops->do_interrupt(cs);
++                                      OBJECT(gpio_d_splitter));
-     return true;
+             qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
- }
+             qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
--#endif /* !CONFIG_USER_ONLY */
+             qdev_connect_gpio_out(
-+
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+         DeviceState *gpad;
- void arm_cpu_update_virq(ARMCPU *cpu)
+         gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
- {
++        object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
          for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
              qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
          }
 --
-.25.1
+.34.1

-[PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss
+[PULL 22/35] hw/arm/stellaris: Add missing QOM 'SoC' parent
-From: Thomas Huth <thuth@redhat.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
+QDev objects created with qdev_new() need to manually add
-poisoned in common code, so the files that include this header have to
+their parent relationship with object_property_add_child().
 be added to specific_ss and recompiled for each, qemu-system-arm and
 qemu-system-aarch64. However, since the kvm headers are only optionally
 used in kvm-constants.h for some sanity checks, we can additionally
 check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro,
 so kvm-constants.h can also be used from "common" files (without the
 sanity checks - which should be OK since they are still done from other
 target-specific files instead). This way, and by adjusting some other
 include statements in the related files here and there, we can move some
 files from specific_ss into softmmu_ss, so that they only need to be
 compiled once during the build process.
-Signed-off-by: Thomas Huth <thuth@redhat.com>
+Since we don't model the SoC, just use a QOM container.
-Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221202154023.293614-1-thuth@redhat.com
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20240213155214.13619-5-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/misc/xlnx-zynqmp-apu-ctrl.h |  2 +-
+ hw/arm/stellaris.c | 11 ++++++++++-
- target/arm/kvm-consts.h                |  8 ++++----
+file changed, 10 insertions(+), 1 deletion(-)
  hw/misc/imx6_src.c                     |  2 +-
  hw/misc/iotkit-sysctl.c                |  1 -
  hw/misc/meson.build                    | 11 +++++------
 files changed, 11 insertions(+), 13 deletions(-)
-diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
+--- a/hw/arm/stellaris.c
-+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
+      * 400fe000 system control
- #include "hw/sysbus.h"
+      */
- #include "hw/register.h"
--#include "target/arm/cpu.h"
++    Object *soc_container;
-+#include "target/arm/cpu-qom.h"
+     DeviceState *gpio_dev[7], *nvic;
+     qemu_irq gpio_in[7][8];
- #define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
+     qemu_irq gpio_out[7][8];
- OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
+     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
-index XXXXXXX..XXXXXXX 100644
+     sram_size = ((board->dc0 >> 18) + 1) * 1024;
---- a/target/arm/kvm-consts.h
-+++ b/target/arm/kvm-consts.h
++    soc_container = object_new("container");
-@@ -XXX,XX +XXX,XX @@
++    object_property_add_child(OBJECT(ms), "soc", soc_container);
- #ifndef ARM_KVM_CONSTS_H
++
- #define ARM_KVM_CONSTS_H
+     /* Flash programming is done via the SCU, so pretend it is ROM.  */
+     memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
-+#ifdef NEED_CPU_H
+                            &error_fatal);
- #ifdef CONFIG_KVM
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
- #include <linux/kvm.h>
+      * need its sysclk output.
- #include <linux/psci.h>
+      */
      ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
 +    object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
      /*
       * Most devices come preprogrammed with a MAC address in the user data.
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
      sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
      nvic = qdev_new(TYPE_ARMV7M);
 +    object_property_add_child(soc_container, "v7m", OBJECT(nvic));
      qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
      qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
      qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
              dev = qdev_new(TYPE_STELLARIS_GPTM);
              sbd = SYS_BUS_DEVICE(dev);
 +            object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
              qdev_connect_clock_in(dev, "clk",
                                    qdev_get_clock_out(ssys_dev, "SYSCLK"));
              sysbus_realize_and_unref(sbd, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
      if (board->dc1 & (1 << 3)) { /* watchdog present */
          dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
 -
- #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
++        object_property_add_child(soc_container, "wdg", OBJECT(dev));
-+#endif
+         qdev_connect_clock_in(dev, "WDOGCLK",
-+#endif
+                               qdev_get_clock_out(ssys_dev, "SYSCLK"));
--#else
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
--
+             SysBusDevice *sbd;
-+#ifndef MISMATCH_CHECK
- #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
+             dev = qdev_new("pl011_luminary");
--
++            object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
- #endif
+             sbd = SYS_BUS_DEVICE(dev);
+             qdev_prop_set_chr(dev, "chardev", serial_hd(i));
- #define CP_REG_SIZE_SHIFT 52
+             sysbus_realize_and_unref(sbd, &error_fatal);
-diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-index XXXXXXX..XXXXXXX 100644
+         DeviceState *enet;
---- a/hw/misc/imx6_src.c
-+++ b/hw/misc/imx6_src.c
+         enet = qdev_new("stellaris_enet");
-@@ -XXX,XX +XXX,XX @@
++        object_property_add_child(soc_container, "enet", OBJECT(enet));
- #include "qemu/log.h"
+         if (nd) {
- #include "qemu/main-loop.h"
+             qdev_set_nic_properties(enet, nd);
- #include "qemu/module.h"
+         } else {
 -#include "arm-powerctl.h"
 +#include "target/arm/arm-powerctl.h"
  #include "hw/core/cpu.h"
  #ifndef DEBUG_IMX6_SRC
 diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/iotkit-sysctl.c
 +++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/qdev-properties.h"
  #include "hw/arm/armsse-version.h"
  #include "target/arm/arm-powerctl.h"
 -#include "target/arm/cpu.h"
  REG32(SECDBGSTAT, 0x0)
  REG32(SECDBGSET, 0x4)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
    'imx25_ccm.c',
    'imx31_ccm.c',
    'imx6_ccm.c',
 +  'imx6_src.c',
    'imx6ul_ccm.c',
    'imx7_ccm.c',
    'imx7_gpr.c',
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
  ))
  softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
  softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
 -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
 -specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
 +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
 +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
  specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
  softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
    'xlnx-versal-xramc.c',
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c'))
  softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
  softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
  softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
 +softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
  softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
  softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
  softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
  specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
 -specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c'))
 -specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
 -
  specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
  specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
  specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
 -specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
 +softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
  # HPPA devices
  softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
 --
-.25.1
+.34.1

-[PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps
+[PULL 23/35] target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
-For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
+We support two different encodings for the AArch32 IMPDEF
-registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
+CBAR register -- older cores like the Cortex A9, A7, A15
-their AArch32 equivalents).  This is a subset of the registers
+have this at 4, c15, c0, 0; newer cores like the
-trapped by HCR_EL2.TID2, which includes all of these and also the
+Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.
 CTR_EL0 register.
-Our implementation already uses a separate access function for
+When we implemented this we picked which encoding to
-CTR_EL0 (ctr_el0_access()), so all of the registers currently using
+use based on whether the CPU set ARM_FEATURE_AARCH64.
-access_aa64_tid2() should also be checking TID4.  Make that function
+However this isn't right for three cases:
-check both TID2 and TID4, and rename it appropriately.
+ * the qemu-system-arm 'max' CPU, which is supposed to be
    a variant on a Cortex-A57; it ought to use the same
    encoding the A57 does and which the AArch64 'max'
    exposes to AArch32 guest code
  * the Cortex-R52, which is AArch32-only but has the CBAR
    at the newer encoding (and where we incorrectly are
    not yet setting ARM_FEATURE_CBAR_RO anyway)
  * any possible future support for other v8 AArch32
    only CPUs, or for supporting "boot the CPU into
    AArch32 mode" on our existing cores like the A57 etc
 Make the decision of the encoding be based on whether
 the CPU implements the ARM_FEATURE_V8 flag instead.
 This changes the behaviour only for the qemu-system-arm
 '-cpu max'. We don't expect anybody to be relying on the
 old behaviour because:
  * it's not what the real hardware Cortex-A57 does
    (and that's what our ID register claims we are)
  * we don't implement the memory-mapped GICv3 support
    which is the only thing that exists at the peripheral
    base address pointed to by the register
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 17 +++++++++--------
+ target/arm/helper.c | 2 +-
-file changed, 9 insertions(+), 8 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
-     scr_write(env, ri, 0);
- }
--static CPAccessResult access_aa64_tid2(CPUARMState *env,
--                                       const ARMCPRegInfo *ri,
--                                       bool isread)
-+static CPAccessResult access_tid4(CPUARMState *env,
-+                                  const ARMCPRegInfo *ri,
-+                                  bool isread)
- {
--    if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
-+    if (arm_current_el(env) == 1 &&
-+        (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
-         return CP_ACCESS_TRAP_EL2;
-     }
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
-     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
-       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
-       .access = PL1_R,
--      .accessfn = access_aa64_tid2,
-+      .accessfn = access_tid4,
-       .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
-     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
-       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
-       .access = PL1_RW,
--      .accessfn = access_aa64_tid2,
-+      .accessfn = access_tid4,
-       .writefn = csselr_write, .resetvalue = 0,
-       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
-                              offsetof(CPUARMState, cp15.csselr_ns) } },
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
-     { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
-       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
-       .access = PL1_R,
--      .accessfn = access_aa64_tid2,
-+      .accessfn = access_tid4,
-       .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
- };
 @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
+          * AArch64 cores we might need to add a specific feature flag
-             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
+          * to indicate cores with "flavour 2" CBAR.
-             .access = PL1_R, .type = ARM_CP_CONST,
+          */
--            .accessfn = access_aa64_tid2,
+-        if (arm_feature(env, ARM_FEATURE_AARCH64)) {
-+            .accessfn = access_tid4,
++        if (arm_feature(env, ARM_FEATURE_V8)) {
-             .resetvalue = cpu->clidr
+             /* 32 bit view is [31:18] 0...0 [43:32]. */
-         };
+             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
-         define_one_arm_cp_reg(cpu, &clidr);
+                 | extract64(cpu->reset_cbar, 32, 12);
 --
-.25.1
+.34.1

-[PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max'
+[PULL 24/35] target/arm: The Cortex-R52 has a read-only CBAR
-Update the ID registers for TCG's '-cpu max' to report the
+The Cortex-R52 implements the Configuration Base Address Register
-FEAT_EVT Enhanced Virtualization Traps support.
+(CBAR), as a read-only register.  Add ARM_FEATURE_CBAR_RO to this CPU
 type, so that our implementation provides the register and the
 associated qdev property.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
 ---
- docs/system/arm/emulation.rst | 1 +
+ target/arm/tcg/cpu32.c | 1 +
- target/arm/cpu64.c            | 1 +
+file changed, 1 insertion(+)
  target/arm/cpu_tcg.c          | 1 +
 files changed, 3 insertions(+)
-diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/emulation.rst
+--- a/target/arm/tcg/cpu32.c
-+++ b/docs/system/arm/emulation.rst
++++ b/target/arm/tcg/cpu32.c
-@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
- - FEAT_DoubleFault (Double Fault Extension)
+     set_feature(&cpu->env, ARM_FEATURE_PMSA);
- - FEAT_E0PD (Preventing EL0 access to halves of address maps)
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
- - FEAT_ETS (Enhanced Translation Synchronization)
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-+- FEAT_EVT (Enhanced Virtualization Traps)
++    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- - FEAT_FCMA (Floating-point complex number instructions)
+     cpu->midr = 0x411fd133; /* r1p3 */
- - FEAT_FHM (Floating-point half-precision multiplication instructions)
+     cpu->revidr = 0x00000000;
- - FEAT_FP16 (Half-precision floating-point data processing)
+     cpu->reset_fpsid = 0x41034023;
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1);      /* FEAT_S2FWB */
      t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
      t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
 +    t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2);      /* FEAT_EVT */
      t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
      cpu->isar.id_aa64mmfr2 = t;
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
      t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
      t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
      t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
 +    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
      cpu->isar.id_mmfr4 = t;
      t = cpu->isar.id_mmfr5;
 --
-.25.1
+.34.1

-[PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps
+[PULL 25/35] target/arm: Add Cortex-R52 IMPDEF sysregs
-For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
+Add the Cortex-R52 IMPDEF sysregs, by defining them here and
-TLB maintenance instructions that operate on the inner shareable
+also by enabling the AUXCR feature which defines the ACTLR
-domain:
+and HACTLR registers. As is our usual practice, we make these
+simple reads-as-zero stubs for now.
 AArch64:
  TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
  TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
  TLBI RVALE1IS, and TLBI RVAALE1IS.
 AArch32:
  TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
  and TLBIMVAALIS.
 Add the trapping support.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 43 +++++++++++++++++++++++++++----------------
+ target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
-file changed, 27 insertions(+), 16 deletions(-)
+file changed, 108 insertions(+)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/tcg/cpu32.c
-+++ b/target/arm/helper.c
++++ b/target/arm/tcg/cpu32.c
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
-     return CP_ACCESS_OK;
+     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
  }
-+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
++static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
-+static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
++    { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
-+                                    bool isread)
++      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
-+{
++    { .name = "IMP_ATCMREGIONR",
-+    if (arm_current_el(env) == 1 &&
++      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
-+        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+        return CP_ACCESS_TRAP_EL2;
++    { .name = "IMP_BTCMREGIONR",
-+    }
++      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
-+    return CP_ACCESS_OK;
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-+}
++    { .name = "IMP_CTCMREGIONR",
 +      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_CSCTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_BPCTLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_MEMPROTCLR",
 +      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_SLAVEPCTLR",
 +      .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_PERIPHREGIONR",
 +      .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_FLASHIFREGIONR",
 +      .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_BUILDOPTR",
 +      .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_PINOPTR",
 +      .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_QOSR",
 +      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_BUSTIMEOUTR",
 +      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_INTMONR",
 +      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_ICERR0",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_ICERR1",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_DCERR0",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_DCERR1",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TCMERR0",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TCMERR1",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TCMSYNDR0",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TCMSYNDR1",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_FLASHERR0",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_FLASHERR1",
 +      .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_CDBGDR0",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_CBDGBR1",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TESTR0",
 +      .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
 +      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 +    { .name = "IMP_TESTR1",
 +      .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +    { .name = "IMP_CDBGDCI",
 +      .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +    { .name = "IMP_CDBGDCT",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +    { .name = "IMP_CDBGICT",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +    { .name = "IMP_CDBGDCD",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +    { .name = "IMP_CDBGICD",
 +      .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
 +      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
 +};
 +
- static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++
  static void cortex_r52_initfn(Object *obj)
  {
-     ARMCPU *cpu = env_archcpu(env);
+     ARMCPU *cpu = ARM_CPU(obj);
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
+@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
- static const ARMCPRegInfo v7mp_cp_reginfo[] = {
+     set_feature(&cpu->env, ARM_FEATURE_NEON);
-     /* 32 bit TLB invalidates, Inner Shareable */
+     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
-     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
+     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
--      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
++    set_feature(&cpu->env, ARM_FEATURE_AUXCR);
-+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
+     cpu->midr = 0x411fd133; /* r1p3 */
-       .writefn = tlbiall_is_write },
+     cpu->revidr = 0x00000000;
-     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
+     cpu->reset_fpsid = 0x41034023;
--      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
-+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
-       .writefn = tlbimva_is_write },
+     cpu->pmsav7_dregion = 16;
-     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
+     cpu->pmsav8r_hdregion = 16;
--      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
++
-+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
++    define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
-       .writefn = tlbiasid_is_write },
+ }
-     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
--      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+ static void cortex_r5f_initfn(Object *obj)
 +      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
        .writefn = tlbimvaa_is_write },
  };
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
      /* TLBI operations */
      { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
  #endif
      /* TLB invalidate last level of translation table walk */
      { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
 -      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
 +      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
        .writefn = tlbimva_is_write },
      { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
 -      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
 +      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
        .writefn = tlbimvaa_is_write },
      { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
        .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
  static const ARMCPRegInfo tlbirange_reginfo[] = {
      { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
 -      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1is_write },
      { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
 --
-.25.1
+.34.1

-[PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps
+[PULL 26/35] target/arm: Allow access to SPSR_hyp from hyp mode
-For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
+Architecturally, the AArch32 MSR/MRS to/from banked register
-and IC IALLUIS cache maintenance instructions.
+instructions are UNPREDICTABLE for attempts to access a banked
 register that the guest could access in a more direct way (e.g.
 using this insn to access r8_fiq when already in FIQ mode).  QEMU has
 chosen to UNDEF on all of these.
-The HCR_EL2.TOCU bit traps all the other cache maintenance
+However, for the case of accessing SPSR_hyp from hyp mode, it turns
-instructions that operate to the point of unification:
+out that real hardware permits this, with the same effect as if the
- AArch64 IC IVAU, IC IALLU, DC CVAU
+guest had directly written to SPSR. Further, there is some
- AArch32 ICIMVAU, ICIALLU, DCCMVAU
+guest code out there that assumes it can do this, because it
 happens to work on hardware: an example Cortex-R52 startup code
 fragment uses this, and it got copied into various other places,
 including Zephyr. Zephyr was fixed to not use this:
  https://github.com/zephyrproject-rtos/zephyr/issues/47330
 but other examples are still out there, like the selftest
 binary for the MPS3-AN536.
-The two trap bits between them cover all of the cache maintenance
+For convenience of being able to run guest code, permit
-instructions which must also check the HCR_TPU flag.  Turn the old
+this UNPREDICTABLE access instead of UNDEFing it.
 aa64_cacheop_pou_access() function into a helper function which takes
 the set of HCR_EL2 flags to check as an argument, and call it from
 new access_ticab() and access_tocu() functions as appropriate for
 each cache op.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 36 +++++++++++++++++++++++-------------
+ target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
-file changed, 23 insertions(+), 13 deletions(-)
+ target/arm/tcg/translate.c | 19 +++++++++++------
 files changed, 43 insertions(+), 19 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/target/arm/tcg/op_helper.c
-+++ b/target/arm/helper.c
++++ b/target/arm/tcg/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
-     return CP_ACCESS_OK;
+      */
- }
+     int curmode = env->uncached_cpsr & CPSR_M;
--static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
+-    if (regno == 17) {
--                                              const ARMCPRegInfo *ri,
+-        /* ELR_Hyp: a special case because access from tgtmode is OK */
--                                              bool isread)
+-        if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
-+static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
+-            goto undef;
- {
++    if (tgtmode == ARM_CPU_MODE_HYP) {
-     /* Cache invalidate/clean to Point of Unification... */
++        /*
-     switch (arm_current_el(env)) {
++         * Handle Hyp target regs first because some are special cases
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
++         * which don't want the usual "not accessible from tgtmode" check.
 +         */
 +        switch (regno) {
 +        case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
 +            if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
 +                goto undef;
 +            }
 +            break;
 +        case 13:
 +            if (curmode != ARM_CPU_MODE_MON) {
 +                goto undef;
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
-         /* fall through */
+         return;
-     case 1:
+     }
--        /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set.  */
+@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
--        if (arm_hcr_el2_eff(env) & HCR_TPU) {
+         }
-+        /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set.  */
+     }
-+        if (arm_hcr_el2_eff(env) & hcrflags) {
-             return CP_ACCESS_TRAP_EL2;
+-    if (tgtmode == ARM_CPU_MODE_HYP) {
 -        /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
 -        if (curmode != ARM_CPU_MODE_MON) {
 -            goto undef;
 -        }
 -    }
 -
      return;
  undef:
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
      switch (regno) {
      case 16: /* SPSRs */
 -        env->banked_spsr[bank_number(tgtmode)] = value;
 +        if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
 +            /* Only happens for SPSR_Hyp access in Hyp mode */
 +            env->spsr = value;
 +        } else {
 +            env->banked_spsr[bank_number(tgtmode)] = value;
 +        }
          break;
      case 17: /* ELR_Hyp */
          env->elr_el[2] = value;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
      switch (regno) {
      case 16: /* SPSRs */
 -        return env->banked_spsr[bank_number(tgtmode)];
 +        if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
 +            /* Only happens for SPSR_Hyp access in Hyp mode */
 +            return env->spsr;
 +        } else {
 +            return env->banked_spsr[bank_number(tgtmode)];
 +        }
      case 17: /* ELR_Hyp */
          return env->elr_el[2];
      case 13:
 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate.c
 +++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
          break;
      case ARM_CPU_MODE_HYP:
          /*
 -         * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
 -         * (and so we can forbid accesses from EL2 or below). elr_hyp
 -         * can be accessed also from Hyp mode, so forbid accesses from
 -         * EL0 or EL1.
 +         * r13_hyp can only be accessed from Monitor mode, and so we
 +         * can forbid accesses from EL2 or below.
 +         * elr_hyp can be accessed also from Hyp mode, so forbid
 +         * accesses from EL0 or EL1.
 +         * SPSR_hyp is supposed to be in the same category as r13_hyp
 +         * and UNPREDICTABLE if accessed from anything except Monitor
 +         * mode. However there is some real-world code that will do
 +         * it because at least some hardware happens to permit the
 +         * access. (Notably a standard Cortex-R52 startup code fragment
 +         * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
 +         * this (incorrect) guest code to run.
           */
 -        if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
 -            (s->current_el < 3 && *regno != 17)) {
 +        if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
 +            || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
              goto undef;
          }
          break;
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
-     return CP_ACCESS_OK;
- }
-+static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
-+                                   bool isread)
-+{
-+    return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
-+}
-+
-+static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
-+                                  bool isread)
-+{
-+    return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
-+}
-+
- /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
-  * Page D4-1736 (DDI0487A.b)
-  */
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-       .access = PL1_W, .type = ARM_CP_NOP,
--      .accessfn = aa64_cacheop_pou_access },
-+      .accessfn = access_ticab },
-     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
-       .access = PL1_W, .type = ARM_CP_NOP,
--      .accessfn = aa64_cacheop_pou_access },
-+      .accessfn = access_tocu },
-     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
-       .access = PL0_W, .type = ARM_CP_NOP,
--      .accessfn = aa64_cacheop_pou_access },
-+      .accessfn = access_tocu },
-     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
-       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
-       .access = PL0_W, .type = ARM_CP_NOP,
--      .accessfn = aa64_cacheop_pou_access },
-+      .accessfn = access_tocu },
-     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
-       .access = PL0_W, .type = ARM_CP_NOP,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .writefn = tlbiipas2is_hyp_write },
-     /* 32 bit cache operations */
-     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
--      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
-     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
-       .type = ARM_CP_NOP, .access = PL1_W },
-     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
--      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
-     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
--      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
-     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
-       .type = ARM_CP_NOP, .access = PL1_W },
-     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
-       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
-     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
--      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
-     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
-       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
-     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
 --
-.25.1
+.34.1

-[PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
+[PULL 27/35] hw/misc/mps2-scc: Fix condition for CFG3 register
-Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset.  This is a
+We currently guard the CFG3 register read with
-simple no-behaviour-change conversion.
+ (scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
 which is clearly wrong as it is never true.
+This register is present on all board types except AN524
+and AN527; correct the condition.
+Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org
+Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
 ---
- hw/intc/arm_gic_common.c | 7 ++++---
+ hw/misc/mps2-scc.c | 2 +-
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
+diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic_common.c
+--- a/hw/misc/mps2-scc.c
-+++ b/hw/intc/arm_gic_common.c
++++ b/hw/misc/mps2-scc.c
-@@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
+@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
-     }
+         r = s->cfg2;
- }
+         break;
+     case A_CFG3:
--static void arm_gic_common_reset(DeviceState *dev)
+-        if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
-+static void arm_gic_common_reset_hold(Object *obj)
++        if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
- {
+             /* CFG3 reserved on AN524 */
--    GICState *s = ARM_GIC_COMMON(dev);
+             goto bad_offset;
-+    GICState *s = ARM_GIC_COMMON(obj);
+         }
      int i, j;
      int resetprio;
@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {
  static void arm_gic_common_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
      ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 -    dc->reset = arm_gic_common_reset;
 +    rc->phases.hold = arm_gic_common_reset_hold;
      dc->realize = arm_gic_common_realize;
      device_class_set_props(dc, arm_gic_common_properties);
      dc->vmsd = &vmstate_gic;
 --
-.25.1
+.34.1

-[PULL 07/29] hw/arm/virt: Add properties to disable high memory regions
+[PULL 28/35] hw/misc/mps2-scc: Factor out which-board conditionals
-From: Gavin Shan <gshan@redhat.com>
+The MPS SCC device has a lot of different flavours for the various
 different MPS FPGA images, which look mostly similar but have
 differences in how particular registers are handled.  Currently we
 deal with this with a lot of open-coded checks on scc_partno(), but
 as we add more board types this is getting a bit hard to read.
-The 3 high memory regions are usually enabled by default, but they may
+Factor out the conditions into some functions which we can
-be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
+give more descriptive names to.
 This leads to waste in the PA space.
-Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-allow users selectively disable them if needed. After that, the high
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-memory region for GICv3 or GICv4 redistributor can be disabled by user,
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-the number of maximal supported CPUs needs to be calculated based on
+Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
-'vms->highmem_redists'. The follow-up error message is also improved
+---
-to indicate if the high memory region for GICv3 and GICv4 has been
+ hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
-enabled or not.
+file changed, 31 insertions(+), 14 deletions(-)
-Suggested-by: Marc Zyngier <maz@kernel.org>
+diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
 Signed-off-by: Gavin Shan <gshan@redhat.com>
 Reviewed-by: Marc Zyngier <maz@kernel.org>
 Reviewed-by: Cornelia Huck <cohuck@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20221029224307.138822-8-gshan@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  docs/system/arm/virt.rst | 13 +++++++
  hw/arm/virt.c            | 75 ++++++++++++++++++++++++++++++++++++++--
 files changed, 86 insertions(+), 2 deletions(-)
 diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/virt.rst
+--- a/hw/misc/mps2-scc.c
-+++ b/docs/system/arm/virt.rst
++++ b/hw/misc/mps2-scc.c
-@@ -XXX,XX +XXX,XX @@ compact-highmem
+@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
-   Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
+     return extract32(s->id, 4, 8);
    The default is ``on`` for machine types later than ``virt-7.2``.
 +highmem-redists
 +  Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
 +  GICv4 redistributor. The default is ``on``. Setting this to ``off`` will
 +  limit the maximum number of CPUs when GICv3 or GICv4 is used.
 +
 +highmem-ecam
 +  Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
 +  The default is ``on`` for machine types later than ``virt-3.0``.
 +
 +highmem-mmio
 +  Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
 +  The default is ``on``.
 +
  gic-version
    Specify the version of the Generic Interrupt Controller (GIC) to provide.
    Valid values are:
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
      if (vms->gic_version == VIRT_GIC_VERSION_2) {
          virt_max_cpus = GIC_NCPU;
      } else {
 -        virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
 -            virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
 +        virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
 +        if (vms->highmem_redists) {
 +            virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
 +        }
      }
      if (max_cpus > virt_max_cpus) {
          error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
                       "supported by machine 'mach-virt' (%d)",
                       max_cpus, virt_max_cpus);
 +        if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
 +            error_printf("Try 'highmem-redists=on' for more CPUs\n");
 +        }
 +
          exit(1);
      }
@@ -XXX,XX +XXX,XX @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
      vms->highmem_compact = value;
  }
-+static bool virt_get_highmem_redists(Object *obj, Error **errp)
++/* Is CFG_REG2 present? */
 +static bool have_cfg2(MPS2SCC *s)
 +{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
 +
 +    return vms->highmem_redists;
 +}
 +
-+static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
++/* Is CFG_REG3 present? */
 +static bool have_cfg3(MPS2SCC *s)
 +{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
 +
 +    vms->highmem_redists = value;
 +}
 +
-+static bool virt_get_highmem_ecam(Object *obj, Error **errp)
++/* Is CFG_REG5 present? */
 +static bool have_cfg5(MPS2SCC *s)
 +{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
 +
 +    return vms->highmem_ecam;
 +}
 +
-+static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
++/* Is CFG_REG6 present? */
 +static bool have_cfg6(MPS2SCC *s)
 +{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++    return scc_partno(s) == 0x524;
 +
 +    vms->highmem_ecam = value;
 +}
 +
-+static bool virt_get_highmem_mmio(Object *obj, Error **errp)
+ /* Handle a write via the SYS_CFG channel to the specified function/device.
-+{
+  * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
+  */
-+
+@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
-+    return vms->highmem_mmio;
+         r = s->cfg1;
-+}
+         break;
-+
+     case A_CFG2:
-+static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
+-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-+{
+-            /* CFG2 reserved on other boards */
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
++        if (!have_cfg2(s)) {
-+
+             goto bad_offset;
-+    vms->highmem_mmio = value;
+         }
-+}
+         r = s->cfg2;
-+
+         break;
-+
+     case A_CFG3:
- static bool virt_get_its(Object *obj, Error **errp)
+-        if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
- {
+-            /* CFG3 reserved on AN524 */
-     VirtMachineState *vms = VIRT_MACHINE(obj);
++        if (!have_cfg3(s)) {
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+             goto bad_offset;
-                                           "Set on/off to enable/disable compact "
+         }
-                                           "layout for high memory regions");
+         /* These are user-settable DIP switches on the board. We don't
+@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
-+    object_class_property_add_bool(oc, "highmem-redists",
+         r = s->cfg4;
-+                                   virt_get_highmem_redists,
+         break;
-+                                   virt_set_highmem_redists);
+     case A_CFG5:
-+    object_class_property_set_description(oc, "highmem-redists",
+-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-+                                          "Set on/off to enable/disable high "
+-            /* CFG5 reserved on other boards */
-+                                          "memory region for GICv3 or GICv4 "
++        if (!have_cfg5(s)) {
-+                                          "redistributor");
+             goto bad_offset;
-+
+         }
-+    object_class_property_add_bool(oc, "highmem-ecam",
+         r = s->cfg5;
-+                                   virt_get_highmem_ecam,
+         break;
-+                                   virt_set_highmem_ecam);
+     case A_CFG6:
-+    object_class_property_set_description(oc, "highmem-ecam",
+-        if (scc_partno(s) != 0x524) {
-+                                          "Set on/off to enable/disable high "
+-            /* CFG6 reserved on other boards */
-+                                          "memory region for PCI ECAM");
++        if (!have_cfg6(s)) {
-+
+             goto bad_offset;
-+    object_class_property_add_bool(oc, "highmem-mmio",
+         }
-+                                   virt_get_highmem_mmio,
+         r = s->cfg6;
-+                                   virt_set_highmem_mmio);
+@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
-+    object_class_property_set_description(oc, "highmem-mmio",
+         }
-+                                          "Set on/off to enable/disable high "
+         break;
-+                                          "memory region for PCI MMIO");
+     case A_CFG2:
-+
+-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
+-            /* CFG2 reserved on other boards */
-                                   virt_set_gic_version);
++        if (!have_cfg2(s)) {
-     object_class_property_set_description(oc, "gic-version",
+             goto bad_offset;
          }
          /* AN524: QSPI Select signal */
          s->cfg2 = value;
          break;
      case A_CFG5:
 -        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
 -            /* CFG5 reserved on other boards */
 +        if (!have_cfg5(s)) {
              goto bad_offset;
          }
          /* AN524: ACLK frequency in Hz */
          s->cfg5 = value;
          break;
      case A_CFG6:
 -        if (scc_partno(s) != 0x524) {
 -            /* CFG6 reserved on other boards */
 +        if (!have_cfg6(s)) {
              goto bad_offset;
          }
          /* AN524: Clock divider for BRAM */
 --
-.25.1
+.34.1

-[PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
+[PULL 29/35] hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
-Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.
+The MPS2 SCC device is broadly the same for all FPGA images, but has
 minor differences in the behaviour of the CFG registers depending on
 the image. In many cases we don't really care about the functionality
 controlled by these registers and a reads-as-written or similar
 behaviour is sufficient for the moment.
 For the AN536 the required behaviour is:
  * A_CFG0 has CPU reset and halt bits
     - implement as reads-as-written for the moment
  * A_CFG1 has flash or ATCM address 0 remap handling
     - QEMU doesn't model this; implement as reads-as-written
  * A_CFG2 has QSPI select (like AN524)
     - implemented (no behaviour, as with AN524)
  * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
     - QEMU doesn't care about these, so use the existing
       RAZ behaviour for convenience
  * A_CFG4 is board rev (like all other images)
     - no change needed
  * A_CFG5 is ACLK frq in hz (like AN524)
     - implemented as reads-as-written, as for other boards
  * A_CFG6 is core 0 vector table base address
     - implemented as reads-as-written for the moment
  * A_CFG7 is core 1 vector table base address
     - implemented as reads-as-written for the moment
 Make the changes necessary for this; leave TODO comments where
 appropriate to indicate where we might want to come back and
 implement things like CPU reset.
 The other aspects of the device specific to this FPGA image (like the
 values of the board ID and similar registers) will be set via the
 device's qdev properties.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org
+Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++-----
+ include/hw/misc/mps2-scc.h |   1 +
-file changed, 9 insertions(+), 5 deletions(-)
+ hw/misc/mps2-scc.c         | 101 +++++++++++++++++++++++++++++++++----
+files changed, 92 insertions(+), 10 deletions(-)
-diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
 diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_its_kvm.c
+--- a/include/hw/misc/mps2-scc.h
-+++ b/hw/intc/arm_gicv3_its_kvm.c
++++ b/include/hw/misc/mps2-scc.h
-@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
+@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
+     uint32_t cfg4;
- struct KVMARMITSClass {
+     uint32_t cfg5;
-     GICv3ITSCommonClass parent_class;
+     uint32_t cfg6;
--    void (*parent_reset)(DeviceState *dev);
++    uint32_t cfg7;
-+    ResettablePhases parent_phases;
+     uint32_t cfgdata_rtn;
      uint32_t cfgdata_out;
      uint32_t cfgctrl;
 diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/mps2-scc.c
 +++ b/hw/misc/mps2-scc.c
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
  REG32(CFG4, 0x10)
  REG32(CFG5, 0x14)
  REG32(CFG6, 0x18)
 +REG32(CFG7, 0x1c)
  REG32(CFGDATA_RTN, 0xa0)
  REG32(CFGDATA_OUT, 0xa4)
  REG32(CFGCTRL, 0xa8)
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
  /* Is CFG_REG2 present? */
  static bool have_cfg2(MPS2SCC *s)
  {
 -    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
 +    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
 +        scc_partno(s) == 0x536;
  }
  /* Is CFG_REG3 present? */
  static bool have_cfg3(MPS2SCC *s)
  {
 -    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
 +    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
 +        scc_partno(s) != 0x536;
  }
  /* Is CFG_REG5 present? */
  static bool have_cfg5(MPS2SCC *s)
  {
 -    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
 +    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
 +        scc_partno(s) == 0x536;
  }
  /* Is CFG_REG6 present? */
  static bool have_cfg6(MPS2SCC *s)
  {
 -    return scc_partno(s) == 0x524;
 +    return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
 +}
 +
 +/* Is CFG_REG7 present? */
 +static bool have_cfg7(MPS2SCC *s)
 +{
 +    return scc_partno(s) == 0x536;
 +}
 +
 +/* Does CFG_REG0 drive the 'remap' GPIO output? */
 +static bool cfg0_is_remap(MPS2SCC *s)
 +{
 +    return scc_partno(s) != 0x536;
 +}
 +
 +/* Is CFG_REG1 driving a set of LEDs? */
 +static bool cfg1_is_leds(MPS2SCC *s)
 +{
 +    return scc_partno(s) != 0x536;
  }
  /* Handle a write via the SYS_CFG channel to the specified function/device.
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
          if (!have_cfg3(s)) {
              goto bad_offset;
          }
 -        /* These are user-settable DIP switches on the board. We don't
 +        /*
 +         * These are user-settable DIP switches on the board. We don't
           * model that, so just return zeroes.
 +         *
 +         * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
 +         * bits". These change which part of the DDR4 the motherboard
 +         * configuration controller can see in its memory map (see the
 +         * appnote section 2.4). QEMU doesn't model the MCC at all, so these
 +         * bits are not interesting to us; read-as-zero is as good as anything
 +         * else.
           */
          r = 0;
          break;
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
          }
          r = s->cfg6;
          break;
 +    case A_CFG7:
 +        if (!have_cfg7(s)) {
 +            goto bad_offset;
 +        }
 +        r = s->cfg7;
 +        break;
      case A_CFGDATA_RTN:
          r = s->cfgdata_rtn;
          break;
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
           * we always reflect bit 0 in the 'remap' GPIO output line,
           * and let the board wire it up or not as it chooses.
           * TODO on some boards bit 1 is CPU_WAIT.
 +         *
 +         * TODO: on the AN536 this register controls reset and halt
 +         * for both CPUs. For the moment we don't implement this, so the
 +         * register just reads as written.
           */
          s->cfg0 = value;
 -        qemu_set_irq(s->remap, s->cfg0 & 1);
 +        if (cfg0_is_remap(s)) {
 +            qemu_set_irq(s->remap, s->cfg0 & 1);
 +        }
          break;
      case A_CFG1:
          s->cfg1 = value;
 -        for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
 -            led_set_state(s->led[i], extract32(value, i, 1));
 +        /*
 +         * On most boards this register drives LEDs.
 +         *
 +         * TODO: for AN536 this controls whether flash and ATCM are
 +         * enabled or disabled on reset. QEMU doesn't model this, and
 +         * always wires up RAM in the ATCM area and ROM in the flash area.
 +         */
 +        if (cfg1_is_leds(s)) {
 +            for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
 +                led_set_state(s->led[i], extract32(value, i, 1));
 +            }
          }
          break;
      case A_CFG2:
          if (!have_cfg2(s)) {
              goto bad_offset;
          }
 -        /* AN524: QSPI Select signal */
 +        /* AN524, AN536: QSPI Select signal */
          s->cfg2 = value;
          break;
      case A_CFG5:
          if (!have_cfg5(s)) {
              goto bad_offset;
          }
 -        /* AN524: ACLK frequency in Hz */
 +        /* AN524, AN536: ACLK frequency in Hz */
          s->cfg5 = value;
          break;
      case A_CFG6:
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
              goto bad_offset;
          }
          /* AN524: Clock divider for BRAM */
 +        /* AN536: Core 0 vector table base address */
 +        s->cfg6 = value;
 +        break;
 +    case A_CFG7:
 +        if (!have_cfg7(s)) {
 +            goto bad_offset;
 +        }
 +        /* AN536: Core 1 vector table base address */
          s->cfg6 = value;
          break;
      case A_CFGDATA_OUT:
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
      g_free(s->oscclk_reset);
  }
 +static bool cfg7_needed(void *opaque)
 +{
 +    MPS2SCC *s = opaque;
 +
 +    return have_cfg7(s);
 +}
 +
 +static const VMStateDescription vmstate_cfg7 = {
 +    .name = "mps2-scc/cfg7",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = cfg7_needed,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT32(cfg7, MPS2SCC),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static const VMStateDescription mps2_scc_vmstate = {
      .name = "mps2-scc",
      .version_id = 3,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
          VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
 , vmstate_info_uint32, uint32_t),
          VMSTATE_END_OF_LIST()
 +    },
 +    .subsections = (const VMStateDescription * const []) {
 +        &vmstate_cfg7,
 +        NULL
      }
  };
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
-                       GITS_CTLR, &s->ctlr, true, &error_abort);
- }
--static void kvm_arm_its_reset(DeviceState *dev)
-+static void kvm_arm_its_reset_hold(Object *obj)
- {
--    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
-+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
-     KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
-     int i;
--    c->parent_reset(dev);
-+    if (c->parent_phases.hold) {
-+        c->parent_phases.hold(obj);
-+    }
-     if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
-                                KVM_DEV_ARM_ITS_CTRL_RESET)) {
-@@ -XXX,XX +XXX,XX @@ static Property kvm_arm_its_props[] = {
- static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
-     GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
-     KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
-     dc->realize = kvm_arm_its_realize;
-     device_class_set_props(dc, kvm_arm_its_props);
--    device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
-+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
-+                                       &ic->parent_phases);
-     icc->send_msi = kvm_its_send_msi;
-     icc->pre_save = kvm_arm_its_pre_save;
-     icc->post_load = kvm_arm_its_post_load;
 --
-.25.1
+.34.1

-[PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps
+[PULL 30/35] hw/arm/mps3r: Initial skeleton for mps3-an536 board
-For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
+The AN536 is another FPGA image for the MPS3 development board. Unlike
-use of TLB maintenance instructions that operate on the
+the existing FPGA images we already model, this board uses a Cortex-R
-outer shareable domain:
+family CPU, and it does not use any equivalent to the M-profile
+"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
-TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
+It's therefore more convenient for us to model it as a completely
-TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
+separate C file.
-TLBI RVALE1OS, and TLBI RVAALE1OS.
+This commit adds the basic skeleton of the board model, and the
-(There are no AArch32 outer-shareable TLB maintenance ops.)
+code to create all the RAM and ROM. We assume that we're probably
+going to want to add more images in future, so use the same
-Implement the trapping.
+base class/subclass setup that mps2-tz.c uses, even though at
 the moment there's only a single subclass.
 Following commits will add the CPUs and the peripherals.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 33 +++++++++++++++++++++++----------
+ MAINTAINERS                             |   3 +-
-file changed, 23 insertions(+), 10 deletions(-)
+ configs/devices/arm-softmmu/default.mak |   1 +
+ hw/arm/mps3r.c                          | 239 ++++++++++++++++++++++++
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+ hw/arm/Kconfig                          |   5 +
  hw/arm/meson.build                      |   1 +
 files changed, 248 insertions(+), 1 deletion(-)
  create mode 100644 hw/arm/mps3r.c
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/MAINTAINERS
-+++ b/target/arm/helper.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
-     return CP_ACCESS_OK;
+ F: hw/pci-host/designware.c
- }
+ F: include/hw/pci-host/designware.h
-+#ifdef TARGET_AARCH64
+-MPS2
-+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
++MPS2 / MPS3
-+static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
+ M: Peter Maydell <peter.maydell@linaro.org>
-+                                    bool isread)
+ L: qemu-arm@nongnu.org
-+{
+ S: Maintained
-+    if (arm_current_el(env) == 1 &&
+ F: hw/arm/mps2.c
-+        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
+ F: hw/arm/mps2-tz.c
-+        return CP_ACCESS_TRAP_EL2;
++F: hw/arm/mps3r.c
-+    }
+ F: hw/misc/mps2-*.c
-+    return CP_ACCESS_OK;
+ F: include/hw/misc/mps2-*.h
-+}
+ F: hw/arm/armsse.c
 diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/configs/devices/arm-softmmu/default.mak
 +++ b/configs/devices/arm-softmmu/default.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
  # CONFIG_INTEGRATOR=n
  # CONFIG_FSL_IMX31=n
  # CONFIG_MUSICPAL=n
 +# CONFIG_MPS3R=n
  # CONFIG_MUSCA=n
  # CONFIG_CHEETAH=n
  # CONFIG_SX1=n
 diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Arm MPS3 board emulation for Cortex-R-based FPGA images.
 + * (For M-profile images see mps2.c and mps2tz.c.)
 + *
 + * Copyright (c) 2017 Linaro Limited
 + * Written by Peter Maydell
 + *
 + *  This program is free software; you can redistribute it and/or modify
 + *  it under the terms of the GNU General Public License version 2 or
 + *  (at your option) any later version.
 + */
 +
 +/*
 + * The MPS3 is an FPGA based dev board. This file handles FPGA images
 + * which use the Cortex-R CPUs. We model these separately from the
 + * M-profile images, because on M-profile the FPGA image is based on
 + * a "Subsystem for Embedded" which is similar to an SoC, whereas
 + * the R-profile FPGA images don't have that abstraction layer.
 + *
 + * We model the following FPGA images here:
 + *  "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
 + *
 + * Application Note AN536:
 + * https://developer.arm.com/documentation/dai0536/latest/
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/units.h"
 +#include "qapi/error.h"
 +#include "exec/address-spaces.h"
 +#include "cpu.h"
 +#include "hw/boards.h"
 +#include "hw/arm/boot.h"
 +
 +/* Define the layout of RAM and ROM in a board */
 +typedef struct RAMInfo {
 +    const char *name;
 +    hwaddr base;
 +    hwaddr size;
 +    int mrindex; /* index into rams[]; -1 for the system RAM block */
 +    int flags;
 +} RAMInfo;
 +
 +/*
 + * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
 + * emulation of that much guest RAM, so artificially make it smaller.
 + */
 +#if HOST_LONG_BITS == 32
 +#define MPS3_DDR_SIZE (1 * GiB)
 +#else
 +#define MPS3_DDR_SIZE (3 * GiB)
 +#endif
 +
- static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
++/*
- {
++ * Flag values:
-     ARMCPU *cpu = env_archcpu(env);
++ * IS_MAIN: this is the main machine RAM
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
++ * IS_ROM: this area is read-only
-       .writefn = tlbi_aa64_rvae1is_write },
++ */
-     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
++#define IS_MAIN 1
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
++#define IS_ROM 2
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++#define MPS3R_RAM_MAX 9
-       .writefn = tlbi_aa64_rvae1is_write },
++
-     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
++typedef enum MPS3RFPGAType {
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
++    FPGA_AN536,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++} MPS3RFPGAType;
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++
-       .writefn = tlbi_aa64_rvae1is_write },
++struct MPS3RMachineClass {
-    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
++    MachineClass parent;
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
++    MPS3RFPGAType fpga_type;
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++    const RAMInfo *raminfo;
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++};
-       .writefn = tlbi_aa64_rvae1is_write },
++
-     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
++struct MPS3RMachineState {
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
++    MachineState parent;
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++    MemoryRegion ram[MPS3R_RAM_MAX];
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++};
-       .writefn = tlbi_aa64_rvae1is_write },
++
-     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
++#define TYPE_MPS3R_MACHINE "mps3r"
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
++#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
++
- static const ARMCPRegInfo tlbios_reginfo[] = {
++OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
-     { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
++
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
++static const RAMInfo an536_raminfo[] = {
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++    {
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        .name = "ATCM",
-       .writefn = tlbi_aa64_vmalle1is_write },
++        .base = 0x00000000,
-     { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
++        .size = 0x00008000,
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
++        .mrindex = 0,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++    }, {
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        /* We model the QSPI flash as simple ROM for now */
-       .writefn = tlbi_aa64_vae1is_write },
++        .name = "QSPI",
-     { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
++        .base = 0x08000000,
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
++        .size = 0x00800000,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++        .flags = IS_ROM,
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        .mrindex = 1,
-       .writefn = tlbi_aa64_vmalle1is_write },
++    }, {
-     { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
++        .name = "BRAM",
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
++        .base = 0x10000000,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++        .size = 0x00080000,
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        .mrindex = 2,
-       .writefn = tlbi_aa64_vae1is_write },
++    }, {
-     { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
++        .name = "DDR",
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
++        .base = 0x20000000,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++        .size = MPS3_DDR_SIZE,
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        .mrindex = -1,
-       .writefn = tlbi_aa64_vae1is_write },
++    }, {
-     { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
++        .name = "ATCM0",
-       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
++        .base = 0xee000000,
--      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
++        .size = 0x00008000,
-+      .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
++        .mrindex = 3,
-       .writefn = tlbi_aa64_vae1is_write },
++    }, {
-     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
++        .name = "BTCM0",
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
++        .base = 0xee100000,
 +        .size = 0x00008000,
 +        .mrindex = 4,
 +    }, {
 +        .name = "CTCM0",
 +        .base = 0xee200000,
 +        .size = 0x00008000,
 +        .mrindex = 5,
 +    }, {
 +        .name = "ATCM1",
 +        .base = 0xee400000,
 +        .size = 0x00008000,
 +        .mrindex = 6,
 +    }, {
 +        .name = "BTCM1",
 +        .base = 0xee500000,
 +        .size = 0x00008000,
 +        .mrindex = 7,
 +    }, {
 +        .name = "CTCM1",
 +        .base = 0xee600000,
 +        .size = 0x00008000,
 +        .mrindex = 8,
 +    }, {
 +        .name = NULL,
 +    }
 +};
 +
 +static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
 +                                    const RAMInfo *raminfo)
 +{
 +    /* Return an initialized MemoryRegion for the RAMInfo. */
 +    MemoryRegion *ram;
 +
 +    if (raminfo->mrindex < 0) {
 +        /* Means this RAMInfo is for QEMU's "system memory" */
 +        MachineState *machine = MACHINE(mms);
 +        assert(!(raminfo->flags & IS_ROM));
 +        return machine->ram;
 +    }
 +
 +    assert(raminfo->mrindex < MPS3R_RAM_MAX);
 +    ram = &mms->ram[raminfo->mrindex];
 +
 +    memory_region_init_ram(ram, NULL, raminfo->name,
 +                           raminfo->size, &error_fatal);
 +    if (raminfo->flags & IS_ROM) {
 +        memory_region_set_readonly(ram, true);
 +    }
 +    return ram;
 +}
 +
 +static void mps3r_common_init(MachineState *machine)
 +{
 +    MPS3RMachineState *mms = MPS3R_MACHINE(machine);
 +    MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
 +    MemoryRegion *sysmem = get_system_memory();
 +
 +    for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
 +        MemoryRegion *mr = mr_for_raminfo(mms, ri);
 +        memory_region_add_subregion(sysmem, ri->base, mr);
 +    }
 +}
 +
 +static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
 +{
 +    /*
 +     * Set mc->default_ram_size and default_ram_id from the
 +     * information in mmc->raminfo.
 +     */
 +    MachineClass *mc = MACHINE_CLASS(mmc);
 +    const RAMInfo *p;
 +
 +    for (p = mmc->raminfo; p->name; p++) {
 +        if (p->mrindex < 0) {
 +            /* Found the entry for "system memory" */
 +            mc->default_ram_size = p->size;
 +            mc->default_ram_id = p->name;
 +            return;
 +        }
 +    }
 +    g_assert_not_reached();
 +}
 +
 +static void mps3r_class_init(ObjectClass *oc, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->init = mps3r_common_init;
 +}
 +
 +static void mps3r_an536_class_init(ObjectClass *oc, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +    MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
 +    static const char * const valid_cpu_types[] = {
 +        ARM_CPU_TYPE_NAME("cortex-r52"),
 +        NULL
 +    };
 +
 +    mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
 +    mc->default_cpus = 2;
 +    mc->min_cpus = mc->default_cpus;
 +    mc->max_cpus = mc->default_cpus;
 +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
 +    mc->valid_cpu_types = valid_cpu_types;
 +    mmc->raminfo = an536_raminfo;
 +    mps3r_set_default_ram_info(mmc);
 +}
 +
 +static const TypeInfo mps3r_machine_types[] = {
 +    {
 +        .name = TYPE_MPS3R_MACHINE,
 +        .parent = TYPE_MACHINE,
 +        .abstract = true,
 +        .instance_size = sizeof(MPS3RMachineState),
 +        .class_size = sizeof(MPS3RMachineClass),
 +        .class_init = mps3r_class_init,
 +    }, {
 +        .name = TYPE_MPS3R_AN536_MACHINE,
 +        .parent = TYPE_MPS3R_MACHINE,
 +        .class_init = mps3r_an536_class_init,
 +    },
 +};
 +
 +DEFINE_TYPES(mps3r_machine_types);
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
      select PFLASH_CFI01
      select SMC91C111
 +config MPS3R
 +    bool
 +    default y
 +    depends on TCG && ARM
 +
  config MUSCA
      bool
      default y
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
  arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
  arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
  arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
 +arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
  arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
  arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
  arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
 --
-.25.1
+.34.1

-[PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT
+[PULL 31/35] hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
-FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
+Create the CPUs, the GIC, and the per-CPU RAM block for
-TICAB, TOCU and TID4.  These allow the guest to enable trapping of
+the mps3-an536 board.
 various EL1 instructions to EL2.  In this commit, add the necessary
 code to allow the guest to set these bits if the feature is present;
 because the bit is always zero when the feature isn't present we
 won't need to use explicit feature checks in the "trap on condition"
 tests in the following commits.
 Note that although full implementation of the feature (mandatory from
 Armv8.5 onward) requires all five trap bits, the ID registers permit
 a value indicating that only TICAB, TOCU and TID4 are implemented,
 which might be the case for CPUs between Armv8.2 and Armv8.5.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
 ---
- target/arm/cpu.h    | 30 ++++++++++++++++++++++++++++++
+ hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
- target/arm/helper.c |  6 ++++++
+file changed, 177 insertions(+), 3 deletions(-)
 files changed, 36 insertions(+)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/arm/mps3r.c
-+++ b/target/arm/cpu.h
++++ b/hw/arm/mps3r.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@
-     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
+ #include "qemu/osdep.h"
  #include "qemu/units.h"
  #include "qapi/error.h"
 +#include "qapi/qmp/qlist.h"
  #include "exec/address-spaces.h"
  #include "cpu.h"
  #include "hw/boards.h"
 +#include "hw/qdev-properties.h"
  #include "hw/arm/boot.h"
 +#include "hw/arm/bsa.h"
 +#include "hw/intc/arm_gicv3.h"
  /* Define the layout of RAM and ROM in a board */
  typedef struct RAMInfo {
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
  #define IS_ROM 2
  #define MPS3R_RAM_MAX 9
 +#define MPS3R_CPU_MAX 2
 +
 +#define PERIPHBASE 0xf0000000
 +#define NUM_SPIS 96
  typedef enum MPS3RFPGAType {
      FPGA_AN536,
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
      MachineClass parent;
      MPS3RFPGAType fpga_type;
      const RAMInfo *raminfo;
 +    hwaddr loader_start;
  };
  struct MPS3RMachineState {
      MachineState parent;
 +    struct arm_boot_info bootinfo;
      MemoryRegion ram[MPS3R_RAM_MAX];
 +    Object *cpu[MPS3R_CPU_MAX];
 +    MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
 +    MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
 +    MemoryRegion cpu_ram[MPS3R_CPU_MAX];
 +    GICv3State gic;
  };
  #define TYPE_MPS3R_MACHINE "mps3r"
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
      return ram;
  }
-+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
++/*
 + * There is no defined secondary boot protocol for Linux for the AN536,
 + * because real hardware has a restriction that atomic operations between
 + * the two CPUs do not function correctly, and so true SMP is not
 + * possible. Therefore for cases where the user is directly booting
 + * a kernel, we treat the system as essentially uniprocessor, and
 + * put the secondary CPU into power-off state (as if the user on the
 + * real hardware had configured the secondary to be halted via the
 + * SCC config registers).
 + *
 + * Note that the default secondary boot code would not work here anyway
 + * as it assumes a GICv2, and we have a GICv3.
 + */
 +static void mps3r_write_secondary_boot(ARMCPU *cpu,
 +                                       const struct arm_boot_info *info)
 +{
-+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
++    /*
 +     * Power the secondary CPU off. This means we don't need to write any
 +     * boot code into guest memory. Note that the 'cpu' argument to this
 +     * function is the primary CPU we passed to arm_load_kernel(), not
 +     * the secondary. Loop around all the other CPUs, as the boot.c
 +     * code does for the "disable secondaries if PSCI is enabled" case.
 +     */
 +    for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
 +        if (cs != first_cpu) {
 +            object_property_set_bool(OBJECT(cs), "start-powered-off", true,
 +                                     &error_abort);
 +        }
 +    }
 +}
 +
-+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
++static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
 +                                      const struct arm_boot_info *info)
 +{
-+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
++    /* We don't need to do anything here because the CPU will be off */
 +}
 +
- static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
++static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
 +{
 +    MachineState *machine = MACHINE(mms);
 +    DeviceState *gicdev;
 +    QList *redist_region_count;
 +
 +    object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
 +    gicdev = DEVICE(&mms->gic);
 +    qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
 +    qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
 +    redist_region_count = qlist_new();
 +    qlist_append_int(redist_region_count, machine->smp.cpus);
 +    qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
 +    object_property_set_link(OBJECT(&mms->gic), "sysmem",
 +                             OBJECT(sysmem), &error_fatal);
 +    sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
 +    /*
 +     * Wire the outputs from each CPU's generic timer and the GICv3
 +     * maintenance interrupt signal to the appropriate GIC PPI inputs,
 +     * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
 +     */
 +    for (int i = 0; i < machine->smp.cpus; i++) {
 +        DeviceState *cpudev = DEVICE(mms->cpu[i]);
 +        SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
 +        int intidbase = NUM_SPIS + i * GIC_INTERNAL;
 +        int irq;
 +        /*
 +         * Mapping from the output timer irq lines from the CPU to the
 +         * GIC PPI inputs used for this board. This isn't a BSA board,
 +         * but it uses the standard convention for the PPI numbers.
 +         */
 +        const int timer_irq[] = {
 +            [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
 +            [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
 +            [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
 +        };
 +
 +        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 +            qdev_connect_gpio_out(cpudev, irq,
 +                                  qdev_get_gpio_in(gicdev,
 +                                                   intidbase + timer_irq[irq]));
 +        }
 +
 +        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
 +                                    qdev_get_gpio_in(gicdev,
 +                                                     intidbase + ARCH_GIC_MAINT_IRQ));
 +
 +        qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
 +                                    qdev_get_gpio_in(gicdev,
 +                                                     intidbase + VIRTUAL_PMU_IRQ));
 +
 +        sysbus_connect_irq(gicsbd, i,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 +        sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 +        sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 +        sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
 +                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 +    }
 +}
 +
  static void mps3r_common_init(MachineState *machine)
  {
-     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
+     MPS3RMachineState *mms = MPS3R_MACHINE(machine);
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
-     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
+         MemoryRegion *mr = mr_for_raminfo(mms, ri);
          memory_region_add_subregion(sysmem, ri->base, mr);
      }
 +
 +    assert(machine->smp.cpus <= MPS3R_CPU_MAX);
 +    for (int i = 0; i < machine->smp.cpus; i++) {
 +        g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
 +        g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
 +        g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
 +
 +        /*
 +         * Each CPU has some private RAM/peripherals, so create the container
 +         * which will house those, with the whole-machine system memory being
 +         * used where there's no CPU-specific device. Note that we need the
 +         * sysmem_alias aliases because we can't put one MR (the original
 +         * 'sysmem') into more than one other MR.
 +         */
 +        memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
 +                           sysmem_name, UINT64_MAX);
 +        memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
 +                                 alias_name, sysmem, 0, UINT64_MAX);
 +        memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
 +                                            &mms->sysmem_alias[i], -1);
 +
 +        mms->cpu[i] = object_new(machine->cpu_type);
 +        object_property_set_link(mms->cpu[i], "memory",
 +                                 OBJECT(&mms->cpu_sysmem[i]), &error_abort);
 +        object_property_set_int(mms->cpu[i], "reset-cbar",
 +                                PERIPHBASE, &error_abort);
 +        qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
 +        object_unref(mms->cpu[i]);
 +
 +        /* Per-CPU RAM */
 +        memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
 +                               0x1000, &error_fatal);
 +        memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
 +                                    &mms->cpu_ram[i]);
 +    }
 +
 +    create_gic(mms, sysmem);
 +
 +    mms->bootinfo.ram_size = machine->ram_size;
 +    mms->bootinfo.board_id = -1;
 +    mms->bootinfo.loader_start = mmc->loader_start;
 +    mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
 +    mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
 +    arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
  }
-+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
+ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
-+{
+@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
-+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
+             /* Found the entry for "system memory" */
-+}
+             mc->default_ram_size = p->size;
-+
+             mc->default_ram_id = p->name;
-+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
++            mmc->loader_start = p->base;
-+{
+             return;
 +    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
 +}
 +
  static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id)
      return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
  }
 +static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
 +}
 +
 +static inline bool isar_feature_any_evt(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
 +}
 +
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
          }
      }
+@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
-+    if (cpu_isar_feature(any_evt, cpu)) {
+     };
-+        valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4;
-+    } else if (cpu_isar_feature(any_half_evt, cpu)) {
+     mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
-+        valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
+-    mc->default_cpus = 2;
-+    }
+-    mc->min_cpus = mc->default_cpus;
-+
+-    mc->max_cpus = mc->default_cpus;
-     /* Clear RES0 bits.  */
++    /*
-     value &= valid_mask;
++     * In the real FPGA image there are always two cores, but the standard
++     * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
 +     * that the second core is held in reset and halted. Many images built for
 +     * the board do not expect the second core to run at startup (especially
 +     * since on the real FPGA image it is not possible to use LDREX/STREX
 +     * in RAM between the two cores, so a true SMP setup isn't supported).
 +     *
 +     * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
 +     * with the default being -smp 1. This seems a more intuitive UI for
 +     * QEMU users than, for instance, having a machine property to allow
 +     * the user to set the initial value of the SYSCON 0x000 register.
 +     */
 +    mc->default_cpus = 1;
 +    mc->min_cpus = 1;
 +    mc->max_cpus = 2;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
      mc->valid_cpu_types = valid_cpu_types;
      mmc->raminfo = an536_raminfo;
 --
-.25.1
+.34.1

-[PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
+[PULL 32/35] hw/arm/mps3r: Add UARTs
-Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
+This board has a lot of UARTs: there is one UART per CPU in the
-TYPE_ARM_GIC_KVM subclass to 3-phase reset.
+per-CPU peripheral part of the address map, whose interrupts are
 connected as per-CPU interrupt lines.  Then there are 4 UARTs in the
 normal part of the peripheral space, whose interrupts are shared
 peripheral interrupts.
 Connect and wire them all up; this involves some OR gates where
 multiple overflow interrupts are wired into one GIC input.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org
+Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
 ---
- hw/intc/arm_gic_kvm.c | 14 +++++++++-----
+ hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
-file changed, 9 insertions(+), 5 deletions(-)
+file changed, 94 insertions(+)
-diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
+diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic_kvm.c
+--- a/hw/arm/mps3r.c
-+++ b/hw/intc/arm_gic_kvm.c
++++ b/hw/arm/mps3r.c
-@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
+@@ -XXX,XX +XXX,XX @@
- struct KVMARMGICClass {
+ #include "qapi/qmp/qlist.h"
-     ARMGICCommonClass parent_class;
+ #include "exec/address-spaces.h"
-     DeviceRealize parent_realize;
+ #include "cpu.h"
--    void (*parent_reset)(DeviceState *dev);
++#include "sysemu/sysemu.h"
-+    ResettablePhases parent_phases;
+ #include "hw/boards.h"
 +#include "hw/or-irq.h"
  #include "hw/qdev-properties.h"
  #include "hw/arm/boot.h"
  #include "hw/arm/bsa.h"
 +#include "hw/char/cmsdk-apb-uart.h"
  #include "hw/intc/arm_gicv3.h"
  /* Define the layout of RAM and ROM in a board */
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
  #define MPS3R_RAM_MAX 9
  #define MPS3R_CPU_MAX 2
 +#define MPS3R_UART_MAX 4 /* shared UART count */
  #define PERIPHBASE 0xf0000000
  #define NUM_SPIS 96
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
      MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
      MemoryRegion cpu_ram[MPS3R_CPU_MAX];
      GICv3State gic;
 +    /* per-CPU UARTs followed by the shared UARTs */
 +    CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
 +    OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
 +    OrIRQState uart_oflow;
  };
- void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
+ #define TYPE_MPS3R_MACHINE "mps3r"
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s)
+@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
  OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
 +/*
 + * Main clock frequency CLK in Hz (50MHz). In the image there are also
 + * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
 + * model we just roll them all into one.
 + */
 +#define CLK_FRQ 50000000
 +
  static const RAMInfo an536_raminfo[] = {
      {
          .name = "ATCM",
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
      }
  }
--static void kvm_arm_gic_reset(DeviceState *dev)
++/*
-+static void kvm_arm_gic_reset_hold(Object *obj)
++ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
 + * The qemu_irq arguments are where we connect the various IRQs from the UART.
 + */
 +static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
 +                        hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
 +                        qemu_irq txoverirq, qemu_irq rxoverirq,
 +                        qemu_irq combirq)
 +{
 +    g_autofree char *s = g_strdup_printf("uart%d", uartno);
 +    SysBusDevice *sbd;
 +
 +    assert(uartno < ARRAY_SIZE(mms->uart));
 +    object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
 +                            TYPE_CMSDK_APB_UART);
 +    qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
 +    qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
 +    sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
 +    sysbus_realize(sbd, &error_fatal);
 +    memory_region_add_subregion(mem, baseaddr,
 +                                sysbus_mmio_get_region(sbd, 0));
 +    sysbus_connect_irq(sbd, 0, txirq);
 +    sysbus_connect_irq(sbd, 1, rxirq);
 +    sysbus_connect_irq(sbd, 2, txoverirq);
 +    sysbus_connect_irq(sbd, 3, rxoverirq);
 +    sysbus_connect_irq(sbd, 4, combirq);
 +}
 +
  static void mps3r_common_init(MachineState *machine)
  {
--    GICState *s = ARM_GIC_COMMON(dev);
+     MPS3RMachineState *mms = MPS3R_MACHINE(machine);
-+    GICState *s = ARM_GIC_COMMON(obj);
+     MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
-     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
+     MemoryRegion *sysmem = get_system_memory();
++    DeviceState *gicdev;
--    kgc->parent_reset(dev);
-+    if (kgc->parent_phases.hold) {
+     for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
-+        kgc->parent_phases.hold(obj);
+         MemoryRegion *mr = mr_for_raminfo(mms, ri);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
      }
      create_gic(mms, sysmem);
 +    gicdev = DEVICE(&mms->gic);
 +
 +    /*
 +     * UARTs 0 and 1 are per-CPU; their interrupts are wired to
 +     * the relevant CPU's PPI 0..3, aka INTID 16..19
 +     */
 +    for (int i = 0; i < machine->smp.cpus; i++) {
 +        int intidbase = NUM_SPIS + i * GIC_INTERNAL;
 +        g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
 +        DeviceState *orgate;
 +
 +        /* The two overflow IRQs from the UART are ORed together into PPI 3 */
 +        object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
 +                                TYPE_OR_IRQ);
 +        orgate = DEVICE(&mms->cpu_uart_oflow[i]);
 +        qdev_prop_set_uint32(orgate, "num-lines", 2);
 +        qdev_realize(orgate, NULL, &error_fatal);
 +        qdev_connect_gpio_out(orgate, 0,
 +                              qdev_get_gpio_in(gicdev, intidbase + 19));
 +
 +        create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
 +                    qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
 +                    qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
 +                    qdev_get_gpio_in(orgate, 0), /* txover */
 +                    qdev_get_gpio_in(orgate, 1), /* rxover */
 +                    qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
 +    }
++    /*
-     if (kvm_arm_gic_can_save_restore(s)) {
++     * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
-         kvm_arm_gic_put(s);
++     * together into IRQ 17
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
++     */
- static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
++    object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
- {
++                            &mms->uart_oflow, TYPE_OR_IRQ);
-     DeviceClass *dc = DEVICE_CLASS(klass);
++    qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
++                         MPS3R_UART_MAX * 2);
-     ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
++    qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
-     KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
++    qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
++                          qdev_get_gpio_in(gicdev, 17));
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
++
-     agcc->post_load = kvm_arm_gic_put;
++    for (int i = 0; i < MPS3R_UART_MAX; i++) {
-     device_class_set_parent_realize(dc, kvm_arm_gic_realize,
++        hwaddr baseaddr = 0xe0205000 + i * 0x1000;
-                                     &kgc->parent_realize);
++        int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
--    device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
++
-+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL,
++        create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
-+                                       &kgc->parent_phases);
++                    qdev_get_gpio_in(gicdev, txirq),
- }
++                    qdev_get_gpio_in(gicdev, rxirq),
++                    qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
- static const TypeInfo kvm_arm_gic_info = {
++                    qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
 +                    qdev_get_gpio_in(gicdev, combirq));
 +    }
      mms->bootinfo.ram_size = machine->ram_size;
      mms->bootinfo.board_id = -1;
 --
-.25.1
+.34.1

-[PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
+[PULL 33/35] hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
-Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.
+Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
 board.  These are all simple devices that just need to be created and
 wired up.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org
+Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_kvm.c | 14 +++++++++-----
+ hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
-file changed, 9 insertions(+), 5 deletions(-)
+file changed, 59 insertions(+)
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
+--- a/hw/arm/mps3r.c
-+++ b/hw/intc/arm_gicv3_kvm.c
++++ b/hw/arm/mps3r.c
-@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
+@@ -XXX,XX +XXX,XX @@
- struct KVMARMGICv3Class {
+ #include "sysemu/sysemu.h"
-     ARMGICv3CommonClass parent_class;
+ #include "hw/boards.h"
-     DeviceRealize parent_realize;
+ #include "hw/or-irq.h"
--    void (*parent_reset)(DeviceState *dev);
++#include "hw/qdev-clock.h"
-+    ResettablePhases parent_phases;
+ #include "hw/qdev-properties.h"
  #include "hw/arm/boot.h"
  #include "hw/arm/bsa.h"
  #include "hw/char/cmsdk-apb-uart.h"
 +#include "hw/i2c/arm_sbcon_i2c.h"
  #include "hw/intc/arm_gicv3.h"
 +#include "hw/misc/unimp.h"
 +#include "hw/timer/cmsdk-apb-dualtimer.h"
 +#include "hw/watchdog/cmsdk-apb-watchdog.h"
  /* Define the layout of RAM and ROM in a board */
  typedef struct RAMInfo {
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
      CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
      OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
      OrIRQState uart_oflow;
 +    CMSDKAPBWatchdog watchdog;
 +    CMSDKAPBDualTimer dualtimer;
 +    ArmSbconI2CState i2c[5];
 +    Clock *clk;
  };
- static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
+ #define TYPE_MPS3R_MACHINE "mps3r"
-@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
-     c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
+     MemoryRegion *sysmem = get_system_memory();
- }
+     DeviceState *gicdev;
--static void kvm_arm_gicv3_reset(DeviceState *dev)
++    mms->clk = clock_new(OBJECT(machine), "CLK");
-+static void kvm_arm_gicv3_reset_hold(Object *obj)
++    clock_set_hz(mms->clk, CLK_FRQ);
- {
++
--    GICv3State *s = ARM_GICV3_COMMON(dev);
+     for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
-+    GICv3State *s = ARM_GICV3_COMMON(obj);
+         MemoryRegion *mr = mr_for_raminfo(mms, ri);
-     KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
+         memory_region_add_subregion(sysmem, ri->base, mr);
+@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
-     DPRINTF("Reset\n");
+                     qdev_get_gpio_in(gicdev, combirq));
+     }
--    kgc->parent_reset(dev);
-+    if (kgc->parent_phases.hold) {
++    for (int i = 0; i < 4; i++) {
-+        kgc->parent_phases.hold(obj);
++        /* CMSDK GPIO controllers */
 +        g_autofree char *s = g_strdup_printf("gpio%d", i);
 +        create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
 +    }
++
-     if (s->migration_blocker) {
++    object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
-         DPRINTF("Cannot put kernel gic state, no kernel interface\n");
++                            TYPE_CMSDK_APB_WATCHDOG);
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
++    qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
- static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
++    sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
- {
++    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
-     DeviceClass *dc = DEVICE_CLASS(klass);
++                       qdev_get_gpio_in(gicdev, 0));
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
-     ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
++
-     KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
++    object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
++                            TYPE_CMSDK_APB_DUALTIMER);
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
++    qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
-     agcc->post_load = kvm_arm_gicv3_put;
++    sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
-     device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
++    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
-                                     &kgc->parent_realize);
++                       qdev_get_gpio_in(gicdev, 3));
--    device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
-+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL,
++                       qdev_get_gpio_in(gicdev, 1));
-+                                       &kgc->parent_phases);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
- }
++                       qdev_get_gpio_in(gicdev, 2));
++    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
- static const TypeInfo kvm_arm_gicv3_info = {
++
 +    for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
 +        static const hwaddr i2cbase[] = {0xe0102000,    /* Touch */
 +                                         0xe0103000,    /* Audio */
 +                                         0xe0107000,    /* Shield0 */
 +                                         0xe0108000,    /* Shield1 */
 +                                         0xe0109000};   /* DDR4 EEPROM */
 +        g_autofree char *s = g_strdup_printf("i2c%d", i);
 +
 +        object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
 +                                TYPE_ARM_SBCON_I2C);
 +        sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
 +        if (i != 2 && i != 3) {
 +            /*
 +             * internal-only bus: mark it full to avoid user-created
 +             * i2c devices being plugged into it.
 +             */
 +            qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
 +        }
 +    }
 +
      mms->bootinfo.ram_size = machine->ram_size;
      mms->bootinfo.board_id = -1;
      mms->bootinfo.loader_start = mmc->loader_start;
 --
-.25.1
+.34.1

-[PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
+[PULL 34/35] hw/arm/mps3r: Add remaining devices
-Convert the TYPE_ARM_SMMUV3 device to 3-phase reset.  The legacy
+Add the remaining devices (or unimplemented-device stubs) for
-reset method doesn't do anything that's invalid in the hold phase, so
+this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
-the conversion only requires changing it to a hold phase method, and
+QSPI write-config block, and ethernet.
 using the 3-phase versions of the "save the parent reset method and
 chain to it" code.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
+Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
 ---
- include/hw/arm/smmuv3.h |  2 +-
+ hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
- hw/arm/smmuv3.c         | 12 ++++++++----
+file changed, 74 insertions(+)
 files changed, 9 insertions(+), 5 deletions(-)
-diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
+diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/smmuv3.h
+--- a/hw/arm/mps3r.c
-+++ b/include/hw/arm/smmuv3.h
++++ b/hw/arm/mps3r.c
-@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
+@@ -XXX,XX +XXX,XX @@
-     /*< public >*/
+ #include "hw/char/cmsdk-apb-uart.h"
+ #include "hw/i2c/arm_sbcon_i2c.h"
-     DeviceRealize parent_realize;
+ #include "hw/intc/arm_gicv3.h"
--    DeviceReset   parent_reset;
++#include "hw/misc/mps2-scc.h"
-+    ResettablePhases parent_phases;
++#include "hw/misc/mps2-fpgaio.h"
  #include "hw/misc/unimp.h"
 +#include "hw/net/lan9118.h"
 +#include "hw/rtc/pl031.h"
 +#include "hw/ssi/pl022.h"
  #include "hw/timer/cmsdk-apb-dualtimer.h"
  #include "hw/watchdog/cmsdk-apb-watchdog.h"
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
      CMSDKAPBWatchdog watchdog;
      CMSDKAPBDualTimer dualtimer;
      ArmSbconI2CState i2c[5];
 +    PL022State spi[3];
 +    MPS2SCC scc;
 +    MPS2FPGAIO fpgaio;
 +    UnimplementedDeviceState i2s_audio;
 +    PL031State rtc;
      Clock *clk;
  };
- #define TYPE_ARM_SMMUV3   "arm-smmuv3"
+@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/smmuv3.c
 +++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
      }
- }
+ };
--static void smmu_reset(DeviceState *dev)
++static const int an536_oscclk[] = {
-+static void smmu_reset_hold(Object *obj)
++    24000000, /* 24MHz reference for RTC and timers */
 +    50000000, /* 50MHz ACLK */
 +    50000000, /* 50MHz MCLK */
 +    50000000, /* 50MHz GPUCLK */
 +    24576000, /* 24.576MHz AUDCLK */
 +    23750000, /* 23.75MHz HDLCDCLK */
 +    100000000, /* 100MHz DDR4_REF_CLK */
 +};
 +
  static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
                                      const RAMInfo *raminfo)
  {
--    SMMUv3State *s = ARM_SMMUV3(dev);
+@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
-+    SMMUv3State *s = ARM_SMMUV3(obj);
+     MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
-     SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
+     MemoryRegion *sysmem = get_system_memory();
+     DeviceState *gicdev;
--    c->parent_reset(dev);
++    QList *oscclk;
-+    if (c->parent_phases.hold) {
-+        c->parent_phases.hold(obj);
+     mms->clk = clock_new(OBJECT(machine), "CLK");
      clock_set_hz(mms->clk, CLK_FRQ);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
          }
      }
 +    for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
 +        g_autofree char *s = g_strdup_printf("spi%d", i);
 +        hwaddr baseaddr = 0xe0104000 + i * 0x1000;
 +
 +        object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
 +        sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
 +                           qdev_get_gpio_in(gicdev, 22 + i));
 +    }
++
-     smmuv3_init_regs(s);
++    object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
- }
++    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
-@@ -XXX,XX +XXX,XX @@ static void smmuv3_instance_init(Object *obj)
++    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
- static void smmuv3_class_init(ObjectClass *klass, void *data)
++    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
- {
++    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
-     DeviceClass *dc = DEVICE_CLASS(klass);
++    oscclk = qlist_new();
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
++    for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
-     SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
++        qlist_append_int(oscclk, an536_oscclk[i]);
++    }
-     dc->vmsd = &vmstate_smmuv3;
++    qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
--    device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
++    sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
-+    resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
++    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
-+                                       &c->parent_phases);
++
-     c->parent_realize = dc->realize;
++    create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
-     dc->realize = smmu_realize;
++
- }
++    object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
 +                            TYPE_MPS2_FPGAIO);
 +    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
 +    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
 +    qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
 +    qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
 +    sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
 +
 +    create_unimplemented_device("clcd", 0xe0209000, 0x1000);
 +
 +    object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
 +    sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
 +                       qdev_get_gpio_in(gicdev, 4));
 +
 +    /*
 +     * In hardware this is a LAN9220; the LAN9118 is software compatible
 +     * except that it doesn't support the checksum-offload feature.
 +     */
 +    lan9118_init(0xe0300000,
 +                 qdev_get_gpio_in(gicdev, 18));
 +
 +    create_unimplemented_device("usb", 0xe0301000, 0x1000);
 +    create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
 +
      mms->bootinfo.ram_size = machine->ram_size;
      mms->bootinfo.board_id = -1;
      mms->bootinfo.loader_start = mmc->loader_start;
 --
-.25.1
+.34.1

-[PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
+[PULL 35/35] docs: Add documentation for the mps3-an536 board
-Convert the TYPE_ARM_SMMU device to 3-phase reset.  The legacy method
+Add documentation for the mps3-an536 board type.
 doesn't do anything that's invalid in the hold phase, so the
 conversion is simple and not a behaviour change.
 Note that we must convert this base class before we can convert the
 TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable
 handles "chain to parent class reset" when the base class is 3-phase
 and the subclass is still using legacy reset, but not the other way
 around.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
 ---
- hw/arm/smmu-common.c | 7 ++++---
+ docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
-file changed, 4 insertions(+), 3 deletions(-)
+file changed, 34 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/smmu-common.c
+--- a/docs/system/arm/mps2.rst
-+++ b/hw/arm/smmu-common.c
++++ b/docs/system/arm/mps2.rst
-@@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@
-     }
+-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
- }
+-=========================================================================================================================================================
++Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
--static void smmu_base_reset(DeviceState *dev)
++=========================================================================================================================================================================
-+static void smmu_base_reset_hold(Object *obj)
- {
+-These board models all use Arm M-profile CPUs.
--    SMMUState *s = ARM_SMMU(dev);
++These board models use Arm M-profile or R-profile CPUs.
-+    SMMUState *s = ARM_SMMU(obj);
+ The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
-     g_hash_table_remove_all(s->configs);
+ bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
-     g_hash_table_remove_all(s->iotlb);
+@@ -XXX,XX +XXX,XX @@ FPGA image.
-@@ -XXX,XX +XXX,XX @@ static Property smmu_dev_properties[] = {
- static void smmu_base_class_init(ObjectClass *klass, void *data)
+ QEMU models the following FPGA images:
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
++FPGA images using M-profile CPUs:
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
++
-     SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
+ ``mps2-an385``
+   Cortex-M3 as documented in Arm Application Note AN385
-     device_class_set_props(dc, smmu_dev_properties);
+ ``mps2-an386``
-     device_class_set_parent_realize(dc, smmu_base_realize,
+@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
-                                     &sbc->parent_realize);
+ ``mps3-an547``
--    dc->reset = smmu_base_reset;
+   Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
-+    rc->phases.hold = smmu_base_reset_hold;
- }
++FPGA images using R-profile CPUs:
++
- static const TypeInfo smmu_base_info = {
++``mps3-an536``
 +  Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
 +
  Differences between QEMU and real hardware:
  - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
    flash, but only as simple ROM, so attempting to rewrite the flash
    from the guest will fail
  - QEMU does not model the USB controller in MPS3 boards
 +- AN536 does not support runtime control of CPU reset and halt via
 +  the SCC CFG_REG0 register.
 +- AN536 does not support enabling or disabling the flash and ATCM
 +  interfaces via the SCC CFG_REG1 register.
 +- AN536 does not support setting of the initial vector table
 +  base address via the SCC CFG_REG6 and CFG_REG7 register config,
 +  and does not provide a mechanism for specifying these values at
 +  startup, so all guest images must be built to start from TCM
 +  (i.e. to expect the interrupt vector base at 0 from reset).
 +- AN536 defaults to only creating a single CPU; this is the equivalent
 +  of the way the real FPGA image usually runs with the second Cortex-R52
 +  held in halt via the initial SCC CFG_REG0 register setting. You can
 +  create the second CPU with ``-smp 2``; both CPUs will then start
 +  execution immediately on startup.
 +
 +Note that for the AN536 the first UART is accessible only by
 +CPU0, and the second UART is accessible only by CPU1. The
 +first UART accessible shared between both CPUs is the third
 +UART. Guest software might therefore be built to use either
 +the first UART or the third UART; if you don't see any output
 +from the UART you are looking at, try one of the others.
 +(Even if the AN536 machine is started with a single CPU and so
 +no "CPU1-only UART", the UART numbering remains the same,
 +with the third UART being the first of the shared ones.)
  Machine-specific options
  """"""""""""""""""""""""
 --
-.25.1
+.34.1

First arm pullreq of the 8.0 series...

The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:

Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215

for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af:

target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: Add properties to allow more granular
   configuration of use of highmem space
 * target/arm: Add Cortex-A55 CPU
 * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
 * Implement FEAT_EVT
 * Some 3-phase-reset conversions for Arm GIC, SMMU
 * hw/arm/boot: set initrd with #address-cells type in fdt
 * align user-mode exposed ID registers with Linux
 * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
 * Restrict arm_cpu_exec_interrupt() to TCG accelerator

----------------------------------------------------------------
Gavin Shan (7):
      hw/arm/virt: Introduce virt_set_high_memmap() helper
      hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
      hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
      hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
      hw/arm/virt: Improve high memory region address assignment
      hw/arm/virt: Add 'compact-highmem' property
      hw/arm/virt: Add properties to disable high memory regions

Luke Starrett (1):
      hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement

Mihai Carabas (1):
      hw/arm/virt: build SMBIOS 19 table

Peter Maydell (15):
      target/arm: Allow relevant HCR bits to be written for FEAT_EVT
      target/arm: Implement HCR_EL2.TTLBIS traps
      target/arm: Implement HCR_EL2.TTLBOS traps
      target/arm: Implement HCR_EL2.TICAB,TOCU traps
      target/arm: Implement HCR_EL2.TID4 traps
      target/arm: Report FEAT_EVT for TCG '-cpu max'
      hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
      hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
      hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
      hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
      hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
      hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
      hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
      hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
      hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset

Philippe Mathieu-Daudé (1):
      target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator

Schspa Shi (1):
      hw/arm/boot: set initrd with #address-cells type in fdt

Thomas Huth (1):
      hw/misc: Move some arm-related files from specific_ss into softmmu_ss

Timofey Kutergin (1):
      target/arm: Add Cortex-A55 CPU

Zhuojia Shen (1):
      target/arm: align exposed ID registers with Linux

From: Gavin Shan <gshan@redhat.com>

This introduces virt_set_high_memmap() helper. The logic of high
memory region address assignment is moved to the helper. The intention
is to make the subsequent optimization for high memory region address
assignment easier.

No functional change intended.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-2-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 74 ++++++++++++++++++++++++++++-----------------------
 1 file changed, 41 insertions(+), 33 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
     return arm_cpu_mp_affinity(idx, clustersz);
 }
 
+static void virt_set_high_memmap(VirtMachineState *vms,
+                                 hwaddr base, int pa_bits)
+{
+    int i;
+
+    for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+        hwaddr size = extended_memmap[i].size;
+        bool fits;
+
+        base = ROUND_UP(base, size);
+        vms->memmap[i].base = base;
+        vms->memmap[i].size = size;
+
+        /*
+         * Check each device to see if they fit in the PA space,
+         * moving highest_gpa as we go.
+         *
+         * For each device that doesn't fit, disable it.
+         */
+        fits = (base + size) <= BIT_ULL(pa_bits);
+        if (fits) {
+            vms->highest_gpa = base + size - 1;
+        }
+
+        switch (i) {
+        case VIRT_HIGH_GIC_REDIST2:
+            vms->highmem_redists &= fits;
+            break;
+        case VIRT_HIGH_PCIE_ECAM:
+            vms->highmem_ecam &= fits;
+            break;
+        case VIRT_HIGH_PCIE_MMIO:
+            vms->highmem_mmio &= fits;
+            break;
+        }
+
+        base += size;
+    }
+}
+
 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
 {
     MachineState *ms = MACHINE(vms);
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
     /* We know for sure that at least the memory fits in the PA space */
     vms->highest_gpa = memtop - 1;
 
-    for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
-        hwaddr size = extended_memmap[i].size;
-        bool fits;
-
-        base = ROUND_UP(base, size);
-        vms->memmap[i].base = base;
-        vms->memmap[i].size = size;
-
-        /*
-         * Check each device to see if they fit in the PA space,
-         * moving highest_gpa as we go.
-         *
-         * For each device that doesn't fit, disable it.
-         */
-        fits = (base + size) <= BIT_ULL(pa_bits);
-        if (fits) {
-            vms->highest_gpa = base + size - 1;
-        }
-
-        switch (i) {
-        case VIRT_HIGH_GIC_REDIST2:
-            vms->highmem_redists &= fits;
-            break;
-        case VIRT_HIGH_PCIE_ECAM:
-            vms->highmem_ecam &= fits;
-            break;
-        case VIRT_HIGH_PCIE_MMIO:
-            vms->highmem_mmio &= fits;
-            break;
-        }
-
-        base += size;
-    }
+    virt_set_high_memmap(vms, base, pa_bits);
 
     if (device_memory_size > 0) {
         ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This renames variable 'size' to 'region_size' in virt_set_high_memmap().
Its counterpart ('region_base') will be introduced in next patch.

No functional change intended.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-3-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
 static void virt_set_high_memmap(VirtMachineState *vms,
                                  hwaddr base, int pa_bits)
 {
+    hwaddr region_size;
+    bool fits;
     int i;
 
     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
-        hwaddr size = extended_memmap[i].size;
-        bool fits;
+        region_size = extended_memmap[i].size;
 
-        base = ROUND_UP(base, size);
+        base = ROUND_UP(base, region_size);
         vms->memmap[i].base = base;
-        vms->memmap[i].size = size;
+        vms->memmap[i].size = region_size;
 
         /*
          * Check each device to see if they fit in the PA space,
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
          *
          * For each device that doesn't fit, disable it.
          */
-        fits = (base + size) <= BIT_ULL(pa_bits);
+        fits = (base + region_size) <= BIT_ULL(pa_bits);
         if (fits) {
-            vms->highest_gpa = base + size - 1;
+            vms->highest_gpa = base + region_size - 1;
         }
 
         switch (i) {
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
             break;
         }
 
-        base += size;
+        base += region_size;
     }
 }
 
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This introduces variable 'region_base' for the base address of the
specific high memory region. It's the preparatory work to optimize
high memory region address assignment.

No functional change intended.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-4-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
 static void virt_set_high_memmap(VirtMachineState *vms,
                                  hwaddr base, int pa_bits)
 {
-    hwaddr region_size;
+    hwaddr region_base, region_size;
     bool fits;
     int i;
 
     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
+        region_base = ROUND_UP(base, extended_memmap[i].size);
         region_size = extended_memmap[i].size;
 
-        base = ROUND_UP(base, region_size);
-        vms->memmap[i].base = base;
+        vms->memmap[i].base = region_base;
         vms->memmap[i].size = region_size;
 
         /*
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
          *
          * For each device that doesn't fit, disable it.
          */
-        fits = (base + region_size) <= BIT_ULL(pa_bits);
+        fits = (region_base + region_size) <= BIT_ULL(pa_bits);
         if (fits) {
-            vms->highest_gpa = base + region_size - 1;
+            vms->highest_gpa = region_base + region_size - 1;
         }
 
         switch (i) {
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
             break;
         }
 
-        base += region_size;
+        base = region_base + region_size;
     }
 }
 
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

This introduces virt_get_high_memmap_enabled() helper, which returns
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
be used in the subsequent patches.

No functional change intended.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-5-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 32 +++++++++++++++++++-------------
 1 file changed, 19 insertions(+), 13 deletions(-)

From: Gavin Shan <gshan@redhat.com>

There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several cases.

(1) One specific high memory region is likely to be disabled by
    code by toggling vms->highmem_{redists, ecam, mmio}.

(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
    'virt-2.12' or ealier than it.

(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
    on 32-bits system.

(4) One specific high memory region is disabled when it breaks the
    PA space limit.

The current implementation of virt_set_{memmap, high_memmap}() isn't
optimized because the high memory region's PA space is always reserved,
regardless of whatever the actual state in the corresponding
vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and
'vms->highest_gpa' are always increased for case (1), (2) and (3).
It's unnecessary since the assigned PA space for the disabled high
memory region won't be used afterwards.

Improve the address assignment for those three high memory region by
skipping the address assignment for one specific high memory region if
it has been disabled in case (1), (2) and (3). The memory layout may
be changed after the improvement is applied, which leads to potential
migration breakage. So 'vms->highmem_compact' is added to control if
the improvement should be applied. For now, 'vms->highmem_compact' is
set to false, meaning that we don't have memory layout change until it
becomes configurable through property 'compact-highmem' in next patch.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-6-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  1 +
 hw/arm/virt.c         | 15 ++++++++++-----
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
     PFlashCFI01 *flash[2];
     bool secure;
     bool highmem;
+    bool highmem_compact;
     bool highmem_ecam;
     bool highmem_mmio;
     bool highmem_redists;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
         vms->memmap[i].size = region_size;
 
         /*
-         * Check each device to see if they fit in the PA space,
-         * moving highest_gpa as we go.
+         * Check each device to see if it fits in the PA space,
+         * moving highest_gpa as we go. For compatibility, move
+         * highest_gpa for disabled fitting devices as well, if
+         * the compact layout has been disabled.
          *
          * For each device that doesn't fit, disable it.
          */
         fits = (region_base + region_size) <= BIT_ULL(pa_bits);
-        if (fits) {
-            vms->highest_gpa = region_base + region_size - 1;
+        *region_enabled &= fits;
+        if (vms->highmem_compact && !*region_enabled) {
+            continue;
         }
 
-        *region_enabled &= fits;
         base = region_base + region_size;
+        if (fits) {
+            vms->highest_gpa = base - 1;
+        }
     }
 }
 
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled or enabled when the optimization is applied or not, with
the following configuration. The configuration is only achievable by
modifying the source code until more properties are added to allow
users selectively disable those high memory regions.

pa_bits              = 40;
  vms->highmem_redists = false;
  vms->highmem_ecam    = false;
  vms->highmem_mmio    = true;

# qemu-system-aarch64 -accel kvm -cpu host    \
    -machine virt-7.2,compact-highmem={on, off} \
    -m 4G,maxmem=511G -monitor stdio

Region             compact-highmem=off         compact-highmem=on
  ----------------------------------------------------------------
  MEM                [1GB         512GB]        [1GB         512GB]
  HIGH_GIC_REDISTS2  [512GB       512GB+64MB]   [disabled]
  HIGH_PCIE_ECAM     [512GB+256MB 512GB+512MB]  [disabled]
  HIGH_PCIE_MMIO     [disabled]                 [512GB       1TB]

In order to keep backwords compatibility, we need to disable the
optimization on machine, which is virt-7.1 or ealier than it. It
means the optimization is enabled by default from virt-7.2. Besides,
'compact-highmem' property is added so that the optimization can be
explicitly enabled or disabled on all machine types by users.

Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-id: 20221029224307.138822-7-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  4 ++++
 include/hw/arm/virt.h    |  1 +
 hw/arm/virt.c            | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ highmem
   address space above 32 bits. The default is ``on`` for machine types
   later than ``virt-2.12``.
 
+compact-highmem
+  Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
+  The default is ``on`` for machine types later than ``virt-7.2``.
+
 gic-version
   Specify the version of the Generic Interrupt Controller (GIC) to provide.
   Valid values are:
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
     bool no_pmu;
     bool claim_edge_triggered_timers;
     bool smbios_old_sys_ver;
+    bool no_highmem_compact;
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 have no support for ACPI GED device */
     bool kvm_no_adjvtime;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
  * Note the extended_memmap is sized so that it eventually also includes the
  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
  * index of base_memmap).
+ *
+ * The memory map for these Highmem IO Regions can be in legacy or compact
+ * layout, depending on 'compact-highmem' property. With legacy layout, the
+ * PA space for one specific region is always reserved, even if the region
+ * has been disabled or doesn't fit into the PA space. However, the PA space
+ * for the region won't be reserved in these circumstances with compact layout.
  */
 static MemMapEntry extended_memmap[] = {
     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
@@ -XXX,XX +XXX,XX @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
     vms->highmem = value;
 }
 
+static bool virt_get_compact_highmem(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->highmem_compact;
+}
+
+static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->highmem_compact = value;
+}
+
 static bool virt_get_its(Object *obj, Error **errp)
 {
     VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
                                           "Set on/off to enable/disable using "
                                           "physical address space above 32 bits");
 
+    object_class_property_add_bool(oc, "compact-highmem",
+                                   virt_get_compact_highmem,
+                                   virt_set_compact_highmem);
+    object_class_property_set_description(oc, "compact-highmem",
+                                          "Set on/off to enable/disable compact "
+                                          "layout for high memory regions");
+
     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
                                   virt_set_gic_version);
     object_class_property_set_description(oc, "gic-version",
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
 
     /* High memory is enabled by default */
     vms->highmem = true;
+    vms->highmem_compact = !vmc->no_highmem_compact;
     vms->gic_version = VIRT_GIC_VERSION_NOSEL;
 
     vms->highmem_ecam = !vmc->no_highmem_ecam;
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
 
 static void virt_machine_7_1_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_7_2_options(mc);
     compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
+    /* Compact layout for high memory regions was introduced with 7.2 */
+    vmc->no_highmem_compact = true;
 }
 DEFINE_VIRT_MACHINE(7, 1)
 
-- 
2.25.1

From: Gavin Shan <gshan@redhat.com>

The 3 high memory regions are usually enabled by default, but they may
be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
This leads to waste in the PA space.

Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
allow users selectively disable them if needed. After that, the high
memory region for GICv3 or GICv4 redistributor can be disabled by user,
the number of maximal supported CPUs needs to be calculated based on
'vms->highmem_redists'. The follow-up error message is also improved
to indicate if the high memory region for GICv3 and GICv4 has been
enabled or not.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221029224307.138822-8-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst | 13 +++++++
 hw/arm/virt.c            | 75 ++++++++++++++++++++++++++++++++++++++--
 2 files changed, 86 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ compact-highmem
   Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
   The default is ``on`` for machine types later than ``virt-7.2``.
 
+highmem-redists
+  Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
+  GICv4 redistributor. The default is ``on``. Setting this to ``off`` will
+  limit the maximum number of CPUs when GICv3 or GICv4 is used.
+
+highmem-ecam
+  Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
+  The default is ``on`` for machine types later than ``virt-3.0``.
+
+highmem-mmio
+  Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
+  The default is ``on``.
+
 gic-version
   Specify the version of the Generic Interrupt Controller (GIC) to provide.
   Valid values are:
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     if (vms->gic_version == VIRT_GIC_VERSION_2) {
         virt_max_cpus = GIC_NCPU;
     } else {
-        virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
-            virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
+        virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
+        if (vms->highmem_redists) {
+            virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
+        }
     }
 
     if (max_cpus > virt_max_cpus) {
         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
                      "supported by machine 'mach-virt' (%d)",
                      max_cpus, virt_max_cpus);
+        if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
+            error_printf("Try 'highmem-redists=on' for more CPUs\n");
+        }
+
         exit(1);
     }
 
@@ -XXX,XX +XXX,XX @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
     vms->highmem_compact = value;
 }
 
+static bool virt_get_highmem_redists(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->highmem_redists;
+}
+
+static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->highmem_redists = value;
+}
+
+static bool virt_get_highmem_ecam(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->highmem_ecam;
+}
+
+static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->highmem_ecam = value;
+}
+
+static bool virt_get_highmem_mmio(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->highmem_mmio;
+}
+
+static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->highmem_mmio = value;
+}
+
+
 static bool virt_get_its(Object *obj, Error **errp)
 {
     VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
                                           "Set on/off to enable/disable compact "
                                           "layout for high memory regions");
 
+    object_class_property_add_bool(oc, "highmem-redists",
+                                   virt_get_highmem_redists,
+                                   virt_set_highmem_redists);
+    object_class_property_set_description(oc, "highmem-redists",
+                                          "Set on/off to enable/disable high "
+                                          "memory region for GICv3 or GICv4 "
+                                          "redistributor");
+
+    object_class_property_add_bool(oc, "highmem-ecam",
+                                   virt_get_highmem_ecam,
+                                   virt_set_highmem_ecam);
+    object_class_property_set_description(oc, "highmem-ecam",
+                                          "Set on/off to enable/disable high "
+                                          "memory region for PCI ECAM");
+
+    object_class_property_add_bool(oc, "highmem-mmio",
+                                   virt_get_highmem_mmio,
+                                   virt_set_highmem_mmio);
+    object_class_property_set_description(oc, "highmem-mmio",
+                                          "Set on/off to enable/disable high "
+                                          "memory region for PCI MMIO");
+
     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
                                   virt_set_gic_version);
     object_class_property_set_description(oc, "gic-version",
-- 
2.25.1

From: Mihai Carabas <mihai.carabas@oracle.com>

Use the base_memmap to build the SMBIOS 19 table which provides the address
mapping for a Physical Memory Array (from spec [1] chapter 7.20).

This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
("SMBIOS: Build aggregate smbios tables and entry point").

[1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf

The absence of this table is a breach of the specs and is
detected by the FirmwareTestSuite (FWTS), but it doesn't
cause any known problems for guest OSes.

Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
 static void virt_build_smbios(VirtMachineState *vms)
 {
     MachineClass *mc = MACHINE_GET_CLASS(vms);
+    MachineState *ms = MACHINE(vms);
     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
     uint8_t *smbios_tables, *smbios_anchor;
     size_t smbios_tables_len, smbios_anchor_len;
+    struct smbios_phys_mem_area mem_array;
     const char *product = "QEMU Virtual Machine";
 
     if (kvm_enabled()) {
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(VirtMachineState *vms)
                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
                         true, SMBIOS_ENTRY_POINT_TYPE_64);
 
-    smbios_get_tables(MACHINE(vms), NULL, 0,
+    /* build the array of physical mem area from base_memmap */
+    mem_array.address = vms->memmap[VIRT_MEM].base;
+    mem_array.length = ms->ram_size;
+
+    smbios_get_tables(ms, &mem_array, 1,
                       &smbios_tables, &smbios_tables_len,
                       &smbios_anchor, &smbios_anchor_len,
                       &error_fatal);
-- 
2.25.1

From: Timofey Kutergin <tkutergin@gmail.com>

The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
it supports the Privileged Access Never (PAN) feature. Add
a model of this CPU, so you can use a CPU type on the virt
board that models a specific real hardware CPU, rather than
having to use the QEMU-specific "max" CPU type.

Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
Message-id: 20221121150819.2782817-1-tkutergin@gmail.com
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/virt.rst |  1 +
 hw/arm/virt.c            |  1 +
 target/arm/cpu64.c       | 69 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
 - ``cortex-a15`` (32-bit; the default)
 - ``cortex-a35`` (64-bit)
 - ``cortex-a53`` (64-bit)
+- ``cortex-a55`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
 - ``cortex-a76`` (64-bit)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a15"),
     ARM_CPU_TYPE_NAME("cortex-a35"),
     ARM_CPU_TYPE_NAME("cortex-a53"),
+    ARM_CPU_TYPE_NAME("cortex-a55"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a76"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     define_cortex_a72_a57_a53_cp_reginfo(cpu);
 }
 
+static void aarch64_a55_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a55";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /* Ordered by B2.4 AArch64 registers by functional group */
+    cpu->clidr = 0x82000023;
+    cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->isar.id_aa64dfr0  = 0x0000000010305408ull;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+    cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+    cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+    cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+    cpu->isar.id_aa64pfr0  = 0x0000000010112222ull;
+    cpu->isar.id_aa64pfr1  = 0x0000000000000010ull;
+    cpu->id_afr0       = 0x00000000;
+    cpu->isar.id_dfr0  = 0x04010088;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x01011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_mmfr0 = 0x10201105;
+    cpu->isar.id_mmfr1 = 0x40000000;
+    cpu->isar.id_mmfr2 = 0x01260000;
+    cpu->isar.id_mmfr3 = 0x02122211;
+    cpu->isar.id_mmfr4 = 0x00021110;
+    cpu->isar.id_pfr0  = 0x10010131;
+    cpu->isar.id_pfr1  = 0x00011011;
+    cpu->isar.id_pfr2  = 0x00000011;
+    cpu->midr = 0x412FD050;          /* r2p0 */
+    cpu->revidr = 0;
+
+    /* From B2.23 CCSIDR_EL1 */
+    cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
+    cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
+
+    /* From B2.96 SCTLR_EL3 */
+    cpu->reset_sctlr = 0x30c50838;
+
+    /* From B4.45 ICH_VTR_EL2 */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    cpu->gic_pribits = 5;
+
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+
+    /* From D5.4 AArch64 PMU register summary */
+    cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
 static void aarch64_a72_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a35",         .initfn = aarch64_a35_initfn },
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
+    { .name = "cortex-a55",         .initfn = aarch64_a55_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
-- 
2.25.1

From: Luke Starrett <lukes@xsightlabs.com>

The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
register:

"indicates the maximum SPI INTID that the GIC implementation supports"

As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
for the internal 16x SGI's and 16x PPI's.  However, the original GICv3
model subtracted off the SGI/PPI.  Cosmetically this can be seen at OS
boot (Linux) showing 32 shy of what should be there, i.e.:

[    0.000000] GICv3: 224 SPIs implemented

Though in hw/arm/virt.c, the machine is configured for 256 SPI's.  ARM
virt machine likely doesn't have a problem with this because the upper
32 IRQ's don't actually have anything meaningful wired. But, this does
become a functional issue on a custom use case which wants to make use
of these IRQ's.  Additionally, boot code (i.e. TF-A) will only init up
to the number (blocks of 32) that it believes to actually be there.

Signed-off-by: Luke Starrett <lukes@xsightlabs.com>
Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_dist.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_dist.c
+++ b/hw/intc/arm_gicv3_dist.c
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
          * MBIS == 0 (message-based SPIs not supported)
          * SecurityExtn == 1 if security extns supported
          * CPUNumber == 0 since for us ARE is always 1
-         * ITLinesNumber == (num external irqs / 32) - 1
+         * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
          */
-        int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
+        int itlinesnumber = (s->num_irq / 32) - 1;
         /*
          * SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
          * "security extensions not supported" always implies DS == 1,
-- 
2.25.1

FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
TICAB, TOCU and TID4.  These allow the guest to enable trapping of
various EL1 instructions to EL2.  In this commit, add the necessary
code to allow the guest to set these bits if the feature is present;
because the bit is always zero when the feature isn't present we
won't need to use explicit feature checks in the "trap on condition"
tests in the following commits.

Note that although full implementation of the feature (mandatory from
Armv8.5 onward) requires all five trap bits, the ID registers permit
a value indicating that only TICAB, TOCU and TID4 are implemented,
which might be the case for CPUs between Armv8.2 and Armv8.5.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 30 ++++++++++++++++++++++++++++++
 target/arm/helper.c |  6 ++++++
 2 files changed, 36 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
 }
 
+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
+}
+
+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
+}
+
 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
 {
     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
 }
 
+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
+}
+
+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
+}
+
 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id)
     return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
 }
 
+static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
+}
+
+static inline bool isar_feature_any_evt(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
         }
     }
 
+    if (cpu_isar_feature(any_evt, cpu)) {
+        valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4;
+    } else if (cpu_isar_feature(any_half_evt, cpu)) {
+        valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
+    }
+
     /* Clear RES0 bits.  */
     value &= valid_mask;
 
-- 
2.25.1

For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
TLB maintenance instructions that operate on the inner shareable
domain:

AArch64:
 TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
 TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
 TLBI RVALE1IS, and TLBI RVAALE1IS.

AArch32:
 TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
 and TLBIMVAALIS.

Add the trapping support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 43 +++++++++++++++++++++++++++----------------
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
     return CP_ACCESS_OK;
 }
 
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
+static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
+                                    bool isread)
+{
+    if (arm_current_el(env) == 1 &&
+        (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
+        return CP_ACCESS_TRAP_EL2;
+    }
+    return CP_ACCESS_OK;
+}
+
 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
     /* 32 bit TLB invalidates, Inner Shareable */
     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbiall_is_write },
     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbimva_is_write },
     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbiasid_is_write },
     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbimvaa_is_write },
 };
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     /* TLBI operations */
     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
 #endif
     /* TLB invalidate last level of translation table walk */
     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbimva_is_write },
     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
-      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
+      .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
       .writefn = tlbimvaa_is_write },
     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
       .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
 static const ARMCPRegInfo tlbirange_reginfo[] = {
     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
-      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
-- 
2.25.1

For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
use of TLB maintenance instructions that operate on the
outer shareable domain:

TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
TLBI RVALE1OS, and TLBI RVAALE1OS.

(There are no AArch32 outer-shareable TLB maintenance ops.)

Implement the trapping.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
and IC IALLUIS cache maintenance instructions.

The HCR_EL2.TOCU bit traps all the other cache maintenance
instructions that operate to the point of unification:
 AArch64 IC IVAU, IC IALLU, DC CVAU
 AArch32 ICIMVAU, ICIALLU, DCCMVAU

The two trap bits between them cover all of the cache maintenance
instructions which must also check the HCR_TPU flag.  Turn the old
aa64_cacheop_pou_access() function into a helper function which takes
the set of HCR_EL2 flags to check as an argument, and call it from
new access_ticab() and access_tocu() functions as appropriate for
each cache op.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 36 +++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
     return CP_ACCESS_OK;
 }
 
-static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
-                                              const ARMCPRegInfo *ri,
-                                              bool isread)
+static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
 {
     /* Cache invalidate/clean to Point of Unification... */
     switch (arm_current_el(env)) {
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
         }
         /* fall through */
     case 1:
-        /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set.  */
-        if (arm_hcr_el2_eff(env) & HCR_TPU) {
+        /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set.  */
+        if (arm_hcr_el2_eff(env) & hcrflags) {
             return CP_ACCESS_TRAP_EL2;
         }
         break;
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
     return CP_ACCESS_OK;
 }
 
+static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   bool isread)
+{
+    return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
+}
+
+static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  bool isread)
+{
+    return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
+}
+
 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
  * Page D4-1736 (DDI0487A.b)
  */
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_pou_access },
+      .accessfn = access_ticab },
     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
       .access = PL1_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_pou_access },
+      .accessfn = access_tocu },
     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_pou_access },
+      .accessfn = access_tocu },
     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
       .access = PL1_W, .accessfn = aa64_cacheop_poc_access,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
-      .accessfn = aa64_cacheop_pou_access },
+      .accessfn = access_tocu },
     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
       .access = PL0_W, .type = ARM_CP_NOP,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbiipas2is_hyp_write },
     /* 32 bit cache operations */
     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W },
     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
-      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
       .type = ARM_CP_NOP, .access = PL1_W },
     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
-      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
+      .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
-- 
2.25.1

For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
their AArch32 equivalents).  This is a subset of the registers
trapped by HCR_EL2.TID2, which includes all of these and also the
CTR_EL0 register.

Our implementation already uses a separate access function for
CTR_EL0 (ctr_el0_access()), so all of the registers currently using
access_aa64_tid2() should also be checking TID4.  Make that function
check both TID2 and TID4, and rename it appropriately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
     scr_write(env, ri, 0);
 }
 
-static CPAccessResult access_aa64_tid2(CPUARMState *env,
-                                       const ARMCPRegInfo *ri,
-                                       bool isread)
+static CPAccessResult access_tid4(CPUARMState *env,
+                                  const ARMCPRegInfo *ri,
+                                  bool isread)
 {
-    if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
+    if (arm_current_el(env) == 1 &&
+        (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
         return CP_ACCESS_TRAP_EL2;
     }
 
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
       .access = PL1_R,
-      .accessfn = access_aa64_tid2,
+      .accessfn = access_tid4,
       .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
       .access = PL1_RW,
-      .accessfn = access_aa64_tid2,
+      .accessfn = access_tid4,
       .writefn = csselr_write, .resetvalue = 0,
       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
                              offsetof(CPUARMState, cp15.csselr_ns) } },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
     { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
       .access = PL1_R,
-      .accessfn = access_aa64_tid2,
+      .accessfn = access_tid4,
       .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
 };
 
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
             .access = PL1_R, .type = ARM_CP_CONST,
-            .accessfn = access_aa64_tid2,
+            .accessfn = access_tid4,
             .resetvalue = cpu->clidr
         };
         define_one_arm_cp_reg(cpu, &clidr);
-- 
2.25.1

Update the ID registers for TCG's '-cpu max' to report the
FEAT_EVT Enhanced Virtualization Traps support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/cpu64.c            | 1 +
 target/arm/cpu_tcg.c          | 1 +
 3 files changed, 3 insertions(+)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_DoubleFault (Double Fault Extension)
 - FEAT_E0PD (Preventing EL0 access to halves of address maps)
 - FEAT_ETS (Enhanced Translation Synchronization)
+- FEAT_EVT (Enhanced Virtualization Traps)
 - FEAT_FCMA (Floating-point complex number instructions)
 - FEAT_FHM (Floating-point half-precision multiplication instructions)
 - FEAT_FP16 (Half-precision floating-point data processing)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1);      /* FEAT_S2FWB */
     t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1);      /* FEAT_TTL */
     t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2);      /* FEAT_BBM at level 2 */
+    t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2);      /* FEAT_EVT */
     t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1);     /* FEAT_E0PD */
     cpu->isar.id_aa64mmfr2 = t;
 
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+    t = FIELD_DP32(t, ID_MMFR4, EVT, 2);          /* FEAT_EVT */
     cpu->isar.id_mmfr4 = t;
 
     t = cpu->isar.id_mmfr5;
-- 
2.25.1

Convert the TYPE_ARM_SMMU device to 3-phase reset.  The legacy method
doesn't do anything that's invalid in the hold phase, so the
conversion is simple and not a behaviour change.

Note that we must convert this base class before we can convert the
TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable
handles "chain to parent class reset" when the base class is 3-phase
and the subclass is still using legacy reset, but not the other way
around.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
---
 hw/arm/smmu-common.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
     }
 }
 
-static void smmu_base_reset(DeviceState *dev)
+static void smmu_base_reset_hold(Object *obj)
 {
-    SMMUState *s = ARM_SMMU(dev);
+    SMMUState *s = ARM_SMMU(obj);
 
     g_hash_table_remove_all(s->configs);
     g_hash_table_remove_all(s->iotlb);
@@ -XXX,XX +XXX,XX @@ static Property smmu_dev_properties[] = {
 static void smmu_base_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
 
     device_class_set_props(dc, smmu_dev_properties);
     device_class_set_parent_realize(dc, smmu_base_realize,
                                     &sbc->parent_realize);
-    dc->reset = smmu_base_reset;
+    rc->phases.hold = smmu_base_reset_hold;
 }
 
 static const TypeInfo smmu_base_info = {
-- 
2.25.1

Convert the TYPE_ARM_SMMUV3 device to 3-phase reset.  The legacy
reset method doesn't do anything that's invalid in the hold phase, so
the conversion only requires changing it to a hold phase method, and
using the 3-phase versions of the "save the parent reset method and
chain to it" code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
---
 include/hw/arm/smmuv3.h |  2 +-
 hw/arm/smmuv3.c         | 12 ++++++++----
 2 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
     /*< public >*/
 
     DeviceRealize parent_realize;
-    DeviceReset   parent_reset;
+    ResettablePhases parent_phases;
 };
 
 #define TYPE_ARM_SMMUV3   "arm-smmuv3"
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
     }
 }
 
-static void smmu_reset(DeviceState *dev)
+static void smmu_reset_hold(Object *obj)
 {
-    SMMUv3State *s = ARM_SMMUV3(dev);
+    SMMUv3State *s = ARM_SMMUV3(obj);
     SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
 
-    c->parent_reset(dev);
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj);
+    }
 
     smmuv3_init_regs(s);
 }
@@ -XXX,XX +XXX,XX @@ static void smmuv3_instance_init(Object *obj)
 static void smmuv3_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
 
     dc->vmsd = &vmstate_smmuv3;
-    device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
+    resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
+                                       &c->parent_phases);
     c->parent_realize = dc->realize;
     dc->realize = smmu_realize;
 }
-- 
2.25.1

Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset.  This is a
simple no-behaviour-change conversion.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org
---
 hw/intc/arm_gic_common.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
     }
 }
 
-static void arm_gic_common_reset(DeviceState *dev)
+static void arm_gic_common_reset_hold(Object *obj)
 {
-    GICState *s = ARM_GIC_COMMON(dev);
+    GICState *s = ARM_GIC_COMMON(obj);
     int i, j;
     int resetprio;
 
@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {
 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 
-    dc->reset = arm_gic_common_reset;
+    rc->phases.hold = arm_gic_common_reset_hold;
     dc->realize = arm_gic_common_realize;
     device_class_set_props(dc, arm_gic_common_properties);
     dc->vmsd = &vmstate_gic;
-- 
2.25.1

Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
TYPE_ARM_GIC_KVM subclass to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org
---
 hw/intc/arm_gic_kvm.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
 struct KVMARMGICClass {
     ARMGICCommonClass parent_class;
     DeviceRealize parent_realize;
-    void (*parent_reset)(DeviceState *dev);
+    ResettablePhases parent_phases;
 };
 
 void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s)
     }
 }
 
-static void kvm_arm_gic_reset(DeviceState *dev)
+static void kvm_arm_gic_reset_hold(Object *obj)
 {
-    GICState *s = ARM_GIC_COMMON(dev);
+    GICState *s = ARM_GIC_COMMON(obj);
     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 
-    kgc->parent_reset(dev);
+    if (kgc->parent_phases.hold) {
+        kgc->parent_phases.hold(obj);
+    }
 
     if (kvm_arm_gic_can_save_restore(s)) {
         kvm_arm_gic_put(s);
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
     KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
 
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
     agcc->post_load = kvm_arm_gic_put;
     device_class_set_parent_realize(dc, kvm_arm_gic_realize,
                                     &kgc->parent_realize);
-    device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL,
+                                       &kgc->parent_phases);
 }
 
 static const TypeInfo kvm_arm_gic_info = {
-- 
2.25.1

Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_common.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj)
     g_free(s->redist_region_count);
 }
 
-static void arm_gicv3_common_reset(DeviceState *dev)
+static void arm_gicv3_common_reset_hold(Object *obj)
 {
-    GICv3State *s = ARM_GICV3_COMMON(dev);
+    GICv3State *s = ARM_GICV3_COMMON(obj);
     int i;
 
     for (i = 0; i < s->num_cpu; i++) {
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
 
-    dc->reset = arm_gicv3_common_reset;
+    rc->phases.hold = arm_gicv3_common_reset_hold;
     dc->realize = arm_gicv3_common_realize;
     device_class_set_props(dc, arm_gicv3_common_properties);
     dc->vmsd = &vmstate_gicv3;
-- 
2.25.1

Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_kvm.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
 struct KVMARMGICv3Class {
     ARMGICv3CommonClass parent_class;
     DeviceRealize parent_realize;
-    void (*parent_reset)(DeviceState *dev);
+    ResettablePhases parent_phases;
 };
 
 static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
     c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
 }
 
-static void kvm_arm_gicv3_reset(DeviceState *dev)
+static void kvm_arm_gicv3_reset_hold(Object *obj)
 {
-    GICv3State *s = ARM_GICV3_COMMON(dev);
+    GICv3State *s = ARM_GICV3_COMMON(obj);
     KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
 
     DPRINTF("Reset\n");
 
-    kgc->parent_reset(dev);
+    if (kgc->parent_phases.hold) {
+        kgc->parent_phases.hold(obj);
+    }
 
     if (s->migration_blocker) {
         DPRINTF("Cannot put kernel gic state, no kernel interface\n");
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
     KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
 
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
     agcc->post_load = kvm_arm_gicv3_put;
     device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
                                     &kgc->parent_realize);
-    device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL,
+                                       &kgc->parent_phases);
 }
 
 static const TypeInfo kvm_arm_gicv3_info = {
-- 
2.25.1

Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_its_common.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_its_common.c
+++ b/hw/intc/arm_gicv3_its_common.c
@@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
     msi_nonbroken = true;
 }
 
-static void gicv3_its_common_reset(DeviceState *dev)
+static void gicv3_its_common_reset_hold(Object *obj)
 {
-    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
 
     s->ctlr = 0;
     s->cbaser = 0;
@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
 static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
-    dc->reset = gicv3_its_common_reset;
+    rc->phases.hold = gicv3_its_common_reset_hold;
     dc->vmsd = &vmstate_its;
 }
 
-- 
2.25.1

Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_its.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_its.c
+++ b/hw/intc/arm_gicv3_its.c
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
 
 struct GICv3ITSClass {
     GICv3ITSCommonClass parent_class;
-    void (*parent_reset)(DeviceState *dev);
+    ResettablePhases parent_phases;
 };
 
 /*
@@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
     }
 }
 
-static void gicv3_its_reset(DeviceState *dev)
+static void gicv3_its_reset_hold(Object *obj)
 {
-    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
     GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
 
-    c->parent_reset(dev);
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj);
+    }
 
     /* Quiescent bit reset to 1 */
     s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
@@ -XXX,XX +XXX,XX @@ static Property gicv3_its_props[] = {
 static void gicv3_its_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
     GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
 
     dc->realize = gicv3_arm_its_realize;
     device_class_set_props(dc, gicv3_its_props);
-    device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
+    resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL,
+                                       &ic->parent_phases);
     icc->post_load = gicv3_its_post_load;
 }
 
-- 
2.25.1

Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
 
 struct KVMARMITSClass {
     GICv3ITSCommonClass parent_class;
-    void (*parent_reset)(DeviceState *dev);
+    ResettablePhases parent_phases;
 };
 
 
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
                       GITS_CTLR, &s->ctlr, true, &error_abort);
 }
 
-static void kvm_arm_its_reset(DeviceState *dev)
+static void kvm_arm_its_reset_hold(Object *obj)
 {
-    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
+    GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
     KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
     int i;
 
-    c->parent_reset(dev);
+    if (c->parent_phases.hold) {
+        c->parent_phases.hold(obj);
+    }
 
     if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
                                KVM_DEV_ARM_ITS_CTRL_RESET)) {
@@ -XXX,XX +XXX,XX @@ static Property kvm_arm_its_props[] = {
 static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
     KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
 
     dc->realize = kvm_arm_its_realize;
     device_class_set_props(dc, kvm_arm_its_props);
-    device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
+    resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
+                                       &ic->parent_phases);
     icc->send_msi = kvm_its_send_msi;
     icc->pre_save = kvm_arm_its_pre_save;
     icc->post_load = kvm_arm_its_post_load;
-- 
2.25.1

From: Schspa Shi <schspa@gmail.com>

We use 32bit value for linux,initrd-[start/end], when we have
loader_start > 4GB, there will be a wrong initrd_start passed
to the kernel, and the kernel will report the following warning.

[    0.000000] ------------[ cut here ]------------
[    0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ...
[    0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G        W          6.1.0-rc3-13250-g30a0b95b1335-dirty #28
[    0.000000] Hardware name: Horizon Sigi Virtual development board (DT)
[    0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    0.000000] pc : arm64_memblock_init+0x158/0x244
[    0.000000] lr : arm64_memblock_init+0x158/0x244
[    0.000000] sp : ffff800009273df0
[    0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000
[    0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000
[    0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000
[    0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020
[    0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261
[    0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000
[    0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000
[    0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69
[    0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88
[    0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056
[    0.000000] Call trace:
[    0.000000]  arm64_memblock_init+0x158/0x244
[    0.000000]  setup_arch+0x164/0x1cc
[    0.000000]  start_kernel+0x94/0x4ac
[    0.000000]  __primary_switched+0xb4/0xbc
[    0.000000] ---[ end trace 0000000000000000 ]---
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000001000000000-0x0000001007ffffff]

This doesn't affect any machine types we currently support, because
for all of our machine types the RAM starts well below the 4GB
mark, but it does demonstrate that we're not currently writing
the device-tree properties quite as intended.

To fix it, we can change it to write these values to the dtb using a
type width matching #address-cells.  This is the intended size for
these dtb properties, and is how u-boot, for instance, writes them,
although in practice the Linux kernel will cope with them being any
width as long as they're big enough to fit the value.

Signed-off-by: Schspa Shi <schspa@gmail.com>
Message-id: 20221129160724.75667-1-schspa@gmail.com
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
     }
 
     if (binfo->initrd_size) {
-        rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
-                                   binfo->initrd_start);
+        rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
+                                          acells, binfo->initrd_start);
         if (rc < 0) {
             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
             goto fail;
         }
 
-        rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
-                                   binfo->initrd_start + binfo->initrd_size);
+        rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
+                                          acells,
+                                          binfo->initrd_start +
+                                          binfo->initrd_size);
         if (rc < 0) {
             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
             goto fail;
-- 
2.25.1

From: Zhuojia Shen <chaosdefinition@hotmail.com>

In CPUID registers exposed to userspace, some registers were missing
and some fields were not exposed.  This patch aligns exposed ID
registers and their fields with what the upstream kernel currently
exposes.

Specifically, the following new ID registers/fields are exposed to
userspace:

ID_AA64PFR1_EL1.BT:       bits 3-0
ID_AA64PFR1_EL1.MTE:      bits 11-8
ID_AA64PFR1_EL1.SME:      bits 27-24

ID_AA64ZFR0_EL1.SVEver:   bits 3-0
ID_AA64ZFR0_EL1.AES:      bits 7-4
ID_AA64ZFR0_EL1.BitPerm:  bits 19-16
ID_AA64ZFR0_EL1.BF16:     bits 23-20
ID_AA64ZFR0_EL1.SHA3:     bits 35-32
ID_AA64ZFR0_EL1.SM4:      bits 43-40
ID_AA64ZFR0_EL1.I8MM:     bits 47-44
ID_AA64ZFR0_EL1.F32MM:    bits 55-52
ID_AA64ZFR0_EL1.F64MM:    bits 59-56

ID_AA64SMFR0_EL1.F32F32:  bit 32
ID_AA64SMFR0_EL1.B16F32:  bit 34
ID_AA64SMFR0_EL1.F16F32:  bit 35
ID_AA64SMFR0_EL1.I8I32:   bits 39-36
ID_AA64SMFR0_EL1.F64F64:  bit 48
ID_AA64SMFR0_EL1.I16I64:  bits 55-52
ID_AA64SMFR0_EL1.FA64:    bit 63

ID_AA64MMFR0_EL1.ECV:     bits 63-60

ID_AA64MMFR1_EL1.AFP:     bits 47-44

ID_AA64MMFR2_EL1.AT:      bits 35-32

ID_AA64ISAR0_EL1.RNDR:    bits 63-60

ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
ID_AA64ISAR1_EL1.BF16:    bits 47-44
ID_AA64ISAR1_EL1.DGH:     bits 51-48
ID_AA64ISAR1_EL1.I8MM:    bits 55-52

ID_AA64ISAR2_EL1.WFxT:    bits 3-0
ID_AA64ISAR2_EL1.RPRES:   bits 7-4
ID_AA64ISAR2_EL1.GPA3:    bits 11-8
ID_AA64ISAR2_EL1.APA3:    bits 15-12

The code is also refactored to use symbolic names for ID register fields
for better readability and maintainability.

Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++--------
 1 file changed, 79 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 #ifdef CONFIG_USER_ONLY
         static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
             { .name = "ID_AA64PFR0_EL1",
-              .exported_bits = 0x000f000f00ff0000,
-              .fixed_bits    = 0x0000000000000011 },
+              .exported_bits = R_ID_AA64PFR0_FP_MASK |
+                               R_ID_AA64PFR0_ADVSIMD_MASK |
+                               R_ID_AA64PFR0_SVE_MASK |
+                               R_ID_AA64PFR0_DIT_MASK,
+              .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) |
+                            (0x1 << R_ID_AA64PFR0_EL1_SHIFT) },
             { .name = "ID_AA64PFR1_EL1",
-              .exported_bits = 0x00000000000000f0 },
+              .exported_bits = R_ID_AA64PFR1_BT_MASK |
+                               R_ID_AA64PFR1_SSBS_MASK |
+                               R_ID_AA64PFR1_MTE_MASK |
+                               R_ID_AA64PFR1_SME_MASK },
             { .name = "ID_AA64PFR*_EL1_RESERVED",
-              .is_glob = true                     },
-            { .name = "ID_AA64ZFR0_EL1"           },
+              .is_glob = true },
+            { .name = "ID_AA64ZFR0_EL1",
+              .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
+                               R_ID_AA64ZFR0_AES_MASK |
+                               R_ID_AA64ZFR0_BITPERM_MASK |
+                               R_ID_AA64ZFR0_BFLOAT16_MASK |
+                               R_ID_AA64ZFR0_SHA3_MASK |
+                               R_ID_AA64ZFR0_SM4_MASK |
+                               R_ID_AA64ZFR0_I8MM_MASK |
+                               R_ID_AA64ZFR0_F32MM_MASK |
+                               R_ID_AA64ZFR0_F64MM_MASK },
+            { .name = "ID_AA64SMFR0_EL1",
+              .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
+                               R_ID_AA64SMFR0_B16F32_MASK |
+                               R_ID_AA64SMFR0_F16F32_MASK |
+                               R_ID_AA64SMFR0_I8I32_MASK |
+                               R_ID_AA64SMFR0_F64F64_MASK |
+                               R_ID_AA64SMFR0_I16I64_MASK |
+                               R_ID_AA64SMFR0_FA64_MASK },
             { .name = "ID_AA64MMFR0_EL1",
-              .fixed_bits    = 0x00000000ff000000 },
-            { .name = "ID_AA64MMFR1_EL1"          },
+              .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
+              .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
+                            (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
+            { .name = "ID_AA64MMFR1_EL1",
+              .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
+            { .name = "ID_AA64MMFR2_EL1",
+              .exported_bits = R_ID_AA64MMFR2_AT_MASK },
             { .name = "ID_AA64MMFR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64DFR0_EL1",
-              .fixed_bits    = 0x0000000000000006 },
-            { .name = "ID_AA64DFR1_EL1"           },
+              .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
+            { .name = "ID_AA64DFR1_EL1" },
             { .name = "ID_AA64DFR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64AFR*",
-              .is_glob = true                     },
+              .is_glob = true },
             { .name = "ID_AA64ISAR0_EL1",
-              .exported_bits = 0x00fffffff0fffff0 },
+              .exported_bits = R_ID_AA64ISAR0_AES_MASK |
+                               R_ID_AA64ISAR0_SHA1_MASK |
+                               R_ID_AA64ISAR0_SHA2_MASK |
+                               R_ID_AA64ISAR0_CRC32_MASK |
+                               R_ID_AA64ISAR0_ATOMIC_MASK |
+                               R_ID_AA64ISAR0_RDM_MASK |
+                               R_ID_AA64ISAR0_SHA3_MASK |
+                               R_ID_AA64ISAR0_SM3_MASK |
+                               R_ID_AA64ISAR0_SM4_MASK |
+                               R_ID_AA64ISAR0_DP_MASK |
+                               R_ID_AA64ISAR0_FHM_MASK |
+                               R_ID_AA64ISAR0_TS_MASK |
+                               R_ID_AA64ISAR0_RNDR_MASK },
             { .name = "ID_AA64ISAR1_EL1",
-              .exported_bits = 0x000000f0ffffffff },
+              .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
+                               R_ID_AA64ISAR1_APA_MASK |
+                               R_ID_AA64ISAR1_API_MASK |
+                               R_ID_AA64ISAR1_JSCVT_MASK |
+                               R_ID_AA64ISAR1_FCMA_MASK |
+                               R_ID_AA64ISAR1_LRCPC_MASK |
+                               R_ID_AA64ISAR1_GPA_MASK |
+                               R_ID_AA64ISAR1_GPI_MASK |
+                               R_ID_AA64ISAR1_FRINTTS_MASK |
+                               R_ID_AA64ISAR1_SB_MASK |
+                               R_ID_AA64ISAR1_BF16_MASK |
+                               R_ID_AA64ISAR1_DGH_MASK |
+                               R_ID_AA64ISAR1_I8MM_MASK },
+            { .name = "ID_AA64ISAR2_EL1",
+              .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
+                               R_ID_AA64ISAR2_RPRES_MASK |
+                               R_ID_AA64ISAR2_GPA3_MASK |
+                               R_ID_AA64ISAR2_APA3_MASK },
             { .name = "ID_AA64ISAR*_EL1_RESERVED",
-              .is_glob = true                     },
+              .is_glob = true },
         };
         modify_arm_cp_regs(v8_idregs, v8_user_idregs);
 #endif
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
 #ifdef CONFIG_USER_ONLY
         static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
             { .name = "MIDR_EL1",
-              .exported_bits = 0x00000000ffffffff },
-            { .name = "REVIDR_EL1"                },
+              .exported_bits = R_MIDR_EL1_REVISION_MASK |
+                               R_MIDR_EL1_PARTNUM_MASK |
+                               R_MIDR_EL1_ARCHITECTURE_MASK |
+                               R_MIDR_EL1_VARIANT_MASK |
+                               R_MIDR_EL1_IMPLEMENTER_MASK },
+            { .name = "REVIDR_EL1" },
         };
         modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
 #endif
-- 
2.25.1

From: Thomas Huth <thuth@redhat.com>

The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
poisoned in common code, so the files that include this header have to
be added to specific_ss and recompiled for each, qemu-system-arm and
qemu-system-aarch64. However, since the kvm headers are only optionally
used in kvm-constants.h for some sanity checks, we can additionally
check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro,
so kvm-constants.h can also be used from "common" files (without the
sanity checks - which should be OK since they are still done from other
target-specific files instead). This way, and by adjusting some other
include statements in the related files here and there, we can move some
files from specific_ss into softmmu_ss, so that they only need to be
compiled once during the build process.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221202154023.293614-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/xlnx-zynqmp-apu-ctrl.h |  2 +-
 target/arm/kvm-consts.h                |  8 ++++----
 hw/misc/imx6_src.c                     |  2 +-
 hw/misc/iotkit-sysctl.c                |  1 -
 hw/misc/meson.build                    | 11 +++++------
 5 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/register.h"
-#include "target/arm/cpu.h"
+#include "target/arm/cpu-qom.h"
 
 #define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -XXX,XX +XXX,XX @@
 #ifndef ARM_KVM_CONSTS_H
 #define ARM_KVM_CONSTS_H
 
+#ifdef NEED_CPU_H
 #ifdef CONFIG_KVM
 #include <linux/kvm.h>
 #include <linux/psci.h>
-
 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
+#endif
+#endif
 
-#else
-
+#ifndef MISMATCH_CHECK
 #define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
-
 #endif
 
 #define CP_REG_SIZE_SHIFT 52
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/main-loop.h"
 #include "qemu/module.h"
-#include "arm-powerctl.h"
+#include "target/arm/arm-powerctl.h"
 #include "hw/core/cpu.h"
 
 #ifndef DEBUG_IMX6_SRC
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "hw/arm/armsse-version.h"
 #include "target/arm/arm-powerctl.h"
-#include "target/arm/cpu.h"
 
 REG32(SECDBGSTAT, 0x0)
 REG32(SECDBGSET, 0x4)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
   'imx25_ccm.c',
   'imx31_ccm.c',
   'imx6_ccm.c',
+  'imx6_src.c',
   'imx6ul_ccm.c',
   'imx7_ccm.c',
   'imx7_gpr.c',
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
 ))
 softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
 specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
 softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
   'xlnx-versal-xramc.c',
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c'))
 softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
 softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
 softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
+softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
 softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
 softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
 softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
 
 specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
 
-specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c'))
-specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
-
 specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
 
 specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
 specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
 
-specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
+softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
 
 # HPPA devices
 softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
-- 
2.25.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

When building with --disable-tcg on Darwin we get:

target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps'
    cc->tcg_ops->do_interrupt(cs);
    ~~~~~~~~~~~^

Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
handler to sysemu") limited this block to system emulation,
but neglected to also limit it to TCG.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Message-id: 20221209110823.59495-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
     arm_rebuild_hflags(env);
 }
 
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 
 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
                                      unsigned int target_el,
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
     cc->tcg_ops->do_interrupt(cs);
     return true;
 }
-#endif /* !CONFIG_USER_ONLY */
+
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 void arm_cpu_update_virq(ARMCPU *cpu)
 {
-- 
2.25.1

The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae:

Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215

for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2:

docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
 * linux-user/aarch64: Choose SYNC as the preferred MTE mode
 * Fix some errors in SVE/SME handling of MTE tags
 * hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
 * hw/block/tc58128: Don't emit deprecation warning under qtest
 * tests/qtest: Fix handling of npcm7xx and GMAC tests
 * hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
 * tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
 * Don't assert on vmload/vmsave of M-profile CPUs
 * hw/arm/smmuv3: add support for stage 1 access fault
 * hw/arm/stellaris: QOM cleanups
 * Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
 * Improve Cortex_R52 IMPDEF sysreg modelling
 * Allow access to SPSR_hyp from hyp mode
 * New board model mps3-an536 (Cortex-R52)

----------------------------------------------------------------
Luc Michel (1):
      hw/arm/smmuv3: add support for stage 1 access fault

Nabih Estefan (1):
      tests/qtest: Fix GMAC test to run on a machine in upstream QEMU

Peter Maydell (22):
      hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses
      hw/block/tc58128: Don't emit deprecation warning under qtest
      tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64
      tests/qtest/bios-tables-test: Allow changes to virt GTDT
      hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ
      tests/qtest/bios-tables-tests: Update virt golden reference
      hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
      tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend
      target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU
      target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
      target/arm: The Cortex-R52 has a read-only CBAR
      target/arm: Add Cortex-R52 IMPDEF sysregs
      target/arm: Allow access to SPSR_hyp from hyp mode
      hw/misc/mps2-scc: Fix condition for CFG3 register
      hw/misc/mps2-scc: Factor out which-board conditionals
      hw/misc/mps2-scc: Make changes needed for AN536 FPGA image
      hw/arm/mps3r: Initial skeleton for mps3-an536 board
      hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM
      hw/arm/mps3r: Add UARTs
      hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices
      hw/arm/mps3r: Add remaining devices
      docs: Add documentation for the mps3-an536 board

Philippe Mathieu-Daudé (5):
      hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC
      hw/arm/stellaris: Convert ADC controller to Resettable interface
      hw/arm/stellaris: Convert I2C controller to Resettable interface
      hw/arm/stellaris: Add missing QOM 'machine' parent
      hw/arm/stellaris: Add missing QOM 'SoC' parent

Richard Henderson (6):
      linux-user/aarch64: Choose SYNC as the preferred MTE mode
      target/arm: Fix nregs computation in do_{ld,st}_zpa
      target/arm: Adjust and validate mtedesc sizem1
      target/arm: Split out make_svemte_desc
      target/arm: Handle mte in do_ldrq, do_ldro
      target/arm: Fix SVE/SME gross MTE suppression checks

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards,
connect FIQ output of the GIC CPU interfaces to the CPU.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240130152548.17855-1-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xilinx_zynq.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
     sysbus_connect_irq(busdev, 0,
                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
+    sysbus_connect_irq(busdev, 1,
+                       qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ));
 
     for (n = 0; n < 64; n++) {
         pic[n] = qdev_get_gpio_in(dev, n);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The API does not generate an error for setting ASYNC | SYNC; that merely
constrains the selection vs the per-cpu default.  For qemu linux-user,
choose SYNC as the default.

Cc: qemu-stable@nongnu.org
Reported-by: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/aarch64/target_prctl.h
+++ b/linux-user/aarch64/target_prctl.h
@@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
     env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
 
     if (cpu_isar_feature(aa64_mte, cpu)) {
-        switch (arg2 & PR_MTE_TCF_MASK) {
-        case PR_MTE_TCF_NONE:
-        case PR_MTE_TCF_SYNC:
-        case PR_MTE_TCF_ASYNC:
-            break;
-        default:
-            return -EINVAL;
-        }
-
         /*
          * Write PR_MTE_TCF to SCTLR_EL1[TCF0].
-         * Note that the syscall values are consistent with hw.
+         *
+         * The kernel has a per-cpu configuration for the sysadmin,
+         * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
+         * which qemu does not implement.
+         *
+         * Because there is no performance difference between the modes, and
+         * because SYNC is most useful for debugging MTE errors, choose SYNC
+         * as the preferred mode.  With this preference, and the way the API
+         * uses only two bits, there is no way for the program to select
+         * ASYMM mode.
          */
-        env->cp15.sctlr_el[1] =
-            deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT);
+        unsigned tcf = 0;
+        if (arg2 & PR_MTE_TCF_SYNC) {
+            tcf = 1;
+        } else if (arg2 & PR_MTE_TCF_ASYNC) {
+            tcf = 2;
+        }
+        env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
 
         /*
          * Write PR_MTE_TAG to GCR_EL1[Exclude].
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The field is encoded as [0-3], which is convenient for
indexing our array of function pointers, but the true
value is [1-4].  Adjust before calling do_mem_zpa.

Add an assert, and move the comment re passing ZT to
the helper back next to the relevant code.

Cc: qemu-stable@nongnu.org
Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-sve.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
     TCGv_ptr t_pg;
     int desc = 0;
 
-    /*
-     * For e.g. LD4, there are not enough arguments to pass all 4
-     * registers as pointers, so encode the regno into the data field.
-     * For consistency, do this even for LD1.
-     */
+    assert(mte_n >= 1 && mte_n <= 4);
     if (s->mte_active[0]) {
         int msz = dtype_msz(dtype);
 
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
         addr = clean_data_tbi(s, addr);
     }
 
+    /*
+     * For e.g. LD4, there are not enough arguments to pass all 4
+     * registers as pointers, so encode the regno into the data field.
+     * For consistency, do this even for LD1.
+     */
     desc = simd_desc(vsz, vsz, zt | desc);
     t_pg = tcg_temp_new_ptr();
 
@@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
      * accessible via the instruction encoding.
      */
     assert(fn != NULL);
-    do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn);
+    do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn);
 }
 
 static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a)
@@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
     if (nreg == 0) {
         /* ST1 */
         fn = fn_single[s->mte_active[0]][be][msz][esz];
-        nreg = 1;
     } else {
         /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */
         assert(msz == esz);
         fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz];
     }
     assert(fn != NULL);
-    do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn);
+    do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn);
 }
 
 static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When we added SVE_MTEDESC_SHIFT, we effectively limited the
maximum size of MTEDESC.  Adjust SIZEM1 to consume the remaining
bits (32 - 10 - 5 - 12 == 5).  Assert that the data to be stored
fits within the field (expecting 8 * 4 - 1 == 31, exact fit).

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h         | 2 +-
 target/arm/tcg/translate-sve.c | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI,   4, 2)
 FIELD(MTEDESC, TCMA,  6, 2)
 FIELD(MTEDESC, WRITE, 8, 1)
 FIELD(MTEDESC, ALIGN, 9, 3)
-FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12)  /* size - 1 */
+FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12)  /* size - 1 */
 
 bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr);
 uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
 {
     unsigned vsz = vec_full_reg_size(s);
     TCGv_ptr t_pg;
+    uint32_t sizem1;
     int desc = 0;
 
     assert(mte_n >= 1 && mte_n <= 4);
+    sizem1 = (mte_n << dtype_msz(dtype)) - 1;
+    assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
     if (s->mte_active[0]) {
-        int msz = dtype_msz(dtype);
-
         desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
         desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
         desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1);
+        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
         desc <<= SVE_MTEDESC_SHIFT;
     } else {
         addr = clean_data_tbi(s, addr);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Share code that creates mtedesc and embeds within simd_desc.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-a64.h |  2 ++
 target/arm/tcg/translate-sme.c | 15 +++--------
 target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++----------------
 3 files changed, 31 insertions(+), 33 deletions(-)

diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.h
+++ b/target/arm/tcg/translate-a64.h
@@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
 bool sve_access_check(DisasContext *s);
 bool sme_enabled_check(DisasContext *s);
 bool sme_enabled_check_with_svcr(DisasContext *s, unsigned);
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
+                          uint32_t msz, bool is_write, uint32_t data);
 
 /* This function corresponds to CheckStreamingSVEEnabled. */
 static inline bool sme_sm_enabled_check(DisasContext *s)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
 
     TCGv_ptr t_za, t_pg;
     TCGv_i64 addr;
-    int svl, desc = 0;
+    uint32_t desc;
     bool be = s->be_data == MO_BE;
     bool mte = s->mte_active[0];
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
     tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz);
     tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
 
-    if (mte) {
-        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
-        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
-        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
-        desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st);
-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1);
-        desc <<= SVE_MTEDESC_SHIFT;
-    } else {
+    if (!mte) {
         addr = clean_data_tbi(s, addr);
     }
-    svl = streaming_vec_reg_size(s);
-    desc = simd_desc(svl, svl, desc);
+
+    desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0);
 
     fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr,
                                       tcg_constant_i32(desc));
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = {
     3, 2, 1, 3
 };
 
-static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
-                       int dtype, uint32_t mte_n, bool is_write,
-                       gen_helper_gvec_mem *fn)
+uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs,
+                          uint32_t msz, bool is_write, uint32_t data)
 {
-    unsigned vsz = vec_full_reg_size(s);
-    TCGv_ptr t_pg;
     uint32_t sizem1;
-    int desc = 0;
+    uint32_t desc = 0;
 
-    assert(mte_n >= 1 && mte_n <= 4);
-    sizem1 = (mte_n << dtype_msz(dtype)) - 1;
+    /* Assert all of the data fits, with or without MTE enabled. */
+    assert(nregs >= 1 && nregs <= 4);
+    sizem1 = (nregs << msz) - 1;
     assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT);
+    assert(data < 1u << SVE_MTEDESC_SHIFT);
+
     if (s->mte_active[0]) {
         desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
         desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
         desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
         desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1);
         desc <<= SVE_MTEDESC_SHIFT;
-    } else {
+    }
+    return simd_desc(vsz, vsz, desc | data);
+}
+
+static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
+                       int dtype, uint32_t nregs, bool is_write,
+                       gen_helper_gvec_mem *fn)
+{
+    TCGv_ptr t_pg;
+    uint32_t desc;
+
+    if (!s->mte_active[0]) {
         addr = clean_data_tbi(s, addr);
     }
 
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
      * registers as pointers, so encode the regno into the data field.
      * For consistency, do this even for LD1.
      */
-    desc = simd_desc(vsz, vsz, zt | desc);
+    desc = make_svemte_desc(s, vec_full_reg_size(s), nregs,
+                            dtype_msz(dtype), is_write, zt);
     t_pg = tcg_temp_new_ptr();
 
     tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
@@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm,
                        int scale, TCGv_i64 scalar, int msz, bool is_write,
                        gen_helper_gvec_mem_scatter *fn)
 {
-    unsigned vsz = vec_full_reg_size(s);
     TCGv_ptr t_zm = tcg_temp_new_ptr();
     TCGv_ptr t_pg = tcg_temp_new_ptr();
     TCGv_ptr t_zt = tcg_temp_new_ptr();
-    int desc = 0;
-
-    if (s->mte_active[0]) {
-        desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s));
-        desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
-        desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
-        desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write);
-        desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1);
-        desc <<= SVE_MTEDESC_SHIFT;
-    }
-    desc = simd_desc(vsz, vsz, desc | scale);
+    uint32_t desc;
 
     tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg));
     tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm));
     tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt));
+
+    desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale);
     fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc));
 }
 
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

These functions "use the standard load helpers", but
fail to clean_data_tbi or populate mtedesc.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-sve.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
     unsigned vsz = vec_full_reg_size(s);
     TCGv_ptr t_pg;
     int poff;
+    uint32_t desc;
 
     /* Load the first quadword using the normal predicated load helpers.  */
+    if (!s->mte_active[0]) {
+        addr = clean_data_tbi(s, addr);
+    }
+
     poff = pred_full_reg_offset(s, pg);
     if (vsz > 16) {
         /*
@@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
 
     gen_helper_gvec_mem *fn
         = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
-    fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
+    desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt);
+    fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
 
     /* Replicate that first quadword.  */
     if (vsz > 16) {
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
     unsigned vsz_r32;
     TCGv_ptr t_pg;
     int poff, doff;
+    uint32_t desc;
 
     if (vsz < 32) {
         /*
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
     }
 
     /* Load the first octaword using the normal predicated load helpers.  */
+    if (!s->mte_active[0]) {
+        addr = clean_data_tbi(s, addr);
+    }
 
     poff = pred_full_reg_offset(s, pg);
     if (vsz > 32) {
@@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
 
     gen_helper_gvec_mem *fn
         = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
-    fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt)));
+    desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt);
+    fn(tcg_env, t_pg, addr, tcg_constant_i32(desc));
 
     /*
      * Replicate that first octaword.
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

The TBI and TCMA bits are located within mtedesc, not desc.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20240207025210.8837-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/sme_helper.c |  8 ++++----
 target/arm/tcg/sve_helper.c | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg,
     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 
     /* Perform gross MTE suppression early. */
-    if (!tbi_check(desc, bit55) ||
-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+    if (!tbi_check(mtedesc, bit55) ||
+        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
         mtedesc = 0;
     }
 
@@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr,
     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 
     /* Perform gross MTE suppression early. */
-    if (!tbi_check(desc, bit55) ||
-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+    if (!tbi_check(mtedesc, bit55) ||
+        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
         mtedesc = 0;
     }
 
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 
     /* Perform gross MTE suppression early. */
-    if (!tbi_check(desc, bit55) ||
-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+    if (!tbi_check(mtedesc, bit55) ||
+        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
         mtedesc = 0;
     }
 
@@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr,
     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 
     /* Perform gross MTE suppression early. */
-    if (!tbi_check(desc, bit55) ||
-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+    if (!tbi_check(mtedesc, bit55) ||
+        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
         mtedesc = 0;
     }
 
@@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr,
     desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT);
 
     /* Perform gross MTE suppression early. */
-    if (!tbi_check(desc, bit55) ||
-        tcma_check(desc, bit55, allocation_tag_from_addr(addr))) {
+    if (!tbi_check(mtedesc, bit55) ||
+        tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) {
         mtedesc = 0;
     }
 
-- 
2.34.1

The raven_io_ops MemoryRegionOps is the only one in the source tree
which sets .valid.unaligned to indicate that it should support
unaligned accesses and which does not also set .impl.unaligned to
indicate that its read and write functions can do the unaligned
handling themselves.  This is a problem, because at the moment the
core memory system does not implement the support for handling
unaligned accesses by doing a series of aligned accesses and
combining them (system/memory.c:access_with_adjusted_size() has a
TODO comment noting this).

Fortunately raven_io_read() and raven_io_write() will correctly deal
with the case of being passed an unaligned address, so we can fix the
missing unaligned access support by setting .impl.unaligned in the
MemoryRegionOps struct.

Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org
---
 hw/pci-host/raven.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/pci-host/raven.c
+++ b/hw/pci-host/raven.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = {
     .write = raven_io_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
     .impl.max_access_size = 4,
+    .impl.unaligned = true,
     .valid.unaligned = true,
 };
 
-- 
2.34.1

We deliberately don't include qtests_npcm7xx in qtests_aarch64,
because we already get the coverage of those tests via qtests_arm,
and we don't want to use extra CI minutes testing them twice.

In commit 327b680877b79c4b we added it to qtests_aarch64; revert
that change.

Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206163043.315535-1-peter.maydell@linaro.org
---
 tests/qtest/meson.build | 1 -
 1 file changed, 1 deletion(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
   (config_all_accel.has_key('CONFIG_TCG') and                                            \
    config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
-  (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
   ['arm-cpu-features',
    'numa-test',
    'boot-serial-test',
-- 
2.34.1

Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a
non-secure EL2 virtual timer.  We implemented the timer itself in the
CPU model, but never wired up its IRQ line to the GIC.

Wire up the IRQ line (this is always safe whether the CPU has the
interrupt or not, since it always creates the outbound IRQ line).
Report it to the guest via dtb and ACPI if the CPU has the feature.

The DTB binding is documented in the kernel's
Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml
and the ACPI table entries are documented in the ACPI specification
version 6.3 or later.

Because the IRQ line ACPI binding is new in 6.3, we need to bump the
FADT table rev to show that we might be using 6.3 features.

Note that exposing this IRQ in the DTB will trigger a bug in EDK2
versions prior to edk2-stable202311, for users who use the virt board
with 'virtualization=on' to enable EL2 emulation and are booting an
EDK2 guest BIOS, if that EDK2 has assertions enabled.  The effect is
that EDK2 will assert on bootup:

ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48

If you see that assertion you should do one of:
 * update your EDK2 binaries to edk2-stable202311 or newer
 * use the 'virt-8.2' versioned machine type
 * not use 'virtualization=on'

(The versions shipped with QEMU itself have the fix.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-3-peter.maydell@linaro.org
---
 include/hw/arm/virt.h    |  2 ++
 hw/arm/virt-acpi-build.c | 20 ++++++++++----
 hw/arm/virt.c            | 60 ++++++++++++++++++++++++++++++++++------
 3 files changed, 67 insertions(+), 15 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
     /* Machines < 6.2 have no support for describing cpu topology to guest */
     bool no_cpu_topology;
     bool no_tcg_lpa2;
+    bool no_ns_el2_virt_timer_irq;
 };
 
 struct VirtMachineState {
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
     PCIBus *bus;
     char *oem_id;
     char *oem_table_id;
+    bool ns_el2_virt_timer_irq;
 };
 
 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 }
 
 /*
- * ACPI spec, Revision 5.1
- * 5.2.24 Generic Timer Description Table (GTDT)
+ * ACPI spec, Revision 6.5
+ * 5.2.25 Generic Timer Description Table (GTDT)
  */
 static void
 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     uint32_t irqflags = vmc->claim_edge_triggered_timers ?
         1 : /* Interrupt is Edge triggered */
         0;  /* Interrupt is Level triggered  */
-    AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
+    AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id,
                         .oem_table_id = vms->oem_table_id };
 
     acpi_table_begin(&table, table_data);
@@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     build_append_int_noprefix(table_data, 0, 4);
     /* Platform Timer Offset */
     build_append_int_noprefix(table_data, 0, 4);
-
+    if (vms->ns_el2_virt_timer_irq) {
+        /* Virtual EL2 Timer GSIV */
+        build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4);
+        /* Virtual EL2 Timer Flags */
+        build_append_int_noprefix(table_data, irqflags, 4);
+    } else {
+        build_append_int_noprefix(table_data, 0, 4);
+        build_append_int_noprefix(table_data, 0, 4);
+    }
     acpi_table_end(linker, &table);
 }
 
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
                             VirtMachineState *vms, unsigned dsdt_tbl_offset)
 {
-    /* ACPI v6.0 */
+    /* ACPI v6.3 */
     AcpiFadtData fadt = {
         .rev = 6,
-        .minor_ver = 0,
+        .minor_ver = 3,
         .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
         .xdsdt_tbl_offset = &dsdt_tbl_offset,
     };
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node)
     qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
 }
 
+/*
+ * The CPU object always exposes the NS EL2 virt timer IRQ line,
+ * but we don't want to advertise it to the guest in the dtb or ACPI
+ * table unless it's really going to do something.
+ */
+static bool ns_el2_virt_timer_present(void)
+{
+    ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
+    CPUARMState *env = &cpu->env;
+
+    return arm_feature(env, ARM_FEATURE_AARCH64) &&
+        arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
+}
+
 static void create_fdt(VirtMachineState *vms)
 {
     MachineState *ms = MACHINE(vms);
@@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms)
                                 "arm,armv7-timer");
     }
     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
-    qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
-                           GIC_FDT_IRQ_TYPE_PPI,
-                           INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
-                           GIC_FDT_IRQ_TYPE_PPI,
-                           INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
-                           GIC_FDT_IRQ_TYPE_PPI,
-                           INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
-                           GIC_FDT_IRQ_TYPE_PPI,
-                           INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
+    if (vms->ns_el2_virt_timer_irq) {
+        qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
+    } else {
+        qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
+                               GIC_FDT_IRQ_TYPE_PPI,
+                               INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
+    }
 }
 
 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
+            [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
         };
 
         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
         object_unref(cpuobj);
     }
+
+    /* Now we've created the CPUs we can see if they have the hypvirt timer */
+    vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
+        !vmc->no_ns_el2_virt_timer_irq;
+
     fdt_add_timer_nodes(vms);
     fdt_add_cpu_nodes(vms);
 
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
 
 static void virt_machine_8_2_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_9_0_options(mc);
     compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
+    /*
+     * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
+     * earlier machines. (Exposing it tickles a bug in older EDK2
+     * guest BIOS binaries.)
+     */
+    vmc->no_ns_el2_virt_timer_irq = true;
 }
 DEFINE_VIRT_MACHINE(8, 2)
 
-- 
2.34.1

Update the virt golden reference files to say that the FACP is ACPI
v6.3, and the GTDT table is a revision 3 table with space for the
virtual EL2 timer.

Diffs from iasl:

@@ -XXX,XX +XXX,XX @@
 /*
  * Intel ACPI Component Architecture
  * AML/ASL+ Disassembler version 20200925 (64-bit version)
  * Copyright (c) 2000 - 2020 Intel Corporation
  *
- * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024
  *
  * ACPI Data Table [FACP]
  *
  * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
  */

[000h 0000   4]                    Signature : "FACP"    [Fixed ACPI Description Table (FADT)]
 [004h 0004   4]                 Table Length : 00000114
 [008h 0008   1]                     Revision : 06
-[009h 0009   1]                     Checksum : 15
+[009h 0009   1]                     Checksum : 12
 [00Ah 0010   6]                       Oem ID : "BOCHS "
 [010h 0016   8]                 Oem Table ID : "BXPC    "
 [018h 0024   4]                 Oem Revision : 00000001
 [01Ch 0028   4]              Asl Compiler ID : "BXPC"
 [020h 0032   4]        Asl Compiler Revision : 00000001

[024h 0036   4]                 FACS Address : 00000000
 [028h 0040   4]                 DSDT Address : 00000000
 [02Ch 0044   1]                        Model : 00
 [02Dh 0045   1]                   PM Profile : 00 [Unspecified]
 [02Eh 0046   2]                SCI Interrupt : 0000
 [030h 0048   4]             SMI Command Port : 00000000
 [034h 0052   1]            ACPI Enable Value : 00
 [035h 0053   1]           ACPI Disable Value : 00
 [036h 0054   1]               S4BIOS Command : 00
 [037h 0055   1]              P-State Control : 00
@@ -XXX,XX +XXX,XX @@
      Use APIC Physical Destination Mode (V4) : 0
                        Hardware Reduced (V5) : 1
                       Low Power S0 Idle (V5) : 0

[074h 0116  12]               Reset Register : [Generic Address Structure]
 [074h 0116   1]                     Space ID : 00 [SystemMemory]
 [075h 0117   1]                    Bit Width : 00
 [076h 0118   1]                   Bit Offset : 00
 [077h 0119   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [078h 0120   8]                      Address : 0000000000000000

[080h 0128   1]         Value to cause reset : 00
 [081h 0129   2]    ARM Flags (decoded below) : 0003
                               PSCI Compliant : 1
                        Must use HVC for PSCI : 1

-[083h 0131   1]          FADT Minor Revision : 00
+[083h 0131   1]          FADT Minor Revision : 03
 [084h 0132   8]                 FACS Address : 0000000000000000
 [08Ch 0140   8]                 DSDT Address : 0000000000000000
 [094h 0148  12]             PM1A Event Block : [Generic Address Structure]
 [094h 0148   1]                     Space ID : 00 [SystemMemory]
 [095h 0149   1]                    Bit Width : 00
 [096h 0150   1]                   Bit Offset : 00
 [097h 0151   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [098h 0152   8]                      Address : 0000000000000000

[0A0h 0160  12]             PM1B Event Block : [Generic Address Structure]
 [0A0h 0160   1]                     Space ID : 00 [SystemMemory]
 [0A1h 0161   1]                    Bit Width : 00
 [0A2h 0162   1]                   Bit Offset : 00
 [0A3h 0163   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0A4h 0164   8]                      Address : 0000000000000000

@@ -XXX,XX +XXX,XX @@
 [0F5h 0245   1]                    Bit Width : 00
 [0F6h 0246   1]                   Bit Offset : 00
 [0F7h 0247   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0F8h 0248   8]                      Address : 0000000000000000

[100h 0256  12]        Sleep Status Register : [Generic Address Structure]
 [100h 0256   1]                     Space ID : 00 [SystemMemory]
 [101h 0257   1]                    Bit Width : 00
 [102h 0258   1]                   Bit Offset : 00
 [103h 0259   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [104h 0260   8]                      Address : 0000000000000000

[10Ch 0268   8]                Hypervisor ID : 00000000554D4551

Raw Table Data: Length 276 (0x114)

-    0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20  // FACP......BOCHS
+    0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20  // FACP......BOCHS
     0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
     0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
-    0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
+    0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
     0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55  // ............QEMU
     0110: 00 00 00 00                                      // ....

@@ -XXX,XX +XXX,XX @@
 /*
  * Intel ACPI Component Architecture
  * AML/ASL+ Disassembler version 20200925 (64-bit version)
  * Copyright (c) 2000 - 2020 Intel Corporation
  *
- * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024
+ * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024
  *
  * ACPI Data Table [GTDT]
  *
  * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
  */

[000h 0000   4]                    Signature : "GTDT"    [Generic Timer Description Table]
-[004h 0004   4]                 Table Length : 00000060
-[008h 0008   1]                     Revision : 02
-[009h 0009   1]                     Checksum : 9C
+[004h 0004   4]                 Table Length : 00000068
+[008h 0008   1]                     Revision : 03
+[009h 0009   1]                     Checksum : 93
 [00Ah 0010   6]                       Oem ID : "BOCHS "
 [010h 0016   8]                 Oem Table ID : "BXPC    "
 [018h 0024   4]                 Oem Revision : 00000001
 [01Ch 0028   4]              Asl Compiler ID : "BXPC"
 [020h 0032   4]        Asl Compiler Revision : 00000001

[024h 0036   8]        Counter Block Address : FFFFFFFFFFFFFFFF
 [02Ch 0044   4]                     Reserved : 00000000

[030h 0048   4]         Secure EL1 Interrupt : 0000001D
 [034h 0052   4]    EL1 Flags (decoded below) : 00000000
                                 Trigger Mode : 0
                                     Polarity : 0
                                    Always On : 0

[038h 0056   4]     Non-Secure EL1 Interrupt : 0000001E
@@ -XXX,XX +XXX,XX @@

[040h 0064   4]      Virtual Timer Interrupt : 0000001B
 [044h 0068   4]     VT Flags (decoded below) : 00000000
                                 Trigger Mode : 0
                                     Polarity : 0
                                    Always On : 0

[048h 0072   4]     Non-Secure EL2 Interrupt : 0000001A
 [04Ch 0076   4]   NEL2 Flags (decoded below) : 00000000
                                 Trigger Mode : 0
                                     Polarity : 0
                                    Always On : 0
 [050h 0080   8]   Counter Read Block Address : FFFFFFFFFFFFFFFF

[058h 0088   4]         Platform Timer Count : 00000000
 [05Ch 0092   4]        Platform Timer Offset : 00000000
+[060h 0096   4]       Virtual EL2 Timer GSIV : 00000000
+[064h 0100   4]      Virtual EL2 Timer Flags : 00000000

-Raw Table Data: Length 96 (0x60)
+Raw Table Data: Length 104 (0x68)

-    0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20  // GTDT`.....BOCHS
+    0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20  // GTDTh.....BOCHS
     0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
     0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00  // ................
     0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00  // ................
     0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00  // ................
     0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00  // ................
+    0060: 00 00 00 00 00 00 00 00                          // ........

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
---
 tests/qtest/bios-tables-test-allowed-diff.h |   2 --
 tests/data/acpi/virt/FACP                   | Bin 276 -> 276 bytes
 tests/data/acpi/virt/GTDT                   | Bin 96 -> 104 bytes
 3 files changed, 2 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,3 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/virt/FACP",
-"tests/data/acpi/virt/GTDT",
diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 25
gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh

delta 28
kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20

diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT
index XXXXXXX..XXXXXXX 100644
GIT binary patch
delta 25
bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L

delta 16
Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u

-- 
2.34.1

The patchset adding the GMAC ethernet to this SoC crossed in the
mail with the patchset cleaning up the NIC handling. When we
create the GMAC modules we must call qemu_configure_nic_device()
so that the user has the opportunity to use the -nic commandline
option to create a network backend and connect it to the GMACs.

Add the missing call.

Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
---
 hw/arm/npcm7xx.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
 
+        qemu_configure_nic_device(DEVICE(sbd), false, NULL);
         /*
          * The device exists regardless of whether it's connected to a QEMU
          * netdev backend. So always instantiate it even if there is no
-- 
2.34.1

Currently QEMU will warn if there is a NIC on the board that
is not connected to a backend. By default the '-nic user' will
get used for all NICs, but if you manually connect a specific
NIC to a specific backend, then the other NICs on the board
have no backend and will be warned about:

qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer
qemu-system-arm: warning: nic npcm-gmac.0 has no peer
qemu-system-arm: warning: nic npcm-gmac.1 has no peer

So suppress those warnings by manually connecting every NIC
on the board to some backend.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20240206171231.396392-3-peter.maydell@linaro.org
---
 tests/qtest/npcm7xx_emc-test.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/npcm7xx_emc-test.c
+++ b/tests/qtest/npcm7xx_emc-test.c
@@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line)
      * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases
      * in the 'model' field to specify the device to match.
      */
-    g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ",
+    g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d "
+                           "-nic user,model=npcm7xx-emc "
+                           "-nic user,model=npcm-gmac "
+                           "-nic user,model=npcm-gmac",
                            test_sockets[1], module_num);
 
     g_test_queue_destroy(packet_test_clear, test_sockets);
-- 
2.34.1

It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile
CPU, and in fact if you try to do it we will assert:

#6  0x00007ffff4b95e96 in __GI___assert_fail
    (assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101
#7  0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600
#8  0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595
#9  0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512

We might call pmu_counter_enabled() on an M-profile CPU (for example
from the migration pre/post hooks in machine.c); this should always
return false because these CPUs don't set ARM_FEATURE_PMU.

Avoid the assertion by not calling arm_mdcr_el2_eff() before we
have done the early return for "PMU not present".

This fixes an assertion failure if you try to do a loadvm or
savevm for an M-profile board.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240208153346.970021-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
     bool enabled, prohibited = false, filtered;
     bool secure = arm_is_secure(env);
     int el = arm_current_el(env);
-    uint64_t mdcr_el2 = arm_mdcr_el2_eff(env);
-    uint8_t hpmn = mdcr_el2 & MDCR_HPMN;
+    uint64_t mdcr_el2;
+    uint8_t hpmn;
 
+    /*
+     * We might be called for M-profile cores where MDCR_EL2 doesn't
+     * exist and arm_mdcr_el2_eff() will assert, so this early-exit check
+     * must be before we read that value.
+     */
     if (!arm_feature(env, ARM_FEATURE_PMU)) {
         return false;
     }
 
+    mdcr_el2 = arm_mdcr_el2_eff(env);
+    hpmn = mdcr_el2 & MDCR_HPMN;
+
     if (!arm_feature(env, ARM_FEATURE_EL2) ||
             (counter < hpmn || counter == 31)) {
         e = env->cp15.c9_pmcr & PMCRE;
-- 
2.34.1

From: Nabih Estefan <nabihestefan@google.com>

Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead
of 8xx. Also fix comments referencing this and values expecting 8xx.

Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8
Signed-Off-By: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Message-id: 20240208194759.2858582-2-nabihestefan@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm_gmac-test.c | 84 +-----------------------------------
 tests/qtest/meson.build      |  3 +-
 2 files changed, 4 insertions(+), 83 deletions(-)

diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/npcm_gmac-test.c
+++ b/tests/qtest/npcm_gmac-test.c
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
     const GMACModule *module;
 } TestData;
 
-/* Values extracted from hw/arm/npcm8xx.c */
+/* Values extracted from hw/arm/npcm7xx.c */
 static const GMACModule gmac_module_list[] = {
     {
         .irq        = 14,
@@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = {
         .irq        = 15,
         .base_addr  = 0xf0804000
     },
-    {
-        .irq        = 16,
-        .base_addr  = 0xf0806000
-    },
-    {
-        .irq        = 17,
-        .base_addr  = 0xf0808000
-    }
 };
 
 /* Returns the index of the GMAC module. */
@@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod,
     return qtest_readl(qts, mod->base_addr + regno);
 }
 
-static uint16_t pcs_read(QTestState *qts, const GMACModule *mod,
-                          NPCMRegister regno)
-{
-    uint32_t write_value = (regno & 0x3ffe00) >> 9;
-    qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value);
-    uint32_t read_offset = regno & 0x1ff;
-    return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset);
-}
-
 /* Check that GMAC registers are reset to default value */
 static void test_init(gconstpointer test_data)
 {
     const TestData *td = test_data;
     const GMACModule *mod = td->module;
-    QTestState *qts = qtest_init("-machine npcm845-evb");
+    QTestState *qts = qtest_init("-machine npcm750-evb");
 
 #define CHECK_REG32(regno, value) \
     do { \
         g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \
     } while (0)
 
-#define CHECK_REG_PCS(regno, value) \
-    do { \
-        g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \
-    } while (0)
-
     CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100);
     CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0);
     CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0);
@@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data)
     CHECK_REG32(NPCM_GMAC_PTP_TAR, 0);
     CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0);
 
-    /* TODO Add registers PCS */
-    if (mod->base_addr == 0xf0802000) {
-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e);
-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000);
-
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000);
-
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048);
-        CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0);
-
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0);
-        CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0);
-    }
-
     qtest_quit(qts);
 }
 
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
    'npcm7xx_sdhci-test',
    'npcm7xx_smbus-test',
    'npcm7xx_timer-test',
-   'npcm7xx_watchdog_timer-test'] + \
+   'npcm7xx_watchdog_timer-test',
+   'npcm_gmac-test'] + \
    (slirp.found() ? ['npcm7xx_emc-test'] : [])
 qtests_aspeed = \
   ['aspeed_hace-test',
-- 
2.34.1

From: Luc Michel <luc.michel@amd.com>

An access fault is raised when the Access Flag is not set in the
looked-up PTE and the AFFD field is not set in the corresponding context
descriptor. This was already implemented for stage 2. Implement it for
stage 1 as well.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Mostafa Saleh <smostafa@google.com>
Message-id: 20240213082211.3330400-1-luc.michel@amd.com
[PMM: tweaked comment text]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h     |  1 +
 include/hw/arm/smmu-common.h |  1 +
 hw/arm/smmu-common.c         | 11 +++++++++++
 hw/arm/smmuv3.c              |  1 +
 4 files changed, 14 insertions(+)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste)
 #define CD_EPD(x, sel)   extract32((x)->word[0], (16 * (sel)) + 14, 1)
 #define CD_ENDI(x)       extract32((x)->word[0], 15, 1)
 #define CD_IPS(x)        extract32((x)->word[1], 0 , 3)
+#define CD_AFFD(x)       extract32((x)->word[1], 3 , 1)
 #define CD_TBI(x)        extract32((x)->word[1], 6 , 2)
 #define CD_HD(x)         extract32((x)->word[1], 10 , 1)
 #define CD_HA(x)         extract32((x)->word[1], 11 , 1)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
     bool disabled;             /* smmu is disabled */
     bool bypassed;             /* translation is bypassed */
     bool aborted;              /* translation is aborted */
+    bool affd;                 /* AF fault disable */
     uint32_t iotlb_hits;       /* counts IOTLB hits */
     uint32_t iotlb_misses;     /* counts IOTLB misses*/
     /* Used by stage-1 only. */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
                                      pte_addr, pte, iova, gpa,
                                      block_size >> 20);
         }
+
+        /*
+         * QEMU does not currently implement HTTU, so if AFFD and PTE.AF
+         * are 0 we take an Access flag fault. (5.4. Context Descriptor)
+         * An Access flag fault takes priority over a Permission fault.
+         */
+        if (!PTE_AF(pte) && !cfg->affd) {
+            info->type = SMMU_PTW_ERR_ACCESS;
+            goto error;
+        }
+
         ap = PTE_AP(pte);
         if (is_permission_fault(ap, perm)) {
             info->type = SMMU_PTW_ERR_PERMISSION;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
     cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas);
     cfg->tbi = CD_TBI(cd);
     cfg->asid = CD_ASID(cd);
+    cfg->affd = CD_AFFD(cd);
 
     trace_smmuv3_decode_cd(cfg->oas);
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
     }
 }
 
-static void stellaris_adc_reset(StellarisADCState *s)
+static void stellaris_adc_reset_hold(Object *obj)
 {
+    StellarisADCState *s = STELLARIS_ADC(obj);
     int n;
 
     for (n = 0; n < 4; n++) {
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
                           "adc", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
-    stellaris_adc_reset(s);
     qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
 }
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = {
 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
+    rc->phases.hold = stellaris_adc_reset_hold;
     dc->vmsd = &vmstate_stellaris_adc;
 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240213155214.13619-3-philmd@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 26 ++++++++++++++++++++++----
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
     s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
 }
 
-/* I2C controller.  */
+/*
+ * I2C controller.
+ * ??? For now we only implement the master interface.
+ */
 
 #define TYPE_STELLARIS_I2C "stellaris-i2c"
 OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
     stellaris_i2c_update(s);
 }
 
-static void stellaris_i2c_reset(stellaris_i2c_state *s)
+static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
 {
+    stellaris_i2c_state *s = STELLARIS_I2C(obj);
+
     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
         i2c_end_transfer(s->bus);
+}
+
+static void stellaris_i2c_reset_hold(Object *obj)
+{
+    stellaris_i2c_state *s = STELLARIS_I2C(obj);
 
     s->msa = 0;
     s->mcs = 0;
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
     s->mimr = 0;
     s->mris = 0;
     s->mcr = 0;
+}
+
+static void stellaris_i2c_reset_exit(Object *obj)
+{
+    stellaris_i2c_state *s = STELLARIS_I2C(obj);
+
     stellaris_i2c_update(s);
 }
 
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
     memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
                           "i2c", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
-    /* ??? For now we only implement the master interface.  */
-    stellaris_i2c_reset(s);
 }
 
 /* Analogue to Digital Converter.  This is only partially implemented,
@@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init)
 static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
+    rc->phases.enter = stellaris_i2c_reset_enter;
+    rc->phases.hold = stellaris_i2c_reset_hold;
+    rc->phases.exit = stellaris_i2c_reset_exit;
     dc->vmsd = &vmstate_stellaris_i2c;
 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().

This commit plug the devices which aren't part of the SoC;
they will be plugged into a SoC container in the next one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
                                    &error_fatal);
 
             ssddev = qdev_new("ssd0323");
+            object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev));
             qdev_prop_set_uint8(ssddev, "cs", 1);
             qdev_realize_and_unref(ssddev, bus, &error_fatal);
 
             gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
+            object_property_add_child(OBJECT(ms), "splitter",
+                                      OBJECT(gpio_d_splitter));
             qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
             qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
             qdev_connect_gpio_out(
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
         DeviceState *gpad;
 
         gpad = qdev_new(TYPE_STELLARIS_GAMEPAD);
+        object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad));
         for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) {
             qlist_append_int(gpad_keycode_list, gpad_keycode[i]);
         }
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

QDev objects created with qdev_new() need to manually add
their parent relationship with object_property_add_child().

Since we don't model the SoC, just use a QOM container.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240213155214.13619-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
      * 400fe000 system control
      */
 
+    Object *soc_container;
     DeviceState *gpio_dev[7], *nvic;
     qemu_irq gpio_in[7][8];
     qemu_irq gpio_out[7][8];
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
     flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
     sram_size = ((board->dc0 >> 18) + 1) * 1024;
 
+    soc_container = object_new("container");
+    object_property_add_child(OBJECT(ms), "soc", soc_container);
+
     /* Flash programming is done via the SCU, so pretend it is ROM.  */
     memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
                            &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
      * need its sysclk output.
      */
     ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
+    object_property_add_child(soc_container, "sys", OBJECT(ssys_dev));
 
     /*
      * Most devices come preprogrammed with a MAC address in the user data.
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
     sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
 
     nvic = qdev_new(TYPE_ARMV7M);
+    object_property_add_child(soc_container, "v7m", OBJECT(nvic));
     qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
     qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS);
     qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
 
             dev = qdev_new(TYPE_STELLARIS_GPTM);
             sbd = SYS_BUS_DEVICE(dev);
+            object_property_add_child(soc_container, "gptm[*]", OBJECT(dev));
             qdev_connect_clock_in(dev, "clk",
                                   qdev_get_clock_out(ssys_dev, "SYSCLK"));
             sysbus_realize_and_unref(sbd, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
 
     if (board->dc1 & (1 << 3)) { /* watchdog present */
         dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
-
+        object_property_add_child(soc_container, "wdg", OBJECT(dev));
         qdev_connect_clock_in(dev, "WDOGCLK",
                               qdev_get_clock_out(ssys_dev, "SYSCLK"));
 
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             SysBusDevice *sbd;
 
             dev = qdev_new("pl011_luminary");
+            object_property_add_child(soc_container, "uart[*]", OBJECT(dev));
             sbd = SYS_BUS_DEVICE(dev);
             qdev_prop_set_chr(dev, "chardev", serial_hd(i));
             sysbus_realize_and_unref(sbd, &error_fatal);
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
         DeviceState *enet;
 
         enet = qdev_new("stellaris_enet");
+        object_property_add_child(soc_container, "enet", OBJECT(enet));
         if (nd) {
             qdev_set_nic_properties(enet, nd);
         } else {
-- 
2.34.1

We support two different encodings for the AArch32 IMPDEF
CBAR register -- older cores like the Cortex A9, A7, A15
have this at 4, c15, c0, 0; newer cores like the
Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0.

When we implemented this we picked which encoding to
use based on whether the CPU set ARM_FEATURE_AARCH64.
However this isn't right for three cases:
 * the qemu-system-arm 'max' CPU, which is supposed to be
   a variant on a Cortex-A57; it ought to use the same
   encoding the A57 does and which the AArch64 'max'
   exposes to AArch32 guest code
 * the Cortex-R52, which is AArch32-only but has the CBAR
   at the newer encoding (and where we incorrectly are
   not yet setting ARM_FEATURE_CBAR_RO anyway)
 * any possible future support for other v8 AArch32
   only CPUs, or for supporting "boot the CPU into
   AArch32 mode" on our existing cores like the A57 etc

Make the decision of the encoding be based on whether
the CPU implements the ARM_FEATURE_V8 flag instead.

This changes the behaviour only for the qemu-system-arm
'-cpu max'. We don't expect anybody to be relying on the
old behaviour because:
 * it's not what the real hardware Cortex-A57 does
   (and that's what our ID register claims we are)
 * we don't implement the memory-mapped GICv3 support
   which is the only thing that exists at the peripheral
   base address pointed to by the register

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-2-peter.maydell@linaro.org
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
          * AArch64 cores we might need to add a specific feature flag
          * to indicate cores with "flavour 2" CBAR.
          */
-        if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+        if (arm_feature(env, ARM_FEATURE_V8)) {
             /* 32 bit view is [31:18] 0...0 [43:32]. */
             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
                 | extract64(cpu->reset_cbar, 32, 12);
-- 
2.34.1

The Cortex-R52 implements the Configuration Base Address Register
(CBAR), as a read-only register.  Add ARM_FEATURE_CBAR_RO to this CPU
type, so that our implementation provides the register and the
associated qdev property.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-3-peter.maydell@linaro.org
---
 target/arm/tcg/cpu32.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     cpu->midr = 0x411fd133; /* r1p3 */
     cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034023;
-- 
2.34.1

Add the Cortex-R52 IMPDEF sysregs, by defining them here and
also by enabling the AUXCR feature which defines the ACTLR
and HACTLR registers. As is our usual practice, we make these
simple reads-as-zero stubs for now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-4-peter.maydell@linaro.org
---
 target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 }
 
+static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
+    { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
+      .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+    { .name = "IMP_ATCMREGIONR",
+      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_BTCMREGIONR",
+      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_CTCMREGIONR",
+      .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_CSCTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_BPCTLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_MEMPROTCLR",
+      .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_SLAVEPCTLR",
+      .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_PERIPHREGIONR",
+      .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_FLASHIFREGIONR",
+      .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_BUILDOPTR",
+      .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_PINOPTR",
+      .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_QOSR",
+      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_BUSTIMEOUTR",
+      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_INTMONR",
+      .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_ICERR0",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_ICERR1",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_DCERR0",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_DCERR1",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TCMERR0",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TCMERR1",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TCMSYNDR0",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TCMSYNDR1",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_FLASHERR0",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_FLASHERR1",
+      .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_CDBGDR0",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_CBDGBR1",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TESTR0",
+      .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
+      .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    { .name = "IMP_TESTR1",
+      .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+    { .name = "IMP_CDBGDCI",
+      .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+    { .name = "IMP_CDBGDCT",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+    { .name = "IMP_CDBGICT",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+    { .name = "IMP_CDBGDCD",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+    { .name = "IMP_CDBGICD",
+      .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
+      .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
+};
+
+
 static void cortex_r52_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_AUXCR);
     cpu->midr = 0x411fd133; /* r1p3 */
     cpu->revidr = 0x00000000;
     cpu->reset_fpsid = 0x41034023;
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
 
     cpu->pmsav7_dregion = 16;
     cpu->pmsav8r_hdregion = 16;
+
+    define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
 }
 
 static void cortex_r5f_initfn(Object *obj)
-- 
2.34.1

Architecturally, the AArch32 MSR/MRS to/from banked register
instructions are UNPREDICTABLE for attempts to access a banked
register that the guest could access in a more direct way (e.g.
using this insn to access r8_fiq when already in FIQ mode).  QEMU has
chosen to UNDEF on all of these.

However, for the case of accessing SPSR_hyp from hyp mode, it turns
out that real hardware permits this, with the same effect as if the
guest had directly written to SPSR. Further, there is some
guest code out there that assumes it can do this, because it
happens to work on hardware: an example Cortex-R52 startup code
fragment uses this, and it got copied into various other places,
including Zephyr. Zephyr was fixed to not use this:
 https://github.com/zephyrproject-rtos/zephyr/issues/47330
but other examples are still out there, like the selftest
binary for the MPS3-AN536.

For convenience of being able to run guest code, permit
this UNPREDICTABLE access instead of UNDEFing it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-5-peter.maydell@linaro.org
---
 target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------
 target/arm/tcg/translate.c | 19 +++++++++++------
 2 files changed, 43 insertions(+), 19 deletions(-)

diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
      */
     int curmode = env->uncached_cpsr & CPSR_M;
 
-    if (regno == 17) {
-        /* ELR_Hyp: a special case because access from tgtmode is OK */
-        if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
-            goto undef;
+    if (tgtmode == ARM_CPU_MODE_HYP) {
+        /*
+         * Handle Hyp target regs first because some are special cases
+         * which don't want the usual "not accessible from tgtmode" check.
+         */
+        switch (regno) {
+        case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */
+            if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) {
+                goto undef;
+            }
+            break;
+        case 13:
+            if (curmode != ARM_CPU_MODE_MON) {
+                goto undef;
+            }
+            break;
+        default:
+            g_assert_not_reached();
         }
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode,
         }
     }
 
-    if (tgtmode == ARM_CPU_MODE_HYP) {
-        /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */
-        if (curmode != ARM_CPU_MODE_MON) {
-            goto undef;
-        }
-    }
-
     return;
 
 undef:
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode,
 
     switch (regno) {
     case 16: /* SPSRs */
-        env->banked_spsr[bank_number(tgtmode)] = value;
+        if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
+            /* Only happens for SPSR_Hyp access in Hyp mode */
+            env->spsr = value;
+        } else {
+            env->banked_spsr[bank_number(tgtmode)] = value;
+        }
         break;
     case 17: /* ELR_Hyp */
         env->elr_el[2] = value;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
 
     switch (regno) {
     case 16: /* SPSRs */
-        return env->banked_spsr[bank_number(tgtmode)];
+        if (tgtmode == (env->uncached_cpsr & CPSR_M)) {
+            /* Only happens for SPSR_Hyp access in Hyp mode */
+            return env->spsr;
+        } else {
+            return env->banked_spsr[bank_number(tgtmode)];
+        }
     case 17: /* ELR_Hyp */
         return env->elr_el[2];
     case 13:
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
         break;
     case ARM_CPU_MODE_HYP:
         /*
-         * SPSR_hyp and r13_hyp can only be accessed from Monitor mode
-         * (and so we can forbid accesses from EL2 or below). elr_hyp
-         * can be accessed also from Hyp mode, so forbid accesses from
-         * EL0 or EL1.
+         * r13_hyp can only be accessed from Monitor mode, and so we
+         * can forbid accesses from EL2 or below.
+         * elr_hyp can be accessed also from Hyp mode, so forbid
+         * accesses from EL0 or EL1.
+         * SPSR_hyp is supposed to be in the same category as r13_hyp
+         * and UNPREDICTABLE if accessed from anything except Monitor
+         * mode. However there is some real-world code that will do
+         * it because at least some hardware happens to permit the
+         * access. (Notably a standard Cortex-R52 startup code fragment
+         * does this.) So we permit SPSR_hyp from Hyp mode also, to allow
+         * this (incorrect) guest code to run.
          */
-        if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 ||
-            (s->current_el < 3 && *regno != 17)) {
+        if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2
+            || (s->current_el < 3 && *regno != 16 && *regno != 17)) {
             goto undef;
         }
         break;
-- 
2.34.1

We currently guard the CFG3 register read with
 (scc_partno(s) == 0x524 && scc_partno(s) == 0x547)
which is clearly wrong as it is never true.

This register is present on all board types except AN524
and AN527; correct the condition.

Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-6-peter.maydell@linaro.org
---
 hw/misc/mps2-scc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
         r = s->cfg2;
         break;
     case A_CFG3:
-        if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) {
+        if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
             /* CFG3 reserved on AN524 */
             goto bad_offset;
         }
-- 
2.34.1

The MPS SCC device has a lot of different flavours for the various
different MPS FPGA images, which look mostly similar but have
differences in how particular registers are handled.  Currently we
deal with this with a lot of open-coded checks on scc_partno(), but
as we add more board types this is getting a bit hard to read.

Factor out the conditions into some functions which we can
give more descriptive names to.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240206132931.38376-7-peter.maydell@linaro.org
---
 hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++--------------
 1 file changed, 31 insertions(+), 14 deletions(-)

diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
     return extract32(s->id, 4, 8);
 }
 
+/* Is CFG_REG2 present? */
+static bool have_cfg2(MPS2SCC *s)
+{
+    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
+}
+
+/* Is CFG_REG3 present? */
+static bool have_cfg3(MPS2SCC *s)
+{
+    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
+}
+
+/* Is CFG_REG5 present? */
+static bool have_cfg5(MPS2SCC *s)
+{
+    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
+}
+
+/* Is CFG_REG6 present? */
+static bool have_cfg6(MPS2SCC *s)
+{
+    return scc_partno(s) == 0x524;
+}
+
 /* Handle a write via the SYS_CFG channel to the specified function/device.
  * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
  */
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
         r = s->cfg1;
         break;
     case A_CFG2:
-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-            /* CFG2 reserved on other boards */
+        if (!have_cfg2(s)) {
             goto bad_offset;
         }
         r = s->cfg2;
         break;
     case A_CFG3:
-        if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) {
-            /* CFG3 reserved on AN524 */
+        if (!have_cfg3(s)) {
             goto bad_offset;
         }
         /* These are user-settable DIP switches on the board. We don't
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
         r = s->cfg4;
         break;
     case A_CFG5:
-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-            /* CFG5 reserved on other boards */
+        if (!have_cfg5(s)) {
             goto bad_offset;
         }
         r = s->cfg5;
         break;
     case A_CFG6:
-        if (scc_partno(s) != 0x524) {
-            /* CFG6 reserved on other boards */
+        if (!have_cfg6(s)) {
             goto bad_offset;
         }
         r = s->cfg6;
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
         }
         break;
     case A_CFG2:
-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-            /* CFG2 reserved on other boards */
+        if (!have_cfg2(s)) {
             goto bad_offset;
         }
         /* AN524: QSPI Select signal */
         s->cfg2 = value;
         break;
     case A_CFG5:
-        if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) {
-            /* CFG5 reserved on other boards */
+        if (!have_cfg5(s)) {
             goto bad_offset;
         }
         /* AN524: ACLK frequency in Hz */
         s->cfg5 = value;
         break;
     case A_CFG6:
-        if (scc_partno(s) != 0x524) {
-            /* CFG6 reserved on other boards */
+        if (!have_cfg6(s)) {
             goto bad_offset;
         }
         /* AN524: Clock divider for BRAM */
-- 
2.34.1

The MPS2 SCC device is broadly the same for all FPGA images, but has
minor differences in the behaviour of the CFG registers depending on
the image. In many cases we don't really care about the functionality
controlled by these registers and a reads-as-written or similar
behaviour is sufficient for the moment.

For the AN536 the required behaviour is:

* A_CFG0 has CPU reset and halt bits
    - implement as reads-as-written for the moment
 * A_CFG1 has flash or ATCM address 0 remap handling
    - QEMU doesn't model this; implement as reads-as-written
 * A_CFG2 has QSPI select (like AN524)
    - implemented (no behaviour, as with AN524)
 * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits"
    - QEMU doesn't care about these, so use the existing
      RAZ behaviour for convenience
 * A_CFG4 is board rev (like all other images)
    - no change needed
 * A_CFG5 is ACLK frq in hz (like AN524)
    - implemented as reads-as-written, as for other boards
 * A_CFG6 is core 0 vector table base address
    - implemented as reads-as-written for the moment
 * A_CFG7 is core 1 vector table base address
    - implemented as reads-as-written for the moment

Make the changes necessary for this; leave TODO comments where
appropriate to indicate where we might want to come back and
implement things like CPU reset.

The other aspects of the device specific to this FPGA image (like the
values of the board ID and similar registers) will be set via the
device's qdev properties.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-8-peter.maydell@linaro.org
---
 include/hw/misc/mps2-scc.h |   1 +
 hw/misc/mps2-scc.c         | 101 +++++++++++++++++++++++++++++++++----
 2 files changed, 92 insertions(+), 10 deletions(-)

diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/mps2-scc.h
+++ b/include/hw/misc/mps2-scc.h
@@ -XXX,XX +XXX,XX @@ struct MPS2SCC {
     uint32_t cfg4;
     uint32_t cfg5;
     uint32_t cfg6;
+    uint32_t cfg7;
     uint32_t cfgdata_rtn;
     uint32_t cfgdata_out;
     uint32_t cfgctrl;
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc)
 REG32(CFG4, 0x10)
 REG32(CFG5, 0x14)
 REG32(CFG6, 0x18)
+REG32(CFG7, 0x1c)
 REG32(CFGDATA_RTN, 0xa0)
 REG32(CFGDATA_OUT, 0xa4)
 REG32(CFGCTRL, 0xa8)
@@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s)
 /* Is CFG_REG2 present? */
 static bool have_cfg2(MPS2SCC *s)
 {
-    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
+    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
+        scc_partno(s) == 0x536;
 }
 
 /* Is CFG_REG3 present? */
 static bool have_cfg3(MPS2SCC *s)
 {
-    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547;
+    return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 &&
+        scc_partno(s) != 0x536;
 }
 
 /* Is CFG_REG5 present? */
 static bool have_cfg5(MPS2SCC *s)
 {
-    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547;
+    return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 ||
+        scc_partno(s) == 0x536;
 }
 
 /* Is CFG_REG6 present? */
 static bool have_cfg6(MPS2SCC *s)
 {
-    return scc_partno(s) == 0x524;
+    return scc_partno(s) == 0x524 || scc_partno(s) == 0x536;
+}
+
+/* Is CFG_REG7 present? */
+static bool have_cfg7(MPS2SCC *s)
+{
+    return scc_partno(s) == 0x536;
+}
+
+/* Does CFG_REG0 drive the 'remap' GPIO output? */
+static bool cfg0_is_remap(MPS2SCC *s)
+{
+    return scc_partno(s) != 0x536;
+}
+
+/* Is CFG_REG1 driving a set of LEDs? */
+static bool cfg1_is_leds(MPS2SCC *s)
+{
+    return scc_partno(s) != 0x536;
 }
 
 /* Handle a write via the SYS_CFG channel to the specified function/device.
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
         if (!have_cfg3(s)) {
             goto bad_offset;
         }
-        /* These are user-settable DIP switches on the board. We don't
+        /*
+         * These are user-settable DIP switches on the board. We don't
          * model that, so just return zeroes.
+         *
+         * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing
+         * bits". These change which part of the DDR4 the motherboard
+         * configuration controller can see in its memory map (see the
+         * appnote section 2.4). QEMU doesn't model the MCC at all, so these
+         * bits are not interesting to us; read-as-zero is as good as anything
+         * else.
          */
         r = 0;
         break;
@@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
         }
         r = s->cfg6;
         break;
+    case A_CFG7:
+        if (!have_cfg7(s)) {
+            goto bad_offset;
+        }
+        r = s->cfg7;
+        break;
     case A_CFGDATA_RTN:
         r = s->cfgdata_rtn;
         break;
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
          * we always reflect bit 0 in the 'remap' GPIO output line,
          * and let the board wire it up or not as it chooses.
          * TODO on some boards bit 1 is CPU_WAIT.
+         *
+         * TODO: on the AN536 this register controls reset and halt
+         * for both CPUs. For the moment we don't implement this, so the
+         * register just reads as written.
          */
         s->cfg0 = value;
-        qemu_set_irq(s->remap, s->cfg0 & 1);
+        if (cfg0_is_remap(s)) {
+            qemu_set_irq(s->remap, s->cfg0 & 1);
+        }
         break;
     case A_CFG1:
         s->cfg1 = value;
-        for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
-            led_set_state(s->led[i], extract32(value, i, 1));
+        /*
+         * On most boards this register drives LEDs.
+         *
+         * TODO: for AN536 this controls whether flash and ATCM are
+         * enabled or disabled on reset. QEMU doesn't model this, and
+         * always wires up RAM in the ATCM area and ROM in the flash area.
+         */
+        if (cfg1_is_leds(s)) {
+            for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
+                led_set_state(s->led[i], extract32(value, i, 1));
+            }
         }
         break;
     case A_CFG2:
         if (!have_cfg2(s)) {
             goto bad_offset;
         }
-        /* AN524: QSPI Select signal */
+        /* AN524, AN536: QSPI Select signal */
         s->cfg2 = value;
         break;
     case A_CFG5:
         if (!have_cfg5(s)) {
             goto bad_offset;
         }
-        /* AN524: ACLK frequency in Hz */
+        /* AN524, AN536: ACLK frequency in Hz */
         s->cfg5 = value;
         break;
     case A_CFG6:
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
             goto bad_offset;
         }
         /* AN524: Clock divider for BRAM */
+        /* AN536: Core 0 vector table base address */
+        s->cfg6 = value;
+        break;
+    case A_CFG7:
+        if (!have_cfg7(s)) {
+            goto bad_offset;
+        }
+        /* AN536: Core 1 vector table base address */
         s->cfg6 = value;
         break;
     case A_CFGDATA_OUT:
@@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj)
     g_free(s->oscclk_reset);
 }
 
+static bool cfg7_needed(void *opaque)
+{
+    MPS2SCC *s = opaque;
+
+    return have_cfg7(s);
+}
+
+static const VMStateDescription vmstate_cfg7 = {
+    .name = "mps2-scc/cfg7",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = cfg7_needed,
+    .fields = (const VMStateField[]) {
+        VMSTATE_UINT32(cfg7, MPS2SCC),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription mps2_scc_vmstate = {
     .name = "mps2-scc",
     .version_id = 3,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = {
         VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
                               0, vmstate_info_uint32, uint32_t),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription * const []) {
+        &vmstate_cfg7,
+        NULL
     }
 };
 
-- 
2.34.1

The AN536 is another FPGA image for the MPS3 development board. Unlike
the existing FPGA images we already model, this board uses a Cortex-R
family CPU, and it does not use any equivalent to the M-profile
"Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c.
It's therefore more convenient for us to model it as a completely
separate C file.

This commit adds the basic skeleton of the board model, and the
code to create all the RAM and ROM. We assume that we're probably
going to want to add more images in future, so use the same
base class/subclass setup that mps2-tz.c uses, even though at
the moment there's only a single subclass.

Following commits will add the CPUs and the peripherals.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-9-peter.maydell@linaro.org
---
 MAINTAINERS                             |   3 +-
 configs/devices/arm-softmmu/default.mak |   1 +
 hw/arm/mps3r.c                          | 239 ++++++++++++++++++++++++
 hw/arm/Kconfig                          |   5 +
 hw/arm/meson.build                      |   1 +
 5 files changed, 248 insertions(+), 1 deletion(-)
 create mode 100644 hw/arm/mps3r.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h
 F: hw/pci-host/designware.c
 F: include/hw/pci-host/designware.h
 
-MPS2
+MPS2 / MPS3
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/mps2.c
 F: hw/arm/mps2-tz.c
+F: hw/arm/mps3r.c
 F: hw/misc/mps2-*.c
 F: include/hw/misc/mps2-*.h
 F: hw/arm/armsse.c
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index XXXXXXX..XXXXXXX 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y
 # CONFIG_INTEGRATOR=n
 # CONFIG_FSL_IMX31=n
 # CONFIG_MUSICPAL=n
+# CONFIG_MPS3R=n
 # CONFIG_MUSCA=n
 # CONFIG_CHEETAH=n
 # CONFIG_SX1=n
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Arm MPS3 board emulation for Cortex-R-based FPGA images.
+ * (For M-profile images see mps2.c and mps2tz.c.)
+ *
+ * Copyright (c) 2017 Linaro Limited
+ * Written by Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or
+ *  (at your option) any later version.
+ */
+
+/*
+ * The MPS3 is an FPGA based dev board. This file handles FPGA images
+ * which use the Cortex-R CPUs. We model these separately from the
+ * M-profile images, because on M-profile the FPGA image is based on
+ * a "Subsystem for Embedded" which is similar to an SoC, whereas
+ * the R-profile FPGA images don't have that abstraction layer.
+ *
+ * We model the following FPGA images here:
+ *  "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
+ *
+ * Application Note AN536:
+ * https://developer.arm.com/documentation/dai0536/latest/
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "cpu.h"
+#include "hw/boards.h"
+#include "hw/arm/boot.h"
+
+/* Define the layout of RAM and ROM in a board */
+typedef struct RAMInfo {
+    const char *name;
+    hwaddr base;
+    hwaddr size;
+    int mrindex; /* index into rams[]; -1 for the system RAM block */
+    int flags;
+} RAMInfo;
+
+/*
+ * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
+ * emulation of that much guest RAM, so artificially make it smaller.
+ */
+#if HOST_LONG_BITS == 32
+#define MPS3_DDR_SIZE (1 * GiB)
+#else
+#define MPS3_DDR_SIZE (3 * GiB)
+#endif
+
+/*
+ * Flag values:
+ * IS_MAIN: this is the main machine RAM
+ * IS_ROM: this area is read-only
+ */
+#define IS_MAIN 1
+#define IS_ROM 2
+
+#define MPS3R_RAM_MAX 9
+
+typedef enum MPS3RFPGAType {
+    FPGA_AN536,
+} MPS3RFPGAType;
+
+struct MPS3RMachineClass {
+    MachineClass parent;
+    MPS3RFPGAType fpga_type;
+    const RAMInfo *raminfo;
+};
+
+struct MPS3RMachineState {
+    MachineState parent;
+    MemoryRegion ram[MPS3R_RAM_MAX];
+};
+
+#define TYPE_MPS3R_MACHINE "mps3r"
+#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
+
+OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
+
+static const RAMInfo an536_raminfo[] = {
+    {
+        .name = "ATCM",
+        .base = 0x00000000,
+        .size = 0x00008000,
+        .mrindex = 0,
+    }, {
+        /* We model the QSPI flash as simple ROM for now */
+        .name = "QSPI",
+        .base = 0x08000000,
+        .size = 0x00800000,
+        .flags = IS_ROM,
+        .mrindex = 1,
+    }, {
+        .name = "BRAM",
+        .base = 0x10000000,
+        .size = 0x00080000,
+        .mrindex = 2,
+    }, {
+        .name = "DDR",
+        .base = 0x20000000,
+        .size = MPS3_DDR_SIZE,
+        .mrindex = -1,
+    }, {
+        .name = "ATCM0",
+        .base = 0xee000000,
+        .size = 0x00008000,
+        .mrindex = 3,
+    }, {
+        .name = "BTCM0",
+        .base = 0xee100000,
+        .size = 0x00008000,
+        .mrindex = 4,
+    }, {
+        .name = "CTCM0",
+        .base = 0xee200000,
+        .size = 0x00008000,
+        .mrindex = 5,
+    }, {
+        .name = "ATCM1",
+        .base = 0xee400000,
+        .size = 0x00008000,
+        .mrindex = 6,
+    }, {
+        .name = "BTCM1",
+        .base = 0xee500000,
+        .size = 0x00008000,
+        .mrindex = 7,
+    }, {
+        .name = "CTCM1",
+        .base = 0xee600000,
+        .size = 0x00008000,
+        .mrindex = 8,
+    }, {
+        .name = NULL,
+    }
+};
+
+static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
+                                    const RAMInfo *raminfo)
+{
+    /* Return an initialized MemoryRegion for the RAMInfo. */
+    MemoryRegion *ram;
+
+    if (raminfo->mrindex < 0) {
+        /* Means this RAMInfo is for QEMU's "system memory" */
+        MachineState *machine = MACHINE(mms);
+        assert(!(raminfo->flags & IS_ROM));
+        return machine->ram;
+    }
+
+    assert(raminfo->mrindex < MPS3R_RAM_MAX);
+    ram = &mms->ram[raminfo->mrindex];
+
+    memory_region_init_ram(ram, NULL, raminfo->name,
+                           raminfo->size, &error_fatal);
+    if (raminfo->flags & IS_ROM) {
+        memory_region_set_readonly(ram, true);
+    }
+    return ram;
+}
+
+static void mps3r_common_init(MachineState *machine)
+{
+    MPS3RMachineState *mms = MPS3R_MACHINE(machine);
+    MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
+    MemoryRegion *sysmem = get_system_memory();
+
+    for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
+        MemoryRegion *mr = mr_for_raminfo(mms, ri);
+        memory_region_add_subregion(sysmem, ri->base, mr);
+    }
+}
+
+static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
+{
+    /*
+     * Set mc->default_ram_size and default_ram_id from the
+     * information in mmc->raminfo.
+     */
+    MachineClass *mc = MACHINE_CLASS(mmc);
+    const RAMInfo *p;
+
+    for (p = mmc->raminfo; p->name; p++) {
+        if (p->mrindex < 0) {
+            /* Found the entry for "system memory" */
+            mc->default_ram_size = p->size;
+            mc->default_ram_id = p->name;
+            return;
+        }
+    }
+    g_assert_not_reached();
+}
+
+static void mps3r_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->init = mps3r_common_init;
+}
+
+static void mps3r_an536_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
+    static const char * const valid_cpu_types[] = {
+        ARM_CPU_TYPE_NAME("cortex-r52"),
+        NULL
+    };
+
+    mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
+    mc->default_cpus = 2;
+    mc->min_cpus = mc->default_cpus;
+    mc->max_cpus = mc->default_cpus;
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
+    mc->valid_cpu_types = valid_cpu_types;
+    mmc->raminfo = an536_raminfo;
+    mps3r_set_default_ram_info(mmc);
+}
+
+static const TypeInfo mps3r_machine_types[] = {
+    {
+        .name = TYPE_MPS3R_MACHINE,
+        .parent = TYPE_MACHINE,
+        .abstract = true,
+        .instance_size = sizeof(MPS3RMachineState),
+        .class_size = sizeof(MPS3RMachineClass),
+        .class_init = mps3r_class_init,
+    }, {
+        .name = TYPE_MPS3R_AN536_MACHINE,
+        .parent = TYPE_MPS3R_MACHINE,
+        .class_init = mps3r_an536_class_init,
+    },
+};
+
+DEFINE_TYPES(mps3r_machine_types);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAINSTONE
     select PFLASH_CFI01
     select SMC91C111
 
+config MPS3R
+    bool
+    default y
+    depends on TCG && ARM
+
 config MUSCA
     bool
     default y
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
 arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
 arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
 arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
+arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c'))
 arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
-- 
2.34.1

Create the CPUs, the GIC, and the per-CPU RAM block for
the mps3-an536 board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240206132931.38376-10-peter.maydell@linaro.org
---
 hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 177 insertions(+), 3 deletions(-)

diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "qapi/error.h"
+#include "qapi/qmp/qlist.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
 #include "hw/boards.h"
+#include "hw/qdev-properties.h"
 #include "hw/arm/boot.h"
+#include "hw/arm/bsa.h"
+#include "hw/intc/arm_gicv3.h"
 
 /* Define the layout of RAM and ROM in a board */
 typedef struct RAMInfo {
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
 #define IS_ROM 2
 
 #define MPS3R_RAM_MAX 9
+#define MPS3R_CPU_MAX 2
+
+#define PERIPHBASE 0xf0000000
+#define NUM_SPIS 96
 
 typedef enum MPS3RFPGAType {
     FPGA_AN536,
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass {
     MachineClass parent;
     MPS3RFPGAType fpga_type;
     const RAMInfo *raminfo;
+    hwaddr loader_start;
 };
 
 struct MPS3RMachineState {
     MachineState parent;
+    struct arm_boot_info bootinfo;
     MemoryRegion ram[MPS3R_RAM_MAX];
+    Object *cpu[MPS3R_CPU_MAX];
+    MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
+    MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
+    MemoryRegion cpu_ram[MPS3R_CPU_MAX];
+    GICv3State gic;
 };
 
 #define TYPE_MPS3R_MACHINE "mps3r"
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
     return ram;
 }
 
+/*
+ * There is no defined secondary boot protocol for Linux for the AN536,
+ * because real hardware has a restriction that atomic operations between
+ * the two CPUs do not function correctly, and so true SMP is not
+ * possible. Therefore for cases where the user is directly booting
+ * a kernel, we treat the system as essentially uniprocessor, and
+ * put the secondary CPU into power-off state (as if the user on the
+ * real hardware had configured the secondary to be halted via the
+ * SCC config registers).
+ *
+ * Note that the default secondary boot code would not work here anyway
+ * as it assumes a GICv2, and we have a GICv3.
+ */
+static void mps3r_write_secondary_boot(ARMCPU *cpu,
+                                       const struct arm_boot_info *info)
+{
+    /*
+     * Power the secondary CPU off. This means we don't need to write any
+     * boot code into guest memory. Note that the 'cpu' argument to this
+     * function is the primary CPU we passed to arm_load_kernel(), not
+     * the secondary. Loop around all the other CPUs, as the boot.c
+     * code does for the "disable secondaries if PSCI is enabled" case.
+     */
+    for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        if (cs != first_cpu) {
+            object_property_set_bool(OBJECT(cs), "start-powered-off", true,
+                                     &error_abort);
+        }
+    }
+}
+
+static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
+                                      const struct arm_boot_info *info)
+{
+    /* We don't need to do anything here because the CPU will be off */
+}
+
+static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
+{
+    MachineState *machine = MACHINE(mms);
+    DeviceState *gicdev;
+    QList *redist_region_count;
+
+    object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
+    gicdev = DEVICE(&mms->gic);
+    qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
+    qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
+    redist_region_count = qlist_new();
+    qlist_append_int(redist_region_count, machine->smp.cpus);
+    qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
+    object_property_set_link(OBJECT(&mms->gic), "sysmem",
+                             OBJECT(sysmem), &error_fatal);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
+    /*
+     * Wire the outputs from each CPU's generic timer and the GICv3
+     * maintenance interrupt signal to the appropriate GIC PPI inputs,
+     * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
+     */
+    for (int i = 0; i < machine->smp.cpus; i++) {
+        DeviceState *cpudev = DEVICE(mms->cpu[i]);
+        SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
+        int intidbase = NUM_SPIS + i * GIC_INTERNAL;
+        int irq;
+        /*
+         * Mapping from the output timer irq lines from the CPU to the
+         * GIC PPI inputs used for this board. This isn't a BSA board,
+         * but it uses the standard convention for the PPI numbers.
+         */
+        const int timer_irq[] = {
+            [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
+            [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
+            [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
+        };
+
+        for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+            qdev_connect_gpio_out(cpudev, irq,
+                                  qdev_get_gpio_in(gicdev,
+                                                   intidbase + timer_irq[irq]));
+        }
+
+        qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
+                                    qdev_get_gpio_in(gicdev,
+                                                     intidbase + ARCH_GIC_MAINT_IRQ));
+
+        qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
+                                    qdev_get_gpio_in(gicdev,
+                                                     intidbase + VIRTUAL_PMU_IRQ));
+
+        sysbus_connect_irq(gicsbd, i,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+        sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+        sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+        sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
+                           qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
+    }
+}
+
 static void mps3r_common_init(MachineState *machine)
 {
     MPS3RMachineState *mms = MPS3R_MACHINE(machine);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
         MemoryRegion *mr = mr_for_raminfo(mms, ri);
         memory_region_add_subregion(sysmem, ri->base, mr);
     }
+
+    assert(machine->smp.cpus <= MPS3R_CPU_MAX);
+    for (int i = 0; i < machine->smp.cpus; i++) {
+        g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
+        g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
+        g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
+
+        /*
+         * Each CPU has some private RAM/peripherals, so create the container
+         * which will house those, with the whole-machine system memory being
+         * used where there's no CPU-specific device. Note that we need the
+         * sysmem_alias aliases because we can't put one MR (the original
+         * 'sysmem') into more than one other MR.
+         */
+        memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
+                           sysmem_name, UINT64_MAX);
+        memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
+                                 alias_name, sysmem, 0, UINT64_MAX);
+        memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
+                                            &mms->sysmem_alias[i], -1);
+
+        mms->cpu[i] = object_new(machine->cpu_type);
+        object_property_set_link(mms->cpu[i], "memory",
+                                 OBJECT(&mms->cpu_sysmem[i]), &error_abort);
+        object_property_set_int(mms->cpu[i], "reset-cbar",
+                                PERIPHBASE, &error_abort);
+        qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
+        object_unref(mms->cpu[i]);
+
+        /* Per-CPU RAM */
+        memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
+                               0x1000, &error_fatal);
+        memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
+                                    &mms->cpu_ram[i]);
+    }
+
+    create_gic(mms, sysmem);
+
+    mms->bootinfo.ram_size = machine->ram_size;
+    mms->bootinfo.board_id = -1;
+    mms->bootinfo.loader_start = mmc->loader_start;
+    mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
+    mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
+    arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
 }
 
 static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
             /* Found the entry for "system memory" */
             mc->default_ram_size = p->size;
             mc->default_ram_id = p->name;
+            mmc->loader_start = p->base;
             return;
         }
     }
@@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data)
     };
 
     mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
-    mc->default_cpus = 2;
-    mc->min_cpus = mc->default_cpus;
-    mc->max_cpus = mc->default_cpus;
+    /*
+     * In the real FPGA image there are always two cores, but the standard
+     * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
+     * that the second core is held in reset and halted. Many images built for
+     * the board do not expect the second core to run at startup (especially
+     * since on the real FPGA image it is not possible to use LDREX/STREX
+     * in RAM between the two cores, so a true SMP setup isn't supported).
+     *
+     * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
+     * with the default being -smp 1. This seems a more intuitive UI for
+     * QEMU users than, for instance, having a machine property to allow
+     * the user to set the initial value of the SYSCON 0x000 register.
+     */
+    mc->default_cpus = 1;
+    mc->min_cpus = 1;
+    mc->max_cpus = 2;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
     mc->valid_cpu_types = valid_cpu_types;
     mmc->raminfo = an536_raminfo;
-- 
2.34.1

This board has a lot of UARTs: there is one UART per CPU in the
per-CPU peripheral part of the address map, whose interrupts are
connected as per-CPU interrupt lines.  Then there are 4 UARTs in the
normal part of the peripheral space, whose interrupts are shared
peripheral interrupts.

Connect and wire them all up; this involves some OR gates where
multiple overflow interrupts are wired into one GIC input.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-11-peter.maydell@linaro.org
---
 hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/qmp/qlist.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
+#include "sysemu/sysemu.h"
 #include "hw/boards.h"
+#include "hw/or-irq.h"
 #include "hw/qdev-properties.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/bsa.h"
+#include "hw/char/cmsdk-apb-uart.h"
 #include "hw/intc/arm_gicv3.h"
 
 /* Define the layout of RAM and ROM in a board */
@@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo {
 
 #define MPS3R_RAM_MAX 9
 #define MPS3R_CPU_MAX 2
+#define MPS3R_UART_MAX 4 /* shared UART count */
 
 #define PERIPHBASE 0xf0000000
 #define NUM_SPIS 96
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
     MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
     MemoryRegion cpu_ram[MPS3R_CPU_MAX];
     GICv3State gic;
+    /* per-CPU UARTs followed by the shared UARTs */
+    CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
+    OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
+    OrIRQState uart_oflow;
 };
 
 #define TYPE_MPS3R_MACHINE "mps3r"
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
 
 OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
 
+/*
+ * Main clock frequency CLK in Hz (50MHz). In the image there are also
+ * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
+ * model we just roll them all into one.
+ */
+#define CLK_FRQ 50000000
+
 static const RAMInfo an536_raminfo[] = {
     {
         .name = "ATCM",
@@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
     }
 }
 
+/*
+ * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
+ * The qemu_irq arguments are where we connect the various IRQs from the UART.
+ */
+static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
+                        hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
+                        qemu_irq txoverirq, qemu_irq rxoverirq,
+                        qemu_irq combirq)
+{
+    g_autofree char *s = g_strdup_printf("uart%d", uartno);
+    SysBusDevice *sbd;
+
+    assert(uartno < ARRAY_SIZE(mms->uart));
+    object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
+                            TYPE_CMSDK_APB_UART);
+    qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
+    qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
+    sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(mem, baseaddr,
+                                sysbus_mmio_get_region(sbd, 0));
+    sysbus_connect_irq(sbd, 0, txirq);
+    sysbus_connect_irq(sbd, 1, rxirq);
+    sysbus_connect_irq(sbd, 2, txoverirq);
+    sysbus_connect_irq(sbd, 3, rxoverirq);
+    sysbus_connect_irq(sbd, 4, combirq);
+}
+
 static void mps3r_common_init(MachineState *machine)
 {
     MPS3RMachineState *mms = MPS3R_MACHINE(machine);
     MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
     MemoryRegion *sysmem = get_system_memory();
+    DeviceState *gicdev;
 
     for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
         MemoryRegion *mr = mr_for_raminfo(mms, ri);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
     }
 
     create_gic(mms, sysmem);
+    gicdev = DEVICE(&mms->gic);
+
+    /*
+     * UARTs 0 and 1 are per-CPU; their interrupts are wired to
+     * the relevant CPU's PPI 0..3, aka INTID 16..19
+     */
+    for (int i = 0; i < machine->smp.cpus; i++) {
+        int intidbase = NUM_SPIS + i * GIC_INTERNAL;
+        g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
+        DeviceState *orgate;
+
+        /* The two overflow IRQs from the UART are ORed together into PPI 3 */
+        object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
+                                TYPE_OR_IRQ);
+        orgate = DEVICE(&mms->cpu_uart_oflow[i]);
+        qdev_prop_set_uint32(orgate, "num-lines", 2);
+        qdev_realize(orgate, NULL, &error_fatal);
+        qdev_connect_gpio_out(orgate, 0,
+                              qdev_get_gpio_in(gicdev, intidbase + 19));
+
+        create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
+                    qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
+                    qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
+                    qdev_get_gpio_in(orgate, 0), /* txover */
+                    qdev_get_gpio_in(orgate, 1), /* rxover */
+                    qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
+    }
+    /*
+     * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
+     * together into IRQ 17
+     */
+    object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
+                            &mms->uart_oflow, TYPE_OR_IRQ);
+    qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
+                         MPS3R_UART_MAX * 2);
+    qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
+    qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
+                          qdev_get_gpio_in(gicdev, 17));
+
+    for (int i = 0; i < MPS3R_UART_MAX; i++) {
+        hwaddr baseaddr = 0xe0205000 + i * 0x1000;
+        int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
+
+        create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
+                    qdev_get_gpio_in(gicdev, txirq),
+                    qdev_get_gpio_in(gicdev, rxirq),
+                    qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
+                    qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
+                    qdev_get_gpio_in(gicdev, combirq));
+    }
 
     mms->bootinfo.ram_size = machine->ram_size;
     mms->bootinfo.board_id = -1;
-- 
2.34.1

Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536
board.  These are all simple devices that just need to be created and
wired up.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-12-peter.maydell@linaro.org
---
 hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
 #include "hw/or-irq.h"
+#include "hw/qdev-clock.h"
 #include "hw/qdev-properties.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/bsa.h"
 #include "hw/char/cmsdk-apb-uart.h"
+#include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/intc/arm_gicv3.h"
+#include "hw/misc/unimp.h"
+#include "hw/timer/cmsdk-apb-dualtimer.h"
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
 
 /* Define the layout of RAM and ROM in a board */
 typedef struct RAMInfo {
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
     CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
     OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
     OrIRQState uart_oflow;
+    CMSDKAPBWatchdog watchdog;
+    CMSDKAPBDualTimer dualtimer;
+    ArmSbconI2CState i2c[5];
+    Clock *clk;
 };
 
 #define TYPE_MPS3R_MACHINE "mps3r"
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
     MemoryRegion *sysmem = get_system_memory();
     DeviceState *gicdev;
 
+    mms->clk = clock_new(OBJECT(machine), "CLK");
+    clock_set_hz(mms->clk, CLK_FRQ);
+
     for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
         MemoryRegion *mr = mr_for_raminfo(mms, ri);
         memory_region_add_subregion(sysmem, ri->base, mr);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
                     qdev_get_gpio_in(gicdev, combirq));
     }
 
+    for (int i = 0; i < 4; i++) {
+        /* CMSDK GPIO controllers */
+        g_autofree char *s = g_strdup_printf("gpio%d", i);
+        create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
+    }
+
+    object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
+                            TYPE_CMSDK_APB_WATCHDOG);
+    qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
+                       qdev_get_gpio_in(gicdev, 0));
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
+
+    object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
+                            TYPE_CMSDK_APB_DUALTIMER);
+    qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
+                       qdev_get_gpio_in(gicdev, 3));
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
+                       qdev_get_gpio_in(gicdev, 1));
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
+                       qdev_get_gpio_in(gicdev, 2));
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
+
+    for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
+        static const hwaddr i2cbase[] = {0xe0102000,    /* Touch */
+                                         0xe0103000,    /* Audio */
+                                         0xe0107000,    /* Shield0 */
+                                         0xe0108000,    /* Shield1 */
+                                         0xe0109000};   /* DDR4 EEPROM */
+        g_autofree char *s = g_strdup_printf("i2c%d", i);
+
+        object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
+                                TYPE_ARM_SBCON_I2C);
+        sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
+        if (i != 2 && i != 3) {
+            /*
+             * internal-only bus: mark it full to avoid user-created
+             * i2c devices being plugged into it.
+             */
+            qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
+        }
+    }
+
     mms->bootinfo.ram_size = machine->ram_size;
     mms->bootinfo.board_id = -1;
     mms->bootinfo.loader_start = mmc->loader_start;
-- 
2.34.1

Add the remaining devices (or unimplemented-device stubs) for
this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the
QSPI write-config block, and ethernet.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-13-peter.maydell@linaro.org
---
 hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/cmsdk-apb-uart.h"
 #include "hw/i2c/arm_sbcon_i2c.h"
 #include "hw/intc/arm_gicv3.h"
+#include "hw/misc/mps2-scc.h"
+#include "hw/misc/mps2-fpgaio.h"
 #include "hw/misc/unimp.h"
+#include "hw/net/lan9118.h"
+#include "hw/rtc/pl031.h"
+#include "hw/ssi/pl022.h"
 #include "hw/timer/cmsdk-apb-dualtimer.h"
 #include "hw/watchdog/cmsdk-apb-watchdog.h"
 
@@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState {
     CMSDKAPBWatchdog watchdog;
     CMSDKAPBDualTimer dualtimer;
     ArmSbconI2CState i2c[5];
+    PL022State spi[3];
+    MPS2SCC scc;
+    MPS2FPGAIO fpgaio;
+    UnimplementedDeviceState i2s_audio;
+    PL031State rtc;
     Clock *clk;
 };
 
@@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = {
     }
 };
 
+static const int an536_oscclk[] = {
+    24000000, /* 24MHz reference for RTC and timers */
+    50000000, /* 50MHz ACLK */
+    50000000, /* 50MHz MCLK */
+    50000000, /* 50MHz GPUCLK */
+    24576000, /* 24.576MHz AUDCLK */
+    23750000, /* 23.75MHz HDLCDCLK */
+    100000000, /* 100MHz DDR4_REF_CLK */
+};
+
 static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
                                     const RAMInfo *raminfo)
 {
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
     MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
     MemoryRegion *sysmem = get_system_memory();
     DeviceState *gicdev;
+    QList *oscclk;
 
     mms->clk = clock_new(OBJECT(machine), "CLK");
     clock_set_hz(mms->clk, CLK_FRQ);
@@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine)
         }
     }
 
+    for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
+        g_autofree char *s = g_strdup_printf("spi%d", i);
+        hwaddr baseaddr = 0xe0104000 + i * 0x1000;
+
+        object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
+        sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
+                           qdev_get_gpio_in(gicdev, 22 + i));
+    }
+
+    object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
+    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
+    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
+    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
+    qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
+    oscclk = qlist_new();
+    for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
+        qlist_append_int(oscclk, an536_oscclk[i]);
+    }
+    qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
+
+    create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
+
+    object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
+                            TYPE_MPS2_FPGAIO);
+    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
+    qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
+    qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
+    qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
+
+    create_unimplemented_device("clcd", 0xe0209000, 0x1000);
+
+    object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
+    sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
+                       qdev_get_gpio_in(gicdev, 4));
+
+    /*
+     * In hardware this is a LAN9220; the LAN9118 is software compatible
+     * except that it doesn't support the checksum-offload feature.
+     */
+    lan9118_init(0xe0300000,
+                 qdev_get_gpio_in(gicdev, 18));
+
+    create_unimplemented_device("usb", 0xe0301000, 0x1000);
+    create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
+
     mms->bootinfo.ram_size = machine->ram_size;
     mms->bootinfo.board_id = -1;
     mms->bootinfo.loader_start = mmc->loader_start;
-- 
2.34.1

Add documentation for the mps3-an536 board type.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240206132931.38376-14-peter.maydell@linaro.org
---
 docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++---
 1 file changed, 34 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -XXX,XX +XXX,XX @@
-Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``)
-=========================================================================================================================================================
+Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``)
+=========================================================================================================================================================================
 
-These board models all use Arm M-profile CPUs.
+These board models use Arm M-profile or R-profile CPUs.
 
 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
@@ -XXX,XX +XXX,XX @@ FPGA image.
 
 QEMU models the following FPGA images:
 
+FPGA images using M-profile CPUs:
+
 ``mps2-an385``
   Cortex-M3 as documented in Arm Application Note AN385
 ``mps2-an386``
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
 ``mps3-an547``
   Cortex-M55 on an MPS3, as documented in Arm Application Note AN547
 
+FPGA images using R-profile CPUs:
+
+``mps3-an536``
+  Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536
+
 Differences between QEMU and real hardware:
 
 - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
@@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware:
   flash, but only as simple ROM, so attempting to rewrite the flash
   from the guest will fail
 - QEMU does not model the USB controller in MPS3 boards
+- AN536 does not support runtime control of CPU reset and halt via
+  the SCC CFG_REG0 register.
+- AN536 does not support enabling or disabling the flash and ATCM
+  interfaces via the SCC CFG_REG1 register.
+- AN536 does not support setting of the initial vector table
+  base address via the SCC CFG_REG6 and CFG_REG7 register config,
+  and does not provide a mechanism for specifying these values at
+  startup, so all guest images must be built to start from TCM
+  (i.e. to expect the interrupt vector base at 0 from reset).
+- AN536 defaults to only creating a single CPU; this is the equivalent
+  of the way the real FPGA image usually runs with the second Cortex-R52
+  held in halt via the initial SCC CFG_REG0 register setting. You can
+  create the second CPU with ``-smp 2``; both CPUs will then start
+  execution immediately on startup.
+
+Note that for the AN536 the first UART is accessible only by
+CPU0, and the second UART is accessible only by CPU1. The
+first UART accessible shared between both CPUs is the third
+UART. Guest software might therefore be built to use either
+the first UART or the third UART; if you don't see any output
+from the UART you are looking at, try one of the others.
+(Even if the AN536 machine is started with a single CPU and so
+no "CPU1-only UART", the UART numbering remains the same,
+with the third UART being the first of the shared ones.)
 
 Machine-specific options
 """"""""""""""""""""""""
-- 
2.34.1