[v1] target/ppc: Implement Dynamic Execution Control Registers

[PATCH 0/2] target/ppc: Implement Dynamic Execution Control Registers

Nicholas Miehlbradt posted 2 patches 1 year, 5 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20221124055143.752601-1-nicholas@linux.ibm.com

Maintainers: Daniel Henrique Barboza <danielhb413@gmail.com>, "Cédric Le Goater" <clg@kaod.org>, David Gibson <david@gibson.dropbear.id.au>, Greg Kurz <groug@kaod.org>

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target/ppc/cpu.h         | 19 +++++++++++++
target/ppc/cpu_init.c    | 25 +++++++++++++++++
target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
target/ppc/spr_common.h  |  1 +
target/ppc/translate.c   |  9 +++++++
5 files changed, 97 insertions(+), 15 deletions(-)

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[PATCH 0/2] target/ppc: Implement Dynamic Execution Control Registers

Posted by Nicholas Miehlbradt 1 year, 5 months ago

Implements the Dynamic Execution Control Register (DEXCR) and the
Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as 
defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction 
enable) and 6 (Privileged hash instruction enable) have architectural 
effects. Other aspects can be manipulated but have no effect on execution.

Adds checks to these registers in the hashst and hashchk instructions so
that they are executed as nops when not enabled.

Nicholas Miehlbradt (2):
  target/ppc: Implement the DEXCR and HDEXCR
  target/ppc: Check DEXCR on hash{st, chk} instructions

 target/ppc/cpu.h         | 19 +++++++++++++
 target/ppc/cpu_init.c    | 25 +++++++++++++++++
 target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
 target/ppc/spr_common.h  |  1 +
 target/ppc/translate.c   |  9 +++++++
 5 files changed, 97 insertions(+), 15 deletions(-)

-- 
2.34.1

Re: [PATCH 0/2] target/ppc: Implement Dynamic Execution Control Registers

Posted by Joel Stanley 1 year, 5 months ago

Hi Nick,

On Thu, 24 Nov 2022 at 05:53, Nicholas Miehlbradt
<nicholas@linux.ibm.com> wrote:
>
> Implements the Dynamic Execution Control Register (DEXCR) and the
> Hypervisor Dynamic Execution Control Register (HDEXCR) in TCG as
> defined in Power ISA 3.1B. Only aspects 5 (Non-privileged hash instruction
> enable) and 6 (Privileged hash instruction enable) have architectural
> effects. Other aspects can be manipulated but have no effect on execution.
>
> Adds checks to these registers in the hashst and hashchk instructions so
> that they are executed as nops when not enabled.

I had a look at these and they appear to follow the style of the
existing code. I am no expert on the target code though!

It might be worth mentioning to reviewers that these registers will be
exercised by the Linux kernel with some upcoming patches that you're
developing.

Cheers,

Joel

>
> Nicholas Miehlbradt (2):
>   target/ppc: Implement the DEXCR and HDEXCR
>   target/ppc: Check DEXCR on hash{st, chk} instructions
>
>  target/ppc/cpu.h         | 19 +++++++++++++
>  target/ppc/cpu_init.c    | 25 +++++++++++++++++
>  target/ppc/excp_helper.c | 58 +++++++++++++++++++++++++++++-----------
>  target/ppc/spr_common.h  |  1 +
>  target/ppc/translate.c   |  9 +++++++
>  5 files changed, 97 insertions(+), 15 deletions(-)
>
> --
> 2.34.1
>
>