| 1 | Hi; this pull request has a couple of fixes for bugs in | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | the Arm page-table-walk code, which arrived in the last | ||
| 3 | day or so. | ||
| 4 | 2 | ||
| 5 | I'm sending this out now in the hope it might just sneak | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 6 | in before rc2 gets tagged, so the fixes can get more | ||
| 7 | testing time before the 7.2 release; but if they don't | ||
| 8 | make it then this should go into rc3. | ||
| 9 | 4 | ||
| 10 | thanks | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 11 | -- PMM | ||
| 12 | |||
| 13 | The following changes since commit 6d71357a3b651ec9db126e4862b77e13165427f5: | ||
| 14 | |||
| 15 | rtl8139: honor large send MSS value (2022-11-21 09:28:43 -0500) | ||
| 16 | 6 | ||
| 17 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 18 | 8 | ||
| 19 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221122 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 20 | 10 | ||
| 21 | for you to fetch changes up to 15f8f4671afd22491ce99d28a296514717fead4f: | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 22 | 12 | ||
| 23 | target/arm: Use signed quantity to represent VMSAv8-64 translation level (2022-11-22 16:10:25 +0000) | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 24 | 14 | ||
| 25 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 26 | target-arm: | 16 | target-arm queue: |
| 27 | * Fix broken 5-level pagetable handling | 17 | * Implement IMPDEF pauth algorithm |
| 28 | * Fix debug accesses when EL2 is present | 18 | * Support ARMv8.4-SEL2 |
| 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns | ||
| 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set | ||
| 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error | ||
| 22 | * docs: Build and install all the docs in a single manual | ||
| 29 | 23 | ||
| 30 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 31 | Ard Biesheuvel (1): | 25 | Gan Qixin (1): |
| 32 | target/arm: Use signed quantity to represent VMSAv8-64 translation level | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 33 | 27 | ||
| 34 | Peter Maydell (1): | 28 | Peter Maydell (1): |
| 35 | target/arm: Don't do two-stage lookup if stage 2 is disabled | 29 | docs: Build and install all the docs in a single manual |
| 36 | 30 | ||
| 37 | target/arm/ptw.c | 11 ++++++----- | 31 | Philippe Mathieu-Daudé (1): |
| 38 | 1 file changed, 6 insertions(+), 5 deletions(-) | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 33 | |||
| 34 | Richard Henderson (7): | ||
| 35 | target/arm: Implement an IMPDEF pauth algorithm | ||
| 36 | target/arm: Add cpu properties to control pauth | ||
| 37 | target/arm: Use object_property_add_bool for "sve" property | ||
| 38 | target/arm: Introduce PREDDESC field definitions | ||
| 39 | target/arm: Update PFIRST, PNEXT for pred_desc | ||
| 40 | target/arm: Update ZIP, UZP, TRN for pred_desc | ||
| 41 | target/arm: Update REV, PUNPK for pred_desc | ||
| 42 | |||
| 43 | Rémi Denis-Courmont (19): | ||
| 44 | target/arm: remove redundant tests | ||
| 45 | target/arm: add arm_is_el2_enabled() helper | ||
| 46 | target/arm: use arm_is_el2_enabled() where applicable | ||
| 47 | target/arm: use arm_hcr_el2_eff() where applicable | ||
| 48 | target/arm: factor MDCR_EL2 common handling | ||
| 49 | target/arm: Define isar_feature function to test for presence of SEL2 | ||
| 50 | target/arm: add 64-bit S-EL2 to EL exception table | ||
| 51 | target/arm: add MMU stage 1 for Secure EL2 | ||
| 52 | target/arm: add ARMv8.4-SEL2 system registers | ||
| 53 | target/arm: handle VMID change in secure state | ||
| 54 | target/arm: do S1_ptw_translate() before address space lookup | ||
| 55 | target/arm: translate NS bit in page-walks | ||
| 56 | target/arm: generalize 2-stage page-walk condition | ||
| 57 | target/arm: secure stage 2 translation regime | ||
| 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults | ||
| 59 | target/arm: revector to run-time pick target EL | ||
| 60 | target/arm: Implement SCR_EL2.EEL2 | ||
| 61 | target/arm: enable Secure EL2 in max CPU | ||
| 62 | target/arm: refactor vae1_tlbmask() | ||
| 63 | |||
| 64 | docs/conf.py | 46 ++++- | ||
| 65 | docs/devel/conf.py | 15 -- | ||
| 66 | docs/index.html.in | 17 -- | ||
| 67 | docs/interop/conf.py | 28 --- | ||
| 68 | docs/meson.build | 64 +++--- | ||
| 69 | docs/specs/conf.py | 16 -- | ||
| 70 | docs/system/arm/cpu-features.rst | 21 ++ | ||
| 71 | docs/system/conf.py | 28 --- | ||
| 72 | docs/tools/conf.py | 37 ---- | ||
| 73 | docs/user/conf.py | 15 -- | ||
| 74 | include/qemu/xxhash.h | 98 +++++++++ | ||
| 75 | target/arm/cpu-param.h | 2 +- | ||
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 102 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In get_phys_addr_with_struct(), we call get_phys_addr_twostage() if | ||
| 2 | the CPU supports EL2. However, we don't check here that stage 2 is | ||
| 3 | actually enabled. Instead we only check that inside | ||
| 4 | get_phys_addr_twostage() to skip stage 2 translation. This means | ||
| 5 | that even if stage 2 is disabled we still tell the stage 1 lookup to | ||
| 6 | do its page table walks via stage 2. | ||
| 7 | 1 | ||
| 8 | This works by luck for normal CPU accesses, but it breaks for debug | ||
| 9 | accesses, which are used by the disassembler and also by semihosting | ||
| 10 | file reads and writes, because the debug case takes a different code | ||
| 11 | path inside S1_ptw_translate(). | ||
| 12 | |||
| 13 | This means that setups that use semihosting for file loads are broken | ||
| 14 | (a regression since 7.1, introduced in recent ptw refactoring), and | ||
| 15 | that sometimes disassembly in debug logs reports "unable to read | ||
| 16 | memory" rather than showing the guest insns. | ||
| 17 | |||
| 18 | Fix the bug by hoisting the "is stage 2 enabled?" check up to | ||
| 19 | get_phys_addr_with_struct(), so that we handle S2 disabled the same | ||
| 20 | way we do the "no EL2" case, with a simple single stage lookup. | ||
| 21 | |||
| 22 | Reported-by: Jens Wiklander <jens.wiklander@linaro.org> | ||
| 23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 25 | Message-id: 20221121212404.1450382-1-peter.maydell@linaro.org | ||
| 26 | --- | ||
| 27 | target/arm/ptw.c | 7 ++++--- | ||
| 28 | 1 file changed, 4 insertions(+), 3 deletions(-) | ||
| 29 | |||
| 30 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 31 | index XXXXXXX..XXXXXXX 100644 | ||
| 32 | --- a/target/arm/ptw.c | ||
| 33 | +++ b/target/arm/ptw.c | ||
| 34 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
| 35 | |||
| 36 | ret = get_phys_addr_with_struct(env, ptw, address, access_type, result, fi); | ||
| 37 | |||
| 38 | - /* If S1 fails or S2 is disabled, return early. */ | ||
| 39 | - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { | ||
| 40 | + /* If S1 fails, return early. */ | ||
| 41 | + if (ret) { | ||
| 42 | return ret; | ||
| 43 | } | ||
| 44 | |||
| 45 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
| 46 | * Otherwise, a stage1+stage2 translation is just stage 1. | ||
| 47 | */ | ||
| 48 | ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; | ||
| 49 | - if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 50 | + if (arm_feature(env, ARM_FEATURE_EL2) && | ||
| 51 | + !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { | ||
| 52 | return get_phys_addr_twostage(env, ptw, address, access_type, | ||
| 53 | result, fi); | ||
| 54 | } | ||
| 55 | -- | ||
| 56 | 2.25.1 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Ard Biesheuvel <ardb@kernel.org> | ||
| 2 | 1 | ||
| 3 | The LPA2 extension implements 52-bit virtual addressing for 4k and 16k | ||
| 4 | translation granules, and for the former, this means an additional level | ||
| 5 | of translation is needed. This means we start counting at -1 instead of | ||
| 6 | 0 when doing a walk, and so 'level' is now a signed quantity, and should | ||
| 7 | be typed as such. So turn it from uint32_t into int32_t. | ||
| 8 | |||
| 9 | This avoids a level of -1 getting misinterpreted as being >= 3, and | ||
| 10 | terminating a page table walk prematurely with a bogus output address. | ||
| 11 | |||
| 12 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 14 | Cc: Richard Henderson <richard.henderson@linaro.org> | ||
| 15 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | ||
| 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | --- | ||
| 19 | target/arm/ptw.c | 4 ++-- | ||
| 20 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/arm/ptw.c | ||
| 25 | +++ b/target/arm/ptw.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 27 | ARMCPU *cpu = env_archcpu(env); | ||
| 28 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; | ||
| 29 | bool is_secure = ptw->in_secure; | ||
| 30 | - uint32_t level; | ||
| 31 | + int32_t level; | ||
| 32 | ARMVAParameters param; | ||
| 33 | uint64_t ttbr; | ||
| 34 | hwaddr descaddr, indexmask, indexmask_grainsize; | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 36 | */ | ||
| 37 | uint32_t sl0 = extract32(tcr, 6, 2); | ||
| 38 | uint32_t sl2 = extract64(tcr, 33, 1); | ||
| 39 | - uint32_t startlevel; | ||
| 40 | + int32_t startlevel; | ||
| 41 | bool ok; | ||
| 42 | |||
| 43 | /* SL2 is RES0 unless DS=1 & 4kb granule. */ | ||
| 44 | -- | ||
| 45 | 2.25.1 | ||
| 46 | |||
| 47 | diff view generated by jsdifflib |