[PULL 0/5] target-arm queue
[PULL v2 00/57] target-arm queue
1
Hi; here's a collection of Arm bug fixes for rc2.
1
Squashed in a trivial fix for 32-bit hosts:
2
2
3
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
4
-- PMM
15
-- PMM
5
16
6
The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
7
18
8
Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
9
20
10
are available in the Git repository at:
21
are available in the Git repository at:
11
22
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
13
24
14
for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
15
26
16
target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
17
28
18
----------------------------------------------------------------
29
----------------------------------------------------------------
19
target-arm queue:
30
target-arm queue:
20
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
21
* hw/intc: add implementation of GICD_IIDR to Arm GIC
32
* docs: Document which architecture extensions we emulate
22
* tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
33
* Fix bugs in M-profile FPCXT_NS accesses
23
* target/arm: Limit LPA2 effective output address when TCR.DS == 0
34
* First slice of MVE patches
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Alex Bennée (2):
39
Alexandre Iooss (1):
27
hw/intc: clean-up access to GIC multi-byte registers
40
docs/system: arm: Add nRF boards description
28
hw/intc: add implementation of GICD_IIDR to Arm GIC
29
41
30
Ard Biesheuvel (1):
42
Peter Collingbourne (1):
31
target/arm: Limit LPA2 effective output address when TCR.DS == 0
43
target/arm: Implement MTE3
32
44
33
Peter Maydell (1):
45
Peter Maydell (55):
34
tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
35
101
36
Strahinja Jankovic (1):
102
docs/system/arm/emulation.rst | 103 ++++
37
hw/sd: Fix sun4i allwinner-sdhost for U-Boot
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
38
135
39
include/hw/sd/allwinner-sdhost.h | 1 +
40
hw/intc/arm_gic.c | 28 ++++++++++++-----
41
hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++-------------
42
target/arm/ptw.c | 8 +++++
43
tests/avocado/boot_linux.py | 2 +-
44
5 files changed, 77 insertions(+), 29 deletions(-)
45
diff view generated by jsdifflib
[PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot
Deleted patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
2
1
3
Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot
4
access SD card. The problem is that FIFO register in current
5
allwinner-sdhost implementation is at the address corresponding to
6
Allwinner H3, but not A10.
7
Linux kernel is not affected since Linux driver uses DMA access and does
8
not use FIFO register for reading/writing.
9
10
This patch adds new class parameter `is_sun4i` and based on that
11
parameter uses register at offset 0x100 either as FIFO register (if
12
sun4i) or as threshold register (if not sun4i; in this case register at
13
0x200 is FIFO register).
14
15
Tested with U-Boot and Linux kernel image built for Cubieboard and
16
OrangePi PC.
17
18
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
include/hw/sd/allwinner-sdhost.h | 1 +
24
hw/sd/allwinner-sdhost.c | 67 ++++++++++++++++++++++----------
25
2 files changed, 47 insertions(+), 21 deletions(-)
26
27
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/sd/allwinner-sdhost.h
30
+++ b/include/hw/sd/allwinner-sdhost.h
31
@@ -XXX,XX +XXX,XX @@ struct AwSdHostClass {
32
33
/** Maximum buffer size in bytes per DMA descriptor */
34
size_t max_desc_size;
35
+ bool is_sun4i;
36
37
};
38
39
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/sd/allwinner-sdhost.c
42
+++ b/hw/sd/allwinner-sdhost.c
43
@@ -XXX,XX +XXX,XX @@ enum {
44
REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
45
REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
46
REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
47
- REG_SD_THLDC = 0x100, /* Card Threshold Control */
48
+ REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
49
REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
50
REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
51
REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
52
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_dma(AwSdHostState *s)
53
}
54
}
55
56
+static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
57
+{
58
+ uint32_t res = 0;
59
+
60
+ if (sdbus_data_ready(&s->sdbus)) {
61
+ sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
62
+ le32_to_cpus(&res);
63
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
64
+ allwinner_sdhost_auto_stop(s);
65
+ allwinner_sdhost_update_irq(s);
66
+ } else {
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
68
+ __func__);
69
+ }
70
+
71
+ return res;
72
+}
73
+
74
static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
75
unsigned size)
76
{
77
AwSdHostState *s = AW_SDHOST(opaque);
78
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
79
uint32_t res = 0;
80
81
switch (offset) {
82
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
83
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
84
res = s->dmac_irq;
85
break;
86
- case REG_SD_THLDC: /* Card Threshold Control */
87
- res = s->card_threshold;
88
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
89
+ if (sc->is_sun4i) {
90
+ res = allwinner_sdhost_fifo_read(s);
91
+ } else {
92
+ res = s->card_threshold;
93
+ }
94
break;
95
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
96
res = s->startbit_detect;
97
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
98
res = s->status_crc;
99
break;
100
case REG_SD_FIFO: /* Read/Write FIFO */
101
- if (sdbus_data_ready(&s->sdbus)) {
102
- sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
103
- le32_to_cpus(&res);
104
- allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
105
- allwinner_sdhost_auto_stop(s);
106
- allwinner_sdhost_update_irq(s);
107
- } else {
108
- qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
109
- __func__);
110
- }
111
+ res = allwinner_sdhost_fifo_read(s);
112
break;
113
default:
114
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
115
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
116
return res;
117
}
118
119
+static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
120
+{
121
+ uint32_t u32 = cpu_to_le32(value);
122
+ sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
123
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
124
+ allwinner_sdhost_auto_stop(s);
125
+ allwinner_sdhost_update_irq(s);
126
+}
127
+
128
static void allwinner_sdhost_write(void *opaque, hwaddr offset,
129
uint64_t value, unsigned size)
130
{
131
AwSdHostState *s = AW_SDHOST(opaque);
132
- uint32_t u32;
133
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
134
135
trace_allwinner_sdhost_write(offset, value, size);
136
137
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
138
s->dmac_irq = value;
139
allwinner_sdhost_update_irq(s);
140
break;
141
- case REG_SD_THLDC: /* Card Threshold Control */
142
- s->card_threshold = value;
143
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
144
+ if (sc->is_sun4i) {
145
+ allwinner_sdhost_fifo_write(s, value);
146
+ } else {
147
+ s->card_threshold = value;
148
+ }
149
break;
150
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
151
s->startbit_detect = value;
152
break;
153
case REG_SD_FIFO: /* Read/Write FIFO */
154
- u32 = cpu_to_le32(value);
155
- sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
156
- allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
157
- allwinner_sdhost_auto_stop(s);
158
- allwinner_sdhost_update_irq(s);
159
+ allwinner_sdhost_fifo_write(s, value);
160
break;
161
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
162
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
163
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
164
{
165
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
166
sc->max_desc_size = 8 * KiB;
167
+ sc->is_sun4i = true;
168
}
169
170
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
171
{
172
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
173
sc->max_desc_size = 64 * KiB;
174
+ sc->is_sun4i = false;
175
}
176
177
static const TypeInfo allwinner_sdhost_info = {
178
--
179
2.25.1
diff view generated by jsdifflib
[PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
gic_dist_readb was returning a word value which just happened to work
4
as a result of the way we OR the data together. Lets fix it so only
5
the explicit byte is returned for each part of GICD_TYPER. I've
6
changed the return type to uint8_t although the overflow is only
7
detected with an explicit -Wconversion.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/intc/arm_gic.c | 16 ++++++++++------
16
1 file changed, 10 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/arm_gic.c
21
+++ b/hw/intc/arm_gic.c
22
@@ -XXX,XX +XXX,XX @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
23
gic_update(s);
24
}
25
26
-static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
27
+static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
28
{
29
GICState *s = (GICState *)opaque;
30
uint32_t res;
31
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
32
cm = 1 << cpu;
33
if (offset < 0x100) {
34
if (offset == 0) { /* GICD_CTLR */
35
+ /* We rely here on the only non-zero bits being in byte 0 */
36
if (s->security_extn && !attrs.secure) {
37
/* The NS bank of this register is just an alias of the
38
* EnableGrp1 bit in the S bank version.
39
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
40
return s->ctlr;
41
}
42
}
43
- if (offset == 4)
44
- /* Interrupt Controller Type Register */
45
- return ((s->num_irq / 32) - 1)
46
- | ((s->num_cpu - 1) << 5)
47
- | (s->security_extn << 10);
48
+ if (offset == 4) {
49
+ /* GICD_TYPER byte 0 */
50
+ return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
51
+ }
52
+ if (offset == 5) {
53
+ /* GICD_TYPER byte 1 */
54
+ return (s->security_extn << 2);
55
+ }
56
if (offset < 0x08)
57
return 0;
58
if (offset >= 0x80) {
59
--
60
2.25.1
61
62
diff view generated by jsdifflib
[PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
4
this for the CPU interface register. The fact we don't implement it
5
shows up when running Xen with -d guest_error which is definitely
6
wrong because the guest is perfectly entitled to read it.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/intc/arm_gic.c | 12 +++++++++++-
14
1 file changed, 11 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gic.c
19
+++ b/hw/intc/arm_gic.c
20
@@ -XXX,XX +XXX,XX @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
21
/* GICD_TYPER byte 1 */
22
return (s->security_extn << 2);
23
}
24
- if (offset < 0x08)
25
+ if (offset == 8) {
26
+ /* GICD_IIDR byte 0 */
27
+ return 0x3b; /* Arm JEP106 identity */
28
+ }
29
+ if (offset == 9) {
30
+ /* GICD_IIDR byte 1 */
31
+ return 0x04; /* Arm JEP106 identity */
32
+ }
33
+ if (offset < 0x0c) {
34
+ /* All other bytes in this range are RAZ */
35
return 0;
36
+ }
37
if (offset >= 0x80) {
38
/* Interrupt Group Registers: these RAZ/WI if this is an NS
39
* access to a GIC with the security extensions, or if the GIC
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
[PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
Deleted patch
1
The two tests
2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
3
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
4
1
5
take quite a long time to run, and the current timeout of 240s
6
is not enough for the tests to complete on slow machines:
7
we've seen these tests time out in the gitlab CI in the
8
'avocado-system-alpine' CI job, for instance. The timeout
9
is also insufficient for running the test with a debug build
10
of QEMU: on my machine the tests take over 10 minutes to run
11
in that config.
12
13
Push the timeout up to 720s so that the test definitely has
14
enough time to complete.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Thomas Huth <thuth@redhat.com>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
---
20
tests/avocado/boot_linux.py | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tests/avocado/boot_linux.py
26
+++ b/tests/avocado/boot_linux.py
27
@@ -XXX,XX +XXX,XX @@ class BootLinuxAarch64(LinuxTest):
28
:avocado: tags=machine:virt
29
:avocado: tags=machine:gic-version=2
30
"""
31
- timeout = 240
32
+ timeout = 720
33
34
def add_common_args(self):
35
self.vm.add_args('-bios',
36
--
37
2.25.1
38
39
diff view generated by jsdifflib
[PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0
Deleted patch
1
From: Ard Biesheuvel <ardb@kernel.org>
2
1
3
With LPA2, the effective output address size is at most 48 bits when
4
TCR.DS == 0. This case is currently unhandled in the page table walker,
5
where we happily assume LVA/64k granule when outputsize > 48 and
6
param.ds == 0, resulting in the wrong conversion to be used from a
7
page table descriptor to a physical address.
8
9
if (outputsize > 48) {
10
if (param.ds) {
11
descaddr |= extract64(descriptor, 8, 2) << 50;
12
} else {
13
descaddr |= extract64(descriptor, 12, 4) << 48;
14
}
15
16
So cap the outputsize to 48 when TCR.DS is cleared, as per the
17
architecture.
18
19
Cc: Peter Maydell <peter.maydell@linaro.org>
20
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Cc: Richard Henderson <richard.henderson@linaro.org>
22
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20221116170316.259695-1-ardb@kernel.org
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
target/arm/ptw.c | 8 ++++++++
28
1 file changed, 8 insertions(+)
29
30
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/ptw.c
33
+++ b/target/arm/ptw.c
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
35
ps = MIN(ps, param.ps);
36
assert(ps < ARRAY_SIZE(pamax_map));
37
outputsize = pamax_map[ps];
38
+
39
+ /*
40
+ * With LPA2, the effective output address (OA) size is at most 48 bits
41
+ * unless TCR.DS == 1
42
+ */
43
+ if (!param.ds && param.gran != Gran64K) {
44
+ outputsize = MIN(outputsize, 48);
45
+ }
46
} else {
47
param = aa32_va_parameters(env, address, mmu_idx);
48
level = 1;
49
--
50
2.25.1
51
52
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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