[PULL 0/5] target-arm queue
[Qemu-devel] [PULL v2 00/23] target-arm queue
1
Hi; here's a collection of Arm bug fixes for rc2.
1
v2: dropped patches that add the microbit nRF51 non-volatile memories
2
and the test case for them.
2
3
3
thanks
4
thanks
4
-- PMM
5
-- PMM
5
6
6
The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:
7
7
8
Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500)
8
The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:
9
10
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)
9
11
10
are available in the Git repository at:
12
are available in the Git repository at:
11
13
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129
13
15
14
for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:
16
for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:
15
17
16
target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000)
18
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
22
* Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
21
* hw/intc: add implementation of GICD_IIDR to Arm GIC
23
* v8m: Ensure IDAU is respected if SAU is disabled
22
* tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
24
* gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
23
* target/arm: Limit LPA2 effective output address when TCR.DS == 0
25
* exec.c: Use correct attrs in cpu_memory_rw_debug()
26
* accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
27
* target/arm: Don't clear supported PMU events when initializing PMCEID1
28
* memory: add memory_region_flush_rom_device()
29
* microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
30
* tests/microbit-test: extend testing of microbit devices
31
* checkpatch: Don't emit spurious warnings about block comments
32
* aspeed/smc: misc bug fixes
33
* xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
34
* xlnx-zynqmp: Realize cluster after putting RPUs in it
35
* accel/tcg: Add cluster number to TCG TB hash so differently configured
36
CPUs don't pick up cached TBs for the wrong kind of CPU
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Alex Bennée (2):
39
Aaron Lindsay OS (1):
27
hw/intc: clean-up access to GIC multi-byte registers
40
target/arm: Don't clear supported PMU events when initializing PMCEID1
28
hw/intc: add implementation of GICD_IIDR to Arm GIC
29
41
30
Ard Biesheuvel (1):
42
Cédric Le Goater (4):
31
target/arm: Limit LPA2 effective output address when TCR.DS == 0
43
aspeed/smc: fix default read value
44
aspeed/smc: define registers for all possible CS
45
aspeed/smc: Add dummy data register
46
aspeed/smc: snoop SPI transfers to fake dummy cycles
32
47
33
Peter Maydell (1):
48
Julia Suvorova (3):
34
tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
49
tests/libqtest: Introduce qtest_init_with_serial()
50
tests/microbit-test: Make test independent of global_qtest
51
tests/microbit-test: Check nRF51 UART functionality
35
52
36
Strahinja Jankovic (1):
53
Luc Michel (1):
37
hw/sd: Fix sun4i allwinner-sdhost for U-Boot
54
gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
38
55
39
include/hw/sd/allwinner-sdhost.h | 1 +
56
Peter Maydell (8):
40
hw/intc/arm_gic.c | 28 ++++++++++++-----
57
exec.c: Use correct attrs in cpu_memory_rw_debug()
41
hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++-------------
58
accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
42
target/arm/ptw.c | 8 +++++
59
checkpatch: Don't emit spurious warnings about block comments
43
tests/avocado/boot_linux.py | 2 +-
60
xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
44
5 files changed, 77 insertions(+), 29 deletions(-)
61
hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
62
qom/cpu: Add cluster_index to CPUState
63
accel/tcg: Add cluster number to TCG TB hash
64
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
45
65
66
Richard Henderson (1):
67
target/arm: Fix validation of 32-bit address spaces for aa32
68
69
Stefan Hajnoczi (3):
70
tests/microbit-test: add TWI stub device test
71
MAINTAINERS: update microbit ARM board files
72
memory: add memory_region_flush_rom_device()
73
74
Steffen Görtz (1):
75
arm: Stub out NRF51 TWI magnetometer/accelerometer detection
76
77
Thomas Roth (1):
78
target/arm: v8m: Ensure IDAU is respected if SAU is disabled
79
80
hw/i2c/Makefile.objs | 1 +
81
include/exec/exec-all.h | 4 +-
82
include/exec/memory.h | 18 +++
83
include/hw/arm/nrf51.h | 2 +
84
include/hw/arm/nrf51_soc.h | 1 +
85
include/hw/cpu/cluster.h | 24 +++
86
include/hw/i2c/microbit_i2c.h | 42 +++++
87
include/hw/ssi/aspeed_smc.h | 3 +
88
include/qom/cpu.h | 7 +
89
target/arm/cpu.h | 11 +-
90
tests/libqtest.h | 11 ++
91
accel/tcg/cpu-exec.c | 3 +
92
accel/tcg/translate-all.c | 3 +
93
accel/tcg/user-exec.c | 66 ++++++--
94
exec.c | 19 ++-
95
gdbstub.c | 120 ++++++---------
96
hw/arm/microbit.c | 16 ++
97
hw/arm/xlnx-zynqmp.c | 9 +-
98
hw/cpu/cluster.c | 46 ++++++
99
hw/i2c/microbit_i2c.c | 127 +++++++++++++++
100
hw/ssi/aspeed_smc.c | 128 ++++++++++++++-
101
qom/cpu.c | 1 +
102
target/arm/cpu.c | 3 +-
103
target/arm/helper.c | 67 ++++----
104
tests/libqtest.c | 25 +++
105
tests/microbit-test.c | 350 +++++++++++++++++++++++++++++-------------
106
MAINTAINERS | 8 +-
107
scripts/checkpatch.pl | 2 +-
108
28 files changed, 874 insertions(+), 243 deletions(-)
109
create mode 100644 include/hw/i2c/microbit_i2c.h
110
create mode 100644 hw/i2c/microbit_i2c.c
111
diff view generated by jsdifflib
[PULL 1/5] hw/sd: Fix sun4i allwinner-sdhost for U-Boot
Deleted patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
2
1
3
Trying to run U-Boot for Cubieboard (Allwinner A10) fails because it cannot
4
access SD card. The problem is that FIFO register in current
5
allwinner-sdhost implementation is at the address corresponding to
6
Allwinner H3, but not A10.
7
Linux kernel is not affected since Linux driver uses DMA access and does
8
not use FIFO register for reading/writing.
9
10
This patch adds new class parameter `is_sun4i` and based on that
11
parameter uses register at offset 0x100 either as FIFO register (if
12
sun4i) or as threshold register (if not sun4i; in this case register at
13
0x200 is FIFO register).
14
15
Tested with U-Boot and Linux kernel image built for Cubieboard and
16
OrangePi PC.
17
18
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Message-id: 20221112214900.24152-1-strahinja.p.jankovic@gmail.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
include/hw/sd/allwinner-sdhost.h | 1 +
24
hw/sd/allwinner-sdhost.c | 67 ++++++++++++++++++++++----------
25
2 files changed, 47 insertions(+), 21 deletions(-)
26
27
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/sd/allwinner-sdhost.h
30
+++ b/include/hw/sd/allwinner-sdhost.h
31
@@ -XXX,XX +XXX,XX @@ struct AwSdHostClass {
32
33
/** Maximum buffer size in bytes per DMA descriptor */
34
size_t max_desc_size;
35
+ bool is_sun4i;
36
37
};
38
39
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/sd/allwinner-sdhost.c
42
+++ b/hw/sd/allwinner-sdhost.c
43
@@ -XXX,XX +XXX,XX @@ enum {
44
REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
45
REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
46
REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
47
- REG_SD_THLDC = 0x100, /* Card Threshold Control */
48
+ REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
49
REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
50
REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
51
REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
52
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_dma(AwSdHostState *s)
53
}
54
}
55
56
+static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
57
+{
58
+ uint32_t res = 0;
59
+
60
+ if (sdbus_data_ready(&s->sdbus)) {
61
+ sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
62
+ le32_to_cpus(&res);
63
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
64
+ allwinner_sdhost_auto_stop(s);
65
+ allwinner_sdhost_update_irq(s);
66
+ } else {
67
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
68
+ __func__);
69
+ }
70
+
71
+ return res;
72
+}
73
+
74
static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
75
unsigned size)
76
{
77
AwSdHostState *s = AW_SDHOST(opaque);
78
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
79
uint32_t res = 0;
80
81
switch (offset) {
82
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
83
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
84
res = s->dmac_irq;
85
break;
86
- case REG_SD_THLDC: /* Card Threshold Control */
87
- res = s->card_threshold;
88
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
89
+ if (sc->is_sun4i) {
90
+ res = allwinner_sdhost_fifo_read(s);
91
+ } else {
92
+ res = s->card_threshold;
93
+ }
94
break;
95
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
96
res = s->startbit_detect;
97
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
98
res = s->status_crc;
99
break;
100
case REG_SD_FIFO: /* Read/Write FIFO */
101
- if (sdbus_data_ready(&s->sdbus)) {
102
- sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
103
- le32_to_cpus(&res);
104
- allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
105
- allwinner_sdhost_auto_stop(s);
106
- allwinner_sdhost_update_irq(s);
107
- } else {
108
- qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
109
- __func__);
110
- }
111
+ res = allwinner_sdhost_fifo_read(s);
112
break;
113
default:
114
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
115
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
116
return res;
117
}
118
119
+static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
120
+{
121
+ uint32_t u32 = cpu_to_le32(value);
122
+ sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
123
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
124
+ allwinner_sdhost_auto_stop(s);
125
+ allwinner_sdhost_update_irq(s);
126
+}
127
+
128
static void allwinner_sdhost_write(void *opaque, hwaddr offset,
129
uint64_t value, unsigned size)
130
{
131
AwSdHostState *s = AW_SDHOST(opaque);
132
- uint32_t u32;
133
+ AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
134
135
trace_allwinner_sdhost_write(offset, value, size);
136
137
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
138
s->dmac_irq = value;
139
allwinner_sdhost_update_irq(s);
140
break;
141
- case REG_SD_THLDC: /* Card Threshold Control */
142
- s->card_threshold = value;
143
+ case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
144
+ if (sc->is_sun4i) {
145
+ allwinner_sdhost_fifo_write(s, value);
146
+ } else {
147
+ s->card_threshold = value;
148
+ }
149
break;
150
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
151
s->startbit_detect = value;
152
break;
153
case REG_SD_FIFO: /* Read/Write FIFO */
154
- u32 = cpu_to_le32(value);
155
- sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
156
- allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
157
- allwinner_sdhost_auto_stop(s);
158
- allwinner_sdhost_update_irq(s);
159
+ allwinner_sdhost_fifo_write(s, value);
160
break;
161
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
162
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
163
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
164
{
165
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
166
sc->max_desc_size = 8 * KiB;
167
+ sc->is_sun4i = true;
168
}
169
170
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
171
{
172
AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
173
sc->max_desc_size = 64 * KiB;
174
+ sc->is_sun4i = false;
175
}
176
177
static const TypeInfo allwinner_sdhost_info = {
178
--
179
2.25.1
diff view generated by jsdifflib
[PULL 2/5] hw/intc: clean-up access to GIC multi-byte registers
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
gic_dist_readb was returning a word value which just happened to work
4
as a result of the way we OR the data together. Lets fix it so only
5
the explicit byte is returned for each part of GICD_TYPER. I've
6
changed the return type to uint8_t although the overflow is only
7
detected with an explicit -Wconversion.
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/intc/arm_gic.c | 16 ++++++++++------
16
1 file changed, 10 insertions(+), 6 deletions(-)
17
18
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/arm_gic.c
21
+++ b/hw/intc/arm_gic.c
22
@@ -XXX,XX +XXX,XX @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
23
gic_update(s);
24
}
25
26
-static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
27
+static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
28
{
29
GICState *s = (GICState *)opaque;
30
uint32_t res;
31
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
32
cm = 1 << cpu;
33
if (offset < 0x100) {
34
if (offset == 0) { /* GICD_CTLR */
35
+ /* We rely here on the only non-zero bits being in byte 0 */
36
if (s->security_extn && !attrs.secure) {
37
/* The NS bank of this register is just an alias of the
38
* EnableGrp1 bit in the S bank version.
39
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
40
return s->ctlr;
41
}
42
}
43
- if (offset == 4)
44
- /* Interrupt Controller Type Register */
45
- return ((s->num_irq / 32) - 1)
46
- | ((s->num_cpu - 1) << 5)
47
- | (s->security_extn << 10);
48
+ if (offset == 4) {
49
+ /* GICD_TYPER byte 0 */
50
+ return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
51
+ }
52
+ if (offset == 5) {
53
+ /* GICD_TYPER byte 1 */
54
+ return (s->security_extn << 2);
55
+ }
56
if (offset < 0x08)
57
return 0;
58
if (offset >= 0x80) {
59
--
60
2.25.1
61
62
diff view generated by jsdifflib
[PULL 3/5] hw/intc: add implementation of GICD_IIDR to Arm GIC
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
a66a24585f (hw/intc/arm_gic: Implement read of GICC_IIDR) implemented
4
this for the CPU interface register. The fact we don't implement it
5
shows up when running Xen with -d guest_error which is definitely
6
wrong because the guest is perfectly entitled to read it.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/intc/arm_gic.c | 12 +++++++++++-
14
1 file changed, 11 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gic.c
19
+++ b/hw/intc/arm_gic.c
20
@@ -XXX,XX +XXX,XX @@ static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
21
/* GICD_TYPER byte 1 */
22
return (s->security_extn << 2);
23
}
24
- if (offset < 0x08)
25
+ if (offset == 8) {
26
+ /* GICD_IIDR byte 0 */
27
+ return 0x3b; /* Arm JEP106 identity */
28
+ }
29
+ if (offset == 9) {
30
+ /* GICD_IIDR byte 1 */
31
+ return 0x04; /* Arm JEP106 identity */
32
+ }
33
+ if (offset < 0x0c) {
34
+ /* All other bytes in this range are RAZ */
35
return 0;
36
+ }
37
if (offset >= 0x80) {
38
/* Interrupt Group Registers: these RAZ/WI if this is an NS
39
* access to a GIC with the security extensions, or if the GIC
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
[PULL 4/5] tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
Deleted patch
1
The two tests
2
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv2
3
tests/avocado/boot_linux.py:BootLinuxAarch64.test_virt_tcg_gicv3
4
1
5
take quite a long time to run, and the current timeout of 240s
6
is not enough for the tests to complete on slow machines:
7
we've seen these tests time out in the gitlab CI in the
8
'avocado-system-alpine' CI job, for instance. The timeout
9
is also insufficient for running the test with a debug build
10
of QEMU: on my machine the tests take over 10 minutes to run
11
in that config.
12
13
Push the timeout up to 720s so that the test definitely has
14
enough time to complete.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Thomas Huth <thuth@redhat.com>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
---
20
tests/avocado/boot_linux.py | 2 +-
21
1 file changed, 1 insertion(+), 1 deletion(-)
22
23
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tests/avocado/boot_linux.py
26
+++ b/tests/avocado/boot_linux.py
27
@@ -XXX,XX +XXX,XX @@ class BootLinuxAarch64(LinuxTest):
28
:avocado: tags=machine:virt
29
:avocado: tags=machine:gic-version=2
30
"""
31
- timeout = 240
32
+ timeout = 720
33
34
def add_common_args(self):
35
self.vm.add_args('-bios',
36
--
37
2.25.1
38
39
diff view generated by jsdifflib
[PULL 5/5] target/arm: Limit LPA2 effective output address when TCR.DS == 0
Deleted patch
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From: Ard Biesheuvel <ardb@kernel.org>
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With LPA2, the effective output address size is at most 48 bits when
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TCR.DS == 0. This case is currently unhandled in the page table walker,
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where we happily assume LVA/64k granule when outputsize > 48 and
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param.ds == 0, resulting in the wrong conversion to be used from a
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page table descriptor to a physical address.
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if (outputsize > 48) {
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if (param.ds) {
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descaddr |= extract64(descriptor, 8, 2) << 50;
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} else {
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descaddr |= extract64(descriptor, 12, 4) << 48;
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}
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So cap the outputsize to 48 when TCR.DS is cleared, as per the
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architecture.
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Cc: Peter Maydell <peter.maydell@linaro.org>
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Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Cc: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20221116170316.259695-1-ardb@kernel.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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ps = MIN(ps, param.ps);
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assert(ps < ARRAY_SIZE(pamax_map));
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outputsize = pamax_map[ps];
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+
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+ /*
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+ * With LPA2, the effective output address (OA) size is at most 48 bits
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+ * unless TCR.DS == 1
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+ */
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+ if (!param.ds && param.gran != Gran64K) {
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+ outputsize = MIN(outputsize, 48);
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+ }
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} else {
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param = aa32_va_parameters(env, address, mmu_idx);
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level = 1;
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--
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2.25.1
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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