Series comparison

-[PULL 0/7] loongarch-to-apply queue
+[PULL 00/18] loongarch-to-apply queue
-The following changes since commit a11f65ec1b8adcb012b89c92819cbda4dc25aaf1:
+The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
-  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2022-11-01 13:49:33 -0400)
+  Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)
 are available in the Git repository at:
-  https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221103
+  https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213
-for you to fetch changes up to d31e2b1af7e6db41e6088679babc3893bd69b4b3:
+for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:
-  target/loongarch: Fix raise_mmu_exception() set wrong exception_index (2022-11-03 17:59:19 +0800)
+  hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)
 ----------------------------------------------------------------
-pull-loongarch-20221103
+pull-loongarch-20241213
 ----------------------------------------------------------------
-Song Gao (2):
+Bibo Mao (8):
-      target/loongarch: Add exception subcode
+      include: Add loongarch_pic_common header file
-      target/loongarch: Fix raise_mmu_exception() set wrong exception_index
+      include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
       hw/intc/loongarch_pch: Merge instance_init() into realize()
       hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
       hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
       hw/intc/loongarch_pch: Inherit from loongarch_pic_common
       hw/intc/loongarch_pch: Add pre_save and post_load interfaces
       hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
-Xiaojuan Yang (5):
+ hw/intc/loongarch_pch_pic.c            | 106 +++++++++++----------------------
-      hw/intc: Convert the memops to with_attrs in LoongArch extioi
+ hw/intc/loongarch_pic_common.c         |  97 ++++++++++++++++++++++++++++++
-      hw/intc: Fix LoongArch extioi coreisr accessing
+ hw/intc/meson.build                    |   2 +-
-      hw/loongarch: Load FDT table into dram memory space
+ hw/loongarch/virt.c                    |   2 +-
-      hw/loongarch: Improve fdt for LoongArch virt machine
+ include/hw/intc/loongarch_pch_pic.h    |  70 +++++-----------------
-      hw/loongarch: Add TPM device for LoongArch virt machine
+ include/hw/intc/loongarch_pic_common.h |  82 +++++++++++++++++++++++++
+files changed, 230 insertions(+), 129 deletions(-)
- hw/intc/loongarch_extioi.c      | 41 ++++++++++++++++-------------
+ create mode 100644 hw/intc/loongarch_pic_common.c
- hw/intc/trace-events            |  3 +--
+ create mode 100644 include/hw/intc/loongarch_pic_common.h
  hw/loongarch/acpi-build.c       | 50 +++++++++++++++++++++++++++++++++--
  hw/loongarch/virt.c             | 53 ++++++++++++++++++++++++++++++++-----
  include/hw/loongarch/virt.h     |  3 ---
  include/hw/pci-host/ls7a.h      |  1 +
  target/loongarch/cpu.c          |  8 ++++--
  target/loongarch/cpu.h          | 58 ++++++++++++++++++++++-------------------
  target/loongarch/iocsr_helper.c | 19 ++++++++------
  target/loongarch/tlb_helper.c   |  5 ++--
 files changed, 170 insertions(+), 71 deletions(-)

-New patch
+[PULL 01/18] include: Add loongarch_pic_common header file
+Add common header file hw/intc/loongarch_pic_common.h, and move
+some macro definition from hw/intc/loongarch_pch_pic.h to the common
+header file.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
+---
+ include/hw/intc/loongarch_pch_pic.h    | 36 +++-------------------
+ include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
+files changed, 47 insertions(+), 31 deletions(-)
+ create mode 100644 include/hw/intc/loongarch_pic_common.h
+diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_pch_pic.h
++++ b/include/hw/intc/loongarch_pch_pic.h
+@@ -XXX,XX +XXX,XX @@
+  * Copyright (c) 2021 Loongson Technology Corporation Limited
+  */
+-#include "hw/sysbus.h"
++#ifndef HW_LOONGARCH_PCH_PIC_H
++#define HW_LOONGARCH_PCH_PIC_H
++
++#include "hw/intc/loongarch_pic_common.h"
+ #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
+ #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
+ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
+-#define PCH_PIC_INT_ID_VAL              0x7000000UL
+-#define PCH_PIC_INT_ID_VER              0x1UL
+-
+-#define PCH_PIC_INT_ID_LO               0x00
+-#define PCH_PIC_INT_ID_HI               0x04
+-#define PCH_PIC_INT_MASK_LO             0x20
+-#define PCH_PIC_INT_MASK_HI             0x24
+-#define PCH_PIC_HTMSI_EN_LO             0x40
+-#define PCH_PIC_HTMSI_EN_HI             0x44
+-#define PCH_PIC_INT_EDGE_LO             0x60
+-#define PCH_PIC_INT_EDGE_HI             0x64
+-#define PCH_PIC_INT_CLEAR_LO            0x80
+-#define PCH_PIC_INT_CLEAR_HI            0x84
+-#define PCH_PIC_AUTO_CTRL0_LO           0xc0
+-#define PCH_PIC_AUTO_CTRL0_HI           0xc4
+-#define PCH_PIC_AUTO_CTRL1_LO           0xe0
+-#define PCH_PIC_AUTO_CTRL1_HI           0xe4
+-#define PCH_PIC_ROUTE_ENTRY_OFFSET      0x100
+-#define PCH_PIC_ROUTE_ENTRY_END         0x13f
+-#define PCH_PIC_HTMSI_VEC_OFFSET        0x200
+-#define PCH_PIC_HTMSI_VEC_END           0x23f
+-#define PCH_PIC_INT_STATUS_LO           0x3a0
+-#define PCH_PIC_INT_STATUS_HI           0x3a4
+-#define PCH_PIC_INT_POL_LO              0x3e0
+-#define PCH_PIC_INT_POL_HI              0x3e4
+-
+-#define STATUS_LO_START                 0
+-#define STATUS_HI_START                 0x4
+-#define POL_LO_START                    0x40
+-#define POL_HI_START                    0x44
+ struct LoongArchPCHPIC {
+     SysBusDevice parent_obj;
+     qemu_irq parent_irq[64];
+@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
+     MemoryRegion iomem8;
+     unsigned int irq_num;
+ };
++#endif /* HW_LOONGARCH_PCH_PIC_H */
+diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/loongarch_pic_common.h
+@@ -XXX,XX +XXX,XX @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * LoongArch 7A1000 I/O interrupt controller definitions
++ * Copyright (c) 2024 Loongson Technology Corporation Limited
++ */
++
++#ifndef HW_LOONGARCH_PIC_COMMON_H
++#define HW_LOONGARCH_PIC_COMMON_H
++
++#include "hw/pci-host/ls7a.h"
++#include "hw/sysbus.h"
++
++#define PCH_PIC_INT_ID_VAL              0x7000000UL
++#define PCH_PIC_INT_ID_VER              0x1UL
++#define PCH_PIC_INT_ID_LO               0x00
++#define PCH_PIC_INT_ID_HI               0x04
++#define PCH_PIC_INT_MASK_LO             0x20
++#define PCH_PIC_INT_MASK_HI             0x24
++#define PCH_PIC_HTMSI_EN_LO             0x40
++#define PCH_PIC_HTMSI_EN_HI             0x44
++#define PCH_PIC_INT_EDGE_LO             0x60
++#define PCH_PIC_INT_EDGE_HI             0x64
++#define PCH_PIC_INT_CLEAR_LO            0x80
++#define PCH_PIC_INT_CLEAR_HI            0x84
++#define PCH_PIC_AUTO_CTRL0_LO           0xc0
++#define PCH_PIC_AUTO_CTRL0_HI           0xc4
++#define PCH_PIC_AUTO_CTRL1_LO           0xe0
++#define PCH_PIC_AUTO_CTRL1_HI           0xe4
++#define PCH_PIC_ROUTE_ENTRY_OFFSET      0x100
++#define PCH_PIC_ROUTE_ENTRY_END         0x13f
++#define PCH_PIC_HTMSI_VEC_OFFSET        0x200
++#define PCH_PIC_HTMSI_VEC_END           0x23f
++#define PCH_PIC_INT_STATUS_LO           0x3a0
++#define PCH_PIC_INT_STATUS_HI           0x3a4
++#define PCH_PIC_INT_POL_LO              0x3e0
++#define PCH_PIC_INT_POL_HI              0x3e4
++
++#define STATUS_LO_START                 0
++#define STATUS_HI_START                 0x4
++#define POL_LO_START                    0x40
++#define POL_HI_START                    0x44
++#endif  /* HW_LOONGARCH_PIC_COMMON_H */
+--
+.43.5

-New patch
+[PULL 02/18] include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
+Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
+to file loongarch_pic_common.h, and rename structure name with
+LoongArchPICCommonState.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
+---
+ include/hw/intc/loongarch_pch_pic.h    | 27 +------------------------
+ include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
+files changed, 29 insertions(+), 26 deletions(-)
+diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_pch_pic.h
++++ b/include/hw/intc/loongarch_pch_pic.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/intc/loongarch_pic_common.h"
++#define LoongArchPCHPIC LoongArchPICCommonState
+ #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
+ #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
+ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
+-struct LoongArchPCHPIC {
+-    SysBusDevice parent_obj;
+-    qemu_irq parent_irq[64];
+-    uint64_t int_mask; /*0x020 interrupt mask register*/
+-    uint64_t htmsi_en; /*0x040 1=msi*/
+-    uint64_t intedge; /*0x060 edge=1 level  =0*/
+-    uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
+-    uint64_t auto_crtl0; /*0x0c0*/
+-    uint64_t auto_crtl1; /*0x0e0*/
+-    uint64_t last_intirr;    /* edge detection */
+-    uint64_t intirr; /* 0x380 interrupt request register */
+-    uint64_t intisr; /* 0x3a0 interrupt service register */
+-    /*
+-     * 0x3e0 interrupt level polarity selection
+-     * register 0 for high level trigger
+-     */
+-    uint64_t int_polarity;
+-
+-    uint8_t route_entry[64]; /*0x100 - 0x138*/
+-    uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
+-
+-    MemoryRegion iomem32_low;
+-    MemoryRegion iomem32_high;
+-    MemoryRegion iomem8;
+-    unsigned int irq_num;
+-};
+ #endif /* HW_LOONGARCH_PCH_PIC_H */
+diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_pic_common.h
++++ b/include/hw/intc/loongarch_pic_common.h
+@@ -XXX,XX +XXX,XX @@
+ #define STATUS_HI_START                 0x4
+ #define POL_LO_START                    0x40
+ #define POL_HI_START                    0x44
++
++struct LoongArchPICCommonState {
++    SysBusDevice parent_obj;
++
++    qemu_irq parent_irq[64];
++    uint64_t int_mask;        /* 0x020 interrupt mask register */
++    uint64_t htmsi_en;        /* 0x040 1=msi */
++    uint64_t intedge;         /* 0x060 edge=1 level=0 */
++    uint64_t intclr;          /* 0x080 clean edge int, set 1 clean, 0 noused */
++    uint64_t auto_crtl0;      /* 0x0c0 */
++    uint64_t auto_crtl1;      /* 0x0e0 */
++    uint64_t last_intirr;     /* edge detection */
++    uint64_t intirr;          /* 0x380 interrupt request register */
++    uint64_t intisr;          /* 0x3a0 interrupt service register */
++    /*
++     * 0x3e0 interrupt level polarity selection
++     * register 0 for high level trigger
++     */
++    uint64_t int_polarity;
++
++    uint8_t route_entry[64];  /* 0x100 - 0x138 */
++    uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
++
++    MemoryRegion iomem32_low;
++    MemoryRegion iomem32_high;
++    MemoryRegion iomem8;
++    unsigned int irq_num;
++};
+ #endif  /* HW_LOONGARCH_PIC_COMMON_H */
+--
+.43.5

-New patch
+[PULL 03/18] hw/intc/loongarch_pch: Merge instance_init() into realize()
+Memory region is created in instance_init(), merge it into function
+realize(). There is no special class_init() for loongarch_pch object.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
+---
+ hw/intc/loongarch_pch_pic.c | 15 ++++-----------
+file changed, 4 insertions(+), 11 deletions(-)
+diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/loongarch_pch_pic.c
++++ b/hw/intc/loongarch_pch_pic.c
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
+ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
+ {
+     LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
++    SysBusDevice *sbd  = SYS_BUS_DEVICE(dev);
+     if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
+         error_setg(errp, "Invalid 'pic_irq_num'");
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
+     qdev_init_gpio_out(dev, s->parent_irq, s->irq_num);
+     qdev_init_gpio_in(dev, pch_pic_irq_handler, s->irq_num);
+-}
+-
+-static void loongarch_pch_pic_init(Object *obj)
+-{
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(obj);
+-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+-
+-    memory_region_init_io(&s->iomem32_low, obj,
++    memory_region_init_io(&s->iomem32_low, OBJECT(dev),
+                           &loongarch_pch_pic_reg32_low_ops,
+                           s, PCH_PIC_NAME(.reg32_part1), 0x100);
+-    memory_region_init_io(&s->iomem8, obj, &loongarch_pch_pic_reg8_ops,
++    memory_region_init_io(&s->iomem8, OBJECT(dev), &loongarch_pch_pic_reg8_ops,
+                           s, PCH_PIC_NAME(.reg8), 0x2a0);
+-    memory_region_init_io(&s->iomem32_high, obj,
++    memory_region_init_io(&s->iomem32_high, OBJECT(dev),
+                           &loongarch_pch_pic_reg32_high_ops,
+                           s, PCH_PIC_NAME(.reg32_part2), 0xc60);
+     sysbus_init_mmio(sbd, &s->iomem32_low);
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo loongarch_pch_pic_info = {
+     .name          = TYPE_LOONGARCH_PCH_PIC,
+     .parent        = TYPE_SYS_BUS_DEVICE,
+     .instance_size = sizeof(LoongArchPCHPIC),
+-    .instance_init = loongarch_pch_pic_init,
+     .class_init    = loongarch_pch_pic_class_init,
+ };
+--
+.43.5

-[PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi
+[PULL 04/18] hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
-From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
 vmstate_loongarch_pic_common, and with pic property rename
 loongarch_pch_pic_properties with loongarch_pic_common_properties.
-Converting the MemoryRegionOps read/write handlers to
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-with_attrs in LoongArch extioi emulation.
+Reviewed-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
 file changed, 32 insertions(+), 20 deletions(-)
-Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
  hw/intc/trace-events       |  3 +--
 files changed, 18 insertions(+), 16 deletions(-)
 diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/loongarch_extioi.c
+--- a/hw/intc/loongarch_pch_pic.c
-+++ b/hw/intc/loongarch_extioi.c
++++ b/hw/intc/loongarch_pch_pic.c
-@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
-     extioi_update_irq(s, irq, level);
+     s->int_polarity = 0x0;
  }
--static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
++static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
-+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
++{
-+                                unsigned size, MemTxAttrs attrs)
++    LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
 +
 +    if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
 +        error_setg(errp, "Invalid 'pic_irq_num'");
 +        return;
 +    }
 +}
 +
  static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
  {
-     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+     LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
-     unsigned long offset = addr & 0xffff;
+     SysBusDevice *sbd  = SYS_BUS_DEVICE(dev);
--    uint32_t index, cpu, ret = 0;
++    Error *local_err = NULL;
-+    uint32_t index, cpu;
+-    if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
-     switch (offset) {
+-        error_setg(errp, "Invalid 'pic_irq_num'");
-     case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
++    loongarch_pic_common_realize(dev, &local_err);
-         index = (offset - EXTIOI_NODETYPE_START) >> 2;
++    if (local_err) {
--        ret = s->nodetype[index];
++        error_propagate(errp, local_err);
-+        *data = s->nodetype[index];
+         return;
          break;
      case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
          index = (offset - EXTIOI_IPMAP_START) >> 2;
 -        ret = s->ipmap[index];
 +        *data = s->ipmap[index];
          break;
      case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
          index = (offset - EXTIOI_ENABLE_START) >> 2;
 -        ret = s->enable[index];
 +        *data = s->enable[index];
          break;
      case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
          index = (offset - EXTIOI_BOUNCE_START) >> 2;
 -        ret = s->bounce[index];
 +        *data = s->bounce[index];
          break;
      case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
          index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
          cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
 -        ret = s->coreisr[cpu][index];
 +        *data = s->coreisr[cpu][index];
          break;
      case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
          index = (offset - EXTIOI_COREMAP_START) >> 2;
 -        ret = s->coremap[index];
 +        *data = s->coremap[index];
          break;
      default:
          break;
      }
--    trace_loongarch_extioi_readw(addr, ret);
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
--    return ret;
 +    trace_loongarch_extioi_readw(addr, *data);
 +    return MEMTX_OK;
  }
- static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
+-static Property loongarch_pch_pic_properties[] = {
-@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
+-    DEFINE_PROP_UINT32("pch_pic_irq_num",  LoongArchPCHPIC, irq_num, 0),
 +static Property loongarch_pic_common_properties[] = {
 +    DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
 -static const VMStateDescription vmstate_loongarch_pch_pic = {
 -    .name = TYPE_LOONGARCH_PCH_PIC,
 +static const VMStateDescription vmstate_loongarch_pic_common = {
 +    .name = "loongarch_pch_pic",
      .version_id = 1,
      .minimum_version_id = 1,
      .fields = (const VMStateField[]) {
 -        VMSTATE_UINT64(int_mask, LoongArchPCHPIC),
 -        VMSTATE_UINT64(htmsi_en, LoongArchPCHPIC),
 -        VMSTATE_UINT64(intedge, LoongArchPCHPIC),
 -        VMSTATE_UINT64(intclr, LoongArchPCHPIC),
 -        VMSTATE_UINT64(auto_crtl0, LoongArchPCHPIC),
 -        VMSTATE_UINT64(auto_crtl1, LoongArchPCHPIC),
 -        VMSTATE_UINT8_ARRAY(route_entry, LoongArchPCHPIC, 64),
 -        VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPCHPIC, 64),
 -        VMSTATE_UINT64(last_intirr, LoongArchPCHPIC),
 -        VMSTATE_UINT64(intirr, LoongArchPCHPIC),
 -        VMSTATE_UINT64(intisr, LoongArchPCHPIC),
 -        VMSTATE_UINT64(int_polarity, LoongArchPCHPIC),
 +        VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
 +        VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intedge, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intclr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
 +        VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intisr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
          VMSTATE_END_OF_LIST()
      }
+ };
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
+     dc->realize = loongarch_pch_pic_realize;
+     device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
+-    dc->vmsd = &vmstate_loongarch_pch_pic;
+-    device_class_set_props(dc, loongarch_pch_pic_properties);
++    dc->vmsd = &vmstate_loongarch_pic_common;
++    device_class_set_props(dc, loongarch_pic_common_properties);
  }
--static void extioi_writew(void *opaque, hwaddr addr,
+ static const TypeInfo loongarch_pch_pic_info = {
 -                          uint64_t val, unsigned size)
 +static MemTxResult extioi_writew(void *opaque, hwaddr addr,
 +                          uint64_t val, unsigned size,
 +                          MemTxAttrs attrs)
  {
      LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
      int i, cpu, index, old_data, irq;
@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
      default:
          break;
      }
 +    return MEMTX_OK;
  }
  static const MemoryRegionOps extioi_ops = {
 -    .read = extioi_readw,
 -    .write = extioi_writew,
 +    .read_with_attrs = extioi_readw,
 +    .write_with_attrs = extioi_writew,
      .impl.min_access_size = 4,
      .impl.max_access_size = 4,
      .valid.min_access_size = 4,
 diff --git a/hw/intc/trace-events b/hw/intc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/trace-events
 +++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
  # loongarch_extioi.c
  loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
 -loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
 +loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
  loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 -
 --
-.31.1
+.43.5

-[PULL 3/7] hw/loongarch: Load FDT table into dram memory space
+[PULL 05/18] hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
-From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+Move some common functions to file loongarch_pic_common.c, the common
 functions include loongarch_pic_common_realize(), property structure
 loongarch_pic_common_properties and vmstate structure
 vmstate_loongarch_pic_common.
-Load FDT table into dram memory space, and the addr is 2 MiB.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Since lowmem region starts from 0, FDT base address is located
+Reviewed-by: Song Gao <gaosong@loongson.cn>
-at 2 MiB to avoid NULL pointer access.
+---
  hw/intc/loongarch_pch_pic.c    | 37 +-----------------------------
  hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
 files changed, 42 insertions(+), 36 deletions(-)
  create mode 100644 hw/intc/loongarch_pic_common.c
-Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
 Acked-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/loongarch/virt.c         | 18 +++++++++++-------
  include/hw/loongarch/virt.h |  3 ---
 files changed, 11 insertions(+), 10 deletions(-)
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/hw/intc/loongarch_pch_pic.c
-+++ b/hw/loongarch/virt.c
++++ b/hw/intc/loongarch_pch_pic.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
-, FDT_PCI_RANGE_MMIO, 2, base_mmio,
+     s->int_polarity = 0x0;
 , base_mmio, 2, size_mmio);
      g_free(nodename);
 -    qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
  }
- static void fdt_add_irqchip_node(LoongArchMachineState *lams)
+-static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
+-{
-     MemoryRegion *address_space_mem = get_system_memory();
+-    LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
      LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
      int i;
 +    hwaddr fdt_base;
      if (!cpu_model) {
          cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
      lams->machine_done.notify = virt_machine_done;
      qemu_add_machine_init_done_notifier(&lams->machine_done);
      fdt_add_pcie_node(lams);
 -
--    /* load fdt */
+-    if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
--    MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
+-        error_setg(errp, "Invalid 'pic_irq_num'");
--    memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
+-        return;
--    memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
+-    }
--    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
+-}
-+    /*
+-
-+     * Since lowmem region starts from 0, FDT base address is located
++#include "loongarch_pic_common.c"
-+     * at 2 MiB to avoid NULL pointer access.
+ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
-+     *
+ {
-+     * Put the FDT into the memory map as a ROM image: this will ensure
+     LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
-+     * the FDT is copied again upon reset, even if addr points into RAM.
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
-+     */
 +    fdt_base = 2 * MiB;
 +    qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
 +    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
  }
- bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
+-static Property loongarch_pic_common_properties[] = {
-diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
+-    DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
-index XXXXXXX..XXXXXXX 100644
+-    DEFINE_PROP_END_OF_LIST(),
---- a/include/hw/loongarch/virt.h
+-};
-+++ b/include/hw/loongarch/virt.h
+-
 -static const VMStateDescription vmstate_loongarch_pic_common = {
 -    .name = "loongarch_pch_pic",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 -    .fields = (const VMStateField[]) {
 -        VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
 -        VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
 -        VMSTATE_UINT64(intedge, LoongArchPICCommonState),
 -        VMSTATE_UINT64(intclr, LoongArchPICCommonState),
 -        VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
 -        VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
 -        VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
 -        VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
 -        VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
 -        VMSTATE_UINT64(intirr, LoongArchPICCommonState),
 -        VMSTATE_UINT64(intisr, LoongArchPICCommonState),
 -        VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
 -        VMSTATE_END_OF_LIST()
 -    }
 -};
 -
  static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/intc/loongarch_pic_common.c
 @@ -XXX,XX +XXX,XX @@
- #define VIRT_GED_MEM_ADDR       (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
++/* SPDX-License-Identifier: GPL-2.0-or-later */
- #define VIRT_GED_REG_ADDR       (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
++/*
++ * QEMU Loongson 7A1000 I/O interrupt controller.
--#define VIRT_FDT_BASE           0x1c400000
++ * Copyright (C) 2024 Loongson Technology Corporation Limited
--#define VIRT_FDT_SIZE           0x100000
++ */
--
++
- struct LoongArchMachineState {
++static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
-     /*< private >*/
++{
-     MachineState parent_obj;
++    LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
 +
 +    if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
 +        error_setg(errp, "Invalid 'pic_irq_num'");
 +        return;
 +    }
 +}
 +
 +static Property loongarch_pic_common_properties[] = {
 +    DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static const VMStateDescription vmstate_loongarch_pic_common = {
 +    .name = "loongarch_pch_pic",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (const VMStateField[]) {
 +        VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
 +        VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intedge, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intclr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl0, LoongArchPICCommonState),
 +        VMSTATE_UINT64(auto_crtl1, LoongArchPICCommonState),
 +        VMSTATE_UINT8_ARRAY(route_entry, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT8_ARRAY(htmsi_vector, LoongArchPICCommonState, 64),
 +        VMSTATE_UINT64(last_intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intirr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(intisr, LoongArchPICCommonState),
 +        VMSTATE_UINT64(int_polarity, LoongArchPICCommonState),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 --
-.31.1
+.43.5

-New patch
+[PULL 06/18] hw/intc/loongarch_pch: Inherit from loongarch_pic_common
+Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
+it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
+its own realize() function.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
+---
+ hw/intc/loongarch_pch_pic.c            | 38 ++++++++++++--------------
+ hw/intc/loongarch_pic_common.c         | 32 +++++++++++++++++++++-
+ hw/intc/meson.build                    |  2 +-
+ include/hw/intc/loongarch_pch_pic.h    | 21 +++++++++++---
+ include/hw/intc/loongarch_pic_common.h | 10 +++++++
+files changed, 77 insertions(+), 26 deletions(-)
+diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/loongarch_pch_pic.c
++++ b/hw/intc/loongarch_pch_pic.c
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
+     s->int_polarity = 0x0;
+ }
+-#include "loongarch_pic_common.c"
+-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
++static void loongarch_pic_realize(DeviceState *dev, Error **errp)
+ {
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
+-    SysBusDevice *sbd  = SYS_BUS_DEVICE(dev);
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
++    LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+     Error *local_err = NULL;
+-    loongarch_pic_common_realize(dev, &local_err);
++    lpc->parent_realize(dev, &local_err);
+     if (local_err) {
+         error_propagate(errp, local_err);
+         return;
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
+ }
+-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
++static void loongarch_pic_class_init(ObjectClass *klass, void *data)
+ {
+     DeviceClass *dc = DEVICE_CLASS(klass);
++    LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
+-    dc->realize = loongarch_pch_pic_realize;
+     device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
+-    dc->vmsd = &vmstate_loongarch_pic_common;
+-    device_class_set_props(dc, loongarch_pic_common_properties);
++    device_class_set_parent_realize(dc, loongarch_pic_realize,
++                                    &lpc->parent_realize);
+ }
+-static const TypeInfo loongarch_pch_pic_info = {
+-    .name          = TYPE_LOONGARCH_PCH_PIC,
+-    .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(LoongArchPCHPIC),
+-    .class_init    = loongarch_pch_pic_class_init,
++static const TypeInfo loongarch_pic_types[] = {
++   {
++        .name               = TYPE_LOONGARCH_PIC,
++        .parent             = TYPE_LOONGARCH_PIC_COMMON,
++        .instance_size      = sizeof(LoongarchPICState),
++        .class_size         = sizeof(LoongarchPICClass),
++        .class_init         = loongarch_pic_class_init,
++    }
+ };
+-static void loongarch_pch_pic_register_types(void)
+-{
+-    type_register_static(&loongarch_pch_pic_info);
+-}
+-
+-type_init(loongarch_pch_pic_register_types)
++DEFINE_TYPES(loongarch_pic_types)
+diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/loongarch_pic_common.c
++++ b/hw/intc/loongarch_pic_common.c
+@@ -XXX,XX +XXX,XX @@
+  * Copyright (C) 2024 Loongson Technology Corporation Limited
+  */
++#include "qemu/osdep.h"
++#include "qapi/error.h"
++#include "hw/intc/loongarch_pic_common.h"
++#include "hw/qdev-properties.h"
++#include "migration/vmstate.h"
++
+ static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
+ {
+-    LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
+     if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
+         error_setg(errp, "Invalid 'pic_irq_num'");
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
+         VMSTATE_END_OF_LIST()
+     }
+ };
++
++static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
++{
++    DeviceClass *dc = DEVICE_CLASS(klass);
++    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
++
++    device_class_set_parent_realize(dc, loongarch_pic_common_realize,
++                                    &lpcc->parent_realize);
++    device_class_set_props(dc, loongarch_pic_common_properties);
++    dc->vmsd = &vmstate_loongarch_pic_common;
++}
++
++static const TypeInfo loongarch_pic_common_types[] = {
++    {
++        .name               = TYPE_LOONGARCH_PIC_COMMON,
++        .parent             = TYPE_SYS_BUS_DEVICE,
++        .instance_size      = sizeof(LoongArchPICCommonState),
++        .class_size         = sizeof(LoongArchPICCommonClass),
++        .class_init         = loongarch_pic_common_class_init,
++        .abstract           = true,
++    }
++};
++
++DEFINE_TYPES(loongarch_pic_common_types)
+diff --git a/hw/intc/meson.build b/hw/intc/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/meson.build
++++ b/hw/intc/meson.build
+@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
+ specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
+ specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
+ specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
+-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
++specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
+ specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
+ specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
+diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_pch_pic.h
++++ b/include/hw/intc/loongarch_pch_pic.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/intc/loongarch_pic_common.h"
+-#define LoongArchPCHPIC LoongArchPICCommonState
+-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
+-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
+-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
++#define TYPE_LOONGARCH_PIC  "loongarch_pic"
++#define PCH_PIC_NAME(name)  TYPE_LOONGARCH_PIC#name
++OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
++
++struct LoongarchPICState {
++    LoongArchPICCommonState parent_obj;
++};
++
++struct LoongarchPICClass {
++    LoongArchPICCommonClass parent_class;
++
++    DeviceRealize parent_realize;
++};
++
++#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
++typedef struct LoongArchPICCommonState LoongArchPCHPIC;
++#define LOONGARCH_PCH_PIC(obj)   ((struct LoongArchPICCommonState *)(obj))
+ #endif /* HW_LOONGARCH_PCH_PIC_H */
+diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_pic_common.h
++++ b/include/hw/intc/loongarch_pic_common.h
+@@ -XXX,XX +XXX,XX @@
+ #define POL_LO_START                    0x40
+ #define POL_HI_START                    0x44
++#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
++OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
++                    LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
++
+ struct LoongArchPICCommonState {
+     SysBusDevice parent_obj;
+@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
+     MemoryRegion iomem8;
+     unsigned int irq_num;
+ };
++
++struct LoongArchPICCommonClass {
++    SysBusDeviceClass parent_class;
++
++    DeviceRealize parent_realize;
++};
+ #endif  /* HW_LOONGARCH_PIC_COMMON_H */
+--
+.43.5

-[PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine
+[PULL 07/18] hw/intc/loongarch_pch: Add pre_save and post_load interfaces
-From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+Add vmstate pre_save and post_load interfaces, which can be used
 by pic kvm driver in future.
-Add new items into LoongArch FDT, including rtc and uart info.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/intc/loongarch_pic_common.c         | 26 ++++++++++++++++++++++++++
  include/hw/intc/loongarch_pic_common.h |  2 ++
 files changed, 28 insertions(+)
-Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/loongarch/virt.c        | 31 +++++++++++++++++++++++++++++++
  include/hw/pci-host/ls7a.h |  1 +
 files changed, 32 insertions(+)
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/virt.c
+--- a/hw/intc/loongarch_pic_common.c
-+++ b/hw/loongarch/virt.c
++++ b/hw/intc/loongarch_pic_common.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/display/ramfb.h"
+ #include "hw/qdev-properties.h"
- #include "hw/mem/pc-dimm.h"
+ #include "migration/vmstate.h"
-+static void fdt_add_rtc_node(LoongArchMachineState *lams)
++static int loongarch_pic_pre_save(void *opaque)
 +{
-+    char *nodename;
++    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
-+    hwaddr base = VIRT_RTC_REG_BASE;
++    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
 +    hwaddr size = VIRT_RTC_LEN;
 +    MachineState *ms = MACHINE(lams);
 +
-+    nodename = g_strdup_printf("/rtc@%" PRIx64, base);
++    if (lpcc->pre_save) {
-+    qemu_fdt_add_subnode(ms->fdt, nodename);
++        return lpcc->pre_save(s);
-+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
++    }
-+    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
++
-+    g_free(nodename);
++    return 0;
 +}
 +
-+static void fdt_add_uart_node(LoongArchMachineState *lams)
++static int loongarch_pic_post_load(void *opaque, int version_id)
 +{
-+    char *nodename;
++    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
-+    hwaddr base = VIRT_UART_BASE;
++    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
 +    hwaddr size = VIRT_UART_SIZE;
 +    MachineState *ms = MACHINE(lams);
 +
-+    nodename = g_strdup_printf("/serial@%" PRIx64, base);
++    if (lpcc->post_load) {
-+    qemu_fdt_add_subnode(ms->fdt, nodename);
++        return lpcc->post_load(s, version_id);
-+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
++    }
-+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
++
-+    qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
++    return 0;
 +    g_free(nodename);
 +}
 +
- static void create_fdt(LoongArchMachineState *lams)
+ static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
  {
-     MachineState *ms = MACHINE(lams);
+     LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
-@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
-                    qdev_get_gpio_in(pch_pic,
+     .name = "loongarch_pch_pic",
-                                     VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
+     .version_id = 1,
-, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+     .minimum_version_id = 1,
-+    fdt_add_uart_node(lams);
++    .pre_save  = loongarch_pic_pre_save,
++    .post_load = loongarch_pic_post_load,
-     /* Network init */
+     .fields = (const VMStateField[]) {
-     for (i = 0; i < nb_nics; i++) {
+         VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
-@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
+         VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
-     sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
+diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
                           qdev_get_gpio_in(pch_pic,
                           VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
 +    fdt_add_rtc_node(lams);
      pm_mem = g_new(MemoryRegion, 1);
      memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
 diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/pci-host/ls7a.h
+--- a/include/hw/intc/loongarch_pic_common.h
-+++ b/include/hw/pci-host/ls7a.h
++++ b/include/hw/intc/loongarch_pic_common.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
- #define VIRT_PCI_IRQS            48
+     SysBusDeviceClass parent_class;
- #define VIRT_UART_IRQ            (PCH_PIC_IRQ_OFFSET + 2)
- #define VIRT_UART_BASE           0x1fe001e0
+     DeviceRealize parent_realize;
-+#define VIRT_UART_SIZE           0X100
++    int (*pre_save)(LoongArchPICCommonState *s);
- #define VIRT_RTC_IRQ             (PCH_PIC_IRQ_OFFSET + 3)
++    int (*post_load)(LoongArchPICCommonState *s, int version_id);
- #define VIRT_MISC_REG_BASE       (VIRT_PCH_REG_BASE + 0x00080000)
+ };
- #define VIRT_RTC_REG_BASE        (VIRT_MISC_REG_BASE + 0x00050100)
+ #endif  /* HW_LOONGARCH_PIC_COMMON_H */
 --
-.31.1
+.43.5

-[PULL 5/7] hw/loongarch: Add TPM device for LoongArch virt machine
+[PULL 08/18] hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic
-From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
 replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
 separately. Also remove unnecessary header files.
-Add TPM device for LoongArch virt machine, including
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
+Reviewed-by: Song Gao <gaosong@loongson.cn>
-to dynamic_sysbus_devices list.
+---
  hw/intc/loongarch_pch_pic.c         | 24 ++++++++++--------------
  hw/loongarch/virt.c                 |  2 +-
  include/hw/intc/loongarch_pch_pic.h |  4 ----
 files changed, 11 insertions(+), 19 deletions(-)
-Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
  hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++++++--
  hw/loongarch/virt.c       |  4 ++++
 files changed, 52 insertions(+), 2 deletions(-)
 diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/loongarch/acpi-build.c
+--- a/hw/intc/loongarch_pch_pic.c
-+++ b/hw/loongarch/acpi-build.c
++++ b/hw/intc/loongarch_pch_pic.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/acpi/generic_event_device.h"
+ #include "qemu/osdep.h"
- #include "hw/pci-host/gpex.h"
+ #include "qemu/bitops.h"
-+#include "sysemu/tpm.h"
+-#include "hw/sysbus.h"
-+#include "hw/platform-bus.h"
+-#include "hw/loongarch/virt.h"
-+#include "hw/acpi/aml-build.h"
+-#include "hw/pci-host/ls7a.h"
+ #include "hw/irq.h"
- #define ACPI_BUILD_ALIGN_SIZE             0x1000
+ #include "hw/intc/loongarch_pch_pic.h"
- #define ACPI_BUILD_TABLE_SIZE             0x20000
+-#include "hw/qdev-properties.h"
-@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
+-#include "migration/vmstate.h"
-     acpi_dsdt_add_gpex(scope, &cfg);
+ #include "trace.h"
- }
+ #include "qapi/error.h"
-+#ifdef CONFIG_TPM
+-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
-+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
++static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
-+{
++                               int level)
-+    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+ {
-+    hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
+     uint64_t val;
-+    SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
+     int irq;
-+    MemoryRegion *sbdev_mr;
+@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
-+    hwaddr tpm_base;
-+
+ static void pch_pic_irq_handler(void *opaque, int irq, int level)
-+    if (!sbdev) {
+ {
-+        return;
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-+    }
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-+
+     uint64_t mask = 1ULL << irq;
-+    tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
-+    assert(tpm_base != -1);
+     assert(irq < s->irq_num);
-+
+@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
-+    tpm_base += pbus_base;
+ static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
-+
+                                             unsigned size)
-+    sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
+ {
-+
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-+    Aml *dev = aml_device("TPM0");
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-+    aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+     uint64_t val = 0;
-+    aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
+     uint32_t offset = addr & 0xfff;
-+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
-+
+@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
-+    Aml *crs = aml_resource_template();
+ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
-+    aml_append(crs,
+                                          uint64_t value, unsigned size)
-+               aml_memory32_fixed(tpm_base,
+ {
-+                                  (uint32_t)memory_region_size(sbdev_mr),
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-+                                  AML_READ_WRITE));
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-+    aml_append(dev, aml_name_decl("_CRS", crs));
+     uint32_t offset, old_valid, data = (uint32_t)value;
-+    aml_append(scope, dev);
+     uint64_t old, int_mask;
-+}
+     offset = addr & 0xfff;
-+#endif
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
-+
+ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
- /* build DSDT */
+                                         unsigned size)
- static void
+ {
- build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-     build_uart_device_aml(dsdt);
+     uint64_t val = 0;
-     build_pci_device_aml(dsdt, lams);
+     uint32_t offset = addr & 0xfff;
-     build_la_ged_aml(dsdt, machine);
--
+@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
-+#ifdef CONFIG_TPM
+ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
-+    acpi_dsdt_add_tpm(dsdt, lams);
+                                      uint64_t value, unsigned size)
-+#endif
+ {
-     /* System State Package */
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-     scope = aml_scope("\\");
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-     pkg = aml_package(4);
+     uint32_t offset, data = (uint32_t)value;
-@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
+     offset = addr & 0xfff;
-         build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
-                    lams->oem_table_id);
+@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
-     }
+ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
--
+                                         unsigned size)
-+    /* TPM info */
+ {
-+    if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
+-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
-+        acpi_add_table(table_offsets, tables_blob);
++    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
-+        build_tpm2(tables_blob, tables->linker,
+     uint64_t val = 0;
-+                   tables->tcpalog, lams->oem_id,
+     uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
-+                   lams->oem_table_id);
+     int64_t offset_tmp;
-+    }
+@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
-     /* Add tables supplied by user (if any) */
+ static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
-     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
+                                      uint64_t data, unsigned size)
-         unsigned len = acpi_table_len(u);
+ {
 -    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
 +    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
      int32_t offset_tmp;
      uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
  static void loongarch_pch_pic_reset(DeviceState *d)
  {
 -    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
 +    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
      int i;
      s->int_mask = -1;
 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/loongarch/virt.c
 +++ b/hw/loongarch/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
- #include "hw/platform-bus.h"
+     /* Add Extend I/O Interrupt Controller node */
- #include "hw/display/ramfb.h"
+     fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
- #include "hw/mem/pc-dimm.h"
-+#include "sysemu/tpm.h"
+-    pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
++    pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
- static void fdt_add_rtc_node(LoongArchMachineState *lams)
+     num = VIRT_PCH_PIC_IRQ_NUM;
- {
+     qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
-@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
+     d = SYS_BUS_DEVICE(pch_pic);
-     object_class_property_set_description(oc, "acpi",
+diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
-         "Enable ACPI");
+index XXXXXXX..XXXXXXX 100644
-     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+--- a/include/hw/intc/loongarch_pch_pic.h
-+#ifdef CONFIG_TPM
++++ b/include/hw/intc/loongarch_pch_pic.h
-+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
+@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
-+#endif
+     DeviceRealize parent_realize;
- }
+ };
- static const TypeInfo loongarch_machine_types[] = {
+-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
 -typedef struct LoongArchPICCommonState LoongArchPCHPIC;
 -#define LOONGARCH_PCH_PIC(obj)   ((struct LoongArchPICCommonState *)(obj))
 -
  #endif /* HW_LOONGARCH_PCH_PIC_H */
 --
-.31.1
+.43.5

-New patch
+[PULL 09/18] include: Add loongarch_extioi_common header file
+Add common header file include/hw/intc/loongarch_extioi_common.h, and
+move some macro definition from include/hw/intc/loongarch_extioi.h to
+the common header file.
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
+---
+ include/hw/intc/loongarch_extioi.h        | 50 +------------------
+ include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
+files changed, 59 insertions(+), 49 deletions(-)
+ create mode 100644 include/hw/intc/loongarch_extioi_common.h
+diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/loongarch_extioi.h
++++ b/include/hw/intc/loongarch_extioi.h
+@@ -XXX,XX +XXX,XX @@
+  * Copyright (C) 2021 Loongson Technology Corporation Limited
+  */
+-#include "hw/sysbus.h"
+-#include "hw/loongarch/virt.h"
+-
+ #ifndef LOONGARCH_EXTIOI_H
+ #define LOONGARCH_EXTIOI_H
+-#define LS3A_INTC_IP               8
+-#define EXTIOI_IRQS                (256)
+-#define EXTIOI_IRQS_BITMAP_SIZE    (256 / 8)
+-/* irq from EXTIOI is routed to no more than 4 cpus */
+-#define EXTIOI_CPUS                (4)
+-/* map to ipnum per 32 irqs */
+-#define EXTIOI_IRQS_IPMAP_SIZE     (256 / 32)
+-#define EXTIOI_IRQS_COREMAP_SIZE   256
+-#define EXTIOI_IRQS_NODETYPE_COUNT  16
+-#define EXTIOI_IRQS_GROUP_COUNT    8
+-
+-#define APIC_OFFSET                  0x400
+-#define APIC_BASE                    (0x1000ULL + APIC_OFFSET)
+-
+-#define EXTIOI_NODETYPE_START        (0x4a0 - APIC_OFFSET)
+-#define EXTIOI_NODETYPE_END          (0x4c0 - APIC_OFFSET)
+-#define EXTIOI_IPMAP_START           (0x4c0 - APIC_OFFSET)
+-#define EXTIOI_IPMAP_END             (0x4c8 - APIC_OFFSET)
+-#define EXTIOI_ENABLE_START          (0x600 - APIC_OFFSET)
+-#define EXTIOI_ENABLE_END            (0x620 - APIC_OFFSET)
+-#define EXTIOI_BOUNCE_START          (0x680 - APIC_OFFSET)
+-#define EXTIOI_BOUNCE_END            (0x6a0 - APIC_OFFSET)
+-#define EXTIOI_ISR_START             (0x700 - APIC_OFFSET)
+-#define EXTIOI_ISR_END               (0x720 - APIC_OFFSET)
+-#define EXTIOI_COREISR_START         (0x800 - APIC_OFFSET)
+-#define EXTIOI_COREISR_END           (0xB20 - APIC_OFFSET)
+-#define EXTIOI_COREMAP_START         (0xC00 - APIC_OFFSET)
+-#define EXTIOI_COREMAP_END           (0xD00 - APIC_OFFSET)
+-#define EXTIOI_SIZE                  0x800
+-
+-#define EXTIOI_VIRT_BASE             (0x40000000)
+-#define EXTIOI_VIRT_SIZE             (0x1000)
+-#define EXTIOI_VIRT_FEATURES         (0x0)
+-#define  EXTIOI_HAS_VIRT_EXTENSION   (0)
+-#define  EXTIOI_HAS_ENABLE_OPTION    (1)
+-#define  EXTIOI_HAS_INT_ENCODE       (2)
+-#define  EXTIOI_HAS_CPU_ENCODE       (3)
+-#define  EXTIOI_VIRT_HAS_FEATURES    (BIT(EXTIOI_HAS_VIRT_EXTENSION)  \
+-                                      | BIT(EXTIOI_HAS_ENABLE_OPTION) \
+-                                      | BIT(EXTIOI_HAS_CPU_ENCODE))
+-#define EXTIOI_VIRT_CONFIG           (0x4)
+-#define  EXTIOI_ENABLE               (1)
+-#define  EXTIOI_ENABLE_INT_ENCODE    (2)
+-#define  EXTIOI_ENABLE_CPU_ENCODE    (3)
+-#define EXTIOI_VIRT_COREMAP_START    (0x40)
+-#define EXTIOI_VIRT_COREMAP_END      (0x240)
++#include "hw/intc/loongarch_extioi_common.h"
+ typedef struct ExtIOICore {
+     uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
+diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/loongarch_extioi_common.h
+@@ -XXX,XX +XXX,XX @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * LoongArch 3A5000 ext interrupt controller definitions
++ * Copyright (C) 2024 Loongson Technology Corporation Limited
++ */
++
++#ifndef LOONGARCH_EXTIOI_COMMON_H
++#define LOONGARCH_EXTIOI_COMMON_H
++
++#include "hw/sysbus.h"
++#include "hw/loongarch/virt.h"
++
++#define LS3A_INTC_IP                 8
++#define EXTIOI_IRQS                  (256)
++#define EXTIOI_IRQS_BITMAP_SIZE      (256 / 8)
++/* irq from EXTIOI is routed to no more than 4 cpus */
++#define EXTIOI_CPUS                  (4)
++/* map to ipnum per 32 irqs */
++#define EXTIOI_IRQS_IPMAP_SIZE       (256 / 32)
++#define EXTIOI_IRQS_COREMAP_SIZE     256
++#define EXTIOI_IRQS_NODETYPE_COUNT   16
++#define EXTIOI_IRQS_GROUP_COUNT      8
++
++#define APIC_OFFSET                  0x400
++#define APIC_BASE                    (0x1000ULL + APIC_OFFSET)
++#define EXTIOI_NODETYPE_START        (0x4a0 - APIC_OFFSET)
++#define EXTIOI_NODETYPE_END          (0x4c0 - APIC_OFFSET)
++#define EXTIOI_IPMAP_START           (0x4c0 - APIC_OFFSET)
++#define EXTIOI_IPMAP_END             (0x4c8 - APIC_OFFSET)
++#define EXTIOI_ENABLE_START          (0x600 - APIC_OFFSET)
++#define EXTIOI_ENABLE_END            (0x620 - APIC_OFFSET)
++#define EXTIOI_BOUNCE_START          (0x680 - APIC_OFFSET)
++#define EXTIOI_BOUNCE_END            (0x6a0 - APIC_OFFSET)
++#define EXTIOI_ISR_START             (0x700 - APIC_OFFSET)
++#define EXTIOI_ISR_END               (0x720 - APIC_OFFSET)
++#define EXTIOI_COREISR_START         (0x800 - APIC_OFFSET)
++#define EXTIOI_COREISR_END           (0xB20 - APIC_OFFSET)
++#define EXTIOI_COREMAP_START         (0xC00 - APIC_OFFSET)
++#define EXTIOI_COREMAP_END           (0xD00 - APIC_OFFSET)
++#define EXTIOI_SIZE                  0x800
++
++#define EXTIOI_VIRT_BASE             (0x40000000)
++#define EXTIOI_VIRT_SIZE             (0x1000)
++#define EXTIOI_VIRT_FEATURES         (0x0)
++#define  EXTIOI_HAS_VIRT_EXTENSION   (0)
++#define  EXTIOI_HAS_ENABLE_OPTION    (1)
++#define  EXTIOI_HAS_INT_ENCODE       (2)
++#define  EXTIOI_HAS_CPU_ENCODE       (3)
++#define  EXTIOI_VIRT_HAS_FEATURES    (BIT(EXTIOI_HAS_VIRT_EXTENSION)  \
++                                      | BIT(EXTIOI_HAS_ENABLE_OPTION) \
++                                      | BIT(EXTIOI_HAS_CPU_ENCODE))
++#define EXTIOI_VIRT_CONFIG           (0x4)
++#define  EXTIOI_ENABLE               (1)
++#define  EXTIOI_ENABLE_INT_ENCODE    (2)
++#define  EXTIOI_ENABLE_CPU_ENCODE    (3)
++#define EXTIOI_VIRT_COREMAP_START    (0x40)
++#define EXTIOI_VIRT_COREMAP_END      (0x240)
++#endif /* LOONGARCH_EXTIOI_H */
+--
+.43.5

-[PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index
+[PULL 10/18] include: Move struct LoongArchExtIOI to header file loongarch_extioi_common
-When the address is invalid address, We should set exception_index
+Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
-according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
+to file loongarch_extioi_common.h.
 Otherwise, The system enters an infinite loop. e.g:
 run test.c on system mode
 test.c:
     #include<stdio.h>
-    void (*func)(int *);
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
 Reviewed-by: Song Gao <gaosong@loongson.cn>
 ---
  include/hw/intc/loongarch_extioi.h        | 26 ----------------------
  include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
 files changed, 27 insertions(+), 26 deletions(-)
-    int main()
+diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
     {
         int i = 8;
         void *ptr = (void *)0x4000000000000000;
         func = ptr;
         func(&i);
         return 0;
     }
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
 ---
  target/loongarch/cpu.c        | 1 +
  target/loongarch/tlb_helper.c | 5 +++--
 files changed, 4 insertions(+), 2 deletions(-)
 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/cpu.c
+--- a/include/hw/intc/loongarch_extioi.h
-+++ b/target/loongarch/cpu.c
++++ b/include/hw/intc/loongarch_extioi.h
-@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@
-         }
-         QEMU_FALLTHROUGH;
+ #include "hw/intc/loongarch_extioi_common.h"
-     case EXCCODE_PIF:
-+    case EXCCODE_ADEF:
+-typedef struct ExtIOICore {
-         cause = cs->exception_index;
+-    uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
-         update_badinstr = 0;
+-    DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
-         break;
+-    qemu_irq parent_irq[LS3A_INTC_IP];
-diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
+-} ExtIOICore;
 -
  #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
  OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
 -struct LoongArchExtIOI {
 -    SysBusDevice parent_obj;
 -    uint32_t num_cpu;
 -    uint32_t features;
 -    uint32_t status;
 -    /* hardware state */
 -    uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
 -    uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
 -    uint32_t isr[EXTIOI_IRQS / 32];
 -    uint32_t enable[EXTIOI_IRQS / 32];
 -    uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
 -    uint32_t coremap[EXTIOI_IRQS / 4];
 -    uint32_t sw_pending[EXTIOI_IRQS / 32];
 -    uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
 -    uint8_t  sw_coremap[EXTIOI_IRQS];
 -    qemu_irq irq[EXTIOI_IRQS];
 -    ExtIOICore *cpu;
 -    MemoryRegion extioi_system_mem;
 -    MemoryRegion virt_extend;
 -};
  #endif /* LOONGARCH_EXTIOI_H */
 diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/tlb_helper.c
+--- a/include/hw/intc/loongarch_extioi_common.h
-+++ b/target/loongarch/tlb_helper.c
++++ b/include/hw/intc/loongarch_extioi_common.h
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
+@@ -XXX,XX +XXX,XX @@
-     switch (tlb_error) {
+ #define  EXTIOI_ENABLE_CPU_ENCODE    (3)
-     default:
+ #define EXTIOI_VIRT_COREMAP_START    (0x40)
-     case TLBRET_BADADDR:
+ #define EXTIOI_VIRT_COREMAP_END      (0x240)
--        cs->exception_index = EXCCODE_ADEM;
++
-+        cs->exception_index = access_type == MMU_INST_FETCH
++typedef struct ExtIOICore {
-+                              ? EXCCODE_ADEF : EXCCODE_ADEM;
++    uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
-         break;
++    DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
-     case TLBRET_NOMATCH:
++    qemu_irq parent_irq[LS3A_INTC_IP];
-         /* No TLB match for a mapped address */
++} ExtIOICore;
-@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
++
-     CPULoongArchState *env = &cpu->env;
++struct LoongArchExtIOI {
-     hwaddr physical;
++    SysBusDevice parent_obj;
-     int prot;
++    uint32_t num_cpu;
--    int ret = TLBRET_BADADDR;
++    uint32_t features;
-+    int ret;
++    uint32_t status;
++    /* hardware state */
-     /* Data access */
++    uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
-     ret = get_physical_address(env, &physical, &prot, address,
++    uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
 +    uint32_t isr[EXTIOI_IRQS / 32];
 +    uint32_t enable[EXTIOI_IRQS / 32];
 +    uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
 +    uint32_t coremap[EXTIOI_IRQS / 4];
 +    uint32_t sw_pending[EXTIOI_IRQS / 32];
 +    uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
 +    uint8_t  sw_coremap[EXTIOI_IRQS];
 +    qemu_irq irq[EXTIOI_IRQS];
 +    ExtIOICore *cpu;
 +    MemoryRegion extioi_system_mem;
 +    MemoryRegion virt_extend;
 +};
  #endif /* LOONGARCH_EXTIOI_H */
 --
-.31.1
+.43.5

-[PULL 6/7] target/loongarch: Add exception subcode
+[PULL 11/18] include: Rename LoongArchExtIOI with LoongArchExtIOICommonState
-We need subcodes to distinguish the same excode cs->exception_indexs,
+Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
-such as EXCCODE_ADEF/EXCCODE_ADEM.
+since it is defined in file loongarch_extioi_common.h
-Signed-off-by: Song Gao <gaosong@loongson.cn>
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Song Gao <gaosong@loongson.cn>
 Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
 ---
- target/loongarch/cpu.c |  7 +++--
+ include/hw/intc/loongarch_extioi.h        | 1 +
- target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
+ include/hw/intc/loongarch_extioi_common.h | 2 +-
-files changed, 36 insertions(+), 29 deletions(-)
+files changed, 2 insertions(+), 1 deletion(-)
-diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
+diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/cpu.c
+--- a/include/hw/intc/loongarch_extioi.h
-+++ b/target/loongarch/cpu.c
++++ b/include/hw/intc/loongarch_extioi.h
-@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@
-         env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
-                                       PC, (env->pc >> 2));
+ #include "hw/intc/loongarch_extioi_common.h"
-     } else {
--        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
++#define LoongArchExtIOI LoongArchExtIOICommonState
-+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
+ #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
-+                                    EXCODE_MCODE(cause));
+ OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
-+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
+ #endif /* LOONGARCH_EXTIOI_H */
-+                                    EXCODE_SUBCODE(cause));
+diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
          env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
                                     FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
          env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
              env->pc = env->CSR_TLBRENTRY;
          } else {
              env->pc = env->CSR_EENTRY;
 -            env->pc += cause * vec_size;
 +            env->pc += EXCODE_MCODE(cause) * vec_size;
          }
          qemu_log_mask(CPU_LOG_INT,
                        "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/loongarch/cpu.h
+--- a/include/hw/intc/loongarch_extioi_common.h
-+++ b/target/loongarch/cpu.h
++++ b/include/hw/intc/loongarch_extioi_common.h
-@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
+@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
- #define FP_DIV0           8
+     qemu_irq parent_irq[LS3A_INTC_IP];
- #define FP_INVALID        16
+ } ExtIOICore;
--#define  EXCCODE_EXTERNAL_INT   64   /* plus external interrupt number */
+-struct LoongArchExtIOI {
--#define  EXCCODE_INT                 0
++struct LoongArchExtIOICommonState {
--#define  EXCCODE_PIL                 1
+     SysBusDevice parent_obj;
--#define  EXCCODE_PIS                 2
+     uint32_t num_cpu;
--#define  EXCCODE_PIF                 3
+     uint32_t features;
 -#define  EXCCODE_PME                 4
 -#define  EXCCODE_PNR                 5
 -#define  EXCCODE_PNX                 6
 -#define  EXCCODE_PPI                 7
 -#define  EXCCODE_ADEF                8 /* Different exception subcode */
 -#define  EXCCODE_ADEM                8
 -#define  EXCCODE_ALE                 9
 -#define  EXCCODE_BCE                 10
 -#define  EXCCODE_SYS                 11
 -#define  EXCCODE_BRK                 12
 -#define  EXCCODE_INE                 13
 -#define  EXCCODE_IPE                 14
 -#define  EXCCODE_FPD                 15
 -#define  EXCCODE_SXD                 16
 -#define  EXCCODE_ASXD                17
 -#define  EXCCODE_FPE                 18 /* Different exception subcode */
 -#define  EXCCODE_VFPE                18
 -#define  EXCCODE_WPEF                19 /* Different exception subcode */
 -#define  EXCCODE_WPEM                19
 -#define  EXCCODE_BTD                 20
 -#define  EXCCODE_BTE                 21
 -#define  EXCCODE_DBP                 26 /* Reserved subcode used for debug */
 +#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
 +#define EXCODE_MCODE(code)    ( (code) & 0x3f )
 +#define EXCODE_SUBCODE(code)  ( (code) >> 6 )
 +
 +#define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
 +#define  EXCCODE_INT                 EXCODE(0, 0)
 +#define  EXCCODE_PIL                 EXCODE(1, 0)
 +#define  EXCCODE_PIS                 EXCODE(2, 0)
 +#define  EXCCODE_PIF                 EXCODE(3, 0)
 +#define  EXCCODE_PME                 EXCODE(4, 0)
 +#define  EXCCODE_PNR                 EXCODE(5, 0)
 +#define  EXCCODE_PNX                 EXCODE(6, 0)
 +#define  EXCCODE_PPI                 EXCODE(7, 0)
 +#define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
 +#define  EXCCODE_ADEM                EXCODE(8, 1)
 +#define  EXCCODE_ALE                 EXCODE(9, 0)
 +#define  EXCCODE_BCE                 EXCODE(10, 0)
 +#define  EXCCODE_SYS                 EXCODE(11, 0)
 +#define  EXCCODE_BRK                 EXCODE(12, 0)
 +#define  EXCCODE_INE                 EXCODE(13, 0)
 +#define  EXCCODE_IPE                 EXCODE(14, 0)
 +#define  EXCCODE_FPD                 EXCODE(15, 0)
 +#define  EXCCODE_SXD                 EXCODE(16, 0)
 +#define  EXCCODE_ASXD                EXCODE(17, 0)
 +#define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
 +#define  EXCCODE_VFPE                EXCODE(18, 1)
 +#define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
 +#define  EXCCODE_WPEM                EXCODE(19, 1)
 +#define  EXCCODE_BTD                 EXCODE(20, 0)
 +#define  EXCCODE_BTE                 EXCODE(21, 0)
 +#define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
  /* cpucfg[0] bits */
  FIELD(CPUCFG0, PRID, 0, 32)
 --
-.31.1
+.43.5

-[PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing
+[PULL 12/18] hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonState
-From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+With some structure such as vmstate and property, rename LoongArchExtIOI
 with LoongArchExtIOICommonState, these common structure will be moved
 to common file.
-. When cpu read or write extioi COREISR reg, it should access
+Signed-off-by: Bibo Mao <maobibo@loongson.cn>
-the reg belonged to itself, so the cpu index of 's->coreisr'
+Reviewed-by: Song Gao <gaosong@loongson.cn>
 is current cpu number. Using MemTxAttrs' requester_id to get
 the cpu index.
 . it need not to mask 0x1f when calculate the coreisr array index.
 Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
 Signed-off-by: Song Gao <gaosong@loongson.cn>
 ---
- hw/intc/loongarch_extioi.c      | 10 ++++++----
+ hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
- target/loongarch/iocsr_helper.c | 19 +++++++++++--------
+file changed, 25 insertions(+), 16 deletions(-)
 files changed, 17 insertions(+), 12 deletions(-)
 diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/loongarch_extioi.c
 +++ b/hw/intc/loongarch_extioi.c
-@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
+@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
-         *data = s->bounce[index];
+     return 0;
-         break;
+ }
-     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
--        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
++static int loongarch_extioi_common_post_load(void *opaque, int version_id)
--        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
++{
-+        index = (offset - EXTIOI_COREISR_START) >> 2;
++    return vmstate_extioi_post_load(opaque, version_id);
-+        /* using attrs to get current cpu index */
++}
 +        cpu = attrs.requester_id;
          *data = s->coreisr[cpu][index];
          break;
      case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
          s->bounce[index] = val;
          break;
      case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
 -        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
 -        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
 +        index = (offset - EXTIOI_COREISR_START) >> 2;
 +        /* using attrs to get current cpu index */
 +        cpu = attrs.requester_id;
          old_data = s->coreisr[cpu][index];
          s->coreisr[cpu][index] = old_data & ~val;
          /* write 1 to clear interrrupt */
 diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/loongarch/iocsr_helper.c
 +++ b/target/loongarch/iocsr_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "tcg/tcg-ldst.h"
 +#define GET_MEMTXATTRS(cas) \
 +        ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
 +
- uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
+ static const VMStateDescription vmstate_extioi_core = {
- {
+     .name = "extioi-core",
-     return address_space_ldub(&env->address_space_iocsr, r_addr,
+     .version_id = 1,
--                              MEMTXATTRS_UNSPECIFIED, NULL);
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
-+                              GET_MEMTXATTRS(env), NULL);
+ };
- }
+ static const VMStateDescription vmstate_loongarch_extioi = {
- uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
+-    .name = TYPE_LOONGARCH_EXTIOI,
- {
++    .name = "loongarch.extioi",
-     return address_space_lduw(&env->address_space_iocsr, r_addr,
+     .version_id = 3,
--                              MEMTXATTRS_UNSPECIFIED, NULL);
+     .minimum_version_id = 3,
-+                              GET_MEMTXATTRS(env), NULL);
+-    .post_load = vmstate_extioi_post_load,
- }
++    .post_load = loongarch_extioi_common_post_load,
+     .fields = (const VMStateField[]) {
- uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
+-        VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
- {
+-        VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
-     return address_space_ldl(&env->address_space_iocsr, r_addr,
++        VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
--                             MEMTXATTRS_UNSPECIFIED, NULL);
++                             EXTIOI_IRQS_GROUP_COUNT),
-+                             GET_MEMTXATTRS(env), NULL);
++        VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
- }
+                              EXTIOI_IRQS_NODETYPE_COUNT / 2),
+-        VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
- uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
+-        VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
- {
+-        VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
-     return address_space_ldq(&env->address_space_iocsr, r_addr,
+-        VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
--                             MEMTXATTRS_UNSPECIFIED, NULL);
+-
-+                             GET_MEMTXATTRS(env), NULL);
+-        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
- }
+-                         vmstate_extioi_core, ExtIOICore),
+-        VMSTATE_UINT32(features, LoongArchExtIOI),
- void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
+-        VMSTATE_UINT32(status, LoongArchExtIOI),
-                       target_ulong val)
++        VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
- {
++                             EXTIOI_IRQS / 32),
-     address_space_stb(&env->address_space_iocsr, w_addr,
++        VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
--                      val, MEMTXATTRS_UNSPECIFIED, NULL);
++                             EXTIOI_IRQS / 32),
-+                      val, GET_MEMTXATTRS(env), NULL);
++        VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
- }
++                             EXTIOI_IRQS_IPMAP_SIZE / 4),
++        VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
- void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
++                             EXTIOI_IRQS / 4),
-                       target_ulong val)
++        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
- {
++                             num_cpu, vmstate_extioi_core, ExtIOICore),
-     address_space_stw(&env->address_space_iocsr, w_addr,
++        VMSTATE_UINT32(features, LoongArchExtIOICommonState),
--                      val, MEMTXATTRS_UNSPECIFIED, NULL);
++        VMSTATE_UINT32(status, LoongArchExtIOICommonState),
-+                      val, GET_MEMTXATTRS(env), NULL);
+         VMSTATE_END_OF_LIST()
- }
+     }
+ };
- void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
-                       target_ulong val)
+ static Property extioi_properties[] = {
- {
+-    DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
-     address_space_stl(&env->address_space_iocsr, w_addr,
+-    DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
--                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+-                    EXTIOI_HAS_VIRT_EXTENSION, 0),
-+                      val, GET_MEMTXATTRS(env), NULL);
++    DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
- }
++    DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
++                    features, EXTIOI_HAS_VIRT_EXTENSION, 0),
- void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
+     DEFINE_PROP_END_OF_LIST(),
-                       target_ulong val)
+ };
- {
      address_space_stq(&env->address_space_iocsr, w_addr,
 -                      val, MEMTXATTRS_UNSPECIFIED, NULL);
 +                      val, GET_MEMTXATTRS(env), NULL);
  }
 --
-.31.1
+.43.5

The following changes since commit a11f65ec1b8adcb012b89c92819cbda4dc25aaf1:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2022-11-01 13:49:33 -0400)

are available in the Git repository at:

https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221103

for you to fetch changes up to d31e2b1af7e6db41e6088679babc3893bd69b4b3:

target/loongarch: Fix raise_mmu_exception() set wrong exception_index (2022-11-03 17:59:19 +0800)

----------------------------------------------------------------
pull-loongarch-20221103

----------------------------------------------------------------
Song Gao (2):
      target/loongarch: Add exception subcode
      target/loongarch: Fix raise_mmu_exception() set wrong exception_index

Xiaojuan Yang (5):
      hw/intc: Convert the memops to with_attrs in LoongArch extioi
      hw/intc: Fix LoongArch extioi coreisr accessing
      hw/loongarch: Load FDT table into dram memory space
      hw/loongarch: Improve fdt for LoongArch virt machine
      hw/loongarch: Add TPM device for LoongArch virt machine

hw/intc/loongarch_extioi.c      | 41 ++++++++++++++++-------------
 hw/intc/trace-events            |  3 +--
 hw/loongarch/acpi-build.c       | 50 +++++++++++++++++++++++++++++++++--
 hw/loongarch/virt.c             | 53 ++++++++++++++++++++++++++++++++-----
 include/hw/loongarch/virt.h     |  3 ---
 include/hw/pci-host/ls7a.h      |  1 +
 target/loongarch/cpu.c          |  8 ++++--
 target/loongarch/cpu.h          | 58 ++++++++++++++++++++++-------------------
 target/loongarch/iocsr_helper.c | 19 ++++++++------
 target/loongarch/tlb_helper.c   |  5 ++--
 10 files changed, 170 insertions(+), 71 deletions(-)

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Converting the MemoryRegionOps read/write handlers to
with_attrs in LoongArch extioi emulation.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
 hw/intc/trace-events       |  3 +--
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
     extioi_update_irq(s, irq, level);
 }
 
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
+                                unsigned size, MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     unsigned long offset = addr & 0xffff;
-    uint32_t index, cpu, ret = 0;
+    uint32_t index, cpu;
 
     switch (offset) {
     case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
         index = (offset - EXTIOI_NODETYPE_START) >> 2;
-        ret = s->nodetype[index];
+        *data = s->nodetype[index];
         break;
     case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
         index = (offset - EXTIOI_IPMAP_START) >> 2;
-        ret = s->ipmap[index];
+        *data = s->ipmap[index];
         break;
     case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
         index = (offset - EXTIOI_ENABLE_START) >> 2;
-        ret = s->enable[index];
+        *data = s->enable[index];
         break;
     case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
         index = (offset - EXTIOI_BOUNCE_START) >> 2;
-        ret = s->bounce[index];
+        *data = s->bounce[index];
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
         index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
         cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
-        ret = s->coreisr[cpu][index];
+        *data = s->coreisr[cpu][index];
         break;
     case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
         index = (offset - EXTIOI_COREMAP_START) >> 2;
-        ret = s->coremap[index];
+        *data = s->coremap[index];
         break;
     default:
         break;
     }
 
-    trace_loongarch_extioi_readw(addr, ret);
-    return ret;
+    trace_loongarch_extioi_readw(addr, *data);
+    return MEMTX_OK;
 }
 
 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
     }
 }
 
-static void extioi_writew(void *opaque, hwaddr addr,
-                          uint64_t val, unsigned size)
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
+                          uint64_t val, unsigned size,
+                          MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     int i, cpu, index, old_data, irq;
@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
     default:
         break;
     }
+    return MEMTX_OK;
 }
 
 static const MemoryRegionOps extioi_ops = {
-    .read = extioi_readw,
-    .write = extioi_writew,
+    .read_with_attrs = extioi_readw,
+    .write_with_attrs = extioi_writew,
     .impl.min_access_size = 4,
     .impl.max_access_size = 4,
     .valid.min_access_size = 4,
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
 
 # loongarch_extioi.c
 loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
-
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it need not to mask 0x1f when calculate the coreisr array index.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c      | 10 ++++++----
 target/loongarch/iocsr_helper.c | 19 +++++++++++--------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
         *data = s->bounce[index];
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        cpu = attrs.requester_id;
         *data = s->coreisr[cpu][index];
         break;
     case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
         s->bounce[index] = val;
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        cpu = attrs.requester_id;
         old_data = s->coreisr[cpu][index];
         s->coreisr[cpu][index] = old_data & ~val;
         /* write 1 to clear interrrupt */
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/iocsr_helper.c
+++ b/target/loongarch/iocsr_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "tcg/tcg-ldst.h"
 
+#define GET_MEMTXATTRS(cas) \
+        ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
+
 uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldub(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_lduw(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldl(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldq(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stb(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stw(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stl(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
 
 void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stq(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, GET_MEMTXATTRS(env), NULL);
 }
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c         | 18 +++++++++++-------
 include/hw/loongarch/virt.h |  3 ---
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
                                  1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
                                  2, base_mmio, 2, size_mmio);
     g_free(nodename);
-    qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
 }
 
 static void fdt_add_irqchip_node(LoongArchMachineState *lams)
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     MemoryRegion *address_space_mem = get_system_memory();
     LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
     int i;
+    hwaddr fdt_base;
 
     if (!cpu_model) {
         cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
     lams->machine_done.notify = virt_machine_done;
     qemu_add_machine_init_done_notifier(&lams->machine_done);
     fdt_add_pcie_node(lams);
-
-    /* load fdt */
-    MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
-    memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
-    memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
-    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
+    /*
+     * Since lowmem region starts from 0, FDT base address is located
+     * at 2 MiB to avoid NULL pointer access.
+     *
+     * Put the FDT into the memory map as a ROM image: this will ensure
+     * the FDT is copied again upon reset, even if addr points into RAM.
+     */
+    fdt_base = 2 * MiB;
+    qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
+    rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
 }
 
 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/loongarch/virt.h
+++ b/include/hw/loongarch/virt.h
@@ -XXX,XX +XXX,XX @@
 #define VIRT_GED_MEM_ADDR       (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
 #define VIRT_GED_REG_ADDR       (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
 
-#define VIRT_FDT_BASE           0x1c400000
-#define VIRT_FDT_SIZE           0x100000
-
 struct LoongArchMachineState {
     /*< private >*/
     MachineState parent_obj;
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add new items into LoongArch FDT, including rtc and uart info.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/virt.c        | 31 +++++++++++++++++++++++++++++++
 include/hw/pci-host/ls7a.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/display/ramfb.h"
 #include "hw/mem/pc-dimm.h"
 
+static void fdt_add_rtc_node(LoongArchMachineState *lams)
+{
+    char *nodename;
+    hwaddr base = VIRT_RTC_REG_BASE;
+    hwaddr size = VIRT_RTC_LEN;
+    MachineState *ms = MACHINE(lams);
+
+    nodename = g_strdup_printf("/rtc@%" PRIx64, base);
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
+    qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
+    g_free(nodename);
+}
+
+static void fdt_add_uart_node(LoongArchMachineState *lams)
+{
+    char *nodename;
+    hwaddr base = VIRT_UART_BASE;
+    hwaddr size = VIRT_UART_SIZE;
+    MachineState *ms = MACHINE(lams);
+
+    nodename = g_strdup_printf("/serial@%" PRIx64, base);
+    qemu_fdt_add_subnode(ms->fdt, nodename);
+    qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
+    qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
+    qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
+    g_free(nodename);
+}
+
 static void create_fdt(LoongArchMachineState *lams)
 {
     MachineState *ms = MACHINE(lams);
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
                    qdev_get_gpio_in(pch_pic,
                                     VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
                    115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+    fdt_add_uart_node(lams);
 
     /* Network init */
     for (i = 0; i < nb_nics; i++) {
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
     sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
                          qdev_get_gpio_in(pch_pic,
                          VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
+    fdt_add_rtc_node(lams);
 
     pm_mem = g_new(MemoryRegion, 1);
     memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -XXX,XX +XXX,XX @@
 #define VIRT_PCI_IRQS            48
 #define VIRT_UART_IRQ            (PCH_PIC_IRQ_OFFSET + 2)
 #define VIRT_UART_BASE           0x1fe001e0
+#define VIRT_UART_SIZE           0X100
 #define VIRT_RTC_IRQ             (PCH_PIC_IRQ_OFFSET + 3)
 #define VIRT_MISC_REG_BASE       (VIRT_PCH_REG_BASE + 0x00080000)
 #define VIRT_RTC_REG_BASE        (VIRT_MISC_REG_BASE + 0x00050100)
-- 
2.31.1

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>

Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++++++--
 hw/loongarch/virt.c       |  4 ++++
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/acpi/generic_event_device.h"
 #include "hw/pci-host/gpex.h"
+#include "sysemu/tpm.h"
+#include "hw/platform-bus.h"
+#include "hw/acpi/aml-build.h"
 
 #define ACPI_BUILD_ALIGN_SIZE             0x1000
 #define ACPI_BUILD_TABLE_SIZE             0x20000
@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
     acpi_dsdt_add_gpex(scope, &cfg);
 }
 
+#ifdef CONFIG_TPM
+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
+{
+    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
+    hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
+    SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
+    MemoryRegion *sbdev_mr;
+    hwaddr tpm_base;
+
+    if (!sbdev) {
+        return;
+    }
+
+    tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
+    assert(tpm_base != -1);
+
+    tpm_base += pbus_base;
+
+    sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
+
+    Aml *dev = aml_device("TPM0");
+    aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
+    aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+    Aml *crs = aml_resource_template();
+    aml_append(crs,
+               aml_memory32_fixed(tpm_base,
+                                  (uint32_t)memory_region_size(sbdev_mr),
+                                  AML_READ_WRITE));
+    aml_append(dev, aml_name_decl("_CRS", crs));
+    aml_append(scope, dev);
+}
+#endif
+
 /* build DSDT */
 static void
 build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
     build_uart_device_aml(dsdt);
     build_pci_device_aml(dsdt, lams);
     build_la_ged_aml(dsdt, machine);
-
+#ifdef CONFIG_TPM
+    acpi_dsdt_add_tpm(dsdt, lams);
+#endif
     /* System State Package */
     scope = aml_scope("\\");
     pkg = aml_package(4);
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
         build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
                    lams->oem_table_id);
     }
-
+    /* TPM info */
+    if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
+        acpi_add_table(table_offsets, tables_blob);
+        build_tpm2(tables_blob, tables->linker,
+                   tables->tcpalog, lams->oem_id,
+                   lams->oem_table_id);
+    }
     /* Add tables supplied by user (if any) */
     for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
         unsigned len = acpi_table_len(u);
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/platform-bus.h"
 #include "hw/display/ramfb.h"
 #include "hw/mem/pc-dimm.h"
+#include "sysemu/tpm.h"
 
 static void fdt_add_rtc_node(LoongArchMachineState *lams)
 {
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
     object_class_property_set_description(oc, "acpi",
         "Enable ACPI");
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+#ifdef CONFIG_TPM
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
+#endif
 }
 
 static const TypeInfo loongarch_machine_types[] = {
-- 
2.31.1

We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
---
 target/loongarch/cpu.c |  7 +++--
 target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
 2 files changed, 36 insertions(+), 29 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
         env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
                                       PC, (env->pc >> 2));
     } else {
-        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
+                                    EXCODE_MCODE(cause));
+        env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
+                                    EXCODE_SUBCODE(cause));
         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
                                    FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
         env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
             env->pc = env->CSR_TLBRENTRY;
         } else {
             env->pc = env->CSR_EENTRY;
-            env->pc += cause * vec_size;
+            env->pc += EXCODE_MCODE(cause) * vec_size;
         }
         qemu_log_mask(CPU_LOG_INT,
                       "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
 #define FP_DIV0           8
 #define FP_INVALID        16
 
-#define  EXCCODE_EXTERNAL_INT   64   /* plus external interrupt number */
-#define  EXCCODE_INT                 0
-#define  EXCCODE_PIL                 1
-#define  EXCCODE_PIS                 2
-#define  EXCCODE_PIF                 3
-#define  EXCCODE_PME                 4
-#define  EXCCODE_PNR                 5
-#define  EXCCODE_PNX                 6
-#define  EXCCODE_PPI                 7
-#define  EXCCODE_ADEF                8 /* Different exception subcode */
-#define  EXCCODE_ADEM                8
-#define  EXCCODE_ALE                 9
-#define  EXCCODE_BCE                 10
-#define  EXCCODE_SYS                 11
-#define  EXCCODE_BRK                 12
-#define  EXCCODE_INE                 13
-#define  EXCCODE_IPE                 14
-#define  EXCCODE_FPD                 15
-#define  EXCCODE_SXD                 16
-#define  EXCCODE_ASXD                17
-#define  EXCCODE_FPE                 18 /* Different exception subcode */
-#define  EXCCODE_VFPE                18
-#define  EXCCODE_WPEF                19 /* Different exception subcode */
-#define  EXCCODE_WPEM                19
-#define  EXCCODE_BTD                 20
-#define  EXCCODE_BTE                 21
-#define  EXCCODE_DBP                 26 /* Reserved subcode used for debug */
+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
+#define EXCODE_MCODE(code)    ( (code) & 0x3f )
+#define EXCODE_SUBCODE(code)  ( (code) >> 6 )
+
+#define  EXCCODE_EXTERNAL_INT        64   /* plus external interrupt number */
+#define  EXCCODE_INT                 EXCODE(0, 0)
+#define  EXCCODE_PIL                 EXCODE(1, 0)
+#define  EXCCODE_PIS                 EXCODE(2, 0)
+#define  EXCCODE_PIF                 EXCODE(3, 0)
+#define  EXCCODE_PME                 EXCODE(4, 0)
+#define  EXCCODE_PNR                 EXCODE(5, 0)
+#define  EXCCODE_PNX                 EXCODE(6, 0)
+#define  EXCCODE_PPI                 EXCODE(7, 0)
+#define  EXCCODE_ADEF                EXCODE(8, 0) /* Different exception subcode */
+#define  EXCCODE_ADEM                EXCODE(8, 1)
+#define  EXCCODE_ALE                 EXCODE(9, 0)
+#define  EXCCODE_BCE                 EXCODE(10, 0)
+#define  EXCCODE_SYS                 EXCODE(11, 0)
+#define  EXCCODE_BRK                 EXCODE(12, 0)
+#define  EXCCODE_INE                 EXCODE(13, 0)
+#define  EXCCODE_IPE                 EXCODE(14, 0)
+#define  EXCCODE_FPD                 EXCODE(15, 0)
+#define  EXCCODE_SXD                 EXCODE(16, 0)
+#define  EXCCODE_ASXD                EXCODE(17, 0)
+#define  EXCCODE_FPE                 EXCODE(18, 0) /* Different exception subcode */
+#define  EXCCODE_VFPE                EXCODE(18, 1)
+#define  EXCCODE_WPEF                EXCODE(19, 0) /* Different exception subcode */
+#define  EXCCODE_WPEM                EXCODE(19, 1)
+#define  EXCCODE_BTD                 EXCODE(20, 0)
+#define  EXCCODE_BTE                 EXCODE(21, 0)
+#define  EXCCODE_DBP                 EXCODE(26, 0) /* Reserved subcode used for debug */
 
 /* cpucfg[0] bits */
 FIELD(CPUCFG0, PRID, 0, 32)
-- 
2.31.1

When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
    #include<stdio.h>

void (*func)(int *);

int main()
    {
        int i = 8;
        void *ptr = (void *)0x4000000000000000;
        func = ptr;
        func(&i);
        return 0;
    }

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
---
 target/loongarch/cpu.c        | 1 +
 target/loongarch/tlb_helper.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
         }
         QEMU_FALLTHROUGH;
     case EXCCODE_PIF:
+    case EXCCODE_ADEF:
         cause = cs->exception_index;
         update_badinstr = 0;
         break;
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
     switch (tlb_error) {
     default:
     case TLBRET_BADADDR:
-        cs->exception_index = EXCCODE_ADEM;
+        cs->exception_index = access_type == MMU_INST_FETCH
+                              ? EXCCODE_ADEF : EXCCODE_ADEM;
         break;
     case TLBRET_NOMATCH:
         /* No TLB match for a mapped address */
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     CPULoongArchState *env = &cpu->env;
     hwaddr physical;
     int prot;
-    int ret = TLBRET_BADADDR;
+    int ret;
 
     /* Data access */
     ret = get_physical_address(env, &physical, &prot, address,
-- 
2.31.1

The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:

Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into staging (2024-12-11 15:16:47 +0000)

are available in the Git repository at:

https://gitlab.com/bibo-mao/qemu.git pull-loongarch-20241213

for you to fetch changes up to 78aa256571aa06f32001bd80635a1858187c609b:

hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic (2024-12-13 14:39:39 +0800)

----------------------------------------------------------------
pull-loongarch-20241213

----------------------------------------------------------------
Bibo Mao (8):
      include: Add loongarch_pic_common header file
      include: Move struct LoongArchPCHPIC to loongarch_pic_common header file
      hw/intc/loongarch_pch: Merge instance_init() into realize()
      hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonState
      hw/intc/loongarch_pch: Move some functions to file loongarch_pic_common
      hw/intc/loongarch_pch: Inherit from loongarch_pic_common
      hw/intc/loongarch_pch: Add pre_save and post_load interfaces
      hw/intc/loongarch_pch: Code cleanup about loongarch_pch_pic

hw/intc/loongarch_pch_pic.c            | 106 +++++++++++----------------------
 hw/intc/loongarch_pic_common.c         |  97 ++++++++++++++++++++++++++++++
 hw/intc/meson.build                    |   2 +-
 hw/loongarch/virt.c                    |   2 +-
 include/hw/intc/loongarch_pch_pic.h    |  70 +++++-----------------
 include/hw/intc/loongarch_pic_common.h |  82 +++++++++++++++++++++++++
 6 files changed, 230 insertions(+), 129 deletions(-)
 create mode 100644 hw/intc/loongarch_pic_common.c
 create mode 100644 include/hw/intc/loongarch_pic_common.h

Add common header file hw/intc/loongarch_pic_common.h, and move
some macro definition from hw/intc/loongarch_pch_pic.h to the common
header file.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 include/hw/intc/loongarch_pch_pic.h    | 36 +++-------------------
 include/hw/intc/loongarch_pic_common.h | 42 ++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 31 deletions(-)
 create mode 100644 include/hw/intc/loongarch_pic_common.h

diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -XXX,XX +XXX,XX @@
  * Copyright (c) 2021 Loongson Technology Corporation Limited
  */
 
-#include "hw/sysbus.h"
+#ifndef HW_LOONGARCH_PCH_PIC_H
+#define HW_LOONGARCH_PCH_PIC_H
+
+#include "hw/intc/loongarch_pic_common.h"
 
 #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
 #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
 
-#define PCH_PIC_INT_ID_VAL              0x7000000UL
-#define PCH_PIC_INT_ID_VER              0x1UL
-
-#define PCH_PIC_INT_ID_LO               0x00
-#define PCH_PIC_INT_ID_HI               0x04
-#define PCH_PIC_INT_MASK_LO             0x20
-#define PCH_PIC_INT_MASK_HI             0x24
-#define PCH_PIC_HTMSI_EN_LO             0x40
-#define PCH_PIC_HTMSI_EN_HI             0x44
-#define PCH_PIC_INT_EDGE_LO             0x60
-#define PCH_PIC_INT_EDGE_HI             0x64
-#define PCH_PIC_INT_CLEAR_LO            0x80
-#define PCH_PIC_INT_CLEAR_HI            0x84
-#define PCH_PIC_AUTO_CTRL0_LO           0xc0
-#define PCH_PIC_AUTO_CTRL0_HI           0xc4
-#define PCH_PIC_AUTO_CTRL1_LO           0xe0
-#define PCH_PIC_AUTO_CTRL1_HI           0xe4
-#define PCH_PIC_ROUTE_ENTRY_OFFSET      0x100
-#define PCH_PIC_ROUTE_ENTRY_END         0x13f
-#define PCH_PIC_HTMSI_VEC_OFFSET        0x200
-#define PCH_PIC_HTMSI_VEC_END           0x23f
-#define PCH_PIC_INT_STATUS_LO           0x3a0
-#define PCH_PIC_INT_STATUS_HI           0x3a4
-#define PCH_PIC_INT_POL_LO              0x3e0
-#define PCH_PIC_INT_POL_HI              0x3e4
-
-#define STATUS_LO_START                 0
-#define STATUS_HI_START                 0x4
-#define POL_LO_START                    0x40
-#define POL_HI_START                    0x44
 struct LoongArchPCHPIC {
     SysBusDevice parent_obj;
     qemu_irq parent_irq[64];
@@ -XXX,XX +XXX,XX @@ struct LoongArchPCHPIC {
     MemoryRegion iomem8;
     unsigned int irq_num;
 };
+#endif /* HW_LOONGARCH_PCH_PIC_H */
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 7A1000 I/O interrupt controller definitions
+ * Copyright (c) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef HW_LOONGARCH_PIC_COMMON_H
+#define HW_LOONGARCH_PIC_COMMON_H
+
+#include "hw/pci-host/ls7a.h"
+#include "hw/sysbus.h"
+
+#define PCH_PIC_INT_ID_VAL              0x7000000UL
+#define PCH_PIC_INT_ID_VER              0x1UL
+#define PCH_PIC_INT_ID_LO               0x00
+#define PCH_PIC_INT_ID_HI               0x04
+#define PCH_PIC_INT_MASK_LO             0x20
+#define PCH_PIC_INT_MASK_HI             0x24
+#define PCH_PIC_HTMSI_EN_LO             0x40
+#define PCH_PIC_HTMSI_EN_HI             0x44
+#define PCH_PIC_INT_EDGE_LO             0x60
+#define PCH_PIC_INT_EDGE_HI             0x64
+#define PCH_PIC_INT_CLEAR_LO            0x80
+#define PCH_PIC_INT_CLEAR_HI            0x84
+#define PCH_PIC_AUTO_CTRL0_LO           0xc0
+#define PCH_PIC_AUTO_CTRL0_HI           0xc4
+#define PCH_PIC_AUTO_CTRL1_LO           0xe0
+#define PCH_PIC_AUTO_CTRL1_HI           0xe4
+#define PCH_PIC_ROUTE_ENTRY_OFFSET      0x100
+#define PCH_PIC_ROUTE_ENTRY_END         0x13f
+#define PCH_PIC_HTMSI_VEC_OFFSET        0x200
+#define PCH_PIC_HTMSI_VEC_END           0x23f
+#define PCH_PIC_INT_STATUS_LO           0x3a0
+#define PCH_PIC_INT_STATUS_HI           0x3a4
+#define PCH_PIC_INT_POL_LO              0x3e0
+#define PCH_PIC_INT_POL_HI              0x3e4
+
+#define STATUS_LO_START                 0
+#define STATUS_HI_START                 0x4
+#define POL_LO_START                    0x40
+#define POL_HI_START                    0x44
+#endif  /* HW_LOONGARCH_PIC_COMMON_H */
-- 
2.43.5

Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h
to file loongarch_pic_common.h, and rename structure name with
LoongArchPICCommonState.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 include/hw/intc/loongarch_pch_pic.h    | 27 +------------------------
 include/hw/intc/loongarch_pic_common.h | 28 ++++++++++++++++++++++++++
 2 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/intc/loongarch_pic_common.h"
 
+#define LoongArchPCHPIC LoongArchPICCommonState
 #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
 #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
 
-struct LoongArchPCHPIC {
-    SysBusDevice parent_obj;
-    qemu_irq parent_irq[64];
-    uint64_t int_mask; /*0x020 interrupt mask register*/
-    uint64_t htmsi_en; /*0x040 1=msi*/
-    uint64_t intedge; /*0x060 edge=1 level  =0*/
-    uint64_t intclr; /*0x080 for clean edge int,set 1 clean,set 0 is noused*/
-    uint64_t auto_crtl0; /*0x0c0*/
-    uint64_t auto_crtl1; /*0x0e0*/
-    uint64_t last_intirr;    /* edge detection */
-    uint64_t intirr; /* 0x380 interrupt request register */
-    uint64_t intisr; /* 0x3a0 interrupt service register */
-    /*
-     * 0x3e0 interrupt level polarity selection
-     * register 0 for high level trigger
-     */
-    uint64_t int_polarity;
-
-    uint8_t route_entry[64]; /*0x100 - 0x138*/
-    uint8_t htmsi_vector[64]; /*0x200 - 0x238*/
-
-    MemoryRegion iomem32_low;
-    MemoryRegion iomem32_high;
-    MemoryRegion iomem8;
-    unsigned int irq_num;
-};
 #endif /* HW_LOONGARCH_PCH_PIC_H */
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pic_common.h
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -XXX,XX +XXX,XX @@
 #define STATUS_HI_START                 0x4
 #define POL_LO_START                    0x40
 #define POL_HI_START                    0x44
+
+struct LoongArchPICCommonState {
+    SysBusDevice parent_obj;
+
+    qemu_irq parent_irq[64];
+    uint64_t int_mask;        /* 0x020 interrupt mask register */
+    uint64_t htmsi_en;        /* 0x040 1=msi */
+    uint64_t intedge;         /* 0x060 edge=1 level=0 */
+    uint64_t intclr;          /* 0x080 clean edge int, set 1 clean, 0 noused */
+    uint64_t auto_crtl0;      /* 0x0c0 */
+    uint64_t auto_crtl1;      /* 0x0e0 */
+    uint64_t last_intirr;     /* edge detection */
+    uint64_t intirr;          /* 0x380 interrupt request register */
+    uint64_t intisr;          /* 0x3a0 interrupt service register */
+    /*
+     * 0x3e0 interrupt level polarity selection
+     * register 0 for high level trigger
+     */
+    uint64_t int_polarity;
+
+    uint8_t route_entry[64];  /* 0x100 - 0x138 */
+    uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
+
+    MemoryRegion iomem32_low;
+    MemoryRegion iomem32_high;
+    MemoryRegion iomem8;
+    unsigned int irq_num;
+};
 #endif  /* HW_LOONGARCH_PIC_COMMON_H */
-- 
2.43.5

Memory region is created in instance_init(), merge it into function
realize(). There is no special class_init() for loongarch_pch object.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

With pic vmstate, rename structure name vmstate_loongarch_pch_pic with
vmstate_loongarch_pic_common, and with pic property rename
loongarch_pch_pic_properties with loongarch_pic_common_properties.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c | 52 +++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 20 deletions(-)

Move some common functions to file loongarch_pic_common.c, the common
functions include loongarch_pic_common_realize(), property structure
loongarch_pic_common_properties and vmstate structure
vmstate_loongarch_pic_common.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c    | 37 +-----------------------------
 hw/intc/loongarch_pic_common.c | 41 ++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 36 deletions(-)
 create mode 100644 hw/intc/loongarch_pic_common.c

Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object,
it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has
its own realize() function.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c            | 38 ++++++++++++--------------
 hw/intc/loongarch_pic_common.c         | 32 +++++++++++++++++++++-
 hw/intc/meson.build                    |  2 +-
 include/hw/intc/loongarch_pch_pic.h    | 21 +++++++++++---
 include/hw/intc/loongarch_pic_common.h | 10 +++++++
 5 files changed, 77 insertions(+), 26 deletions(-)

diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loongarch_pch_pic.c
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_reset(DeviceState *d)
     s->int_polarity = 0x0;
 }
 
-#include "loongarch_pic_common.c"
-static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
+static void loongarch_pic_realize(DeviceState *dev, Error **errp)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(dev);
-    SysBusDevice *sbd  = SYS_BUS_DEVICE(dev);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
+    LoongarchPICClass *lpc = LOONGARCH_PIC_GET_CLASS(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     Error *local_err = NULL;
 
-    loongarch_pic_common_realize(dev, &local_err);
+    lpc->parent_realize(dev, &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
         return;
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_realize(DeviceState *dev, Error **errp)
 
 }
 
-static void loongarch_pch_pic_class_init(ObjectClass *klass, void *data)
+static void loongarch_pic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    LoongarchPICClass *lpc = LOONGARCH_PIC_CLASS(klass);
 
-    dc->realize = loongarch_pch_pic_realize;
     device_class_set_legacy_reset(dc, loongarch_pch_pic_reset);
-    dc->vmsd = &vmstate_loongarch_pic_common;
-    device_class_set_props(dc, loongarch_pic_common_properties);
+    device_class_set_parent_realize(dc, loongarch_pic_realize,
+                                    &lpc->parent_realize);
 }
 
-static const TypeInfo loongarch_pch_pic_info = {
-    .name          = TYPE_LOONGARCH_PCH_PIC,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(LoongArchPCHPIC),
-    .class_init    = loongarch_pch_pic_class_init,
+static const TypeInfo loongarch_pic_types[] = {
+   {
+        .name               = TYPE_LOONGARCH_PIC,
+        .parent             = TYPE_LOONGARCH_PIC_COMMON,
+        .instance_size      = sizeof(LoongarchPICState),
+        .class_size         = sizeof(LoongarchPICClass),
+        .class_init         = loongarch_pic_class_init,
+    }
 };
 
-static void loongarch_pch_pic_register_types(void)
-{
-    type_register_static(&loongarch_pch_pic_info);
-}
-
-type_init(loongarch_pch_pic_register_types)
+DEFINE_TYPES(loongarch_pic_types)
diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_pic_common.c
+++ b/hw/intc/loongarch_pic_common.c
@@ -XXX,XX +XXX,XX @@
  * Copyright (C) 2024 Loongson Technology Corporation Limited
  */
 
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/intc/loongarch_pic_common.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+
 static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
 {
-    LoongArchPICCommonState *s = LOONGARCH_PCH_PIC(dev);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
 
     if (!s->irq_num || s->irq_num  > VIRT_PCH_PIC_IRQ_NUM) {
         error_setg(errp, "Invalid 'pic_irq_num'");
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
         VMSTATE_END_OF_LIST()
     }
 };
+
+static void loongarch_pic_common_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_CLASS(klass);
+
+    device_class_set_parent_realize(dc, loongarch_pic_common_realize,
+                                    &lpcc->parent_realize);
+    device_class_set_props(dc, loongarch_pic_common_properties);
+    dc->vmsd = &vmstate_loongarch_pic_common;
+}
+
+static const TypeInfo loongarch_pic_common_types[] = {
+    {
+        .name               = TYPE_LOONGARCH_PIC_COMMON,
+        .parent             = TYPE_SYS_BUS_DEVICE,
+        .instance_size      = sizeof(LoongArchPICCommonState),
+        .class_size         = sizeof(LoongArchPICCommonClass),
+        .class_init         = loongarch_pic_common_class_init,
+        .abstract           = true,
+    }
+};
+
+DEFINE_TYPES(loongarch_pic_common_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c'))
 specific_ss.add(when: 'CONFIG_LOONGSON_IPI_COMMON', if_true: files('loongson_ipi_common.c'))
 specific_ss.add(when: 'CONFIG_LOONGSON_IPI', if_true: files('loongson_ipi.c'))
 specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
-specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c', 'loongarch_pic_common.c'))
 specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
 specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/intc/loongarch_pic_common.h"
 
-#define LoongArchPCHPIC LoongArchPICCommonState
-#define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic"
-#define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name
-OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC)
+#define TYPE_LOONGARCH_PIC  "loongarch_pic"
+#define PCH_PIC_NAME(name)  TYPE_LOONGARCH_PIC#name
+OBJECT_DECLARE_TYPE(LoongarchPICState, LoongarchPICClass, LOONGARCH_PIC)
+
+struct LoongarchPICState {
+    LoongArchPICCommonState parent_obj;
+};
+
+struct LoongarchPICClass {
+    LoongArchPICCommonClass parent_class;
+
+    DeviceRealize parent_realize;
+};
+
+#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
+typedef struct LoongArchPICCommonState LoongArchPCHPIC;
+#define LOONGARCH_PCH_PIC(obj)   ((struct LoongArchPICCommonState *)(obj))
 
 #endif /* HW_LOONGARCH_PCH_PIC_H */
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pic_common.h
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -XXX,XX +XXX,XX @@
 #define POL_LO_START                    0x40
 #define POL_HI_START                    0x44
 
+#define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
+OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
+                    LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
+
 struct LoongArchPICCommonState {
     SysBusDevice parent_obj;
 
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonState {
     MemoryRegion iomem8;
     unsigned int irq_num;
 };
+
+struct LoongArchPICCommonClass {
+    SysBusDeviceClass parent_class;
+
+    DeviceRealize parent_realize;
+};
 #endif  /* HW_LOONGARCH_PIC_COMMON_H */
-- 
2.43.5

Add vmstate pre_save and post_load interfaces, which can be used
by pic kvm driver in future.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pic_common.c         | 26 ++++++++++++++++++++++++++
 include/hw/intc/loongarch_pic_common.h |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_pic_common.c
+++ b/hw/intc/loongarch_pic_common.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 
+static int loongarch_pic_pre_save(void *opaque)
+{
+    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
+    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
+
+    if (lpcc->pre_save) {
+        return lpcc->pre_save(s);
+    }
+
+    return 0;
+}
+
+static int loongarch_pic_post_load(void *opaque, int version_id)
+{
+    LoongArchPICCommonState *s = (LoongArchPICCommonState *)opaque;
+    LoongArchPICCommonClass *lpcc = LOONGARCH_PIC_COMMON_GET_CLASS(s);
+
+    if (lpcc->post_load) {
+        return lpcc->post_load(s, version_id);
+    }
+
+    return 0;
+}
+
 static void loongarch_pic_common_realize(DeviceState *dev, Error **errp)
 {
     LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(dev);
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_loongarch_pic_common = {
     .name = "loongarch_pch_pic",
     .version_id = 1,
     .minimum_version_id = 1,
+    .pre_save  = loongarch_pic_pre_save,
+    .post_load = loongarch_pic_post_load,
     .fields = (const VMStateField[]) {
         VMSTATE_UINT64(int_mask, LoongArchPICCommonState),
         VMSTATE_UINT64(htmsi_en, LoongArchPICCommonState),
diff --git a/include/hw/intc/loongarch_pic_common.h b/include/hw/intc/loongarch_pic_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pic_common.h
+++ b/include/hw/intc/loongarch_pic_common.h
@@ -XXX,XX +XXX,XX @@ struct LoongArchPICCommonClass {
     SysBusDeviceClass parent_class;
 
     DeviceRealize parent_realize;
+    int (*pre_save)(LoongArchPICCommonState *s);
+    int (*post_load)(LoongArchPICCommonState *s, int version_id);
 };
 #endif  /* HW_LOONGARCH_PIC_COMMON_H */
-- 
2.43.5

Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and
replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON
separately. Also remove unnecessary header files.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_pch_pic.c         | 24 ++++++++++--------------
 hw/loongarch/virt.c                 |  2 +-
 include/hw/intc/loongarch_pch_pic.h |  4 ----
 3 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loongarch_pch_pic.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/bitops.h"
-#include "hw/sysbus.h"
-#include "hw/loongarch/virt.h"
-#include "hw/pci-host/ls7a.h"
 #include "hw/irq.h"
 #include "hw/intc/loongarch_pch_pic.h"
-#include "hw/qdev-properties.h"
-#include "migration/vmstate.h"
 #include "trace.h"
 #include "qapi/error.h"
 
-static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
+static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask,
+                               int level)
 {
     uint64_t val;
     int irq;
@@ -XXX,XX +XXX,XX @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t mask, int level)
 
 static void pch_pic_irq_handler(void *opaque, int irq, int level)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint64_t mask = 1ULL << irq;
 
     assert(irq < s->irq_num);
@@ -XXX,XX +XXX,XX @@ static void pch_pic_irq_handler(void *opaque, int irq, int level)
 static uint64_t loongarch_pch_pic_low_readw(void *opaque, hwaddr addr,
                                             unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint64_t val = 0;
     uint32_t offset = addr & 0xfff;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t get_writew_val(uint64_t value, uint32_t target, bool hi)
 static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
                                          uint64_t value, unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint32_t offset, old_valid, data = (uint32_t)value;
     uint64_t old, int_mask;
     offset = addr & 0xfff;
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_low_writew(void *opaque, hwaddr addr,
 static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
                                         unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint64_t val = 0;
     uint32_t offset = addr & 0xfff;
 
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_high_readw(void *opaque, hwaddr addr,
 static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
                                      uint64_t value, unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint32_t offset, data = (uint32_t)value;
     offset = addr & 0xfff;
 
@@ -XXX,XX +XXX,XX @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
 static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
                                         unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     uint64_t val = 0;
     uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
     int64_t offset_tmp;
@@ -XXX,XX +XXX,XX @@ static uint64_t loongarch_pch_pic_readb(void *opaque, hwaddr addr,
 static void loongarch_pch_pic_writeb(void *opaque, hwaddr addr,
                                      uint64_t data, unsigned size)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(opaque);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque);
     int32_t offset_tmp;
     uint32_t offset = (addr & 0xfff) + PCH_PIC_ROUTE_ENTRY_OFFSET;
 
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps loongarch_pch_pic_reg8_ops = {
 
 static void loongarch_pch_pic_reset(DeviceState *d)
 {
-    LoongArchPCHPIC *s = LOONGARCH_PCH_PIC(d);
+    LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(d);
     int i;
 
     s->int_mask = -1;
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_irq_init(LoongArchVirtMachineState *lvms)
     /* Add Extend I/O Interrupt Controller node */
     fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle);
 
-    pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
+    pch_pic = qdev_new(TYPE_LOONGARCH_PIC);
     num = VIRT_PCH_PIC_IRQ_NUM;
     qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num);
     d = SYS_BUS_DEVICE(pch_pic);
diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_pch_pic.h
+++ b/include/hw/intc/loongarch_pch_pic.h
@@ -XXX,XX +XXX,XX @@ struct LoongarchPICClass {
     DeviceRealize parent_realize;
 };
 
-#define TYPE_LOONGARCH_PCH_PIC TYPE_LOONGARCH_PIC
-typedef struct LoongArchPICCommonState LoongArchPCHPIC;
-#define LOONGARCH_PCH_PIC(obj)   ((struct LoongArchPICCommonState *)(obj))
-
 #endif /* HW_LOONGARCH_PCH_PIC_H */
-- 
2.43.5

Add common header file include/hw/intc/loongarch_extioi_common.h, and
move some macro definition from include/hw/intc/loongarch_extioi.h to
the common header file.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 include/hw/intc/loongarch_extioi.h        | 50 +------------------
 include/hw/intc/loongarch_extioi_common.h | 58 +++++++++++++++++++++++
 2 files changed, 59 insertions(+), 49 deletions(-)
 create mode 100644 include/hw/intc/loongarch_extioi_common.h

diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi.h
+++ b/include/hw/intc/loongarch_extioi.h
@@ -XXX,XX +XXX,XX @@
  * Copyright (C) 2021 Loongson Technology Corporation Limited
  */
 
-#include "hw/sysbus.h"
-#include "hw/loongarch/virt.h"
-
 #ifndef LOONGARCH_EXTIOI_H
 #define LOONGARCH_EXTIOI_H
 
-#define LS3A_INTC_IP               8
-#define EXTIOI_IRQS                (256)
-#define EXTIOI_IRQS_BITMAP_SIZE    (256 / 8)
-/* irq from EXTIOI is routed to no more than 4 cpus */
-#define EXTIOI_CPUS                (4)
-/* map to ipnum per 32 irqs */
-#define EXTIOI_IRQS_IPMAP_SIZE     (256 / 32)
-#define EXTIOI_IRQS_COREMAP_SIZE   256
-#define EXTIOI_IRQS_NODETYPE_COUNT  16
-#define EXTIOI_IRQS_GROUP_COUNT    8
-
-#define APIC_OFFSET                  0x400
-#define APIC_BASE                    (0x1000ULL + APIC_OFFSET)
-
-#define EXTIOI_NODETYPE_START        (0x4a0 - APIC_OFFSET)
-#define EXTIOI_NODETYPE_END          (0x4c0 - APIC_OFFSET)
-#define EXTIOI_IPMAP_START           (0x4c0 - APIC_OFFSET)
-#define EXTIOI_IPMAP_END             (0x4c8 - APIC_OFFSET)
-#define EXTIOI_ENABLE_START          (0x600 - APIC_OFFSET)
-#define EXTIOI_ENABLE_END            (0x620 - APIC_OFFSET)
-#define EXTIOI_BOUNCE_START          (0x680 - APIC_OFFSET)
-#define EXTIOI_BOUNCE_END            (0x6a0 - APIC_OFFSET)
-#define EXTIOI_ISR_START             (0x700 - APIC_OFFSET)
-#define EXTIOI_ISR_END               (0x720 - APIC_OFFSET)
-#define EXTIOI_COREISR_START         (0x800 - APIC_OFFSET)
-#define EXTIOI_COREISR_END           (0xB20 - APIC_OFFSET)
-#define EXTIOI_COREMAP_START         (0xC00 - APIC_OFFSET)
-#define EXTIOI_COREMAP_END           (0xD00 - APIC_OFFSET)
-#define EXTIOI_SIZE                  0x800
-
-#define EXTIOI_VIRT_BASE             (0x40000000)
-#define EXTIOI_VIRT_SIZE             (0x1000)
-#define EXTIOI_VIRT_FEATURES         (0x0)
-#define  EXTIOI_HAS_VIRT_EXTENSION   (0)
-#define  EXTIOI_HAS_ENABLE_OPTION    (1)
-#define  EXTIOI_HAS_INT_ENCODE       (2)
-#define  EXTIOI_HAS_CPU_ENCODE       (3)
-#define  EXTIOI_VIRT_HAS_FEATURES    (BIT(EXTIOI_HAS_VIRT_EXTENSION)  \
-                                      | BIT(EXTIOI_HAS_ENABLE_OPTION) \
-                                      | BIT(EXTIOI_HAS_CPU_ENCODE))
-#define EXTIOI_VIRT_CONFIG           (0x4)
-#define  EXTIOI_ENABLE               (1)
-#define  EXTIOI_ENABLE_INT_ENCODE    (2)
-#define  EXTIOI_ENABLE_CPU_ENCODE    (3)
-#define EXTIOI_VIRT_COREMAP_START    (0x40)
-#define EXTIOI_VIRT_COREMAP_END      (0x240)
+#include "hw/intc/loongarch_extioi_common.h"
 
 typedef struct ExtIOICore {
     uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/loongarch_extioi_common.h
@@ -XXX,XX +XXX,XX @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 3A5000 ext interrupt controller definitions
+ * Copyright (C) 2024 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_EXTIOI_COMMON_H
+#define LOONGARCH_EXTIOI_COMMON_H
+
+#include "hw/sysbus.h"
+#include "hw/loongarch/virt.h"
+
+#define LS3A_INTC_IP                 8
+#define EXTIOI_IRQS                  (256)
+#define EXTIOI_IRQS_BITMAP_SIZE      (256 / 8)
+/* irq from EXTIOI is routed to no more than 4 cpus */
+#define EXTIOI_CPUS                  (4)
+/* map to ipnum per 32 irqs */
+#define EXTIOI_IRQS_IPMAP_SIZE       (256 / 32)
+#define EXTIOI_IRQS_COREMAP_SIZE     256
+#define EXTIOI_IRQS_NODETYPE_COUNT   16
+#define EXTIOI_IRQS_GROUP_COUNT      8
+
+#define APIC_OFFSET                  0x400
+#define APIC_BASE                    (0x1000ULL + APIC_OFFSET)
+#define EXTIOI_NODETYPE_START        (0x4a0 - APIC_OFFSET)
+#define EXTIOI_NODETYPE_END          (0x4c0 - APIC_OFFSET)
+#define EXTIOI_IPMAP_START           (0x4c0 - APIC_OFFSET)
+#define EXTIOI_IPMAP_END             (0x4c8 - APIC_OFFSET)
+#define EXTIOI_ENABLE_START          (0x600 - APIC_OFFSET)
+#define EXTIOI_ENABLE_END            (0x620 - APIC_OFFSET)
+#define EXTIOI_BOUNCE_START          (0x680 - APIC_OFFSET)
+#define EXTIOI_BOUNCE_END            (0x6a0 - APIC_OFFSET)
+#define EXTIOI_ISR_START             (0x700 - APIC_OFFSET)
+#define EXTIOI_ISR_END               (0x720 - APIC_OFFSET)
+#define EXTIOI_COREISR_START         (0x800 - APIC_OFFSET)
+#define EXTIOI_COREISR_END           (0xB20 - APIC_OFFSET)
+#define EXTIOI_COREMAP_START         (0xC00 - APIC_OFFSET)
+#define EXTIOI_COREMAP_END           (0xD00 - APIC_OFFSET)
+#define EXTIOI_SIZE                  0x800
+
+#define EXTIOI_VIRT_BASE             (0x40000000)
+#define EXTIOI_VIRT_SIZE             (0x1000)
+#define EXTIOI_VIRT_FEATURES         (0x0)
+#define  EXTIOI_HAS_VIRT_EXTENSION   (0)
+#define  EXTIOI_HAS_ENABLE_OPTION    (1)
+#define  EXTIOI_HAS_INT_ENCODE       (2)
+#define  EXTIOI_HAS_CPU_ENCODE       (3)
+#define  EXTIOI_VIRT_HAS_FEATURES    (BIT(EXTIOI_HAS_VIRT_EXTENSION)  \
+                                      | BIT(EXTIOI_HAS_ENABLE_OPTION) \
+                                      | BIT(EXTIOI_HAS_CPU_ENCODE))
+#define EXTIOI_VIRT_CONFIG           (0x4)
+#define  EXTIOI_ENABLE               (1)
+#define  EXTIOI_ENABLE_INT_ENCODE    (2)
+#define  EXTIOI_ENABLE_CPU_ENCODE    (3)
+#define EXTIOI_VIRT_COREMAP_START    (0x40)
+#define EXTIOI_VIRT_COREMAP_END      (0x240)
+#endif /* LOONGARCH_EXTIOI_H */
-- 
2.43.5

Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h
to file loongarch_extioi_common.h.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 include/hw/intc/loongarch_extioi.h        | 26 ----------------------
 include/hw/intc/loongarch_extioi_common.h | 27 +++++++++++++++++++++++
 2 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi.h
+++ b/include/hw/intc/loongarch_extioi.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/intc/loongarch_extioi_common.h"
 
-typedef struct ExtIOICore {
-    uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
-    DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
-    qemu_irq parent_irq[LS3A_INTC_IP];
-} ExtIOICore;
-
 #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
-struct LoongArchExtIOI {
-    SysBusDevice parent_obj;
-    uint32_t num_cpu;
-    uint32_t features;
-    uint32_t status;
-    /* hardware state */
-    uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
-    uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
-    uint32_t isr[EXTIOI_IRQS / 32];
-    uint32_t enable[EXTIOI_IRQS / 32];
-    uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
-    uint32_t coremap[EXTIOI_IRQS / 4];
-    uint32_t sw_pending[EXTIOI_IRQS / 32];
-    uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
-    uint8_t  sw_coremap[EXTIOI_IRQS];
-    qemu_irq irq[EXTIOI_IRQS];
-    ExtIOICore *cpu;
-    MemoryRegion extioi_system_mem;
-    MemoryRegion virt_extend;
-};
 #endif /* LOONGARCH_EXTIOI_H */
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi_common.h
+++ b/include/hw/intc/loongarch_extioi_common.h
@@ -XXX,XX +XXX,XX @@
 #define  EXTIOI_ENABLE_CPU_ENCODE    (3)
 #define EXTIOI_VIRT_COREMAP_START    (0x40)
 #define EXTIOI_VIRT_COREMAP_END      (0x240)
+
+typedef struct ExtIOICore {
+    uint32_t coreisr[EXTIOI_IRQS_GROUP_COUNT];
+    DECLARE_BITMAP(sw_isr[LS3A_INTC_IP], EXTIOI_IRQS);
+    qemu_irq parent_irq[LS3A_INTC_IP];
+} ExtIOICore;
+
+struct LoongArchExtIOI {
+    SysBusDevice parent_obj;
+    uint32_t num_cpu;
+    uint32_t features;
+    uint32_t status;
+    /* hardware state */
+    uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
+    uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
+    uint32_t isr[EXTIOI_IRQS / 32];
+    uint32_t enable[EXTIOI_IRQS / 32];
+    uint32_t ipmap[EXTIOI_IRQS_IPMAP_SIZE / 4];
+    uint32_t coremap[EXTIOI_IRQS / 4];
+    uint32_t sw_pending[EXTIOI_IRQS / 32];
+    uint8_t  sw_ipmap[EXTIOI_IRQS_IPMAP_SIZE];
+    uint8_t  sw_coremap[EXTIOI_IRQS];
+    qemu_irq irq[EXTIOI_IRQS];
+    ExtIOICore *cpu;
+    MemoryRegion extioi_system_mem;
+    MemoryRegion virt_extend;
+};
 #endif /* LOONGARCH_EXTIOI_H */
-- 
2.43.5

Rename structure LoongArchExtIOI with LoongArchExtIOICommonState,
since it is defined in file loongarch_extioi_common.h

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 include/hw/intc/loongarch_extioi.h        | 1 +
 include/hw/intc/loongarch_extioi_common.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/hw/intc/loongarch_extioi.h b/include/hw/intc/loongarch_extioi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi.h
+++ b/include/hw/intc/loongarch_extioi.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/intc/loongarch_extioi_common.h"
 
+#define LoongArchExtIOI LoongArchExtIOICommonState
 #define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
 OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
 #endif /* LOONGARCH_EXTIOI_H */
diff --git a/include/hw/intc/loongarch_extioi_common.h b/include/hw/intc/loongarch_extioi_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/loongarch_extioi_common.h
+++ b/include/hw/intc/loongarch_extioi_common.h
@@ -XXX,XX +XXX,XX @@ typedef struct ExtIOICore {
     qemu_irq parent_irq[LS3A_INTC_IP];
 } ExtIOICore;
 
-struct LoongArchExtIOI {
+struct LoongArchExtIOICommonState {
     SysBusDevice parent_obj;
     uint32_t num_cpu;
     uint32_t features;
-- 
2.43.5

With some structure such as vmstate and property, rename LoongArchExtIOI
with LoongArchExtIOICommonState, these common structure will be moved
to common file.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
---
 hw/intc/loongarch_extioi.c | 41 +++++++++++++++++++++++---------------
 1 file changed, 25 insertions(+), 16 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -XXX,XX +XXX,XX @@ static int vmstate_extioi_post_load(void *opaque, int version_id)
     return 0;
 }
 
+static int loongarch_extioi_common_post_load(void *opaque, int version_id)
+{
+    return vmstate_extioi_post_load(opaque, version_id);
+}
+
 static const VMStateDescription vmstate_extioi_core = {
     .name = "extioi-core",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_extioi_core = {
 };
 
 static const VMStateDescription vmstate_loongarch_extioi = {
-    .name = TYPE_LOONGARCH_EXTIOI,
+    .name = "loongarch.extioi",
     .version_id = 3,
     .minimum_version_id = 3,
-    .post_load = vmstate_extioi_post_load,
+    .post_load = loongarch_extioi_common_post_load,
     .fields = (const VMStateField[]) {
-        VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
-        VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
+        VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
+                             EXTIOI_IRQS_GROUP_COUNT),
+        VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
                              EXTIOI_IRQS_NODETYPE_COUNT / 2),
-        VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
-        VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
-        VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
-        VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
-
-        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOI, num_cpu,
-                         vmstate_extioi_core, ExtIOICore),
-        VMSTATE_UINT32(features, LoongArchExtIOI),
-        VMSTATE_UINT32(status, LoongArchExtIOI),
+        VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
+                             EXTIOI_IRQS / 32),
+        VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
+                             EXTIOI_IRQS / 32),
+        VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
+                             EXTIOI_IRQS_IPMAP_SIZE / 4),
+        VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
+                             EXTIOI_IRQS / 4),
+        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
+                             num_cpu, vmstate_extioi_core, ExtIOICore),
+        VMSTATE_UINT32(features, LoongArchExtIOICommonState),
+        VMSTATE_UINT32(status, LoongArchExtIOICommonState),
         VMSTATE_END_OF_LIST()
     }
 };
 
 static Property extioi_properties[] = {
-    DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOI, num_cpu, 1),
-    DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOI, features,
-                    EXTIOI_HAS_VIRT_EXTENSION, 0),
+    DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1),
+    DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
+                    features, EXTIOI_HAS_VIRT_EXTENSION, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.43.5