[PULL 0/7] loongarch-to-apply queue
[PULL 0/1] loongarch-to-apply queue
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The following changes since commit a11f65ec1b8adcb012b89c92819cbda4dc25aaf1:
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The following changes since commit 848a6caa88b9f082c89c9b41afa975761262981d:
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Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2022-11-01 13:49:33 -0400)
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Merge tag 'migration-20230602-pull-request' of https://gitlab.com/juan.quintela/qemu into staging (2023-06-02 17:33:29 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20221103
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https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230605
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for you to fetch changes up to d31e2b1af7e6db41e6088679babc3893bd69b4b3:
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for you to fetch changes up to 8555ddc671203969b0e6eb651e538d02a9a79b3a:
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target/loongarch: Fix raise_mmu_exception() set wrong exception_index (2022-11-03 17:59:19 +0800)
11
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes (2023-06-05 11:08:55 +0800)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
pull-loongarch-20221103
14
Fixes Coverity CID: 1512452, 1512453
15
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
15
16
16
----------------------------------------------------------------
17
----------------------------------------------------------------
17
Song Gao (2):
18
Jiaxun Yang (1):
18
target/loongarch: Add exception subcode
19
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
19
target/loongarch: Fix raise_mmu_exception() set wrong exception_index
20
20
21
Xiaojuan Yang (5):
21
hw/intc/loongarch_ipi.c | 6 +++---
22
hw/intc: Convert the memops to with_attrs in LoongArch extioi
22
include/hw/intc/loongarch_ipi.h | 4 +++-
23
hw/intc: Fix LoongArch extioi coreisr accessing
23
2 files changed, 6 insertions(+), 4 deletions(-)
24
hw/loongarch: Load FDT table into dram memory space
25
hw/loongarch: Improve fdt for LoongArch virt machine
26
hw/loongarch: Add TPM device for LoongArch virt machine
27
28
hw/intc/loongarch_extioi.c | 41 ++++++++++++++++-------------
29
hw/intc/trace-events | 3 +--
30
hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++--
31
hw/loongarch/virt.c | 53 ++++++++++++++++++++++++++++++++-----
32
include/hw/loongarch/virt.h | 3 ---
33
include/hw/pci-host/ls7a.h | 1 +
34
target/loongarch/cpu.c | 8 ++++--
35
target/loongarch/cpu.h | 58 ++++++++++++++++++++++-------------------
36
target/loongarch/iocsr_helper.c | 19 ++++++++------
37
target/loongarch/tlb_helper.c | 5 ++--
38
10 files changed, 170 insertions(+), 71 deletions(-)
diff view generated by jsdifflib
[PULL 1/7] hw/intc: Convert the memops to with_attrs in LoongArch extioi
[PULL 1/1] hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
1
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
2
2
3
Converting the MemoryRegionOps read/write handlers to
3
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
4
with_attrs in LoongArch extioi emulation.
4
Loongson 3A5000's IPI implementation have 4 mailboxes per
5
core.
5
6
6
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
7
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
percpu device"), the number of IPI mailboxes was reduced to
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
one, which mismatches actual hardware.
9
Message-Id: <20221021015307.2570844-2-yangxiaojuan@loongson.cn>
10
11
It won't affect LoongArch based system as LoongArch boot code
12
only uses the first mailbox, however MIPS based Loongson boot
13
code uses all 4 mailboxes.
14
15
Fixes Coverity CID: 1512452, 1512453
16
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
17
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
18
Reviewed-by: Song Gao <gaosong@loongson.cn>
19
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
20
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
21
---
12
hw/intc/loongarch_extioi.c | 31 +++++++++++++++++--------------
22
hw/intc/loongarch_ipi.c | 6 +++---
13
hw/intc/trace-events | 3 +--
23
include/hw/intc/loongarch_ipi.h | 4 +++-
14
2 files changed, 18 insertions(+), 16 deletions(-)
24
2 files changed, 6 insertions(+), 4 deletions(-)
15
25
16
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
26
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/loongarch_extioi.c
28
--- a/hw/intc/loongarch_ipi.c
19
+++ b/hw/intc/loongarch_extioi.c
29
+++ b/hw/intc/loongarch_ipi.c
20
@@ -XXX,XX +XXX,XX @@ static void extioi_setirq(void *opaque, int irq, int level)
30
@@ -XXX,XX +XXX,XX @@ static void loongarch_ipi_init(Object *obj)
21
extioi_update_irq(s, irq, level);
31
22
}
32
static const VMStateDescription vmstate_ipi_core = {
23
33
.name = "ipi-single",
24
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
34
- .version_id = 1,
25
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
35
- .minimum_version_id = 1,
26
+ unsigned size, MemTxAttrs attrs)
36
+ .version_id = 2,
27
{
37
+ .minimum_version_id = 2,
28
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
38
.fields = (VMStateField[]) {
29
unsigned long offset = addr & 0xffff;
39
VMSTATE_UINT32(status, IPICore),
30
- uint32_t index, cpu, ret = 0;
40
VMSTATE_UINT32(en, IPICore),
31
+ uint32_t index, cpu;
41
VMSTATE_UINT32(set, IPICore),
32
42
VMSTATE_UINT32(clear, IPICore),
33
switch (offset) {
43
- VMSTATE_UINT32_ARRAY(buf, IPICore, 2),
34
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
44
+ VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2),
35
index = (offset - EXTIOI_NODETYPE_START) >> 2;
45
VMSTATE_END_OF_LIST()
36
- ret = s->nodetype[index];
37
+ *data = s->nodetype[index];
38
break;
39
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
40
index = (offset - EXTIOI_IPMAP_START) >> 2;
41
- ret = s->ipmap[index];
42
+ *data = s->ipmap[index];
43
break;
44
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
45
index = (offset - EXTIOI_ENABLE_START) >> 2;
46
- ret = s->enable[index];
47
+ *data = s->enable[index];
48
break;
49
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
50
index = (offset - EXTIOI_BOUNCE_START) >> 2;
51
- ret = s->bounce[index];
52
+ *data = s->bounce[index];
53
break;
54
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
55
index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
56
cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
57
- ret = s->coreisr[cpu][index];
58
+ *data = s->coreisr[cpu][index];
59
break;
60
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
61
index = (offset - EXTIOI_COREMAP_START) >> 2;
62
- ret = s->coremap[index];
63
+ *data = s->coremap[index];
64
break;
65
default:
66
break;
67
}
46
}
68
47
};
69
- trace_loongarch_extioi_readw(addr, ret);
48
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
70
- return ret;
71
+ trace_loongarch_extioi_readw(addr, *data);
72
+ return MEMTX_OK;
73
}
74
75
static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
76
@@ -XXX,XX +XXX,XX @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
77
}
78
}
79
80
-static void extioi_writew(void *opaque, hwaddr addr,
81
- uint64_t val, unsigned size)
82
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
83
+ uint64_t val, unsigned size,
84
+ MemTxAttrs attrs)
85
{
86
LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
87
int i, cpu, index, old_data, irq;
88
@@ -XXX,XX +XXX,XX @@ static void extioi_writew(void *opaque, hwaddr addr,
89
default:
90
break;
91
}
92
+ return MEMTX_OK;
93
}
94
95
static const MemoryRegionOps extioi_ops = {
96
- .read = extioi_readw,
97
- .write = extioi_writew,
98
+ .read_with_attrs = extioi_readw,
99
+ .write_with_attrs = extioi_writew,
100
.impl.min_access_size = 4,
101
.impl.max_access_size = 4,
102
.valid.min_access_size = 4,
103
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
104
index XXXXXXX..XXXXXXX 100644
49
index XXXXXXX..XXXXXXX 100644
105
--- a/hw/intc/trace-events
50
--- a/include/hw/intc/loongarch_ipi.h
106
+++ b/hw/intc/trace-events
51
+++ b/include/hw/intc/loongarch_ipi.h
107
@@ -XXX,XX +XXX,XX @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
52
@@ -XXX,XX +XXX,XX @@
108
53
#define MAIL_SEND_OFFSET 0
109
# loongarch_extioi.c
54
#define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
110
loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
55
111
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
56
+#define IPI_MBX_NUM 4
112
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
57
+
113
loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
58
#define TYPE_LOONGARCH_IPI "loongarch_ipi"
114
-
59
OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
60
61
@@ -XXX,XX +XXX,XX @@ typedef struct IPICore {
62
uint32_t set;
63
uint32_t clear;
64
/* 64bit buf divide into 2 32bit buf */
65
- uint32_t buf[2];
66
+ uint32_t buf[IPI_MBX_NUM * 2];
67
qemu_irq irq;
68
} IPICore;
69
115
--
70
--
116
2.31.1
71
2.39.1
117
118
diff view generated by jsdifflib
[PULL 2/7] hw/intc: Fix LoongArch extioi coreisr accessing
Deleted patch
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
1
3
1. When cpu read or write extioi COREISR reg, it should access
4
the reg belonged to itself, so the cpu index of 's->coreisr'
5
is current cpu number. Using MemTxAttrs' requester_id to get
6
the cpu index.
7
2. it need not to mask 0x1f when calculate the coreisr array index.
8
9
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20221021015307.2570844-3-yangxiaojuan@loongson.cn>
12
Signed-off-by: Song Gao <gaosong@loongson.cn>
13
---
14
hw/intc/loongarch_extioi.c | 10 ++++++----
15
target/loongarch/iocsr_helper.c | 19 +++++++++++--------
16
2 files changed, 17 insertions(+), 12 deletions(-)
17
18
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/loongarch_extioi.c
21
+++ b/hw/intc/loongarch_extioi.c
22
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
23
*data = s->bounce[index];
24
break;
25
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
26
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
27
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
28
+ index = (offset - EXTIOI_COREISR_START) >> 2;
29
+ /* using attrs to get current cpu index */
30
+ cpu = attrs.requester_id;
31
*data = s->coreisr[cpu][index];
32
break;
33
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
34
@@ -XXX,XX +XXX,XX @@ static MemTxResult extioi_writew(void *opaque, hwaddr addr,
35
s->bounce[index] = val;
36
break;
37
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
38
- index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
39
- cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
40
+ index = (offset - EXTIOI_COREISR_START) >> 2;
41
+ /* using attrs to get current cpu index */
42
+ cpu = attrs.requester_id;
43
old_data = s->coreisr[cpu][index];
44
s->coreisr[cpu][index] = old_data & ~val;
45
/* write 1 to clear interrrupt */
46
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/loongarch/iocsr_helper.c
49
+++ b/target/loongarch/iocsr_helper.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "exec/cpu_ldst.h"
52
#include "tcg/tcg-ldst.h"
53
54
+#define GET_MEMTXATTRS(cas) \
55
+ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
56
+
57
uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
58
{
59
return address_space_ldub(&env->address_space_iocsr, r_addr,
60
- MEMTXATTRS_UNSPECIFIED, NULL);
61
+ GET_MEMTXATTRS(env), NULL);
62
}
63
64
uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
65
{
66
return address_space_lduw(&env->address_space_iocsr, r_addr,
67
- MEMTXATTRS_UNSPECIFIED, NULL);
68
+ GET_MEMTXATTRS(env), NULL);
69
}
70
71
uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
72
{
73
return address_space_ldl(&env->address_space_iocsr, r_addr,
74
- MEMTXATTRS_UNSPECIFIED, NULL);
75
+ GET_MEMTXATTRS(env), NULL);
76
}
77
78
uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
79
{
80
return address_space_ldq(&env->address_space_iocsr, r_addr,
81
- MEMTXATTRS_UNSPECIFIED, NULL);
82
+ GET_MEMTXATTRS(env), NULL);
83
}
84
85
void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
86
target_ulong val)
87
{
88
address_space_stb(&env->address_space_iocsr, w_addr,
89
- val, MEMTXATTRS_UNSPECIFIED, NULL);
90
+ val, GET_MEMTXATTRS(env), NULL);
91
}
92
93
void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
94
target_ulong val)
95
{
96
address_space_stw(&env->address_space_iocsr, w_addr,
97
- val, MEMTXATTRS_UNSPECIFIED, NULL);
98
+ val, GET_MEMTXATTRS(env), NULL);
99
}
100
101
void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
102
target_ulong val)
103
{
104
address_space_stl(&env->address_space_iocsr, w_addr,
105
- val, MEMTXATTRS_UNSPECIFIED, NULL);
106
+ val, GET_MEMTXATTRS(env), NULL);
107
}
108
109
void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
110
target_ulong val)
111
{
112
address_space_stq(&env->address_space_iocsr, w_addr,
113
- val, MEMTXATTRS_UNSPECIFIED, NULL);
114
+ val, GET_MEMTXATTRS(env), NULL);
115
}
116
--
117
2.31.1
diff view generated by jsdifflib
[PULL 3/7] hw/loongarch: Load FDT table into dram memory space
Deleted patch
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
1
3
Load FDT table into dram memory space, and the addr is 2 MiB.
4
Since lowmem region starts from 0, FDT base address is located
5
at 2 MiB to avoid NULL pointer access.
6
7
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Acked-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20221028014007.2718352-2-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
12
hw/loongarch/virt.c | 18 +++++++++++-------
13
include/hw/loongarch/virt.h | 3 ---
14
2 files changed, 11 insertions(+), 10 deletions(-)
15
16
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/loongarch/virt.c
19
+++ b/hw/loongarch/virt.c
20
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
21
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
22
2, base_mmio, 2, size_mmio);
23
g_free(nodename);
24
- qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
25
}
26
27
static void fdt_add_irqchip_node(LoongArchMachineState *lams)
28
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
29
MemoryRegion *address_space_mem = get_system_memory();
30
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
31
int i;
32
+ hwaddr fdt_base;
33
34
if (!cpu_model) {
35
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
36
@@ -XXX,XX +XXX,XX @@ static void loongarch_init(MachineState *machine)
37
lams->machine_done.notify = virt_machine_done;
38
qemu_add_machine_init_done_notifier(&lams->machine_done);
39
fdt_add_pcie_node(lams);
40
-
41
- /* load fdt */
42
- MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
43
- memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
44
- memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
45
- rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
46
+ /*
47
+ * Since lowmem region starts from 0, FDT base address is located
48
+ * at 2 MiB to avoid NULL pointer access.
49
+ *
50
+ * Put the FDT into the memory map as a ROM image: this will ensure
51
+ * the FDT is copied again upon reset, even if addr points into RAM.
52
+ */
53
+ fdt_base = 2 * MiB;
54
+ qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size);
55
+ rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base);
56
}
57
58
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
59
diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h
60
index XXXXXXX..XXXXXXX 100644
61
--- a/include/hw/loongarch/virt.h
62
+++ b/include/hw/loongarch/virt.h
63
@@ -XXX,XX +XXX,XX @@
64
#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
65
#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
66
67
-#define VIRT_FDT_BASE 0x1c400000
68
-#define VIRT_FDT_SIZE 0x100000
69
-
70
struct LoongArchMachineState {
71
/*< private >*/
72
MachineState parent_obj;
73
--
74
2.31.1
diff view generated by jsdifflib
[PULL 4/7] hw/loongarch: Improve fdt for LoongArch virt machine
Deleted patch
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
1
3
Add new items into LoongArch FDT, including rtc and uart info.
4
5
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
6
Reviewed-by: Song Gao <gaosong@loongson.cn>
7
Message-Id: <20221028014007.2718352-3-yangxiaojuan@loongson.cn>
8
Signed-off-by: Song Gao <gaosong@loongson.cn>
9
---
10
hw/loongarch/virt.c | 31 +++++++++++++++++++++++++++++++
11
include/hw/pci-host/ls7a.h | 1 +
12
2 files changed, 32 insertions(+)
13
14
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/loongarch/virt.c
17
+++ b/hw/loongarch/virt.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/display/ramfb.h"
20
#include "hw/mem/pc-dimm.h"
21
22
+static void fdt_add_rtc_node(LoongArchMachineState *lams)
23
+{
24
+ char *nodename;
25
+ hwaddr base = VIRT_RTC_REG_BASE;
26
+ hwaddr size = VIRT_RTC_LEN;
27
+ MachineState *ms = MACHINE(lams);
28
+
29
+ nodename = g_strdup_printf("/rtc@%" PRIx64, base);
30
+ qemu_fdt_add_subnode(ms->fdt, nodename);
31
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc");
32
+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 0x0, base, size);
33
+ g_free(nodename);
34
+}
35
+
36
+static void fdt_add_uart_node(LoongArchMachineState *lams)
37
+{
38
+ char *nodename;
39
+ hwaddr base = VIRT_UART_BASE;
40
+ hwaddr size = VIRT_UART_SIZE;
41
+ MachineState *ms = MACHINE(lams);
42
+
43
+ nodename = g_strdup_printf("/serial@%" PRIx64, base);
44
+ qemu_fdt_add_subnode(ms->fdt, nodename);
45
+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
46
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
47
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
48
+ g_free(nodename);
49
+}
50
+
51
static void create_fdt(LoongArchMachineState *lams)
52
{
53
MachineState *ms = MACHINE(lams);
54
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
55
qdev_get_gpio_in(pch_pic,
56
VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
57
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
58
+ fdt_add_uart_node(lams);
59
60
/* Network init */
61
for (i = 0; i < nb_nics; i++) {
62
@@ -XXX,XX +XXX,XX @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
63
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
64
qdev_get_gpio_in(pch_pic,
65
VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
66
+ fdt_add_rtc_node(lams);
67
68
pm_mem = g_new(MemoryRegion, 1);
69
memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
70
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/include/hw/pci-host/ls7a.h
73
+++ b/include/hw/pci-host/ls7a.h
74
@@ -XXX,XX +XXX,XX @@
75
#define VIRT_PCI_IRQS 48
76
#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
77
#define VIRT_UART_BASE 0x1fe001e0
78
+#define VIRT_UART_SIZE 0X100
79
#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
80
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
81
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
82
--
83
2.31.1
diff view generated by jsdifflib
[PULL 5/7] hw/loongarch: Add TPM device for LoongArch virt machine
Deleted patch
1
From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
2
1
3
Add TPM device for LoongArch virt machine, including
4
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
5
to dynamic_sysbus_devices list.
6
7
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
8
Reviewed-by: Song Gao <gaosong@loongson.cn>
9
Message-Id: <20221028014007.2718352-4-yangxiaojuan@loongson.cn>
10
Signed-off-by: Song Gao <gaosong@loongson.cn>
11
---
12
hw/loongarch/acpi-build.c | 50 +++++++++++++++++++++++++++++++++++++--
13
hw/loongarch/virt.c | 4 ++++
14
2 files changed, 52 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/loongarch/acpi-build.c
19
+++ b/hw/loongarch/acpi-build.c
20
@@ -XXX,XX +XXX,XX @@
21
22
#include "hw/acpi/generic_event_device.h"
23
#include "hw/pci-host/gpex.h"
24
+#include "sysemu/tpm.h"
25
+#include "hw/platform-bus.h"
26
+#include "hw/acpi/aml-build.h"
27
28
#define ACPI_BUILD_ALIGN_SIZE 0x1000
29
#define ACPI_BUILD_TABLE_SIZE 0x20000
30
@@ -XXX,XX +XXX,XX @@ static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams)
31
acpi_dsdt_add_gpex(scope, &cfg);
32
}
33
34
+#ifdef CONFIG_TPM
35
+static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms)
36
+{
37
+ PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
38
+ hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS;
39
+ SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
40
+ MemoryRegion *sbdev_mr;
41
+ hwaddr tpm_base;
42
+
43
+ if (!sbdev) {
44
+ return;
45
+ }
46
+
47
+ tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
48
+ assert(tpm_base != -1);
49
+
50
+ tpm_base += pbus_base;
51
+
52
+ sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
53
+
54
+ Aml *dev = aml_device("TPM0");
55
+ aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
56
+ aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
57
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
58
+
59
+ Aml *crs = aml_resource_template();
60
+ aml_append(crs,
61
+ aml_memory32_fixed(tpm_base,
62
+ (uint32_t)memory_region_size(sbdev_mr),
63
+ AML_READ_WRITE));
64
+ aml_append(dev, aml_name_decl("_CRS", crs));
65
+ aml_append(scope, dev);
66
+}
67
+#endif
68
+
69
/* build DSDT */
70
static void
71
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
72
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
73
build_uart_device_aml(dsdt);
74
build_pci_device_aml(dsdt, lams);
75
build_la_ged_aml(dsdt, machine);
76
-
77
+#ifdef CONFIG_TPM
78
+ acpi_dsdt_add_tpm(dsdt, lams);
79
+#endif
80
/* System State Package */
81
scope = aml_scope("\\");
82
pkg = aml_package(4);
83
@@ -XXX,XX +XXX,XX @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
84
build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
85
lams->oem_table_id);
86
}
87
-
88
+ /* TPM info */
89
+ if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
90
+ acpi_add_table(table_offsets, tables_blob);
91
+ build_tpm2(tables_blob, tables->linker,
92
+ tables->tcpalog, lams->oem_id,
93
+ lams->oem_table_id);
94
+ }
95
/* Add tables supplied by user (if any) */
96
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
97
unsigned len = acpi_table_len(u);
98
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/hw/loongarch/virt.c
101
+++ b/hw/loongarch/virt.c
102
@@ -XXX,XX +XXX,XX @@
103
#include "hw/platform-bus.h"
104
#include "hw/display/ramfb.h"
105
#include "hw/mem/pc-dimm.h"
106
+#include "sysemu/tpm.h"
107
108
static void fdt_add_rtc_node(LoongArchMachineState *lams)
109
{
110
@@ -XXX,XX +XXX,XX @@ static void loongarch_class_init(ObjectClass *oc, void *data)
111
object_class_property_set_description(oc, "acpi",
112
"Enable ACPI");
113
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
114
+#ifdef CONFIG_TPM
115
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
116
+#endif
117
}
118
119
static const TypeInfo loongarch_machine_types[] = {
120
--
121
2.31.1
diff view generated by jsdifflib
[PULL 6/7] target/loongarch: Add exception subcode
Deleted patch
1
We need subcodes to distinguish the same excode cs->exception_indexs,
2
such as EXCCODE_ADEF/EXCCODE_ADEM.
3
1
4
Signed-off-by: Song Gao <gaosong@loongson.cn>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-ID: <20221101073210.3934280-1-gaosong@loongson.cn>
7
---
8
target/loongarch/cpu.c | 7 +++--
9
target/loongarch/cpu.h | 58 ++++++++++++++++++++++--------------------
10
2 files changed, 36 insertions(+), 29 deletions(-)
11
12
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/loongarch/cpu.c
15
+++ b/target/loongarch/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
17
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
18
PC, (env->pc >> 2));
19
} else {
20
- env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE, cause);
21
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
22
+ EXCODE_MCODE(cause));
23
+ env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
24
+ EXCODE_SUBCODE(cause));
25
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
26
FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
27
env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
28
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
29
env->pc = env->CSR_TLBRENTRY;
30
} else {
31
env->pc = env->CSR_EENTRY;
32
- env->pc += cause * vec_size;
33
+ env->pc += EXCODE_MCODE(cause) * vec_size;
34
}
35
qemu_log_mask(CPU_LOG_INT,
36
"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
37
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/loongarch/cpu.h
40
+++ b/target/loongarch/cpu.h
41
@@ -XXX,XX +XXX,XX @@ FIELD(FCSR0, CAUSE, 24, 5)
42
#define FP_DIV0 8
43
#define FP_INVALID 16
44
45
-#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
46
-#define EXCCODE_INT 0
47
-#define EXCCODE_PIL 1
48
-#define EXCCODE_PIS 2
49
-#define EXCCODE_PIF 3
50
-#define EXCCODE_PME 4
51
-#define EXCCODE_PNR 5
52
-#define EXCCODE_PNX 6
53
-#define EXCCODE_PPI 7
54
-#define EXCCODE_ADEF 8 /* Different exception subcode */
55
-#define EXCCODE_ADEM 8
56
-#define EXCCODE_ALE 9
57
-#define EXCCODE_BCE 10
58
-#define EXCCODE_SYS 11
59
-#define EXCCODE_BRK 12
60
-#define EXCCODE_INE 13
61
-#define EXCCODE_IPE 14
62
-#define EXCCODE_FPD 15
63
-#define EXCCODE_SXD 16
64
-#define EXCCODE_ASXD 17
65
-#define EXCCODE_FPE 18 /* Different exception subcode */
66
-#define EXCCODE_VFPE 18
67
-#define EXCCODE_WPEF 19 /* Different exception subcode */
68
-#define EXCCODE_WPEM 19
69
-#define EXCCODE_BTD 20
70
-#define EXCCODE_BTE 21
71
-#define EXCCODE_DBP 26 /* Reserved subcode used for debug */
72
+#define EXCODE(code, subcode) ( ((subcode) << 6) | (code) )
73
+#define EXCODE_MCODE(code) ( (code) & 0x3f )
74
+#define EXCODE_SUBCODE(code) ( (code) >> 6 )
75
+
76
+#define EXCCODE_EXTERNAL_INT 64 /* plus external interrupt number */
77
+#define EXCCODE_INT EXCODE(0, 0)
78
+#define EXCCODE_PIL EXCODE(1, 0)
79
+#define EXCCODE_PIS EXCODE(2, 0)
80
+#define EXCCODE_PIF EXCODE(3, 0)
81
+#define EXCCODE_PME EXCODE(4, 0)
82
+#define EXCCODE_PNR EXCODE(5, 0)
83
+#define EXCCODE_PNX EXCODE(6, 0)
84
+#define EXCCODE_PPI EXCODE(7, 0)
85
+#define EXCCODE_ADEF EXCODE(8, 0) /* Different exception subcode */
86
+#define EXCCODE_ADEM EXCODE(8, 1)
87
+#define EXCCODE_ALE EXCODE(9, 0)
88
+#define EXCCODE_BCE EXCODE(10, 0)
89
+#define EXCCODE_SYS EXCODE(11, 0)
90
+#define EXCCODE_BRK EXCODE(12, 0)
91
+#define EXCCODE_INE EXCODE(13, 0)
92
+#define EXCCODE_IPE EXCODE(14, 0)
93
+#define EXCCODE_FPD EXCODE(15, 0)
94
+#define EXCCODE_SXD EXCODE(16, 0)
95
+#define EXCCODE_ASXD EXCODE(17, 0)
96
+#define EXCCODE_FPE EXCODE(18, 0) /* Different exception subcode */
97
+#define EXCCODE_VFPE EXCODE(18, 1)
98
+#define EXCCODE_WPEF EXCODE(19, 0) /* Different exception subcode */
99
+#define EXCCODE_WPEM EXCODE(19, 1)
100
+#define EXCCODE_BTD EXCODE(20, 0)
101
+#define EXCCODE_BTE EXCODE(21, 0)
102
+#define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode used for debug */
103
104
/* cpucfg[0] bits */
105
FIELD(CPUCFG0, PRID, 0, 32)
106
--
107
2.31.1
diff view generated by jsdifflib
[PULL 7/7] target/loongarch: Fix raise_mmu_exception() set wrong exception_index
Deleted patch
1
When the address is invalid address, We should set exception_index
2
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
3
Otherwise, The system enters an infinite loop. e.g:
4
run test.c on system mode
5
test.c:
6
#include<stdio.h>
7
1
8
void (*func)(int *);
9
10
int main()
11
{
12
int i = 8;
13
void *ptr = (void *)0x4000000000000000;
14
func = ptr;
15
func(&i);
16
return 0;
17
}
18
19
Signed-off-by: Song Gao <gaosong@loongson.cn>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-ID: <20221101073210.3934280-2-gaosong@loongson.cn>
22
---
23
target/loongarch/cpu.c | 1 +
24
target/loongarch/tlb_helper.c | 5 +++--
25
2 files changed, 4 insertions(+), 2 deletions(-)
26
27
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/loongarch/cpu.c
30
+++ b/target/loongarch/cpu.c
31
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
32
}
33
QEMU_FALLTHROUGH;
34
case EXCCODE_PIF:
35
+ case EXCCODE_ADEF:
36
cause = cs->exception_index;
37
update_badinstr = 0;
38
break;
39
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/loongarch/tlb_helper.c
42
+++ b/target/loongarch/tlb_helper.c
43
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
44
switch (tlb_error) {
45
default:
46
case TLBRET_BADADDR:
47
- cs->exception_index = EXCCODE_ADEM;
48
+ cs->exception_index = access_type == MMU_INST_FETCH
49
+ ? EXCCODE_ADEF : EXCCODE_ADEM;
50
break;
51
case TLBRET_NOMATCH:
52
/* No TLB match for a mapped address */
53
@@ -XXX,XX +XXX,XX @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
54
CPULoongArchState *env = &cpu->env;
55
hwaddr physical;
56
int prot;
57
- int ret = TLBRET_BADADDR;
58
+ int ret;
59
60
/* Data access */
61
ret = get_physical_address(env, &physical, &prot, address,
62
--
63
2.31.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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