We need to check HCR_E2H and HCR_TGE to select the right MMU index for
the correct translation regime.
To check for EL2&0 translation regime:
- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
- For S1E2* ops, check only HCR_E2H
Signed-off-by: Ake Koomsin <ake@igel.co.jp>
---
v3:
- Avoid recomputing arm_hcr_el2_eff() as recommended by Richard H.
- Use ':?' for more compact code as recommended by Richard H.
v2:
- Rebase with the latest upstream
- It turns out that we need to check both HCR_E2H and HCR_TGE for
S1E0*, S1E1* and S12E* address translation as well according to the
Architecture Manual.
- https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg06084.html
v1:
https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg02627.html
target/arm/helper.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b070a20f1a..c17962372d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3501,19 +3501,22 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
ARMMMUIdx mmu_idx;
int secure = arm_is_secure_below_el3(env);
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+ bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
switch (ri->opc2 & 6) {
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
- mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
+ mmu_idx = regime_e20 ?
+ ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN;
} else {
- mmu_idx = ARMMMUIdx_Stage1_E1;
+ mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1;
}
break;
case 4: /* AT S1E2R, AT S1E2W */
- mmu_idx = ARMMMUIdx_E2;
+ mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_E3;
@@ -3524,13 +3527,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
}
break;
case 2: /* AT S1E0R, AT S1E0W */
- mmu_idx = ARMMMUIdx_Stage1_E0;
+ mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0;
break;
case 4: /* AT S12E1R, AT S12E1W */
- mmu_idx = ARMMMUIdx_E10_1;
+ mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
- mmu_idx = ARMMMUIdx_E10_0;
+ mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0;
break;
default:
g_assert_not_reached();
--
2.25.1
On 11/1/22 17:42, Ake Koomsin wrote: > We need to check HCR_E2H and HCR_TGE to select the right MMU index for > the correct translation regime. > > To check for EL2&0 translation regime: > - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE > - For S1E2* ops, check only HCR_E2H > > Signed-off-by: Ake Koomsin<ake@igel.co.jp> > --- > > v3: > - Avoid recomputing arm_hcr_el2_eff() as recommended by Richard H. > - Use ':?' for more compact code as recommended by Richard H. > > v2: > - Rebase with the latest upstream > - It turns out that we need to check both HCR_E2H and HCR_TGE for > S1E0*, S1E1* and S12E* address translation as well according to the > Architecture Manual. > -https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg06084.html > > v1: > https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg02627.html > > target/arm/helper.c | 15 +++++++++------ > 1 file changed, 9 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Wed, 2 Nov 2022 at 05:33, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/1/22 17:42, Ake Koomsin wrote: > > We need to check HCR_E2H and HCR_TGE to select the right MMU index for > > the correct translation regime. > > > > To check for EL2&0 translation regime: > > - For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE > > - For S1E2* ops, check only HCR_E2H > > > > Signed-off-by: Ake Koomsin<ake@igel.co.jp> > > --- > > > > v3: > > - Avoid recomputing arm_hcr_el2_eff() as recommended by Richard H. > > - Use ':?' for more compact code as recommended by Richard H. > > > > v2: > > - Rebase with the latest upstream > > - It turns out that we need to check both HCR_E2H and HCR_TGE for > > S1E0*, S1E1* and S12E* address translation as well according to the > > Architecture Manual. > > -https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg06084.html > > > > v1: > > https://lists.gnu.org/archive/html/qemu-devel/2022-10/msg02627.html > > > > target/arm/helper.c | 15 +++++++++------ > > 1 file changed, 9 insertions(+), 6 deletions(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Applied to target-arm.next, thanks. -- PMM
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