[v1] hw/isa/piix4: Remove MIPS Malta specific bits

[PATCH 0/3] hw/isa/piix4: Remove MIPS Malta specific bits

Philippe Mathieu-Daudé posted 3 patches 1 year, 6 months ago

Diff against v2
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20221026194619.28880-1-philmd@linaro.org

Maintainers: "Hervé Poussineau" <hpoussin@reactos.org>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>

There is a newer version of this series

hw/isa/piix4.c  |  8 ++++----
hw/mips/malta.c | 23 ++++++++++++++++++++++-
2 files changed, 26 insertions(+), 5 deletions(-)

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[PATCH 0/3] hw/isa/piix4: Remove MIPS Malta specific bits

Posted by Philippe Mathieu-Daudé 1 year, 6 months ago

Bernhard posted a series merging both PIIX3/PIIX4 models
in one [1]. Due to Malta-specific board code forced into
the PIIX4 reset values, Bernhard had to include an array
of "register values at reset" as a class property. This
is not wrong, but to model properly the model, we should
simply use the hardware real reset values, not try to
bend the model to please the Malta board.

This series fix this issue by having the Malta bootloader
code setting the board-specific PIIX4 IRQ routing values.

Note patch 2 still misses an equivalent nanoMIPS code.

Regards,

Phil.

[1] https://lore.kernel.org/qemu-devel/20221022150508.26830-1-shentey@gmail.com/

Philippe Mathieu-Daudé (3):
  hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition
  hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
  hw/isa/piix4: Correct IRQRC[A:D] reset values

 hw/isa/piix4.c  |  8 ++++----
 hw/mips/malta.c | 23 ++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 5 deletions(-)

-- 
2.37.3

Re: [PATCH 0/3] hw/isa/piix4: Remove MIPS Malta specific bits

Posted by Philippe Mathieu-Daudé 1 year, 6 months ago

On 26/10/22 21:46, Philippe Mathieu-Daudé wrote:
> Bernhard posted a series merging both PIIX3/PIIX4 models
> in one [1]. Due to Malta-specific board code forced into
> the PIIX4 reset values, Bernhard had to include an array
> of "register values at reset" as a class property. This
> is not wrong, but to model properly the model, we should
> simply use the hardware real reset values, not try to
> bend the model to please the Malta board.
> 
> This series fix this issue by having the Malta bootloader
> code setting the board-specific PIIX4 IRQ routing values.
> 
> Note patch 2 still misses an equivalent nanoMIPS code.
> 
> Regards,
> 
> Phil.
> 
> [1] https://lore.kernel.org/qemu-devel/20221022150508.26830-1-shentey@gmail.com/
> 
> Philippe Mathieu-Daudé (3):
>    hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition
>    hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader
>    hw/isa/piix4: Correct IRQRC[A:D] reset values

Based-on: <20221026191821.28167-1-philmd@linaro.org>
https://lore.kernel.org/qemu-devel/20221026191821.28167-1-philmd@linaro.org/