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[RESEND PATCH v2] target/i386: Switch back XFRM value

Yang Zhong posted 1 patch 1 year, 6 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20221026115745.528314-1-yang.zhong@intel.com
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[RESEND PATCH v2] target/i386: Switch back XFRM value
Posted by Yang Zhong 1 year, 6 months ago 
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).

Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")

Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ad623d91e4..19aaed877b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         } else {
             *eax &= env->features[FEAT_SGX_12_1_EAX];
             *ebx &= 0; /* ebx reserve */
-            *ecx &= env->features[FEAT_XSAVE_XSS_LO];
-            *edx &= env->features[FEAT_XSAVE_XSS_HI];
+            *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
+            *edx &= env->features[FEAT_XSAVE_XCR0_HI];
 
             /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
             *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
-- 
2.30.2
Re: [RESEND PATCH v2] target/i386: Switch back XFRM value
Posted by Yang, Weijiang 1 year, 6 months ago 
On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> SGX enclave only supported SSE and x87 feature(xfrm=0x3).
>
> Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
>
> Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
> ---
>   target/i386/cpu.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index ad623d91e4..19aaed877b 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           } else {
>               *eax &= env->features[FEAT_SGX_12_1_EAX];
>               *ebx &= 0; /* ebx reserve */
> -            *ecx &= env->features[FEAT_XSAVE_XSS_LO];
> -            *edx &= env->features[FEAT_XSAVE_XSS_HI];
> +            *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
> +            *edx &= env->features[FEAT_XSAVE_XCR0_HI];

Oops, that's my fault to replace with wrong definitions, thanks for the fix!

Reviewed-by:  Yang Weijiang <weijiang.yang@intel.com>

>   
>               /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
>               *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
Re: [RESEND PATCH v2] target/i386: Switch back XFRM value
Posted by Christian Ehrhardt 1 year, 1 month ago 
On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote:
>
>
> On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > SGX enclave only supported SSE and x87 feature(xfrm=0x3).
> >
> > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
> >
> > Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
> > ---
> >   target/i386/cpu.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index ad623d91e4..19aaed877b 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> >           } else {
> >               *eax &= env->features[FEAT_SGX_12_1_EAX];
> >               *ebx &= 0; /* ebx reserve */
> > -            *ecx &= env->features[FEAT_XSAVE_XSS_LO];
> > -            *edx &= env->features[FEAT_XSAVE_XSS_HI];
> > +            *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
> > +            *edx &= env->features[FEAT_XSAVE_XCR0_HI];
>
> Oops, that's my fault to replace with wrong definitions, thanks for the fix!
>
> Reviewed-by:  Yang Weijiang <weijiang.yang@intel.com>

Hi,
I do not have any background on this but stumbled over this and wondered,
is there any particular reason why this wasn't applied yet?

It seemed to fix a former mistake, was acked and then ... silence

> >
> >               /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
> >               *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
>


-- 
Christian Ehrhardt
Senior Staff Engineer, Ubuntu Server
Canonical Ltd
Re: [RESEND PATCH v2] target/i386: Switch back XFRM value
Posted by Yang, Weijiang 1 year, 1 month ago 
On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
> On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote:
>>
>> On 10/26/2022 7:57 PM, Zhong, Yang wrote:
>>> The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
>>> FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
>>> SGX enclave only supported SSE and x87 feature(xfrm=0x3).
>>>
>>> Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
>>>
>>> Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
>>> ---
>>>    target/i386/cpu.c | 4 ++--
>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>>> index ad623d91e4..19aaed877b 100644
>>> --- a/target/i386/cpu.c
>>> +++ b/target/i386/cpu.c
>>> @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>>>            } else {
>>>                *eax &= env->features[FEAT_SGX_12_1_EAX];
>>>                *ebx &= 0; /* ebx reserve */
>>> -            *ecx &= env->features[FEAT_XSAVE_XSS_LO];
>>> -            *edx &= env->features[FEAT_XSAVE_XSS_HI];
>>> +            *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
>>> +            *edx &= env->features[FEAT_XSAVE_XCR0_HI];
>> Oops, that's my fault to replace with wrong definitions, thanks for the fix!
>>
>> Reviewed-by:  Yang Weijiang <weijiang.yang@intel.com>
> Hi,
> I do not have any background on this but stumbled over this and wondered,
> is there any particular reason why this wasn't applied yet?
>
> It seemed to fix a former mistake, was acked and then ... silence

Chris, thanks for the catch!

I double checked this patch isn't in the latest 8.0.0-rc1 tree.


Hi, Paolo,

Could you help merge this fixup patch? Thanks!

>
>>>                /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
>>>                *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
>
Re: [RESEND PATCH v2] target/i386: Switch back XFRM value
Posted by Yang Zhong 1 year ago 
On Mon, Mar 27, 2023 at 04:03:54PM +0800, Yang, Weijiang wrote:
> 
> On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
> > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang <weijiang.yang@intel.com> wrote:
> > > 
> > > On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> > > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > > > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
> > > > SGX enclave only supported SSE and x87 feature(xfrm=0x3).
> > > > 
> > > > Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
> > > > 
> > > > Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
> > > > ---
> > > >    target/i386/cpu.c | 4 ++--
> > > >    1 file changed, 2 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > > index ad623d91e4..19aaed877b 100644
> > > > --- a/target/i386/cpu.c
> > > > +++ b/target/i386/cpu.c
> > > > @@ -5584,8 +5584,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> > > >            } else {
> > > >                *eax &= env->features[FEAT_SGX_12_1_EAX];
> > > >                *ebx &= 0; /* ebx reserve */
> > > > -            *ecx &= env->features[FEAT_XSAVE_XSS_LO];
> > > > -            *edx &= env->features[FEAT_XSAVE_XSS_HI];
> > > > +            *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
> > > > +            *edx &= env->features[FEAT_XSAVE_XCR0_HI];
> > > Oops, that's my fault to replace with wrong definitions, thanks for the fix!
> > > 
> > > Reviewed-by:  Yang Weijiang <weijiang.yang@intel.com>
> > Hi,
> > I do not have any background on this but stumbled over this and wondered,
> > is there any particular reason why this wasn't applied yet?
> > 
> > It seemed to fix a former mistake, was acked and then ... silence
> 
> Chris, thanks for the catch!
> 
> I double checked this patch isn't in the latest 8.0.0-rc1 tree.
> 
> 
> Hi, Paolo,
> 
> Could you help merge this fixup patch? Thanks!


  Hello all,

  Let me rebase this patch and resend it, thanks!

  Yang


> 
> > 
> > > >                /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
> > > >                *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
> >

Patchew 2.1-devel-0870f84

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