Series comparison

-[PULL 00/16] aspeed queue
+[PULL 00/24] aspeed queue
-The following changes since commit 0529245488865038344d64fff7ee05864d3d17f6:
+The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7:
-  Merge tag 'pull-target-arm-20221020' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-10-20 14:36:12 -0400)
+  Update version for v9.2.0 release (2024-12-10 16:20:54 +0000)
 are available in the Git repository at:
-  https://github.com/legoater/qemu/ tags/pull-aspeed-20221025
+  https://github.com/legoater/qemu/ tags/pull-aspeed-20241211
-for you to fetch changes up to 703229132bb05327044368fc6d19f6acf7dde848:
+for you to fetch changes up to 124f4dc0d832c1bf3a4513c05a2b93bac0a5fac0:
-  arm/aspeed: Replace mx25l25635e chip model (2022-10-24 11:20:16 +0200)
+  test/qtest/ast2700-smc-test: Support to test AST2700 (2024-12-11 07:25:53 +0100)
 ----------------------------------------------------------------
-aspeed queue :
+aspeed queue:
-* Performance improvement with Object class caching
+* Removed tacoma-bmc machine
-* Serial Flash Discovery Parameters support for m25p80 device
+* Added support for SDHCI on AST2700 SoC
-* Various small adjustments on intructions and models
+* Improved functional tests
 * Extended SMC qtest to all Aspeed SoCs
 ----------------------------------------------------------------
-Alex Bennée (1):
+Cédric Le Goater (8):
-      ssi: cache SSIPeripheralClass to avoid GET_CLASS()
+      arm: Remove tacoma-bmc machine
       tests/functional: Introduce a specific test for ast1030 SoC
       tests/functional: Introduce a specific test for palmetto-bmc machine
       tests/functional: Introduce a specific test for romulus-bmc machine
       tests/functional: Introduce a specific test for ast2500 SoC
       tests/functional: Introduce a specific test for ast2600 SoC
       tests/functional: Introduce a specific test for rainier-bmc machine
       tests/functional: Move debian boot test from avocado
-Cédric Le Goater (12):
+Jamin Lin (16):
-      tests/avocado/machine_aspeed.py: Fix typos on buildroot
+      hw/sd/aspeed_sdhci: Fix coding style
-      aspeed/smc: Cache AspeedSMCClass
+      hw/arm/aspeed: Fix coding style
-      ast2600: Drop NEON from the CPU features
+      hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
-      m25p80: Add basic support for the SFDP command
+      hw/sd/aspeed_sdhci: Add AST2700 Support
-      m25p80: Add the n25q256a SFDP table
+      aspeed/soc: Support SDHCI for AST2700
-      m25p80: Add erase size for mx25l25635e
+      aspeed/soc: Support eMMC for AST2700
-      m25p80: Add the mx25l25635e SFPD table
+      test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function
-      m25p80: Add the mx25l25635f SFPD table
+      test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs
-      m25p80: Add the mx66l1g45g SFDP table
+      test/qtest/aspeed_smc-test: Support to test all CE pins
-      m25p80: Add the w25q256 SFPD table
+      test/qtest/aspeed_smc-test: Introducing a "page_addr" data field
-      m25p80: Add the w25q512jv SFPD table
+      test/qtest/aspeed_smc-test: Support to test AST2500
-      arm/aspeed: Replace mx25l25635e chip model
+      test/qtest/aspeed_smc-test: Support to test AST2600
       test/qtest/aspeed_smc-test: Support to test AST1030
       test/qtest/aspeed_smc-test: Support write page command with QPI mode
       test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases
       test/qtest/ast2700-smc-test: Support to test AST2700
-Patrick Williams (2):
+ docs/about/deprecated.rst                    |   8 -
-      hw/arm/aspeed: increase Bletchley memory size
+ docs/about/removed-features.rst              |  10 +
-      m25p80: Add the w25q01jvq SFPD table
+ docs/system/arm/aspeed.rst                   |   1 -
  include/hw/sd/aspeed_sdhci.h                 |  13 +-
  tests/qtest/aspeed-smc-utils.h               |  95 ++++
  hw/arm/aspeed.c                              |  28 -
  hw/arm/aspeed_ast2400.c                      |   3 +-
  hw/arm/aspeed_ast2600.c                      |  10 +-
  hw/arm/aspeed_ast27x0.c                      |  35 ++
  hw/sd/aspeed_sdhci.c                         |  67 ++-
  tests/qtest/aspeed-smc-utils.c               | 686 ++++++++++++++++++++++++
  tests/qtest/aspeed_smc-test.c                | 775 ++++++---------------------
  tests/qtest/ast2700-smc-test.c               |  71 +++
  tests/avocado/boot_linux_console.py          |  26 -
  tests/functional/aspeed.py                   |  56 ++
  tests/functional/meson.build                 |  13 +-
  tests/functional/test_arm_aspeed.py          | 351 ------------
  tests/functional/test_arm_aspeed_ast1030.py  |  81 +++
  tests/functional/test_arm_aspeed_ast2500.py  |  59 ++
  tests/functional/test_arm_aspeed_ast2600.py  | 143 +++++
  tests/functional/test_arm_aspeed_palmetto.py |  24 +
  tests/functional/test_arm_aspeed_rainier.py  |  64 +++
  tests/functional/test_arm_aspeed_romulus.py  |  24 +
  tests/qtest/meson.build                      |   5 +-
 files changed, 1623 insertions(+), 1025 deletions(-)
  create mode 100644 tests/qtest/aspeed-smc-utils.h
  create mode 100644 tests/qtest/aspeed-smc-utils.c
  create mode 100644 tests/qtest/ast2700-smc-test.c
  create mode 100644 tests/functional/aspeed.py
  delete mode 100755 tests/functional/test_arm_aspeed.py
  create mode 100644 tests/functional/test_arm_aspeed_ast1030.py
  create mode 100644 tests/functional/test_arm_aspeed_ast2500.py
  create mode 100644 tests/functional/test_arm_aspeed_ast2600.py
  create mode 100644 tests/functional/test_arm_aspeed_palmetto.py
  create mode 100644 tests/functional/test_arm_aspeed_rainier.py
  create mode 100644 tests/functional/test_arm_aspeed_romulus.py
-Peter Delevoryas (1):
-      hw/i2c/aspeed: Fix old reg slave receive
- hw/block/m25p80_sfdp.h          |  29 ++++
- include/hw/i2c/aspeed_i2c.h     |   1 +
- include/hw/ssi/aspeed_smc.h     |   2 +
- include/hw/ssi/ssi.h            |   3 +
- hw/arm/aspeed.c                 |  15 +-
- hw/arm/aspeed_ast2600.c         |   2 +
- hw/block/m25p80.c               |  52 ++++++-
- hw/block/m25p80_sfdp.c          | 332 ++++++++++++++++++++++++++++++++++++++++
- hw/i2c/aspeed_i2c.c             |   8 +-
- hw/ssi/aspeed_smc.c             |   9 +-
- hw/ssi/ssi.c                    |  18 +--
- MAINTAINERS                     |   2 +-
- hw/block/meson.build            |   1 +
- hw/block/trace-events           |   1 +
- tests/avocado/machine_aspeed.py |  16 +-
-files changed, 452 insertions(+), 39 deletions(-)
- create mode 100644 hw/block/m25p80_sfdp.h
- create mode 100644 hw/block/m25p80_sfdp.c

-[PULL 06/16] hw/arm/aspeed: increase Bletchley memory size
+[PULL 01/24] arm: Remove tacoma-bmc machine
-From: Patrick Williams <patrick@stwcx.xyz>
+Removal was scheduled for 10.0. Use the rainier-bmc machine or the
 ast2600-evb as a replacement.
-For the PVT-class hardware we have increased the memory size of
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-this device to 2 GiB.  Adjust the device model accordingly.
+Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
  docs/about/deprecated.rst       |  8 --------
  docs/about/removed-features.rst | 10 ++++++++++
  docs/system/arm/aspeed.rst      |  1 -
  hw/arm/aspeed.c                 | 28 ----------------------------
 files changed, 10 insertions(+), 37 deletions(-)
-Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
+diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+index XXXXXXX..XXXXXXX 100644
-Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
+--- a/docs/about/deprecated.rst
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
++++ b/docs/about/deprecated.rst
----
+@@ -XXX,XX +XXX,XX @@ images are not available, OpenWRT dropped support in 2019, U-Boot in
- hw/arm/aspeed.c | 9 ++++++++-
+, Linux also is dropping support in 2024. It is time to let go of
-file changed, 8 insertions(+), 1 deletion(-)
+ this ancient hardware and focus on newer CPUs and platforms.
 -Arm ``tacoma-bmc`` machine (since 9.1)
 -''''''''''''''''''''''''''''''''''''''''
 -
 -The ``tacoma-bmc`` machine was a board including an AST2600 SoC based
 -BMC and a witherspoon like OpenPOWER system. It was used for bring up
 -of the AST2600 SoC in labs.  It can be easily replaced by the
 -``rainier-bmc`` machine which is a real product.
 -
  Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
  ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/about/removed-features.rst
 +++ b/docs/about/removed-features.rst
@@ -XXX,XX +XXX,XX @@ Aspeed ``swift-bmc`` machine (removed in 7.0)
  This machine was removed because it was unused. Alternative AST2500 based
  OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
 +Aspeed ``tacoma-bmc`` machine (removed in 10.0)
 +'''''''''''''''''''''''''''''''''''''''''''''''
 +
 +The ``tacoma-bmc`` machine was removed because it didn't bring much
 +compared to the ``rainier-bmc`` machine. Also, the ``tacoma-bmc`` was
 +a board used for bring up of the AST2600 SoC that never left the
 +labs. It can be easily replaced by the ``rainier-bmc`` machine, which
 +was the actual final product, or by the ``ast2600-evb`` with some
 +tweaks.
 +
  ppc ``taihu`` machine (removed in 7.2)
  '''''''''''''''''''''''''''''''''''''''''''''
 diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/arm/aspeed.rst
 +++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
  AST2600 SoC based machines :
  - ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex-A7)
 -- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
  - ``rainier-bmc``          IBM Rainier POWER10 BMC
  - ``fuji-bmc``             Facebook Fuji BMC
  - ``bletchley-bmc``        Facebook Bletchley BMC
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
-         aspeed_soc_num_cpus(amc->soc_name);
+ #define AST2700_EVB_HW_STRAP2 0x00000003
  #endif
 -/* Tacoma hardware value */
 -#define TACOMA_BMC_HW_STRAP1  0x00000000
 -#define TACOMA_BMC_HW_STRAP2  0x00000040
 -
  /* Rainier hardware value: (QEMU prototype) */
  #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
  #define RAINIER_BMC_HW_STRAP2 0x80000848
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
      aspeed_machine_ast2600_class_emmc_init(oc);
  };
-+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+-static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
-+#if HOST_LONG_BITS == 32
+-{
-+#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
+-    MachineClass *mc = MACHINE_CLASS(oc);
-+#else
+-    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-+#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
+-
-+#endif
+-    mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
-+
+-    amc->soc_name  = "ast2600-a3";
- static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
+-    amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
 -    amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
 -    amc->fmc_model = "mx66l1g45g";
 -    amc->spi_model = "mx66l1g45g";
 -    amc->num_cs    = 2;
 -    amc->macs_mask  = ASPEED_MAC2_ON;
 -    amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
 -    mc->default_ram_size = 1 * GiB;
 -    aspeed_machine_class_init_cpus_defaults(mc);
 -
 -    mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine";
 -};
 -
  static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
-     amc->num_cs    = 2;
+         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
-     amc->macs_mask = ASPEED_MAC2_ON;
+         .parent        = TYPE_ASPEED_MACHINE,
-     amc->i2c_init  = bletchley_bmc_i2c_init;
+         .class_init    = aspeed_machine_yosemitev2_class_init,
--    mc->default_ram_size = 512 * MiB;
+-    }, {
-+    mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
+-        .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
-     mc->default_cpus = mc->min_cpus = mc->max_cpus =
+-        .parent        = TYPE_ASPEED_MACHINE,
-         aspeed_soc_num_cpus(amc->soc_name);
+-        .class_init    = aspeed_machine_tacoma_class_init,
- }
+     }, {
          .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
          .parent        = TYPE_ASPEED_MACHINE,
 --
-.37.3
+.47.1

-[PULL 09/16] m25p80: Add erase size for mx25l25635e
+[PULL 02/24] hw/sd/aspeed_sdhci: Fix coding style
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-Message-Id: <20221013161241.2805140-4-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Fix coding style issues from checkpatch.pl.
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241204084453.610660-2-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80.c | 3 ++-
+ hw/sd/aspeed_sdhci.c | 6 ++++--
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 4 insertions(+), 2 deletions(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/sd/aspeed_sdhci.c
-+++ b/hw/block/m25p80.c
++++ b/hw/sd/aspeed_sdhci.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
-     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
+         sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
-     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
+         break;
-     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
+     case ASPEED_SDHCI_SDIO_140:
--    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512, 0) },
+-        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 0, 32, val);
-+    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
++        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,
-+            ER_4K | ER_32K) },
++                                            0, 32, val);
-     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
+         break;
-     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
+     case ASPEED_SDHCI_SDIO_144:
-     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
+-        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 32, 32, val);
 +        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,
 +                                            32, 32, val);
          break;
      case ASPEED_SDHCI_SDIO_148:
          sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr,
 --
-.37.3
+.47.1

-[PULL 05/16] ast2600: Drop NEON from the CPU features
+[PULL 03/24] hw/arm/aspeed: Fix coding style
-Currently, the CPU features exposed to the AST2600 QEMU machines are :
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-  half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
+Fix coding style issues from checkpatch.pl.
   vfpd32 lpae evtstrm
-But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-are :
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
+Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_lin@aspeedtech.com
-  half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
   lpae evtstrm
 Drop NEON support in the Aspeed AST2600 SoC.
 Reviewed-by: Joel Stanley <joel@jms.id.au>
 Message-Id: <20220928164719.655586-3-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_ast2600.c | 2 ++
+ hw/arm/aspeed_ast2600.c | 3 ++-
-file changed, 2 insertions(+)
+file changed, 2 insertions(+), 1 deletion(-)
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
 @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
-         object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+         return;
-                                 &error_abort);
+     }
-+        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
-+                                &error_abort);
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
-         object_property_set_link(OBJECT(&s->cpu[i]), "memory",
++                    sc->memmap[ASPEED_DEV_GPIO]);
-                                  OBJECT(s->memory), &error_abort);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                         aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
 --
-.37.3
+.47.1

-[PULL 04/16] aspeed/smc: Cache AspeedSMCClass
+[PULL 04/24] hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
-Store a reference on the AspeedSMC class under the flash object and
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 use it when accessing the flash contents. Avoiding the class cast
 checkers in these hot paths improves performance by 10% when running
 the aspeed avocado tests.
-Message-Id: <20220923084803.498337-7-clg@kaod.org>
+Currently, it set the hardcode value of capability registers to all ASPEED SOCs
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+However, the value of capability registers should be different for all ASPEED
 SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
 -bits System Bus support for AST2700.
 Introduce a new "capareg" class member whose data type is uint_64 to set the
 different Capability Registers to all ASPEED SOCs.
 The value of Capability Register is "0x0000000001e80080" for AST2400 and
 AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- include/hw/ssi/aspeed_smc.h | 2 ++
+ include/hw/sd/aspeed_sdhci.h | 12 +++++++--
- hw/ssi/aspeed_smc.c         | 9 ++++-----
+ hw/arm/aspeed_ast2400.c      |  3 ++-
-files changed, 6 insertions(+), 5 deletions(-)
+ hw/arm/aspeed_ast2600.c      |  7 +++---
  hw/sd/aspeed_sdhci.c         | 47 +++++++++++++++++++++++++++++++++++-
 files changed, 61 insertions(+), 8 deletions(-)
-diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
+diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/aspeed_smc.h
+--- a/include/hw/sd/aspeed_sdhci.h
-+++ b/include/hw/ssi/aspeed_smc.h
++++ b/include/hw/sd/aspeed_sdhci.h
 @@ -XXX,XX +XXX,XX @@
  #include "qom/object.h"
- struct AspeedSMCState;
+ #define TYPE_ASPEED_SDHCI "aspeed.sdhci"
-+struct AspeedSMCClass;
+-OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI)
++#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
- #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
++#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
- OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
++#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
-@@ -XXX,XX +XXX,XX @@ struct AspeedSMCFlash {
++OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
-     SysBusDevice parent_obj;
+-#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
-     struct AspeedSMCState *controller;
+ #define ASPEED_SDHCI_NUM_SLOTS    2
-+    struct AspeedSMCClass *asc;
+ #define ASPEED_SDHCI_NUM_REGS     (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
-     uint8_t cs;
+ #define ASPEED_SDHCI_REG_SIZE     0x100
+@@ -XXX,XX +XXX,XX @@ struct AspeedSDHCIState {
-     MemoryRegion mmio;
+     uint32_t regs[ASPEED_SDHCI_NUM_REGS];
-diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
+ };
 +struct AspeedSDHCIClass {
 +    SysBusDeviceClass parent_class;
 +
 +    uint64_t capareg;
 +};
 +
  #endif /* ASPEED_SDHCI_H */
 diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/aspeed_smc.c
+--- a/hw/arm/aspeed_ast2400.c
-+++ b/hw/ssi/aspeed_smc.c
++++ b/hw/arm/aspeed_ast2400.c
-@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
- static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
+     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
      object_initialize_child(obj, "gpio", &s->gpio, typename);
 -    object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
 +    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
 +    object_initialize_child(obj, "sdc", &s->sdhci, typename);
      object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
      object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
 -    object_initialize_child(obj, "sd-controller", &s->sdhci,
 -                            TYPE_ASPEED_SDHCI);
 +    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
 +    object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
      object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
                                  &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
      }
 -    object_initialize_child(obj, "emmc-controller", &s->emmc,
 -                            TYPE_ASPEED_SDHCI);
 +    object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
      object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
 diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/aspeed_sdhci.c
 +++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
  {
-     const AspeedSMCState *s = fl->controller;
+     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
--    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
-+    AspeedSMCClass *asc = fl->asc;
++    AspeedSDHCIClass *asc = ASPEED_SDHCI_GET_CLASS(sdhci);
-     if (asc->addr_width) {
+     /* Create input irqs for the slots */
-         return asc->addr_width(s);
+     qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
-@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
+@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
-                                               uint32_t addr)
+         }
- {
-     const AspeedSMCState *s = fl->controller;
+         if (!object_property_set_uint(sdhci_slot, "capareg",
--    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+-                                      ASPEED_SDHCI_CAPABILITIES, errp)) {
-+    AspeedSMCClass *asc = fl->asc;
++                                      asc->capareg, errp)) {
-     AspeedSegments seg;
+             return;
+         }
-     asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_smc_info = {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
- static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
+     device_class_set_props(dc, aspeed_sdhci_properties);
  {
      AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
 -    AspeedSMCClass *asc;
      g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
      if (!s->controller) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
          return;
      }
 -    asc = ASPEED_SMC_GET_CLASS(s->controller);
 +    s->asc = ASPEED_SMC_GET_CLASS(s->controller);
      /*
       * Use the default segment value to size the memory region. This
       * can be changed by FW at runtime.
       */
      memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
 -                          s, name, asc->segments[s->cs].size);
 +                          s, name, s->asc->segments[s->cs].size);
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
  }
++static void aspeed_2400_sdhci_class_init(ObjectClass *klass, void *data)
++{
++    DeviceClass *dc = DEVICE_CLASS(klass);
++    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
++
++    dc->desc = "ASPEED 2400 SDHCI Controller";
++    asc->capareg = 0x0000000001e80080;
++}
++
++static void aspeed_2500_sdhci_class_init(ObjectClass *klass, void *data)
++{
++    DeviceClass *dc = DEVICE_CLASS(klass);
++    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
++
++    dc->desc = "ASPEED 2500 SDHCI Controller";
++    asc->capareg = 0x0000000001e80080;
++}
++
++static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data)
++{
++    DeviceClass *dc = DEVICE_CLASS(klass);
++    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
++
++    dc->desc = "ASPEED 2600 SDHCI Controller";
++    asc->capareg = 0x0000000701f80080;
++}
++
+ static const TypeInfo aspeed_sdhci_types[] = {
+     {
+         .name           = TYPE_ASPEED_SDHCI,
+         .parent         = TYPE_SYS_BUS_DEVICE,
+         .instance_size  = sizeof(AspeedSDHCIState),
+         .class_init     = aspeed_sdhci_class_init,
++        .class_size = sizeof(AspeedSDHCIClass),
++        .abstract = true,
++    },
++    {
++        .name = TYPE_ASPEED_2400_SDHCI,
++        .parent = TYPE_ASPEED_SDHCI,
++        .class_init = aspeed_2400_sdhci_class_init,
++    },
++    {
++        .name = TYPE_ASPEED_2500_SDHCI,
++        .parent = TYPE_ASPEED_SDHCI,
++        .class_init = aspeed_2500_sdhci_class_init,
++    },
++    {
++        .name = TYPE_ASPEED_2600_SDHCI,
++        .parent = TYPE_ASPEED_SDHCI,
++        .class_init = aspeed_2600_sdhci_class_init,
+     },
+ };
 --
-.37.3
+.47.1

-[PULL 15/16] m25p80: Add the w25q01jvq SFPD table
+[PULL 05/24] hw/sd/aspeed_sdhci: Add AST2700 Support
-From: Patrick Williams <patrick@stwcx.xyz>
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-Generated from hardware using the following command and then padding
+Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
-with 0xff to fill out a power-of-2:
+init function and set the value of capability register to "0x0000000719f80080".
     hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`
-Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
-[ clg: removed extern ]
+Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_lin@aspeedtech.com
-Message-Id: <20221006224424.3556372-1-patrick@stwcx.xyz>
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
 Message-Id: <20221013161241.2805140-10-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ include/hw/sd/aspeed_sdhci.h |  1 +
- hw/block/m25p80.c      |  3 ++-
+ hw/sd/aspeed_sdhci.c         | 14 ++++++++++++++
- hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
+files changed, 15 insertions(+)
 files changed, 40 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/include/hw/sd/aspeed_sdhci.h
-+++ b/hw/block/m25p80_sfdp.h
++++ b/include/hw/sd/aspeed_sdhci.h
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@
- uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+ #define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
- uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
+ #define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
+ #define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
-+uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
++#define TYPE_ASPEED_2700_SDHCI TYPE_ASPEED_SDHCI "-ast2700"
  OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
  #define ASPEED_SDHCI_NUM_SLOTS    2
 diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/aspeed_sdhci.c
 +++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data)
      asc->capareg = 0x0000000701f80080;
  }
 +static void aspeed_2700_sdhci_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
 +
- #endif
++    dc->desc = "ASPEED 2700 SDHCI Controller";
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++    asc->capareg = 0x0000000719f80080;
-index XXXXXXX..XXXXXXX 100644
++}
---- a/hw/block/m25p80.c
++
-+++ b/hw/block/m25p80.c
+ static const TypeInfo aspeed_sdhci_types[] = {
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+     {
-       .sfdp_read = m25p80_sfdp_w25q256 },
+         .name           = TYPE_ASPEED_SDHCI,
-     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdhci_types[] = {
-       .sfdp_read = m25p80_sfdp_w25q512jv },
+         .parent = TYPE_ASPEED_SDHCI,
--    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
+         .class_init = aspeed_2600_sdhci_class_init,
-+    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
+     },
-+      .sfdp_read = m25p80_sfdp_w25q01jvq },
++    {
 +        .name = TYPE_ASPEED_2700_SDHCI,
 +        .parent = TYPE_ASPEED_SDHCI,
 +        .class_init = aspeed_2700_sdhci_class_init,
 +    },
  };
- typedef enum {
+ DEFINE_TYPES(aspeed_sdhci_types)
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q512jv[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(w25q512jv);
 +
 +static const uint8_t sfdp_w25q01jvq[] = {
 +    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
 +    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
 +    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
 +    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
 +    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
 +    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
 +    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
 +    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
 +    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(w25q01jvq);
 --
-.37.3
+.47.1

-New patch
+[PULL 06/24] aspeed/soc: Support SDHCI for AST2700
+From: Jamin Lin <jamin_lin@aspeedtech.com>
+Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
+slot and registers base address is start at 0x1408_0000 and its interrupt is
+connected to GICINT133_INTC at bit 1.
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
+Link: https://lore.kernel.org/r/20241204084453.610660-6-jamin_lin@aspeedtech.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ hw/arm/aspeed_ast27x0.c | 20 ++++++++++++++++++++
+file changed, 20 insertions(+)
+diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed_ast27x0.c
++++ b/hw/arm/aspeed_ast27x0.c
+@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
+     [ASPEED_DEV_I2C]       =  0x14C0F000,
+     [ASPEED_DEV_GPIO]      =  0x14C0B000,
+     [ASPEED_DEV_RTC]       =  0x12C0F000,
++    [ASPEED_DEV_SDHCI]     =  0x14080000,
+ };
+ #define AST2700_MAX_IRQ 256
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_irqmap[] = {
+     [ASPEED_DEV_KCS]       = 128,
+     [ASPEED_DEV_DP]        = 28,
+     [ASPEED_DEV_I3C]       = 131,
++    [ASPEED_DEV_SDHCI]     = 133,
+ };
+ /* GICINT 128 */
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
+ /* GICINT 133 */
+ static const int aspeed_soc_ast2700_gic133_intcmap[] = {
++    [ASPEED_DEV_SDHCI]     = 1,
+     [ASPEED_DEV_PECI]      = 4,
+ };
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)
+     object_initialize_child(obj, "gpio", &s->gpio, typename);
+     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
++
++    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
++    object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
++    object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort);
++
++    /* Init sd card slot class here so that they're under the correct parent */
++    object_initialize_child(obj, "sd-controller.sdhci",
++                            &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
+                        aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
++    /* SDHCI */
++    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
++        return;
++    }
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
++                    sc->memmap[ASPEED_DEV_SDHCI]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
++                       aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
++
+     create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
+     create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
+     create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
+--
+.47.1

-New patch
+[PULL 07/24] aspeed/soc: Support eMMC for AST2700
+From: Jamin Lin <jamin_lin@aspeedtech.com>
+Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
+slot and registers base address is start at 0x1209_0000 and its interrupt is
+connected to GICINT 15.
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
+Link: https://lore.kernel.org/r/20241204084453.610660-7-jamin_lin@aspeedtech.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
+file changed, 15 insertions(+)
+diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/aspeed_ast27x0.c
++++ b/hw/arm/aspeed_ast27x0.c
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)
+     /* Init sd card slot class here so that they're under the correct parent */
+     object_initialize_child(obj, "sd-controller.sdhci",
+                             &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
++
++    object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
++    object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
++
++    object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
++                            TYPE_SYSBUS_SDHCI);
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+                        aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
++    /* eMMC */
++    if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
++        return;
++    }
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
++                    sc->memmap[ASPEED_DEV_EMMC]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
++                       aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
++
+     create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
+     create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
+     create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
+--
+.47.1

-New patch
+[PULL 08/24] tests/functional: Introduce a specific test for ast1030 SoC
+This simply moves the ast1030 tests to a new test file. No changes.
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Link: https://lore.kernel.org/r/20241206131132.520911-2-clg@redhat.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ tests/functional/meson.build                |  1 +
+ tests/functional/test_arm_aspeed.py         | 64 ----------------
+ tests/functional/test_arm_aspeed_ast1030.py | 81 +++++++++++++++++++++
+files changed, 82 insertions(+), 64 deletions(-)
+ create mode 100644 tests/functional/test_arm_aspeed_ast1030.py
+diff --git a/tests/functional/meson.build b/tests/functional/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/functional/meson.build
++++ b/tests/functional/meson.build
+@@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [
+ tests_arm_system_thorough = [
+   'arm_aspeed',
++  'arm_aspeed_ast1030',
+   'arm_bpim2u',
+   'arm_canona1100',
+   'arm_collie',
+diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
+index XXXXXXX..XXXXXXX 100755
+--- a/tests/functional/test_arm_aspeed.py
++++ b/tests/functional/test_arm_aspeed.py
+@@ -XXX,XX +XXX,XX @@
+ from zipfile import ZipFile
+ from unittest import skipUnless
+-class AST1030Machine(LinuxKernelTest):
+-
+-    ASSET_ZEPHYR_1_04 = Asset(
+-        ('https://github.com/AspeedTech-BMC'
+-         '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
+-        '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
+-
+-    def test_ast1030_zephyros_1_04(self):
+-        self.set_machine('ast1030-evb')
+-
+-        zip_file = self.ASSET_ZEPHYR_1_04.fetch()
+-
+-        kernel_name = "ast1030-evb-demo/zephyr.elf"
+-        with ZipFile(zip_file, 'r') as zf:
+-                     zf.extract(kernel_name, path=self.workdir)
+-        kernel_file = os.path.join(self.workdir, kernel_name)
+-
+-        self.vm.set_console()
+-        self.vm.add_args('-kernel', kernel_file, '-nographic')
+-        self.vm.launch()
+-        self.wait_for_console_pattern("Booting Zephyr OS")
+-        exec_command_and_wait_for_pattern(self, "help",
+-                                          "Available commands")
+-
+-    ASSET_ZEPHYR_1_07 = Asset(
+-        ('https://github.com/AspeedTech-BMC'
+-         '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
+-        'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
+-
+-    def test_ast1030_zephyros_1_07(self):
+-        self.set_machine('ast1030-evb')
+-
+-        zip_file = self.ASSET_ZEPHYR_1_07.fetch()
+-
+-        kernel_name = "ast1030-evb-demo/zephyr.bin"
+-        with ZipFile(zip_file, 'r') as zf:
+-                     zf.extract(kernel_name, path=self.workdir)
+-        kernel_file = os.path.join(self.workdir, kernel_name)
+-
+-        self.vm.set_console()
+-        self.vm.add_args('-kernel', kernel_file, '-nographic')
+-        self.vm.launch()
+-        self.wait_for_console_pattern("Booting Zephyr OS")
+-        for shell_cmd in [
+-                'kernel stacks',
+-                'otp info conf',
+-                'otp info scu',
+-                'hwinfo devid',
+-                'crypto aes256_cbc_vault',
+-                'random get',
+-                'jtag JTAG1 sw_xfer high TMS',
+-                'adc ADC0 resolution 12',
+-                'adc ADC0 read 42',
+-                'adc ADC1 read 69',
+-                'i2c scan I2C_0',
+-                'i3c attach I3C_0',
+-                'hash test',
+-                'kernel uptime',
+-                'kernel reboot warm',
+-                'kernel uptime',
+-                'kernel reboot cold',
+-                'kernel uptime',
+-        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
+-
+ class AST2x00Machine(LinuxKernelTest):
+     def do_test_arm_aspeed(self, machine, image):
+diff --git a/tests/functional/test_arm_aspeed_ast1030.py b/tests/functional/test_arm_aspeed_ast1030.py
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/tests/functional/test_arm_aspeed_ast1030.py
+@@ -XXX,XX +XXX,XX @@
++#!/usr/bin/env python3
++#
++# Functional test that boots the ASPEED SoCs with firmware
++#
++# Copyright (C) 2022 ASPEED Technology Inc
++#
++# SPDX-License-Identifier: GPL-2.0-or-later
++
++import os
++
++from qemu_test import LinuxKernelTest, Asset
++from qemu_test import exec_command_and_wait_for_pattern
++from zipfile import ZipFile
++
++class AST1030Machine(LinuxKernelTest):
++
++    ASSET_ZEPHYR_1_04 = Asset(
++        ('https://github.com/AspeedTech-BMC'
++         '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
++        '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
++
++    def test_ast1030_zephyros_1_04(self):
++        self.set_machine('ast1030-evb')
++
++        zip_file = self.ASSET_ZEPHYR_1_04.fetch()
++
++        kernel_name = "ast1030-evb-demo/zephyr.elf"
++        with ZipFile(zip_file, 'r') as zf:
++                     zf.extract(kernel_name, path=self.workdir)
++        kernel_file = os.path.join(self.workdir, kernel_name)
++
++        self.vm.set_console()
++        self.vm.add_args('-kernel', kernel_file, '-nographic')
++        self.vm.launch()
++        self.wait_for_console_pattern("Booting Zephyr OS")
++        exec_command_and_wait_for_pattern(self, "help",
++                                          "Available commands")
++
++    ASSET_ZEPHYR_1_07 = Asset(
++        ('https://github.com/AspeedTech-BMC'
++         '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
++        'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
++
++    def test_ast1030_zephyros_1_07(self):
++        self.set_machine('ast1030-evb')
++
++        zip_file = self.ASSET_ZEPHYR_1_07.fetch()
++
++        kernel_name = "ast1030-evb-demo/zephyr.bin"
++        with ZipFile(zip_file, 'r') as zf:
++                     zf.extract(kernel_name, path=self.workdir)
++        kernel_file = os.path.join(self.workdir, kernel_name)
++
++        self.vm.set_console()
++        self.vm.add_args('-kernel', kernel_file, '-nographic')
++        self.vm.launch()
++        self.wait_for_console_pattern("Booting Zephyr OS")
++        for shell_cmd in [
++                'kernel stacks',
++                'otp info conf',
++                'otp info scu',
++                'hwinfo devid',
++                'crypto aes256_cbc_vault',
++                'random get',
++                'jtag JTAG1 sw_xfer high TMS',
++                'adc ADC0 resolution 12',
++                'adc ADC0 read 42',
++                'adc ADC1 read 69',
++                'i2c scan I2C_0',
++                'i3c attach I3C_0',
++                'hash test',
++                'kernel uptime',
++                'kernel reboot warm',
++                'kernel uptime',
++                'kernel reboot cold',
++                'kernel uptime',
++        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
++
++
++if __name__ == '__main__':
++    LinuxKernelTest.main()
+--
+.47.1

-New patch
+[PULL 09/24] tests/functional: Introduce a specific test for palmetto-bmc machine
+This introduces a new aspeed module for sharing code between tests and
+moves the palmetto test to a new test file. No changes in the test.
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Link: https://lore.kernel.org/r/20241206131132.520911-3-clg@redhat.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ tests/functional/aspeed.py                   | 23 +++++++++++++++++++
+ tests/functional/meson.build                 |  2 ++
+ tests/functional/test_arm_aspeed.py          | 10 --------
+ tests/functional/test_arm_aspeed_palmetto.py | 24 ++++++++++++++++++++
+files changed, 49 insertions(+), 10 deletions(-)
+ create mode 100644 tests/functional/aspeed.py
+ create mode 100644 tests/functional/test_arm_aspeed_palmetto.py
+diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/tests/functional/aspeed.py
+@@ -XXX,XX +XXX,XX @@
++# Test class to boot aspeed machines
++#
++# SPDX-License-Identifier: GPL-2.0-or-later
++
++from qemu_test import LinuxKernelTest
++
++class AspeedTest(LinuxKernelTest):
++
++    def do_test_arm_aspeed(self, machine, image):
++        self.set_machine(machine)
++        self.vm.set_console()
++        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
++                         '-net', 'nic', '-snapshot')
++        self.vm.launch()
++
++        self.wait_for_console_pattern("U-Boot 2016.07")
++        self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")
++        self.wait_for_console_pattern("Starting kernel ...")
++        self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
++        self.wait_for_console_pattern(
++                "aspeed-smc 1e620000.spi: read control register: 203b0641")
++        self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
++        self.wait_for_console_pattern("systemd[1]: Set hostname to")
+diff --git a/tests/functional/meson.build b/tests/functional/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/functional/meson.build
++++ b/tests/functional/meson.build
+@@ -XXX,XX +XXX,XX @@ test_timeouts = {
+   'aarch64_tuxrun' : 240,
+   'aarch64_virt' : 720,
+   'acpi_bits' : 420,
++  'arm_aspeed_palmetto' : 120,
+   'arm_aspeed' : 600,
+   'arm_bpim2u' : 500,
+   'arm_collie' : 180,
+@@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [
+ tests_arm_system_thorough = [
+   'arm_aspeed',
+   'arm_aspeed_ast1030',
++  'arm_aspeed_palmetto',
+   'arm_bpim2u',
+   'arm_canona1100',
+   'arm_collie',
+diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
+index XXXXXXX..XXXXXXX 100755
+--- a/tests/functional/test_arm_aspeed.py
++++ b/tests/functional/test_arm_aspeed.py
+@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image):
+         self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
+         self.wait_for_console_pattern("systemd[1]: Set hostname to")
+-    ASSET_PALMETTO_FLASH = Asset(
+-        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
+-         'obmc-phosphor-image-palmetto.static.mtd'),
+-        '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d');
+-
+-    def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
+-        image_path = self.ASSET_PALMETTO_FLASH.fetch()
+-
+-        self.do_test_arm_aspeed('palmetto-bmc', image_path)
+-
+     ASSET_ROMULUS_FLASH = Asset(
+         ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
+          'obmc-phosphor-image-romulus.static.mtd'),
+diff --git a/tests/functional/test_arm_aspeed_palmetto.py b/tests/functional/test_arm_aspeed_palmetto.py
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/tests/functional/test_arm_aspeed_palmetto.py
+@@ -XXX,XX +XXX,XX @@
++#!/usr/bin/env python3
++#
++# Functional test that boots the ASPEED machines
++#
++# SPDX-License-Identifier: GPL-2.0-or-later
++
++from qemu_test import Asset
++from aspeed import AspeedTest
++
++class PalmettoMachine(AspeedTest):
++
++    ASSET_PALMETTO_FLASH = Asset(
++        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
++         'obmc-phosphor-image-palmetto.static.mtd'),
++        '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d');
++
++    def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
++        image_path = self.ASSET_PALMETTO_FLASH.fetch()
++
++        self.do_test_arm_aspeed('palmetto-bmc', image_path)
++
++
++if __name__ == '__main__':
++    AspeedTest.main()
+--
+.47.1

-[PULL 10/16] m25p80: Add the mx25l25635e SFPD table
+[PULL 10/24] tests/functional: Introduce a specific test for romulus-bmc machine
-The SFDP table is 0x80 bytes long. The mandatory table for basic
+This simply moves the romulus-bmc test to a new test file. No changes
-features is available at byte 0x30 and an extra Macronix specific
+in the test. The do_test_arm_aspeed routine is removed from the
-table is available at 0x60.
+test_arm_aspeed.py file because it is now unused.
-B opcodes are not supported.
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Link: https://lore.kernel.org/r/20241206131132.520911-4-clg@redhat.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
  tests/functional/meson.build                |  2 ++
  tests/functional/test_arm_aspeed.py         | 26 ---------------------
  tests/functional/test_arm_aspeed_romulus.py | 24 +++++++++++++++++++
 files changed, 26 insertions(+), 26 deletions(-)
  create mode 100644 tests/functional/test_arm_aspeed_romulus.py
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+diff --git a/tests/functional/meson.build b/tests/functional/meson.build
 Message-Id: <20220722063602.128144-4-clg@kaod.org>
 Message-Id: <20221013161241.2805140-5-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  hw/block/m25p80_sfdp.h |  3 +++
  hw/block/m25p80.c      |  2 +-
  hw/block/m25p80_sfdp.c | 26 ++++++++++++++++++++++++++
 files changed, 30 insertions(+), 1 deletion(-)
 diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/tests/functional/meson.build
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ test_timeouts = {
    'aarch64_virt' : 720,
    'acpi_bits' : 420,
    'arm_aspeed_palmetto' : 120,
 +  'arm_aspeed_romulus' : 120,
    'arm_aspeed' : 600,
    'arm_bpim2u' : 500,
    'arm_collie' : 180,
@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [
    'arm_aspeed',
    'arm_aspeed_ast1030',
    'arm_aspeed_palmetto',
 +  'arm_aspeed_romulus',
    'arm_bpim2u',
    'arm_canona1100',
    'arm_collie',
 diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_arm_aspeed.py
 +++ b/tests/functional/test_arm_aspeed.py
 @@ -XXX,XX +XXX,XX @@
- uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+ class AST2x00Machine(LinuxKernelTest):
-+uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+-    def do_test_arm_aspeed(self, machine, image):
 -        self.set_machine(machine)
 -        self.vm.set_console()
 -        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
 -                         '-net', 'nic', '-snapshot')
 -        self.vm.launch()
 -
 -        self.wait_for_console_pattern("U-Boot 2016.07")
 -        self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")
 -        self.wait_for_console_pattern("Starting kernel ...")
 -        self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
 -        self.wait_for_console_pattern(
 -                "aspeed-smc 1e620000.spi: read control register: 203b0641")
 -        self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
 -        self.wait_for_console_pattern("systemd[1]: Set hostname to")
 -
 -    ASSET_ROMULUS_FLASH = Asset(
 -        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
 -         'obmc-phosphor-image-romulus.static.mtd'),
 -        '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
 -
 -    def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
 -        image_path = self.ASSET_ROMULUS_FLASH.fetch()
 -
 -        self.do_test_arm_aspeed('romulus-bmc', image_path)
 -
      def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
          self.require_netdev('user')
          self.vm.set_console()
 diff --git a/tests/functional/test_arm_aspeed_romulus.py b/tests/functional/test_arm_aspeed_romulus.py
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/functional/test_arm_aspeed_romulus.py
@@ -XXX,XX +XXX,XX @@
 +#!/usr/bin/env python3
 +#
 +# Functional test that boots the ASPEED machines
 +#
 +# SPDX-License-Identifier: GPL-2.0-or-later
 +
 +from qemu_test import Asset
 +from aspeed import AspeedTest
 +
 +class RomulusMachine(AspeedTest):
 +
 +    ASSET_ROMULUS_FLASH = Asset(
 +        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
 +         'obmc-phosphor-image-romulus.static.mtd'),
 +        '820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
 +
 +    def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
 +        image_path = self.ASSET_ROMULUS_FLASH.fetch()
 +
 +        self.do_test_arm_aspeed('romulus-bmc', image_path)
 +
 +
- #endif
++if __name__ == '__main__':
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++    AspeedTest.main()
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80.c
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
      { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
      { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
 -            ER_4K | ER_32K) },
 +            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
      { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
      { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
      { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_n25q256a[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(n25q256a);
 +
 +
 +/*
 + * Matronix
 + */
 +
 +/* mx25l25635e. No 4B opcodes */
 +static const uint8_t sfdp_mx25l25635e[] = {
 +    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
 +    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
 +    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
 +    0xee, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
 +    0xff, 0xff, 0x00, 0xff, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0x00, 0x36, 0x00, 0x27, 0xf7, 0x4f, 0xff, 0xff,
 +    0xd9, 0xc8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(mx25l25635e)
 --
-.37.3
+.47.1

-New patch
+[PULL 11/24] tests/functional: Introduce a specific test for ast2500 SoC
+This moves the ast2500-evb tests to a new test file and extends the
 aspeed module with routines used to run the buildroot and sdk
 tests. No changes in the test.
 Reviewed-by: Thomas Huth <thuth@redhat.com>
 Link: https://lore.kernel.org/r/20241206131132.520911-5-clg@redhat.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
  tests/functional/aspeed.py                  | 33 ++++++++++++
  tests/functional/meson.build                |  2 +
  tests/functional/test_arm_aspeed.py         | 44 ---------------
  tests/functional/test_arm_aspeed_ast2500.py | 59 +++++++++++++++++++++
 files changed, 94 insertions(+), 44 deletions(-)
  create mode 100644 tests/functional/test_arm_aspeed_ast2500.py
 diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/functional/aspeed.py
 +++ b/tests/functional/aspeed.py
@@ -XXX,XX +XXX,XX @@
  #
  # SPDX-License-Identifier: GPL-2.0-or-later
 +from qemu_test import exec_command_and_wait_for_pattern
  from qemu_test import LinuxKernelTest
  class AspeedTest(LinuxKernelTest):
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image):
                  "aspeed-smc 1e620000.spi: read control register: 203b0641")
          self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
          self.wait_for_console_pattern("systemd[1]: Set hostname to")
 +
 +    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
 +        self.require_netdev('user')
 +        self.vm.set_console()
 +        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true',
 +                         '-net', 'nic', '-net', 'user')
 +        self.vm.launch()
 +
 +        self.wait_for_console_pattern('U-Boot 2019.04')
 +        self.wait_for_console_pattern('## Loading kernel from FIT Image')
 +        self.wait_for_console_pattern('Starting kernel ...')
 +        self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
 +        self.wait_for_console_pattern('lease of 10.0.2.15')
 +        # the line before login:
 +        self.wait_for_console_pattern(pattern)
 +        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
 +        exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
 +
 +    def do_test_arm_aspeed_buildroot_poweroff(self):
 +        exec_command_and_wait_for_pattern(self, 'poweroff',
 +                                          'reboot: System halted');
 +
 +    def do_test_arm_aspeed_sdk_start(self, image):
 +        self.require_netdev('user')
 +        self.vm.set_console()
 +        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
 +                         '-net', 'nic', '-net', 'user', '-snapshot')
 +        self.vm.launch()
 +
 +        self.wait_for_console_pattern('U-Boot 2019.04')
 +        self.wait_for_console_pattern('## Loading kernel from FIT Image')
 +        self.wait_for_console_pattern('Starting kernel ...')
 diff --git a/tests/functional/meson.build b/tests/functional/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/functional/meson.build
 +++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ test_timeouts = {
    'acpi_bits' : 420,
    'arm_aspeed_palmetto' : 120,
    'arm_aspeed_romulus' : 120,
 +  'arm_aspeed_ast2500' : 480,
    'arm_aspeed' : 600,
    'arm_bpim2u' : 500,
    'arm_collie' : 180,
@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [
    'arm_aspeed_ast1030',
    'arm_aspeed_palmetto',
    'arm_aspeed_romulus',
 +  'arm_aspeed_ast2500',
    'arm_bpim2u',
    'arm_canona1100',
    'arm_collie',
 diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
 index XXXXXXX..XXXXXXX 100755
 --- a/tests/functional/test_arm_aspeed.py
 +++ b/tests/functional/test_arm_aspeed.py
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'
      def do_test_arm_aspeed_buildroot_poweroff(self):
          exec_command_and_wait_for_pattern(self, 'poweroff',
                                            'reboot: System halted');
 -
 -    ASSET_BR2_202311_AST2500_FLASH = Asset(
 -        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
 -         'images/ast2500-evb/buildroot-2023.11/flash.img'),
 -        'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
 -
 -    def test_arm_ast2500_evb_buildroot(self):
 -        self.set_machine('ast2500-evb')
 -
 -        image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch()
 -
 -        self.vm.add_args('-device',
 -                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
 -        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
 -                                                'ast2500-evb login:')
 -
 -        exec_command_and_wait_for_pattern(self,
 -             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
 -             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
 -        exec_command_and_wait_for_pattern(self,
 -                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
 -        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
 -                    property='temperature', value=18000);
 -        exec_command_and_wait_for_pattern(self,
 -                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
 -
 -        self.do_test_arm_aspeed_buildroot_poweroff()
 -
      ASSET_BR2_202311_AST2600_FLASH = Asset(
          ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
           'images/ast2600-evb/buildroot-2023.11/flash.img'),
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image):
          self.wait_for_console_pattern('## Loading kernel from FIT Image')
          self.wait_for_console_pattern('Starting kernel ...')
 -    ASSET_SDK_V806_AST2500 = Asset(
 -        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz',
 -        'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
 -
 -    def test_arm_ast2500_evb_sdk(self):
 -        self.set_machine('ast2500-evb')
 -
 -        image_path = self.ASSET_SDK_V806_AST2500.fetch()
 -
 -        archive_extract(image_path, self.workdir)
 -
 -        self.do_test_arm_aspeed_sdk_start(
 -            self.workdir + '/ast2500-default/image-bmc')
 -
 -        self.wait_for_console_pattern('ast2500-default login:')
 -
      ASSET_SDK_V806_AST2600_A2 = Asset(
          'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
          '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
 diff --git a/tests/functional/test_arm_aspeed_ast2500.py b/tests/functional/test_arm_aspeed_ast2500.py
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/functional/test_arm_aspeed_ast2500.py
@@ -XXX,XX +XXX,XX @@
 +#!/usr/bin/env python3
 +#
 +# Functional test that boots the ASPEED machines
 +#
 +# SPDX-License-Identifier: GPL-2.0-or-later
 +
 +from qemu_test import Asset
 +from aspeed import AspeedTest
 +from qemu_test import exec_command_and_wait_for_pattern
 +from qemu_test.utils import archive_extract
 +
 +class AST2500Machine(AspeedTest):
 +
 +    ASSET_BR2_202311_AST2500_FLASH = Asset(
 +        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
 +         'images/ast2500-evb/buildroot-2023.11/flash.img'),
 +        'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
 +
 +    def test_arm_ast2500_evb_buildroot(self):
 +        self.set_machine('ast2500-evb')
 +
 +        image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch()
 +
 +        self.vm.add_args('-device',
 +                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
 +        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
 +                                                'ast2500-evb login:')
 +
 +        exec_command_and_wait_for_pattern(self,
 +             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
 +             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
 +        exec_command_and_wait_for_pattern(self,
 +                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
 +        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
 +                    property='temperature', value=18000);
 +        exec_command_and_wait_for_pattern(self,
 +                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
 +
 +        self.do_test_arm_aspeed_buildroot_poweroff()
 +
 +    ASSET_SDK_V806_AST2500 = Asset(
 +        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz',
 +        'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
 +
 +    def test_arm_ast2500_evb_sdk(self):
 +        self.set_machine('ast2500-evb')
 +
 +        image_path = self.ASSET_SDK_V806_AST2500.fetch()
 +
 +        archive_extract(image_path, self.workdir)
 +
 +        self.do_test_arm_aspeed_sdk_start(
 +            self.workdir + '/ast2500-default/image-bmc')
 +
 +        self.wait_for_console_pattern('ast2500-default login:')
 +
 +
 +if __name__ == '__main__':
 +    AspeedTest.main()
 --
 .47.1

-New patch
+[PULL 12/24] tests/functional: Introduce a specific test for ast2600 SoC
+This moves the ast2600-evb tests to a new test file. No changes in the
+test. The routines used to run the buildroot and sdk tests are removed
+from the test_arm_aspeed.py file because now unused.
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Link: https://lore.kernel.org/r/20241206131132.520911-6-clg@redhat.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ tests/functional/meson.build                |   2 +
+ tests/functional/test_arm_aspeed.py         | 155 --------------------
+ tests/functional/test_arm_aspeed_ast2600.py | 143 ++++++++++++++++++
+files changed, 145 insertions(+), 155 deletions(-)
+ create mode 100644 tests/functional/test_arm_aspeed_ast2600.py
+diff --git a/tests/functional/meson.build b/tests/functional/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/functional/meson.build
++++ b/tests/functional/meson.build
+@@ -XXX,XX +XXX,XX @@ test_timeouts = {
+   'arm_aspeed_palmetto' : 120,
+   'arm_aspeed_romulus' : 120,
+   'arm_aspeed_ast2500' : 480,
++  'arm_aspeed_ast2600' : 720,
+   'arm_aspeed' : 600,
+   'arm_bpim2u' : 500,
+   'arm_collie' : 180,
+@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [
+   'arm_aspeed_palmetto',
+   'arm_aspeed_romulus',
+   'arm_aspeed_ast2500',
++  'arm_aspeed_ast2600',
+   'arm_bpim2u',
+   'arm_canona1100',
+   'arm_collie',
+diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
+index XXXXXXX..XXXXXXX 100755
+--- a/tests/functional/test_arm_aspeed.py
++++ b/tests/functional/test_arm_aspeed.py
+@@ -XXX,XX +XXX,XX @@
+ from zipfile import ZipFile
+ from unittest import skipUnless
+-class AST2x00Machine(LinuxKernelTest):
+-
+-    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
+-        self.require_netdev('user')
+-        self.vm.set_console()
+-        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true',
+-                         '-net', 'nic', '-net', 'user')
+-        self.vm.launch()
+-
+-        self.wait_for_console_pattern('U-Boot 2019.04')
+-        self.wait_for_console_pattern('## Loading kernel from FIT Image')
+-        self.wait_for_console_pattern('Starting kernel ...')
+-        self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
+-        self.wait_for_console_pattern('lease of 10.0.2.15')
+-        # the line before login:
+-        self.wait_for_console_pattern(pattern)
+-        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+-        exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
+-
+-    def do_test_arm_aspeed_buildroot_poweroff(self):
+-        exec_command_and_wait_for_pattern(self, 'poweroff',
+-                                          'reboot: System halted');
+-    ASSET_BR2_202311_AST2600_FLASH = Asset(
+-        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+-         'images/ast2600-evb/buildroot-2023.11/flash.img'),
+-        'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
+-
+-    def test_arm_ast2600_evb_buildroot(self):
+-        self.set_machine('ast2600-evb')
+-
+-        image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch()
+-
+-        self.vm.add_args('-device',
+-                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
+-        self.vm.add_args('-device',
+-                         'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
+-        self.vm.add_args('-device',
+-                         'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
+-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
+-                                                'ast2600-evb login:')
+-
+-        exec_command_and_wait_for_pattern(self,
+-             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
+-             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
+-        exec_command_and_wait_for_pattern(self,
+-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
+-        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+-                    property='temperature', value=18000);
+-        exec_command_and_wait_for_pattern(self,
+-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
+-
+-        exec_command_and_wait_for_pattern(self,
+-             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
+-             'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
+-        year = time.strftime("%Y")
+-        exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
+-
+-        exec_command_and_wait_for_pattern(self,
+-             'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
+-             'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64');
+-        exec_command_and_wait_for_pattern(self,
+-             'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
+-        exec_command_and_wait_for_pattern(self,
+-             'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
+-             '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
+-        self.do_test_arm_aspeed_buildroot_poweroff()
+-
+-    ASSET_BR2_202302_AST2600_TPM_FLASH = Asset(
+-        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+-         'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
+-        'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
+-
+-    @skipUnless(*has_cmd('swtpm'))
+-    def test_arm_ast2600_evb_buildroot_tpm(self):
+-        self.set_machine('ast2600-evb')
+-
+-        image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
+-
+-        tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_")
+-        socket = os.path.join(tpmstate_dir.name, 'swtpm-socket')
+-
+-        # We must put the TPM state dir in /tmp/, not the build dir,
+-        # because some distros use AppArmor to lock down swtpm and
+-        # restrict the set of locations it can access files in.
+-        subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
+-                        '--tpmstate', f'dir={tpmstate_dir.name}',
+-                        '--ctrl', f'type=unixio,path={socket}'])
+-
+-        self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
+-        self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
+-        self.vm.add_args('-device',
+-                         'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
+-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
+-
+-        exec_command_and_wait_for_pattern(self,
+-            'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
+-            'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
+-        exec_command_and_wait_for_pattern(self,
+-            'cat /sys/class/tpm/tpm0/pcr-sha256/0',
+-            'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0');
+-
+-        self.do_test_arm_aspeed_buildroot_poweroff()
+-
+-    def do_test_arm_aspeed_sdk_start(self, image):
+-        self.require_netdev('user')
+-        self.vm.set_console()
+-        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
+-                         '-net', 'nic', '-net', 'user', '-snapshot')
+-        self.vm.launch()
+-
+-        self.wait_for_console_pattern('U-Boot 2019.04')
+-        self.wait_for_console_pattern('## Loading kernel from FIT Image')
+-        self.wait_for_console_pattern('Starting kernel ...')
+-
+-    ASSET_SDK_V806_AST2600_A2 = Asset(
+-        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
+-        '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
+-
+-    def test_arm_ast2600_evb_sdk(self):
+-        self.set_machine('ast2600-evb')
+-
+-        image_path = self.ASSET_SDK_V806_AST2600_A2.fetch()
+-
+-        archive_extract(image_path, self.workdir)
+-
+-        self.vm.add_args('-device',
+-            'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test');
+-        self.vm.add_args('-device',
+-            'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
+-        self.do_test_arm_aspeed_sdk_start(
+-            self.workdir + '/ast2600-a2/image-bmc')
+-
+-        self.wait_for_console_pattern('ast2600-a2 login:')
+-
+-        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+-        exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#')
+-
+-        exec_command_and_wait_for_pattern(self,
+-            'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
+-            'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
+-        exec_command_and_wait_for_pattern(self,
+-             'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
+-        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+-                    property='temperature', value=18000);
+-        exec_command_and_wait_for_pattern(self,
+-             'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
+-
+-        exec_command_and_wait_for_pattern(self,
+-             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device',
+-             'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
+-        year = time.strftime("%Y")
+-        exec_command_and_wait_for_pattern(self,
+-             '/sbin/hwclock -f /dev/rtc1', year);
+-
+-
+ class AST2x00MachineMMC(LinuxKernelTest):
+     ASSET_RAINIER_EMMC = Asset(
+diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional/test_arm_aspeed_ast2600.py
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/tests/functional/test_arm_aspeed_ast2600.py
+@@ -XXX,XX +XXX,XX @@
++#!/usr/bin/env python3
++#
++# Functional test that boots the ASPEED machines
++#
++# SPDX-License-Identifier: GPL-2.0-or-later
++
++import os
++import time
++import tempfile
++import subprocess
++
++from qemu_test import Asset
++from aspeed import AspeedTest
++from qemu_test import exec_command_and_wait_for_pattern
++from qemu_test import has_cmd
++from qemu_test.utils import archive_extract
++from unittest import skipUnless
++
++class AST2600Machine(AspeedTest):
++
++    ASSET_BR2_202311_AST2600_FLASH = Asset(
++        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
++         'images/ast2600-evb/buildroot-2023.11/flash.img'),
++        'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
++
++    def test_arm_ast2600_evb_buildroot(self):
++        self.set_machine('ast2600-evb')
++
++        image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch()
++
++        self.vm.add_args('-device',
++                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
++        self.vm.add_args('-device',
++                         'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
++        self.vm.add_args('-device',
++                         'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
++        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
++                                                'ast2600-evb login:')
++
++        exec_command_and_wait_for_pattern(self,
++             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
++             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
++        exec_command_and_wait_for_pattern(self,
++                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
++        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
++                    property='temperature', value=18000);
++        exec_command_and_wait_for_pattern(self,
++                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
++
++        exec_command_and_wait_for_pattern(self,
++             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
++             'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
++        year = time.strftime("%Y")
++        exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
++
++        exec_command_and_wait_for_pattern(self,
++             'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
++             'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64');
++        exec_command_and_wait_for_pattern(self,
++             'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
++        exec_command_and_wait_for_pattern(self,
++             'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
++             '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
++        self.do_test_arm_aspeed_buildroot_poweroff()
++
++    ASSET_BR2_202302_AST2600_TPM_FLASH = Asset(
++        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
++         'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
++        'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
++
++    @skipUnless(*has_cmd('swtpm'))
++    def test_arm_ast2600_evb_buildroot_tpm(self):
++        self.set_machine('ast2600-evb')
++
++        image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
++
++        tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_")
++        socket = os.path.join(tpmstate_dir.name, 'swtpm-socket')
++
++        # We must put the TPM state dir in /tmp/, not the build dir,
++        # because some distros use AppArmor to lock down swtpm and
++        # restrict the set of locations it can access files in.
++        subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
++                        '--tpmstate', f'dir={tpmstate_dir.name}',
++                        '--ctrl', f'type=unixio,path={socket}'])
++
++        self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
++        self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
++        self.vm.add_args('-device',
++                         'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
++        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
++
++        exec_command_and_wait_for_pattern(self,
++            'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
++            'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
++        exec_command_and_wait_for_pattern(self,
++            'cat /sys/class/tpm/tpm0/pcr-sha256/0',
++            'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0');
++
++        self.do_test_arm_aspeed_buildroot_poweroff()
++
++    ASSET_SDK_V806_AST2600_A2 = Asset(
++        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
++        '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
++
++    def test_arm_ast2600_evb_sdk(self):
++        self.set_machine('ast2600-evb')
++
++        image_path = self.ASSET_SDK_V806_AST2600_A2.fetch()
++
++        archive_extract(image_path, self.workdir)
++
++        self.vm.add_args('-device',
++            'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test');
++        self.vm.add_args('-device',
++            'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
++        self.do_test_arm_aspeed_sdk_start(
++            self.workdir + '/ast2600-a2/image-bmc')
++
++        self.wait_for_console_pattern('ast2600-a2 login:')
++
++        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
++        exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#')
++
++        exec_command_and_wait_for_pattern(self,
++            'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
++            'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
++        exec_command_and_wait_for_pattern(self,
++             'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
++        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
++                    property='temperature', value=18000);
++        exec_command_and_wait_for_pattern(self,
++             'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
++
++        exec_command_and_wait_for_pattern(self,
++             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device',
++             'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
++        year = time.strftime("%Y")
++        exec_command_and_wait_for_pattern(self,
++             '/sbin/hwclock -f /dev/rtc1', year);
++
++if __name__ == '__main__':
++    AspeedTest.main()
+--
+.47.1

-New patch
+[PULL 13/24] tests/functional: Introduce a specific test for rainier-bmc machine
+This simply moves the rainier-bmc test to a new test file. No changes
+in the test. The test_arm_aspeed.py is deleted.
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Link: https://lore.kernel.org/r/20241206131132.520911-7-clg@redhat.com
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
+---
+ tests/functional/meson.build                  |  4 ++--
+ ...m_aspeed.py => test_arm_aspeed_rainier.py} | 22 +++++--------------
+files changed, 7 insertions(+), 19 deletions(-)
+ rename tests/functional/{test_arm_aspeed.py => test_arm_aspeed_rainier.py} (71%)
+ mode change 100755 => 100644
+diff --git a/tests/functional/meson.build b/tests/functional/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/functional/meson.build
++++ b/tests/functional/meson.build
+@@ -XXX,XX +XXX,XX @@ test_timeouts = {
+   'arm_aspeed_romulus' : 120,
+   'arm_aspeed_ast2500' : 480,
+   'arm_aspeed_ast2600' : 720,
+-  'arm_aspeed' : 600,
++  'arm_aspeed_rainier' : 240,
+   'arm_bpim2u' : 500,
+   'arm_collie' : 180,
+   'arm_orangepi' : 540,
+@@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [
+ ]
+ tests_arm_system_thorough = [
+-  'arm_aspeed',
+   'arm_aspeed_ast1030',
+   'arm_aspeed_palmetto',
+   'arm_aspeed_romulus',
+   'arm_aspeed_ast2500',
+   'arm_aspeed_ast2600',
++  'arm_aspeed_rainier',
+   'arm_bpim2u',
+   'arm_canona1100',
+   'arm_collie',
+diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed_rainier.py
+old mode 100755
+new mode 100644
+similarity index 71%
+rename from tests/functional/test_arm_aspeed.py
+rename to tests/functional/test_arm_aspeed_rainier.py
+index XXXXXXX..XXXXXXX
+--- a/tests/functional/test_arm_aspeed.py
++++ b/tests/functional/test_arm_aspeed_rainier.py
+@@ -XXX,XX +XXX,XX @@
+ #!/usr/bin/env python3
+ #
+-# Functional test that boots the ASPEED SoCs with firmware
+-#
+-# Copyright (C) 2022 ASPEED Technology Inc
++# Functional test that boots the ASPEED machines
+ #
+ # SPDX-License-Identifier: GPL-2.0-or-later
+-import os
+-import time
+-import subprocess
+-import tempfile
+-
+-from qemu_test import LinuxKernelTest, Asset
+-from qemu_test import exec_command_and_wait_for_pattern
+-from qemu_test import interrupt_interactive_console_until_pattern
+-from qemu_test import has_cmd
+-from qemu_test.utils import archive_extract
+-from zipfile import ZipFile
+-from unittest import skipUnless
++from qemu_test import Asset
++from aspeed import AspeedTest
+-class AST2x00MachineMMC(LinuxKernelTest):
++class RainierMachine(AspeedTest):
+     ASSET_RAINIER_EMMC = Asset(
+         ('https://fileserver.linaro.org/s/B6pJTwWEkzSDi36/download/'
+@@ -XXX,XX +XXX,XX @@ def test_arm_aspeed_emmc_boot(self):
+         self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterprise')
+ if __name__ == '__main__':
+-    LinuxKernelTest.main()
++    AspeedTest.main()
+--
+.47.1

-[PULL 16/16] arm/aspeed: Replace mx25l25635e chip model
+[PULL 14/24] tests/functional: Move debian boot test from avocado
-A mx25l25635f chip model is generally found on these machines. It's
+This simply moves the debian boot test from the avocado testsuite to
-newer and uses 4B opcodes which is better to exercise the support in
+the new functional testsuite. No changes in the test.
 the Linux kernel.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
-Message-Id: <20220722063602.128144-9-clg@kaod.org>
+Link: https://lore.kernel.org/r/20241206131132.520911-8-clg@redhat.com
-Message-Id: <20221013161241.2805140-11-clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 6 +++---
+ tests/avocado/boot_linux_console.py         | 26 ---------------------
-file changed, 3 insertions(+), 3 deletions(-)
+ tests/functional/test_arm_aspeed_rainier.py | 24 +++++++++++++++++++
 files changed, 24 insertions(+), 26 deletions(-)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
+--- a/tests/avocado/boot_linux_console.py
-+++ b/hw/arm/aspeed.c
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ def test_arm_quanta_gsj_initrd(self):
-     amc->soc_name  = "ast2400-a1";
+         self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
-     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
+         self.wait_for_console_pattern(
-     amc->fmc_model = "n25q256a";
+                 'Give root password for system maintenance')
--    amc->spi_model = "mx25l25635e";
+-
-+    amc->spi_model = "mx25l25635f";
+-    def test_arm_ast2600_debian(self):
-     amc->num_cs    = 1;
+-        """
-     amc->i2c_init  = palmetto_bmc_i2c_init;
+-        :avocado: tags=arch:arm
-     mc->default_ram_size       = 256 * MiB;
+-        :avocado: tags=machine:rainier-bmc
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
+-        """
-     amc->soc_name  = "ast2500-a1";
+-        deb_url = ('http://snapshot.debian.org/archive/debian/'
-     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
+-                   '20220606T211338Z/'
-     amc->fmc_model = "mx25l25635e";
+-                   'pool/main/l/linux/'
--    amc->spi_model = "mx25l25635e";
+-                   'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
-+    amc->spi_model = "mx25l25635f";
+-        deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
-     amc->num_cs    = 1;
+-        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
-     amc->i2c_init  = ast2500_evb_i2c_init;
+-                                    algorithm='sha256')
-     mc->default_ram_size       = 512 * MiB;
+-        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
+-        dtb_path = self.extract_from_deb(deb_path,
-     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
+-                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
-     amc->soc_name  = "ast2500-a1";
+-
-     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
+-        self.vm.set_console()
--    amc->fmc_model = "mx25l25635e";
+-        self.vm.add_args('-kernel', kernel_path,
-+    amc->fmc_model = "mx25l25635f";
+-                         '-dtb', dtb_path,
-     amc->spi_model = "mx66l1g45g";
+-                         '-net', 'nic')
-     amc->num_cs    = 2;
+-        self.vm.launch()
-     amc->i2c_init  = witherspoon_bmc_i2c_init;
+-        self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00")
 -        self.wait_for_console_pattern("SMP: Total of 2 processors activated")
 -        self.wait_for_console_pattern("No filesystem could mount root")
 -
 diff --git a/tests/functional/test_arm_aspeed_rainier.py b/tests/functional/test_arm_aspeed_rainier.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/functional/test_arm_aspeed_rainier.py
 +++ b/tests/functional/test_arm_aspeed_rainier.py
@@ -XXX,XX +XXX,XX @@ def test_arm_aspeed_emmc_boot(self):
          self.wait_for_console_pattern('mmcblk0: p1 p2 p3 p4 p5 p6 p7')
          self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterprise')
 +    ASSET_DEBIAN_LINUX_ARMHF_DEB = Asset(
 +            ('http://snapshot.debian.org/archive/debian/20220606T211338Z/pool/main/l/linux/linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb'),
 +        '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e')
 +
 +    def test_arm_debian_kernel_boot(self):
 +        self.set_machine('rainier-bmc')
 +
 +        deb_path = self.ASSET_DEBIAN_LINUX_ARMHF_DEB.fetch()
 +
 +        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
 +        dtb_path = self.extract_from_deb(deb_path,
 +                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
 +
 +        self.vm.set_console()
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-dtb', dtb_path,
 +                         '-net', 'nic')
 +        self.vm.launch()
 +
 +        self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00")
 +        self.wait_for_console_pattern("SMP: Total of 2 processors activated")
 +        self.wait_for_console_pattern("No filesystem could mount root")
 +
 +
  if __name__ == '__main__':
      AspeedTest.main()
 --
-.37.3
+.47.1

-[PULL 13/16] m25p80: Add the w25q256 SFPD table
+[PULL 15/24] test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function
-The SFDP table size is 0x100 bytes long. Only the mandatory table for
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 basic features is available at byte 0x80.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+So far, the test cases are used for testing SMC model with AST2400 BMC.
-Message-Id: <20220722063602.128144-7-clg@kaod.org>
+However, AST2400 is end off live and ASPEED is no longer support this SOC.
-Message-Id: <20221013161241.2805140-8-clg@kaod.org>
+To test SMC model for AST2500, AST2600 and AST1030, move the test cases
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+from main to test_palmetto_bmc function.
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-2-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ tests/qtest/aspeed_smc-test.c | 16 ++++++++++++----
- hw/block/m25p80.c      |  3 ++-
+file changed, 12 insertions(+), 4 deletions(-)
  hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
 files changed, 44 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
- uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
+     flash_reset();
- uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+ }
-+uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+-int main(int argc, char **argv)
 +static int test_palmetto_bmc(void)
  {
      g_autofree char *tmp_path = NULL;
      int ret;
      int fd;
 -    g_test_init(&argc, &argv, NULL);
 -
      fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
      g_assert(fd >= 0);
      ret = ftruncate(fd, FLASH_SIZE);
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
      flash_reset();
      ret = g_test_run();
 -
      qtest_quit(global_qtest);
      unlink(tmp_path);
 +
- #endif
++    return ret;
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++}
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80.c
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
      { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
      { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
 -    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
 +    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
 +      .sfdp_read = m25p80_sfdp_w25q256 },
      { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
      { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
  };
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx66l1g45g[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(mx66l1g45g);
 +
-+/*
++int main(int argc, char **argv)
-+ * Windbond
++{
-+ */
++    int ret;
 +
-+static const uint8_t sfdp_w25q256[] = {
++    g_test_init(&argc, &argv, NULL);
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
++    ret = test_palmetto_bmc();
-+    0x00, 0x00, 0x01, 0x09, 0x80, 0x00, 0x00, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     return ret;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ }
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
 +    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
 +    0xff, 0xff, 0x21, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(w25q256);
 --
-.37.3
+.47.1

-[PULL 03/16] ssi: cache SSIPeripheralClass to avoid GET_CLASS()
+[PULL 16/24] test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-Investigating why some BMC models are so slow compared to a plain ARM
+Currently, these test cases are only used for testing fmc_cs0 for AST2400.
-virt machines I did some profiling of:
+To test others BMC SOCs, introduces a new TestData structure.
 Users can set the spi base address, flash base address, jedesc id and so on
 for different BMC SOCs and flash model testing.
-  ./qemu-system-arm -M romulus-bmc -nic user \
+Introduce new helper functions to make the test case more readable.
     -drive
     file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
     -nographic -serial mon:stdio
-And saw that object_class_dynamic_cast_assert was dominating the
+Set spi base address 0x1E620000, flash_base address 0x20000000
-profile times. We have a number of cases in this model of the SSI bus.
+and jedec id 0x20ba19 for fmc_cs0 with n25q256a flash for AST2400
-As the class is static once the object is created we just cache it and
+SMC model testing.
 use it instead of the dynamic case macros.
-Profiling against:
+To pass the TestData into the test case, replace qtest_add_func with
 qtest_add_data_func.
-  ./tests/venv/bin/avocado run \
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-    tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-3-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
  tests/qtest/aspeed_smc-test.c | 546 +++++++++++++++++++---------------
 file changed, 299 insertions(+), 247 deletions(-)
-Before: 35.565 s ±  0.087 s
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 After: 15.713 s ±  0.287 s
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Cc: Cédric Le Goater <clg@kaod.org>
 Tested-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org>
 Message-Id: <20220923084803.498337-6-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  include/hw/ssi/ssi.h |  3 +++
  hw/ssi/ssi.c         | 18 ++++++++----------
 files changed, 11 insertions(+), 10 deletions(-)
 diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/ssi.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/include/hw/ssi/ssi.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ struct SSIPeripheralClass {
+@@ -XXX,XX +XXX,XX @@
- struct SSIPeripheral {
+ #define   CTRL_USERMODE        0x3
-     DeviceState parent_obj;
+ #define SR_WEL BIT(1)
-+    /* cache the class */
+-#define ASPEED_FMC_BASE    0x1E620000
-+    SSIPeripheralClass *spc;
+-#define ASPEED_FLASH_BASE  0x20000000
 -
  /*
   * Flash commands
   */
@@ -XXX,XX +XXX,XX @@ enum {
      ERASE_SECTOR = 0xd8,
  };
 -#define FLASH_JEDEC         0x20ba19  /* n25q256a */
 -#define FLASH_SIZE          (32 * 1024 * 1024)
 -
  #define FLASH_PAGE_SIZE           256
 +typedef struct TestData {
 +    QTestState *s;
 +    uint64_t spi_base;
 +    uint64_t flash_base;
 +    uint32_t jedec_id;
 +    char *tmp_path;
 +} TestData;
 +
-     /* Chip select state */
+ /*
-     bool cs;
+  * Use an explicit bswap for the values read/wrote to the flash region
- };
+  * as they are BE and the Aspeed CPU is LE.
-diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t make_be32(uint32_t data)
-index XXXXXXX..XXXXXXX 100644
+     return bswap32(data);
---- a/hw/ssi/ssi.c
+ }
-+++ b/hw/ssi/ssi.c
-@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
+-static void spi_conf(uint32_t value)
-     bool cs = !!level;
++static inline void spi_writel(const TestData *data, uint64_t offset,
-     assert(n == 0);
++                              uint32_t value)
-     if (s->cs != cs) {
++{
--        SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
++    qtest_writel(data->s, data->spi_base + offset, value);
--        if (ssc->set_cs) {
++}
--            ssc->set_cs(s, cs);
++
-+        if (s->spc->set_cs) {
++static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
-+            s->spc->set_cs(s, cs);
++{
 +    return qtest_readl(data->s, data->spi_base + offset);
 +}
 +
 +static inline void flash_writeb(const TestData *data, uint64_t offset,
 +                                uint8_t value)
 +{
 +    qtest_writeb(data->s, data->flash_base + offset, value);
 +}
 +
 +static inline void flash_writel(const TestData *data, uint64_t offset,
 +                                uint32_t value)
 +{
 +    qtest_writel(data->s, data->flash_base + offset, value);
 +}
 +
 +static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
  {
 -    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
 +    return qtest_readb(data->s, data->flash_base + offset);
 +}
 +
 +static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
 +{
 +    return qtest_readl(data->s, data->flash_base + offset);
 +}
 +
 +static void spi_conf(const TestData *data, uint32_t value)
 +{
 +    uint32_t conf = spi_readl(data, R_CONF);
      conf |= value;
 -    writel(ASPEED_FMC_BASE + R_CONF, conf);
 +    spi_writel(data, R_CONF, conf);
  }
 -static void spi_conf_remove(uint32_t value)
 +static void spi_conf_remove(const TestData *data, uint32_t value)
  {
 -    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
 +    uint32_t conf = spi_readl(data, R_CONF);
      conf &= ~value;
 -    writel(ASPEED_FMC_BASE + R_CONF, conf);
 +    spi_writel(data, R_CONF, conf);
  }
 -static void spi_ce_ctrl(uint32_t value)
 +static void spi_ce_ctrl(const TestData *data, uint32_t value)
  {
 -    uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);
 +    uint32_t conf = spi_readl(data, R_CE_CTRL);
      conf |= value;
 -    writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
 +    spi_writel(data, R_CE_CTRL, conf);
  }
 -static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
 +static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
  {
 -    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
 +    uint32_t ctrl = spi_readl(data, R_CTRL0);
      ctrl &= ~(CTRL_USERMODE | 0xff << 16);
      ctrl |= mode | (cmd << 16);
 -    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
 +    spi_writel(data, R_CTRL0, ctrl);
  }
 -static void spi_ctrl_start_user(void)
 +static void spi_ctrl_start_user(const TestData *data)
  {
 -    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
 +    uint32_t ctrl = spi_readl(data, R_CTRL0);
      ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
 +    spi_writel(data, R_CTRL0, ctrl);
      ctrl &= ~CTRL_CE_STOP_ACTIVE;
 -    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
 +    spi_writel(data, R_CTRL0, ctrl);
  }
 -static void spi_ctrl_stop_user(void)
 +static void spi_ctrl_stop_user(const TestData *data)
  {
 -    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
 +    uint32_t ctrl = spi_readl(data, R_CTRL0);
      ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
 +    spi_writel(data, R_CTRL0, ctrl);
  }
 -static void flash_reset(void)
 +static void flash_reset(const TestData *data)
  {
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(data, CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
 -    writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, BULK_ERASE);
 -    writeb(ASPEED_FLASH_BASE, WRDI);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(data);
 +    flash_writeb(data, 0, RESET_ENABLE);
 +    flash_writeb(data, 0, RESET_MEMORY);
 +    flash_writeb(data, 0, WREN);
 +    flash_writeb(data, 0, BULK_ERASE);
 +    flash_writeb(data, 0, WRDI);
 +    spi_ctrl_stop_user(data);
 -    spi_conf_remove(CONF_ENABLE_W0);
 +    spi_conf_remove(data, CONF_ENABLE_W0);
  }
 -static void test_read_jedec(void)
 +static void test_read_jedec(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t jedec = 0x0;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, JEDEC_READ);
 -    jedec |= readb(ASPEED_FLASH_BASE) << 16;
 -    jedec |= readb(ASPEED_FLASH_BASE) << 8;
 -    jedec |= readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, JEDEC_READ);
 +    jedec |= flash_readb(test_data, 0) << 16;
 +    jedec |= flash_readb(test_data, 0) << 8;
 +    jedec |= flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 -    flash_reset();
 +    flash_reset(test_data);
 -    g_assert_cmphex(jedec, ==, FLASH_JEDEC);
 +    g_assert_cmphex(jedec, ==, test_data->jedec_id);
  }
 -static void read_page(uint32_t addr, uint32_t *page)
 +static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
  {
      int i;
 -    spi_ctrl_start_user();
 +    spi_ctrl_start_user(data);
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, READ);
 -    writel(ASPEED_FLASH_BASE, make_be32(addr));
 +    flash_writeb(data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(data, 0, READ);
 +    flash_writel(data, 0, make_be32(addr));
      /* Continuous read are supported */
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        page[i] = make_be32(readl(ASPEED_FLASH_BASE));
 +        page[i] = make_be32(flash_readl(data, 0));
      }
 -    spi_ctrl_stop_user();
 +    spi_ctrl_stop_user(data);
  }
 -static void read_page_mem(uint32_t addr, uint32_t *page)
 +static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page)
  {
      int i;
      /* move out USER mode to use direct reads from the AHB bus */
 -    spi_ctrl_setmode(CTRL_READMODE, READ);
 +    spi_ctrl_setmode(data, CTRL_READMODE, READ);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
 +        page[i] = make_be32(flash_readl(data, addr + i * 4));
      }
  }
 -static void write_page_mem(uint32_t addr, uint32_t write_value)
 +static void write_page_mem(const TestData *data, uint32_t addr,
 +                           uint32_t write_value)
  {
 -    spi_ctrl_setmode(CTRL_WRITEMODE, PP);
 +    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
      for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
 +        flash_writel(data, addr + i * 4, write_value);
      }
  }
 -static void assert_page_mem(uint32_t addr, uint32_t expected_value)
 +static void assert_page_mem(const TestData *data, uint32_t addr,
 +                            uint32_t expected_value)
  {
      uint32_t page[FLASH_PAGE_SIZE / 4];
 -    read_page_mem(addr, page);
 +    read_page_mem(data, addr, page);
      for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, expected_value);
      }
  }
 -static void test_erase_sector(void)
 +static void test_erase_sector(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
      /*
       * Previous page should be full of 0xffs after backend is
       * initialized
       */
 -    read_page(some_page_addr - FLASH_PAGE_SIZE, page);
 +    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, PP);
 -    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
      /* Fill the page with its own addresses */
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
 +        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
      }
 -    spi_ctrl_stop_user();
 +    spi_ctrl_stop_user(test_data);
      /* Check the page is correctly written */
 -    read_page(some_page_addr, page);
 +    read_page(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
      }
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
 -    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, ERASE_SECTOR);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
 +    spi_ctrl_stop_user(test_data);
      /* Check the page is erased */
 -    read_page(some_page_addr, page);
 +    read_page(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_erase_all(void)
 +static void test_erase_all(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
      /*
       * Previous page should be full of 0xffs after backend is
       * initialized
       */
 -    read_page(some_page_addr - FLASH_PAGE_SIZE, page);
 +    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, PP);
 -    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
      /* Fill the page with its own addresses */
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
 +        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
      }
 -    spi_ctrl_stop_user();
 +    spi_ctrl_stop_user(test_data);
      /* Check the page is correctly written */
 -    read_page(some_page_addr, page);
 +    read_page(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
      }
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, BULK_ERASE);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, BULK_ERASE);
 +    spi_ctrl_stop_user(test_data);
      /* Check the page is erased */
 -    read_page(some_page_addr, page);
 +    read_page(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_write_page(void)
 +static void test_write_page(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
      uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, PP);
 -    writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(my_page_addr));
      /* Fill the page with its own addresses */
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
      }
 -    spi_ctrl_stop_user();
 +    spi_ctrl_stop_user(test_data);
      /* Check what was written */
 -    read_page(my_page_addr, page);
 +    read_page(test_data, my_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
      }
      /* Check some other page. It should be full of 0xff */
 -    read_page(some_page_addr, page);
 +    read_page(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_read_page_mem(void)
 +static void test_read_page_mem(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
      uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
      uint32_t page[FLASH_PAGE_SIZE / 4];
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(void)
       * Enable 4BYTE mode for controller. This is should be strapped by
       * HW for CE0 anyhow.
       */
 -    spi_ce_ctrl(1 << CRTL_EXTENDED0);
 +    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
      /* Enable 4BYTE mode for flash. */
 -    spi_conf(CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, PP);
 -    writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
 +    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(my_page_addr));
      /* Fill the page with its own addresses */
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
      }
 -    spi_ctrl_stop_user();
 -    spi_conf_remove(CONF_ENABLE_W0);
 +    spi_ctrl_stop_user(test_data);
 +    spi_conf_remove(test_data, CONF_ENABLE_W0);
      /* Check what was written */
 -    read_page_mem(my_page_addr, page);
 +    read_page_mem(test_data, my_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
      }
      /* Check some other page. It should be full of 0xff */
 -    read_page_mem(some_page_addr, page);
 +    read_page_mem(test_data, some_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, 0xffffffff);
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_write_page_mem(void)
 +static void test_write_page_mem(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE;
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
@@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(void)
       * Enable 4BYTE mode for controller. This is should be strapped by
       * HW for CE0 anyhow.
       */
 -    spi_ce_ctrl(1 << CRTL_EXTENDED0);
 +    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
      /* Enable 4BYTE mode for flash. */
 -    spi_conf(CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    spi_ctrl_stop_user();
 +    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    spi_ctrl_stop_user(test_data);
      /* move out USER mode to use direct writes to the AHB bus */
 -    spi_ctrl_setmode(CTRL_WRITEMODE, PP);
 +    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
 +        flash_writel(test_data, my_page_addr + i * 4,
                 make_be32(my_page_addr + i * 4));
      }
      /* Check what was written */
 -    read_page_mem(my_page_addr, page);
 +    read_page_mem(test_data, my_page_addr, page);
      for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
          g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_read_status_reg(void)
 +static void test_read_status_reg(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint8_t r;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SR_WEL, ==, 0);
      g_assert(!qtest_qom_get_bool
 -            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
      g_assert(qtest_qom_get_bool
 -            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WRDI);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WRDI);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SR_WEL, ==, 0);
      g_assert(!qtest_qom_get_bool
 -            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_status_reg_write_protection(void)
 +static void test_status_reg_write_protection(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint8_t r;
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
      /* default case: WP# is high and SRWD is low -> status register writable */
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
      /* test ability to write SRWD */
 -    writeb(ASPEED_FLASH_BASE, WRSR);
 -    writeb(ASPEED_FLASH_BASE, SRWD);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, SRWD);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SRWD, ==, SRWD);
      /* WP# high and SRWD high -> status register writable */
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
      /* test ability to write SRWD */
 -    writeb(ASPEED_FLASH_BASE, WRSR);
 -    writeb(ASPEED_FLASH_BASE, 0);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, 0);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SRWD, ==, 0);
      /* WP# low and SRWD low -> status register writable */
 -    qtest_set_irq_in(global_qtest,
 +    qtest_set_irq_in(test_data->s,
                       "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
      /* test ability to write SRWD */
 -    writeb(ASPEED_FLASH_BASE, WRSR);
 -    writeb(ASPEED_FLASH_BASE, SRWD);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, SRWD);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      g_assert_cmphex(r & SRWD, ==, SRWD);
      /* WP# low and SRWD high -> status register NOT writable */
 -    spi_ctrl_start_user();
 -    writeb(ASPEED_FLASH_BASE, WREN);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0 , WREN);
      /* test ability to write SRWD */
 -    writeb(ASPEED_FLASH_BASE, WRSR);
 -    writeb(ASPEED_FLASH_BASE, 0);
 -    writeb(ASPEED_FLASH_BASE, RDSR);
 -    r = readb(ASPEED_FLASH_BASE);
 -    spi_ctrl_stop_user();
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, 0);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
      /* write is not successful */
      g_assert_cmphex(r & SRWD, ==, SRWD);
 -    qtest_set_irq_in(global_qtest,
 +    qtest_set_irq_in(test_data->s,
                       "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static void test_write_block_protect(void)
 +static void test_write_block_protect(const void *data)
  {
 +    const TestData *test_data = (const TestData *)data;
      uint32_t sector_size = 65536;
      uint32_t n_sectors = 512;
 -    spi_ce_ctrl(1 << CRTL_EXTENDED0);
 -    spi_conf(CONF_ENABLE_W0);
 +    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 +    spi_conf(test_data, CONF_ENABLE_W0);
      uint32_t bp_bits = 0b0;
      for (int i = 0; i < 16; i++) {
          bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
 -        spi_ctrl_start_user();
 -        writeb(ASPEED_FLASH_BASE, WREN);
 -        writeb(ASPEED_FLASH_BASE, BULK_ERASE);
 -        writeb(ASPEED_FLASH_BASE, WREN);
 -        writeb(ASPEED_FLASH_BASE, WRSR);
 -        writeb(ASPEED_FLASH_BASE, bp_bits);
 -        writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
 -        writeb(ASPEED_FLASH_BASE, WREN);
 -        spi_ctrl_stop_user();
 +        spi_ctrl_start_user(test_data);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, BULK_ERASE);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, WRSR);
 +        flash_writeb(test_data, 0, bp_bits);
 +        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +        flash_writeb(test_data, 0, WREN);
 +        spi_ctrl_stop_user(test_data);
          uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
          uint32_t protection_start = n_sectors - num_protected_sectors;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(void)
          for (int sector = 0; sector < n_sectors; sector++) {
              uint32_t addr = sector * sector_size;
 -            assert_page_mem(addr, 0xffffffff);
 -            write_page_mem(addr, make_be32(0xabcdef12));
 +            assert_page_mem(test_data, addr, 0xffffffff);
 +            write_page_mem(test_data, addr, make_be32(0xabcdef12));
              uint32_t expected_value = protection_start <= sector
                                        && sector < protection_end
                                        ? 0xffffffff : 0xabcdef12;
 -            assert_page_mem(addr, expected_value);
 +            assert_page_mem(test_data, addr, expected_value);
          }
      }
-     s->cs = cs;
-@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
+-    flash_reset();
++    flash_reset(test_data);
- static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
+ }
- {
--    SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
+-static void test_write_block_protect_bottom_bit(void)
-+    SSIPeripheralClass *ssc = dev->spc;
++static void test_write_block_protect_bottom_bit(const void *data)
+ {
-     if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
++    const TestData *test_data = (const TestData *)data;
--            (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
+     uint32_t sector_size = 65536;
--            ssc->cs_polarity == SSI_CS_NONE) {
+     uint32_t n_sectors = 512;
-+        (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
-+        ssc->cs_polarity == SSI_CS_NONE) {
+-    spi_ce_ctrl(1 << CRTL_EXTENDED0);
-         return ssc->transfer(dev, val);
+-    spi_conf(CONF_ENABLE_W0);
-     }
++    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
-     return 0;
++    spi_conf(test_data, CONF_ENABLE_W0);
-@@ -XXX,XX +XXX,XX @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
-             ssc->cs_polarity != SSI_CS_NONE) {
+     /* top bottom bit is enabled */
-         qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
+     uint32_t bp_bits = 0b00100 << 3;
-     }
+@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
-+    s->spc = ssc;
+     for (int i = 0; i < 16; i++) {
+         bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
-     ssc->realize(s, errp);
- }
+-        spi_ctrl_start_user();
-@@ -XXX,XX +XXX,XX @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
+-        writeb(ASPEED_FLASH_BASE, WREN);
- {
+-        writeb(ASPEED_FLASH_BASE, BULK_ERASE);
-     BusState *b = BUS(bus);
+-        writeb(ASPEED_FLASH_BASE, WREN);
-     BusChild *kid;
+-        writeb(ASPEED_FLASH_BASE, WRSR);
--    SSIPeripheralClass *ssc;
+-        writeb(ASPEED_FLASH_BASE, bp_bits);
-     uint32_t r = 0;
+-        writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+-        writeb(ASPEED_FLASH_BASE, WREN);
-     QTAILQ_FOREACH(kid, &b->children, sibling) {
+-        spi_ctrl_stop_user();
--        SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
++        spi_ctrl_start_user(test_data);
--        ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
++        flash_writeb(test_data, 0, WREN);
--        r |= ssc->transfer_raw(peripheral, val);
++        flash_writeb(test_data, 0, BULK_ERASE);
-+        SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
++        flash_writeb(test_data, 0, WREN);
-+        r |= p->spc->transfer_raw(p, val);
++        flash_writeb(test_data, 0, WRSR);
-     }
++        flash_writeb(test_data, 0, bp_bits);
++        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-     return r;
++        flash_writeb(test_data, 0, WREN);
 +        spi_ctrl_stop_user(test_data);
          uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
          uint32_t protection_start = 0;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
          for (int sector = 0; sector < n_sectors; sector++) {
              uint32_t addr = sector * sector_size;
 -            assert_page_mem(addr, 0xffffffff);
 -            write_page_mem(addr, make_be32(0xabcdef12));
 +            assert_page_mem(test_data, addr, 0xffffffff);
 +            write_page_mem(test_data, addr, make_be32(0xabcdef12));
              uint32_t expected_value = protection_start <= sector
                                        && sector < protection_end
                                        ? 0xffffffff : 0xabcdef12;
 -            assert_page_mem(addr, expected_value);
 +            assert_page_mem(test_data, addr, expected_value);
          }
      }
 -    flash_reset();
 +    flash_reset(test_data);
  }
 -static int test_palmetto_bmc(void)
 +static void test_palmetto_bmc(TestData *data)
  {
 -    g_autofree char *tmp_path = NULL;
      int ret;
      int fd;
 -    fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
 +    fd = g_file_open_tmp("qtest.m25p80.n25q256a.XXXXXX", &data->tmp_path, NULL);
      g_assert(fd >= 0);
 -    ret = ftruncate(fd, FLASH_SIZE);
 +    ret = ftruncate(fd, 32 * 1024 * 1024);
      g_assert(ret == 0);
      close(fd);
 -    global_qtest = qtest_initf("-m 256 -machine palmetto-bmc "
 -                               "-drive file=%s,format=raw,if=mtd",
 -                               tmp_path);
 -
 -    qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec);
 -    qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector);
 -    qtest_add_func("/ast2400/smc/erase_all",  test_erase_all);
 -    qtest_add_func("/ast2400/smc/write_page", test_write_page);
 -    qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
 -    qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
 -    qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
 -    qtest_add_func("/ast2400/smc/status_reg_write_protection",
 -                   test_status_reg_write_protection);
 -    qtest_add_func("/ast2400/smc/write_block_protect",
 -                   test_write_block_protect);
 -    qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
 -                   test_write_block_protect_bottom_bit);
 -
 -    flash_reset();
 -    ret = g_test_run();
 -    qtest_quit(global_qtest);
 -    unlink(tmp_path);
 -
 -    return ret;
 +    data->s = qtest_initf("-m 256 -machine palmetto-bmc "
 +                          "-drive file=%s,format=raw,if=mtd",
 +                          data->tmp_path);
 +
 +    /* fmc cs0 with n25q256a flash */
 +    data->flash_base = 0x20000000;
 +    data->spi_base = 0x1E620000;
 +    data->jedec_id = 0x20ba19;
 +
 +    qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
 +    qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
 +    qtest_add_data_func("/ast2400/smc/erase_all",  data, test_erase_all);
 +    qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast2400/smc/read_page_mem",
 +                        data, test_read_page_mem);
 +    qtest_add_data_func("/ast2400/smc/write_page_mem",
 +                        data, test_write_page_mem);
 +    qtest_add_data_func("/ast2400/smc/read_status_reg",
 +                        data, test_read_status_reg);
 +    qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
 +                        data, test_status_reg_write_protection);
 +    qtest_add_data_func("/ast2400/smc/write_block_protect",
 +                        data, test_write_block_protect);
 +    qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
 +                        data, test_write_block_protect_bottom_bit);
  }
  int main(int argc, char **argv)
  {
 +    TestData palmetto_data;
      int ret;
      g_test_init(&argc, &argv, NULL);
 -    ret = test_palmetto_bmc();
 +    test_palmetto_bmc(&palmetto_data);
 +    ret = g_test_run();
 +
 +    qtest_quit(palmetto_data.s);
 +    unlink(palmetto_data.tmp_path);
      return ret;
  }
 --
-.37.3
+.47.1

-New patch
+[PULL 17/24] test/qtest/aspeed_smc-test: Support to test all CE pins
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 Currently, these test cases only support to test CE0. To test all CE pins,
 introduces new ce and node members in TestData structure. The ce member is used
 for saving the ce index and node member is used for saving the node path,
 respectively.
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-4-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
  tests/qtest/aspeed_smc-test.c | 77 ++++++++++++++++++-----------------
 file changed, 40 insertions(+), 37 deletions(-)
 diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/aspeed_smc-test.c
 +++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@
   * ASPEED SPI Controller registers
   */
  #define R_CONF              0x00
 -#define   CONF_ENABLE_W0       (1 << 16)
 +#define   CONF_ENABLE_W0       16
  #define R_CE_CTRL           0x04
  #define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
  #define R_CTRL0             0x10
 -#define   CTRL_CE_STOP_ACTIVE  (1 << 2)
 +#define   CTRL_CE_STOP_ACTIVE  BIT(2)
  #define   CTRL_READMODE        0x0
  #define   CTRL_FREADMODE       0x1
  #define   CTRL_WRITEMODE       0x2
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
      uint64_t flash_base;
      uint32_t jedec_id;
      char *tmp_path;
 +    uint8_t cs;
 +    const char *node;
  } TestData;
  /*
@@ -XXX,XX +XXX,XX @@ static void spi_ce_ctrl(const TestData *data, uint32_t value)
  static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
  {
 -    uint32_t ctrl = spi_readl(data, R_CTRL0);
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
      ctrl &= ~(CTRL_USERMODE | 0xff << 16);
      ctrl |= mode | (cmd << 16);
 -    spi_writel(data, R_CTRL0, ctrl);
 +    spi_writel(data, ctrl_reg, ctrl);
  }
  static void spi_ctrl_start_user(const TestData *data)
  {
 -    uint32_t ctrl = spi_readl(data, R_CTRL0);
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
      ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, R_CTRL0, ctrl);
 +    spi_writel(data, ctrl_reg, ctrl);
      ctrl &= ~CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, R_CTRL0, ctrl);
 +    spi_writel(data, ctrl_reg, ctrl);
  }
  static void spi_ctrl_stop_user(const TestData *data)
  {
 -    uint32_t ctrl = spi_readl(data, R_CTRL0);
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
      ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, R_CTRL0, ctrl);
 +    spi_writel(data, ctrl_reg, ctrl);
  }
  static void flash_reset(const TestData *data)
  {
 -    spi_conf(data, CONF_ENABLE_W0);
 +    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
      spi_ctrl_start_user(data);
      flash_writeb(data, 0, RESET_ENABLE);
@@ -XXX,XX +XXX,XX @@ static void flash_reset(const TestData *data)
      flash_writeb(data, 0, WRDI);
      spi_ctrl_stop_user(data);
 -    spi_conf_remove(data, CONF_ENABLE_W0);
 +    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
  }
  static void test_read_jedec(const void *data)
@@ -XXX,XX +XXX,XX @@ static void test_read_jedec(const void *data)
      const TestData *test_data = (const TestData *)data;
      uint32_t jedec = 0x0;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, JEDEC_READ);
@@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data)
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      /*
       * Previous page should be full of 0xffs after backend is
@@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data)
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      /*
       * Previous page should be full of 0xffs after backend is
@@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data)
      uint32_t page[FLASH_PAGE_SIZE / 4];
      int i;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, EN_4BYTE_ADDR);
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
      int i;
      /*
 -     * Enable 4BYTE mode for controller. This is should be strapped by
 -     * HW for CE0 anyhow.
 +     * Enable 4BYTE mode for controller.
       */
 -    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
      /* Enable 4BYTE mode for flash. */
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, EN_4BYTE_ADDR);
      flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
          flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
      }
      spi_ctrl_stop_user(test_data);
 -    spi_conf_remove(test_data, CONF_ENABLE_W0);
 +    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      /* Check what was written */
      read_page_mem(test_data, my_page_addr, page);
@@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(const void *data)
      int i;
      /*
 -     * Enable 4BYTE mode for controller. This is should be strapped by
 -     * HW for CE0 anyhow.
 +     * Enable 4BYTE mode for controller.
       */
 -    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
      /* Enable 4BYTE mode for flash. */
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, EN_4BYTE_ADDR);
      flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
      const TestData *test_data = (const TestData *)data;
      uint8_t r;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, RDSR);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
      g_assert_cmphex(r & SR_WEL, ==, 0);
      g_assert(!qtest_qom_get_bool
 -            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, test_data->node, "write-enable"));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
      g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
      g_assert(qtest_qom_get_bool
 -            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, test_data->node, "write-enable"));
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, WRDI);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
      g_assert_cmphex(r & SR_WEL, ==, 0);
      g_assert(!qtest_qom_get_bool
 -            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 +            (test_data->s, test_data->node, "write-enable"));
      flash_reset(test_data);
  }
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
      const TestData *test_data = (const TestData *)data;
      uint8_t r;
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      /* default case: WP# is high and SRWD is low -> status register writable */
      spi_ctrl_start_user(test_data);
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
      g_assert_cmphex(r & SRWD, ==, 0);
      /* WP# low and SRWD low -> status register writable */
 -    qtest_set_irq_in(test_data->s,
 -                     "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
 +    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
      spi_ctrl_start_user(test_data);
      flash_writeb(test_data, 0, WREN);
      /* test ability to write SRWD */
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
      /* write is not successful */
      g_assert_cmphex(r & SRWD, ==, SRWD);
 -    qtest_set_irq_in(test_data->s,
 -                     "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
 +    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
      flash_reset(test_data);
  }
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(const void *data)
      uint32_t sector_size = 65536;
      uint32_t n_sectors = 512;
 -    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      uint32_t bp_bits = 0b0;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data)
      uint32_t sector_size = 65536;
      uint32_t n_sectors = 512;
 -    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 -    spi_conf(test_data, CONF_ENABLE_W0);
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
      /* top bottom bit is enabled */
      uint32_t bp_bits = 0b00100 << 3;
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
      data->flash_base = 0x20000000;
      data->spi_base = 0x1E620000;
      data->jedec_id = 0x20ba19;
 +    data->cs = 0;
 +    data->node = "/machine/soc/fmc/ssi.0/child[0]";
      qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
      qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
 --
 .47.1

-[PULL 12/16] m25p80: Add the mx66l1g45g SFDP table
+[PULL 18/24] test/qtest/aspeed_smc-test: Introducing a "page_addr" data field
-The SFDP table size is 0x200 bytes long. The mandatory table for basic
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 features is available at byte 0x30 plus some more Macronix specific
 tables.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Currently, these test cases used the hardcode offset 0x1400000 (0x14000 * 256)
-Message-Id: <20220722063602.128144-6-clg@kaod.org>
+which was beyond the 16MB flash size for flash page read/write command testing.
-Message-Id: <20221013161241.2805140-7-clg@kaod.org>
+However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+is 1MB. To test SoC flash models, introduces a new page_addr member in TestData
 structure, so users can set the offset for flash page read/write command
 testing.
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-5-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h |  2 +-
+ tests/qtest/aspeed_smc-test.c | 17 ++++++++++-------
- hw/block/m25p80.c      |  3 +-
+file changed, 10 insertions(+), 7 deletions(-)
  hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 files changed, 71 insertions(+), 2 deletions(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
+     char *tmp_path;
- uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+     uint8_t cs;
- uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
+     const char *node;
--
++    uint32_t page_addr;
-+uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+ } TestData;
- #endif
+ /*
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+@@ -XXX,XX +XXX,XX @@ static void assert_page_mem(const TestData *data, uint32_t addr,
-index XXXXXXX..XXXXXXX 100644
+ static void test_erase_sector(const void *data)
---- a/hw/block/m25p80.c
+ {
-+++ b/hw/block/m25p80.c
+     const TestData *test_data = (const TestData *)data;
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+-    uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
-     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
++    uint32_t some_page_addr = test_data->page_addr;
-     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
+     uint32_t page[FLASH_PAGE_SIZE / 4];
-     { INFO("mx66u1g45g",  0xc2253b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
+     int i;
--    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
-+    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K),
+@@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data)
-+      .sfdp_read = m25p80_sfdp_mx66l1g45g },
+ static void test_erase_all(const void *data)
+ {
-     /* Micron */
+     const TestData *test_data = (const TestData *)data;
-     { INFO("n25q032a11",  0x20bb16,      0,  64 << 10,  64, ER_4K) },
+-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
++    uint32_t some_page_addr = test_data->page_addr;
-index XXXXXXX..XXXXXXX 100644
+     uint32_t page[FLASH_PAGE_SIZE / 4];
---- a/hw/block/m25p80_sfdp.c
+     int i;
-+++ b/hw/block/m25p80_sfdp.c
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635f[] = {
+@@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data)
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ static void test_write_page(const void *data)
- };
+ {
- define_sfdp_read(mx25l25635f);
+     const TestData *test_data = (const TestData *)data;
-+
+-    uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
-+static const uint8_t sfdp_mx66l1g45g[] = {
+-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
-+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xff,
++    uint32_t my_page_addr = test_data->page_addr;
-+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
++    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-+    0xc2, 0x00, 0x01, 0x04, 0x10, 0x01, 0x00, 0xff,
+     uint32_t page[FLASH_PAGE_SIZE / 4];
-+    0x84, 0x00, 0x01, 0x02, 0xc0, 0x00, 0x00, 0xff,
+     int i;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+@@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data)
-+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+ static void test_read_page_mem(const void *data)
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+ {
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+     const TestData *test_data = (const TestData *)data;
-+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+-    uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
-+    0x10, 0xd8, 0x00, 0xff, 0xd6, 0x49, 0xc5, 0x00,
+-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
-+    0x85, 0xdf, 0x04, 0xe3, 0x44, 0x03, 0x67, 0x38,
++    uint32_t my_page_addr = test_data->page_addr;
-+    0x30, 0xb0, 0x30, 0xb0, 0xf7, 0xbd, 0xd5, 0x5c,
++    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-+    0x4a, 0x9e, 0x29, 0xff, 0xf0, 0x50, 0xf9, 0x85,
+     uint32_t page[FLASH_PAGE_SIZE / 4];
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     int i;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ static void test_write_page_mem(const void *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ {
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     const TestData *test_data = (const TestData *)data;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+-    uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    uint32_t my_page_addr = test_data->page_addr;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     uint32_t page[FLASH_PAGE_SIZE / 4];
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     int i;
-+    0x7f, 0xef, 0xff, 0xff, 0x21, 0x5c, 0xdc, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     data->jedec_id = 0x20ba19;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     data->cs = 0;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     data->node = "/machine/soc/fmc/ssi.0/child[0]";
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /* beyond 16MB */
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
 +    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
 +    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xc2, 0xf5, 0x08, 0x00, 0x0c, 0x04, 0x08, 0x08,
 +    0x01, 0x00, 0x19, 0x0f, 0x01, 0x01, 0x06, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(mx66l1g45g);
 --
-.37.3
+.47.1

-[PULL 11/16] m25p80: Add the mx25l25635f SFPD table
+[PULL 19/24] test/qtest/aspeed_smc-test: Support to test AST2500
-The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 mx25l25635f has more capabilities reported in the SFDP table. Support
 for 4B opcodes is of interest because it is exploited by the Linux
 kernel.
-The SFDP table size is 0x200 bytes long. The mandatory table for basic
+Add test_ast2500_evb function and reused testcases for AST2500 testing.
-features is available at byte 0x30 and an extra Macronix specific
+The spi base address, flash base address and ce index of fmc_cs0 are
-table is available at 0x60.
+x1E620000, 0x20000000 and 0, respectively.
 The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB,
 so set jedec_id 0xc22019.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-Message-Id: <20220722063602.128144-5-clg@kaod.org>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
-Message-Id: <20221013161241.2805140-6-clg@kaod.org>
+Link: https://lore.kernel.org/r/20241127091543.1243114-6-jamin_lin@aspeedtech.com
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h |  1 +
+ tests/qtest/aspeed_smc-test.c | 40 +++++++++++++++++++++++++++++++++++
- hw/block/m25p80.c      |  2 ++
+file changed, 40 insertions(+)
  hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 files changed, 71 insertions(+)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
- uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+                         data, test_write_block_protect_bottom_bit);
+ }
- uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
-+uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
++static void test_ast2500_evb(TestData *data)
++{
++    int ret;
- #endif
++    int fd;
 diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80.c
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
      { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
              ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
 +    { INFO6("mx25l25635f", 0xc22019,     0xc22019,  64 << 10, 512,
 +            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
      { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
      { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
      { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635e[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(mx25l25635e)
 +
-+static const uint8_t sfdp_mx25l25635f[] = {
++    fd = g_file_open_tmp("qtest.m25p80.mx25l25635e.XXXXXX",
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
++                         &data->tmp_path, NULL);
-+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
++    g_assert(fd >= 0);
-+    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
++    ret = ftruncate(fd, 32 * 1024 * 1024);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    g_assert(ret == 0);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    close(fd);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
++    data->s = qtest_initf("-machine ast2500-evb "
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
++                          "-drive file=%s,format=raw,if=mtd",
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
++                          data->tmp_path);
-+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
++
-+    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /* fmc cs0 with mx25l25635e flash */
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->flash_base = 0x20000000;
-+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
++    data->spi_base = 0x1E620000;
-+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->jedec_id = 0xc22019;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->cs = 0;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->node = "/machine/soc/fmc/ssi.0/child[0]";
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /* beyond 16MB */
-+    0xff, 0xff, 0xff, 0xff, 0xc2, 0xf5, 0x08, 0x0a,
++    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
-+    0x08, 0x04, 0x03, 0x06, 0x00, 0x00, 0x07, 0x29,
++
-+    0x17, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/erase_all",  data, test_erase_all);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/read_page_mem",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, test_read_page_mem);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/write_page_mem",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, test_write_page_mem);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2500/smc/read_status_reg",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, test_read_status_reg);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++}
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ int main(int argc, char **argv)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ {
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     TestData palmetto_data;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    TestData ast2500_evb_data;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     int ret;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     g_test_init(&argc, &argv, NULL);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     test_palmetto_bmc(&palmetto_data);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    test_ast2500_evb(&ast2500_evb_data);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     ret = g_test_run();
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     qtest_quit(palmetto_data.s);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_quit(ast2500_evb_data.s);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     unlink(palmetto_data.tmp_path);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    unlink(ast2500_evb_data.tmp_path);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     return ret;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ }
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(mx25l25635f);
 --
-.37.3
+.47.1

-[PULL 02/16] tests/avocado/machine_aspeed.py: Fix typos on buildroot
+[PULL 20/24] test/qtest/aspeed_smc-test: Support to test AST2600
-Replace 'buidroot' and 'builroot' by 'buildroot'.
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-Fixes: f7bc7da0724f ("test/avocado/machine_aspeed.py: Add tests using buildroot images")
+Add test_ast2600_evb function and reused testcases for AST2600 testing.
-Reviewed-by: Thomas Huth <thuth@redhat.com>
+The spi base address, flash base address and ce index of fmc_cs0 are
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+x1E620000, 0x20000000 and 0, respectively.
-Reviewed-by: Joel Stanley <joel@jms.id.au>
+The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
-Message-Id: <20220923084803.498337-2-clg@kaod.org>
+so set jedec_id 0xc2253a.
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-7-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- tests/avocado/machine_aspeed.py | 16 ++++++++--------
+ tests/qtest/aspeed_smc-test.c | 41 +++++++++++++++++++++++++++++++++++
-file changed, 8 insertions(+), 8 deletions(-)
+file changed, 41 insertions(+)
-diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/machine_aspeed.py
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/tests/avocado/machine_aspeed.py
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
+@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
+     qtest_add_data_func("/ast2500/smc/read_status_reg",
-         self.do_test_arm_aspeed(image_path)
+                         data, test_read_status_reg);
+ }
--    def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
++
-+    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
++static void test_ast2600_evb(TestData *data)
-         self.require_netdev('user')
++{
++    int ret;
-         self.vm.set_console()
++    int fd;
-@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
++
-         exec_command(self, 'root')
++    fd = g_file_open_tmp("qtest.m25p80.mx66u51235f.XXXXXX",
-         time.sleep(0.1)
++                         &data->tmp_path, NULL);
++    g_assert(fd >= 0);
--    def do_test_arm_aspeed_buidroot_poweroff(self):
++    ret = ftruncate(fd, 64 * 1024 * 1024);
-+    def do_test_arm_aspeed_buildroot_poweroff(self):
++    g_assert(ret == 0);
-         exec_command_and_wait_for_pattern(self, 'poweroff',
++    close(fd);
-                                           'reboot: System halted');
++
++    data->s = qtest_initf("-machine ast2600-evb "
--    def test_arm_ast2500_evb_builroot(self):
++                          "-drive file=%s,format=raw,if=mtd",
-+    def test_arm_ast2500_evb_buildroot(self):
++                          data->tmp_path);
-         """
++
-         :avocado: tags=arch:arm
++    /* fmc cs0 with mx66u51235f flash */
-         :avocado: tags=machine:ast2500-evb
++    data->flash_base = 0x20000000;
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
++    data->spi_base = 0x1E620000;
++    data->jedec_id = 0xc2253a;
-         self.vm.add_args('-device',
++    data->cs = 0;
-                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
++    data->node = "/machine/soc/fmc/ssi.0/child[0]";
--        self.do_test_arm_aspeed_buidroot_start(image_path, '0x0')
++    /* beyond 16MB */
-+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
++    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
++
-         exec_command_and_wait_for_pattern(self,
++    qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
-              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
++    qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector);
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
++    qtest_add_data_func("/ast2600/smc/erase_all",  data, test_erase_all);
-         exec_command_and_wait_for_pattern(self,
++    qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
-                              'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
++    qtest_add_data_func("/ast2600/smc/read_page_mem",
++                        data, test_read_page_mem);
--        self.do_test_arm_aspeed_buidroot_poweroff()
++    qtest_add_data_func("/ast2600/smc/write_page_mem",
-+        self.do_test_arm_aspeed_buildroot_poweroff()
++                        data, test_write_page_mem);
++    qtest_add_data_func("/ast2600/smc/read_status_reg",
--    def test_arm_ast2600_evb_builroot(self):
++                        data, test_read_status_reg);
-+    def test_arm_ast2600_evb_buildroot(self):
++}
-         """
+ int main(int argc, char **argv)
-         :avocado: tags=arch:arm
+ {
-         :avocado: tags=machine:ast2600-evb
+     TestData palmetto_data;
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
+     TestData ast2500_evb_data;
-                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
++    TestData ast2600_evb_data;
-         self.vm.add_args('-device',
+     int ret;
-                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
--        self.do_test_arm_aspeed_buidroot_start(image_path, '0xf00')
+     g_test_init(&argc, &argv, NULL);
-+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
+     test_palmetto_bmc(&palmetto_data);
-         exec_command_and_wait_for_pattern(self,
+     test_ast2500_evb(&ast2500_evb_data);
-              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
++    test_ast2600_evb(&ast2600_evb_data);
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
+     ret = g_test_run();
-         year = time.strftime("%Y")
-         exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
+     qtest_quit(palmetto_data.s);
+     qtest_quit(ast2500_evb_data.s);
--        self.do_test_arm_aspeed_buidroot_poweroff()
++    qtest_quit(ast2600_evb_data.s);
-+        self.do_test_arm_aspeed_buildroot_poweroff()
+     unlink(palmetto_data.tmp_path);
+     unlink(ast2500_evb_data.tmp_path);
++    unlink(ast2600_evb_data.tmp_path);
- class AST2x00MachineSDK(QemuSystemTest):
+     return ret;
  }
 --
-.37.3
+.47.1

-[PULL 01/16] hw/i2c/aspeed: Fix old reg slave receive
+[PULL 21/24] test/qtest/aspeed_smc-test: Support to test AST1030
-From: Peter Delevoryas <peter@pjd.dev>
+From: Jamin Lin <jamin_lin@aspeedtech.com>
-I think when Klaus ported his slave mode changes from the original patch
+Add test_ast1030_evb function and reused testcases for AST1030 testing.
-series to the rewritten I2C module, he changed the behavior of the first
+The base address, flash base address and ce index of fmc_cs0 are
-byte that is received by the slave device.
+x7E620000, 0x80000000 and 0, respectively.
 The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB,
 so set jedec_id 0xef4014.
-What's supposed to happen is that the AspeedI2CBus's slave device's
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-i2c_event callback should run, and if the event is "send_async", then it
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
-should populate the byte buffer with the 8-bit I2C address that is being
+Link: https://lore.kernel.org/r/20241127091543.1243114-8-jamin_lin@aspeedtech.com
-sent to. Since we only support "send_async", the lowest bit should
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
-always be 0 (indicating that the master is requesting to send data).
+---
  tests/qtest/aspeed_smc-test.c | 42 +++++++++++++++++++++++++++++++++++
 file changed, 42 insertions(+)
-This is the code Klaus had previously, for reference. [1]
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
     switch (event) {
     case I2C_START_SEND:
         bus->buf = bus->dev_addr << 1;
         bus->buf &= I2CD_BYTE_BUF_RX_MASK;
         bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT;
         bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE);
         aspeed_i2c_set_state(bus, I2CD_STXD);
         break;
 [1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/
 Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode")
 Signed-off-by: Peter Delevoryas <peter@pjd.dev>
 Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
 Message-Id: <20220820225712.713209-2-peter@pjd.dev>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
  include/hw/i2c/aspeed_i2c.h | 1 +
  hw/i2c/aspeed_i2c.c         | 8 +++++---
 files changed, 6 insertions(+), 3 deletions(-)
 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/aspeed_i2c.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/include/hw/i2c/aspeed_i2c.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
+@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
-     SHARED_FIELD(M_TX_CMD, 1, 1)
+     qtest_add_data_func("/ast2600/smc/read_status_reg",
-     SHARED_FIELD(M_START_CMD, 0, 1)
+                         data, test_read_status_reg);
- REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
+ }
-+    SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
++
- REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
++static void test_ast1030_evb(TestData *data)
-     SHARED_FIELD(RX_COUNT, 24, 5)
++{
-     SHARED_FIELD(RX_SIZE, 16, 5)
++    int ret;
-diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
++    int fd;
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/i2c/aspeed_i2c.c
++    fd = g_file_open_tmp("qtest.m25p80.w25q80bl.XXXXXX",
-+++ b/hw/i2c/aspeed_i2c.c
++                         &data->tmp_path, NULL);
-@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
++    g_assert(fd >= 0);
-     AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
++    ret = ftruncate(fd, 1 * 1024 * 1024);
-     uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
++    g_assert(ret == 0);
-     uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
++    close(fd);
--    uint32_t value;
++
-+    uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
++    data->s = qtest_initf("-machine ast1030-evb "
-+    uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
++                          "-drive file=%s,format=raw,if=mtd",
-+                                                SLAVE_DEV_ADDR1);
++                          data->tmp_path);
++
-     if (aspeed_i2c_is_new_mode(bus->controller)) {
++    /* fmc cs0 with w25q80bl flash */
-         return aspeed_i2c_bus_new_slave_event(bus, event);
++    data->flash_base = 0x80000000;
-@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
++    data->spi_base = 0x7E620000;
++    data->jedec_id = 0xef4014;
-     switch (event) {
++    data->cs = 0;
-     case I2C_START_SEND_ASYNC:
++    data->node = "/machine/soc/fmc/ssi.0/child[0]";
--        value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
++    /* beyond 512KB */
--        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << 1);
++    data->page_addr = 0x800 * FLASH_PAGE_SIZE;
-+        /* Bit[0] == 0 indicates "send". */
++
-+        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
++    qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
++    qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector);
-         ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
++    qtest_add_data_func("/ast1030/smc/erase_all",  data, test_erase_all);
-         SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
++    qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast1030/smc/read_page_mem",
 +                        data, test_read_page_mem);
 +    qtest_add_data_func("/ast1030/smc/write_page_mem",
 +                        data, test_write_page_mem);
 +    qtest_add_data_func("/ast1030/smc/read_status_reg",
 +                        data, test_read_status_reg);
 +}
 +
  int main(int argc, char **argv)
  {
      TestData palmetto_data;
      TestData ast2500_evb_data;
      TestData ast2600_evb_data;
 +    TestData ast1030_evb_data;
      int ret;
      g_test_init(&argc, &argv, NULL);
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
      test_palmetto_bmc(&palmetto_data);
      test_ast2500_evb(&ast2500_evb_data);
      test_ast2600_evb(&ast2600_evb_data);
 +    test_ast1030_evb(&ast1030_evb_data);
      ret = g_test_run();
      qtest_quit(palmetto_data.s);
      qtest_quit(ast2500_evb_data.s);
      qtest_quit(ast2600_evb_data.s);
 +    qtest_quit(ast1030_evb_data.s);
      unlink(palmetto_data.tmp_path);
      unlink(ast2500_evb_data.tmp_path);
      unlink(ast2600_evb_data.tmp_path);
 +    unlink(ast1030_evb_data.tmp_path);
      return ret;
  }
 --
-.37.3
+.47.1

-[PULL 14/16] m25p80: Add the w25q512jv SFPD table
+[PULL 22/24] test/qtest/aspeed_smc-test: Support write page command with QPI mode
-The SFDP table size is 0x100 bytes long. The mandatory table for basic
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 features is available at byte 0x80 and two extra Winbond specifics
 table are available at 0xC0 and 0xF0.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Add a new testcase for write page command with QPI mode testing.
-Message-Id: <20220722063602.128144-8-clg@kaod.org>
+Currently, only run this testcase for AST2500, AST2600 and AST1030.
-Message-Id: <20221013161241.2805140-9-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-9-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h |  1 +
+ tests/qtest/aspeed_smc-test.c | 74 +++++++++++++++++++++++++++++++++++
- hw/block/m25p80.c      |  3 ++-
+file changed, 74 insertions(+)
  hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
 files changed, 39 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/qtest/aspeed_smc-test.c
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@
- uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+ #define R_CE_CTRL           0x04
+ #define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
- uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+ #define R_CTRL0             0x10
-+uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
++#define   CTRL_IO_QUAD_IO      BIT(31)
+ #define   CTRL_CE_STOP_ACTIVE  BIT(2)
- #endif
+ #define   CTRL_READMODE        0x0
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+ #define   CTRL_FREADMODE       0x1
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ enum {
---- a/hw/block/m25p80.c
+     ERASE_SECTOR = 0xd8,
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
      { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
        .sfdp_read = m25p80_sfdp_w25q256 },
 -    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
 +    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
 +      .sfdp_read = m25p80_sfdp_w25q512jv },
      { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
  };
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
++#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
-index XXXXXXX..XXXXXXX 100644
+ #define FLASH_PAGE_SIZE           256
---- a/hw/block/m25p80_sfdp.c
-+++ b/hw/block/m25p80_sfdp.c
+ typedef struct TestData {
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q256[] = {
+@@ -XXX,XX +XXX,XX @@ static void spi_ctrl_stop_user(const TestData *data)
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     spi_writel(data, ctrl_reg, ctrl);
- };
+ }
- define_sfdp_read(w25q256);
 +static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
 +{
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
 +    uint32_t mode;
 +
-+static const uint8_t sfdp_w25q512jv[] = {
++    mode = value & CTRL_IO_MODE_MASK;
-+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
++    ctrl &= ~CTRL_IO_MODE_MASK;
-+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
++    ctrl |= mode;
-+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
++    spi_writel(data, ctrl_reg, ctrl);
-+    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
++}
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ static void flash_reset(const TestData *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ {
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     flash_reset(test_data);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ }
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++static void test_write_page_qpi(const void *data)
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++{
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    const TestData *test_data = (const TestData *)data;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    uint32_t my_page_addr = test_data->page_addr;
-+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
++    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
++    uint32_t page[FLASH_PAGE_SIZE / 4];
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
++    uint32_t page_pattern[] = {
-+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
++        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
-+    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
++    };
-+    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
++    int i;
-+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
++
-+    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
++    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    spi_ctrl_start_user(test_data);
-+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
++    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    flash_writeb(test_data, 0, WREN);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    flash_writeb(test_data, 0, PP);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    flash_writel(test_data, 0, make_be32(my_page_addr));
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /* Set QPI mode */
-+};
++    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
-+define_sfdp_read(w25q512jv);
++
 +    /* Fill the page pattern */
 +    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 +        flash_writel(test_data, 0, make_be32(page_pattern[i]));
 +    }
 +
 +    /* Fill the page with its own addresses */
 +    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 +    }
 +
 +    /* Restore io mode */
 +    spi_ctrl_set_io_mode(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check what was written */
 +    read_page(test_data, my_page_addr, page);
 +    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 +        g_assert_cmphex(page[i], ==, page_pattern[i]);
 +    }
 +    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 +    }
 +
 +    /* Check some other page. It should be full of 0xff */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
  static void test_palmetto_bmc(TestData *data)
  {
      int ret;
@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
                          data, test_write_page_mem);
      qtest_add_data_func("/ast2500/smc/read_status_reg",
                          data, test_read_status_reg);
 +    qtest_add_data_func("/ast2500/smc/write_page_qpi",
 +                        data, test_write_page_qpi);
  }
  static void test_ast2600_evb(TestData *data)
@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
                          data, test_write_page_mem);
      qtest_add_data_func("/ast2600/smc/read_status_reg",
                          data, test_read_status_reg);
 +    qtest_add_data_func("/ast2600/smc/write_page_qpi",
 +                        data, test_write_page_qpi);
  }
  static void test_ast1030_evb(TestData *data)
@@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data)
                          data, test_write_page_mem);
      qtest_add_data_func("/ast1030/smc/read_status_reg",
                          data, test_read_status_reg);
 +    qtest_add_data_func("/ast1030/smc/write_page_qpi",
 +                        data, test_write_page_qpi);
  }
  int main(int argc, char **argv)
 --
-.37.3
+.47.1

-[PULL 07/16] m25p80: Add basic support for the SFDP command
+[PULL 23/24] test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases
-JEDEC STANDARD JESD216 for Serial Flash Discovery Parameters (SFDP)
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 provides a mean to describe the features of a serial flash device
 using a set of internal parameter tables.
-This is the initial framework for the RDSFDP command giving access to
+The testcases for ASPEED SMC model were placed in aspeed_smc-test.c.
-a private SFDP area under the flash. This area now needs to be
+However, this test file only supports for ARM32. To support all ASPEED SOCs
-populated with the flash device characteristics, using a new
+such as AST2700 whose CPU architecture is aarch64, introduces a new
-'sfdp_read' handler under FlashPartInfo.
+aspeed-smc-utils source file and move all common APIs and testcases
 from aspeed_smc-test.c to aspeed-smc-utils.c.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Finally, users are able to re-used these testcase for AST2700 and future
-Message-Id: <20220722063602.128144-2-clg@kaod.org>
+ASPEED SOCs testing.
-Message-Id: <20221013161241.2805140-2-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
 Reviewed-by: Cédric Le Goater <clg@redhat.com>
 Link: https://lore.kernel.org/r/20241127091543.1243114-10-jamin_lin@aspeedtech.com
 Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h | 18 ++++++++++++++++++
+ tests/qtest/aspeed-smc-utils.h |  95 ++++
- hw/block/m25p80.c      | 27 +++++++++++++++++++++++++++
+ tests/qtest/aspeed-smc-utils.c | 686 ++++++++++++++++++++++++++++
- MAINTAINERS            |  2 +-
+ tests/qtest/aspeed_smc-test.c  | 800 +++------------------------------
- hw/block/trace-events  |  1 +
+ tests/qtest/meson.build        |   1 +
-files changed, 47 insertions(+), 1 deletion(-)
+files changed, 841 insertions(+), 741 deletions(-)
- create mode 100644 hw/block/m25p80_sfdp.h
+ create mode 100644 tests/qtest/aspeed-smc-utils.h
  create mode 100644 tests/qtest/aspeed-smc-utils.c
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/aspeed-smc-utils.h b/tests/qtest/aspeed-smc-utils.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/block/m25p80_sfdp.h
++++ b/tests/qtest/aspeed-smc-utils.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * M25P80 SFDP
++ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
 + * Controller)
 + *
-+ * Copyright (c) 2020, IBM Corporation.
++ * Copyright (C) 2016 IBM Corp.
 + *
-+ * This code is licensed under the GPL version 2 or later. See the
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+ * COPYING file in the top-level directory.
++ * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
-+#ifndef HW_M25P80_SFDP_H
++#ifndef TESTS_ASPEED_SMC_UTILS_H
-+#define HW_M25P80_SFDP_H
++#define TESTS_ASPEED_SMC_UTILS_H
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bswap.h"
 +#include "libqtest-single.h"
 +#include "qemu/bitops.h"
 +
 +/*
-+ * SFDP area has a 3 bytes address space.
++ * ASPEED SPI Controller registers
 + */
-+#define M25P80_SFDP_MAX_SIZE  (1 << 24)
++#define R_CONF              0x00
-+
++#define   CONF_ENABLE_W0       16
-+#endif
++#define R_CE_CTRL           0x04
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++#define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
 +#define R_CTRL0             0x10
 +#define   CTRL_IO_QUAD_IO      BIT(31)
 +#define   CTRL_CE_STOP_ACTIVE  BIT(2)
 +#define   CTRL_READMODE        0x0
 +#define   CTRL_FREADMODE       0x1
 +#define   CTRL_WRITEMODE       0x2
 +#define   CTRL_USERMODE        0x3
 +#define SR_WEL BIT(1)
 +
 +/*
 + * Flash commands
 + */
 +enum {
 +    JEDEC_READ = 0x9f,
 +    RDSR = 0x5,
 +    WRDI = 0x4,
 +    BULK_ERASE = 0xc7,
 +    READ = 0x03,
 +    PP = 0x02,
 +    WRSR = 0x1,
 +    WREN = 0x6,
 +    SRWD = 0x80,
 +    RESET_ENABLE = 0x66,
 +    RESET_MEMORY = 0x99,
 +    EN_4BYTE_ADDR = 0xB7,
 +    ERASE_SECTOR = 0xd8,
 +};
 +
 +#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
 +#define FLASH_PAGE_SIZE           256
 +
 +typedef struct AspeedSMCTestData {
 +    QTestState *s;
 +    uint64_t spi_base;
 +    uint64_t flash_base;
 +    uint32_t jedec_id;
 +    char *tmp_path;
 +    uint8_t cs;
 +    const char *node;
 +    uint32_t page_addr;
 +} AspeedSMCTestData;
 +
 +void aspeed_smc_test_read_jedec(const void *data);
 +void aspeed_smc_test_erase_sector(const void *data);
 +void aspeed_smc_test_erase_all(const void *data);
 +void aspeed_smc_test_write_page(const void *data);
 +void aspeed_smc_test_read_page_mem(const void *data);
 +void aspeed_smc_test_write_page_mem(const void *data);
 +void aspeed_smc_test_read_status_reg(const void *data);
 +void aspeed_smc_test_status_reg_write_protection(const void *data);
 +void aspeed_smc_test_write_block_protect(const void *data);
 +void aspeed_smc_test_write_block_protect_bottom_bit(const void *data);
 +void aspeed_smc_test_write_page_qpi(const void *data);
 +
 +#endif /* TESTS_ASPEED_SMC_UTILS_H */
 diff --git a/tests/qtest/aspeed-smc-utils.c b/tests/qtest/aspeed-smc-utils.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/qtest/aspeed-smc-utils.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
 + * Controller)
 + *
 + * Copyright (C) 2016 IBM Corp.
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bswap.h"
 +#include "libqtest-single.h"
 +#include "qemu/bitops.h"
 +#include "aspeed-smc-utils.h"
 +
 +/*
 + * Use an explicit bswap for the values read/wrote to the flash region
 + * as they are BE and the Aspeed CPU is LE.
 + */
 +static inline uint32_t make_be32(uint32_t data)
 +{
 +    return bswap32(data);
 +}
 +
 +static inline void spi_writel(const AspeedSMCTestData *data, uint64_t offset,
 +                              uint32_t value)
 +{
 +    qtest_writel(data->s, data->spi_base + offset, value);
 +}
 +
 +static inline uint32_t spi_readl(const AspeedSMCTestData *data, uint64_t offset)
 +{
 +    return qtest_readl(data->s, data->spi_base + offset);
 +}
 +
 +static inline void flash_writeb(const AspeedSMCTestData *data, uint64_t offset,
 +                                uint8_t value)
 +{
 +    qtest_writeb(data->s, data->flash_base + offset, value);
 +}
 +
 +static inline void flash_writel(const AspeedSMCTestData *data, uint64_t offset,
 +                                uint32_t value)
 +{
 +    qtest_writel(data->s, data->flash_base + offset, value);
 +}
 +
 +static inline uint8_t flash_readb(const AspeedSMCTestData *data,
 +                                  uint64_t offset)
 +{
 +    return qtest_readb(data->s, data->flash_base + offset);
 +}
 +
 +static inline uint32_t flash_readl(const AspeedSMCTestData *data,
 +                                   uint64_t offset)
 +{
 +    return qtest_readl(data->s, data->flash_base + offset);
 +}
 +
 +static void spi_conf(const AspeedSMCTestData *data, uint32_t value)
 +{
 +    uint32_t conf = spi_readl(data, R_CONF);
 +
 +    conf |= value;
 +    spi_writel(data, R_CONF, conf);
 +}
 +
 +static void spi_conf_remove(const AspeedSMCTestData *data, uint32_t value)
 +{
 +    uint32_t conf = spi_readl(data, R_CONF);
 +
 +    conf &= ~value;
 +    spi_writel(data, R_CONF, conf);
 +}
 +
 +static void spi_ce_ctrl(const AspeedSMCTestData *data, uint32_t value)
 +{
 +    uint32_t conf = spi_readl(data, R_CE_CTRL);
 +
 +    conf |= value;
 +    spi_writel(data, R_CE_CTRL, conf);
 +}
 +
 +static void spi_ctrl_setmode(const AspeedSMCTestData *data, uint8_t mode,
 +                             uint8_t cmd)
 +{
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
 +    ctrl &= ~(CTRL_USERMODE | 0xff << 16);
 +    ctrl |= mode | (cmd << 16);
 +    spi_writel(data, ctrl_reg, ctrl);
 +}
 +
 +static void spi_ctrl_start_user(const AspeedSMCTestData *data)
 +{
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
 +
 +    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 +    spi_writel(data, ctrl_reg, ctrl);
 +
 +    ctrl &= ~CTRL_CE_STOP_ACTIVE;
 +    spi_writel(data, ctrl_reg, ctrl);
 +}
 +
 +static void spi_ctrl_stop_user(const AspeedSMCTestData *data)
 +{
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
 +
 +    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 +    spi_writel(data, ctrl_reg, ctrl);
 +}
 +
 +static void spi_ctrl_set_io_mode(const AspeedSMCTestData *data, uint32_t value)
 +{
 +    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 +    uint32_t ctrl = spi_readl(data, ctrl_reg);
 +    uint32_t mode;
 +
 +    mode = value & CTRL_IO_MODE_MASK;
 +    ctrl &= ~CTRL_IO_MODE_MASK;
 +    ctrl |= mode;
 +    spi_writel(data, ctrl_reg, ctrl);
 +}
 +
 +static void flash_reset(const AspeedSMCTestData *data)
 +{
 +    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
 +
 +    spi_ctrl_start_user(data);
 +    flash_writeb(data, 0, RESET_ENABLE);
 +    flash_writeb(data, 0, RESET_MEMORY);
 +    flash_writeb(data, 0, WREN);
 +    flash_writeb(data, 0, BULK_ERASE);
 +    flash_writeb(data, 0, WRDI);
 +    spi_ctrl_stop_user(data);
 +
 +    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
 +}
 +
 +static void read_page(const AspeedSMCTestData *data, uint32_t addr,
 +                      uint32_t *page)
 +{
 +    int i;
 +
 +    spi_ctrl_start_user(data);
 +
 +    flash_writeb(data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(data, 0, READ);
 +    flash_writel(data, 0, make_be32(addr));
 +
 +    /* Continuous read are supported */
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        page[i] = make_be32(flash_readl(data, 0));
 +    }
 +    spi_ctrl_stop_user(data);
 +}
 +
 +static void read_page_mem(const AspeedSMCTestData *data, uint32_t addr,
 +                          uint32_t *page)
 +{
 +    int i;
 +
 +    /* move out USER mode to use direct reads from the AHB bus */
 +    spi_ctrl_setmode(data, CTRL_READMODE, READ);
 +
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        page[i] = make_be32(flash_readl(data, addr + i * 4));
 +    }
 +}
 +
 +static void write_page_mem(const AspeedSMCTestData *data, uint32_t addr,
 +                           uint32_t write_value)
 +{
 +    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
 +
 +    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(data, addr + i * 4, write_value);
 +    }
 +}
 +
 +static void assert_page_mem(const AspeedSMCTestData *data, uint32_t addr,
 +                            uint32_t expected_value)
 +{
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    read_page_mem(data, addr, page);
 +    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, expected_value);
 +    }
 +}
 +
 +void aspeed_smc_test_read_jedec(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t jedec = 0x0;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, JEDEC_READ);
 +    jedec |= flash_readb(test_data, 0) << 16;
 +    jedec |= flash_readb(test_data, 0) << 8;
 +    jedec |= flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    flash_reset(test_data);
 +
 +    g_assert_cmphex(jedec, ==, test_data->jedec_id);
 +}
 +
 +void aspeed_smc_test_erase_sector(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t some_page_addr = test_data->page_addr;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    int i;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    /*
 +     * Previous page should be full of 0xffs after backend is
 +     * initialized
 +     */
 +    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
 +
 +    /* Fill the page with its own addresses */
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
 +    }
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check the page is correctly written */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
 +    }
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, ERASE_SECTOR);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check the page is erased */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_erase_all(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t some_page_addr = test_data->page_addr;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    int i;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    /*
 +     * Previous page should be full of 0xffs after backend is
 +     * initialized
 +     */
 +    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(some_page_addr));
 +
 +    /* Fill the page with its own addresses */
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
 +    }
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check the page is correctly written */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
 +    }
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, BULK_ERASE);
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check the page is erased */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_write_page(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t my_page_addr = test_data->page_addr;
 +    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    int i;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(my_page_addr));
 +
 +    /* Fill the page with its own addresses */
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 +    }
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check what was written */
 +    read_page(test_data, my_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 +    }
 +
 +    /* Check some other page. It should be full of 0xff */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_read_page_mem(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t my_page_addr = test_data->page_addr;
 +    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    int i;
 +
 +    /*
 +     * Enable 4BYTE mode for controller.
 +     */
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +
 +    /* Enable 4BYTE mode for flash. */
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(my_page_addr));
 +
 +    /* Fill the page with its own addresses */
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 +    }
 +    spi_ctrl_stop_user(test_data);
 +    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    /* Check what was written */
 +    read_page_mem(test_data, my_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 +    }
 +
 +    /* Check some other page. It should be full of 0xff */
 +    read_page_mem(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_write_page_mem(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t my_page_addr = test_data->page_addr;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    int i;
 +
 +    /*
 +     * Enable 4BYTE mode for controller.
 +     */
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +
 +    /* Enable 4BYTE mode for flash. */
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* move out USER mode to use direct writes to the AHB bus */
 +    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
 +
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, my_page_addr + i * 4,
 +               make_be32(my_page_addr + i * 4));
 +    }
 +
 +    /* Check what was written */
 +    read_page_mem(test_data, my_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_read_status_reg(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint8_t r;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    g_assert_cmphex(r & SR_WEL, ==, 0);
 +    g_assert(!qtest_qom_get_bool
 +            (test_data->s, test_data->node, "write-enable"));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
 +    g_assert(qtest_qom_get_bool
 +            (test_data->s, test_data->node, "write-enable"));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WRDI);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    g_assert_cmphex(r & SR_WEL, ==, 0);
 +    g_assert(!qtest_qom_get_bool
 +            (test_data->s, test_data->node, "write-enable"));
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_status_reg_write_protection(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint8_t r;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    /* default case: WP# is high and SRWD is low -> status register writable */
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    /* test ability to write SRWD */
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, SRWD);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +    g_assert_cmphex(r & SRWD, ==, SRWD);
 +
 +    /* WP# high and SRWD high -> status register writable */
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    /* test ability to write SRWD */
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, 0);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +    g_assert_cmphex(r & SRWD, ==, 0);
 +
 +    /* WP# low and SRWD low -> status register writable */
 +    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, WREN);
 +    /* test ability to write SRWD */
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, SRWD);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +    g_assert_cmphex(r & SRWD, ==, SRWD);
 +
 +    /* WP# low and SRWD high -> status register NOT writable */
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0 , WREN);
 +    /* test ability to write SRWD */
 +    flash_writeb(test_data, 0, WRSR);
 +    flash_writeb(test_data, 0, 0);
 +    flash_writeb(test_data, 0, RDSR);
 +    r = flash_readb(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +    /* write is not successful */
 +    g_assert_cmphex(r & SRWD, ==, SRWD);
 +
 +    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_write_block_protect(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t sector_size = 65536;
 +    uint32_t n_sectors = 512;
 +
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    uint32_t bp_bits = 0b0;
 +
 +    for (int i = 0; i < 16; i++) {
 +        bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
 +
 +        spi_ctrl_start_user(test_data);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, BULK_ERASE);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, WRSR);
 +        flash_writeb(test_data, 0, bp_bits);
 +        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +        flash_writeb(test_data, 0, WREN);
 +        spi_ctrl_stop_user(test_data);
 +
 +        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
 +        uint32_t protection_start = n_sectors - num_protected_sectors;
 +        uint32_t protection_end = n_sectors;
 +
 +        for (int sector = 0; sector < n_sectors; sector++) {
 +            uint32_t addr = sector * sector_size;
 +
 +            assert_page_mem(test_data, addr, 0xffffffff);
 +            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 +
 +            uint32_t expected_value = protection_start <= sector
 +                                      && sector < protection_end
 +                                      ? 0xffffffff : 0xabcdef12;
 +
 +            assert_page_mem(test_data, addr, expected_value);
 +        }
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_write_block_protect_bottom_bit(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t sector_size = 65536;
 +    uint32_t n_sectors = 512;
 +
 +    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    /* top bottom bit is enabled */
 +    uint32_t bp_bits = 0b00100 << 3;
 +
 +    for (int i = 0; i < 16; i++) {
 +        bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
 +
 +        spi_ctrl_start_user(test_data);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, BULK_ERASE);
 +        flash_writeb(test_data, 0, WREN);
 +        flash_writeb(test_data, 0, WRSR);
 +        flash_writeb(test_data, 0, bp_bits);
 +        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +        flash_writeb(test_data, 0, WREN);
 +        spi_ctrl_stop_user(test_data);
 +
 +        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
 +        uint32_t protection_start = 0;
 +        uint32_t protection_end = num_protected_sectors;
 +
 +        for (int sector = 0; sector < n_sectors; sector++) {
 +            uint32_t addr = sector * sector_size;
 +
 +            assert_page_mem(test_data, addr, 0xffffffff);
 +            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 +
 +            uint32_t expected_value = protection_start <= sector
 +                                      && sector < protection_end
 +                                      ? 0xffffffff : 0xabcdef12;
 +
 +            assert_page_mem(test_data, addr, expected_value);
 +        }
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 +void aspeed_smc_test_write_page_qpi(const void *data)
 +{
 +    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
 +    uint32_t my_page_addr = test_data->page_addr;
 +    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 +    uint32_t page[FLASH_PAGE_SIZE / 4];
 +    uint32_t page_pattern[] = {
 +        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
 +    };
 +    int i;
 +
 +    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 +
 +    spi_ctrl_start_user(test_data);
 +    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 +    flash_writeb(test_data, 0, WREN);
 +    flash_writeb(test_data, 0, PP);
 +    flash_writel(test_data, 0, make_be32(my_page_addr));
 +
 +    /* Set QPI mode */
 +    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
 +
 +    /* Fill the page pattern */
 +    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 +        flash_writel(test_data, 0, make_be32(page_pattern[i]));
 +    }
 +
 +    /* Fill the page with its own addresses */
 +    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 +        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 +    }
 +
 +    /* Restore io mode */
 +    spi_ctrl_set_io_mode(test_data, 0);
 +    spi_ctrl_stop_user(test_data);
 +
 +    /* Check what was written */
 +    read_page(test_data, my_page_addr, page);
 +    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 +        g_assert_cmphex(page[i], ==, page_pattern[i]);
 +    }
 +    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 +    }
 +
 +    /* Check some other page. It should be full of 0xff */
 +    read_page(test_data, some_page_addr, page);
 +    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 +        g_assert_cmphex(page[i], ==, 0xffffffff);
 +    }
 +
 +    flash_reset(test_data);
 +}
 +
 diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/tests/qtest/aspeed_smc-test.c
-+++ b/hw/block/m25p80.c
++++ b/tests/qtest/aspeed_smc-test.c
 @@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
+ #include "qemu/bswap.h"
- #include "trace.h"
+ #include "libqtest-single.h"
- #include "qom/object.h"
+ #include "qemu/bitops.h"
-+#include "m25p80_sfdp.h"
++#include "aspeed-smc-utils.h"
- /* 16 MiB max in 3 byte address mode */
+-/*
- #define MAX_3BYTES_SIZE 0x1000000
+- * ASPEED SPI Controller registers
-@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
+- */
-      * This field inform how many die is in the chip.
+-#define R_CONF              0x00
-      */
+-#define   CONF_ENABLE_W0       16
-     uint8_t die_cnt;
+-#define R_CE_CTRL           0x04
-+    uint8_t (*sfdp_read)(uint32_t sfdp_addr);
+-#define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
- } FlashPartInfo;
+-#define R_CTRL0             0x10
+-#define   CTRL_IO_QUAD_IO      BIT(31)
- /* adapted from linux */
+-#define   CTRL_CE_STOP_ACTIVE  BIT(2)
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+-#define   CTRL_READMODE        0x0
-     BULK_ERASE = 0xc7,
+-#define   CTRL_FREADMODE       0x1
-     READ_FSR = 0x70,
+-#define   CTRL_WRITEMODE       0x2
-     RDCR = 0x15,
+-#define   CTRL_USERMODE        0x3
-+    RDSFDP = 0x5a,
+-#define SR_WEL BIT(1)
+-
-     READ = 0x03,
+-/*
-     READ4 = 0x13,
+- * Flash commands
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+- */
-     STATE_COLLECTING_DATA,
+-enum {
-     STATE_COLLECTING_VAR_LEN_DATA,
+-    JEDEC_READ = 0x9f,
-     STATE_READING_DATA,
+-    RDSR = 0x5,
-+    STATE_READING_SFDP,
+-    WRDI = 0x4,
- } CMDState;
+-    BULK_ERASE = 0xc7,
+-    READ = 0x03,
- typedef enum {
+-    PP = 0x02,
-@@ -XXX,XX +XXX,XX @@ static inline int get_addr_length(Flash *s)
+-    WRSR = 0x1,
-     }
+-    WREN = 0x6,
+-    SRWD = 0x80,
-    switch (s->cmd_in_progress) {
+-    RESET_ENABLE = 0x66,
-+   case RDSFDP:
+-    RESET_MEMORY = 0x99,
-+       return 3;
+-    EN_4BYTE_ADDR = 0xB7,
-    case PP4:
+-    ERASE_SECTOR = 0xd8,
-    case PP4_4:
+-};
-    case QPP_4:
+-
-@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
+-#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
-                           " by device\n");
+-#define FLASH_PAGE_SIZE           256
-         }
+-
-         break;
+-typedef struct TestData {
-+
+-    QTestState *s;
-+    case RDSFDP:
+-    uint64_t spi_base;
-+        s->state = STATE_READING_SFDP;
+-    uint64_t flash_base;
-+        break;
+-    uint32_t jedec_id;
-+
+-    char *tmp_path;
-     default:
+-    uint8_t cs;
-         break;
+-    const char *node;
-     }
+-    uint32_t page_addr;
-@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
+-} TestData;
-             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
+-
-         }
+-/*
-         break;
+- * Use an explicit bswap for the values read/wrote to the flash region
-+    case RDSFDP:
+- * as they are BE and the Aspeed CPU is LE.
-+        if (s->pi->sfdp_read) {
+- */
-+            s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
+-static inline uint32_t make_be32(uint32_t data)
-+            s->pos = 0;
+-{
-+            s->len = 0;
+-    return bswap32(data);
-+            s->state = STATE_COLLECTING_DATA;
+-}
-+            break;
+-
-+        }
+-static inline void spi_writel(const TestData *data, uint64_t offset,
-+        /* Fallthrough */
+-                              uint32_t value)
-+
+-{
-     default:
+-    qtest_writel(data->s, data->spi_base + offset, value);
-         s->pos = 0;
+-}
-         s->len = 1;
+-
-@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
+-static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
-             }
+-{
-         }
+-    return qtest_readl(data->s, data->spi_base + offset);
-         break;
+-}
-+    case STATE_READING_SFDP:
+-
-+        assert(s->pi->sfdp_read);
+-static inline void flash_writeb(const TestData *data, uint64_t offset,
-+        r = s->pi->sfdp_read(s->cur_addr);
+-                                uint8_t value)
-+        trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
+-{
-+        s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
+-    qtest_writeb(data->s, data->flash_base + offset, value);
-+        break;
+-}
+-
-     default:
+-static inline void flash_writel(const TestData *data, uint64_t offset,
-     case STATE_IDLE:
+-                                uint32_t value)
-diff --git a/MAINTAINERS b/MAINTAINERS
+-{
 -    qtest_writel(data->s, data->flash_base + offset, value);
 -}
 -
 -static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
 -{
 -    return qtest_readb(data->s, data->flash_base + offset);
 -}
 -
 -static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
 -{
 -    return qtest_readl(data->s, data->flash_base + offset);
 -}
 -
 -static void spi_conf(const TestData *data, uint32_t value)
 -{
 -    uint32_t conf = spi_readl(data, R_CONF);
 -
 -    conf |= value;
 -    spi_writel(data, R_CONF, conf);
 -}
 -
 -static void spi_conf_remove(const TestData *data, uint32_t value)
 -{
 -    uint32_t conf = spi_readl(data, R_CONF);
 -
 -    conf &= ~value;
 -    spi_writel(data, R_CONF, conf);
 -}
 -
 -static void spi_ce_ctrl(const TestData *data, uint32_t value)
 -{
 -    uint32_t conf = spi_readl(data, R_CE_CTRL);
 -
 -    conf |= value;
 -    spi_writel(data, R_CE_CTRL, conf);
 -}
 -
 -static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
 -{
 -    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 -    uint32_t ctrl = spi_readl(data, ctrl_reg);
 -    ctrl &= ~(CTRL_USERMODE | 0xff << 16);
 -    ctrl |= mode | (cmd << 16);
 -    spi_writel(data, ctrl_reg, ctrl);
 -}
 -
 -static void spi_ctrl_start_user(const TestData *data)
 -{
 -    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 -    uint32_t ctrl = spi_readl(data, ctrl_reg);
 -
 -    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, ctrl_reg, ctrl);
 -
 -    ctrl &= ~CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, ctrl_reg, ctrl);
 -}
 -
 -static void spi_ctrl_stop_user(const TestData *data)
 -{
 -    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 -    uint32_t ctrl = spi_readl(data, ctrl_reg);
 -
 -    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
 -    spi_writel(data, ctrl_reg, ctrl);
 -}
 -
 -static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
 -{
 -    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
 -    uint32_t ctrl = spi_readl(data, ctrl_reg);
 -    uint32_t mode;
 -
 -    mode = value & CTRL_IO_MODE_MASK;
 -    ctrl &= ~CTRL_IO_MODE_MASK;
 -    ctrl |= mode;
 -    spi_writel(data, ctrl_reg, ctrl);
 -}
 -
 -static void flash_reset(const TestData *data)
 -{
 -    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
 -
 -    spi_ctrl_start_user(data);
 -    flash_writeb(data, 0, RESET_ENABLE);
 -    flash_writeb(data, 0, RESET_MEMORY);
 -    flash_writeb(data, 0, WREN);
 -    flash_writeb(data, 0, BULK_ERASE);
 -    flash_writeb(data, 0, WRDI);
 -    spi_ctrl_stop_user(data);
 -
 -    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
 -}
 -
 -static void test_read_jedec(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t jedec = 0x0;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, JEDEC_READ);
 -    jedec |= flash_readb(test_data, 0) << 16;
 -    jedec |= flash_readb(test_data, 0) << 8;
 -    jedec |= flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -
 -    flash_reset(test_data);
 -
 -    g_assert_cmphex(jedec, ==, test_data->jedec_id);
 -}
 -
 -static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
 -{
 -    int i;
 -
 -    spi_ctrl_start_user(data);
 -
 -    flash_writeb(data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(data, 0, READ);
 -    flash_writel(data, 0, make_be32(addr));
 -
 -    /* Continuous read are supported */
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        page[i] = make_be32(flash_readl(data, 0));
 -    }
 -    spi_ctrl_stop_user(data);
 -}
 -
 -static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page)
 -{
 -    int i;
 -
 -    /* move out USER mode to use direct reads from the AHB bus */
 -    spi_ctrl_setmode(data, CTRL_READMODE, READ);
 -
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        page[i] = make_be32(flash_readl(data, addr + i * 4));
 -    }
 -}
 -
 -static void write_page_mem(const TestData *data, uint32_t addr,
 -                           uint32_t write_value)
 -{
 -    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
 -
 -    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(data, addr + i * 4, write_value);
 -    }
 -}
 -
 -static void assert_page_mem(const TestData *data, uint32_t addr,
 -                            uint32_t expected_value)
 -{
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    read_page_mem(data, addr, page);
 -    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, expected_value);
 -    }
 -}
 -
 -static void test_erase_sector(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t some_page_addr = test_data->page_addr;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    int i;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    /*
 -     * Previous page should be full of 0xffs after backend is
 -     * initialized
 -     */
 -    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, PP);
 -    flash_writel(test_data, 0, make_be32(some_page_addr));
 -
 -    /* Fill the page with its own addresses */
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
 -    }
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check the page is correctly written */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
 -    }
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, ERASE_SECTOR);
 -    flash_writel(test_data, 0, make_be32(some_page_addr));
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check the page is erased */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_erase_all(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t some_page_addr = test_data->page_addr;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    int i;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    /*
 -     * Previous page should be full of 0xffs after backend is
 -     * initialized
 -     */
 -    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, PP);
 -    flash_writel(test_data, 0, make_be32(some_page_addr));
 -
 -    /* Fill the page with its own addresses */
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
 -    }
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check the page is correctly written */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
 -    }
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, BULK_ERASE);
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check the page is erased */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_write_page(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t my_page_addr = test_data->page_addr;
 -    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    int i;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, PP);
 -    flash_writel(test_data, 0, make_be32(my_page_addr));
 -
 -    /* Fill the page with its own addresses */
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 -    }
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check what was written */
 -    read_page(test_data, my_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 -    }
 -
 -    /* Check some other page. It should be full of 0xff */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_read_page_mem(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t my_page_addr = test_data->page_addr;
 -    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    int i;
 -
 -    /*
 -     * Enable 4BYTE mode for controller.
 -     */
 -    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 -
 -    /* Enable 4BYTE mode for flash. */
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, PP);
 -    flash_writel(test_data, 0, make_be32(my_page_addr));
 -
 -    /* Fill the page with its own addresses */
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 -    }
 -    spi_ctrl_stop_user(test_data);
 -    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    /* Check what was written */
 -    read_page_mem(test_data, my_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 -    }
 -
 -    /* Check some other page. It should be full of 0xff */
 -    read_page_mem(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_write_page_mem(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t my_page_addr = test_data->page_addr;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    int i;
 -
 -    /*
 -     * Enable 4BYTE mode for controller.
 -     */
 -    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 -
 -    /* Enable 4BYTE mode for flash. */
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* move out USER mode to use direct writes to the AHB bus */
 -    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
 -
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, my_page_addr + i * 4,
 -               make_be32(my_page_addr + i * 4));
 -    }
 -
 -    /* Check what was written */
 -    read_page_mem(test_data, my_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_read_status_reg(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint8_t r;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -
 -    g_assert_cmphex(r & SR_WEL, ==, 0);
 -    g_assert(!qtest_qom_get_bool
 -            (test_data->s, test_data->node, "write-enable"));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -
 -    g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
 -    g_assert(qtest_qom_get_bool
 -            (test_data->s, test_data->node, "write-enable"));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WRDI);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -
 -    g_assert_cmphex(r & SR_WEL, ==, 0);
 -    g_assert(!qtest_qom_get_bool
 -            (test_data->s, test_data->node, "write-enable"));
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_status_reg_write_protection(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint8_t r;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    /* default case: WP# is high and SRWD is low -> status register writable */
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    /* test ability to write SRWD */
 -    flash_writeb(test_data, 0, WRSR);
 -    flash_writeb(test_data, 0, SRWD);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -    g_assert_cmphex(r & SRWD, ==, SRWD);
 -
 -    /* WP# high and SRWD high -> status register writable */
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    /* test ability to write SRWD */
 -    flash_writeb(test_data, 0, WRSR);
 -    flash_writeb(test_data, 0, 0);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -    g_assert_cmphex(r & SRWD, ==, 0);
 -
 -    /* WP# low and SRWD low -> status register writable */
 -    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, WREN);
 -    /* test ability to write SRWD */
 -    flash_writeb(test_data, 0, WRSR);
 -    flash_writeb(test_data, 0, SRWD);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -    g_assert_cmphex(r & SRWD, ==, SRWD);
 -
 -    /* WP# low and SRWD high -> status register NOT writable */
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0 , WREN);
 -    /* test ability to write SRWD */
 -    flash_writeb(test_data, 0, WRSR);
 -    flash_writeb(test_data, 0, 0);
 -    flash_writeb(test_data, 0, RDSR);
 -    r = flash_readb(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -    /* write is not successful */
 -    g_assert_cmphex(r & SRWD, ==, SRWD);
 -
 -    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
 -    flash_reset(test_data);
 -}
 -
 -static void test_write_block_protect(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t sector_size = 65536;
 -    uint32_t n_sectors = 512;
 -
 -    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    uint32_t bp_bits = 0b0;
 -
 -    for (int i = 0; i < 16; i++) {
 -        bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
 -
 -        spi_ctrl_start_user(test_data);
 -        flash_writeb(test_data, 0, WREN);
 -        flash_writeb(test_data, 0, BULK_ERASE);
 -        flash_writeb(test_data, 0, WREN);
 -        flash_writeb(test_data, 0, WRSR);
 -        flash_writeb(test_data, 0, bp_bits);
 -        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -        flash_writeb(test_data, 0, WREN);
 -        spi_ctrl_stop_user(test_data);
 -
 -        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
 -        uint32_t protection_start = n_sectors - num_protected_sectors;
 -        uint32_t protection_end = n_sectors;
 -
 -        for (int sector = 0; sector < n_sectors; sector++) {
 -            uint32_t addr = sector * sector_size;
 -
 -            assert_page_mem(test_data, addr, 0xffffffff);
 -            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 -
 -            uint32_t expected_value = protection_start <= sector
 -                                      && sector < protection_end
 -                                      ? 0xffffffff : 0xabcdef12;
 -
 -            assert_page_mem(test_data, addr, expected_value);
 -        }
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_write_block_protect_bottom_bit(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t sector_size = 65536;
 -    uint32_t n_sectors = 512;
 -
 -    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    /* top bottom bit is enabled */
 -    uint32_t bp_bits = 0b00100 << 3;
 -
 -    for (int i = 0; i < 16; i++) {
 -        bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
 -
 -        spi_ctrl_start_user(test_data);
 -        flash_writeb(test_data, 0, WREN);
 -        flash_writeb(test_data, 0, BULK_ERASE);
 -        flash_writeb(test_data, 0, WREN);
 -        flash_writeb(test_data, 0, WRSR);
 -        flash_writeb(test_data, 0, bp_bits);
 -        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -        flash_writeb(test_data, 0, WREN);
 -        spi_ctrl_stop_user(test_data);
 -
 -        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
 -        uint32_t protection_start = 0;
 -        uint32_t protection_end = num_protected_sectors;
 -
 -        for (int sector = 0; sector < n_sectors; sector++) {
 -            uint32_t addr = sector * sector_size;
 -
 -            assert_page_mem(test_data, addr, 0xffffffff);
 -            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 -
 -            uint32_t expected_value = protection_start <= sector
 -                                      && sector < protection_end
 -                                      ? 0xffffffff : 0xabcdef12;
 -
 -            assert_page_mem(test_data, addr, expected_value);
 -        }
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_write_page_qpi(const void *data)
 -{
 -    const TestData *test_data = (const TestData *)data;
 -    uint32_t my_page_addr = test_data->page_addr;
 -    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
 -    uint32_t page[FLASH_PAGE_SIZE / 4];
 -    uint32_t page_pattern[] = {
 -        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
 -    };
 -    int i;
 -
 -    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 -
 -    spi_ctrl_start_user(test_data);
 -    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
 -    flash_writeb(test_data, 0, WREN);
 -    flash_writeb(test_data, 0, PP);
 -    flash_writel(test_data, 0, make_be32(my_page_addr));
 -
 -    /* Set QPI mode */
 -    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
 -
 -    /* Fill the page pattern */
 -    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 -        flash_writel(test_data, 0, make_be32(page_pattern[i]));
 -    }
 -
 -    /* Fill the page with its own addresses */
 -    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 -        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
 -    }
 -
 -    /* Restore io mode */
 -    spi_ctrl_set_io_mode(test_data, 0);
 -    spi_ctrl_stop_user(test_data);
 -
 -    /* Check what was written */
 -    read_page(test_data, my_page_addr, page);
 -    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
 -        g_assert_cmphex(page[i], ==, page_pattern[i]);
 -    }
 -    for (; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
 -    }
 -
 -    /* Check some other page. It should be full of 0xff */
 -    read_page(test_data, some_page_addr, page);
 -    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
 -        g_assert_cmphex(page[i], ==, 0xffffffff);
 -    }
 -
 -    flash_reset(test_data);
 -}
 -
 -static void test_palmetto_bmc(TestData *data)
 +static void test_palmetto_bmc(AspeedSMCTestData *data)
  {
      int ret;
      int fd;
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
      /* beyond 16MB */
      data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 -    qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
 -    qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
 -    qtest_add_data_func("/ast2400/smc/erase_all",  data, test_erase_all);
 -    qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast2400/smc/read_jedec",
 +                        data, aspeed_smc_test_read_jedec);
 +    qtest_add_data_func("/ast2400/smc/erase_sector",
 +                        data, aspeed_smc_test_erase_sector);
 +    qtest_add_data_func("/ast2400/smc/erase_all",
 +                        data, aspeed_smc_test_erase_all);
 +    qtest_add_data_func("/ast2400/smc/write_page",
 +                        data, aspeed_smc_test_write_page);
      qtest_add_data_func("/ast2400/smc/read_page_mem",
 -                        data, test_read_page_mem);
 +                        data, aspeed_smc_test_read_page_mem);
      qtest_add_data_func("/ast2400/smc/write_page_mem",
 -                        data, test_write_page_mem);
 +                        data, aspeed_smc_test_write_page_mem);
      qtest_add_data_func("/ast2400/smc/read_status_reg",
 -                        data, test_read_status_reg);
 +                        data, aspeed_smc_test_read_status_reg);
      qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
 -                        data, test_status_reg_write_protection);
 +                        data, aspeed_smc_test_status_reg_write_protection);
      qtest_add_data_func("/ast2400/smc/write_block_protect",
 -                        data, test_write_block_protect);
 +                        data, aspeed_smc_test_write_block_protect);
      qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
 -                        data, test_write_block_protect_bottom_bit);
 +                        data, aspeed_smc_test_write_block_protect_bottom_bit);
  }
 -static void test_ast2500_evb(TestData *data)
 +static void test_ast2500_evb(AspeedSMCTestData *data)
  {
      int ret;
      int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
      /* beyond 16MB */
      data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 -    qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
 -    qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector);
 -    qtest_add_data_func("/ast2500/smc/erase_all",  data, test_erase_all);
 -    qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast2500/smc/read_jedec",
 +                        data, aspeed_smc_test_read_jedec);
 +    qtest_add_data_func("/ast2500/smc/erase_sector",
 +                        data, aspeed_smc_test_erase_sector);
 +    qtest_add_data_func("/ast2500/smc/erase_all",
 +                        data, aspeed_smc_test_erase_all);
 +    qtest_add_data_func("/ast2500/smc/write_page",
 +                        data, aspeed_smc_test_write_page);
      qtest_add_data_func("/ast2500/smc/read_page_mem",
 -                        data, test_read_page_mem);
 +                        data, aspeed_smc_test_read_page_mem);
      qtest_add_data_func("/ast2500/smc/write_page_mem",
 -                        data, test_write_page_mem);
 +                        data, aspeed_smc_test_write_page_mem);
      qtest_add_data_func("/ast2500/smc/read_status_reg",
 -                        data, test_read_status_reg);
 +                        data, aspeed_smc_test_read_status_reg);
      qtest_add_data_func("/ast2500/smc/write_page_qpi",
 -                        data, test_write_page_qpi);
 +                        data, aspeed_smc_test_write_page_qpi);
  }
 -static void test_ast2600_evb(TestData *data)
 +static void test_ast2600_evb(AspeedSMCTestData *data)
  {
      int ret;
      int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
      /* beyond 16MB */
      data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 -    qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
 -    qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector);
 -    qtest_add_data_func("/ast2600/smc/erase_all",  data, test_erase_all);
 -    qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast2600/smc/read_jedec",
 +                        data, aspeed_smc_test_read_jedec);
 +    qtest_add_data_func("/ast2600/smc/erase_sector",
 +                        data, aspeed_smc_test_erase_sector);
 +    qtest_add_data_func("/ast2600/smc/erase_all",
 +                        data, aspeed_smc_test_erase_all);
 +    qtest_add_data_func("/ast2600/smc/write_page",
 +                        data, aspeed_smc_test_write_page);
      qtest_add_data_func("/ast2600/smc/read_page_mem",
 -                        data, test_read_page_mem);
 +                        data, aspeed_smc_test_read_page_mem);
      qtest_add_data_func("/ast2600/smc/write_page_mem",
 -                        data, test_write_page_mem);
 +                        data, aspeed_smc_test_write_page_mem);
      qtest_add_data_func("/ast2600/smc/read_status_reg",
 -                        data, test_read_status_reg);
 +                        data, aspeed_smc_test_read_status_reg);
      qtest_add_data_func("/ast2600/smc/write_page_qpi",
 -                        data, test_write_page_qpi);
 +                        data, aspeed_smc_test_write_page_qpi);
  }
 -static void test_ast1030_evb(TestData *data)
 +static void test_ast1030_evb(AspeedSMCTestData *data)
  {
      int ret;
      int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data)
      /* beyond 512KB */
      data->page_addr = 0x800 * FLASH_PAGE_SIZE;
 -    qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
 -    qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector);
 -    qtest_add_data_func("/ast1030/smc/erase_all",  data, test_erase_all);
 -    qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
 +    qtest_add_data_func("/ast1030/smc/read_jedec",
 +                        data, aspeed_smc_test_read_jedec);
 +    qtest_add_data_func("/ast1030/smc/erase_sector",
 +                        data, aspeed_smc_test_erase_sector);
 +    qtest_add_data_func("/ast1030/smc/erase_all",
 +                        data, aspeed_smc_test_erase_all);
 +    qtest_add_data_func("/ast1030/smc/write_page",
 +                        data, aspeed_smc_test_write_page);
      qtest_add_data_func("/ast1030/smc/read_page_mem",
 -                        data, test_read_page_mem);
 +                        data, aspeed_smc_test_read_page_mem);
      qtest_add_data_func("/ast1030/smc/write_page_mem",
 -                        data, test_write_page_mem);
 +                        data, aspeed_smc_test_write_page_mem);
      qtest_add_data_func("/ast1030/smc/read_status_reg",
 -                        data, test_read_status_reg);
 +                        data, aspeed_smc_test_read_status_reg);
      qtest_add_data_func("/ast1030/smc/write_page_qpi",
 -                        data, test_write_page_qpi);
 +                        data, aspeed_smc_test_write_page_qpi);
  }
  int main(int argc, char **argv)
  {
 -    TestData palmetto_data;
 -    TestData ast2500_evb_data;
 -    TestData ast2600_evb_data;
 -    TestData ast1030_evb_data;
 +    AspeedSMCTestData palmetto_data;
 +    AspeedSMCTestData ast2500_evb_data;
 +    AspeedSMCTestData ast2600_evb_data;
 +    AspeedSMCTestData ast1030_evb_data;
      int ret;
      g_test_init(&argc, &argv, NULL);
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/tests/qtest/meson.build
-+++ b/MAINTAINERS
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ SSI
+@@ -XXX,XX +XXX,XX @@ qtests = {
- M: Alistair Francis <alistair@alistair23.me>
+   'virtio-net-failover': files('migration-helpers.c'),
- S: Maintained
+   'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
- F: hw/ssi/*
+   'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
--F: hw/block/m25p80.c
++  'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
-+F: hw/block/m25p80*
+ }
- F: include/hw/ssi/ssi.h
- X: hw/ssi/xilinx_*
+ if vnc.found()
  F: tests/qtest/m25p80-test.c
 diff --git a/hw/block/trace-events b/hw/block/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/trace-events
 +++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_a
  m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
  m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
  m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
 +m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
  m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
  m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
 --
-.37.3
+.47.1

-[PULL 08/16] m25p80: Add the n25q256a SFDP table
+[PULL 24/24] test/qtest/ast2700-smc-test: Support to test AST2700
-The same values were collected on 4 differents OpenPower systems,
+From: Jamin Lin <jamin_lin@aspeedtech.com>
 palmettos, romulus and tacoma.
-The SFDP table size is defined as being 0x100 bytes but it could be
+Add test_ast2700_evb function and reused testcases which are from
-bigger. Only the mandatory table for basic features is available at
+aspeed_smc-test.c for AST2700 testing. The base address, flash base address
-byte 0x30.
+and ce index of fmc_cs0 are 0x14000000, 0x100000000 and 0, respectively.
 The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB,
 so set jedec_id 0xef4021.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
-Message-Id: <20220722063602.128144-3-clg@kaod.org>
+Reviewed-by: Cédric Le Goater <clg@redhat.com>
-Message-Id: <20221013161241.2805140-3-clg@kaod.org>
+Link: https://lore.kernel.org/r/20241127091543.1243114-11-jamin_lin@aspeedtech.com
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
+Signed-off-by: Cédric Le Goater <clg@redhat.com>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ tests/qtest/ast2700-smc-test.c | 71 ++++++++++++++++++++++++++++++++++
- hw/block/m25p80.c      |  8 +++---
+ tests/qtest/meson.build        |  4 +-
- hw/block/m25p80_sfdp.c | 58 ++++++++++++++++++++++++++++++++++++++++++
+files changed, 74 insertions(+), 1 deletion(-)
- hw/block/meson.build   |  1 +
+ create mode 100644 tests/qtest/ast2700-smc-test.c
 files changed, 66 insertions(+), 3 deletions(-)
  create mode 100644 hw/block/m25p80_sfdp.c
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/tests/qtest/ast2700-smc-test.c b/tests/qtest/ast2700-smc-test.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.h
 +++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
   */
  #define M25P80_SFDP_MAX_SIZE  (1 << 24)
 +uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
 +
  #endif
 diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80.c
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, ER_4K) },
      { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, ER_4K) },
      { INFO("n25q256a11",  0x20bb19,      0,  64 << 10, 512, ER_4K) },
 -    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K) },
 +    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K),
 +      .sfdp_read = m25p80_sfdp_n25q256a },
      { INFO("n25q512a11",  0x20bb20,      0,  64 << 10, 1024, ER_4K) },
      { INFO("n25q512a13",  0x20ba20,      0,  64 << 10, 1024, ER_4K) },
      { INFO("n25q128",     0x20ba18,      0,  64 << 10, 256, 0) },
      { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512,
 -           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB) },
 -    { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
 +           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
 +      .sfdp_read = m25p80_sfdp_n25q256a },
 +   { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
      { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
      { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
      { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/block/m25p80_sfdp.c
++++ b/tests/qtest/ast2700-smc-test.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * M25P80 Serial Flash Discoverable Parameter (SFDP)
++ * QTest testcase for the M25P80 Flash using the ASPEED SPI Controller since
 + * AST2700.
 + *
-+ * Copyright (c) 2020, IBM Corporation.
++ * SPDX-License-Identifier: GPL-2.0-or-later
-+ *
++ * Copyright (C) 2024 ASPEED Technology Inc.
 + * This code is licensed under the GPL version 2 or later. See the
 + * COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qemu/host-utils.h"
++#include "qemu/bswap.h"
-+#include "m25p80_sfdp.h"
++#include "libqtest-single.h"
 +#include "qemu/bitops.h"
 +#include "aspeed-smc-utils.h"
 +
-+#define define_sfdp_read(model)                                       \
++static void test_ast2700_evb(AspeedSMCTestData *data)
-+    uint8_t m25p80_sfdp_##model(uint32_t addr)                        \
++{
-+    {                                                                 \
++    int ret;
-+        assert(is_power_of_2(sizeof(sfdp_##model)));                  \
++    int fd;
 +        return sfdp_##model[addr & (sizeof(sfdp_##model) - 1)];       \
 +    }
 +
-+/*
++    fd = g_file_open_tmp("qtest.m25p80.w25q01jvq.XXXXXX",
-+ * Micron
++                         &data->tmp_path, NULL);
-+ */
++    g_assert(fd >= 0);
-+static const uint8_t sfdp_n25q256a[] = {
++    ret = ftruncate(fd, 128 * 1024 * 1024);
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
++    g_assert(ret == 0);
-+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
++    close(fd);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->s = qtest_initf("-machine ast2700-evb "
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                          "-drive file=%s,format=raw,if=mtd",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                          data->tmp_path);
-+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
++
-+    0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
++    /* fmc cs0 with w25q01jvq flash */
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
++    data->flash_base = 0x100000000;
-+    0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
++    data->spi_base = 0x14000000;
-+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
++    data->jedec_id = 0xef4021;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->cs = 0;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->node = "/machine/soc/fmc/ssi.0/child[0]";
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /* beyond 64MB */
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    data->page_addr = 0x40000 * FLASH_PAGE_SIZE;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/read_jedec",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_read_jedec);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/erase_sector",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_erase_sector);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/erase_all",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_erase_all);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/write_page",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_write_page);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/read_page_mem",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_read_page_mem);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/write_page_mem",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_write_page_mem);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/read_status_reg",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_read_status_reg);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    qtest_add_data_func("/ast2700/smc/write_page_qpi",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                        data, aspeed_smc_test_write_page_qpi);
-+};
++}
-+define_sfdp_read(n25q256a);
++
-diff --git a/hw/block/meson.build b/hw/block/meson.build
++int main(int argc, char **argv)
 +{
 +    AspeedSMCTestData ast2700_evb_data;
 +    int ret;
 +
 +    g_test_init(&argc, &argv, NULL);
 +
 +    test_ast2700_evb(&ast2700_evb_data);
 +    ret = g_test_run();
 +
 +    qtest_quit(ast2700_evb_data.s);
 +    unlink(ast2700_evb_data.tmp_path);
 +    return ret;
 +}
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/meson.build
+--- a/tests/qtest/meson.build
-+++ b/hw/block/meson.build
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ONENAND', if_true: files('onenand.c'))
+@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
- softmmu_ss.add(when: 'CONFIG_PFLASH_CFI01', if_true: files('pflash_cfi01.c'))
+    'aspeed_smc-test',
- softmmu_ss.add(when: 'CONFIG_PFLASH_CFI02', if_true: files('pflash_cfi02.c'))
+    'aspeed_gpio-test']
- softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
+ qtests_aspeed64 = \
-+softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80_sfdp.c'))
+-  ['ast2700-gpio-test']
- softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
++  ['ast2700-gpio-test',
- softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
++   'ast2700-smc-test']
- softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c'))
  qtests_stm32l4x5 = \
    ['stm32l4x5_exti-test',
@@ -XXX,XX +XXX,XX @@ qtests = {
    'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
    'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
    'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
 +  'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'),
  }
  if vnc.found()
 --
-.37.3
+.47.1

The following changes since commit 0529245488865038344d64fff7ee05864d3d17f6:

Merge tag 'pull-target-arm-20221020' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-10-20 14:36:12 -0400)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20221025

for you to fetch changes up to 703229132bb05327044368fc6d19f6acf7dde848:

arm/aspeed: Replace mx25l25635e chip model (2022-10-24 11:20:16 +0200)

----------------------------------------------------------------
aspeed queue :

* Performance improvement with Object class caching
* Serial Flash Discovery Parameters support for m25p80 device
* Various small adjustments on intructions and models

----------------------------------------------------------------
Alex Bennée (1):
      ssi: cache SSIPeripheralClass to avoid GET_CLASS()

Cédric Le Goater (12):
      tests/avocado/machine_aspeed.py: Fix typos on buildroot
      aspeed/smc: Cache AspeedSMCClass
      ast2600: Drop NEON from the CPU features
      m25p80: Add basic support for the SFDP command
      m25p80: Add the n25q256a SFDP table
      m25p80: Add erase size for mx25l25635e
      m25p80: Add the mx25l25635e SFPD table
      m25p80: Add the mx25l25635f SFPD table
      m25p80: Add the mx66l1g45g SFDP table
      m25p80: Add the w25q256 SFPD table
      m25p80: Add the w25q512jv SFPD table
      arm/aspeed: Replace mx25l25635e chip model

Patrick Williams (2):
      hw/arm/aspeed: increase Bletchley memory size
      m25p80: Add the w25q01jvq SFPD table

Peter Delevoryas (1):
      hw/i2c/aspeed: Fix old reg slave receive

From: Peter Delevoryas <peter@pjd.dev>

I think when Klaus ported his slave mode changes from the original patch
series to the rewritten I2C module, he changed the behavior of the first
byte that is received by the slave device.

What's supposed to happen is that the AspeedI2CBus's slave device's
i2c_event callback should run, and if the event is "send_async", then it
should populate the byte buffer with the 8-bit I2C address that is being
sent to. Since we only support "send_async", the lowest bit should
always be 0 (indicating that the master is requesting to send data).

This is the code Klaus had previously, for reference. [1]

switch (event) {
    case I2C_START_SEND:
        bus->buf = bus->dev_addr << 1;

bus->buf &= I2CD_BYTE_BUF_RX_MASK;
        bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT;

bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE);
        aspeed_i2c_set_state(bus, I2CD_STXD);

break;

[1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/

Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Message-Id: <20220820225712.713209-2-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/i2c/aspeed_i2c.h | 1 +
 hw/i2c/aspeed_i2c.c         | 8 +++++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -XXX,XX +XXX,XX @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
     SHARED_FIELD(M_TX_CMD, 1, 1)
     SHARED_FIELD(M_START_CMD, 0, 1)
 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
+    SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
     SHARED_FIELD(RX_COUNT, 24, 5)
     SHARED_FIELD(RX_SIZE, 16, 5)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
     AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
     uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
     uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
-    uint32_t value;
+    uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
+    uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
+                                                SLAVE_DEV_ADDR1);
 
     if (aspeed_i2c_is_new_mode(bus->controller)) {
         return aspeed_i2c_bus_new_slave_event(bus, event);
@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
 
     switch (event) {
     case I2C_START_SEND_ASYNC:
-        value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
-        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << 1);
+        /* Bit[0] == 0 indicates "send". */
+        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
 
         ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
         SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
-- 
2.37.3

Replace 'buidroot' and 'builroot' by 'buildroot'.

Fixes: f7bc7da0724f ("test/avocado/machine_aspeed.py: Add tests using buildroot images")
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220923084803.498337-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
 
         self.do_test_arm_aspeed(image_path)
 
-    def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
+    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
         self.require_netdev('user')
 
         self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
         exec_command(self, 'root')
         time.sleep(0.1)
 
-    def do_test_arm_aspeed_buidroot_poweroff(self):
+    def do_test_arm_aspeed_buildroot_poweroff(self):
         exec_command_and_wait_for_pattern(self, 'poweroff',
                                           'reboot: System halted');
 
-    def test_arm_ast2500_evb_builroot(self):
+    def test_arm_ast2500_evb_buildroot(self):
         """
         :avocado: tags=arch:arm
         :avocado: tags=machine:ast2500-evb
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
 
         self.vm.add_args('-device',
                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-        self.do_test_arm_aspeed_buidroot_start(image_path, '0x0')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
         exec_command_and_wait_for_pattern(self,
                              'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
 
-        self.do_test_arm_aspeed_buidroot_poweroff()
+        self.do_test_arm_aspeed_buildroot_poweroff()
 
-    def test_arm_ast2600_evb_builroot(self):
+    def test_arm_ast2600_evb_buildroot(self):
         """
         :avocado: tags=arch:arm
         :avocado: tags=machine:ast2600-evb
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
         self.vm.add_args('-device',
                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
-        self.do_test_arm_aspeed_buidroot_start(image_path, '0xf00')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
         year = time.strftime("%Y")
         exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
 
-        self.do_test_arm_aspeed_buidroot_poweroff()
+        self.do_test_arm_aspeed_buildroot_poweroff()
 
 
 class AST2x00MachineSDK(QemuSystemTest):
-- 
2.37.3

From: Alex Bennée <alex.bennee@linaro.org>

Investigating why some BMC models are so slow compared to a plain ARM
virt machines I did some profiling of:

./qemu-system-arm -M romulus-bmc -nic user \
    -drive
    file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
    -nographic -serial mon:stdio

And saw that object_class_dynamic_cast_assert was dominating the
profile times. We have a number of cases in this model of the SSI bus.
As the class is static once the object is created we just cache it and
use it instead of the dynamic case macros.

Profiling against:

./tests/venv/bin/avocado run \
    tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0

Before: 35.565 s ±  0.087 s
After: 15.713 s ±  0.287 s

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org>
Message-Id: <20220923084803.498337-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/ssi.h |  3 +++
 hw/ssi/ssi.c         | 18 ++++++++----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ struct SSIPeripheralClass {
 struct SSIPeripheral {
     DeviceState parent_obj;
 
+    /* cache the class */
+    SSIPeripheralClass *spc;
+
     /* Chip select state */
     bool cs;
 };
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
     bool cs = !!level;
     assert(n == 0);
     if (s->cs != cs) {
-        SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
-        if (ssc->set_cs) {
-            ssc->set_cs(s, cs);
+        if (s->spc->set_cs) {
+            s->spc->set_cs(s, cs);
         }
     }
     s->cs = cs;
@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
 
 static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
 {
-    SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
+    SSIPeripheralClass *ssc = dev->spc;
 
     if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
-            (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
-            ssc->cs_polarity == SSI_CS_NONE) {
+        (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
+        ssc->cs_polarity == SSI_CS_NONE) {
         return ssc->transfer(dev, val);
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
             ssc->cs_polarity != SSI_CS_NONE) {
         qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
     }
+    s->spc = ssc;
 
     ssc->realize(s, errp);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
 {
     BusState *b = BUS(bus);
     BusChild *kid;
-    SSIPeripheralClass *ssc;
     uint32_t r = 0;
 
     QTAILQ_FOREACH(kid, &b->children, sibling) {
-        SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
-        ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
-        r |= ssc->transfer_raw(peripheral, val);
+        SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
+        r |= p->spc->transfer_raw(p, val);
     }
 
     return r;
-- 
2.37.3

Store a reference on the AspeedSMC class under the flash object and
use it when accessing the flash contents. Avoiding the class cast
checkers in these hot paths improves performance by 10% when running
the aspeed avocado tests.

Message-Id: <20220923084803.498337-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/aspeed_smc.h | 2 ++
 hw/ssi/aspeed_smc.c         | 9 ++++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 struct AspeedSMCState;
+struct AspeedSMCClass;
 
 #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
 OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
@@ -XXX,XX +XXX,XX @@ struct AspeedSMCFlash {
     SysBusDevice parent_obj;
 
     struct AspeedSMCState *controller;
+    struct AspeedSMCClass *asc;
     uint8_t cs;
 
     MemoryRegion mmio;
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
 {
     const AspeedSMCState *s = fl->controller;
-    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+    AspeedSMCClass *asc = fl->asc;
 
     if (asc->addr_width) {
         return asc->addr_width(s);
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
                                               uint32_t addr)
 {
     const AspeedSMCState *s = fl->controller;
-    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+    AspeedSMCClass *asc = fl->asc;
     AspeedSegments seg;
 
     asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_smc_info = {
 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
 {
     AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
-    AspeedSMCClass *asc;
     g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
 
     if (!s->controller) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    asc = ASPEED_SMC_GET_CLASS(s->controller);
+    s->asc = ASPEED_SMC_GET_CLASS(s->controller);
 
     /*
      * Use the default segment value to size the memory region. This
      * can be changed by FW at runtime.
      */
     memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
-                          s, name, asc->segments[s->cs].size);
+                          s, name, s->asc->segments[s->cs].size);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 }
 
-- 
2.37.3

Currently, the CPU features exposed to the AST2600 QEMU machines are :

half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
  vfpd32 lpae evtstrm

But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
are :

half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
  lpae evtstrm

Drop NEON support in the Aspeed AST2600 SoC.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220928164719.655586-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast2600.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 
         object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
+        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+                                &error_abort);
         object_property_set_link(OBJECT(&s->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-- 
2.37.3

From: Patrick Williams <patrick@stwcx.xyz>

For the PVT-class hardware we have increased the memory size of
this device to 2 GiB.  Adjust the device model accordingly.

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
         aspeed_soc_num_cpus(amc->soc_name);
 };
 
+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+#if HOST_LONG_BITS == 32
+#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
+#else
+#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
+#endif
+
 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->macs_mask = ASPEED_MAC2_ON;
     amc->i2c_init  = bletchley_bmc_i2c_init;
-    mc->default_ram_size = 512 * MiB;
+    mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
     mc->default_cpus = mc->min_cpus = mc->max_cpus =
         aspeed_soc_num_cpus(amc->soc_name);
 }
-- 
2.37.3

JEDEC STANDARD JESD216 for Serial Flash Discovery Parameters (SFDP)
provides a mean to describe the features of a serial flash device
using a set of internal parameter tables.

This is the initial framework for the RDSFDP command giving access to
a private SFDP area under the flash. This area now needs to be
populated with the flash device characteristics, using a new
'sfdp_read' handler under FlashPartInfo.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-2-clg@kaod.org>
Message-Id: <20221013161241.2805140-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h | 18 ++++++++++++++++++
 hw/block/m25p80.c      | 27 +++++++++++++++++++++++++++
 MAINTAINERS            |  2 +-
 hw/block/trace-events  |  1 +
 4 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 hw/block/m25p80_sfdp.h

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * M25P80 SFDP
+ *
+ * Copyright (c) 2020, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef HW_M25P80_SFDP_H
+#define HW_M25P80_SFDP_H
+
+/*
+ * SFDP area has a 3 bytes address space.
+ */
+#define M25P80_SFDP_MAX_SIZE  (1 << 24)
+
+#endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "trace.h"
 #include "qom/object.h"
+#include "m25p80_sfdp.h"
 
 /* 16 MiB max in 3 byte address mode */
 #define MAX_3BYTES_SIZE 0x1000000
@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
      * This field inform how many die is in the chip.
      */
     uint8_t die_cnt;
+    uint8_t (*sfdp_read)(uint32_t sfdp_addr);
 } FlashPartInfo;
 
 /* adapted from linux */
@@ -XXX,XX +XXX,XX @@ typedef enum {
     BULK_ERASE = 0xc7,
     READ_FSR = 0x70,
     RDCR = 0x15,
+    RDSFDP = 0x5a,
 
     READ = 0x03,
     READ4 = 0x13,
@@ -XXX,XX +XXX,XX @@ typedef enum {
     STATE_COLLECTING_DATA,
     STATE_COLLECTING_VAR_LEN_DATA,
     STATE_READING_DATA,
+    STATE_READING_SFDP,
 } CMDState;
 
 typedef enum {
@@ -XXX,XX +XXX,XX @@ static inline int get_addr_length(Flash *s)
     }
 
    switch (s->cmd_in_progress) {
+   case RDSFDP:
+       return 3;
    case PP4:
    case PP4_4:
    case QPP_4:
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
                           " by device\n");
         }
         break;
+
+    case RDSFDP:
+        s->state = STATE_READING_SFDP;
+        break;
+
     default:
         break;
     }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
         }
         break;
+    case RDSFDP:
+        if (s->pi->sfdp_read) {
+            s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
+            s->pos = 0;
+            s->len = 0;
+            s->state = STATE_COLLECTING_DATA;
+            break;
+        }
+        /* Fallthrough */
+
     default:
         s->pos = 0;
         s->len = 1;
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
             }
         }
         break;
+    case STATE_READING_SFDP:
+        assert(s->pi->sfdp_read);
+        r = s->pi->sfdp_read(s->cur_addr);
+        trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
+        s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
+        break;
 
     default:
     case STATE_IDLE:
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ SSI
 M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/ssi/*
-F: hw/block/m25p80.c
+F: hw/block/m25p80*
 F: include/hw/ssi/ssi.h
 X: hw/ssi/xilinx_*
 F: tests/qtest/m25p80-test.c
diff --git a/hw/block/trace-events b/hw/block/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_a
 m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
 m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
 m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
+m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
 m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
 m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
-- 
2.37.3

The same values were collected on 4 differents OpenPower systems,
palmettos, romulus and tacoma.

The SFDP table size is defined as being 0x100 bytes but it could be
bigger. Only the mandatory table for basic features is available at
byte 0x30.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-3-clg@kaod.org>
Message-Id: <20221013161241.2805140-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  8 +++---
 hw/block/m25p80_sfdp.c | 58 ++++++++++++++++++++++++++++++++++++++++++
 hw/block/meson.build   |  1 +
 4 files changed, 66 insertions(+), 3 deletions(-)
 create mode 100644 hw/block/m25p80_sfdp.c

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
  */
 #define M25P80_SFDP_MAX_SIZE  (1 << 24)
 
+uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, ER_4K) },
     { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, ER_4K) },
     { INFO("n25q256a11",  0x20bb19,      0,  64 << 10, 512, ER_4K) },
-    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K) },
+    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K),
+      .sfdp_read = m25p80_sfdp_n25q256a },
     { INFO("n25q512a11",  0x20bb20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q512a13",  0x20ba20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q128",     0x20ba18,      0,  64 << 10, 256, 0) },
     { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512,
-           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB) },
-    { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
+           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
+      .sfdp_read = m25p80_sfdp_n25q256a },
+   { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
     { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
     { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * M25P80 Serial Flash Discoverable Parameter (SFDP)
+ *
+ * Copyright (c) 2020, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "m25p80_sfdp.h"
+
+#define define_sfdp_read(model)                                       \
+    uint8_t m25p80_sfdp_##model(uint32_t addr)                        \
+    {                                                                 \
+        assert(is_power_of_2(sizeof(sfdp_##model)));                  \
+        return sfdp_##model[addr & (sizeof(sfdp_##model) - 1)];       \
+    }
+
+/*
+ * Micron
+ */
+static const uint8_t sfdp_n25q256a[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
+    0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(n25q256a);
diff --git a/hw/block/meson.build b/hw/block/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/meson.build
+++ b/hw/block/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ONENAND', if_true: files('onenand.c'))
 softmmu_ss.add(when: 'CONFIG_PFLASH_CFI01', if_true: files('pflash_cfi01.c'))
 softmmu_ss.add(when: 'CONFIG_PFLASH_CFI02', if_true: files('pflash_cfi02.c'))
 softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
+softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80_sfdp.c'))
 softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
 softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
 softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c'))
-- 
2.37.3

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20221013161241.2805140-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
-    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512, 0) },
+    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
+            ER_4K | ER_32K) },
     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
-- 
2.37.3

The SFDP table is 0x80 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.

4B opcodes are not supported.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-4-clg@kaod.org>
Message-Id: <20221013161241.2805140-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  3 +++
 hw/block/m25p80.c      |  2 +-
 hw/block/m25p80_sfdp.c | 26 ++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
mx25l25635f has more capabilities reported in the SFDP table. Support
for 4B opcodes is of interest because it is exploited by the Linux
kernel.

The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-5-clg@kaod.org>
Message-Id: <20221013161241.2805140-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  1 +
 hw/block/m25p80.c      |  2 ++
 hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
 uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
 
 uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
     { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
             ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
+    { INFO6("mx25l25635f", 0xc22019,     0xc22019,  64 << 10, 512,
+            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635e[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx25l25635e)
+
+static const uint8_t sfdp_mx25l25635f[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
+    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xc2, 0xf5, 0x08, 0x0a,
+    0x08, 0x04, 0x03, 0x06, 0x00, 0x00, 0x07, 0x29,
+    0x17, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(mx25l25635f);
-- 
2.37.3

The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 plus some more Macronix specific
tables.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-6-clg@kaod.org>
Message-Id: <20221013161241.2805140-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 +-
 hw/block/m25p80.c      |  3 +-
 hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
 
 uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
 uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
-
+uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u1g45g",  0xc2253b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
-    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
+    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K),
+      .sfdp_read = m25p80_sfdp_mx66l1g45g },
 
     /* Micron */
     { INFO("n25q032a11",  0x20bb16,      0,  64 << 10,  64, ER_4K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635f[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx25l25635f);
+
+static const uint8_t sfdp_mx66l1g45g[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
+    0xc2, 0x00, 0x01, 0x04, 0x10, 0x01, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xc0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0xd6, 0x49, 0xc5, 0x00,
+    0x85, 0xdf, 0x04, 0xe3, 0x44, 0x03, 0x67, 0x38,
+    0x30, 0xb0, 0x30, 0xb0, 0xf7, 0xbd, 0xd5, 0x5c,
+    0x4a, 0x9e, 0x29, 0xff, 0xf0, 0x50, 0xf9, 0x85,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x7f, 0xef, 0xff, 0xff, 0x21, 0x5c, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xc2, 0xf5, 0x08, 0x00, 0x0c, 0x04, 0x08, 0x08,
+    0x01, 0x00, 0x19, 0x0f, 0x01, 0x01, 0x06, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(mx66l1g45g);
-- 
2.37.3

The SFDP table size is 0x100 bytes long. Only the mandatory table for
basic features is available at byte 0x80.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-7-clg@kaod.org>
Message-Id: <20221013161241.2805140-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
 uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
+uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
     { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
-    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
+    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q256 },
     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
 };
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx66l1g45g[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx66l1g45g);
+
+/*
+ * Windbond
+ */
+
+static const uint8_t sfdp_w25q256[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x80, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x21, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q256);
-- 
2.37.3

The SFDP table size is 0x100 bytes long. The mandatory table for basic
features is available at byte 0x80 and two extra Winbond specifics
table are available at 0xC0 and 0xF0.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-8-clg@kaod.org>
Message-Id: <20221013161241.2805140-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  1 +
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
 uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
     { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q256 },
-    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
+    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q512jv },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
 };
 
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q256[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(w25q256);
+
+static const uint8_t sfdp_w25q512jv[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
+    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
+    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q512jv);
-- 
2.37.3

From: Patrick Williams <patrick@stwcx.xyz>

Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
    hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
[ clg: removed extern ]
Message-Id: <20221006224424.3556372-1-patrick@stwcx.xyz>
Message-Id: <20221013161241.2805140-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 uint8_t m25p80_sfdp_w25q256(uint32_t addr);
 uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
+uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
       .sfdp_read = m25p80_sfdp_w25q256 },
     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q512jv },
-    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
+    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q01jvq },
 };
 
 typedef enum {
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q512jv[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(w25q512jv);
+
+static const uint8_t sfdp_w25q01jvq[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
+    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
+    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q01jvq);
-- 
2.37.3

A mx25l25635f chip model is generally found on these machines. It's
newer and uses 4B opcodes which is better to exercise the support in
the Linux kernel.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-9-clg@kaod.org>
Message-Id: <20221013161241.2805140-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
     amc->soc_name  = "ast2400-a1";
     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
     amc->fmc_model = "n25q256a";
-    amc->spi_model = "mx25l25635e";
+    amc->spi_model = "mx25l25635f";
     amc->num_cs    = 1;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size       = 256 * MiB;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
     amc->soc_name  = "ast2500-a1";
     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
     amc->fmc_model = "mx25l25635e";
-    amc->spi_model = "mx25l25635e";
+    amc->spi_model = "mx25l25635f";
     amc->num_cs    = 1;
     amc->i2c_init  = ast2500_evb_i2c_init;
     mc->default_ram_size       = 512 * MiB;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
     amc->soc_name  = "ast2500-a1";
     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
-    amc->fmc_model = "mx25l25635e";
+    amc->fmc_model = "mx25l25635f";
     amc->spi_model = "mx66l1g45g";
     amc->num_cs    = 2;
     amc->i2c_init  = witherspoon_bmc_i2c_init;
-- 
2.37.3

The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7:

Update version for v9.2.0 release (2024-12-10 16:20:54 +0000)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20241211

for you to fetch changes up to 124f4dc0d832c1bf3a4513c05a2b93bac0a5fac0:

test/qtest/ast2700-smc-test: Support to test AST2700 (2024-12-11 07:25:53 +0100)

----------------------------------------------------------------
aspeed queue:

* Removed tacoma-bmc machine
* Added support for SDHCI on AST2700 SoC
* Improved functional tests
* Extended SMC qtest to all Aspeed SoCs

----------------------------------------------------------------
Cédric Le Goater (8):
      arm: Remove tacoma-bmc machine
      tests/functional: Introduce a specific test for ast1030 SoC
      tests/functional: Introduce a specific test for palmetto-bmc machine
      tests/functional: Introduce a specific test for romulus-bmc machine
      tests/functional: Introduce a specific test for ast2500 SoC
      tests/functional: Introduce a specific test for ast2600 SoC
      tests/functional: Introduce a specific test for rainier-bmc machine
      tests/functional: Move debian boot test from avocado

Jamin Lin (16):
      hw/sd/aspeed_sdhci: Fix coding style
      hw/arm/aspeed: Fix coding style
      hw:sdhci: Introduce a new "capareg" class member to set the different Capability Registers
      hw/sd/aspeed_sdhci: Add AST2700 Support
      aspeed/soc: Support SDHCI for AST2700
      aspeed/soc: Support eMMC for AST2700
      test/qtest/aspeed_smc-test: Move testcases to test_palmetto_bmc function
      test/qtest/aspeed_smc-test: Introduce a new TestData to test different BMC SOCs
      test/qtest/aspeed_smc-test: Support to test all CE pins
      test/qtest/aspeed_smc-test: Introducing a "page_addr" data field
      test/qtest/aspeed_smc-test: Support to test AST2500
      test/qtest/aspeed_smc-test: Support to test AST2600
      test/qtest/aspeed_smc-test: Support to test AST1030
      test/qtest/aspeed_smc-test: Support write page command with QPI mode
      test/qtest: Introduce a new aspeed-smc-utils.c to place common testcases
      test/qtest/ast2700-smc-test: Support to test AST2700

docs/about/deprecated.rst                    |   8 -
 docs/about/removed-features.rst              |  10 +
 docs/system/arm/aspeed.rst                   |   1 -
 include/hw/sd/aspeed_sdhci.h                 |  13 +-
 tests/qtest/aspeed-smc-utils.h               |  95 ++++
 hw/arm/aspeed.c                              |  28 -
 hw/arm/aspeed_ast2400.c                      |   3 +-
 hw/arm/aspeed_ast2600.c                      |  10 +-
 hw/arm/aspeed_ast27x0.c                      |  35 ++
 hw/sd/aspeed_sdhci.c                         |  67 ++-
 tests/qtest/aspeed-smc-utils.c               | 686 ++++++++++++++++++++++++
 tests/qtest/aspeed_smc-test.c                | 775 ++++++---------------------
 tests/qtest/ast2700-smc-test.c               |  71 +++
 tests/avocado/boot_linux_console.py          |  26 -
 tests/functional/aspeed.py                   |  56 ++
 tests/functional/meson.build                 |  13 +-
 tests/functional/test_arm_aspeed.py          | 351 ------------
 tests/functional/test_arm_aspeed_ast1030.py  |  81 +++
 tests/functional/test_arm_aspeed_ast2500.py  |  59 ++
 tests/functional/test_arm_aspeed_ast2600.py  | 143 +++++
 tests/functional/test_arm_aspeed_palmetto.py |  24 +
 tests/functional/test_arm_aspeed_rainier.py  |  64 +++
 tests/functional/test_arm_aspeed_romulus.py  |  24 +
 tests/qtest/meson.build                      |   5 +-
 24 files changed, 1623 insertions(+), 1025 deletions(-)
 create mode 100644 tests/qtest/aspeed-smc-utils.h
 create mode 100644 tests/qtest/aspeed-smc-utils.c
 create mode 100644 tests/qtest/ast2700-smc-test.c
 create mode 100644 tests/functional/aspeed.py
 delete mode 100755 tests/functional/test_arm_aspeed.py
 create mode 100644 tests/functional/test_arm_aspeed_ast1030.py
 create mode 100644 tests/functional/test_arm_aspeed_ast2500.py
 create mode 100644 tests/functional/test_arm_aspeed_ast2600.py
 create mode 100644 tests/functional/test_arm_aspeed_palmetto.py
 create mode 100644 tests/functional/test_arm_aspeed_rainier.py
 create mode 100644 tests/functional/test_arm_aspeed_romulus.py

Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 docs/about/deprecated.rst       |  8 --------
 docs/about/removed-features.rst | 10 ++++++++++
 docs/system/arm/aspeed.rst      |  1 -
 hw/arm/aspeed.c                 | 28 ----------------------------
 4 files changed, 10 insertions(+), 37 deletions(-)

diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -XXX,XX +XXX,XX @@ images are not available, OpenWRT dropped support in 2019, U-Boot in
 2017, Linux also is dropping support in 2024. It is time to let go of
 this ancient hardware and focus on newer CPUs and platforms.
 
-Arm ``tacoma-bmc`` machine (since 9.1)
-''''''''''''''''''''''''''''''''''''''''
-
-The ``tacoma-bmc`` machine was a board including an AST2600 SoC based
-BMC and a witherspoon like OpenPOWER system. It was used for bring up
-of the AST2600 SoC in labs.  It can be easily replaced by the
-``rainier-bmc`` machine which is a real product.
-
 Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
 ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
 
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -XXX,XX +XXX,XX @@ Aspeed ``swift-bmc`` machine (removed in 7.0)
 This machine was removed because it was unused. Alternative AST2500 based
 OpenPOWER machines are ``witherspoon-bmc`` and ``romulus-bmc``.
 
+Aspeed ``tacoma-bmc`` machine (removed in 10.0)
+'''''''''''''''''''''''''''''''''''''''''''''''
+
+The ``tacoma-bmc`` machine was removed because it didn't bring much
+compared to the ``rainier-bmc`` machine. Also, the ``tacoma-bmc`` was
+a board used for bring up of the AST2600 SoC that never left the
+labs. It can be easily replaced by the ``rainier-bmc`` machine, which
+was the actual final product, or by the ``ast2600-evb`` with some
+tweaks.
+
 ppc ``taihu`` machine (removed in 7.2)
 '''''''''''''''''''''''''''''''''''''''''''''
 
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
 AST2600 SoC based machines :
 
 - ``ast2600-evb``          Aspeed AST2600 Evaluation board (Cortex-A7)
-- ``tacoma-bmc``           OpenPOWER Witherspoon POWER9 AST2600 BMC
 - ``rainier-bmc``          IBM Rainier POWER10 BMC
 - ``fuji-bmc``             Facebook Fuji BMC
 - ``bletchley-bmc``        Facebook Bletchley BMC
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
 #define AST2700_EVB_HW_STRAP2 0x00000003
 #endif
 
-/* Tacoma hardware value */
-#define TACOMA_BMC_HW_STRAP1  0x00000000
-#define TACOMA_BMC_HW_STRAP2  0x00000040
-
 /* Rainier hardware value: (QEMU prototype) */
 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
 #define RAINIER_BMC_HW_STRAP2 0x80000848
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
     aspeed_machine_ast2600_class_emmc_init(oc);
 };
 
-static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
-{
-    MachineClass *mc = MACHINE_CLASS(oc);
-    AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
-    mc->desc       = "OpenPOWER Tacoma BMC (Cortex-A7)";
-    amc->soc_name  = "ast2600-a3";
-    amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
-    amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
-    amc->fmc_model = "mx66l1g45g";
-    amc->spi_model = "mx66l1g45g";
-    amc->num_cs    = 2;
-    amc->macs_mask  = ASPEED_MAC2_ON;
-    amc->i2c_init  = witherspoon_bmc_i2c_init; /* Same board layout */
-    mc->default_ram_size = 1 * GiB;
-    aspeed_machine_class_init_cpus_defaults(mc);
-
-    mc->deprecation_reason = "Please use the similar 'rainier-bmc' machine";
-};
-
 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_yosemitev2_class_init,
-    }, {
-        .name          = MACHINE_TYPE_NAME("tacoma-bmc"),
-        .parent        = TYPE_ASPEED_MACHINE,
-        .class_init    = aspeed_machine_tacoma_class_init,
     }, {
         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Fix coding style issues from checkpatch.pl.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/sd/aspeed_sdhci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
         sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;
         break;
     case ASPEED_SDHCI_SDIO_140:
-        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 0, 32, val);
+        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,
+                                            0, 32, val);
         break;
     case ASPEED_SDHCI_SDIO_144:
-        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 32, 32, val);
+        sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg,
+                                            32, 32, val);
         break;
     case ASPEED_SDHCI_SDIO_148:
         sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr,
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Fix coding style issues from checkpatch.pl.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed_ast2600.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
         return;
     }
-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
+                    sc->memmap[ASPEED_DEV_GPIO]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
 
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.

Introduce a new "capareg" class member whose data type is uint_64 to set the
different Capability Registers to all ASPEED SOCs.

The value of Capability Register is "0x0000000001e80080" for AST2400 and
AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 include/hw/sd/aspeed_sdhci.h | 12 +++++++--
 hw/arm/aspeed_ast2400.c      |  3 ++-
 hw/arm/aspeed_ast2600.c      |  7 +++---
 hw/sd/aspeed_sdhci.c         | 47 +++++++++++++++++++++++++++++++++++-
 4 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_ASPEED_SDHCI "aspeed.sdhci"
-OBJECT_DECLARE_SIMPLE_TYPE(AspeedSDHCIState, ASPEED_SDHCI)
+#define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
+#define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
+#define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
+OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
 
-#define ASPEED_SDHCI_CAPABILITIES 0x01E80080
 #define ASPEED_SDHCI_NUM_SLOTS    2
 #define ASPEED_SDHCI_NUM_REGS     (ASPEED_SDHCI_REG_SIZE / sizeof(uint32_t))
 #define ASPEED_SDHCI_REG_SIZE     0x100
@@ -XXX,XX +XXX,XX @@ struct AspeedSDHCIState {
     uint32_t regs[ASPEED_SDHCI_NUM_REGS];
 };
 
+struct AspeedSDHCIClass {
+    SysBusDeviceClass parent_class;
+
+    uint64_t capareg;
+};
+
 #endif /* ASPEED_SDHCI_H */
diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2400.c
+++ b/hw/arm/aspeed_ast2400.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
     object_initialize_child(obj, "gpio", &s->gpio, typename);
 
-    object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
+    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+    object_initialize_child(obj, "sdc", &s->sdhci, typename);
 
     object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
 
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
     object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
 
-    object_initialize_child(obj, "sd-controller", &s->sdhci,
-                            TYPE_ASPEED_SDHCI);
+    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+    object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
 
     object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
                                 &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
     }
 
-    object_initialize_child(obj, "emmc-controller", &s->emmc,
-                            TYPE_ASPEED_SDHCI);
+    object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
 
     object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
 
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
     AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);
+    AspeedSDHCIClass *asc = ASPEED_SDHCI_GET_CLASS(sdhci);
 
     /* Create input irqs for the slots */
     qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq,
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_realize(DeviceState *dev, Error **errp)
         }
 
         if (!object_property_set_uint(sdhci_slot, "capareg",
-                                      ASPEED_SDHCI_CAPABILITIES, errp)) {
+                                      asc->capareg, errp)) {
             return;
         }
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_class_init(ObjectClass *classp, void *data)
     device_class_set_props(dc, aspeed_sdhci_properties);
 }
 
+static void aspeed_2400_sdhci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
+
+    dc->desc = "ASPEED 2400 SDHCI Controller";
+    asc->capareg = 0x0000000001e80080;
+}
+
+static void aspeed_2500_sdhci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
+
+    dc->desc = "ASPEED 2500 SDHCI Controller";
+    asc->capareg = 0x0000000001e80080;
+}
+
+static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
+
+    dc->desc = "ASPEED 2600 SDHCI Controller";
+    asc->capareg = 0x0000000701f80080;
+}
+
 static const TypeInfo aspeed_sdhci_types[] = {
     {
         .name           = TYPE_ASPEED_SDHCI,
         .parent         = TYPE_SYS_BUS_DEVICE,
         .instance_size  = sizeof(AspeedSDHCIState),
         .class_init     = aspeed_sdhci_class_init,
+        .class_size = sizeof(AspeedSDHCIClass),
+        .abstract = true,
+    },
+    {
+        .name = TYPE_ASPEED_2400_SDHCI,
+        .parent = TYPE_ASPEED_SDHCI,
+        .class_init = aspeed_2400_sdhci_class_init,
+    },
+    {
+        .name = TYPE_ASPEED_2500_SDHCI,
+        .parent = TYPE_ASPEED_SDHCI,
+        .class_init = aspeed_2500_sdhci_class_init,
+    },
+    {
+        .name = TYPE_ASPEED_2600_SDHCI,
+        .parent = TYPE_ASPEED_SDHCI,
+        .class_init = aspeed_2600_sdhci_class_init,
     },
 };
 
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x0000000719f80080".

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 include/hw/sd/aspeed_sdhci.h |  1 +
 hw/sd/aspeed_sdhci.c         | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/include/hw/sd/aspeed_sdhci.h b/include/hw/sd/aspeed_sdhci.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/sd/aspeed_sdhci.h
+++ b/include/hw/sd/aspeed_sdhci.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_ASPEED_2400_SDHCI TYPE_ASPEED_SDHCI "-ast2400"
 #define TYPE_ASPEED_2500_SDHCI TYPE_ASPEED_SDHCI "-ast2500"
 #define TYPE_ASPEED_2600_SDHCI TYPE_ASPEED_SDHCI "-ast2600"
+#define TYPE_ASPEED_2700_SDHCI TYPE_ASPEED_SDHCI "-ast2700"
 OBJECT_DECLARE_TYPE(AspeedSDHCIState, AspeedSDHCIClass, ASPEED_SDHCI)
 
 #define ASPEED_SDHCI_NUM_SLOTS    2
diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/aspeed_sdhci.c
+++ b/hw/sd/aspeed_sdhci.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data)
     asc->capareg = 0x0000000701f80080;
 }
 
+static void aspeed_2700_sdhci_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass);
+
+    dc->desc = "ASPEED 2700 SDHCI Controller";
+    asc->capareg = 0x0000000719f80080;
+}
+
 static const TypeInfo aspeed_sdhci_types[] = {
     {
         .name           = TYPE_ASPEED_SDHCI,
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdhci_types[] = {
         .parent = TYPE_ASPEED_SDHCI,
         .class_init = aspeed_2600_sdhci_class_init,
     },
+    {
+        .name = TYPE_ASPEED_2700_SDHCI,
+        .parent = TYPE_ASPEED_SDHCI,
+        .class_init = aspeed_2700_sdhci_class_init,
+    },
 };
 
 DEFINE_TYPES(aspeed_sdhci_types)
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_0000 and its interrupt is
connected to GICINT133_INTC at bit 1.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed_ast27x0.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
     [ASPEED_DEV_I2C]       =  0x14C0F000,
     [ASPEED_DEV_GPIO]      =  0x14C0B000,
     [ASPEED_DEV_RTC]       =  0x12C0F000,
+    [ASPEED_DEV_SDHCI]     =  0x14080000,
 };
 
 #define AST2700_MAX_IRQ 256
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_irqmap[] = {
     [ASPEED_DEV_KCS]       = 128,
     [ASPEED_DEV_DP]        = 28,
     [ASPEED_DEV_I3C]       = 131,
+    [ASPEED_DEV_SDHCI]     = 133,
 };
 
 /* GICINT 128 */
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2700_gic132_intcmap[] = {
 
 /* GICINT 133 */
 static const int aspeed_soc_ast2700_gic133_intcmap[] = {
+    [ASPEED_DEV_SDHCI]     = 1,
     [ASPEED_DEV_PECI]      = 4,
 };
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)
     object_initialize_child(obj, "gpio", &s->gpio, typename);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
+
+    snprintf(typename, sizeof(typename), "aspeed.sdhci-%s", socname);
+    object_initialize_child(obj, "sd-controller", &s->sdhci, typename);
+    object_property_set_int(OBJECT(&s->sdhci), "num-slots", 1, &error_abort);
+
+    /* Init sd card slot class here so that they're under the correct parent */
+    object_initialize_child(obj, "sd-controller.sdhci",
+                            &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
 
+    /* SDHCI */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
+                    sc->memmap[ASPEED_DEV_SDHCI]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+                       aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+
     create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
     create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
     create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_0000 and its interrupt is
connected to GICINT 15.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241204084453.610660-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_init(Object *obj)
     /* Init sd card slot class here so that they're under the correct parent */
     object_initialize_child(obj, "sd-controller.sdhci",
                             &s->sdhci.slots[0], TYPE_SYSBUS_SDHCI);
+
+    object_initialize_child(obj, "emmc-controller", &s->emmc, typename);
+    object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
+
+    object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
+                            TYPE_SYSBUS_SDHCI);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
 
+    /* eMMC */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
+        return;
+    }
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
+                    sc->memmap[ASPEED_DEV_EMMC]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
+                       aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
+
     create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
     create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
     create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
-- 
2.47.1

This simply moves the ast1030 tests to a new test file. No changes.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-2-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/meson.build                |  1 +
 tests/functional/test_arm_aspeed.py         | 64 ----------------
 tests/functional/test_arm_aspeed_ast1030.py | 81 +++++++++++++++++++++
 3 files changed, 82 insertions(+), 64 deletions(-)
 create mode 100644 tests/functional/test_arm_aspeed_ast1030.py

diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [
 
 tests_arm_system_thorough = [
   'arm_aspeed',
+  'arm_aspeed_ast1030',
   'arm_bpim2u',
   'arm_canona1100',
   'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -XXX,XX +XXX,XX @@
 from zipfile import ZipFile
 from unittest import skipUnless
 
-class AST1030Machine(LinuxKernelTest):
-
-    ASSET_ZEPHYR_1_04 = Asset(
-        ('https://github.com/AspeedTech-BMC'
-         '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
-        '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
-
-    def test_ast1030_zephyros_1_04(self):
-        self.set_machine('ast1030-evb')
-
-        zip_file = self.ASSET_ZEPHYR_1_04.fetch()
-
-        kernel_name = "ast1030-evb-demo/zephyr.elf"
-        with ZipFile(zip_file, 'r') as zf:
-                     zf.extract(kernel_name, path=self.workdir)
-        kernel_file = os.path.join(self.workdir, kernel_name)
-
-        self.vm.set_console()
-        self.vm.add_args('-kernel', kernel_file, '-nographic')
-        self.vm.launch()
-        self.wait_for_console_pattern("Booting Zephyr OS")
-        exec_command_and_wait_for_pattern(self, "help",
-                                          "Available commands")
-
-    ASSET_ZEPHYR_1_07 = Asset(
-        ('https://github.com/AspeedTech-BMC'
-         '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
-        'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
-
-    def test_ast1030_zephyros_1_07(self):
-        self.set_machine('ast1030-evb')
-
-        zip_file = self.ASSET_ZEPHYR_1_07.fetch()
-
-        kernel_name = "ast1030-evb-demo/zephyr.bin"
-        with ZipFile(zip_file, 'r') as zf:
-                     zf.extract(kernel_name, path=self.workdir)
-        kernel_file = os.path.join(self.workdir, kernel_name)
-
-        self.vm.set_console()
-        self.vm.add_args('-kernel', kernel_file, '-nographic')
-        self.vm.launch()
-        self.wait_for_console_pattern("Booting Zephyr OS")
-        for shell_cmd in [
-                'kernel stacks',
-                'otp info conf',
-                'otp info scu',
-                'hwinfo devid',
-                'crypto aes256_cbc_vault',
-                'random get',
-                'jtag JTAG1 sw_xfer high TMS',
-                'adc ADC0 resolution 12',
-                'adc ADC0 read 42',
-                'adc ADC1 read 69',
-                'i2c scan I2C_0',
-                'i3c attach I3C_0',
-                'hash test',
-                'kernel uptime',
-                'kernel reboot warm',
-                'kernel uptime',
-                'kernel reboot cold',
-                'kernel uptime',
-        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
-
 class AST2x00Machine(LinuxKernelTest):
 
     def do_test_arm_aspeed(self, machine, image):
diff --git a/tests/functional/test_arm_aspeed_ast1030.py b/tests/functional/test_arm_aspeed_ast1030.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast1030.py
@@ -XXX,XX +XXX,XX @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED SoCs with firmware
+#
+# Copyright (C) 2022 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+
+from qemu_test import LinuxKernelTest, Asset
+from qemu_test import exec_command_and_wait_for_pattern
+from zipfile import ZipFile
+
+class AST1030Machine(LinuxKernelTest):
+
+    ASSET_ZEPHYR_1_04 = Asset(
+        ('https://github.com/AspeedTech-BMC'
+         '/zephyr/releases/download/v00.01.04/ast1030-evb-demo.zip'),
+        '4ac6210adcbc61294927918707c6762483fd844dde5e07f3ba834ad1f91434d3')
+
+    def test_ast1030_zephyros_1_04(self):
+        self.set_machine('ast1030-evb')
+
+        zip_file = self.ASSET_ZEPHYR_1_04.fetch()
+
+        kernel_name = "ast1030-evb-demo/zephyr.elf"
+        with ZipFile(zip_file, 'r') as zf:
+                     zf.extract(kernel_name, path=self.workdir)
+        kernel_file = os.path.join(self.workdir, kernel_name)
+
+        self.vm.set_console()
+        self.vm.add_args('-kernel', kernel_file, '-nographic')
+        self.vm.launch()
+        self.wait_for_console_pattern("Booting Zephyr OS")
+        exec_command_and_wait_for_pattern(self, "help",
+                                          "Available commands")
+
+    ASSET_ZEPHYR_1_07 = Asset(
+        ('https://github.com/AspeedTech-BMC'
+         '/zephyr/releases/download/v00.01.07/ast1030-evb-demo.zip'),
+        'ad52e27959746988afaed8429bf4e12ab988c05c4d07c9d90e13ec6f7be4574c')
+
+    def test_ast1030_zephyros_1_07(self):
+        self.set_machine('ast1030-evb')
+
+        zip_file = self.ASSET_ZEPHYR_1_07.fetch()
+
+        kernel_name = "ast1030-evb-demo/zephyr.bin"
+        with ZipFile(zip_file, 'r') as zf:
+                     zf.extract(kernel_name, path=self.workdir)
+        kernel_file = os.path.join(self.workdir, kernel_name)
+
+        self.vm.set_console()
+        self.vm.add_args('-kernel', kernel_file, '-nographic')
+        self.vm.launch()
+        self.wait_for_console_pattern("Booting Zephyr OS")
+        for shell_cmd in [
+                'kernel stacks',
+                'otp info conf',
+                'otp info scu',
+                'hwinfo devid',
+                'crypto aes256_cbc_vault',
+                'random get',
+                'jtag JTAG1 sw_xfer high TMS',
+                'adc ADC0 resolution 12',
+                'adc ADC0 read 42',
+                'adc ADC1 read 69',
+                'i2c scan I2C_0',
+                'i3c attach I3C_0',
+                'hash test',
+                'kernel uptime',
+                'kernel reboot warm',
+                'kernel uptime',
+                'kernel reboot cold',
+                'kernel uptime',
+        ]: exec_command_and_wait_for_pattern(self, shell_cmd, "uart:~$")
+
+
+if __name__ == '__main__':
+    LinuxKernelTest.main()
-- 
2.47.1

This introduces a new aspeed module for sharing code between tests and
moves the palmetto test to a new test file. No changes in the test.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-3-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/aspeed.py                   | 23 +++++++++++++++++++
 tests/functional/meson.build                 |  2 ++
 tests/functional/test_arm_aspeed.py          | 10 --------
 tests/functional/test_arm_aspeed_palmetto.py | 24 ++++++++++++++++++++
 4 files changed, 49 insertions(+), 10 deletions(-)
 create mode 100644 tests/functional/aspeed.py
 create mode 100644 tests/functional/test_arm_aspeed_palmetto.py

diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/functional/aspeed.py
@@ -XXX,XX +XXX,XX @@
+# Test class to boot aspeed machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import LinuxKernelTest
+
+class AspeedTest(LinuxKernelTest):
+
+    def do_test_arm_aspeed(self, machine, image):
+        self.set_machine(machine)
+        self.vm.set_console()
+        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
+                         '-net', 'nic', '-snapshot')
+        self.vm.launch()
+
+        self.wait_for_console_pattern("U-Boot 2016.07")
+        self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")
+        self.wait_for_console_pattern("Starting kernel ...")
+        self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
+        self.wait_for_console_pattern(
+                "aspeed-smc 1e620000.spi: read control register: 203b0641")
+        self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
+        self.wait_for_console_pattern("systemd[1]: Set hostname to")
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ test_timeouts = {
   'aarch64_tuxrun' : 240,
   'aarch64_virt' : 720,
   'acpi_bits' : 420,
+  'arm_aspeed_palmetto' : 120,
   'arm_aspeed' : 600,
   'arm_bpim2u' : 500,
   'arm_collie' : 180,
@@ -XXX,XX +XXX,XX @@ tests_alpha_system_thorough = [
 tests_arm_system_thorough = [
   'arm_aspeed',
   'arm_aspeed_ast1030',
+  'arm_aspeed_palmetto',
   'arm_bpim2u',
   'arm_canona1100',
   'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image):
         self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
         self.wait_for_console_pattern("systemd[1]: Set hostname to")
 
-    ASSET_PALMETTO_FLASH = Asset(
-        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
-         'obmc-phosphor-image-palmetto.static.mtd'),
-        '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d');
-
-    def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
-        image_path = self.ASSET_PALMETTO_FLASH.fetch()
-
-        self.do_test_arm_aspeed('palmetto-bmc', image_path)
-
     ASSET_ROMULUS_FLASH = Asset(
         ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
          'obmc-phosphor-image-romulus.static.mtd'),
diff --git a/tests/functional/test_arm_aspeed_palmetto.py b/tests/functional/test_arm_aspeed_palmetto.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_palmetto.py
@@ -XXX,XX +XXX,XX @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+
+class PalmettoMachine(AspeedTest):
+
+    ASSET_PALMETTO_FLASH = Asset(
+        ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
+         'obmc-phosphor-image-palmetto.static.mtd'),
+        '3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d');
+
+    def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
+        image_path = self.ASSET_PALMETTO_FLASH.fetch()
+
+        self.do_test_arm_aspeed('palmetto-bmc', image_path)
+
+
+if __name__ == '__main__':
+    AspeedTest.main()
-- 
2.47.1

This simply moves the romulus-bmc test to a new test file. No changes
in the test. The do_test_arm_aspeed routine is removed from the
test_arm_aspeed.py file because it is now unused.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-4-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/meson.build                |  2 ++
 tests/functional/test_arm_aspeed.py         | 26 ---------------------
 tests/functional/test_arm_aspeed_romulus.py | 24 +++++++++++++++++++
 3 files changed, 26 insertions(+), 26 deletions(-)
 create mode 100644 tests/functional/test_arm_aspeed_romulus.py

This moves the ast2500-evb tests to a new test file and extends the
aspeed module with routines used to run the buildroot and sdk
tests. No changes in the test.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-5-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/aspeed.py                  | 33 ++++++++++++
 tests/functional/meson.build                |  2 +
 tests/functional/test_arm_aspeed.py         | 44 ---------------
 tests/functional/test_arm_aspeed_ast2500.py | 59 +++++++++++++++++++++
 4 files changed, 94 insertions(+), 44 deletions(-)
 create mode 100644 tests/functional/test_arm_aspeed_ast2500.py

diff --git a/tests/functional/aspeed.py b/tests/functional/aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/aspeed.py
+++ b/tests/functional/aspeed.py
@@ -XXX,XX +XXX,XX @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+from qemu_test import exec_command_and_wait_for_pattern
 from qemu_test import LinuxKernelTest
 
 class AspeedTest(LinuxKernelTest):
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed(self, machine, image):
                 "aspeed-smc 1e620000.spi: read control register: 203b0641")
         self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
         self.wait_for_console_pattern("systemd[1]: Set hostname to")
+
+    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
+        self.require_netdev('user')
+        self.vm.set_console()
+        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true',
+                         '-net', 'nic', '-net', 'user')
+        self.vm.launch()
+
+        self.wait_for_console_pattern('U-Boot 2019.04')
+        self.wait_for_console_pattern('## Loading kernel from FIT Image')
+        self.wait_for_console_pattern('Starting kernel ...')
+        self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
+        self.wait_for_console_pattern('lease of 10.0.2.15')
+        # the line before login:
+        self.wait_for_console_pattern(pattern)
+        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+        exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
+
+    def do_test_arm_aspeed_buildroot_poweroff(self):
+        exec_command_and_wait_for_pattern(self, 'poweroff',
+                                          'reboot: System halted');
+
+    def do_test_arm_aspeed_sdk_start(self, image):
+        self.require_netdev('user')
+        self.vm.set_console()
+        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
+                         '-net', 'nic', '-net', 'user', '-snapshot')
+        self.vm.launch()
+
+        self.wait_for_console_pattern('U-Boot 2019.04')
+        self.wait_for_console_pattern('## Loading kernel from FIT Image')
+        self.wait_for_console_pattern('Starting kernel ...')
diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ test_timeouts = {
   'acpi_bits' : 420,
   'arm_aspeed_palmetto' : 120,
   'arm_aspeed_romulus' : 120,
+  'arm_aspeed_ast2500' : 480,
   'arm_aspeed' : 600,
   'arm_bpim2u' : 500,
   'arm_collie' : 180,
@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [
   'arm_aspeed_ast1030',
   'arm_aspeed_palmetto',
   'arm_aspeed_romulus',
+  'arm_aspeed_ast2500',
   'arm_bpim2u',
   'arm_canona1100',
   'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'
     def do_test_arm_aspeed_buildroot_poweroff(self):
         exec_command_and_wait_for_pattern(self, 'poweroff',
                                           'reboot: System halted');
-
-    ASSET_BR2_202311_AST2500_FLASH = Asset(
-        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-         'images/ast2500-evb/buildroot-2023.11/flash.img'),
-        'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
-
-    def test_arm_ast2500_evb_buildroot(self):
-        self.set_machine('ast2500-evb')
-
-        image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch()
-
-        self.vm.add_args('-device',
-                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
-                                                'ast2500-evb login:')
-
-        exec_command_and_wait_for_pattern(self,
-             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
-        exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
-        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
-                    property='temperature', value=18000);
-        exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
-
-        self.do_test_arm_aspeed_buildroot_poweroff()
-
     ASSET_BR2_202311_AST2600_FLASH = Asset(
         ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
          'images/ast2600-evb/buildroot-2023.11/flash.img'),
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_sdk_start(self, image):
         self.wait_for_console_pattern('## Loading kernel from FIT Image')
         self.wait_for_console_pattern('Starting kernel ...')
 
-    ASSET_SDK_V806_AST2500 = Asset(
-        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz',
-        'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
-
-    def test_arm_ast2500_evb_sdk(self):
-        self.set_machine('ast2500-evb')
-
-        image_path = self.ASSET_SDK_V806_AST2500.fetch()
-
-        archive_extract(image_path, self.workdir)
-
-        self.do_test_arm_aspeed_sdk_start(
-            self.workdir + '/ast2500-default/image-bmc')
-
-        self.wait_for_console_pattern('ast2500-default login:')
-
     ASSET_SDK_V806_AST2600_A2 = Asset(
         'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
         '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
diff --git a/tests/functional/test_arm_aspeed_ast2500.py b/tests/functional/test_arm_aspeed_ast2500.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast2500.py
@@ -XXX,XX +XXX,XX @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+from qemu_test import exec_command_and_wait_for_pattern
+from qemu_test.utils import archive_extract
+
+class AST2500Machine(AspeedTest):
+
+    ASSET_BR2_202311_AST2500_FLASH = Asset(
+        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+         'images/ast2500-evb/buildroot-2023.11/flash.img'),
+        'c23db6160cf77d0258397eb2051162c8473a56c441417c52a91ba217186e715f')
+
+    def test_arm_ast2500_evb_buildroot(self):
+        self.set_machine('ast2500-evb')
+
+        image_path = self.ASSET_BR2_202311_AST2500_FLASH.fetch()
+
+        self.vm.add_args('-device',
+                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0',
+                                                'ast2500-evb login:')
+
+        exec_command_and_wait_for_pattern(self,
+             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
+             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
+        exec_command_and_wait_for_pattern(self,
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
+        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+                    property='temperature', value=18000);
+        exec_command_and_wait_for_pattern(self,
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
+
+        self.do_test_arm_aspeed_buildroot_poweroff()
+
+    ASSET_SDK_V806_AST2500 = Asset(
+        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2500-default-obmc.tar.gz',
+        'e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
+
+    def test_arm_ast2500_evb_sdk(self):
+        self.set_machine('ast2500-evb')
+
+        image_path = self.ASSET_SDK_V806_AST2500.fetch()
+
+        archive_extract(image_path, self.workdir)
+
+        self.do_test_arm_aspeed_sdk_start(
+            self.workdir + '/ast2500-default/image-bmc')
+
+        self.wait_for_console_pattern('ast2500-default login:')
+
+
+if __name__ == '__main__':
+    AspeedTest.main()
-- 
2.47.1

This moves the ast2600-evb tests to a new test file. No changes in the
test. The routines used to run the buildroot and sdk tests are removed
from the test_arm_aspeed.py file because now unused.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-6-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/meson.build                |   2 +
 tests/functional/test_arm_aspeed.py         | 155 --------------------
 tests/functional/test_arm_aspeed_ast2600.py | 143 ++++++++++++++++++
 3 files changed, 145 insertions(+), 155 deletions(-)
 create mode 100644 tests/functional/test_arm_aspeed_ast2600.py

diff --git a/tests/functional/meson.build b/tests/functional/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/meson.build
+++ b/tests/functional/meson.build
@@ -XXX,XX +XXX,XX @@ test_timeouts = {
   'arm_aspeed_palmetto' : 120,
   'arm_aspeed_romulus' : 120,
   'arm_aspeed_ast2500' : 480,
+  'arm_aspeed_ast2600' : 720,
   'arm_aspeed' : 600,
   'arm_bpim2u' : 500,
   'arm_collie' : 180,
@@ -XXX,XX +XXX,XX @@ tests_arm_system_thorough = [
   'arm_aspeed_palmetto',
   'arm_aspeed_romulus',
   'arm_aspeed_ast2500',
+  'arm_aspeed_ast2600',
   'arm_bpim2u',
   'arm_canona1100',
   'arm_collie',
diff --git a/tests/functional/test_arm_aspeed.py b/tests/functional/test_arm_aspeed.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_aspeed.py
+++ b/tests/functional/test_arm_aspeed.py
@@ -XXX,XX +XXX,XX @@
 from zipfile import ZipFile
 from unittest import skipUnless
 
-class AST2x00Machine(LinuxKernelTest):
-
-    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id, pattern='Aspeed EVB'):
-        self.require_netdev('user')
-        self.vm.set_console()
-        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw,read-only=true',
-                         '-net', 'nic', '-net', 'user')
-        self.vm.launch()
-
-        self.wait_for_console_pattern('U-Boot 2019.04')
-        self.wait_for_console_pattern('## Loading kernel from FIT Image')
-        self.wait_for_console_pattern('Starting kernel ...')
-        self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
-        self.wait_for_console_pattern('lease of 10.0.2.15')
-        # the line before login:
-        self.wait_for_console_pattern(pattern)
-        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
-        exec_command_and_wait_for_pattern(self, 'passw0rd', '#')
-
-    def do_test_arm_aspeed_buildroot_poweroff(self):
-        exec_command_and_wait_for_pattern(self, 'poweroff',
-                                          'reboot: System halted');
-    ASSET_BR2_202311_AST2600_FLASH = Asset(
-        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-         'images/ast2600-evb/buildroot-2023.11/flash.img'),
-        'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
-
-    def test_arm_ast2600_evb_buildroot(self):
-        self.set_machine('ast2600-evb')
-
-        image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch()
-
-        self.vm.add_args('-device',
-                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-        self.vm.add_args('-device',
-                         'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
-        self.vm.add_args('-device',
-                         'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
-                                                'ast2600-evb login:')
-
-        exec_command_and_wait_for_pattern(self,
-             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
-        exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
-        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
-                    property='temperature', value=18000);
-        exec_command_and_wait_for_pattern(self,
-                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
-
-        exec_command_and_wait_for_pattern(self,
-             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
-             'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
-        year = time.strftime("%Y")
-        exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
-
-        exec_command_and_wait_for_pattern(self,
-             'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
-             'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64');
-        exec_command_and_wait_for_pattern(self,
-             'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
-        exec_command_and_wait_for_pattern(self,
-             'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
-             '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
-        self.do_test_arm_aspeed_buildroot_poweroff()
-
-    ASSET_BR2_202302_AST2600_TPM_FLASH = Asset(
-        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
-         'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
-        'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
-
-    @skipUnless(*has_cmd('swtpm'))
-    def test_arm_ast2600_evb_buildroot_tpm(self):
-        self.set_machine('ast2600-evb')
-
-        image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
-
-        tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_")
-        socket = os.path.join(tpmstate_dir.name, 'swtpm-socket')
-
-        # We must put the TPM state dir in /tmp/, not the build dir,
-        # because some distros use AppArmor to lock down swtpm and
-        # restrict the set of locations it can access files in.
-        subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
-                        '--tpmstate', f'dir={tpmstate_dir.name}',
-                        '--ctrl', f'type=unixio,path={socket}'])
-
-        self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
-        self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
-        self.vm.add_args('-device',
-                         'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
-        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
-
-        exec_command_and_wait_for_pattern(self,
-            'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
-            'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
-        exec_command_and_wait_for_pattern(self,
-            'cat /sys/class/tpm/tpm0/pcr-sha256/0',
-            'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0');
-
-        self.do_test_arm_aspeed_buildroot_poweroff()
-
-    def do_test_arm_aspeed_sdk_start(self, image):
-        self.require_netdev('user')
-        self.vm.set_console()
-        self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
-                         '-net', 'nic', '-net', 'user', '-snapshot')
-        self.vm.launch()
-
-        self.wait_for_console_pattern('U-Boot 2019.04')
-        self.wait_for_console_pattern('## Loading kernel from FIT Image')
-        self.wait_for_console_pattern('Starting kernel ...')
-
-    ASSET_SDK_V806_AST2600_A2 = Asset(
-        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
-        '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
-
-    def test_arm_ast2600_evb_sdk(self):
-        self.set_machine('ast2600-evb')
-
-        image_path = self.ASSET_SDK_V806_AST2600_A2.fetch()
-
-        archive_extract(image_path, self.workdir)
-
-        self.vm.add_args('-device',
-            'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test');
-        self.vm.add_args('-device',
-            'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
-        self.do_test_arm_aspeed_sdk_start(
-            self.workdir + '/ast2600-a2/image-bmc')
-
-        self.wait_for_console_pattern('ast2600-a2 login:')
-
-        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
-        exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#')
-
-        exec_command_and_wait_for_pattern(self,
-            'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
-            'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
-        exec_command_and_wait_for_pattern(self,
-             'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
-        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
-                    property='temperature', value=18000);
-        exec_command_and_wait_for_pattern(self,
-             'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
-
-        exec_command_and_wait_for_pattern(self,
-             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device',
-             'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
-        year = time.strftime("%Y")
-        exec_command_and_wait_for_pattern(self,
-             '/sbin/hwclock -f /dev/rtc1', year);
-
-
 class AST2x00MachineMMC(LinuxKernelTest):
 
     ASSET_RAINIER_EMMC = Asset(
diff --git a/tests/functional/test_arm_aspeed_ast2600.py b/tests/functional/test_arm_aspeed_ast2600.py
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/functional/test_arm_aspeed_ast2600.py
@@ -XXX,XX +XXX,XX @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the ASPEED machines
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import time
+import tempfile
+import subprocess
+
+from qemu_test import Asset
+from aspeed import AspeedTest
+from qemu_test import exec_command_and_wait_for_pattern
+from qemu_test import has_cmd
+from qemu_test.utils import archive_extract
+from unittest import skipUnless
+
+class AST2600Machine(AspeedTest):
+
+    ASSET_BR2_202311_AST2600_FLASH = Asset(
+        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+         'images/ast2600-evb/buildroot-2023.11/flash.img'),
+        'b62808daef48b438d0728ee07662290490ecfa65987bb91294cafb1bb7ad1a68')
+
+    def test_arm_ast2600_evb_buildroot(self):
+        self.set_machine('ast2600-evb')
+
+        image_path = self.ASSET_BR2_202311_AST2600_FLASH.fetch()
+
+        self.vm.add_args('-device',
+                         'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
+        self.vm.add_args('-device',
+                         'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
+        self.vm.add_args('-device',
+                         'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00',
+                                                'ast2600-evb login:')
+
+        exec_command_and_wait_for_pattern(self,
+             'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
+             'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
+        exec_command_and_wait_for_pattern(self,
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
+        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+                    property='temperature', value=18000);
+        exec_command_and_wait_for_pattern(self,
+                             'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
+
+        exec_command_and_wait_for_pattern(self,
+             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
+             'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
+        year = time.strftime("%Y")
+        exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
+
+        exec_command_and_wait_for_pattern(self,
+             'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
+             'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64');
+        exec_command_and_wait_for_pattern(self,
+             'i2cset -y 3 0x42 0x64 0x00 0xaa i', '#');
+        exec_command_and_wait_for_pattern(self,
+             'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
+             '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
+        self.do_test_arm_aspeed_buildroot_poweroff()
+
+    ASSET_BR2_202302_AST2600_TPM_FLASH = Asset(
+        ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
+         'images/ast2600-evb/buildroot-2023.02-tpm/flash.img'),
+        'a46009ae8a5403a0826d607215e731a8c68d27c14c41e55331706b8f9c7bd997')
+
+    @skipUnless(*has_cmd('swtpm'))
+    def test_arm_ast2600_evb_buildroot_tpm(self):
+        self.set_machine('ast2600-evb')
+
+        image_path = self.ASSET_BR2_202302_AST2600_TPM_FLASH.fetch()
+
+        tpmstate_dir = tempfile.TemporaryDirectory(prefix="qemu_")
+        socket = os.path.join(tpmstate_dir.name, 'swtpm-socket')
+
+        # We must put the TPM state dir in /tmp/, not the build dir,
+        # because some distros use AppArmor to lock down swtpm and
+        # restrict the set of locations it can access files in.
+        subprocess.run(['swtpm', 'socket', '-d', '--tpm2',
+                        '--tpmstate', f'dir={tpmstate_dir.name}',
+                        '--ctrl', f'type=unixio,path={socket}'])
+
+        self.vm.add_args('-chardev', f'socket,id=chrtpm,path={socket}')
+        self.vm.add_args('-tpmdev', 'emulator,id=tpm0,chardev=chrtpm')
+        self.vm.add_args('-device',
+                         'tpm-tis-i2c,tpmdev=tpm0,bus=aspeed.i2c.bus.12,address=0x2e')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00', 'Aspeed AST2600 EVB')
+
+        exec_command_and_wait_for_pattern(self,
+            'echo tpm_tis_i2c 0x2e > /sys/bus/i2c/devices/i2c-12/new_device',
+            'tpm_tis_i2c 12-002e: 2.0 TPM (device-id 0x1, rev-id 1)');
+        exec_command_and_wait_for_pattern(self,
+            'cat /sys/class/tpm/tpm0/pcr-sha256/0',
+            'B804724EA13F52A9072BA87FE8FDCC497DFC9DF9AA15B9088694639C431688E0');
+
+        self.do_test_arm_aspeed_buildroot_poweroff()
+
+    ASSET_SDK_V806_AST2600_A2 = Asset(
+        'https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.06/ast2600-a2-obmc.tar.gz',
+        '9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
+
+    def test_arm_ast2600_evb_sdk(self):
+        self.set_machine('ast2600-evb')
+
+        image_path = self.ASSET_SDK_V806_AST2600_A2.fetch()
+
+        archive_extract(image_path, self.workdir)
+
+        self.vm.add_args('-device',
+            'tmp105,bus=aspeed.i2c.bus.5,address=0x4d,id=tmp-test');
+        self.vm.add_args('-device',
+            'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
+        self.do_test_arm_aspeed_sdk_start(
+            self.workdir + '/ast2600-a2/image-bmc')
+
+        self.wait_for_console_pattern('ast2600-a2 login:')
+
+        exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+        exec_command_and_wait_for_pattern(self, '0penBmc', 'root@ast2600-a2:~#')
+
+        exec_command_and_wait_for_pattern(self,
+            'echo lm75 0x4d > /sys/class/i2c-dev/i2c-5/device/new_device',
+            'i2c i2c-5: new_device: Instantiated device lm75 at 0x4d');
+        exec_command_and_wait_for_pattern(self,
+             'cat /sys/class/hwmon/hwmon19/temp1_input', '0')
+        self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+                    property='temperature', value=18000);
+        exec_command_and_wait_for_pattern(self,
+             'cat /sys/class/hwmon/hwmon19/temp1_input', '18000')
+
+        exec_command_and_wait_for_pattern(self,
+             'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-5/device/new_device',
+             'i2c i2c-5: new_device: Instantiated device ds1307 at 0x32');
+        year = time.strftime("%Y")
+        exec_command_and_wait_for_pattern(self,
+             '/sbin/hwclock -f /dev/rtc1', year);
+
+if __name__ == '__main__':
+    AspeedTest.main()
-- 
2.47.1

This simply moves the rainier-bmc test to a new test file. No changes
in the test. The test_arm_aspeed.py is deleted.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-7-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/functional/meson.build                  |  4 ++--
 ...m_aspeed.py => test_arm_aspeed_rainier.py} | 22 +++++--------------
 2 files changed, 7 insertions(+), 19 deletions(-)
 rename tests/functional/{test_arm_aspeed.py => test_arm_aspeed_rainier.py} (71%)
 mode change 100755 => 100644

This simply moves the debian boot test from the avocado testsuite to
the new functional testsuite. No changes in the test.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Link: https://lore.kernel.org/r/20241206131132.520911-8-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/avocado/boot_linux_console.py         | 26 ---------------------
 tests/functional/test_arm_aspeed_rainier.py | 24 +++++++++++++++++++
 2 files changed, 24 insertions(+), 26 deletions(-)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_quanta_gsj_initrd(self):
         self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
         self.wait_for_console_pattern(
                 'Give root password for system maintenance')
-
-    def test_arm_ast2600_debian(self):
-        """
-        :avocado: tags=arch:arm
-        :avocado: tags=machine:rainier-bmc
-        """
-        deb_url = ('http://snapshot.debian.org/archive/debian/'
-                   '20220606T211338Z/'
-                   'pool/main/l/linux/'
-                   'linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb')
-        deb_hash = '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e'
-        deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash,
-                                    algorithm='sha256')
-        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
-        dtb_path = self.extract_from_deb(deb_path,
-                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
-
-        self.vm.set_console()
-        self.vm.add_args('-kernel', kernel_path,
-                         '-dtb', dtb_path,
-                         '-net', 'nic')
-        self.vm.launch()
-        self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00")
-        self.wait_for_console_pattern("SMP: Total of 2 processors activated")
-        self.wait_for_console_pattern("No filesystem could mount root")
-
diff --git a/tests/functional/test_arm_aspeed_rainier.py b/tests/functional/test_arm_aspeed_rainier.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/functional/test_arm_aspeed_rainier.py
+++ b/tests/functional/test_arm_aspeed_rainier.py
@@ -XXX,XX +XXX,XX @@ def test_arm_aspeed_emmc_boot(self):
         self.wait_for_console_pattern('mmcblk0: p1 p2 p3 p4 p5 p6 p7')
         self.wait_for_console_pattern('IBM eBMC (OpenBMC for IBM Enterprise')
 
+    ASSET_DEBIAN_LINUX_ARMHF_DEB = Asset(
+            ('http://snapshot.debian.org/archive/debian/20220606T211338Z/pool/main/l/linux/linux-image-5.17.0-2-armmp_5.17.6-1%2Bb1_armhf.deb'),
+        '8acb2b4439faedc2f3ed4bdb2847ad4f6e0491f73debaeb7f660c8abe4dcdc0e')
+
+    def test_arm_debian_kernel_boot(self):
+        self.set_machine('rainier-bmc')
+
+        deb_path = self.ASSET_DEBIAN_LINUX_ARMHF_DEB.fetch()
+
+        kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
+        dtb_path = self.extract_from_deb(deb_path,
+                '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
+
+        self.vm.set_console()
+        self.vm.add_args('-kernel', kernel_path,
+                         '-dtb', dtb_path,
+                         '-net', 'nic')
+        self.vm.launch()
+
+        self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00")
+        self.wait_for_console_pattern("SMP: Total of 2 processors activated")
+        self.wait_for_console_pattern("No filesystem could mount root")
+
+
 if __name__ == '__main__':
     AspeedTest.main()
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

So far, the test cases are used for testing SMC model with AST2400 BMC.
However, AST2400 is end off live and ASPEED is no longer support this SOC.
To test SMC model for AST2500, AST2600 and AST1030, move the test cases
from main to test_palmetto_bmc function.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
     flash_reset();
 }
 
-int main(int argc, char **argv)
+static int test_palmetto_bmc(void)
 {
     g_autofree char *tmp_path = NULL;
     int ret;
     int fd;
 
-    g_test_init(&argc, &argv, NULL);
-
     fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
     g_assert(fd >= 0);
     ret = ftruncate(fd, FLASH_SIZE);
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 
     flash_reset();
     ret = g_test_run();
-
     qtest_quit(global_qtest);
     unlink(tmp_path);
+
+    return ret;
+}
+
+int main(int argc, char **argv)
+{
+    int ret;
+
+    g_test_init(&argc, &argv, NULL);
+    ret = test_palmetto_bmc();
+
     return ret;
 }
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, these test cases are only used for testing fmc_cs0 for AST2400.
To test others BMC SOCs, introduces a new TestData structure.
Users can set the spi base address, flash base address, jedesc id and so on
for different BMC SOCs and flash model testing.

Introduce new helper functions to make the test case more readable.

Set spi base address 0x1E620000, flash_base address 0x20000000
and jedec id 0x20ba19 for fmc_cs0 with n25q256a flash for AST2400
SMC model testing.

To pass the TestData into the test case, replace qtest_add_func with
qtest_add_data_func.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 546 +++++++++++++++++++---------------
 1 file changed, 299 insertions(+), 247 deletions(-)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@
 #define   CTRL_USERMODE        0x3
 #define SR_WEL BIT(1)
 
-#define ASPEED_FMC_BASE    0x1E620000
-#define ASPEED_FLASH_BASE  0x20000000
-
 /*
  * Flash commands
  */
@@ -XXX,XX +XXX,XX @@ enum {
     ERASE_SECTOR = 0xd8,
 };
 
-#define FLASH_JEDEC         0x20ba19  /* n25q256a */
-#define FLASH_SIZE          (32 * 1024 * 1024)
-
 #define FLASH_PAGE_SIZE           256
 
+typedef struct TestData {
+    QTestState *s;
+    uint64_t spi_base;
+    uint64_t flash_base;
+    uint32_t jedec_id;
+    char *tmp_path;
+} TestData;
+
 /*
  * Use an explicit bswap for the values read/wrote to the flash region
  * as they are BE and the Aspeed CPU is LE.
@@ -XXX,XX +XXX,XX @@ static inline uint32_t make_be32(uint32_t data)
     return bswap32(data);
 }
 
-static void spi_conf(uint32_t value)
+static inline void spi_writel(const TestData *data, uint64_t offset,
+                              uint32_t value)
+{
+    qtest_writel(data->s, data->spi_base + offset, value);
+}
+
+static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
+{
+    return qtest_readl(data->s, data->spi_base + offset);
+}
+
+static inline void flash_writeb(const TestData *data, uint64_t offset,
+                                uint8_t value)
+{
+    qtest_writeb(data->s, data->flash_base + offset, value);
+}
+
+static inline void flash_writel(const TestData *data, uint64_t offset,
+                                uint32_t value)
+{
+    qtest_writel(data->s, data->flash_base + offset, value);
+}
+
+static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
 {
-    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
+    return qtest_readb(data->s, data->flash_base + offset);
+}
+
+static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
+{
+    return qtest_readl(data->s, data->flash_base + offset);
+}
+
+static void spi_conf(const TestData *data, uint32_t value)
+{
+    uint32_t conf = spi_readl(data, R_CONF);
 
     conf |= value;
-    writel(ASPEED_FMC_BASE + R_CONF, conf);
+    spi_writel(data, R_CONF, conf);
 }
 
-static void spi_conf_remove(uint32_t value)
+static void spi_conf_remove(const TestData *data, uint32_t value)
 {
-    uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF);
+    uint32_t conf = spi_readl(data, R_CONF);
 
     conf &= ~value;
-    writel(ASPEED_FMC_BASE + R_CONF, conf);
+    spi_writel(data, R_CONF, conf);
 }
 
-static void spi_ce_ctrl(uint32_t value)
+static void spi_ce_ctrl(const TestData *data, uint32_t value)
 {
-    uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL);
+    uint32_t conf = spi_readl(data, R_CE_CTRL);
 
     conf |= value;
-    writel(ASPEED_FMC_BASE + R_CE_CTRL, conf);
+    spi_writel(data, R_CE_CTRL, conf);
 }
 
-static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd)
+static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
 {
-    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
+    uint32_t ctrl = spi_readl(data, R_CTRL0);
     ctrl &= ~(CTRL_USERMODE | 0xff << 16);
     ctrl |= mode | (cmd << 16);
-    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+    spi_writel(data, R_CTRL0, ctrl);
 }
 
-static void spi_ctrl_start_user(void)
+static void spi_ctrl_start_user(const TestData *data)
 {
-    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
+    uint32_t ctrl = spi_readl(data, R_CTRL0);
 
     ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+    spi_writel(data, R_CTRL0, ctrl);
 
     ctrl &= ~CTRL_CE_STOP_ACTIVE;
-    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+    spi_writel(data, R_CTRL0, ctrl);
 }
 
-static void spi_ctrl_stop_user(void)
+static void spi_ctrl_stop_user(const TestData *data)
 {
-    uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0);
+    uint32_t ctrl = spi_readl(data, R_CTRL0);
 
     ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    writel(ASPEED_FMC_BASE + R_CTRL0, ctrl);
+    spi_writel(data, R_CTRL0, ctrl);
 }
 
-static void flash_reset(void)
+static void flash_reset(const TestData *data)
 {
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(data, CONF_ENABLE_W0);
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
-    writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, BULK_ERASE);
-    writeb(ASPEED_FLASH_BASE, WRDI);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(data);
+    flash_writeb(data, 0, RESET_ENABLE);
+    flash_writeb(data, 0, RESET_MEMORY);
+    flash_writeb(data, 0, WREN);
+    flash_writeb(data, 0, BULK_ERASE);
+    flash_writeb(data, 0, WRDI);
+    spi_ctrl_stop_user(data);
 
-    spi_conf_remove(CONF_ENABLE_W0);
+    spi_conf_remove(data, CONF_ENABLE_W0);
 }
 
-static void test_read_jedec(void)
+static void test_read_jedec(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t jedec = 0x0;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, JEDEC_READ);
-    jedec |= readb(ASPEED_FLASH_BASE) << 16;
-    jedec |= readb(ASPEED_FLASH_BASE) << 8;
-    jedec |= readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, JEDEC_READ);
+    jedec |= flash_readb(test_data, 0) << 16;
+    jedec |= flash_readb(test_data, 0) << 8;
+    jedec |= flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
 
-    flash_reset();
+    flash_reset(test_data);
 
-    g_assert_cmphex(jedec, ==, FLASH_JEDEC);
+    g_assert_cmphex(jedec, ==, test_data->jedec_id);
 }
 
-static void read_page(uint32_t addr, uint32_t *page)
+static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
 {
     int i;
 
-    spi_ctrl_start_user();
+    spi_ctrl_start_user(data);
 
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, READ);
-    writel(ASPEED_FLASH_BASE, make_be32(addr));
+    flash_writeb(data, 0, EN_4BYTE_ADDR);
+    flash_writeb(data, 0, READ);
+    flash_writel(data, 0, make_be32(addr));
 
     /* Continuous read are supported */
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        page[i] = make_be32(readl(ASPEED_FLASH_BASE));
+        page[i] = make_be32(flash_readl(data, 0));
     }
-    spi_ctrl_stop_user();
+    spi_ctrl_stop_user(data);
 }
 
-static void read_page_mem(uint32_t addr, uint32_t *page)
+static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page)
 {
     int i;
 
     /* move out USER mode to use direct reads from the AHB bus */
-    spi_ctrl_setmode(CTRL_READMODE, READ);
+    spi_ctrl_setmode(data, CTRL_READMODE, READ);
 
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4));
+        page[i] = make_be32(flash_readl(data, addr + i * 4));
     }
 }
 
-static void write_page_mem(uint32_t addr, uint32_t write_value)
+static void write_page_mem(const TestData *data, uint32_t addr,
+                           uint32_t write_value)
 {
-    spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
 
     for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
+        flash_writel(data, addr + i * 4, write_value);
     }
 }
 
-static void assert_page_mem(uint32_t addr, uint32_t expected_value)
+static void assert_page_mem(const TestData *data, uint32_t addr,
+                            uint32_t expected_value)
 {
     uint32_t page[FLASH_PAGE_SIZE / 4];
-    read_page_mem(addr, page);
+    read_page_mem(data, addr, page);
     for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, expected_value);
     }
 }
 
-static void test_erase_sector(void)
+static void test_erase_sector(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
     /*
      * Previous page should be full of 0xffs after backend is
      * initialized
      */
-    read_page(some_page_addr - FLASH_PAGE_SIZE, page);
+    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, PP);
-    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
 
     /* Fill the page with its own addresses */
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
+        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
     }
-    spi_ctrl_stop_user();
+    spi_ctrl_stop_user(test_data);
 
     /* Check the page is correctly written */
-    read_page(some_page_addr, page);
+    read_page(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
     }
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, ERASE_SECTOR);
-    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, ERASE_SECTOR);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
+    spi_ctrl_stop_user(test_data);
 
     /* Check the page is erased */
-    read_page(some_page_addr, page);
+    read_page(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_erase_all(void)
+static void test_erase_all(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
     /*
      * Previous page should be full of 0xffs after backend is
      * initialized
      */
-    read_page(some_page_addr - FLASH_PAGE_SIZE, page);
+    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, PP);
-    writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
 
     /* Fill the page with its own addresses */
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
+        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
     }
-    spi_ctrl_stop_user();
+    spi_ctrl_stop_user(test_data);
 
     /* Check the page is correctly written */
-    read_page(some_page_addr, page);
+    read_page(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
     }
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, BULK_ERASE);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, BULK_ERASE);
+    spi_ctrl_stop_user(test_data);
 
     /* Check the page is erased */
-    read_page(some_page_addr, page);
+    read_page(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_write_page(void)
+static void test_write_page(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
     uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, PP);
-    writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
 
     /* Fill the page with its own addresses */
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
     }
-    spi_ctrl_stop_user();
+    spi_ctrl_stop_user(test_data);
 
     /* Check what was written */
-    read_page(my_page_addr, page);
+    read_page(test_data, my_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
     }
 
     /* Check some other page. It should be full of 0xff */
-    read_page(some_page_addr, page);
+    read_page(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_read_page_mem(void)
+static void test_read_page_mem(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
     uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(void)
      * Enable 4BYTE mode for controller. This is should be strapped by
      * HW for CE0 anyhow.
      */
-    spi_ce_ctrl(1 << CRTL_EXTENDED0);
+    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 
     /* Enable 4BYTE mode for flash. */
-    spi_conf(CONF_ENABLE_W0);
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, PP);
-    writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
+    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
 
     /* Fill the page with its own addresses */
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
     }
-    spi_ctrl_stop_user();
-    spi_conf_remove(CONF_ENABLE_W0);
+    spi_ctrl_stop_user(test_data);
+    spi_conf_remove(test_data, CONF_ENABLE_W0);
 
     /* Check what was written */
-    read_page_mem(my_page_addr, page);
+    read_page_mem(test_data, my_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
     }
 
     /* Check some other page. It should be full of 0xff */
-    read_page_mem(some_page_addr, page);
+    read_page_mem(test_data, some_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, 0xffffffff);
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_write_page_mem(void)
+static void test_write_page_mem(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
@@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(void)
      * Enable 4BYTE mode for controller. This is should be strapped by
      * HW for CE0 anyhow.
      */
-    spi_ce_ctrl(1 << CRTL_EXTENDED0);
+    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
 
     /* Enable 4BYTE mode for flash. */
-    spi_conf(CONF_ENABLE_W0);
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-    writeb(ASPEED_FLASH_BASE, WREN);
-    spi_ctrl_stop_user();
+    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    spi_ctrl_stop_user(test_data);
 
     /* move out USER mode to use direct writes to the AHB bus */
-    spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
 
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        writel(ASPEED_FLASH_BASE + my_page_addr + i * 4,
+        flash_writel(test_data, my_page_addr + i * 4,
                make_be32(my_page_addr + i * 4));
     }
 
     /* Check what was written */
-    read_page_mem(my_page_addr, page);
+    read_page_mem(test_data, my_page_addr, page);
     for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
         g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_read_status_reg(void)
+static void test_read_status_reg(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint8_t r;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
 
     g_assert_cmphex(r & SR_WEL, ==, 0);
     g_assert(!qtest_qom_get_bool
-            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
 
     g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
     g_assert(qtest_qom_get_bool
-            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WRDI);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WRDI);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
 
     g_assert_cmphex(r & SR_WEL, ==, 0);
     g_assert(!qtest_qom_get_bool
-            (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_status_reg_write_protection(void)
+static void test_status_reg_write_protection(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint8_t r;
 
-    spi_conf(CONF_ENABLE_W0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
     /* default case: WP# is high and SRWD is low -> status register writable */
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
     /* test ability to write SRWD */
-    writeb(ASPEED_FLASH_BASE, WRSR);
-    writeb(ASPEED_FLASH_BASE, SRWD);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, SRWD);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
     g_assert_cmphex(r & SRWD, ==, SRWD);
 
     /* WP# high and SRWD high -> status register writable */
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
     /* test ability to write SRWD */
-    writeb(ASPEED_FLASH_BASE, WRSR);
-    writeb(ASPEED_FLASH_BASE, 0);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, 0);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
     g_assert_cmphex(r & SRWD, ==, 0);
 
     /* WP# low and SRWD low -> status register writable */
-    qtest_set_irq_in(global_qtest,
+    qtest_set_irq_in(test_data->s,
                      "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
     /* test ability to write SRWD */
-    writeb(ASPEED_FLASH_BASE, WRSR);
-    writeb(ASPEED_FLASH_BASE, SRWD);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, SRWD);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
     g_assert_cmphex(r & SRWD, ==, SRWD);
 
     /* WP# low and SRWD high -> status register NOT writable */
-    spi_ctrl_start_user();
-    writeb(ASPEED_FLASH_BASE, WREN);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0 , WREN);
     /* test ability to write SRWD */
-    writeb(ASPEED_FLASH_BASE, WRSR);
-    writeb(ASPEED_FLASH_BASE, 0);
-    writeb(ASPEED_FLASH_BASE, RDSR);
-    r = readb(ASPEED_FLASH_BASE);
-    spi_ctrl_stop_user();
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, 0);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
     /* write is not successful */
     g_assert_cmphex(r & SRWD, ==, SRWD);
 
-    qtest_set_irq_in(global_qtest,
+    qtest_set_irq_in(test_data->s,
                      "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_write_block_protect(void)
+static void test_write_block_protect(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t sector_size = 65536;
     uint32_t n_sectors = 512;
 
-    spi_ce_ctrl(1 << CRTL_EXTENDED0);
-    spi_conf(CONF_ENABLE_W0);
+    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
     uint32_t bp_bits = 0b0;
 
     for (int i = 0; i < 16; i++) {
         bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
 
-        spi_ctrl_start_user();
-        writeb(ASPEED_FLASH_BASE, WREN);
-        writeb(ASPEED_FLASH_BASE, BULK_ERASE);
-        writeb(ASPEED_FLASH_BASE, WREN);
-        writeb(ASPEED_FLASH_BASE, WRSR);
-        writeb(ASPEED_FLASH_BASE, bp_bits);
-        writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-        writeb(ASPEED_FLASH_BASE, WREN);
-        spi_ctrl_stop_user();
+        spi_ctrl_start_user(test_data);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, BULK_ERASE);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, WRSR);
+        flash_writeb(test_data, 0, bp_bits);
+        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+        flash_writeb(test_data, 0, WREN);
+        spi_ctrl_stop_user(test_data);
 
         uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
         uint32_t protection_start = n_sectors - num_protected_sectors;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(void)
         for (int sector = 0; sector < n_sectors; sector++) {
             uint32_t addr = sector * sector_size;
 
-            assert_page_mem(addr, 0xffffffff);
-            write_page_mem(addr, make_be32(0xabcdef12));
+            assert_page_mem(test_data, addr, 0xffffffff);
+            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 
             uint32_t expected_value = protection_start <= sector
                                       && sector < protection_end
                                       ? 0xffffffff : 0xabcdef12;
 
-            assert_page_mem(addr, expected_value);
+            assert_page_mem(test_data, addr, expected_value);
         }
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static void test_write_block_protect_bottom_bit(void)
+static void test_write_block_protect_bottom_bit(const void *data)
 {
+    const TestData *test_data = (const TestData *)data;
     uint32_t sector_size = 65536;
     uint32_t n_sectors = 512;
 
-    spi_ce_ctrl(1 << CRTL_EXTENDED0);
-    spi_conf(CONF_ENABLE_W0);
+    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+    spi_conf(test_data, CONF_ENABLE_W0);
 
     /* top bottom bit is enabled */
     uint32_t bp_bits = 0b00100 << 3;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
     for (int i = 0; i < 16; i++) {
         bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
 
-        spi_ctrl_start_user();
-        writeb(ASPEED_FLASH_BASE, WREN);
-        writeb(ASPEED_FLASH_BASE, BULK_ERASE);
-        writeb(ASPEED_FLASH_BASE, WREN);
-        writeb(ASPEED_FLASH_BASE, WRSR);
-        writeb(ASPEED_FLASH_BASE, bp_bits);
-        writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
-        writeb(ASPEED_FLASH_BASE, WREN);
-        spi_ctrl_stop_user();
+        spi_ctrl_start_user(test_data);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, BULK_ERASE);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, WRSR);
+        flash_writeb(test_data, 0, bp_bits);
+        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+        flash_writeb(test_data, 0, WREN);
+        spi_ctrl_stop_user(test_data);
 
         uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
         uint32_t protection_start = 0;
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(void)
         for (int sector = 0; sector < n_sectors; sector++) {
             uint32_t addr = sector * sector_size;
 
-            assert_page_mem(addr, 0xffffffff);
-            write_page_mem(addr, make_be32(0xabcdef12));
+            assert_page_mem(test_data, addr, 0xffffffff);
+            write_page_mem(test_data, addr, make_be32(0xabcdef12));
 
             uint32_t expected_value = protection_start <= sector
                                       && sector < protection_end
                                       ? 0xffffffff : 0xabcdef12;
 
-            assert_page_mem(addr, expected_value);
+            assert_page_mem(test_data, addr, expected_value);
         }
     }
 
-    flash_reset();
+    flash_reset(test_data);
 }
 
-static int test_palmetto_bmc(void)
+static void test_palmetto_bmc(TestData *data)
 {
-    g_autofree char *tmp_path = NULL;
     int ret;
     int fd;
 
-    fd = g_file_open_tmp("qtest.m25p80.XXXXXX", &tmp_path, NULL);
+    fd = g_file_open_tmp("qtest.m25p80.n25q256a.XXXXXX", &data->tmp_path, NULL);
     g_assert(fd >= 0);
-    ret = ftruncate(fd, FLASH_SIZE);
+    ret = ftruncate(fd, 32 * 1024 * 1024);
     g_assert(ret == 0);
     close(fd);
 
-    global_qtest = qtest_initf("-m 256 -machine palmetto-bmc "
-                               "-drive file=%s,format=raw,if=mtd",
-                               tmp_path);
-
-    qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec);
-    qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector);
-    qtest_add_func("/ast2400/smc/erase_all",  test_erase_all);
-    qtest_add_func("/ast2400/smc/write_page", test_write_page);
-    qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
-    qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
-    qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
-    qtest_add_func("/ast2400/smc/status_reg_write_protection",
-                   test_status_reg_write_protection);
-    qtest_add_func("/ast2400/smc/write_block_protect",
-                   test_write_block_protect);
-    qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
-                   test_write_block_protect_bottom_bit);
-
-    flash_reset();
-    ret = g_test_run();
-    qtest_quit(global_qtest);
-    unlink(tmp_path);
-
-    return ret;
+    data->s = qtest_initf("-m 256 -machine palmetto-bmc "
+                          "-drive file=%s,format=raw,if=mtd",
+                          data->tmp_path);
+
+    /* fmc cs0 with n25q256a flash */
+    data->flash_base = 0x20000000;
+    data->spi_base = 0x1E620000;
+    data->jedec_id = 0x20ba19;
+
+    qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
+    qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
+    qtest_add_data_func("/ast2400/smc/erase_all",  data, test_erase_all);
+    qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2400/smc/read_page_mem",
+                        data, test_read_page_mem);
+    qtest_add_data_func("/ast2400/smc/write_page_mem",
+                        data, test_write_page_mem);
+    qtest_add_data_func("/ast2400/smc/read_status_reg",
+                        data, test_read_status_reg);
+    qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
+                        data, test_status_reg_write_protection);
+    qtest_add_data_func("/ast2400/smc/write_block_protect",
+                        data, test_write_block_protect);
+    qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
+                        data, test_write_block_protect_bottom_bit);
 }
 
 int main(int argc, char **argv)
 {
+    TestData palmetto_data;
     int ret;
 
     g_test_init(&argc, &argv, NULL);
-    ret = test_palmetto_bmc();
 
+    test_palmetto_bmc(&palmetto_data);
+    ret = g_test_run();
+
+    qtest_quit(palmetto_data.s);
+    unlink(palmetto_data.tmp_path);
     return ret;
 }
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, these test cases only support to test CE0. To test all CE pins,
introduces new ce and node members in TestData structure. The ce member is used
for saving the ce index and node member is used for saving the node path,
respectively.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 77 ++++++++++++++++++-----------------
 1 file changed, 40 insertions(+), 37 deletions(-)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@
  * ASPEED SPI Controller registers
  */
 #define R_CONF              0x00
-#define   CONF_ENABLE_W0       (1 << 16)
+#define   CONF_ENABLE_W0       16
 #define R_CE_CTRL           0x04
 #define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
 #define R_CTRL0             0x10
-#define   CTRL_CE_STOP_ACTIVE  (1 << 2)
+#define   CTRL_CE_STOP_ACTIVE  BIT(2)
 #define   CTRL_READMODE        0x0
 #define   CTRL_FREADMODE       0x1
 #define   CTRL_WRITEMODE       0x2
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
     uint64_t flash_base;
     uint32_t jedec_id;
     char *tmp_path;
+    uint8_t cs;
+    const char *node;
 } TestData;
 
 /*
@@ -XXX,XX +XXX,XX @@ static void spi_ce_ctrl(const TestData *data, uint32_t value)
 
 static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
 {
-    uint32_t ctrl = spi_readl(data, R_CTRL0);
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
     ctrl &= ~(CTRL_USERMODE | 0xff << 16);
     ctrl |= mode | (cmd << 16);
-    spi_writel(data, R_CTRL0, ctrl);
+    spi_writel(data, ctrl_reg, ctrl);
 }
 
 static void spi_ctrl_start_user(const TestData *data)
 {
-    uint32_t ctrl = spi_readl(data, R_CTRL0);
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
 
     ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, R_CTRL0, ctrl);
+    spi_writel(data, ctrl_reg, ctrl);
 
     ctrl &= ~CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, R_CTRL0, ctrl);
+    spi_writel(data, ctrl_reg, ctrl);
 }
 
 static void spi_ctrl_stop_user(const TestData *data)
 {
-    uint32_t ctrl = spi_readl(data, R_CTRL0);
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
 
     ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, R_CTRL0, ctrl);
+    spi_writel(data, ctrl_reg, ctrl);
 }
 
 static void flash_reset(const TestData *data)
 {
-    spi_conf(data, CONF_ENABLE_W0);
+    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
 
     spi_ctrl_start_user(data);
     flash_writeb(data, 0, RESET_ENABLE);
@@ -XXX,XX +XXX,XX @@ static void flash_reset(const TestData *data)
     flash_writeb(data, 0, WRDI);
     spi_ctrl_stop_user(data);
 
-    spi_conf_remove(data, CONF_ENABLE_W0);
+    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
 }
 
 static void test_read_jedec(const void *data)
@@ -XXX,XX +XXX,XX @@ static void test_read_jedec(const void *data)
     const TestData *test_data = (const TestData *)data;
     uint32_t jedec = 0x0;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, JEDEC_READ);
@@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data)
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     /*
      * Previous page should be full of 0xffs after backend is
@@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data)
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     /*
      * Previous page should be full of 0xffs after backend is
@@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data)
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, EN_4BYTE_ADDR);
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
     int i;
 
     /*
-     * Enable 4BYTE mode for controller. This is should be strapped by
-     * HW for CE0 anyhow.
+     * Enable 4BYTE mode for controller.
      */
-    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 
     /* Enable 4BYTE mode for flash. */
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, EN_4BYTE_ADDR);
     flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
         flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
     }
     spi_ctrl_stop_user(test_data);
-    spi_conf_remove(test_data, CONF_ENABLE_W0);
+    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     /* Check what was written */
     read_page_mem(test_data, my_page_addr, page);
@@ -XXX,XX +XXX,XX @@ static void test_write_page_mem(const void *data)
     int i;
 
     /*
-     * Enable 4BYTE mode for controller. This is should be strapped by
-     * HW for CE0 anyhow.
+     * Enable 4BYTE mode for controller.
      */
-    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
 
     /* Enable 4BYTE mode for flash. */
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, EN_4BYTE_ADDR);
     flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
     const TestData *test_data = (const TestData *)data;
     uint8_t r;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, RDSR);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
 
     g_assert_cmphex(r & SR_WEL, ==, 0);
     g_assert(!qtest_qom_get_bool
-            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, test_data->node, "write-enable"));
 
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, WREN);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
 
     g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
     g_assert(qtest_qom_get_bool
-            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, test_data->node, "write-enable"));
 
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, WRDI);
@@ -XXX,XX +XXX,XX @@ static void test_read_status_reg(const void *data)
 
     g_assert_cmphex(r & SR_WEL, ==, 0);
     g_assert(!qtest_qom_get_bool
-            (test_data->s, "/machine/soc/fmc/ssi.0/child[0]", "write-enable"));
+            (test_data->s, test_data->node, "write-enable"));
 
     flash_reset(test_data);
 }
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
     const TestData *test_data = (const TestData *)data;
     uint8_t r;
 
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     /* default case: WP# is high and SRWD is low -> status register writable */
     spi_ctrl_start_user(test_data);
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
     g_assert_cmphex(r & SRWD, ==, 0);
 
     /* WP# low and SRWD low -> status register writable */
-    qtest_set_irq_in(test_data->s,
-                     "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
+    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
     spi_ctrl_start_user(test_data);
     flash_writeb(test_data, 0, WREN);
     /* test ability to write SRWD */
@@ -XXX,XX +XXX,XX @@ static void test_status_reg_write_protection(const void *data)
     /* write is not successful */
     g_assert_cmphex(r & SRWD, ==, SRWD);
 
-    qtest_set_irq_in(test_data->s,
-                     "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
+    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
     flash_reset(test_data);
 }
 
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect(const void *data)
     uint32_t sector_size = 65536;
     uint32_t n_sectors = 512;
 
-    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     uint32_t bp_bits = 0b0;
 
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data)
     uint32_t sector_size = 65536;
     uint32_t n_sectors = 512;
 
-    spi_ce_ctrl(test_data, 1 << CRTL_EXTENDED0);
-    spi_conf(test_data, CONF_ENABLE_W0);
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
 
     /* top bottom bit is enabled */
     uint32_t bp_bits = 0b00100 << 3;
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
     data->flash_base = 0x20000000;
     data->spi_base = 0x1E620000;
     data->jedec_id = 0x20ba19;
+    data->cs = 0;
+    data->node = "/machine/soc/fmc/ssi.0/child[0]";
 
     qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
     qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Currently, these test cases used the hardcode offset 0x1400000 (0x14000 * 256)
which was beyond the 16MB flash size for flash page read/write command testing.
However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size
is 1MB. To test SoC flash models, introduces a new page_addr member in TestData
structure, so users can set the offset for flash page read/write command
testing.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@ typedef struct TestData {
     char *tmp_path;
     uint8_t cs;
     const char *node;
+    uint32_t page_addr;
 } TestData;
 
 /*
@@ -XXX,XX +XXX,XX @@ static void assert_page_mem(const TestData *data, uint32_t addr,
 static void test_erase_sector(const void *data)
 {
     const TestData *test_data = (const TestData *)data;
-    uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
+    uint32_t some_page_addr = test_data->page_addr;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void test_erase_sector(const void *data)
 static void test_erase_all(const void *data)
 {
     const TestData *test_data = (const TestData *)data;
-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
+    uint32_t some_page_addr = test_data->page_addr;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void test_erase_all(const void *data)
 static void test_write_page(const void *data)
 {
     const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void test_write_page(const void *data)
 static void test_read_page_mem(const void *data)
 {
     const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */
-    uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void test_read_page_mem(const void *data)
 static void test_write_page_mem(const void *data)
 {
     const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE;
+    uint32_t my_page_addr = test_data->page_addr;
     uint32_t page[FLASH_PAGE_SIZE / 4];
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
     data->jedec_id = 0x20ba19;
     data->cs = 0;
     data->node = "/machine/soc/fmc/ssi.0/child[0]";
+    /* beyond 16MB */
+    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 
     qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
     qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add test_ast2500_evb function and reused testcases for AST2500 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E620000, 0x20000000 and 0, respectively.
The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB,
so set jedec_id 0xc22019.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 40 +++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
                         data, test_write_block_protect_bottom_bit);
 }
 
+static void test_ast2500_evb(TestData *data)
+{
+    int ret;
+    int fd;
+
+    fd = g_file_open_tmp("qtest.m25p80.mx25l25635e.XXXXXX",
+                         &data->tmp_path, NULL);
+    g_assert(fd >= 0);
+    ret = ftruncate(fd, 32 * 1024 * 1024);
+    g_assert(ret == 0);
+    close(fd);
+
+    data->s = qtest_initf("-machine ast2500-evb "
+                          "-drive file=%s,format=raw,if=mtd",
+                          data->tmp_path);
+
+    /* fmc cs0 with mx25l25635e flash */
+    data->flash_base = 0x20000000;
+    data->spi_base = 0x1E620000;
+    data->jedec_id = 0xc22019;
+    data->cs = 0;
+    data->node = "/machine/soc/fmc/ssi.0/child[0]";
+    /* beyond 16MB */
+    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
+
+    qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
+    qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector);
+    qtest_add_data_func("/ast2500/smc/erase_all",  data, test_erase_all);
+    qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2500/smc/read_page_mem",
+                        data, test_read_page_mem);
+    qtest_add_data_func("/ast2500/smc/write_page_mem",
+                        data, test_write_page_mem);
+    qtest_add_data_func("/ast2500/smc/read_status_reg",
+                        data, test_read_status_reg);
+}
 int main(int argc, char **argv)
 {
     TestData palmetto_data;
+    TestData ast2500_evb_data;
     int ret;
 
     g_test_init(&argc, &argv, NULL);
 
     test_palmetto_bmc(&palmetto_data);
+    test_ast2500_evb(&ast2500_evb_data);
     ret = g_test_run();
 
     qtest_quit(palmetto_data.s);
+    qtest_quit(ast2500_evb_data.s);
     unlink(palmetto_data.tmp_path);
+    unlink(ast2500_evb_data.tmp_path);
     return ret;
 }
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add test_ast2600_evb function and reused testcases for AST2600 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E620000, 0x20000000 and 0, respectively.
The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
so set jedec_id 0xc2253a.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 41 +++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
     qtest_add_data_func("/ast2500/smc/read_status_reg",
                         data, test_read_status_reg);
 }
+
+static void test_ast2600_evb(TestData *data)
+{
+    int ret;
+    int fd;
+
+    fd = g_file_open_tmp("qtest.m25p80.mx66u51235f.XXXXXX",
+                         &data->tmp_path, NULL);
+    g_assert(fd >= 0);
+    ret = ftruncate(fd, 64 * 1024 * 1024);
+    g_assert(ret == 0);
+    close(fd);
+
+    data->s = qtest_initf("-machine ast2600-evb "
+                          "-drive file=%s,format=raw,if=mtd",
+                          data->tmp_path);
+
+    /* fmc cs0 with mx66u51235f flash */
+    data->flash_base = 0x20000000;
+    data->spi_base = 0x1E620000;
+    data->jedec_id = 0xc2253a;
+    data->cs = 0;
+    data->node = "/machine/soc/fmc/ssi.0/child[0]";
+    /* beyond 16MB */
+    data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
+
+    qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
+    qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector);
+    qtest_add_data_func("/ast2600/smc/erase_all",  data, test_erase_all);
+    qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2600/smc/read_page_mem",
+                        data, test_read_page_mem);
+    qtest_add_data_func("/ast2600/smc/write_page_mem",
+                        data, test_write_page_mem);
+    qtest_add_data_func("/ast2600/smc/read_status_reg",
+                        data, test_read_status_reg);
+}
 int main(int argc, char **argv)
 {
     TestData palmetto_data;
     TestData ast2500_evb_data;
+    TestData ast2600_evb_data;
     int ret;
 
     g_test_init(&argc, &argv, NULL);
 
     test_palmetto_bmc(&palmetto_data);
     test_ast2500_evb(&ast2500_evb_data);
+    test_ast2600_evb(&ast2600_evb_data);
     ret = g_test_run();
 
     qtest_quit(palmetto_data.s);
     qtest_quit(ast2500_evb_data.s);
+    qtest_quit(ast2600_evb_data.s);
     unlink(palmetto_data.tmp_path);
     unlink(ast2500_evb_data.tmp_path);
+    unlink(ast2600_evb_data.tmp_path);
     return ret;
 }
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add test_ast1030_evb function and reused testcases for AST1030 testing.
The base address, flash base address and ce index of fmc_cs0 are
0x7E620000, 0x80000000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB,
so set jedec_id 0xef4014.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 42 +++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
     qtest_add_data_func("/ast2600/smc/read_status_reg",
                         data, test_read_status_reg);
 }
+
+static void test_ast1030_evb(TestData *data)
+{
+    int ret;
+    int fd;
+
+    fd = g_file_open_tmp("qtest.m25p80.w25q80bl.XXXXXX",
+                         &data->tmp_path, NULL);
+    g_assert(fd >= 0);
+    ret = ftruncate(fd, 1 * 1024 * 1024);
+    g_assert(ret == 0);
+    close(fd);
+
+    data->s = qtest_initf("-machine ast1030-evb "
+                          "-drive file=%s,format=raw,if=mtd",
+                          data->tmp_path);
+
+    /* fmc cs0 with w25q80bl flash */
+    data->flash_base = 0x80000000;
+    data->spi_base = 0x7E620000;
+    data->jedec_id = 0xef4014;
+    data->cs = 0;
+    data->node = "/machine/soc/fmc/ssi.0/child[0]";
+    /* beyond 512KB */
+    data->page_addr = 0x800 * FLASH_PAGE_SIZE;
+
+    qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
+    qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector);
+    qtest_add_data_func("/ast1030/smc/erase_all",  data, test_erase_all);
+    qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast1030/smc/read_page_mem",
+                        data, test_read_page_mem);
+    qtest_add_data_func("/ast1030/smc/write_page_mem",
+                        data, test_write_page_mem);
+    qtest_add_data_func("/ast1030/smc/read_status_reg",
+                        data, test_read_status_reg);
+}
+
 int main(int argc, char **argv)
 {
     TestData palmetto_data;
     TestData ast2500_evb_data;
     TestData ast2600_evb_data;
+    TestData ast1030_evb_data;
     int ret;
 
     g_test_init(&argc, &argv, NULL);
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
     test_palmetto_bmc(&palmetto_data);
     test_ast2500_evb(&ast2500_evb_data);
     test_ast2600_evb(&ast2600_evb_data);
+    test_ast1030_evb(&ast1030_evb_data);
     ret = g_test_run();
 
     qtest_quit(palmetto_data.s);
     qtest_quit(ast2500_evb_data.s);
     qtest_quit(ast2600_evb_data.s);
+    qtest_quit(ast1030_evb_data.s);
     unlink(palmetto_data.tmp_path);
     unlink(ast2500_evb_data.tmp_path);
     unlink(ast2600_evb_data.tmp_path);
+    unlink(ast1030_evb_data.tmp_path);
     return ret;
 }
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add a new testcase for write page command with QPI mode testing.
Currently, only run this testcase for AST2500, AST2600 and AST1030.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-9-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed_smc-test.c | 74 +++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@
 #define R_CE_CTRL           0x04
 #define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
 #define R_CTRL0             0x10
+#define   CTRL_IO_QUAD_IO      BIT(31)
 #define   CTRL_CE_STOP_ACTIVE  BIT(2)
 #define   CTRL_READMODE        0x0
 #define   CTRL_FREADMODE       0x1
@@ -XXX,XX +XXX,XX @@ enum {
     ERASE_SECTOR = 0xd8,
 };
 
+#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
 #define FLASH_PAGE_SIZE           256
 
 typedef struct TestData {
@@ -XXX,XX +XXX,XX @@ static void spi_ctrl_stop_user(const TestData *data)
     spi_writel(data, ctrl_reg, ctrl);
 }
 
+static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
+{
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
+    uint32_t mode;
+
+    mode = value & CTRL_IO_MODE_MASK;
+    ctrl &= ~CTRL_IO_MODE_MASK;
+    ctrl |= mode;
+    spi_writel(data, ctrl_reg, ctrl);
+}
+
 static void flash_reset(const TestData *data)
 {
     spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
@@ -XXX,XX +XXX,XX @@ static void test_write_block_protect_bottom_bit(const void *data)
     flash_reset(test_data);
 }
 
+static void test_write_page_qpi(const void *data)
+{
+    const TestData *test_data = (const TestData *)data;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    uint32_t page_pattern[] = {
+        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
+    };
+    int i;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
+
+    /* Set QPI mode */
+    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
+
+    /* Fill the page pattern */
+    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
+        flash_writel(test_data, 0, make_be32(page_pattern[i]));
+    }
+
+    /* Fill the page with its own addresses */
+    for (; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+    }
+
+    /* Restore io mode */
+    spi_ctrl_set_io_mode(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    /* Check what was written */
+    read_page(test_data, my_page_addr, page);
+    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
+        g_assert_cmphex(page[i], ==, page_pattern[i]);
+    }
+    for (; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
+    }
+
+    /* Check some other page. It should be full of 0xff */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
 static void test_palmetto_bmc(TestData *data)
 {
     int ret;
@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
                         data, test_write_page_mem);
     qtest_add_data_func("/ast2500/smc/read_status_reg",
                         data, test_read_status_reg);
+    qtest_add_data_func("/ast2500/smc/write_page_qpi",
+                        data, test_write_page_qpi);
 }
 
 static void test_ast2600_evb(TestData *data)
@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
                         data, test_write_page_mem);
     qtest_add_data_func("/ast2600/smc/read_status_reg",
                         data, test_read_status_reg);
+    qtest_add_data_func("/ast2600/smc/write_page_qpi",
+                        data, test_write_page_qpi);
 }
 
 static void test_ast1030_evb(TestData *data)
@@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data)
                         data, test_write_page_mem);
     qtest_add_data_func("/ast1030/smc/read_status_reg",
                         data, test_read_status_reg);
+    qtest_add_data_func("/ast1030/smc/write_page_qpi",
+                        data, test_write_page_qpi);
 }
 
 int main(int argc, char **argv)
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

The testcases for ASPEED SMC model were placed in aspeed_smc-test.c.
However, this test file only supports for ARM32. To support all ASPEED SOCs
such as AST2700 whose CPU architecture is aarch64, introduces a new
aspeed-smc-utils source file and move all common APIs and testcases
from aspeed_smc-test.c to aspeed-smc-utils.c.

Finally, users are able to re-used these testcase for AST2700 and future
ASPEED SOCs testing.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/aspeed-smc-utils.h |  95 ++++
 tests/qtest/aspeed-smc-utils.c | 686 ++++++++++++++++++++++++++++
 tests/qtest/aspeed_smc-test.c  | 800 +++------------------------------
 tests/qtest/meson.build        |   1 +
 4 files changed, 841 insertions(+), 741 deletions(-)
 create mode 100644 tests/qtest/aspeed-smc-utils.h
 create mode 100644 tests/qtest/aspeed-smc-utils.c

diff --git a/tests/qtest/aspeed-smc-utils.h b/tests/qtest/aspeed-smc-utils.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/aspeed-smc-utils.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
+ * Controller)
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TESTS_ASPEED_SMC_UTILS_H
+#define TESTS_ASPEED_SMC_UTILS_H
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+
+/*
+ * ASPEED SPI Controller registers
+ */
+#define R_CONF              0x00
+#define   CONF_ENABLE_W0       16
+#define R_CE_CTRL           0x04
+#define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
+#define R_CTRL0             0x10
+#define   CTRL_IO_QUAD_IO      BIT(31)
+#define   CTRL_CE_STOP_ACTIVE  BIT(2)
+#define   CTRL_READMODE        0x0
+#define   CTRL_FREADMODE       0x1
+#define   CTRL_WRITEMODE       0x2
+#define   CTRL_USERMODE        0x3
+#define SR_WEL BIT(1)
+
+/*
+ * Flash commands
+ */
+enum {
+    JEDEC_READ = 0x9f,
+    RDSR = 0x5,
+    WRDI = 0x4,
+    BULK_ERASE = 0xc7,
+    READ = 0x03,
+    PP = 0x02,
+    WRSR = 0x1,
+    WREN = 0x6,
+    SRWD = 0x80,
+    RESET_ENABLE = 0x66,
+    RESET_MEMORY = 0x99,
+    EN_4BYTE_ADDR = 0xB7,
+    ERASE_SECTOR = 0xd8,
+};
+
+#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
+#define FLASH_PAGE_SIZE           256
+
+typedef struct AspeedSMCTestData {
+    QTestState *s;
+    uint64_t spi_base;
+    uint64_t flash_base;
+    uint32_t jedec_id;
+    char *tmp_path;
+    uint8_t cs;
+    const char *node;
+    uint32_t page_addr;
+} AspeedSMCTestData;
+
+void aspeed_smc_test_read_jedec(const void *data);
+void aspeed_smc_test_erase_sector(const void *data);
+void aspeed_smc_test_erase_all(const void *data);
+void aspeed_smc_test_write_page(const void *data);
+void aspeed_smc_test_read_page_mem(const void *data);
+void aspeed_smc_test_write_page_mem(const void *data);
+void aspeed_smc_test_read_status_reg(const void *data);
+void aspeed_smc_test_status_reg_write_protection(const void *data);
+void aspeed_smc_test_write_block_protect(const void *data);
+void aspeed_smc_test_write_block_protect_bottom_bit(const void *data);
+void aspeed_smc_test_write_page_qpi(const void *data);
+
+#endif /* TESTS_ASPEED_SMC_UTILS_H */
diff --git a/tests/qtest/aspeed-smc-utils.c b/tests/qtest/aspeed-smc-utils.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/aspeed-smc-utils.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcase for the M25P80 Flash (Using the Aspeed SPI
+ * Controller)
+ *
+ * Copyright (C) 2016 IBM Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
+
+/*
+ * Use an explicit bswap for the values read/wrote to the flash region
+ * as they are BE and the Aspeed CPU is LE.
+ */
+static inline uint32_t make_be32(uint32_t data)
+{
+    return bswap32(data);
+}
+
+static inline void spi_writel(const AspeedSMCTestData *data, uint64_t offset,
+                              uint32_t value)
+{
+    qtest_writel(data->s, data->spi_base + offset, value);
+}
+
+static inline uint32_t spi_readl(const AspeedSMCTestData *data, uint64_t offset)
+{
+    return qtest_readl(data->s, data->spi_base + offset);
+}
+
+static inline void flash_writeb(const AspeedSMCTestData *data, uint64_t offset,
+                                uint8_t value)
+{
+    qtest_writeb(data->s, data->flash_base + offset, value);
+}
+
+static inline void flash_writel(const AspeedSMCTestData *data, uint64_t offset,
+                                uint32_t value)
+{
+    qtest_writel(data->s, data->flash_base + offset, value);
+}
+
+static inline uint8_t flash_readb(const AspeedSMCTestData *data,
+                                  uint64_t offset)
+{
+    return qtest_readb(data->s, data->flash_base + offset);
+}
+
+static inline uint32_t flash_readl(const AspeedSMCTestData *data,
+                                   uint64_t offset)
+{
+    return qtest_readl(data->s, data->flash_base + offset);
+}
+
+static void spi_conf(const AspeedSMCTestData *data, uint32_t value)
+{
+    uint32_t conf = spi_readl(data, R_CONF);
+
+    conf |= value;
+    spi_writel(data, R_CONF, conf);
+}
+
+static void spi_conf_remove(const AspeedSMCTestData *data, uint32_t value)
+{
+    uint32_t conf = spi_readl(data, R_CONF);
+
+    conf &= ~value;
+    spi_writel(data, R_CONF, conf);
+}
+
+static void spi_ce_ctrl(const AspeedSMCTestData *data, uint32_t value)
+{
+    uint32_t conf = spi_readl(data, R_CE_CTRL);
+
+    conf |= value;
+    spi_writel(data, R_CE_CTRL, conf);
+}
+
+static void spi_ctrl_setmode(const AspeedSMCTestData *data, uint8_t mode,
+                             uint8_t cmd)
+{
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
+    ctrl &= ~(CTRL_USERMODE | 0xff << 16);
+    ctrl |= mode | (cmd << 16);
+    spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_start_user(const AspeedSMCTestData *data)
+{
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
+
+    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+    spi_writel(data, ctrl_reg, ctrl);
+
+    ctrl &= ~CTRL_CE_STOP_ACTIVE;
+    spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_stop_user(const AspeedSMCTestData *data)
+{
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
+
+    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
+    spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void spi_ctrl_set_io_mode(const AspeedSMCTestData *data, uint32_t value)
+{
+    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
+    uint32_t ctrl = spi_readl(data, ctrl_reg);
+    uint32_t mode;
+
+    mode = value & CTRL_IO_MODE_MASK;
+    ctrl &= ~CTRL_IO_MODE_MASK;
+    ctrl |= mode;
+    spi_writel(data, ctrl_reg, ctrl);
+}
+
+static void flash_reset(const AspeedSMCTestData *data)
+{
+    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
+
+    spi_ctrl_start_user(data);
+    flash_writeb(data, 0, RESET_ENABLE);
+    flash_writeb(data, 0, RESET_MEMORY);
+    flash_writeb(data, 0, WREN);
+    flash_writeb(data, 0, BULK_ERASE);
+    flash_writeb(data, 0, WRDI);
+    spi_ctrl_stop_user(data);
+
+    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
+}
+
+static void read_page(const AspeedSMCTestData *data, uint32_t addr,
+                      uint32_t *page)
+{
+    int i;
+
+    spi_ctrl_start_user(data);
+
+    flash_writeb(data, 0, EN_4BYTE_ADDR);
+    flash_writeb(data, 0, READ);
+    flash_writel(data, 0, make_be32(addr));
+
+    /* Continuous read are supported */
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        page[i] = make_be32(flash_readl(data, 0));
+    }
+    spi_ctrl_stop_user(data);
+}
+
+static void read_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+                          uint32_t *page)
+{
+    int i;
+
+    /* move out USER mode to use direct reads from the AHB bus */
+    spi_ctrl_setmode(data, CTRL_READMODE, READ);
+
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        page[i] = make_be32(flash_readl(data, addr + i * 4));
+    }
+}
+
+static void write_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+                           uint32_t write_value)
+{
+    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
+
+    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(data, addr + i * 4, write_value);
+    }
+}
+
+static void assert_page_mem(const AspeedSMCTestData *data, uint32_t addr,
+                            uint32_t expected_value)
+{
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    read_page_mem(data, addr, page);
+    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, expected_value);
+    }
+}
+
+void aspeed_smc_test_read_jedec(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t jedec = 0x0;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, JEDEC_READ);
+    jedec |= flash_readb(test_data, 0) << 16;
+    jedec |= flash_readb(test_data, 0) << 8;
+    jedec |= flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    flash_reset(test_data);
+
+    g_assert_cmphex(jedec, ==, test_data->jedec_id);
+}
+
+void aspeed_smc_test_erase_sector(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t some_page_addr = test_data->page_addr;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    int i;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    /*
+     * Previous page should be full of 0xffs after backend is
+     * initialized
+     */
+    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
+
+    /* Fill the page with its own addresses */
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
+    }
+    spi_ctrl_stop_user(test_data);
+
+    /* Check the page is correctly written */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
+    }
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, ERASE_SECTOR);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
+    spi_ctrl_stop_user(test_data);
+
+    /* Check the page is erased */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_erase_all(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t some_page_addr = test_data->page_addr;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    int i;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    /*
+     * Previous page should be full of 0xffs after backend is
+     * initialized
+     */
+    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(some_page_addr));
+
+    /* Fill the page with its own addresses */
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
+    }
+    spi_ctrl_stop_user(test_data);
+
+    /* Check the page is correctly written */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
+    }
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, BULK_ERASE);
+    spi_ctrl_stop_user(test_data);
+
+    /* Check the page is erased */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    int i;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
+
+    /* Fill the page with its own addresses */
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+    }
+    spi_ctrl_stop_user(test_data);
+
+    /* Check what was written */
+    read_page(test_data, my_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
+    }
+
+    /* Check some other page. It should be full of 0xff */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_read_page_mem(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    int i;
+
+    /*
+     * Enable 4BYTE mode for controller.
+     */
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+
+    /* Enable 4BYTE mode for flash. */
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
+
+    /* Fill the page with its own addresses */
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+    }
+    spi_ctrl_stop_user(test_data);
+    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    /* Check what was written */
+    read_page_mem(test_data, my_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
+    }
+
+    /* Check some other page. It should be full of 0xff */
+    read_page_mem(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page_mem(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    int i;
+
+    /*
+     * Enable 4BYTE mode for controller.
+     */
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+
+    /* Enable 4BYTE mode for flash. */
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    spi_ctrl_stop_user(test_data);
+
+    /* move out USER mode to use direct writes to the AHB bus */
+    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
+
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, my_page_addr + i * 4,
+               make_be32(my_page_addr + i * 4));
+    }
+
+    /* Check what was written */
+    read_page_mem(test_data, my_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_read_status_reg(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint8_t r;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    g_assert_cmphex(r & SR_WEL, ==, 0);
+    g_assert(!qtest_qom_get_bool
+            (test_data->s, test_data->node, "write-enable"));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
+    g_assert(qtest_qom_get_bool
+            (test_data->s, test_data->node, "write-enable"));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WRDI);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    g_assert_cmphex(r & SR_WEL, ==, 0);
+    g_assert(!qtest_qom_get_bool
+            (test_data->s, test_data->node, "write-enable"));
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_status_reg_write_protection(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint8_t r;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    /* default case: WP# is high and SRWD is low -> status register writable */
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    /* test ability to write SRWD */
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, SRWD);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+    g_assert_cmphex(r & SRWD, ==, SRWD);
+
+    /* WP# high and SRWD high -> status register writable */
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    /* test ability to write SRWD */
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, 0);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+    g_assert_cmphex(r & SRWD, ==, 0);
+
+    /* WP# low and SRWD low -> status register writable */
+    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, WREN);
+    /* test ability to write SRWD */
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, SRWD);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+    g_assert_cmphex(r & SRWD, ==, SRWD);
+
+    /* WP# low and SRWD high -> status register NOT writable */
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0 , WREN);
+    /* test ability to write SRWD */
+    flash_writeb(test_data, 0, WRSR);
+    flash_writeb(test_data, 0, 0);
+    flash_writeb(test_data, 0, RDSR);
+    r = flash_readb(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+    /* write is not successful */
+    g_assert_cmphex(r & SRWD, ==, SRWD);
+
+    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_block_protect(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t sector_size = 65536;
+    uint32_t n_sectors = 512;
+
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    uint32_t bp_bits = 0b0;
+
+    for (int i = 0; i < 16; i++) {
+        bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
+
+        spi_ctrl_start_user(test_data);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, BULK_ERASE);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, WRSR);
+        flash_writeb(test_data, 0, bp_bits);
+        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+        flash_writeb(test_data, 0, WREN);
+        spi_ctrl_stop_user(test_data);
+
+        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+        uint32_t protection_start = n_sectors - num_protected_sectors;
+        uint32_t protection_end = n_sectors;
+
+        for (int sector = 0; sector < n_sectors; sector++) {
+            uint32_t addr = sector * sector_size;
+
+            assert_page_mem(test_data, addr, 0xffffffff);
+            write_page_mem(test_data, addr, make_be32(0xabcdef12));
+
+            uint32_t expected_value = protection_start <= sector
+                                      && sector < protection_end
+                                      ? 0xffffffff : 0xabcdef12;
+
+            assert_page_mem(test_data, addr, expected_value);
+        }
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_block_protect_bottom_bit(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t sector_size = 65536;
+    uint32_t n_sectors = 512;
+
+    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    /* top bottom bit is enabled */
+    uint32_t bp_bits = 0b00100 << 3;
+
+    for (int i = 0; i < 16; i++) {
+        bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
+
+        spi_ctrl_start_user(test_data);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, BULK_ERASE);
+        flash_writeb(test_data, 0, WREN);
+        flash_writeb(test_data, 0, WRSR);
+        flash_writeb(test_data, 0, bp_bits);
+        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+        flash_writeb(test_data, 0, WREN);
+        spi_ctrl_stop_user(test_data);
+
+        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+        uint32_t protection_start = 0;
+        uint32_t protection_end = num_protected_sectors;
+
+        for (int sector = 0; sector < n_sectors; sector++) {
+            uint32_t addr = sector * sector_size;
+
+            assert_page_mem(test_data, addr, 0xffffffff);
+            write_page_mem(test_data, addr, make_be32(0xabcdef12));
+
+            uint32_t expected_value = protection_start <= sector
+                                      && sector < protection_end
+                                      ? 0xffffffff : 0xabcdef12;
+
+            assert_page_mem(test_data, addr, expected_value);
+        }
+    }
+
+    flash_reset(test_data);
+}
+
+void aspeed_smc_test_write_page_qpi(const void *data)
+{
+    const AspeedSMCTestData *test_data = (const AspeedSMCTestData *)data;
+    uint32_t my_page_addr = test_data->page_addr;
+    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
+    uint32_t page[FLASH_PAGE_SIZE / 4];
+    uint32_t page_pattern[] = {
+        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
+    };
+    int i;
+
+    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
+
+    spi_ctrl_start_user(test_data);
+    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
+    flash_writeb(test_data, 0, WREN);
+    flash_writeb(test_data, 0, PP);
+    flash_writel(test_data, 0, make_be32(my_page_addr));
+
+    /* Set QPI mode */
+    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
+
+    /* Fill the page pattern */
+    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
+        flash_writel(test_data, 0, make_be32(page_pattern[i]));
+    }
+
+    /* Fill the page with its own addresses */
+    for (; i < FLASH_PAGE_SIZE / 4; i++) {
+        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
+    }
+
+    /* Restore io mode */
+    spi_ctrl_set_io_mode(test_data, 0);
+    spi_ctrl_stop_user(test_data);
+
+    /* Check what was written */
+    read_page(test_data, my_page_addr, page);
+    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
+        g_assert_cmphex(page[i], ==, page_pattern[i]);
+    }
+    for (; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
+    }
+
+    /* Check some other page. It should be full of 0xff */
+    read_page(test_data, some_page_addr, page);
+    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+        g_assert_cmphex(page[i], ==, 0xffffffff);
+    }
+
+    flash_reset(test_data);
+}
+
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 #include "libqtest-single.h"
 #include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
 
-/*
- * ASPEED SPI Controller registers
- */
-#define R_CONF              0x00
-#define   CONF_ENABLE_W0       16
-#define R_CE_CTRL           0x04
-#define   CRTL_EXTENDED0       0  /* 32 bit addressing for SPI */
-#define R_CTRL0             0x10
-#define   CTRL_IO_QUAD_IO      BIT(31)
-#define   CTRL_CE_STOP_ACTIVE  BIT(2)
-#define   CTRL_READMODE        0x0
-#define   CTRL_FREADMODE       0x1
-#define   CTRL_WRITEMODE       0x2
-#define   CTRL_USERMODE        0x3
-#define SR_WEL BIT(1)
-
-/*
- * Flash commands
- */
-enum {
-    JEDEC_READ = 0x9f,
-    RDSR = 0x5,
-    WRDI = 0x4,
-    BULK_ERASE = 0xc7,
-    READ = 0x03,
-    PP = 0x02,
-    WRSR = 0x1,
-    WREN = 0x6,
-    SRWD = 0x80,
-    RESET_ENABLE = 0x66,
-    RESET_MEMORY = 0x99,
-    EN_4BYTE_ADDR = 0xB7,
-    ERASE_SECTOR = 0xd8,
-};
-
-#define CTRL_IO_MODE_MASK  (BIT(31) | BIT(30) | BIT(29) | BIT(28))
-#define FLASH_PAGE_SIZE           256
-
-typedef struct TestData {
-    QTestState *s;
-    uint64_t spi_base;
-    uint64_t flash_base;
-    uint32_t jedec_id;
-    char *tmp_path;
-    uint8_t cs;
-    const char *node;
-    uint32_t page_addr;
-} TestData;
-
-/*
- * Use an explicit bswap for the values read/wrote to the flash region
- * as they are BE and the Aspeed CPU is LE.
- */
-static inline uint32_t make_be32(uint32_t data)
-{
-    return bswap32(data);
-}
-
-static inline void spi_writel(const TestData *data, uint64_t offset,
-                              uint32_t value)
-{
-    qtest_writel(data->s, data->spi_base + offset, value);
-}
-
-static inline uint32_t spi_readl(const TestData *data, uint64_t offset)
-{
-    return qtest_readl(data->s, data->spi_base + offset);
-}
-
-static inline void flash_writeb(const TestData *data, uint64_t offset,
-                                uint8_t value)
-{
-    qtest_writeb(data->s, data->flash_base + offset, value);
-}
-
-static inline void flash_writel(const TestData *data, uint64_t offset,
-                                uint32_t value)
-{
-    qtest_writel(data->s, data->flash_base + offset, value);
-}
-
-static inline uint8_t flash_readb(const TestData *data, uint64_t offset)
-{
-    return qtest_readb(data->s, data->flash_base + offset);
-}
-
-static inline uint32_t flash_readl(const TestData *data, uint64_t offset)
-{
-    return qtest_readl(data->s, data->flash_base + offset);
-}
-
-static void spi_conf(const TestData *data, uint32_t value)
-{
-    uint32_t conf = spi_readl(data, R_CONF);
-
-    conf |= value;
-    spi_writel(data, R_CONF, conf);
-}
-
-static void spi_conf_remove(const TestData *data, uint32_t value)
-{
-    uint32_t conf = spi_readl(data, R_CONF);
-
-    conf &= ~value;
-    spi_writel(data, R_CONF, conf);
-}
-
-static void spi_ce_ctrl(const TestData *data, uint32_t value)
-{
-    uint32_t conf = spi_readl(data, R_CE_CTRL);
-
-    conf |= value;
-    spi_writel(data, R_CE_CTRL, conf);
-}
-
-static void spi_ctrl_setmode(const TestData *data, uint8_t mode, uint8_t cmd)
-{
-    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
-    uint32_t ctrl = spi_readl(data, ctrl_reg);
-    ctrl &= ~(CTRL_USERMODE | 0xff << 16);
-    ctrl |= mode | (cmd << 16);
-    spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_start_user(const TestData *data)
-{
-    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
-    uint32_t ctrl = spi_readl(data, ctrl_reg);
-
-    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, ctrl_reg, ctrl);
-
-    ctrl &= ~CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_stop_user(const TestData *data)
-{
-    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
-    uint32_t ctrl = spi_readl(data, ctrl_reg);
-
-    ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE;
-    spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void spi_ctrl_set_io_mode(const TestData *data, uint32_t value)
-{
-    uint32_t ctrl_reg = R_CTRL0 + data->cs * 4;
-    uint32_t ctrl = spi_readl(data, ctrl_reg);
-    uint32_t mode;
-
-    mode = value & CTRL_IO_MODE_MASK;
-    ctrl &= ~CTRL_IO_MODE_MASK;
-    ctrl |= mode;
-    spi_writel(data, ctrl_reg, ctrl);
-}
-
-static void flash_reset(const TestData *data)
-{
-    spi_conf(data, 1 << (CONF_ENABLE_W0 + data->cs));
-
-    spi_ctrl_start_user(data);
-    flash_writeb(data, 0, RESET_ENABLE);
-    flash_writeb(data, 0, RESET_MEMORY);
-    flash_writeb(data, 0, WREN);
-    flash_writeb(data, 0, BULK_ERASE);
-    flash_writeb(data, 0, WRDI);
-    spi_ctrl_stop_user(data);
-
-    spi_conf_remove(data, 1 << (CONF_ENABLE_W0 + data->cs));
-}
-
-static void test_read_jedec(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t jedec = 0x0;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, JEDEC_READ);
-    jedec |= flash_readb(test_data, 0) << 16;
-    jedec |= flash_readb(test_data, 0) << 8;
-    jedec |= flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-
-    flash_reset(test_data);
-
-    g_assert_cmphex(jedec, ==, test_data->jedec_id);
-}
-
-static void read_page(const TestData *data, uint32_t addr, uint32_t *page)
-{
-    int i;
-
-    spi_ctrl_start_user(data);
-
-    flash_writeb(data, 0, EN_4BYTE_ADDR);
-    flash_writeb(data, 0, READ);
-    flash_writel(data, 0, make_be32(addr));
-
-    /* Continuous read are supported */
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        page[i] = make_be32(flash_readl(data, 0));
-    }
-    spi_ctrl_stop_user(data);
-}
-
-static void read_page_mem(const TestData *data, uint32_t addr, uint32_t *page)
-{
-    int i;
-
-    /* move out USER mode to use direct reads from the AHB bus */
-    spi_ctrl_setmode(data, CTRL_READMODE, READ);
-
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        page[i] = make_be32(flash_readl(data, addr + i * 4));
-    }
-}
-
-static void write_page_mem(const TestData *data, uint32_t addr,
-                           uint32_t write_value)
-{
-    spi_ctrl_setmode(data, CTRL_WRITEMODE, PP);
-
-    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(data, addr + i * 4, write_value);
-    }
-}
-
-static void assert_page_mem(const TestData *data, uint32_t addr,
-                            uint32_t expected_value)
-{
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    read_page_mem(data, addr, page);
-    for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, expected_value);
-    }
-}
-
-static void test_erase_sector(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t some_page_addr = test_data->page_addr;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    int i;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    /*
-     * Previous page should be full of 0xffs after backend is
-     * initialized
-     */
-    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, PP);
-    flash_writel(test_data, 0, make_be32(some_page_addr));
-
-    /* Fill the page with its own addresses */
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
-    }
-    spi_ctrl_stop_user(test_data);
-
-    /* Check the page is correctly written */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
-    }
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, ERASE_SECTOR);
-    flash_writel(test_data, 0, make_be32(some_page_addr));
-    spi_ctrl_stop_user(test_data);
-
-    /* Check the page is erased */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_erase_all(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t some_page_addr = test_data->page_addr;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    int i;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    /*
-     * Previous page should be full of 0xffs after backend is
-     * initialized
-     */
-    read_page(test_data, some_page_addr - FLASH_PAGE_SIZE, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, PP);
-    flash_writel(test_data, 0, make_be32(some_page_addr));
-
-    /* Fill the page with its own addresses */
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, 0, make_be32(some_page_addr + i * 4));
-    }
-    spi_ctrl_stop_user(test_data);
-
-    /* Check the page is correctly written */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
-    }
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, BULK_ERASE);
-    spi_ctrl_stop_user(test_data);
-
-    /* Check the page is erased */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_write_page(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = test_data->page_addr;
-    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    int i;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, PP);
-    flash_writel(test_data, 0, make_be32(my_page_addr));
-
-    /* Fill the page with its own addresses */
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
-    }
-    spi_ctrl_stop_user(test_data);
-
-    /* Check what was written */
-    read_page(test_data, my_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
-    }
-
-    /* Check some other page. It should be full of 0xff */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_read_page_mem(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = test_data->page_addr;
-    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    int i;
-
-    /*
-     * Enable 4BYTE mode for controller.
-     */
-    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-
-    /* Enable 4BYTE mode for flash. */
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, PP);
-    flash_writel(test_data, 0, make_be32(my_page_addr));
-
-    /* Fill the page with its own addresses */
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
-    }
-    spi_ctrl_stop_user(test_data);
-    spi_conf_remove(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    /* Check what was written */
-    read_page_mem(test_data, my_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
-    }
-
-    /* Check some other page. It should be full of 0xff */
-    read_page_mem(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_write_page_mem(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = test_data->page_addr;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    int i;
-
-    /*
-     * Enable 4BYTE mode for controller.
-     */
-    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-
-    /* Enable 4BYTE mode for flash. */
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    spi_ctrl_stop_user(test_data);
-
-    /* move out USER mode to use direct writes to the AHB bus */
-    spi_ctrl_setmode(test_data, CTRL_WRITEMODE, PP);
-
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, my_page_addr + i * 4,
-               make_be32(my_page_addr + i * 4));
-    }
-
-    /* Check what was written */
-    read_page_mem(test_data, my_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_read_status_reg(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint8_t r;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-
-    g_assert_cmphex(r & SR_WEL, ==, 0);
-    g_assert(!qtest_qom_get_bool
-            (test_data->s, test_data->node, "write-enable"));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-
-    g_assert_cmphex(r & SR_WEL, ==, SR_WEL);
-    g_assert(qtest_qom_get_bool
-            (test_data->s, test_data->node, "write-enable"));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WRDI);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-
-    g_assert_cmphex(r & SR_WEL, ==, 0);
-    g_assert(!qtest_qom_get_bool
-            (test_data->s, test_data->node, "write-enable"));
-
-    flash_reset(test_data);
-}
-
-static void test_status_reg_write_protection(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint8_t r;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    /* default case: WP# is high and SRWD is low -> status register writable */
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    /* test ability to write SRWD */
-    flash_writeb(test_data, 0, WRSR);
-    flash_writeb(test_data, 0, SRWD);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-    g_assert_cmphex(r & SRWD, ==, SRWD);
-
-    /* WP# high and SRWD high -> status register writable */
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    /* test ability to write SRWD */
-    flash_writeb(test_data, 0, WRSR);
-    flash_writeb(test_data, 0, 0);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-    g_assert_cmphex(r & SRWD, ==, 0);
-
-    /* WP# low and SRWD low -> status register writable */
-    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 0);
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, WREN);
-    /* test ability to write SRWD */
-    flash_writeb(test_data, 0, WRSR);
-    flash_writeb(test_data, 0, SRWD);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-    g_assert_cmphex(r & SRWD, ==, SRWD);
-
-    /* WP# low and SRWD high -> status register NOT writable */
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0 , WREN);
-    /* test ability to write SRWD */
-    flash_writeb(test_data, 0, WRSR);
-    flash_writeb(test_data, 0, 0);
-    flash_writeb(test_data, 0, RDSR);
-    r = flash_readb(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-    /* write is not successful */
-    g_assert_cmphex(r & SRWD, ==, SRWD);
-
-    qtest_set_irq_in(test_data->s, test_data->node, "WP#", 0, 1);
-    flash_reset(test_data);
-}
-
-static void test_write_block_protect(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t sector_size = 65536;
-    uint32_t n_sectors = 512;
-
-    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    uint32_t bp_bits = 0b0;
-
-    for (int i = 0; i < 16; i++) {
-        bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
-
-        spi_ctrl_start_user(test_data);
-        flash_writeb(test_data, 0, WREN);
-        flash_writeb(test_data, 0, BULK_ERASE);
-        flash_writeb(test_data, 0, WREN);
-        flash_writeb(test_data, 0, WRSR);
-        flash_writeb(test_data, 0, bp_bits);
-        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-        flash_writeb(test_data, 0, WREN);
-        spi_ctrl_stop_user(test_data);
-
-        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
-        uint32_t protection_start = n_sectors - num_protected_sectors;
-        uint32_t protection_end = n_sectors;
-
-        for (int sector = 0; sector < n_sectors; sector++) {
-            uint32_t addr = sector * sector_size;
-
-            assert_page_mem(test_data, addr, 0xffffffff);
-            write_page_mem(test_data, addr, make_be32(0xabcdef12));
-
-            uint32_t expected_value = protection_start <= sector
-                                      && sector < protection_end
-                                      ? 0xffffffff : 0xabcdef12;
-
-            assert_page_mem(test_data, addr, expected_value);
-        }
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_write_block_protect_bottom_bit(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t sector_size = 65536;
-    uint32_t n_sectors = 512;
-
-    spi_ce_ctrl(test_data, 1 << (CRTL_EXTENDED0 + test_data->cs));
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    /* top bottom bit is enabled */
-    uint32_t bp_bits = 0b00100 << 3;
-
-    for (int i = 0; i < 16; i++) {
-        bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
-
-        spi_ctrl_start_user(test_data);
-        flash_writeb(test_data, 0, WREN);
-        flash_writeb(test_data, 0, BULK_ERASE);
-        flash_writeb(test_data, 0, WREN);
-        flash_writeb(test_data, 0, WRSR);
-        flash_writeb(test_data, 0, bp_bits);
-        flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-        flash_writeb(test_data, 0, WREN);
-        spi_ctrl_stop_user(test_data);
-
-        uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
-        uint32_t protection_start = 0;
-        uint32_t protection_end = num_protected_sectors;
-
-        for (int sector = 0; sector < n_sectors; sector++) {
-            uint32_t addr = sector * sector_size;
-
-            assert_page_mem(test_data, addr, 0xffffffff);
-            write_page_mem(test_data, addr, make_be32(0xabcdef12));
-
-            uint32_t expected_value = protection_start <= sector
-                                      && sector < protection_end
-                                      ? 0xffffffff : 0xabcdef12;
-
-            assert_page_mem(test_data, addr, expected_value);
-        }
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_write_page_qpi(const void *data)
-{
-    const TestData *test_data = (const TestData *)data;
-    uint32_t my_page_addr = test_data->page_addr;
-    uint32_t some_page_addr = my_page_addr + FLASH_PAGE_SIZE;
-    uint32_t page[FLASH_PAGE_SIZE / 4];
-    uint32_t page_pattern[] = {
-        0xebd8c134, 0x5da196bc, 0xae15e729, 0x5085ccdf
-    };
-    int i;
-
-    spi_conf(test_data, 1 << (CONF_ENABLE_W0 + test_data->cs));
-
-    spi_ctrl_start_user(test_data);
-    flash_writeb(test_data, 0, EN_4BYTE_ADDR);
-    flash_writeb(test_data, 0, WREN);
-    flash_writeb(test_data, 0, PP);
-    flash_writel(test_data, 0, make_be32(my_page_addr));
-
-    /* Set QPI mode */
-    spi_ctrl_set_io_mode(test_data, CTRL_IO_QUAD_IO);
-
-    /* Fill the page pattern */
-    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
-        flash_writel(test_data, 0, make_be32(page_pattern[i]));
-    }
-
-    /* Fill the page with its own addresses */
-    for (; i < FLASH_PAGE_SIZE / 4; i++) {
-        flash_writel(test_data, 0, make_be32(my_page_addr + i * 4));
-    }
-
-    /* Restore io mode */
-    spi_ctrl_set_io_mode(test_data, 0);
-    spi_ctrl_stop_user(test_data);
-
-    /* Check what was written */
-    read_page(test_data, my_page_addr, page);
-    for (i = 0; i < ARRAY_SIZE(page_pattern); i++) {
-        g_assert_cmphex(page[i], ==, page_pattern[i]);
-    }
-    for (; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, my_page_addr + i * 4);
-    }
-
-    /* Check some other page. It should be full of 0xff */
-    read_page(test_data, some_page_addr, page);
-    for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
-        g_assert_cmphex(page[i], ==, 0xffffffff);
-    }
-
-    flash_reset(test_data);
-}
-
-static void test_palmetto_bmc(TestData *data)
+static void test_palmetto_bmc(AspeedSMCTestData *data)
 {
     int ret;
     int fd;
@@ -XXX,XX +XXX,XX @@ static void test_palmetto_bmc(TestData *data)
     /* beyond 16MB */
     data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 
-    qtest_add_data_func("/ast2400/smc/read_jedec", data, test_read_jedec);
-    qtest_add_data_func("/ast2400/smc/erase_sector", data, test_erase_sector);
-    qtest_add_data_func("/ast2400/smc/erase_all",  data, test_erase_all);
-    qtest_add_data_func("/ast2400/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2400/smc/read_jedec",
+                        data, aspeed_smc_test_read_jedec);
+    qtest_add_data_func("/ast2400/smc/erase_sector",
+                        data, aspeed_smc_test_erase_sector);
+    qtest_add_data_func("/ast2400/smc/erase_all",
+                        data, aspeed_smc_test_erase_all);
+    qtest_add_data_func("/ast2400/smc/write_page",
+                        data, aspeed_smc_test_write_page);
     qtest_add_data_func("/ast2400/smc/read_page_mem",
-                        data, test_read_page_mem);
+                        data, aspeed_smc_test_read_page_mem);
     qtest_add_data_func("/ast2400/smc/write_page_mem",
-                        data, test_write_page_mem);
+                        data, aspeed_smc_test_write_page_mem);
     qtest_add_data_func("/ast2400/smc/read_status_reg",
-                        data, test_read_status_reg);
+                        data, aspeed_smc_test_read_status_reg);
     qtest_add_data_func("/ast2400/smc/status_reg_write_protection",
-                        data, test_status_reg_write_protection);
+                        data, aspeed_smc_test_status_reg_write_protection);
     qtest_add_data_func("/ast2400/smc/write_block_protect",
-                        data, test_write_block_protect);
+                        data, aspeed_smc_test_write_block_protect);
     qtest_add_data_func("/ast2400/smc/write_block_protect_bottom_bit",
-                        data, test_write_block_protect_bottom_bit);
+                        data, aspeed_smc_test_write_block_protect_bottom_bit);
 }
 
-static void test_ast2500_evb(TestData *data)
+static void test_ast2500_evb(AspeedSMCTestData *data)
 {
     int ret;
     int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast2500_evb(TestData *data)
     /* beyond 16MB */
     data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 
-    qtest_add_data_func("/ast2500/smc/read_jedec", data, test_read_jedec);
-    qtest_add_data_func("/ast2500/smc/erase_sector", data, test_erase_sector);
-    qtest_add_data_func("/ast2500/smc/erase_all",  data, test_erase_all);
-    qtest_add_data_func("/ast2500/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2500/smc/read_jedec",
+                        data, aspeed_smc_test_read_jedec);
+    qtest_add_data_func("/ast2500/smc/erase_sector",
+                        data, aspeed_smc_test_erase_sector);
+    qtest_add_data_func("/ast2500/smc/erase_all",
+                        data, aspeed_smc_test_erase_all);
+    qtest_add_data_func("/ast2500/smc/write_page",
+                        data, aspeed_smc_test_write_page);
     qtest_add_data_func("/ast2500/smc/read_page_mem",
-                        data, test_read_page_mem);
+                        data, aspeed_smc_test_read_page_mem);
     qtest_add_data_func("/ast2500/smc/write_page_mem",
-                        data, test_write_page_mem);
+                        data, aspeed_smc_test_write_page_mem);
     qtest_add_data_func("/ast2500/smc/read_status_reg",
-                        data, test_read_status_reg);
+                        data, aspeed_smc_test_read_status_reg);
     qtest_add_data_func("/ast2500/smc/write_page_qpi",
-                        data, test_write_page_qpi);
+                        data, aspeed_smc_test_write_page_qpi);
 }
 
-static void test_ast2600_evb(TestData *data)
+static void test_ast2600_evb(AspeedSMCTestData *data)
 {
     int ret;
     int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast2600_evb(TestData *data)
     /* beyond 16MB */
     data->page_addr = 0x14000 * FLASH_PAGE_SIZE;
 
-    qtest_add_data_func("/ast2600/smc/read_jedec", data, test_read_jedec);
-    qtest_add_data_func("/ast2600/smc/erase_sector", data, test_erase_sector);
-    qtest_add_data_func("/ast2600/smc/erase_all",  data, test_erase_all);
-    qtest_add_data_func("/ast2600/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast2600/smc/read_jedec",
+                        data, aspeed_smc_test_read_jedec);
+    qtest_add_data_func("/ast2600/smc/erase_sector",
+                        data, aspeed_smc_test_erase_sector);
+    qtest_add_data_func("/ast2600/smc/erase_all",
+                        data, aspeed_smc_test_erase_all);
+    qtest_add_data_func("/ast2600/smc/write_page",
+                        data, aspeed_smc_test_write_page);
     qtest_add_data_func("/ast2600/smc/read_page_mem",
-                        data, test_read_page_mem);
+                        data, aspeed_smc_test_read_page_mem);
     qtest_add_data_func("/ast2600/smc/write_page_mem",
-                        data, test_write_page_mem);
+                        data, aspeed_smc_test_write_page_mem);
     qtest_add_data_func("/ast2600/smc/read_status_reg",
-                        data, test_read_status_reg);
+                        data, aspeed_smc_test_read_status_reg);
     qtest_add_data_func("/ast2600/smc/write_page_qpi",
-                        data, test_write_page_qpi);
+                        data, aspeed_smc_test_write_page_qpi);
 }
 
-static void test_ast1030_evb(TestData *data)
+static void test_ast1030_evb(AspeedSMCTestData *data)
 {
     int ret;
     int fd;
@@ -XXX,XX +XXX,XX @@ static void test_ast1030_evb(TestData *data)
     /* beyond 512KB */
     data->page_addr = 0x800 * FLASH_PAGE_SIZE;
 
-    qtest_add_data_func("/ast1030/smc/read_jedec", data, test_read_jedec);
-    qtest_add_data_func("/ast1030/smc/erase_sector", data, test_erase_sector);
-    qtest_add_data_func("/ast1030/smc/erase_all",  data, test_erase_all);
-    qtest_add_data_func("/ast1030/smc/write_page", data, test_write_page);
+    qtest_add_data_func("/ast1030/smc/read_jedec",
+                        data, aspeed_smc_test_read_jedec);
+    qtest_add_data_func("/ast1030/smc/erase_sector",
+                        data, aspeed_smc_test_erase_sector);
+    qtest_add_data_func("/ast1030/smc/erase_all",
+                        data, aspeed_smc_test_erase_all);
+    qtest_add_data_func("/ast1030/smc/write_page",
+                        data, aspeed_smc_test_write_page);
     qtest_add_data_func("/ast1030/smc/read_page_mem",
-                        data, test_read_page_mem);
+                        data, aspeed_smc_test_read_page_mem);
     qtest_add_data_func("/ast1030/smc/write_page_mem",
-                        data, test_write_page_mem);
+                        data, aspeed_smc_test_write_page_mem);
     qtest_add_data_func("/ast1030/smc/read_status_reg",
-                        data, test_read_status_reg);
+                        data, aspeed_smc_test_read_status_reg);
     qtest_add_data_func("/ast1030/smc/write_page_qpi",
-                        data, test_write_page_qpi);
+                        data, aspeed_smc_test_write_page_qpi);
 }
 
 int main(int argc, char **argv)
 {
-    TestData palmetto_data;
-    TestData ast2500_evb_data;
-    TestData ast2600_evb_data;
-    TestData ast1030_evb_data;
+    AspeedSMCTestData palmetto_data;
+    AspeedSMCTestData ast2500_evb_data;
+    AspeedSMCTestData ast2600_evb_data;
+    AspeedSMCTestData ast1030_evb_data;
     int ret;
 
     g_test_init(&argc, &argv, NULL);
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests = {
   'virtio-net-failover': files('migration-helpers.c'),
   'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
   'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
+  'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
 }
 
 if vnc.found()
-- 
2.47.1

From: Jamin Lin <jamin_lin@aspeedtech.com>

Add test_ast2700_evb function and reused testcases which are from
aspeed_smc-test.c for AST2700 testing. The base address, flash base address
and ce index of fmc_cs0 are 0x14000000, 0x100000000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q01jvq" whose size is 128MB,
so set jedec_id 0xef4021.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/r/20241127091543.1243114-11-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
 tests/qtest/ast2700-smc-test.c | 71 ++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build        |  4 +-
 2 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/ast2700-smc-test.c

diff --git a/tests/qtest/ast2700-smc-test.c b/tests/qtest/ast2700-smc-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/ast2700-smc-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTest testcase for the M25P80 Flash using the ASPEED SPI Controller since
+ * AST2700.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright (C) 2024 ASPEED Technology Inc.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bswap.h"
+#include "libqtest-single.h"
+#include "qemu/bitops.h"
+#include "aspeed-smc-utils.h"
+
+static void test_ast2700_evb(AspeedSMCTestData *data)
+{
+    int ret;
+    int fd;
+
+    fd = g_file_open_tmp("qtest.m25p80.w25q01jvq.XXXXXX",
+                         &data->tmp_path, NULL);
+    g_assert(fd >= 0);
+    ret = ftruncate(fd, 128 * 1024 * 1024);
+    g_assert(ret == 0);
+    close(fd);
+
+    data->s = qtest_initf("-machine ast2700-evb "
+                          "-drive file=%s,format=raw,if=mtd",
+                          data->tmp_path);
+
+    /* fmc cs0 with w25q01jvq flash */
+    data->flash_base = 0x100000000;
+    data->spi_base = 0x14000000;
+    data->jedec_id = 0xef4021;
+    data->cs = 0;
+    data->node = "/machine/soc/fmc/ssi.0/child[0]";
+    /* beyond 64MB */
+    data->page_addr = 0x40000 * FLASH_PAGE_SIZE;
+
+    qtest_add_data_func("/ast2700/smc/read_jedec",
+                        data, aspeed_smc_test_read_jedec);
+    qtest_add_data_func("/ast2700/smc/erase_sector",
+                        data, aspeed_smc_test_erase_sector);
+    qtest_add_data_func("/ast2700/smc/erase_all",
+                        data, aspeed_smc_test_erase_all);
+    qtest_add_data_func("/ast2700/smc/write_page",
+                        data, aspeed_smc_test_write_page);
+    qtest_add_data_func("/ast2700/smc/read_page_mem",
+                        data, aspeed_smc_test_read_page_mem);
+    qtest_add_data_func("/ast2700/smc/write_page_mem",
+                        data, aspeed_smc_test_write_page_mem);
+    qtest_add_data_func("/ast2700/smc/read_status_reg",
+                        data, aspeed_smc_test_read_status_reg);
+    qtest_add_data_func("/ast2700/smc/write_page_qpi",
+                        data, aspeed_smc_test_write_page_qpi);
+}
+
+int main(int argc, char **argv)
+{
+    AspeedSMCTestData ast2700_evb_data;
+    int ret;
+
+    g_test_init(&argc, &argv, NULL);
+
+    test_ast2700_evb(&ast2700_evb_data);
+    ret = g_test_run();
+
+    qtest_quit(ast2700_evb_data.s);
+    unlink(ast2700_evb_data.tmp_path);
+    return ret;
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_aspeed = \
    'aspeed_smc-test',
    'aspeed_gpio-test']
 qtests_aspeed64 = \
-  ['ast2700-gpio-test']
+  ['ast2700-gpio-test',
+   'ast2700-smc-test']
 
 qtests_stm32l4x5 = \
   ['stm32l4x5_exti-test',
@@ -XXX,XX +XXX,XX @@ qtests = {
   'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
   'netdev-socket': files('netdev-socket.c', '../unit/socket-helpers.c'),
   'aspeed_smc-test': files('aspeed-smc-utils.c', 'aspeed_smc-test.c'),
+  'ast2700-smc-test': files('aspeed-smc-utils.c', 'ast2700-smc-test.c'),
 }
 
 if vnc.found()
-- 
2.47.1