Series comparison

-[PULL 00/16] aspeed queue
+[PULL 00/12] aspeed queue
-The following changes since commit 0529245488865038344d64fff7ee05864d3d17f6:
+The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:
-  Merge tag 'pull-target-arm-20221020' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-10-20 14:36:12 -0400)
+  Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)
 are available in the Git repository at:
-  https://github.com/legoater/qemu/ tags/pull-aspeed-20221025
+  https://github.com/legoater/qemu/ tags/pull-aspeed-20231025
-for you to fetch changes up to 703229132bb05327044368fc6d19f6acf7dde848:
+for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:
-  arm/aspeed: Replace mx25l25635e chip model (2022-10-24 11:20:16 +0200)
+  hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)
 ----------------------------------------------------------------
-aspeed queue :
+aspeed queue:
-* Performance improvement with Object class caching
+* Update of Andrew's email
-* Serial Flash Discovery Parameters support for m25p80 device
+* Split of AspeedSoCState per 2400/2600/10x0
 * Various small adjustments on intructions and models
 ----------------------------------------------------------------
-Alex Bennée (1):
+Andrew Jeffery (1):
-      ssi: cache SSIPeripheralClass to avoid GET_CLASS()
+      MAINTAINERS: aspeed: Update Andrew's email address
-Cédric Le Goater (12):
+Philippe Mathieu-Daudé (11):
-      tests/avocado/machine_aspeed.py: Fix typos on buildroot
+      hw/arm/aspeed: Extract code common to all boards to a common file
-      aspeed/smc: Cache AspeedSMCClass
+      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
-      ast2600: Drop NEON from the CPU features
+      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
-      m25p80: Add basic support for the SFDP command
+      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
-      m25p80: Add the n25q256a SFDP table
+      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
-      m25p80: Add erase size for mx25l25635e
+      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
-      m25p80: Add the mx25l25635e SFPD table
+      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
-      m25p80: Add the mx25l25635f SFPD table
+      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
-      m25p80: Add the mx66l1g45g SFDP table
+      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
-      m25p80: Add the w25q256 SFPD table
+      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
-      m25p80: Add the w25q512jv SFPD table
+      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
       arm/aspeed: Replace mx25l25635e chip model
-Patrick Williams (2):
+ MAINTAINERS                               |   2 +-
-      hw/arm/aspeed: increase Bletchley memory size
+ include/hw/arm/aspeed_soc.h               |  35 +++++-
-      m25p80: Add the w25q01jvq SFPD table
+ hw/arm/aspeed.c                           | 101 +++++++--------
  hw/arm/aspeed_ast10x0.c                   |  53 ++++----
  hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
  hw/arm/aspeed_ast2600.c                   |  75 ++++++------
  hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
  hw/arm/fby35.c                            |  27 ++--
  hw/arm/meson.build                        |   3 +-
 files changed, 363 insertions(+), 284 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
  create mode 100644 hw/arm/aspeed_soc_common.c
-Peter Delevoryas (1):
-      hw/i2c/aspeed: Fix old reg slave receive
- hw/block/m25p80_sfdp.h          |  29 ++++
- include/hw/i2c/aspeed_i2c.h     |   1 +
- include/hw/ssi/aspeed_smc.h     |   2 +
- include/hw/ssi/ssi.h            |   3 +
- hw/arm/aspeed.c                 |  15 +-
- hw/arm/aspeed_ast2600.c         |   2 +
- hw/block/m25p80.c               |  52 ++++++-
- hw/block/m25p80_sfdp.c          | 332 ++++++++++++++++++++++++++++++++++++++++
- hw/i2c/aspeed_i2c.c             |   8 +-
- hw/ssi/aspeed_smc.c             |   9 +-
- hw/ssi/ssi.c                    |  18 +--
- MAINTAINERS                     |   2 +-
- hw/block/meson.build            |   1 +
- hw/block/trace-events           |   1 +
- tests/avocado/machine_aspeed.py |  16 +-
-files changed, 452 insertions(+), 39 deletions(-)
- create mode 100644 hw/block/m25p80_sfdp.h
- create mode 100644 hw/block/m25p80_sfdp.c

-[PULL 01/16] hw/i2c/aspeed: Fix old reg slave receive
+Deleted patch
-From: Peter Delevoryas <peter@pjd.dev>
-I think when Klaus ported his slave mode changes from the original patch
-series to the rewritten I2C module, he changed the behavior of the first
-byte that is received by the slave device.
-What's supposed to happen is that the AspeedI2CBus's slave device's
-i2c_event callback should run, and if the event is "send_async", then it
-should populate the byte buffer with the 8-bit I2C address that is being
-sent to. Since we only support "send_async", the lowest bit should
-always be 0 (indicating that the master is requesting to send data).
-This is the code Klaus had previously, for reference. [1]
-    switch (event) {
-    case I2C_START_SEND:
-        bus->buf = bus->dev_addr << 1;
-        bus->buf &= I2CD_BYTE_BUF_RX_MASK;
-        bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT;
-        bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE);
-        aspeed_i2c_set_state(bus, I2CD_STXD);
-        break;
-[1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/
-Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode")
-Signed-off-by: Peter Delevoryas <peter@pjd.dev>
-Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
-Message-Id: <20220820225712.713209-2-peter@pjd.dev>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- include/hw/i2c/aspeed_i2c.h | 1 +
- hw/i2c/aspeed_i2c.c         | 8 +++++---
-files changed, 6 insertions(+), 3 deletions(-)
-diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/i2c/aspeed_i2c.h
-+++ b/include/hw/i2c/aspeed_i2c.h
-@@ -XXX,XX +XXX,XX @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
-     SHARED_FIELD(M_TX_CMD, 1, 1)
-     SHARED_FIELD(M_START_CMD, 0, 1)
- REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
-+    SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
- REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
-     SHARED_FIELD(RX_COUNT, 24, 5)
-     SHARED_FIELD(RX_SIZE, 16, 5)
-diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/i2c/aspeed_i2c.c
-+++ b/hw/i2c/aspeed_i2c.c
-@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
-     AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
-     uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
-     uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
--    uint32_t value;
-+    uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
-+    uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
-+                                                SLAVE_DEV_ADDR1);
-     if (aspeed_i2c_is_new_mode(bus->controller)) {
-         return aspeed_i2c_bus_new_slave_event(bus, event);
-@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
-     switch (event) {
-     case I2C_START_SEND_ASYNC:
--        value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
--        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << 1);
-+        /* Bit[0] == 0 indicates "send". */
-+        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
-         ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
-         SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
---
-.37.3

-[PULL 02/16] tests/avocado/machine_aspeed.py: Fix typos on buildroot
+Deleted patch
-Replace 'buidroot' and 'builroot' by 'buildroot'.
-Fixes: f7bc7da0724f ("test/avocado/machine_aspeed.py: Add tests using buildroot images")
-Reviewed-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Joel Stanley <joel@jms.id.au>
-Message-Id: <20220923084803.498337-2-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- tests/avocado/machine_aspeed.py | 16 ++++++++--------
-file changed, 8 insertions(+), 8 deletions(-)
-diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
-index XXXXXXX..XXXXXXX 100644
---- a/tests/avocado/machine_aspeed.py
-+++ b/tests/avocado/machine_aspeed.py
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
-         self.do_test_arm_aspeed(image_path)
--    def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
-+    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
-         self.require_netdev('user')
-         self.vm.set_console()
-@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
-         exec_command(self, 'root')
-         time.sleep(0.1)
--    def do_test_arm_aspeed_buidroot_poweroff(self):
-+    def do_test_arm_aspeed_buildroot_poweroff(self):
-         exec_command_and_wait_for_pattern(self, 'poweroff',
-                                           'reboot: System halted');
--    def test_arm_ast2500_evb_builroot(self):
-+    def test_arm_ast2500_evb_buildroot(self):
-         """
-         :avocado: tags=arch:arm
-         :avocado: tags=machine:ast2500-evb
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
-         self.vm.add_args('-device',
-                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
--        self.do_test_arm_aspeed_buidroot_start(image_path, '0x0')
-+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
-         exec_command_and_wait_for_pattern(self,
-              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
-         exec_command_and_wait_for_pattern(self,
-                              'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
--        self.do_test_arm_aspeed_buidroot_poweroff()
-+        self.do_test_arm_aspeed_buildroot_poweroff()
--    def test_arm_ast2600_evb_builroot(self):
-+    def test_arm_ast2600_evb_buildroot(self):
-         """
-         :avocado: tags=arch:arm
-         :avocado: tags=machine:ast2600-evb
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
-                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-         self.vm.add_args('-device',
-                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
--        self.do_test_arm_aspeed_buidroot_start(image_path, '0xf00')
-+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
-         exec_command_and_wait_for_pattern(self,
-              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
-@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
-         year = time.strftime("%Y")
-         exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
--        self.do_test_arm_aspeed_buidroot_poweroff()
-+        self.do_test_arm_aspeed_buildroot_poweroff()
- class AST2x00MachineSDK(QemuSystemTest):
---
-.37.3

-[PULL 07/16] m25p80: Add basic support for the SFDP command
+[PULL 01/12] MAINTAINERS: aspeed: Update Andrew's email address
-JEDEC STANDARD JESD216 for Serial Flash Discovery Parameters (SFDP)
+From: Andrew Jeffery <andrew@codeconstruct.com.au>
 provides a mean to describe the features of a serial flash device
 using a set of internal parameter tables.
-This is the initial framework for the RDSFDP command giving access to
+I've changed employers, have company email that deals with patch-based
-a private SFDP area under the flash. This area now needs to be
+workflows without too much of a headache, and am trying to steer some
-populated with the flash device characteristics, using a new
+content out of my personal mail.
 'sfdp_read' handler under FlashPartInfo.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
 Message-Id: <20220722063602.128144-2-clg@kaod.org>
 Message-Id: <20221013161241.2805140-2-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h | 18 ++++++++++++++++++
+ MAINTAINERS | 2 +-
- hw/block/m25p80.c      | 27 +++++++++++++++++++++++++++
+file changed, 1 insertion(+), 1 deletion(-)
  MAINTAINERS            |  2 +-
  hw/block/trace-events  |  1 +
 files changed, 47 insertions(+), 1 deletion(-)
  create mode 100644 hw/block/m25p80_sfdp.h
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/hw/block/m25p80_sfdp.h
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ * M25P80 SFDP
-+ *
-+ * Copyright (c) 2020, IBM Corporation.
-+ *
-+ * This code is licensed under the GPL version 2 or later. See the
-+ * COPYING file in the top-level directory.
-+ */
-+
-+#ifndef HW_M25P80_SFDP_H
-+#define HW_M25P80_SFDP_H
-+
-+/*
-+ * SFDP area has a 3 bytes address space.
-+ */
-+#define M25P80_SFDP_MAX_SIZE  (1 << 24)
-+
-+#endif
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "trace.h"
- #include "qom/object.h"
-+#include "m25p80_sfdp.h"
- /* 16 MiB max in 3 byte address mode */
- #define MAX_3BYTES_SIZE 0x1000000
-@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
-      * This field inform how many die is in the chip.
-      */
-     uint8_t die_cnt;
-+    uint8_t (*sfdp_read)(uint32_t sfdp_addr);
- } FlashPartInfo;
- /* adapted from linux */
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     BULK_ERASE = 0xc7,
-     READ_FSR = 0x70,
-     RDCR = 0x15,
-+    RDSFDP = 0x5a,
-     READ = 0x03,
-     READ4 = 0x13,
-@@ -XXX,XX +XXX,XX @@ typedef enum {
-     STATE_COLLECTING_DATA,
-     STATE_COLLECTING_VAR_LEN_DATA,
-     STATE_READING_DATA,
-+    STATE_READING_SFDP,
- } CMDState;
- typedef enum {
-@@ -XXX,XX +XXX,XX @@ static inline int get_addr_length(Flash *s)
-     }
-    switch (s->cmd_in_progress) {
-+   case RDSFDP:
-+       return 3;
-    case PP4:
-    case PP4_4:
-    case QPP_4:
-@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
-                           " by device\n");
-         }
-         break;
-+
-+    case RDSFDP:
-+        s->state = STATE_READING_SFDP;
-+        break;
-+
-     default:
-         break;
-     }
-@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
-             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
-         }
-         break;
-+    case RDSFDP:
-+        if (s->pi->sfdp_read) {
-+            s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
-+            s->pos = 0;
-+            s->len = 0;
-+            s->state = STATE_COLLECTING_DATA;
-+            break;
-+        }
-+        /* Fallthrough */
-+
-     default:
-         s->pos = 0;
-         s->len = 1;
-@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
-             }
-         }
-         break;
-+    case STATE_READING_SFDP:
-+        assert(s->pi->sfdp_read);
-+        r = s->pi->sfdp_read(s->cur_addr);
-+        trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
-+        s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
-+        break;
-     default:
-     case STATE_IDLE:
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ SSI
+@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/emcraft-sf2.rst
- M: Alistair Francis <alistair@alistair23.me>
+ ASPEED BMCs
  M: Cédric Le Goater <clg@kaod.org>
  M: Peter Maydell <peter.maydell@linaro.org>
 -R: Andrew Jeffery <andrew@aj.id.au>
 +R: Andrew Jeffery <andrew@codeconstruct.com.au>
  R: Joel Stanley <joel@jms.id.au>
  L: qemu-arm@nongnu.org
  S: Maintained
- F: hw/ssi/*
--F: hw/block/m25p80.c
-+F: hw/block/m25p80*
- F: include/hw/ssi/ssi.h
- X: hw/ssi/xilinx_*
- F: tests/qtest/m25p80-test.c
-diff --git a/hw/block/trace-events b/hw/block/trace-events
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/trace-events
-+++ b/hw/block/trace-events
-@@ -XXX,XX +XXX,XX @@ m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_a
- m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
- m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
- m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
-+m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
- m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
- m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
 --
-.37.3
+.41.0

-[PULL 08/16] m25p80: Add the n25q256a SFDP table
+[PULL 02/12] hw/arm/aspeed: Extract code common to all boards to a common file
-The same values were collected on 4 differents OpenPower systems,
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-palmettos, romulus and tacoma.
+aspeed_soc.c contains definitions specific to the AST2400
-The SFDP table size is defined as being 0x100 bytes but it could be
+and AST2500 SoCs, but also some definitions for other AST
-bigger. Only the mandatory table for basic features is available at
+SoCs: move them to a common file.
-byte 0x30.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-Id: <20220722063602.128144-3-clg@kaod.org>
 Message-Id: <20221013161241.2805140-3-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ hw/arm/aspeed_soc.c        |  96 -------------------------------
- hw/block/m25p80.c      |  8 +++---
+ hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
- hw/block/m25p80_sfdp.c | 58 ++++++++++++++++++++++++++++++++++++++++++
+ hw/arm/meson.build         |   1 +
- hw/block/meson.build   |  1 +
+files changed, 115 insertions(+), 96 deletions(-)
-files changed, 66 insertions(+), 3 deletions(-)
+ create mode 100644 hw/arm/aspeed_soc_common.c
- create mode 100644 hw/block/m25p80_sfdp.c
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
-  */
+ };
- #define M25P80_SFDP_MAX_SIZE  (1 << 24)
+ type_init(aspeed_soc_register_types);
-+uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+-
-+
+-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
- #endif
+-{
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+-    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-index XXXXXXX..XXXXXXX 100644
+-}
---- a/hw/block/m25p80.c
+-
-+++ b/hw/block/m25p80.c
+-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+-{
-     { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, ER_4K) },
+-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, ER_4K) },
+-    SerialMM *smm;
-     { INFO("n25q256a11",  0x20bb19,      0,  64 << 10, 512, ER_4K) },
+-
--    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K) },
+-    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-+    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K),
+-        smm = &s->uart[i];
-+      .sfdp_read = m25p80_sfdp_n25q256a },
+-
-     { INFO("n25q512a11",  0x20bb20,      0,  64 << 10, 1024, ER_4K) },
+-        /* Chardev property is set by the machine. */
-     { INFO("n25q512a13",  0x20ba20,      0,  64 << 10, 1024, ER_4K) },
+-        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-     { INFO("n25q128",     0x20ba18,      0,  64 << 10, 256, 0) },
+-        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
-     { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512,
+-        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
--           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB) },
+-        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
--    { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
+-        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
-+           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
+-            return false;
-+      .sfdp_read = m25p80_sfdp_n25q256a },
+-        }
-+   { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
+-
-     { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
+-        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-     { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
+-        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-     { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
+-    }
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
+-
 -    return true;
 -}
 -
 -void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    int i = dev - ASPEED_DEV_UART1;
 -
 -    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
 -    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
 -}
 -
 -/*
 - * SDMC should be realized first to get correct RAM size and max size
 - * values
 - */
 -bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
 -{
 -    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    ram_addr_t ram_size, max_ram_size;
 -
 -    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
 -                                        &error_abort);
 -    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
 -                                            &error_abort);
 -
 -    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
 -                       max_ram_size);
 -    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
 -
 -    /*
 -     * Add a memory region beyond the RAM region to let firmwares scan
 -     * the address space with load/store and guess how much RAM the
 -     * SoC has.
 -     */
 -    if (ram_size < max_ram_size) {
 -        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
 -
 -        qdev_prop_set_string(dev, "name", "ram-empty");
 -        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
 -        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
 -            return false;
 -        }
 -
 -        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
 -                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
 -    }
 -
 -    memory_region_add_subregion(s->memory,
 -                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
 -    return true;
 -}
 -
 -void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 -{
 -    memory_region_add_subregion(s->memory, addr,
 -                                sysbus_mmio_get_region(dev, n));
 -}
 -
 -void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 -                                   const char *name, hwaddr addr, uint64_t size)
 -{
 -    qdev_prop_set_string(DEVICE(dev), "name", name);
 -    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 -    sysbus_realize(dev, &error_abort);
 -
 -    memory_region_add_subregion_overlap(s->memory, addr,
 -                                        sysbus_mmio_get_region(dev, 0), -1000);
 -}
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/block/m25p80_sfdp.c
++++ b/hw/arm/aspeed_soc_common.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * M25P80 Serial Flash Discoverable Parameter (SFDP)
++ * ASPEED SoC family
 + *
-+ * Copyright (c) 2020, IBM Corporation.
++ * Andrew Jeffery <andrew@aj.id.au>
 + * Jeremy Kerr <jk@ozlabs.org>
 + *
-+ * This code is licensed under the GPL version 2 or later. See the
++ * Copyright 2016 IBM Corp.
-+ * COPYING file in the top-level directory.
++ *
 + * This code is licensed under the GPL version 2 or later.  See
 + * the COPYING file in the top-level directory.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qemu/host-utils.h"
++#include "qapi/error.h"
-+#include "m25p80_sfdp.h"
++#include "hw/misc/unimp.h"
-+
++#include "hw/arm/aspeed_soc.h"
-+#define define_sfdp_read(model)                                       \
++#include "hw/char/serial.h"
-+    uint8_t m25p80_sfdp_##model(uint32_t addr)                        \
++
-+    {                                                                 \
++
-+        assert(is_power_of_2(sizeof(sfdp_##model)));                  \
++qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-+        return sfdp_##model[addr & (sizeof(sfdp_##model) - 1)];       \
++{
 +    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
 +}
 +
 +bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
 +{
 +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 +    SerialMM *smm;
 +
 +    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
 +        smm = &s->uart[i];
 +
 +        /* Chardev property is set by the machine. */
 +        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
 +        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
 +        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
 +        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
 +        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
 +            return false;
 +        }
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
 +        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
 +    }
 +
++    return true;
++}
++
++void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
++{
++    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
++    int i = dev - ASPEED_DEV_UART1;
++
++    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
++    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
++}
++
 +/*
-+ * Micron
++ * SDMC should be realized first to get correct RAM size and max size
 + * values
 + */
-+static const uint8_t sfdp_n25q256a[] = {
++bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
++{
-+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
++    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    ram_addr_t ram_size, max_ram_size;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                                        &error_abort);
-+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
++    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-+    0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
++                                            &error_abort);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
++
-+    0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
++    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
++                       max_ram_size);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    /*
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++     * Add a memory region beyond the RAM region to let firmwares scan
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++     * the address space with load/store and guess how much RAM the
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++     * SoC has.
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++     */
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    if (ram_size < max_ram_size) {
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        qdev_prop_set_string(dev, "name", "ram-empty");
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++            return false;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        }
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    }
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    memory_region_add_subregion(s->memory,
-+};
++                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-+define_sfdp_read(n25q256a);
++    return true;
-diff --git a/hw/block/meson.build b/hw/block/meson.build
++}
 +
 +void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
 +{
 +    memory_region_add_subregion(s->memory, addr,
 +                                sysbus_mmio_get_region(dev, n));
 +}
 +
 +void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 +                                   const char *name, hwaddr addr, uint64_t size)
 +{
 +    qdev_prop_set_string(DEVICE(dev), "name", name);
 +    qdev_prop_set_uint64(DEVICE(dev), "size", size);
 +    sysbus_realize(dev, &error_abort);
 +
 +    memory_region_add_subregion_overlap(s->memory, addr,
 +                                        sysbus_mmio_get_region(dev, 0), -1000);
 +}
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/meson.build
+--- a/hw/arm/meson.build
-+++ b/hw/block/meson.build
++++ b/hw/arm/meson.build
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ONENAND', if_true: files('onenand.c'))
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
- softmmu_ss.add(when: 'CONFIG_PFLASH_CFI01', if_true: files('pflash_cfi01.c'))
+ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
- softmmu_ss.add(when: 'CONFIG_PFLASH_CFI02', if_true: files('pflash_cfi02.c'))
+   'aspeed_soc.c',
- softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
+   'aspeed.c',
-+softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80_sfdp.c'))
++  'aspeed_soc_common.c',
- softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
+   'aspeed_ast2600.c',
- softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
+   'aspeed_ast10x0.c',
- softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c'))
+   'aspeed_eeprom.c',
 --
-.37.3
+.41.0

-[PULL 13/16] m25p80: Add the w25q256 SFPD table
+[PULL 03/12] hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
-The SFDP table size is 0x100 bytes long. Only the mandatory table for
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 basic features is available at byte 0x80.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-Id: <20220722063602.128144-7-clg@kaod.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-Id: <20221013161241.2805140-8-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ hw/arm/aspeed_soc.c | 6 +++---
- hw/block/m25p80.c      |  3 ++-
+file changed, 3 insertions(+), 3 deletions(-)
  hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
 files changed, 44 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
- uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
+     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
- uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+ }
-+uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+-static void aspeed_soc_init(Object *obj)
-+
++static void aspeed_ast2400_soc_init(Object *obj)
- #endif
+ {
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+     AspeedSoCState *s = ASPEED_SOC(obj);
-index XXXXXXX..XXXXXXX 100644
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
---- a/hw/block/m25p80.c
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-+++ b/hw/block/m25p80.c
+ static const TypeInfo aspeed_soc_ast2400_type_info = {
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+     .name           = "ast2400-a1",
-     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
+     .parent         = TYPE_ASPEED_SOC,
-     { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
+-    .instance_init  = aspeed_soc_init,
-     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
++    .instance_init  = aspeed_ast2400_soc_init,
--    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
+     .instance_size  = sizeof(AspeedSoCState),
-+    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
+     .class_init     = aspeed_soc_ast2400_class_init,
 +      .sfdp_read = m25p80_sfdp_w25q256 },
      { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
      { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
  };
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
-index XXXXXXX..XXXXXXX 100644
+ static const TypeInfo aspeed_soc_ast2500_type_info = {
---- a/hw/block/m25p80_sfdp.c
+     .name           = "ast2500-a1",
-+++ b/hw/block/m25p80_sfdp.c
+     .parent         = TYPE_ASPEED_SOC,
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx66l1g45g[] = {
+-    .instance_init  = aspeed_soc_init,
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++    .instance_init  = aspeed_ast2400_soc_init,
      .instance_size  = sizeof(AspeedSoCState),
      .class_init     = aspeed_soc_ast2500_class_init,
  };
- define_sfdp_read(mx66l1g45g);
-+
-+/*
-+ * Windbond
-+ */
-+
-+static const uint8_t sfdp_w25q256[] = {
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
-+    0x00, 0x00, 0x01, 0x09, 0x80, 0x00, 0x00, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
-+    0xff, 0xff, 0x21, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
-+    0x10, 0xd8, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+};
-+define_sfdp_read(w25q256);
 --
-.37.3
+.41.0

-[PULL 12/16] m25p80: Add the mx66l1g45g SFDP table
+[PULL 04/12] hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
-The SFDP table size is 0x200 bytes long. The mandatory table for basic
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 features is available at byte 0x30 plus some more Macronix specific
 tables.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Keep aspeed_soc_class_init() generic, set the realize handler
-Message-Id: <20220722063602.128144-6-clg@kaod.org>
+to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.
-Message-Id: <20221013161241.2805140-7-clg@kaod.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  2 +-
+ hw/arm/aspeed_soc.c | 15 +++++++++++----
- hw/block/m25p80.c      |  3 +-
+file changed, 11 insertions(+), 4 deletions(-)
  hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 files changed, 71 insertions(+), 2 deletions(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/block/m25p80_sfdp.h
++++ b/hw/arm/aspeed_soc.c
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
+     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
- uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+ }
- uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
--
+-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
-+uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
++static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
+ {
- #endif
+     int i;
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+     AspeedSoCState *s = ASPEED_SOC(dev);
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
---- a/hw/block/m25p80.c
+ {
-+++ b/hw/block/m25p80.c
+     DeviceClass *dc = DEVICE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
-     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
+-    dc->realize = aspeed_soc_realize;
-     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
+-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-     { INFO("mx66u1g45g",  0xc2253b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
+-    dc->user_creatable = false;
--    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
+     device_class_set_props(dc, aspeed_soc_properties);
-+    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K),
+ }
-+      .sfdp_read = m25p80_sfdp_mx66l1g45g },
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
-     /* Micron */
+ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
-     { INFO("n25q032a11",  0x20bb16,      0,  64 << 10,  64, ER_4K) },
+ {
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-index XXXXXXX..XXXXXXX 100644
++    DeviceClass *dc = DEVICE_CLASS(oc);
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635f[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(mx25l25635f);
 +
-+static const uint8_t sfdp_mx66l1g45g[] = {
++    dc->realize = aspeed_ast2400_soc_realize;
-+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xff,
++    /* Reason: Uses serial_hds and nd_table in realize() directly */
-+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
++    dc->user_creatable = false;
-+    0xc2, 0x00, 0x01, 0x04, 0x10, 0x01, 0x00, 0xff,
-+    0x84, 0x00, 0x01, 0x02, 0xc0, 0x00, 0x00, 0xff,
+     sc->name         = "ast2400-a1";
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
-+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+ {
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
-+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
++    DeviceClass *dc = DEVICE_CLASS(oc);
-+    0x10, 0xd8, 0x00, 0xff, 0xd6, 0x49, 0xc5, 0x00,
++
-+    0x85, 0xdf, 0x04, 0xe3, 0x44, 0x03, 0x67, 0x38,
++    dc->realize = aspeed_ast2400_soc_realize;
-+    0x30, 0xb0, 0x30, 0xb0, 0xf7, 0xbd, 0xd5, 0x5c,
++    /* Reason: Uses serial_hds and nd_table in realize() directly */
-+    0x4a, 0x9e, 0x29, 0xff, 0xf0, 0x50, 0xf9, 0x85,
++    dc->user_creatable = false;
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     sc->name         = "ast2500-a1";
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0x7f, 0xef, 0xff, 0xff, 0x21, 0x5c, 0xdc, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
 +    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xc2, 0xf5, 0x08, 0x00, 0x0c, 0x04, 0x08, 0x08,
 +    0x01, 0x00, 0x19, 0x0f, 0x01, 0x01, 0x06, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(mx66l1g45g);
 --
-.37.3
+.41.0

-[PULL 16/16] arm/aspeed: Replace mx25l25635e chip model
+[PULL 05/12] hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
-A mx25l25635f chip model is generally found on these machines. It's
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-newer and uses 4B opcodes which is better to exercise the support in
-the Linux kernel.
+We want to derivate the big AspeedSoCState object in some more
+SoC-specific ones. Since the object size will vary, allocate it
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+dynamically.
-Message-Id: <20220722063602.128144-9-clg@kaod.org>
-Message-Id: <20221013161241.2805140-11-clg@kaod.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 6 +++---
+ hw/arm/aspeed.c | 101 +++++++++++++++++++++++++-----------------------
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 52 insertions(+), 49 deletions(-)
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
-     amc->soc_name  = "ast2400-a1";
+     MachineState parent_obj;
-     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
+     /* Public */
-     amc->fmc_model = "n25q256a";
--    amc->spi_model = "mx25l25635e";
+-    AspeedSoCState soc;
-+    amc->spi_model = "mx25l25635f";
++    AspeedSoCState *soc;
-     amc->num_cs    = 1;
+     MemoryRegion boot_rom;
-     amc->i2c_init  = palmetto_bmc_i2c_init;
+     bool mmio_exec;
-     mc->default_ram_size       = 256 * MiB;
+     uint32_t uart_chosen;
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
-     amc->soc_name  = "ast2500-a1";
+ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
-     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
+                                     uint64_t rom_size)
-     amc->fmc_model = "mx25l25635e";
+ {
--    amc->spi_model = "mx25l25635e";
+-    AspeedSoCState *soc = &bmc->soc;
-+    amc->spi_model = "mx25l25635f";
++    AspeedSoCState *soc = bmc->soc;
-     amc->num_cs    = 1;
-     amc->i2c_init  = ast2500_evb_i2c_init;
+     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
-     mc->default_ram_size       = 512 * MiB;
+                            &error_abort);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
-     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
+ static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
-     amc->soc_name  = "ast2500-a1";
+ {
-     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
+     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
--    amc->fmc_model = "mx25l25635e";
+-    AspeedSoCState *s = &bmc->soc;
-+    amc->fmc_model = "mx25l25635f";
++    AspeedSoCState *s = bmc->soc;
-     amc->spi_model = "mx66l1g45g";
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-     amc->num_cs    = 2;
+     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
-     amc->i2c_init  = witherspoon_bmc_i2c_init;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
      int i;
      NICInfo *nd = &nd_table[0];
 -    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 -
 -    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
 +    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
 +    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
 +    object_unref(OBJECT(bmc->soc));
 +    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
      /*
       * This will error out if the RAM size is not supported by the
       * memory controller of the SoC.
       */
 -    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
 +    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                               &error_fatal);
      for (i = 0; i < sc->macs_num; i++) {
          if ((amc->macs_mask & (1 << i)) && nd->used) {
              qemu_check_nic_model(nd, TYPE_FTGMAC100);
 -            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
 +            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
              nd++;
          }
      }
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                              &error_abort);
 -    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
 +    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                              &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "memory",
 +    object_property_set_link(OBJECT(bmc->soc), "memory",
                               OBJECT(get_system_memory()), &error_abort);
 -    object_property_set_link(OBJECT(&bmc->soc), "dram",
 +    object_property_set_link(OBJECT(bmc->soc), "dram",
                               OBJECT(machine->ram), &error_abort);
      if (machine->kernel_filename) {
          /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
           * that runs to unlock the SCU. In this case set the default to
           * be unlocked as the kernel expects
           */
 -        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
 +        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                  ASPEED_SCU_PROT_KEY, &error_abort);
      }
      connect_serial_hds_to_uarts(bmc);
 -    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 +    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
      if (defaults_enabled()) {
 -        aspeed_board_init_flashes(&bmc->soc.fmc,
 +        aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs, 0);
 -        aspeed_board_init_flashes(&bmc->soc.spi[0],
 +        aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
 , amc->num_cs);
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          amc->i2c_init(bmc);
      }
 -    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
 -        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
 +    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
 +        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                             drive_get(IF_SD, 0, i));
      }
 -    if (bmc->soc.emmc.num_slots) {
 -        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
 -                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
 +    if (bmc->soc->emmc.num_slots) {
 +        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
 +                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
      }
      if (!bmc->mmio_exec) {
 -        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
 +        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
          BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
          if (fmc0) {
 -            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
 +            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
              aspeed_install_boot_rom(bmc, fmc0, rom_size);
          }
      }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
  static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
  static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /*
       * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
  static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
  static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
  static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
  static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
       * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
  static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
      at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
  static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* bus 2 : */
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
          {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
          {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
      };
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      uint8_t *eeprom_buf = g_malloc0(8 * 1024);
      DeviceState *dev;
      LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
  static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      DeviceState *dev;
      dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
  static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
  static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *i2c_mux;
      at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
  static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[144] = {};
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
  static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[13] = {};
      for (int i = 0; i < 13; i++) {
          if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
  static void fby35_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CBus *i2c[16];
      for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
  static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
  }
  static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      I2CSlave *therm_mux, *cpuvr_mux;
      /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
  static void fby35_reset(MachineState *state, ShutdownCause reason)
  {
      AspeedMachineState *bmc = ASPEED_MACHINE(state);
 -    AspeedGPIOState *gpio = &bmc->soc.gpio;
 +    AspeedGPIOState *gpio = &bmc->soc->gpio;
      qemu_devices_reset(reason);
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
      sysclk = clock_new(OBJECT(machine), "SYSCLK");
      clock_set_hz(sysclk, SYSCLK_FRQ);
 -    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
 -    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
 +    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
 +    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
 +    object_unref(OBJECT(bmc->soc));
 +    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 -    object_property_set_link(OBJECT(&bmc->soc), "memory",
 +    object_property_set_link(OBJECT(bmc->soc), "memory",
                               OBJECT(get_system_memory()), &error_abort);
      connect_serial_hds_to_uarts(bmc);
 -    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
 +    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 -    aspeed_board_init_flashes(&bmc->soc.fmc,
 +    aspeed_board_init_flashes(&bmc->soc->fmc,
                                bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                                amc->num_cs,
 );
 -    aspeed_board_init_flashes(&bmc->soc.spi[0],
 +    aspeed_board_init_flashes(&bmc->soc->spi[0],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, amc->num_cs);
 -    aspeed_board_init_flashes(&bmc->soc.spi[1],
 +    aspeed_board_init_flashes(&bmc->soc->spi[1],
                                bmc->spi_model ? bmc->spi_model : amc->spi_model,
                                amc->num_cs, (amc->num_cs * 2));
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
  static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
  {
 -    AspeedSoCState *soc = &bmc->soc;
 +    AspeedSoCState *soc = bmc->soc;
      /* U10 24C08 connects to SDA/SCL Group 1 by default */
      uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 --
-.37.3
+.41.0

-[PULL 15/16] m25p80: Add the w25q01jvq SFPD table
+[PULL 06/12] hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
-From: Patrick Williams <patrick@stwcx.xyz>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Generated from hardware using the following command and then padding
+TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
-with 0xff to fill out a power-of-2:
+In few commits we'll add more fields, but to keep
-    hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`
+review process simple, don't add any yet.
-Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 [ clg: removed extern ]
 Message-Id: <20221006224424.3556372-1-patrick@stwcx.xyz>
 Message-Id: <20221013161241.2805140-10-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  2 ++
+ include/hw/arm/aspeed_soc.h |  7 +++++++
- hw/block/m25p80.c      |  3 ++-
+ hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
- hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
+files changed, 20 insertions(+), 13 deletions(-)
 files changed, 40 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/block/m25p80_sfdp.h
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
- uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+ #define TYPE_ASPEED_SOC "aspeed-soc"
- uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
-+uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
++struct Aspeed10x0SoCState {
 +    AspeedSoCState parent;
 +};
 +
- #endif
++#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
 +
  struct AspeedSoCClass {
      DeviceClass parent_class;
 diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/arm/aspeed_ast10x0.c
-+++ b/hw/block/m25p80.c
++++ b/hw/arm/aspeed_ast10x0.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
-       .sfdp_read = m25p80_sfdp_w25q256 },
+     sc->get_irq = aspeed_soc_ast1030_get_irq;
-     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
+ }
-       .sfdp_read = m25p80_sfdp_w25q512jv },
--    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
+-static const TypeInfo aspeed_soc_ast1030_type_info = {
-+    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
+-    .name          = "ast1030-a1",
-+      .sfdp_read = m25p80_sfdp_w25q01jvq },
+-    .parent        = TYPE_ASPEED_SOC,
 -    .instance_size = sizeof(AspeedSoCState),
 -    .instance_init = aspeed_soc_ast1030_init,
 -    .class_init    = aspeed_soc_ast1030_class_init,
 -    .class_size    = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast10x0_types[] = {
 +    {
 +        .name           = TYPE_ASPEED10X0_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed10x0SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast1030-a1",
 +        .parent         = TYPE_ASPEED10X0_SOC,
 +        .instance_init  = aspeed_soc_ast1030_init,
 +        .class_init     = aspeed_soc_ast1030_class_init,
 +    },
  };
- typedef enum {
+-static void aspeed_soc_register_types(void)
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
+-{
-index XXXXXXX..XXXXXXX 100644
+-    type_register_static(&aspeed_soc_ast1030_type_info);
---- a/hw/block/m25p80_sfdp.c
+-}
-+++ b/hw/block/m25p80_sfdp.c
+-
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q512jv[] = {
+-type_init(aspeed_soc_register_types)
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
++DEFINE_TYPES(aspeed_soc_ast10x0_types)
  };
  define_sfdp_read(w25q512jv);
 +
 +static const uint8_t sfdp_w25q01jvq[] = {
 +    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
 +    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
 +    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
 +    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
 +    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
 +    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
 +    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
 +    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
 +    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(w25q01jvq);
 --
-.37.3
+.41.0

-[PULL 14/16] m25p80: Add the w25q512jv SFPD table
+[PULL 07/12] hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
-The SFDP table size is 0x100 bytes long. The mandatory table for basic
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 features is available at byte 0x80 and two extra Winbond specifics
 table are available at 0xC0 and 0xF0.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
-Message-Id: <20220722063602.128144-8-clg@kaod.org>
+In few commits we'll add more fields, but to keep
-Message-Id: <20221013161241.2805140-9-clg@kaod.org>
+review process simple, don't add any yet.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  1 +
+ include/hw/arm/aspeed_soc.h |  7 +++++++
- hw/block/m25p80.c      |  3 ++-
+ hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
- hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
+files changed, 20 insertions(+), 13 deletions(-)
 files changed, 39 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/block/m25p80_sfdp.h
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
+@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
- uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
+ #define TYPE_ASPEED_SOC "aspeed-soc"
+ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
- uint8_t m25p80_sfdp_w25q256(uint32_t addr);
-+uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
++struct Aspeed2600SoCState {
++    AspeedSoCState parent;
- #endif
++};
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++
 +#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
 +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 +
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
  };
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/arm/aspeed_ast2600.c
-+++ b/hw/block/m25p80.c
++++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
-     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
+     sc->get_irq      = aspeed_soc_ast2600_get_irq;
-     { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
+ }
-       .sfdp_read = m25p80_sfdp_w25q256 },
--    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
+-static const TypeInfo aspeed_soc_ast2600_type_info = {
-+    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
+-    .name           = "ast2600-a3",
-+      .sfdp_read = m25p80_sfdp_w25q512jv },
+-    .parent         = TYPE_ASPEED_SOC,
-     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
+-    .instance_size  = sizeof(AspeedSoCState),
 -    .instance_init  = aspeed_soc_ast2600_init,
 -    .class_init     = aspeed_soc_ast2600_class_init,
 -    .class_size     = sizeof(AspeedSoCClass),
 +static const TypeInfo aspeed_soc_ast2600_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2600_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_size  = sizeof(Aspeed2600SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2600-a3",
 +        .parent         = TYPE_ASPEED2600_SOC,
 +        .instance_init  = aspeed_soc_ast2600_init,
 +        .class_init     = aspeed_soc_ast2600_class_init,
 +    },
  };
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
+-static void aspeed_soc_register_types(void)
-index XXXXXXX..XXXXXXX 100644
+-{
---- a/hw/block/m25p80_sfdp.c
+-    type_register_static(&aspeed_soc_ast2600_type_info);
-+++ b/hw/block/m25p80_sfdp.c
+-};
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q256[] = {
+-
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+-type_init(aspeed_soc_register_types)
- };
++DEFINE_TYPES(aspeed_soc_ast2600_types)
  define_sfdp_read(w25q256);
 +
 +static const uint8_t sfdp_w25q512jv[] = {
 +    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
 +    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
 +    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
 +    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
 +    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
 +    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
 +    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
 +    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
 +    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(w25q512jv);
 --
-.37.3
+.41.0

-[PULL 10/16] m25p80: Add the mx25l25635e SFPD table
+[PULL 08/12] hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
-The SFDP table is 0x80 bytes long. The mandatory table for basic
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 features is available at byte 0x30 and an extra Macronix specific
 table is available at 0x60.
-B opcodes are not supported.
+TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
 In few commits we'll add more fields, but to keep
 review process simple, don't add any yet.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+TYPE_ASPEED_SOC is common to various Aspeed SoCs,
-Message-Id: <20220722063602.128144-4-clg@kaod.org>
+define it in aspeed_soc_common.c.
-Message-Id: <20221013161241.2805140-5-clg@kaod.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/block/m25p80_sfdp.h |  3 +++
+ include/hw/arm/aspeed_soc.h |  7 +++++
- hw/block/m25p80.c      |  2 +-
+ hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
- hw/block/m25p80_sfdp.c | 26 ++++++++++++++++++++++++++
+ hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
-files changed, 30 insertions(+), 1 deletion(-)
+files changed, 53 insertions(+), 44 deletions(-)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/block/m25p80_sfdp.h
++++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
  #define TYPE_ASPEED_SOC "aspeed-soc"
  OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 +struct Aspeed2400SoCState {
 +    AspeedSoCState parent;
 +};
 +
 +#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
 +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 +
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
  };
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc.c
 +++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                         aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
  }
 -static Property aspeed_soc_properties[] = {
 -    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 -                     MemoryRegion *),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
 -static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 -{
 -    DeviceClass *dc = DEVICE_CLASS(oc);
 -
 -    device_class_set_props(dc, aspeed_soc_properties);
 -}
 -
 -static const TypeInfo aspeed_soc_type_info = {
 -    .name           = TYPE_ASPEED_SOC,
 -    .parent         = TYPE_DEVICE,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_size     = sizeof(AspeedSoCClass),
 -    .class_init     = aspeed_soc_class_init,
 -    .abstract       = true,
 -};
  static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
  {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2400_type_info = {
 -    .name           = "ast2400-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2400_class_init,
 -};
 -
  static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
  {
      AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
      sc->get_irq      = aspeed_soc_ast2400_get_irq;
  }
 -static const TypeInfo aspeed_soc_ast2500_type_info = {
 -    .name           = "ast2500-a1",
 -    .parent         = TYPE_ASPEED_SOC,
 -    .instance_init  = aspeed_ast2400_soc_init,
 -    .instance_size  = sizeof(AspeedSoCState),
 -    .class_init     = aspeed_soc_ast2500_class_init,
 -};
 -static void aspeed_soc_register_types(void)
 -{
 -    type_register_static(&aspeed_soc_type_info);
 -    type_register_static(&aspeed_soc_ast2400_type_info);
 -    type_register_static(&aspeed_soc_ast2500_type_info);
 +static const TypeInfo aspeed_soc_ast2400_types[] = {
 +    {
 +        .name           = TYPE_ASPEED2400_SOC,
 +        .parent         = TYPE_ASPEED_SOC,
 +        .instance_init  = aspeed_ast2400_soc_init,
 +        .instance_size  = sizeof(Aspeed2400SoCState),
 +        .abstract       = true,
 +    }, {
 +        .name           = "ast2400-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2400_class_init,
 +    }, {
 +        .name           = "ast2500-a1",
 +        .parent         = TYPE_ASPEED2400_SOC,
 +        .class_init     = aspeed_soc_ast2500_class_init,
 +    },
  };
 -type_init(aspeed_soc_register_types);
 +DEFINE_TYPES(aspeed_soc_ast2400_types)
 diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_soc_common.c
 +++ b/hw/arm/aspeed_soc_common.c
 @@ -XXX,XX +XXX,XX @@
- uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+ #include "qemu/osdep.h"
+ #include "qapi/error.h"
-+uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
++#include "hw/qdev-properties.h"
  #include "hw/misc/unimp.h"
  #include "hw/arm/aspeed_soc.h"
  #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
      memory_region_add_subregion_overlap(s->memory, addr,
                                          sysbus_mmio_get_region(dev, 0), -1000);
  }
 +
++static Property aspeed_soc_properties[] = {
++    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
++                     MemoryRegion *),
++    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
++                     MemoryRegion *),
++    DEFINE_PROP_END_OF_LIST(),
++};
 +
- #endif
++static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
++{
-index XXXXXXX..XXXXXXX 100644
++    DeviceClass *dc = DEVICE_CLASS(oc);
 --- a/hw/block/m25p80.c
 +++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
      { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
      { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
      { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
 -            ER_4K | ER_32K) },
 +            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
      { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
      { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
      { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
 diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/m25p80_sfdp.c
 +++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_n25q256a[] = {
 xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  };
  define_sfdp_read(n25q256a);
 +
++    device_class_set_props(dc, aspeed_soc_properties);
++}
 +
-+/*
++static const TypeInfo aspeed_soc_types[] = {
-+ * Matronix
++    {
-+ */
++        .name           = TYPE_ASPEED_SOC,
 +        .parent         = TYPE_DEVICE,
 +        .instance_size  = sizeof(AspeedSoCState),
 +        .class_size     = sizeof(AspeedSoCClass),
 +        .class_init     = aspeed_soc_class_init,
 +        .abstract       = true,
 +    },
 +};
 +
-+/* mx25l25635e. No 4B opcodes */
++DEFINE_TYPES(aspeed_soc_types)
 +static const uint8_t sfdp_mx25l25635e[] = {
 +    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
 +    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
 +    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
 +    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
 +    0xee, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
 +    0xff, 0xff, 0x00, 0xff, 0x0c, 0x20, 0x0f, 0x52,
 +    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0x00, 0x36, 0x00, 0x27, 0xf7, 0x4f, 0xff, 0xff,
 +    0xd9, 0xc8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 +};
 +define_sfdp_read(mx25l25635e)
 --
-.37.3
+.41.0

-[PULL 04/16] aspeed/smc: Cache AspeedSMCClass
+[PULL 09/12] hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
-Store a reference on the AspeedSMC class under the flash object and
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 use it when accessing the flash contents. Avoiding the class cast
 checkers in these hot paths improves performance by 10% when running
 the aspeed avocado tests.
-Message-Id: <20220923084803.498337-7-clg@kaod.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/ssi/aspeed_smc.h | 2 ++
+ hw/arm/aspeed_soc_common.c | 11 +++++++++++
- hw/ssi/aspeed_smc.c         | 9 ++++-----
+file changed, 11 insertions(+)
 files changed, 6 insertions(+), 5 deletions(-)
-diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
+diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/aspeed_smc.h
+--- a/hw/arm/aspeed_soc_common.c
-+++ b/include/hw/ssi/aspeed_smc.h
++++ b/hw/arm/aspeed_soc_common.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
- #include "qom/object.h"
+                                         sysbus_mmio_get_region(dev, 0), -1000);
+ }
- struct AspeedSMCState;
-+struct AspeedSMCClass;
++static void aspeed_soc_realize(DeviceState *dev, Error **errp)
++{
- #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
++    AspeedSoCState *s = ASPEED_SOC(dev);
- OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
++
-@@ -XXX,XX +XXX,XX @@ struct AspeedSMCFlash {
++    if (!s->memory) {
-     SysBusDevice parent_obj;
++        error_setg(errp, "'memory' link is not set");
++        return;
-     struct AspeedSMCState *controller;
++    }
-+    struct AspeedSMCClass *asc;
++}
-     uint8_t cs;
++
+ static Property aspeed_soc_properties[] = {
-     MemoryRegion mmio;
+     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
+                      MemoryRegion *),
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 --- a/hw/ssi/aspeed_smc.c
 +++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
  static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
  {
-     const AspeedSMCState *s = fl->controller;
+     DeviceClass *dc = DEVICE_CLASS(oc);
--    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
-+    AspeedSMCClass *asc = fl->asc;
++    dc->realize = aspeed_soc_realize;
+     device_class_set_props(dc, aspeed_soc_properties);
      if (asc->addr_width) {
          return asc->addr_width(s);
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
                                                uint32_t addr)
  {
      const AspeedSMCState *s = fl->controller;
 -    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
 +    AspeedSMCClass *asc = fl->asc;
      AspeedSegments seg;
      asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_smc_info = {
  static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
  {
      AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
 -    AspeedSMCClass *asc;
      g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
      if (!s->controller) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
          return;
      }
 -    asc = ASPEED_SMC_GET_CLASS(s->controller);
 +    s->asc = ASPEED_SMC_GET_CLASS(s->controller);
      /*
       * Use the default segment value to size the memory region. This
       * can be changed by FW at runtime.
       */
      memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
 -                          s, name, asc->segments[s->cs].size);
 +                          s, name, s->asc->segments[s->cs].size);
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
  }
 --
-.37.3
+.41.0

-[PULL 06/16] hw/arm/aspeed: increase Bletchley memory size
+[PULL 10/12] hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
-From: Patrick Williams <patrick@stwcx.xyz>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-For the PVT-class hardware we have increased the memory size of
+The v7-M core is specific to the Aspeed 10x0 series,
-this device to 2 GiB.  Adjust the device model accordingly.
+remove it from the common AspeedSoCState.
-Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed.c | 9 ++++++++-
+ include/hw/arm/aspeed_soc.h |  5 ++---
-file changed, 8 insertions(+), 1 deletion(-)
+ hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
  hw/arm/fby35.c              | 13 ++++++++-----
 files changed, 25 insertions(+), 20 deletions(-)
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/hw/arm/aspeed.c
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@
-         aspeed_soc_num_cpus(amc->soc_name);
+ #define ASPEED_JTAG_NUM  2
  struct AspeedSoCState {
 -    /*< private >*/
      DeviceState parent;
 -    /*< public >*/
      ARMCPU cpu[ASPEED_CPUS_NUM];
      A15MPPrivState     a7mpcore;
 -    ARMv7MState        armv7m;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
  struct Aspeed10x0SoCState {
      AspeedSoCState parent;
 +
 +    ARMv7MState armv7m;
  };
-+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+ #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
-+#if HOST_LONG_BITS == 32
+diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
-+#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
+index XXXXXXX..XXXXXXX 100644
-+#else
+--- a/hw/arm/aspeed_ast10x0.c
-+#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
++++ b/hw/arm/aspeed_ast10x0.c
-+#endif
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
  static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
 +    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
  }
  static void aspeed_soc_ast1030_init(Object *obj)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
          g_assert_not_reached();
      }
 -    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
 +    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
      s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
  static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
  {
 +    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
      AspeedSoCState *s = ASPEED_SOC(dev_soc);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 x40000);
      /* AST1030 CPU Core */
 -    armv7m = DEVICE(&s->armv7m);
 +    armv7m = DEVICE(&a->armv7m);
      qdev_prop_set_uint32(armv7m, "num-irq", 256);
      qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
      qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
 -    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +    object_property_set_link(OBJECT(&a->armv7m), "memory",
                               OBJECT(s->memory), &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
      /* Internal SRAM */
      sram_name = g_strdup_printf("aspeed.sram.%d",
 -                                CPU(s->armv7m.cpu)->cpu_index);
 +                                CPU(a->armv7m.cpu)->cpu_index);
      memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
      if (err != NULL) {
          error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
      for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I2C] + i);
          /* The AST1030 I2C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      }
      aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
      for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
 -        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
 +        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                          sc->irqmap[ASPEED_DEV_I3C] + i);
          /* The AST1030 I3C controller has one IRQ per bus. */
          sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
       * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
       */
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
 -                       qdev_get_gpio_in(DEVICE(&s->armv7m),
 +                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                  sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
      /* UART */
 diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fby35.c
 +++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
      Clock *bic_sysclk;
      AspeedSoCState bmc;
 -    AspeedSoCState bic;
 +    Aspeed10x0SoCState bic;
      bool mmio_exec;
  };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
  static void fby35_bic_init(Fby35State *s)
  {
 +    AspeedSoCState *soc;
 +
- static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
+     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
- {
+     clock_set_hz(s->bic_sysclk, 200000000ULL);
-     MachineClass *mc = MACHINE_CLASS(oc);
-@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
+     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
-     amc->num_cs    = 2;
++    soc = ASPEED_SOC(&s->bic);
-     amc->macs_mask = ASPEED_MAC2_ON;
-     amc->i2c_init  = bletchley_bmc_i2c_init;
+     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
--    mc->default_ram_size = 512 * MiB;
+                        UINT64_MAX);
-+    mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
+@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
-     mc->default_cpus = mc->min_cpus = mc->max_cpus =
+     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
-         aspeed_soc_num_cpus(amc->soc_name);
+     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                               &error_abort);
 -    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
 +    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
      qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 -    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
 -    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
 -    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
 +    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
 +    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
 +    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
  }
+ static void fby35_init(MachineState *machine)
 --
-.37.3
+.41.0

-[PULL 05/16] ast2600: Drop NEON from the CPU features
+[PULL 11/12] hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
-Currently, the CPU features exposed to the AST2600 QEMU machines are :
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-  half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
+The v7-A cluster is specific to the Aspeed 2600 series,
-  vfpd32 lpae evtstrm
+remove it from the common AspeedSoCState.
-But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
+The ARM cores belong to the MP cluster, but the array
-are :
+is currently used by TYPE_ASPEED2600_SOC. We'll clean
+that soon, but for now keep it in Aspeed2600SoCState.
-  half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
-  lpae evtstrm
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Drop NEON support in the Aspeed AST2600 SoC.
 Reviewed-by: Joel Stanley <joel@jms.id.au>
 Message-Id: <20220928164719.655586-3-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- hw/arm/aspeed_ast2600.c | 2 ++
+ include/hw/arm/aspeed_soc.h |  4 ++-
-file changed, 2 insertions(+)
+ hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
+ hw/arm/fby35.c              | 14 ++++++-----
 files changed, 37 insertions(+), 30 deletions(-)
 diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
      DeviceState parent;
      ARMCPU cpu[ASPEED_CPUS_NUM];
 -    A15MPPrivState     a7mpcore;
      MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
  struct Aspeed2600SoCState {
      AspeedSoCState parent;
 +
 +    A15MPPrivState a7mpcore;
 +    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
  };
  #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed_ast2600.c
 +++ b/hw/arm/aspeed_ast2600.c
-@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
-         object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+ static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
  {
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 -    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
 +    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
  }
  static void aspeed_soc_ast2600_init(Object *obj)
  {
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
 +        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
      object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                                "hw-prot-key");
 -    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
 +    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                              TYPE_A15MPCORE_PRIV);
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
  static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
          if (sc->num_cpus > 1) {
 -            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 +            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                      ASPEED_A7MPCORE_ADDR, &error_abort);
          }
 -        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
 +        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                  aspeed_calc_affinity(i), &error_abort);
 -        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
 +        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                  &error_abort);
-+        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+-        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
-+                                &error_abort);
++        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
-         object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+                                 &error_abort);
 -        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
 +        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                  &error_abort);
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
+-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
++        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
+             return;
+         }
+     }
+     /* A7MPCORE */
+-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
++    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
+                             &error_abort);
+-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
++    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
+                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
+                             &error_abort);
+-    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
+-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
++    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+     for (i = 0; i < sc->num_cpus; i++) {
+-        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
+-        DeviceState  *d   = DEVICE(&s->cpu[i]);
++        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
++        DeviceState  *d   = DEVICE(&a->cpu[i]);
+         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
+         sysbus_connect_irq(sbd, i, irq);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+     }
+     /* SRAM */
+-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
++    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
+     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
+     if (err) {
+         error_propagate(errp, err);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+     }
+     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
+     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
+-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                sc->irqmap[ASPEED_DEV_I2C] + i);
+         /* The AST2600 I2C controller has one IRQ per bus. */
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+      * offset 0.
+      */
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
+     /* HACE */
+@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
+     }
+     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
+     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
+-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
++        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
+                                sc->irqmap[ASPEED_DEV_I3C] + i);
+         /* The AST2600 I3C controller has one IRQ per bus. */
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
+diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fby35.c
++++ b/hw/arm/fby35.c
+@@ -XXX,XX +XXX,XX @@ struct Fby35State {
+     MemoryRegion bic_memory;
+     Clock *bic_sysclk;
+-    AspeedSoCState bmc;
++    Aspeed2600SoCState bmc;
+     Aspeed10x0SoCState bic;
+     bool mmio_exec;
+@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
+ static void fby35_bmc_init(Fby35State *s)
+ {
++    AspeedSoCState *soc;
++
+     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
++    soc = ASPEED_SOC(&s->bmc);
+     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
+                        UINT64_MAX);
+@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
+                             &error_abort);
+     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
+                             &error_abort);
+-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
++    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
+     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
+-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
++    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
+     /* Install first FMC flash content as a boot rom. */
+     if (!s->mmio_exec) {
+         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
+         if (mtd0) {
+-            AspeedSoCState *bmc = &s->bmc;
+-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
++            uint64_t rom_size = memory_region_size(&soc->spi_boot);
+             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
+                                    rom_size, &error_abort);
+-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
++            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
+                                                 &s->bmc_boot_rom, 1);
+             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
 --
-.37.3
+.41.0

-[PULL 03/16] ssi: cache SSIPeripheralClass to avoid GET_CLASS()
+[PULL 12/12] hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Investigating why some BMC models are so slow compared to a plain ARM
+The ARM array and VIC peripheral are only used by the
-virt machines I did some profiling of:
+series, remove them from the common AspeedSoCState.
-  ./qemu-system-arm -M romulus-bmc -nic user \
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
     -drive
     file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
     -nographic -serial mon:stdio
 And saw that object_class_dynamic_cast_assert was dominating the
 profile times. We have a number of cases in this model of the SSI bus.
 As the class is static once the object is created we just cache it and
 use it instead of the dynamic case macros.
 Profiling against:
   ./tests/venv/bin/avocado run \
     tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0
 Before: 35.565 s ±  0.087 s
 After: 15.713 s ±  0.287 s
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Cc: Cédric Le Goater <clg@kaod.org>
 Tested-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org>
-Message-Id: <20220923084803.498337-6-clg@kaod.org>
 Signed-off-by: Cédric Le Goater <clg@kaod.org>
 ---
- include/hw/ssi/ssi.h |  3 +++
+ include/hw/arm/aspeed_soc.h               |  5 +++--
- hw/ssi/ssi.c         | 18 ++++++++----------
+ hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
-files changed, 11 insertions(+), 10 deletions(-)
+ hw/arm/meson.build                        |  2 +-
 files changed, 19 insertions(+), 15 deletions(-)
  rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)
-diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ssi/ssi.h
+--- a/include/hw/arm/aspeed_soc.h
-+++ b/include/hw/ssi/ssi.h
++++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@ struct SSIPeripheralClass {
+@@ -XXX,XX +XXX,XX @@
- struct SSIPeripheral {
+ struct AspeedSoCState {
-     DeviceState parent_obj;
+     DeviceState parent;
-+    /* cache the class */
+-    ARMCPU cpu[ASPEED_CPUS_NUM];
-+    SSIPeripheralClass *spc;
+     MemoryRegion *memory;
      MemoryRegion *dram_mr;
      MemoryRegion dram_container;
      MemoryRegion sram;
      MemoryRegion spi_boot_container;
      MemoryRegion spi_boot;
 -    AspeedVICState vic;
      AspeedRtcState rtc;
      AspeedTimerCtrlState timerctrl;
      AspeedI2CState i2c;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  struct Aspeed2400SoCState {
      AspeedSoCState parent;
 +
-     /* Chip select state */
++    ARMCPU cpu[ASPEED_CPUS_NUM];
-     bool cs;
++    AspeedVICState vic;
  };
-diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
  #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_ast2400.c
 similarity index 95%
 rename from hw/arm/aspeed_soc.c
 rename to hw/arm/aspeed_ast2400.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/ssi.c
+--- a/hw/arm/aspeed_soc.c
-+++ b/hw/ssi/ssi.c
++++ b/hw/arm/aspeed_ast2400.c
-@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
+@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = {
-     bool cs = !!level;
-     assert(n == 0);
+ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
-     if (s->cs != cs) {
+ {
--        SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
++    Aspeed2400SoCState *a = ASPEED2400_SOC(s);
--        if (ssc->set_cs) {
+     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
--            ssc->set_cs(s, cs);
-+        if (s->spc->set_cs) {
+-    return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
-+            s->spc->set_cs(s, cs);
++    return qdev_get_gpio_in(DEVICE(&a->vic), sc->irqmap[dev]);
  }
  static void aspeed_ast2400_soc_init(Object *obj)
  {
 +    Aspeed2400SoCState *a = ASPEED2400_SOC(obj);
      AspeedSoCState *s = ASPEED_SOC(obj);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
      }
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
 +        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
      }
      snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
      object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                                "hw-prot-key");
 -    object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
 +    object_initialize_child(obj, "vic", &a->vic, TYPE_ASPEED_VIC);
      object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
  static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
  {
      int i;
 +    Aspeed2400SoCState *a = ASPEED2400_SOC(dev);
      AspeedSoCState *s = ASPEED_SOC(dev);
      AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
      /* CPU */
      for (i = 0; i < sc->num_cpus; i++) {
 -        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
 +        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                   OBJECT(s->memory), &error_abort);
 -        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
              return;
          }
      }
-     s->cs = cs;
-@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
+     /* SRAM */
+-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
- static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
++    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
- {
+     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
--    SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
+     if (err) {
-+    SSIPeripheralClass *ssc = dev->spc;
+         error_propagate(errp, err);
+@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
-     if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
+     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
--            (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
--            ssc->cs_polarity == SSI_CS_NONE) {
+     /* VIC */
-+        (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
+-    if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
-+        ssc->cs_polarity == SSI_CS_NONE) {
++    if (!sysbus_realize(SYS_BUS_DEVICE(&a->vic), errp)) {
-         return ssc->transfer(dev, val);
+         return;
      }
-     return 0;
+-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
-@@ -XXX,XX +XXX,XX @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
+-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
-             ssc->cs_polarity != SSI_CS_NONE) {
+-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
-         qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
+-    sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
-     }
+-                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
-+    s->spc = ssc;
++    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 0,
-     ssc->realize(s, errp);
++                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_IRQ));
- }
++    sysbus_connect_irq(SYS_BUS_DEVICE(&a->vic), 1,
-@@ -XXX,XX +XXX,XX @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
++                       qdev_get_gpio_in(DEVICE(&a->cpu), ARM_CPU_FIQ));
- {
-     BusState *b = BUS(bus);
+     /* RTC */
-     BusChild *kid;
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
--    SSIPeripheralClass *ssc;
+diff --git a/hw/arm/meson.build b/hw/arm/meson.build
-     uint32_t r = 0;
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/meson.build
-     QTAILQ_FOREACH(kid, &b->children, sibling) {
++++ b/hw/arm/meson.build
--        SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
+@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'
--        ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
+ arm_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
--        r |= ssc->transfer_raw(peripheral, val);
+ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-+        SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
+ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
-+        r |= p->spc->transfer_raw(p, val);
+-  'aspeed_soc.c',
-     }
+   'aspeed.c',
+   'aspeed_soc_common.c',
-     return r;
++  'aspeed_ast2400.c',
    'aspeed_ast2600.c',
    'aspeed_ast10x0.c',
    'aspeed_eeprom.c',
 --
-.37.3
+.41.0

-[PULL 09/16] m25p80: Add erase size for mx25l25635e
+Deleted patch
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Message-Id: <20221013161241.2805140-4-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/block/m25p80.c | 3 ++-
-file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
-     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
-     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
-     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
--    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512, 0) },
-+    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
-+            ER_4K | ER_32K) },
-     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
-     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
-     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
---
-.37.3

-[PULL 11/16] m25p80: Add the mx25l25635f SFPD table
+Deleted patch
-The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
-mx25l25635f has more capabilities reported in the SFDP table. Support
-for 4B opcodes is of interest because it is exploited by the Linux
-kernel.
-The SFDP table size is 0x200 bytes long. The mandatory table for basic
-features is available at byte 0x30 and an extra Macronix specific
-table is available at 0x60.
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Message-Id: <20220722063602.128144-5-clg@kaod.org>
-Message-Id: <20221013161241.2805140-6-clg@kaod.org>
-Signed-off-by: Cédric Le Goater <clg@kaod.org>
----
- hw/block/m25p80_sfdp.h |  1 +
- hw/block/m25p80.c      |  2 ++
- hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
-files changed, 71 insertions(+)
-diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.h
-+++ b/hw/block/m25p80_sfdp.h
-@@ -XXX,XX +XXX,XX @@
- uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
- uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
-+uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
- #endif
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
-+++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
-     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
-     { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
-             ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
-+    { INFO6("mx25l25635f", 0xc22019,     0xc22019,  64 << 10, 512,
-+            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
-     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
-     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
-     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
-diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80_sfdp.c
-+++ b/hw/block/m25p80_sfdp.c
-@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635e[] = {
-xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- };
- define_sfdp_read(mx25l25635e)
-+
-+static const uint8_t sfdp_mx25l25635f[] = {
-+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
-+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
-+    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
-+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
-+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
-+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
-+    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
-+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xc2, 0xf5, 0x08, 0x0a,
-+    0x08, 0x04, 0x03, 0x06, 0x00, 0x00, 0x07, 0x29,
-+    0x17, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-+};
-+define_sfdp_read(mx25l25635f);
---
-.37.3

The following changes since commit 0529245488865038344d64fff7ee05864d3d17f6:

Merge tag 'pull-target-arm-20221020' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-10-20 14:36:12 -0400)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20221025

for you to fetch changes up to 703229132bb05327044368fc6d19f6acf7dde848:

arm/aspeed: Replace mx25l25635e chip model (2022-10-24 11:20:16 +0200)

----------------------------------------------------------------
aspeed queue :

* Performance improvement with Object class caching
* Serial Flash Discovery Parameters support for m25p80 device
* Various small adjustments on intructions and models

----------------------------------------------------------------
Alex Bennée (1):
      ssi: cache SSIPeripheralClass to avoid GET_CLASS()

Cédric Le Goater (12):
      tests/avocado/machine_aspeed.py: Fix typos on buildroot
      aspeed/smc: Cache AspeedSMCClass
      ast2600: Drop NEON from the CPU features
      m25p80: Add basic support for the SFDP command
      m25p80: Add the n25q256a SFDP table
      m25p80: Add erase size for mx25l25635e
      m25p80: Add the mx25l25635e SFPD table
      m25p80: Add the mx25l25635f SFPD table
      m25p80: Add the mx66l1g45g SFDP table
      m25p80: Add the w25q256 SFPD table
      m25p80: Add the w25q512jv SFPD table
      arm/aspeed: Replace mx25l25635e chip model

Patrick Williams (2):
      hw/arm/aspeed: increase Bletchley memory size
      m25p80: Add the w25q01jvq SFPD table

Peter Delevoryas (1):
      hw/i2c/aspeed: Fix old reg slave receive

From: Peter Delevoryas <peter@pjd.dev>

I think when Klaus ported his slave mode changes from the original patch
series to the rewritten I2C module, he changed the behavior of the first
byte that is received by the slave device.

What's supposed to happen is that the AspeedI2CBus's slave device's
i2c_event callback should run, and if the event is "send_async", then it
should populate the byte buffer with the 8-bit I2C address that is being
sent to. Since we only support "send_async", the lowest bit should
always be 0 (indicating that the master is requesting to send data).

This is the code Klaus had previously, for reference. [1]

switch (event) {
    case I2C_START_SEND:
        bus->buf = bus->dev_addr << 1;

bus->buf &= I2CD_BYTE_BUF_RX_MASK;
        bus->buf <<= I2CD_BYTE_BUF_RX_SHIFT;

bus->intr_status |= (I2CD_INTR_SLAVE_ADDR_RX_MATCH | I2CD_INTR_RX_DONE);
        aspeed_i2c_set_state(bus, I2CD_STXD);

break;

[1]: https://lore.kernel.org/qemu-devel/20220331165737.1073520-4-its@irrelevant.dk/

Fixes: a8d48f59cd021b25 ("hw/i2c/aspeed: add slave device in old register mode")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Message-Id: <20220820225712.713209-2-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/i2c/aspeed_i2c.h | 1 +
 hw/i2c/aspeed_i2c.c         | 8 +++++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -XXX,XX +XXX,XX @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
     SHARED_FIELD(M_TX_CMD, 1, 1)
     SHARED_FIELD(M_START_CMD, 0, 1)
 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
+    SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
     SHARED_FIELD(RX_COUNT, 24, 5)
     SHARED_FIELD(RX_SIZE, 16, 5)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
     AspeedI2CBus *bus = ASPEED_I2C_BUS(qbus->parent);
     uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
     uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
-    uint32_t value;
+    uint32_t reg_dev_addr = aspeed_i2c_bus_dev_addr_offset(bus);
+    uint32_t dev_addr = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_dev_addr,
+                                                SLAVE_DEV_ADDR1);
 
     if (aspeed_i2c_is_new_mode(bus->controller)) {
         return aspeed_i2c_bus_new_slave_event(bus, event);
@@ -XXX,XX +XXX,XX @@ static int aspeed_i2c_bus_slave_event(I2CSlave *slave, enum i2c_event event)
 
     switch (event) {
     case I2C_START_SEND_ASYNC:
-        value = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_byte_buf, TX_BUF);
-        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, value << 1);
+        /* Bit[0] == 0 indicates "send". */
+        SHARED_ARRAY_FIELD_DP32(bus->regs, reg_byte_buf, RX_BUF, dev_addr << 1);
 
         ARRAY_FIELD_DP32(bus->regs, I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 1);
         SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, RX_DONE, 1);
-- 
2.37.3

Replace 'buidroot' and 'builroot' by 'buildroot'.

Fixes: f7bc7da0724f ("test/avocado/machine_aspeed.py: Add tests using buildroot images")
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220923084803.498337-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 tests/avocado/machine_aspeed.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
 
         self.do_test_arm_aspeed(image_path)
 
-    def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
+    def do_test_arm_aspeed_buildroot_start(self, image, cpu_id):
         self.require_netdev('user')
 
         self.vm.set_console()
@@ -XXX,XX +XXX,XX @@ def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
         exec_command(self, 'root')
         time.sleep(0.1)
 
-    def do_test_arm_aspeed_buidroot_poweroff(self):
+    def do_test_arm_aspeed_buildroot_poweroff(self):
         exec_command_and_wait_for_pattern(self, 'poweroff',
                                           'reboot: System halted');
 
-    def test_arm_ast2500_evb_builroot(self):
+    def test_arm_ast2500_evb_buildroot(self):
         """
         :avocado: tags=arch:arm
         :avocado: tags=machine:ast2500-evb
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
 
         self.vm.add_args('-device',
                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
-        self.do_test_arm_aspeed_buidroot_start(image_path, '0x0')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0x0')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2500_evb_builroot(self):
         exec_command_and_wait_for_pattern(self,
                              'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
 
-        self.do_test_arm_aspeed_buidroot_poweroff()
+        self.do_test_arm_aspeed_buildroot_poweroff()
 
-    def test_arm_ast2600_evb_builroot(self):
+    def test_arm_ast2600_evb_buildroot(self):
         """
         :avocado: tags=arch:arm
         :avocado: tags=machine:ast2600-evb
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
                          'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
         self.vm.add_args('-device',
                          'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
-        self.do_test_arm_aspeed_buidroot_start(image_path, '0xf00')
+        self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
 
         exec_command_and_wait_for_pattern(self,
              'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
@@ -XXX,XX +XXX,XX @@ def test_arm_ast2600_evb_builroot(self):
         year = time.strftime("%Y")
         exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
 
-        self.do_test_arm_aspeed_buidroot_poweroff()
+        self.do_test_arm_aspeed_buildroot_poweroff()
 
 
 class AST2x00MachineSDK(QemuSystemTest):
-- 
2.37.3

From: Alex Bennée <alex.bennee@linaro.org>

Investigating why some BMC models are so slow compared to a plain ARM
virt machines I did some profiling of:

./qemu-system-arm -M romulus-bmc -nic user \
    -drive
    file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \
    -nographic -serial mon:stdio

And saw that object_class_dynamic_cast_assert was dominating the
profile times. We have a number of cases in this model of the SSI bus.
As the class is static once the object is created we just cache it and
use it instead of the dynamic case macros.

Profiling against:

./tests/venv/bin/avocado run \
    tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0

Before: 35.565 s ±  0.087 s
After: 15.713 s ±  0.287 s

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org>
Message-Id: <20220923084803.498337-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/ssi.h |  3 +++
 hw/ssi/ssi.c         | 18 ++++++++----------
 2 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -XXX,XX +XXX,XX @@ struct SSIPeripheralClass {
 struct SSIPeripheral {
     DeviceState parent_obj;
 
+    /* cache the class */
+    SSIPeripheralClass *spc;
+
     /* Chip select state */
     bool cs;
 };
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
     bool cs = !!level;
     assert(n == 0);
     if (s->cs != cs) {
-        SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
-        if (ssc->set_cs) {
-            ssc->set_cs(s, cs);
+        if (s->spc->set_cs) {
+            s->spc->set_cs(s, cs);
         }
     }
     s->cs = cs;
@@ -XXX,XX +XXX,XX @@ static void ssi_cs_default(void *opaque, int n, int level)
 
 static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
 {
-    SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
+    SSIPeripheralClass *ssc = dev->spc;
 
     if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
-            (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
-            ssc->cs_polarity == SSI_CS_NONE) {
+        (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
+        ssc->cs_polarity == SSI_CS_NONE) {
         return ssc->transfer(dev, val);
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
             ssc->cs_polarity != SSI_CS_NONE) {
         qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
     }
+    s->spc = ssc;
 
     ssc->realize(s, errp);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
 {
     BusState *b = BUS(bus);
     BusChild *kid;
-    SSIPeripheralClass *ssc;
     uint32_t r = 0;
 
     QTAILQ_FOREACH(kid, &b->children, sibling) {
-        SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
-        ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
-        r |= ssc->transfer_raw(peripheral, val);
+        SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
+        r |= p->spc->transfer_raw(p, val);
     }
 
     return r;
-- 
2.37.3

Store a reference on the AspeedSMC class under the flash object and
use it when accessing the flash contents. Avoiding the class cast
checkers in these hot paths improves performance by 10% when running
the aspeed avocado tests.

Message-Id: <20220923084803.498337-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/ssi/aspeed_smc.h | 2 ++
 hw/ssi/aspeed_smc.c         | 9 ++++-----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 struct AspeedSMCState;
+struct AspeedSMCClass;
 
 #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
 OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
@@ -XXX,XX +XXX,XX @@ struct AspeedSMCFlash {
     SysBusDevice parent_obj;
 
     struct AspeedSMCState *controller;
+    struct AspeedSMCClass *asc;
     uint8_t cs;
 
     MemoryRegion mmio;
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
 static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
 {
     const AspeedSMCState *s = fl->controller;
-    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+    AspeedSMCClass *asc = fl->asc;
 
     if (asc->addr_width) {
         return asc->addr_width(s);
@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
                                               uint32_t addr)
 {
     const AspeedSMCState *s = fl->controller;
-    AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
+    AspeedSMCClass *asc = fl->asc;
     AspeedSegments seg;
 
     asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_smc_info = {
 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
 {
     AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
-    AspeedSMCClass *asc;
     g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
 
     if (!s->controller) {
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
         return;
     }
 
-    asc = ASPEED_SMC_GET_CLASS(s->controller);
+    s->asc = ASPEED_SMC_GET_CLASS(s->controller);
 
     /*
      * Use the default segment value to size the memory region. This
      * can be changed by FW at runtime.
      */
     memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
-                          s, name, asc->segments[s->cs].size);
+                          s, name, s->asc->segments[s->cs].size);
     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
 }
 
-- 
2.37.3

Currently, the CPU features exposed to the AST2600 QEMU machines are :

half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
  vfpd32 lpae evtstrm

But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
are :

half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
  lpae evtstrm

Drop NEON support in the Aspeed AST2600 SoC.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20220928164719.655586-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast2600.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 
         object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
+        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+                                &error_abort);
         object_property_set_link(OBJECT(&s->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-- 
2.37.3

From: Patrick Williams <patrick@stwcx.xyz>

For the PVT-class hardware we have increased the memory size of
this device to 2 GiB.  Adjust the device model accordingly.

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20221007110529.3657749-1-patrick@stwcx.xyz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
         aspeed_soc_num_cpus(amc->soc_name);
 };
 
+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+#if HOST_LONG_BITS == 32
+#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB)
+#else
+#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB)
+#endif
+
 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
     amc->num_cs    = 2;
     amc->macs_mask = ASPEED_MAC2_ON;
     amc->i2c_init  = bletchley_bmc_i2c_init;
-    mc->default_ram_size = 512 * MiB;
+    mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
     mc->default_cpus = mc->min_cpus = mc->max_cpus =
         aspeed_soc_num_cpus(amc->soc_name);
 }
-- 
2.37.3

JEDEC STANDARD JESD216 for Serial Flash Discovery Parameters (SFDP)
provides a mean to describe the features of a serial flash device
using a set of internal parameter tables.

This is the initial framework for the RDSFDP command giving access to
a private SFDP area under the flash. This area now needs to be
populated with the flash device characteristics, using a new
'sfdp_read' handler under FlashPartInfo.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-2-clg@kaod.org>
Message-Id: <20221013161241.2805140-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h | 18 ++++++++++++++++++
 hw/block/m25p80.c      | 27 +++++++++++++++++++++++++++
 MAINTAINERS            |  2 +-
 hw/block/trace-events  |  1 +
 4 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 hw/block/m25p80_sfdp.h

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * M25P80 SFDP
+ *
+ * Copyright (c) 2020, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef HW_M25P80_SFDP_H
+#define HW_M25P80_SFDP_H
+
+/*
+ * SFDP area has a 3 bytes address space.
+ */
+#define M25P80_SFDP_MAX_SIZE  (1 << 24)
+
+#endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "trace.h"
 #include "qom/object.h"
+#include "m25p80_sfdp.h"
 
 /* 16 MiB max in 3 byte address mode */
 #define MAX_3BYTES_SIZE 0x1000000
@@ -XXX,XX +XXX,XX @@ typedef struct FlashPartInfo {
      * This field inform how many die is in the chip.
      */
     uint8_t die_cnt;
+    uint8_t (*sfdp_read)(uint32_t sfdp_addr);
 } FlashPartInfo;
 
 /* adapted from linux */
@@ -XXX,XX +XXX,XX @@ typedef enum {
     BULK_ERASE = 0xc7,
     READ_FSR = 0x70,
     RDCR = 0x15,
+    RDSFDP = 0x5a,
 
     READ = 0x03,
     READ4 = 0x13,
@@ -XXX,XX +XXX,XX @@ typedef enum {
     STATE_COLLECTING_DATA,
     STATE_COLLECTING_VAR_LEN_DATA,
     STATE_READING_DATA,
+    STATE_READING_SFDP,
 } CMDState;
 
 typedef enum {
@@ -XXX,XX +XXX,XX @@ static inline int get_addr_length(Flash *s)
     }
 
    switch (s->cmd_in_progress) {
+   case RDSFDP:
+       return 3;
    case PP4:
    case PP4_4:
    case QPP_4:
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
                           " by device\n");
         }
         break;
+
+    case RDSFDP:
+        s->state = STATE_READING_SFDP;
+        break;
+
     default:
         break;
     }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
         }
         break;
+    case RDSFDP:
+        if (s->pi->sfdp_read) {
+            s->needed_bytes = get_addr_length(s) + 1; /* SFDP addr + dummy */
+            s->pos = 0;
+            s->len = 0;
+            s->state = STATE_COLLECTING_DATA;
+            break;
+        }
+        /* Fallthrough */
+
     default:
         s->pos = 0;
         s->len = 1;
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
             }
         }
         break;
+    case STATE_READING_SFDP:
+        assert(s->pi->sfdp_read);
+        r = s->pi->sfdp_read(s->cur_addr);
+        trace_m25p80_read_sfdp(s, s->cur_addr, (uint8_t)r);
+        s->cur_addr = (s->cur_addr + 1) & (M25P80_SFDP_MAX_SIZE - 1);
+        break;
 
     default:
     case STATE_IDLE:
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ SSI
 M: Alistair Francis <alistair@alistair23.me>
 S: Maintained
 F: hw/ssi/*
-F: hw/block/m25p80.c
+F: hw/block/m25p80*
 F: include/hw/ssi/ssi.h
 X: hw/ssi/xilinx_*
 F: tests/qtest/m25p80-test.c
diff --git a/hw/block/trace-events b/hw/block/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_a
 m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
 m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
 m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
+m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8
 m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
 m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
-- 
2.37.3

The same values were collected on 4 differents OpenPower systems,
palmettos, romulus and tacoma.

The SFDP table size is defined as being 0x100 bytes but it could be
bigger. Only the mandatory table for basic features is available at
byte 0x30.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-3-clg@kaod.org>
Message-Id: <20221013161241.2805140-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  8 +++---
 hw/block/m25p80_sfdp.c | 58 ++++++++++++++++++++++++++++++++++++++++++
 hw/block/meson.build   |  1 +
 4 files changed, 66 insertions(+), 3 deletions(-)
 create mode 100644 hw/block/m25p80_sfdp.c

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
  */
 #define M25P80_SFDP_MAX_SIZE  (1 << 24)
 
+uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("n25q128a11",  0x20bb18,      0,  64 << 10, 256, ER_4K) },
     { INFO("n25q128a13",  0x20ba18,      0,  64 << 10, 256, ER_4K) },
     { INFO("n25q256a11",  0x20bb19,      0,  64 << 10, 512, ER_4K) },
-    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K) },
+    { INFO("n25q256a13",  0x20ba19,      0,  64 << 10, 512, ER_4K),
+      .sfdp_read = m25p80_sfdp_n25q256a },
     { INFO("n25q512a11",  0x20bb20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q512a13",  0x20ba20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q128",     0x20ba18,      0,  64 << 10, 256, 0) },
     { INFO("n25q256a",    0x20ba19,      0,  64 << 10, 512,
-           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB) },
-    { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
+           ER_4K | HAS_SR_BP3_BIT6 | HAS_SR_TB),
+      .sfdp_read = m25p80_sfdp_n25q256a },
+   { INFO("n25q512a",    0x20ba20,      0,  64 << 10, 1024, ER_4K) },
     { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
     { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
     { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024,
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * M25P80 Serial Flash Discoverable Parameter (SFDP)
+ *
+ * Copyright (c) 2020, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "m25p80_sfdp.h"
+
+#define define_sfdp_read(model)                                       \
+    uint8_t m25p80_sfdp_##model(uint32_t addr)                        \
+    {                                                                 \
+        assert(is_power_of_2(sizeof(sfdp_##model)));                  \
+        return sfdp_##model[addr & (sizeof(sfdp_##model) - 1)];       \
+    }
+
+/*
+ * Micron
+ */
+static const uint8_t sfdp_n25q256a[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x29, 0xeb, 0x27, 0x6b, 0x08, 0x3b, 0x27, 0xbb,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x27, 0xbb,
+    0xff, 0xff, 0x29, 0xeb, 0x0c, 0x20, 0x10, 0xd8,
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(n25q256a);
diff --git a/hw/block/meson.build b/hw/block/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/meson.build
+++ b/hw/block/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ONENAND', if_true: files('onenand.c'))
 softmmu_ss.add(when: 'CONFIG_PFLASH_CFI01', if_true: files('pflash_cfi01.c'))
 softmmu_ss.add(when: 'CONFIG_PFLASH_CFI02', if_true: files('pflash_cfi02.c'))
 softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80.c'))
+softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files('m25p80_sfdp.c'))
 softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c'))
 softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c'))
 softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c'))
-- 
2.37.3

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20221013161241.2805140-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx25l6405d",  0xc22017,      0,  64 << 10, 128, 0) },
     { INFO("mx25l12805d", 0xc22018,      0,  64 << 10, 256, 0) },
     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
-    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512, 0) },
+    { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
+            ER_4K | ER_32K) },
     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
-- 
2.37.3

The SFDP table is 0x80 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.

4B opcodes are not supported.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-4-clg@kaod.org>
Message-Id: <20221013161241.2805140-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  3 +++
 hw/block/m25p80.c      |  2 +-
 hw/block/m25p80_sfdp.c | 26 ++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

The mx25l25635e and mx25l25635f chips have the same JEDEC id but the
mx25l25635f has more capabilities reported in the SFDP table. Support
for 4B opcodes is of interest because it is exploited by the Linux
kernel.

The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 and an extra Macronix specific
table is available at 0x60.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-5-clg@kaod.org>
Message-Id: <20221013161241.2805140-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  1 +
 hw/block/m25p80.c      |  2 ++
 hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@
 uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
 
 uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
+uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx25l12855e", 0xc22618,      0,  64 << 10, 256, 0) },
     { INFO6("mx25l25635e", 0xc22019,     0xc22019,  64 << 10, 512,
             ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635e },
+    { INFO6("mx25l25635f", 0xc22019,     0xc22019,  64 << 10, 512,
+            ER_4K | ER_32K), .sfdp_read = m25p80_sfdp_mx25l25635f },
     { INFO("mx25l25655e", 0xc22619,      0,  64 << 10, 512, 0) },
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635e[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx25l25635e)
+
+static const uint8_t sfdp_mx25l25635f[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x01, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x30, 0x00, 0x00, 0xff,
+    0xc2, 0x00, 0x01, 0x04, 0x60, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xc2, 0xf5, 0x08, 0x0a,
+    0x08, 0x04, 0x03, 0x06, 0x00, 0x00, 0x07, 0x29,
+    0x17, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(mx25l25635f);
-- 
2.37.3

The SFDP table size is 0x200 bytes long. The mandatory table for basic
features is available at byte 0x30 plus some more Macronix specific
tables.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-6-clg@kaod.org>
Message-Id: <20221013161241.2805140-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 +-
 hw/block/m25p80.c      |  3 +-
 hw/block/m25p80_sfdp.c | 68 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 71 insertions(+), 2 deletions(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_n25q256a(uint32_t addr);
 
 uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
 uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
-
+uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("mx66l51235f", 0xc2201a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u51235f", 0xc2253a,      0,  64 << 10, 1024, ER_4K | ER_32K) },
     { INFO("mx66u1g45g",  0xc2253b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
-    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K) },
+    { INFO("mx66l1g45g",  0xc2201b,      0,  64 << 10, 2048, ER_4K | ER_32K),
+      .sfdp_read = m25p80_sfdp_mx66l1g45g },
 
     /* Micron */
     { INFO("n25q032a11",  0x20bb16,      0,  64 << 10,  64, ER_4K) },
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx25l25635f[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx25l25635f);
+
+static const uint8_t sfdp_mx66l1g45g[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x30, 0x00, 0x00, 0xff,
+    0xc2, 0x00, 0x01, 0x04, 0x10, 0x01, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xc0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x04, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff,
+    0xff, 0xff, 0x44, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0xff, 0xd6, 0x49, 0xc5, 0x00,
+    0x85, 0xdf, 0x04, 0xe3, 0x44, 0x03, 0x67, 0x38,
+    0x30, 0xb0, 0x30, 0xb0, 0xf7, 0xbd, 0xd5, 0x5c,
+    0x4a, 0x9e, 0x29, 0xff, 0xf0, 0x50, 0xf9, 0x85,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x7f, 0xef, 0xff, 0xff, 0x21, 0x5c, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0x00, 0x36, 0x00, 0x27, 0x9d, 0xf9, 0xc0, 0x64,
+    0x85, 0xcb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xc2, 0xf5, 0x08, 0x00, 0x0c, 0x04, 0x08, 0x08,
+    0x01, 0x00, 0x19, 0x0f, 0x01, 0x01, 0x06, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(mx66l1g45g);
-- 
2.37.3

The SFDP table size is 0x100 bytes long. Only the mandatory table for
basic features is available at byte 0x80.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-7-clg@kaod.org>
Message-Id: <20221013161241.2805140-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 40 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635e(uint32_t addr);
 uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
+uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("w25q64",      0xef4017,      0,  64 << 10, 128, ER_4K) },
     { INFO("w25q80",      0xef5014,      0,  64 << 10,  16, ER_4K) },
     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
-    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K) },
+    { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q256 },
     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
 };
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_mx66l1g45g[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(mx66l1g45g);
+
+/*
+ * Windbond
+ */
+
+static const uint8_t sfdp_w25q256[] = {
+    0x53, 0x46, 0x44, 0x50, 0x00, 0x01, 0x00, 0xff,
+    0x00, 0x00, 0x01, 0x09, 0x80, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xf3, 0xff, 0xff, 0xff, 0xff, 0x0f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x21, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q256);
-- 
2.37.3

The SFDP table size is 0x100 bytes long. The mandatory table for basic
features is available at byte 0x80 and two extra Winbond specifics
table are available at 0xC0 and 0xF0.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-8-clg@kaod.org>
Message-Id: <20221013161241.2805140-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  1 +
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx25l25635f(uint32_t addr);
 uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 
 uint8_t m25p80_sfdp_w25q256(uint32_t addr);
+uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
     { INFO("w25q80bl",    0xef4014,      0,  64 << 10,  16, ER_4K) },
     { INFO("w25q256",     0xef4019,      0,  64 << 10, 512, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q256 },
-    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K) },
+    { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q512jv },
     { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
 };
 
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q256[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(w25q256);
+
+static const uint8_t sfdp_w25q512jv[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x1f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
+    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
+    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q512jv);
-- 
2.37.3

From: Patrick Williams <patrick@stwcx.xyz>

Generated from hardware using the following command and then padding
with 0xff to fill out a power-of-2:
    hexdump -v -e '8/1 "0x%02x, " "\n"' sfdp`

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
[ clg: removed extern ]
Message-Id: <20221006224424.3556372-1-patrick@stwcx.xyz>
Message-Id: <20221013161241.2805140-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/block/m25p80_sfdp.h |  2 ++
 hw/block/m25p80.c      |  3 ++-
 hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.h
+++ b/hw/block/m25p80_sfdp.h
@@ -XXX,XX +XXX,XX @@ uint8_t m25p80_sfdp_mx66l1g45g(uint32_t addr);
 uint8_t m25p80_sfdp_w25q256(uint32_t addr);
 uint8_t m25p80_sfdp_w25q512jv(uint32_t addr);
 
+uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr);
+
 #endif
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {
       .sfdp_read = m25p80_sfdp_w25q256 },
     { INFO("w25q512jv",   0xef4020,      0,  64 << 10, 1024, ER_4K),
       .sfdp_read = m25p80_sfdp_w25q512jv },
-    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K) },
+    { INFO("w25q01jvq",   0xef4021,      0,  64 << 10, 2048, ER_4K),
+      .sfdp_read = m25p80_sfdp_w25q01jvq },
 };
 
 typedef enum {
diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80_sfdp.c
+++ b/hw/block/m25p80_sfdp.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t sfdp_w25q512jv[] = {
     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 define_sfdp_read(w25q512jv);
+
+static const uint8_t sfdp_w25q01jvq[] = {
+    0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff,
+    0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff,
+    0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff,
+    0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x3f,
+    0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb,
+    0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00,
+    0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52,
+    0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00,
+    0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33,
+    0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c,
+    0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+};
+define_sfdp_read(w25q01jvq);
-- 
2.37.3

A mx25l25635f chip model is generally found on these machines. It's
newer and uses 4B opcodes which is better to exercise the support in
the Linux kernel.

Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220722063602.128144-9-clg@kaod.org>
Message-Id: <20221013161241.2805140-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
     amc->soc_name  = "ast2400-a1";
     amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
     amc->fmc_model = "n25q256a";
-    amc->spi_model = "mx25l25635e";
+    amc->spi_model = "mx25l25635f";
     amc->num_cs    = 1;
     amc->i2c_init  = palmetto_bmc_i2c_init;
     mc->default_ram_size       = 256 * MiB;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
     amc->soc_name  = "ast2500-a1";
     amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
     amc->fmc_model = "mx25l25635e";
-    amc->spi_model = "mx25l25635e";
+    amc->spi_model = "mx25l25635f";
     amc->num_cs    = 1;
     amc->i2c_init  = ast2500_evb_i2c_init;
     mc->default_ram_size       = 512 * MiB;
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
     mc->desc       = "OpenPOWER Witherspoon BMC (ARM1176)";
     amc->soc_name  = "ast2500-a1";
     amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
-    amc->fmc_model = "mx25l25635e";
+    amc->fmc_model = "mx25l25635f";
     amc->spi_model = "mx66l1g45g";
     amc->num_cs    = 2;
     amc->i2c_init  = witherspoon_bmc_i2c_init;
-- 
2.37.3

The following changes since commit a95260486aa7e78d7c7194eba65cf03311ad94ad:

Merge tag 'pull-tcg-20231023' of https://gitlab.com/rth7680/qemu into staging (2023-10-23 14:45:46 -0700)

are available in the Git repository at:

https://github.com/legoater/qemu/ tags/pull-aspeed-20231025

for you to fetch changes up to dd41ce7a6f13ad4f45ebaf52b9fa91fe5fc961df:

hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState (2023-10-25 09:52:44 +0200)

----------------------------------------------------------------
aspeed queue:

* Update of Andrew's email
* Split of AspeedSoCState per 2400/2600/10x0

----------------------------------------------------------------
Andrew Jeffery (1):
      MAINTAINERS: aspeed: Update Andrew's email address

Philippe Mathieu-Daudé (11):
      hw/arm/aspeed: Extract code common to all boards to a common file
      hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
      hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
      hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
      hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
      hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
      hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
      hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
      hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
      hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState

MAINTAINERS                               |   2 +-
 include/hw/arm/aspeed_soc.h               |  35 +++++-
 hw/arm/aspeed.c                           | 101 +++++++--------
 hw/arm/aspeed_ast10x0.c                   |  53 ++++----
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 197 +++++++-----------------------
 hw/arm/aspeed_ast2600.c                   |  75 ++++++------
 hw/arm/aspeed_soc_common.c                | 154 +++++++++++++++++++++++
 hw/arm/fby35.c                            |  27 ++--
 hw/arm/meson.build                        |   3 +-
 9 files changed, 363 insertions(+), 284 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (76%)
 create mode 100644 hw/arm/aspeed_soc_common.c

From: Philippe Mathieu-Daudé <philmd@linaro.org>

aspeed_soc.c contains definitions specific to the AST2400
and AST2500 SoCs, but also some definitions for other AST
SoCs: move them to a common file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_soc.c        |  96 -------------------------------
 hw/arm/aspeed_soc_common.c | 114 +++++++++++++++++++++++++++++++++++++
 hw/arm/meson.build         |   1 +
 3 files changed, 115 insertions(+), 96 deletions(-)
 create mode 100644 hw/arm/aspeed_soc_common.c

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_register_types(void)
 };
 
 type_init(aspeed_soc_register_types);
-
-qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
-{
-    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
-}
-
-bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    SerialMM *smm;
-
-    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
-        smm = &s->uart[i];
-
-        /* Chardev property is set by the machine. */
-        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
-        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
-        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
-        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
-        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
-            return false;
-        }
-
-        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
-        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
-    }
-
-    return true;
-}
-
-void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    int i = dev - ASPEED_DEV_UART1;
-
-    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
-    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
-}
-
-/*
- * SDMC should be realized first to get correct RAM size and max size
- * values
- */
-bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
-{
-    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
-    ram_addr_t ram_size, max_ram_size;
-
-    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
-                                        &error_abort);
-    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
-                                            &error_abort);
-
-    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
-                       max_ram_size);
-    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
-
-    /*
-     * Add a memory region beyond the RAM region to let firmwares scan
-     * the address space with load/store and guess how much RAM the
-     * SoC has.
-     */
-    if (ram_size < max_ram_size) {
-        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
-
-        qdev_prop_set_string(dev, "name", "ram-empty");
-        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
-        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
-            return false;
-        }
-
-        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
-                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
-    }
-
-    memory_region_add_subregion(s->memory,
-                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
-    return true;
-}
-
-void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
-{
-    memory_region_add_subregion(s->memory, addr,
-                                sysbus_mmio_get_region(dev, n));
-}
-
-void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
-                                   const char *name, hwaddr addr, uint64_t size)
-{
-    qdev_prop_set_string(DEVICE(dev), "name", name);
-    qdev_prop_set_uint64(DEVICE(dev), "size", size);
-    sysbus_realize(dev, &error_abort);
-
-    memory_region_add_subregion_overlap(s->memory, addr,
-                                        sysbus_mmio_get_region(dev, 0), -1000);
-}
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ASPEED SoC family
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ * Jeremy Kerr <jk@ozlabs.org>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/char/serial.h"
+
+
+qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
+{
+    return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
+}
+
+bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    SerialMM *smm;
+
+    for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+        smm = &s->uart[i];
+
+        /* Chardev property is set by the machine. */
+        qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
+        qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
+        qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
+        qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
+        if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
+            return false;
+        }
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
+        aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
+    }
+
+    return true;
+}
+
+void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    int i = dev - ASPEED_DEV_UART1;
+
+    g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
+    qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
+}
+
+/*
+ * SDMC should be realized first to get correct RAM size and max size
+ * values
+ */
+bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
+{
+    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+    ram_addr_t ram_size, max_ram_size;
+
+    ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
+                                        &error_abort);
+    max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
+                                            &error_abort);
+
+    memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
+                       max_ram_size);
+    memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
+
+    /*
+     * Add a memory region beyond the RAM region to let firmwares scan
+     * the address space with load/store and guess how much RAM the
+     * SoC has.
+     */
+    if (ram_size < max_ram_size) {
+        DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
+
+        qdev_prop_set_string(dev, "name", "ram-empty");
+        qdev_prop_set_uint64(dev, "size", max_ram_size  - ram_size);
+        if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
+            return false;
+        }
+
+        memory_region_add_subregion_overlap(&s->dram_container, ram_size,
+                      sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
+    }
+
+    memory_region_add_subregion(s->memory,
+                      sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
+    return true;
+}
+
+void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
+{
+    memory_region_add_subregion(s->memory, addr,
+                                sysbus_mmio_get_region(dev, n));
+}
+
+void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
+                                   const char *name, hwaddr addr, uint64_t size)
+{
+    qdev_prop_set_string(DEVICE(dev), "name", name);
+    qdev_prop_set_uint64(DEVICE(dev), "size", size);
+    sysbus_realize(dev, &error_abort);
+
+    memory_region_add_subregion_overlap(s->memory, addr,
+                                        sysbus_mmio_get_region(dev, 0), -1000);
+}
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
 arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed_soc.c',
   'aspeed.c',
+  'aspeed_soc_common.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
   'aspeed_eeprom.c',
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
 }
 
-static void aspeed_soc_init(Object *obj)
+static void aspeed_ast2400_soc_init(Object *obj)
 {
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2400_type_info = {
     .name           = "ast2400-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2400_class_init,
 };
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 static const TypeInfo aspeed_soc_ast2500_type_info = {
     .name           = "ast2500-a1",
     .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_soc_init,
+    .instance_init  = aspeed_ast2400_soc_init,
     .instance_size  = sizeof(AspeedSoCState),
     .class_init     = aspeed_soc_ast2500_class_init,
 };
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Keep aspeed_soc_class_init() generic, set the realize handler
to aspeed_ast2400_soc_realize() in each 2400/2500 class_init.

diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_init(Object *obj)
     object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
 }
 
-static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
 {
     int i;
     AspeedSoCState *s = ASPEED_SOC(dev);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
-    dc->realize = aspeed_soc_realize;
-    /* Reason: Uses serial_hds and nd_table in realize() directly */
-    dc->user_creatable = false;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_type_info = {
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2400-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_soc_ast2400_type_info = {
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = aspeed_ast2400_soc_realize;
+    /* Reason: Uses serial_hds and nd_table in realize() directly */
+    dc->user_creatable = false;
 
     sc->name         = "ast2500-a1";
     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

We want to derivate the big AspeedSoCState object in some more
SoC-specific ones. Since the object size will vary, allocate it
dynamically.

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@ struct AspeedMachineState {
     MachineState parent_obj;
     /* Public */
 
-    AspeedSoCState soc;
+    AspeedSoCState *soc;
     MemoryRegion boot_rom;
     bool mmio_exec;
     uint32_t uart_chosen;
@@ -XXX,XX +XXX,XX @@ static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
 static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
                                     uint64_t rom_size)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size,
                            &error_abort);
@@ -XXX,XX +XXX,XX @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
 static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
 {
     AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
-    AspeedSoCState *s = &bmc->soc;
+    AspeedSoCState *s = bmc->soc;
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int uart_chosen = bmc->uart_chosen ? bmc->uart_chosen : amc->uart_default;
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
     int i;
     NICInfo *nd = &nd_table[0];
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-
-    sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    sc = ASPEED_SOC_GET_CLASS(bmc->soc);
 
     /*
      * This will error out if the RAM size is not supported by the
      * memory controller of the SoC.
      */
-    object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
+    object_property_set_uint(OBJECT(bmc->soc), "ram-size", machine->ram_size,
                              &error_fatal);
 
     for (i = 0; i < sc->macs_num; i++) {
         if ((amc->macs_mask & (1 << i)) && nd->used) {
             qemu_check_nic_model(nd, TYPE_FTGMAC100);
-            qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
+            qdev_set_nic_properties(DEVICE(&bmc->soc->ftgmac100[i]), nd);
             nd++;
         }
     }
 
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap1", amc->hw_strap1,
                             &error_abort);
-    object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
+    object_property_set_int(OBJECT(bmc->soc), "hw-strap2", amc->hw_strap2,
                             &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
-    object_property_set_link(OBJECT(&bmc->soc), "dram",
+    object_property_set_link(OBJECT(bmc->soc), "dram",
                              OBJECT(machine->ram), &error_abort);
     if (machine->kernel_filename) {
         /*
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
          * that runs to unlock the SCU. In this case set the default to
          * be unlocked as the kernel expects
          */
-        object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
+        object_property_set_int(OBJECT(bmc->soc), "hw-prot-key",
                                 ASPEED_SCU_PROT_KEY, &error_abort);
     }
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
     if (defaults_enabled()) {
-        aspeed_board_init_flashes(&bmc->soc.fmc,
+        aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs, 0);
-        aspeed_board_init_flashes(&bmc->soc.spi[0],
+        aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               1, amc->num_cs);
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
         amc->i2c_init(bmc);
     }
 
-    for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
-        sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
+    for (i = 0; i < bmc->soc->sdhci.num_slots; i++) {
+        sdhci_attach_drive(&bmc->soc->sdhci.slots[i],
                            drive_get(IF_SD, 0, i));
     }
 
-    if (bmc->soc.emmc.num_slots) {
-        sdhci_attach_drive(&bmc->soc.emmc.slots[0],
-                           drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
+    if (bmc->soc->emmc.num_slots) {
+        sdhci_attach_drive(&bmc->soc->emmc.slots[0],
+                           drive_get(IF_SD, 0, bmc->soc->sdhci.num_slots));
     }
 
     if (!bmc->mmio_exec) {
-        DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0);
+        DeviceState *dev = ssi_get_cs(bmc->soc->fmc.spi, 0);
         BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL;
 
         if (fmc0) {
-            uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+            uint64_t rom_size = memory_region_size(&bmc->soc->spi_boot);
             aspeed_install_boot_rom(bmc, fmc0, rom_size);
         }
     }
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_init(MachineState *machine)
 
 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
 
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /*
      * The quanta-q71l platform expects tmp75s which are compatible with
@@ -XXX,XX +XXX,XX @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
 
 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
 
     smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
@@ -XXX,XX +XXX,XX @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
 
 static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
      * good enough */
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
     at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
@@ -XXX,XX +XXX,XX @@ static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
 
 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* bus 2 : */
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
         {14, LED_COLOR_GREEN, "front-power-3",  GPIO_POLARITY_ACTIVE_LOW},
         {15, LED_COLOR_GREEN, "front-id-5",     GPIO_POLARITY_ACTIVE_LOW},
     };
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     uint8_t *eeprom_buf = g_malloc0(8 * 1024);
     DeviceState *dev;
     LEDState *led;
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     DeviceState *dev;
 
     dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
@@ -XXX,XX +XXX,XX @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     /* The at24c256 */
@@ -XXX,XX +XXX,XX @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *i2c_mux;
 
     at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
@@ -XXX,XX +XXX,XX @@ static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
 
 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[144] = {};
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[13] = {};
     for (int i = 0; i < 13; i++) {
         if ((i == 8) || (i == 11)) {
@@ -XXX,XX +XXX,XX @@ static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
 
 static void fby35_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CBus *i2c[16];
 
     for (int i = 0; i < 16; i++) {
@@ -XXX,XX +XXX,XX @@ static void fby35_i2c_init(AspeedMachineState *bmc)
 
 static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
 }
 
 static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
     I2CSlave *therm_mux, *cpuvr_mux;
 
     /* Create the generic DC-SCM hardware */
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
 static void fby35_reset(MachineState *state, ShutdownCause reason)
 {
     AspeedMachineState *bmc = ASPEED_MACHINE(state);
-    AspeedGPIOState *gpio = &bmc->soc.gpio;
+    AspeedGPIOState *gpio = &bmc->soc->gpio;
 
     qemu_devices_reset(reason);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
     sysclk = clock_new(OBJECT(machine), "SYSCLK");
     clock_set_hz(sysclk, SYSCLK_FRQ);
 
-    object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
-    qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
+    bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+    object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+    object_unref(OBJECT(bmc->soc));
+    qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
 
-    object_property_set_link(OBJECT(&bmc->soc), "memory",
+    object_property_set_link(OBJECT(bmc->soc), "memory",
                              OBJECT(get_system_memory()), &error_abort);
     connect_serial_hds_to_uarts(bmc);
-    qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
+    qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&bmc->soc.fmc,
+    aspeed_board_init_flashes(&bmc->soc->fmc,
                               bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
                               amc->num_cs,
                               0);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[0],
+    aspeed_board_init_flashes(&bmc->soc->spi[0],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, amc->num_cs);
 
-    aspeed_board_init_flashes(&bmc->soc.spi[1],
+    aspeed_board_init_flashes(&bmc->soc->spi[1],
                               bmc->spi_model ? bmc->spi_model : amc->spi_model,
                               amc->num_cs, (amc->num_cs * 2));
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_minibmc_machine_init(MachineState *machine)
 
 static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
 {
-    AspeedSoCState *soc = &bmc->soc;
+    AspeedSoCState *soc = bmc->soc;
 
     /* U10 24C08 connects to SDA/SCL Group 1 by default */
     uint8_t *eeprom_buf = g_malloc0(32 * 1024);
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED10X0_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast10x0.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed10x0SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
+
 struct AspeedSoCClass {
     DeviceClass parent_class;
 
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
     sc->get_irq = aspeed_soc_ast1030_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast1030_type_info = {
-    .name          = "ast1030-a1",
-    .parent        = TYPE_ASPEED_SOC,
-    .instance_size = sizeof(AspeedSoCState),
-    .instance_init = aspeed_soc_ast1030_init,
-    .class_init    = aspeed_soc_ast1030_class_init,
-    .class_size    = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast10x0_types[] = {
+    {
+        .name           = TYPE_ASPEED10X0_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed10x0SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast1030-a1",
+        .parent         = TYPE_ASPEED10X0_SOC,
+        .instance_init  = aspeed_soc_ast1030_init,
+        .class_init     = aspeed_soc_ast1030_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast1030_type_info);
-}
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast10x0_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2600_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++++
 hw/arm/aspeed_ast2600.c     | 26 +++++++++++++-------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2600SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2600_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2600_type_info = {
-    .name           = "ast2600-a3",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_size  = sizeof(AspeedSoCState),
-    .instance_init  = aspeed_soc_ast2600_init,
-    .class_init     = aspeed_soc_ast2600_class_init,
-    .class_size     = sizeof(AspeedSoCClass),
+static const TypeInfo aspeed_soc_ast2600_types[] = {
+    {
+        .name           = TYPE_ASPEED2600_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_size  = sizeof(Aspeed2600SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2600-a3",
+        .parent         = TYPE_ASPEED2600_SOC,
+        .instance_init  = aspeed_soc_ast2600_init,
+        .class_init     = aspeed_soc_ast2600_class_init,
+    },
 };
 
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_ast2600_type_info);
-};
-
-type_init(aspeed_soc_register_types)
+DEFINE_TYPES(aspeed_soc_ast2600_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

TYPE_ASPEED2400_SOC inherits from TYPE_ASPEED_SOC.
In few commits we'll add more fields, but to keep
review process simple, don't add any yet.

TYPE_ASPEED_SOC is common to various Aspeed SoCs,
define it in aspeed_soc_common.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  7 +++++
 hw/arm/aspeed_soc.c         | 61 +++++++++++--------------------------
 hw/arm/aspeed_soc_common.c  | 29 ++++++++++++++++++
 3 files changed, 53 insertions(+), 44 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
 #define TYPE_ASPEED_SOC "aspeed-soc"
 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
 
+struct Aspeed2400SoCState {
+    AspeedSoCState parent;
+};
+
+#define TYPE_ASPEED2400_SOC "aspeed2400-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
+
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
 };
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
                        aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
 }
-static Property aspeed_soc_properties[] = {
-    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
-                     MemoryRegion *),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void aspeed_soc_class_init(ObjectClass *oc, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(oc);
-
-    device_class_set_props(dc, aspeed_soc_properties);
-}
-
-static const TypeInfo aspeed_soc_type_info = {
-    .name           = TYPE_ASPEED_SOC,
-    .parent         = TYPE_DEVICE,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_size     = sizeof(AspeedSoCClass),
-    .class_init     = aspeed_soc_class_init,
-    .abstract       = true,
-};
 
 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 {
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2400_type_info = {
-    .name           = "ast2400-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2400_class_init,
-};
-
 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 {
     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     sc->get_irq      = aspeed_soc_ast2400_get_irq;
 }
 
-static const TypeInfo aspeed_soc_ast2500_type_info = {
-    .name           = "ast2500-a1",
-    .parent         = TYPE_ASPEED_SOC,
-    .instance_init  = aspeed_ast2400_soc_init,
-    .instance_size  = sizeof(AspeedSoCState),
-    .class_init     = aspeed_soc_ast2500_class_init,
-};
-static void aspeed_soc_register_types(void)
-{
-    type_register_static(&aspeed_soc_type_info);
-    type_register_static(&aspeed_soc_ast2400_type_info);
-    type_register_static(&aspeed_soc_ast2500_type_info);
+static const TypeInfo aspeed_soc_ast2400_types[] = {
+    {
+        .name           = TYPE_ASPEED2400_SOC,
+        .parent         = TYPE_ASPEED_SOC,
+        .instance_init  = aspeed_ast2400_soc_init,
+        .instance_size  = sizeof(Aspeed2400SoCState),
+        .abstract       = true,
+    }, {
+        .name           = "ast2400-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2400_class_init,
+    }, {
+        .name           = "ast2500-a1",
+        .parent         = TYPE_ASPEED2400_SOC,
+        .class_init     = aspeed_soc_ast2500_class_init,
+    },
 };
 
-type_init(aspeed_soc_register_types);
+DEFINE_TYPES(aspeed_soc_ast2400_types)
diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/qdev-properties.h"
 #include "hw/misc/unimp.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/char/serial.h"
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
     memory_region_add_subregion_overlap(s->memory, addr,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
+
+static Property aspeed_soc_properties[] = {
+    DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    device_class_set_props(dc, aspeed_soc_properties);
+}
+
+static const TypeInfo aspeed_soc_types[] = {
+    {
+        .name           = TYPE_ASPEED_SOC,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(AspeedSoCState),
+        .class_size     = sizeof(AspeedSoCClass),
+        .class_init     = aspeed_soc_class_init,
+        .abstract       = true,
+    },
+};
+
+DEFINE_TYPES(aspeed_soc_types)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_soc_common.c
+++ b/hw/arm/aspeed_soc_common.c
@@ -XXX,XX +XXX,XX @@ void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
                                         sysbus_mmio_get_region(dev, 0), -1000);
 }
 
+static void aspeed_soc_realize(DeviceState *dev, Error **errp)
+{
+    AspeedSoCState *s = ASPEED_SOC(dev);
+
+    if (!s->memory) {
+        error_setg(errp, "'memory' link is not set");
+        return;
+    }
+}
+
 static Property aspeed_soc_properties[] = {
     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
                      MemoryRegion *),
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
 
+    dc->realize = aspeed_soc_realize;
     device_class_set_props(dc, aspeed_soc_properties);
 }
 
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-M core is specific to the Aspeed 10x0 series,
remove it from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  5 ++---
 hw/arm/aspeed_ast10x0.c     | 27 +++++++++++++++------------
 hw/arm/fby35.c              | 13 ++++++++-----
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #define ASPEED_JTAG_NUM  2
 
 struct AspeedSoCState {
-    /*< private >*/
     DeviceState parent;
 
-    /*< public >*/
     ARMCPU cpu[ASPEED_CPUS_NUM];
     A15MPPrivState     a7mpcore;
-    ARMv7MState        armv7m;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 
 struct Aspeed10x0SoCState {
     AspeedSoCState parent;
+
+    ARMv7MState armv7m;
 };
 
 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast1030_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast1030_init(Object *obj)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     char socname[8];
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
         g_assert_not_reached();
     }
 
-    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+    object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
 
     s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
 
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_init(Object *obj)
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
 {
+    Aspeed10x0SoCState *a = ASPEED10X0_SOC(dev_soc);
     AspeedSoCState *s = ASPEED_SOC(dev_soc);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     DeviceState *armv7m;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
                                   0x40000);
 
     /* AST1030 CPU Core */
-    armv7m = DEVICE(&s->armv7m);
+    armv7m = DEVICE(&a->armv7m);
     qdev_prop_set_uint32(armv7m, "num-irq", 256);
     qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
     qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
-    object_property_set_link(OBJECT(&s->armv7m), "memory",
+    object_property_set_link(OBJECT(&a->armv7m), "memory",
                              OBJECT(s->memory), &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
 
     /* Internal SRAM */
     sram_name = g_strdup_printf("aspeed.sram.%d",
-                                CPU(s->armv7m.cpu)->cpu_index);
+                                CPU(a->armv7m.cpu)->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err != NULL) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST1030 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
+        qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m),
                                         sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST1030 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
      * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->armv7m),
+                       qdev_get_gpio_in(DEVICE(&a->armv7m),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* UART */
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     Clock *bic_sysclk;
 
     AspeedSoCState bmc;
-    AspeedSoCState bic;
+    Aspeed10x0SoCState bic;
 
     bool mmio_exec;
 };
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
 
 static void fby35_bic_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     s->bic_sysclk = clock_new(OBJECT(s), "SYSCLK");
     clock_set_hz(s->bic_sysclk, 200000000ULL);
 
     object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
+    soc = ASPEED_SOC(&s->bic);
 
     memory_region_init(&s->bic_memory, OBJECT(&s->bic), "bic-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bic_init(Fby35State *s)
     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                              &error_abort);
-    aspeed_soc_uart_set_chr(&s->bic, ASPEED_DEV_UART5, serial_hd(1));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(1));
     qdev_realize(DEVICE(&s->bic), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bic.fmc, "sst25vf032b", 2, 2);
-    aspeed_board_init_flashes(&s->bic.spi[0], "sst25vf032b", 2, 4);
-    aspeed_board_init_flashes(&s->bic.spi[1], "sst25vf032b", 2, 6);
+    aspeed_board_init_flashes(&soc->fmc, "sst25vf032b", 2, 2);
+    aspeed_board_init_flashes(&soc->spi[0], "sst25vf032b", 2, 4);
+    aspeed_board_init_flashes(&soc->spi[1], "sst25vf032b", 2, 6);
 }
 
 static void fby35_init(MachineState *machine)
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The v7-A cluster is specific to the Aspeed 2600 series,
remove it from the common AspeedSoCState.

The ARM cores belong to the MP cluster, but the array
is currently used by TYPE_ASPEED2600_SOC. We'll clean
that soon, but for now keep it in Aspeed2600SoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  4 ++-
 hw/arm/aspeed_ast2600.c     | 49 ++++++++++++++++++++-----------------
 hw/arm/fby35.c              | 14 ++++++-----
 3 files changed, 37 insertions(+), 30 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedSoCState {
     DeviceState parent;
 
     ARMCPU cpu[ASPEED_CPUS_NUM];
-    A15MPPrivState     a7mpcore;
     MemoryRegion *memory;
     MemoryRegion *dram_mr;
     MemoryRegion dram_container;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 
 struct Aspeed2600SoCState {
     AspeedSoCState parent;
+
+    A15MPPrivState a7mpcore;
+    ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 };
 
 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = {
 
 static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(s);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 
-    return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
+    return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]);
 }
 
 static void aspeed_soc_ast2600_init(Object *obj)
 {
+    Aspeed2600SoCState *a = ASPEED2600_SOC(obj);
     AspeedSoCState *s = ASPEED_SOC(obj);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     int i;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     }
 
     for (i = 0; i < sc->num_cpus; i++) {
-        object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
+        object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type);
     }
 
     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj)
     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
                               "hw-prot-key");
 
-    object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
+    object_initialize_child(obj, "a7mpcore", &a->a7mpcore,
                             TYPE_A15MPCORE_PRIV);
 
     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_calc_affinity(int cpu)
 static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
 {
     int i;
+    Aspeed2600SoCState *a = ASPEED2600_SOC(dev);
     AspeedSoCState *s = ASPEED_SOC(dev);
     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     /* CPU */
     for (i = 0; i < sc->num_cpus; i++) {
         if (sc->num_cpus > 1) {
-            object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+            object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar",
                                     ASPEED_A7MPCORE_ADDR, &error_abort);
         }
-        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+        object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity",
                                 aspeed_calc_affinity(i), &error_abort);
 
-        object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
+        object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false,
                                 &error_abort);
-        object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false,
+        object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false,
                                 &error_abort);
-        object_property_set_link(OBJECT(&s->cpu[i]), "memory",
+        object_property_set_link(OBJECT(&a->cpu[i]), "memory",
                                  OBJECT(s->memory), &error_abort);
 
-        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+        if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) {
             return;
         }
     }
 
     /* A7MPCORE */
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
+    object_property_set_int(OBJECT(&a->a7mpcore), "num-irq",
                             ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
                             &error_abort);
 
-    sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
-    aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
+    sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort);
+    aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
 
     for (i = 0; i < sc->num_cpus; i++) {
-        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
-        DeviceState  *d   = DEVICE(&s->cpu[i]);
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore);
+        DeviceState  *d   = DEVICE(&a->cpu[i]);
 
         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
         sysbus_connect_irq(sbd, i, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
 
     /* SRAM */
-    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
+    sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
     memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
     if (err) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
     for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I2C] + i);
         /* The AST2600 I2C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
      * offset 0.
      */
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
 
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
-                       qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                       qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
 
     /* HACE */
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
     aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
     for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
-        irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+        irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore),
                                sc->irqmap[ASPEED_DEV_I3C] + i);
         /* The AST2600 I3C controller has one IRQ per bus. */
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -XXX,XX +XXX,XX @@ struct Fby35State {
     MemoryRegion bic_memory;
     Clock *bic_sysclk;
 
-    AspeedSoCState bmc;
+    Aspeed2600SoCState bmc;
     Aspeed10x0SoCState bic;
 
     bool mmio_exec;
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, MemoryRegion *mr,
 
 static void fby35_bmc_init(Fby35State *s)
 {
+    AspeedSoCState *soc;
+
     object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+    soc = ASPEED_SOC(&s->bmc);
 
     memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory",
                        UINT64_MAX);
@@ -XXX,XX +XXX,XX @@ static void fby35_bmc_init(Fby35State *s)
                             &error_abort);
     object_property_set_int(OBJECT(&s->bmc), "hw-strap2", 0x00000003,
                             &error_abort);
-    aspeed_soc_uart_set_chr(&s->bmc, ASPEED_DEV_UART5, serial_hd(0));
+    aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART5, serial_hd(0));
     qdev_realize(DEVICE(&s->bmc), NULL, &error_abort);
 
-    aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0);
+    aspeed_board_init_flashes(&soc->fmc, "n25q00", 2, 0);
 
     /* Install first FMC flash content as a boot rom. */
     if (!s->mmio_exec) {
         DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
 
         if (mtd0) {
-            AspeedSoCState *bmc = &s->bmc;
-            uint64_t rom_size = memory_region_size(&bmc->spi_boot);
+            uint64_t rom_size = memory_region_size(&soc->spi_boot);
 
             memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_rom",
                                    rom_size, &error_abort);
-            memory_region_add_subregion_overlap(&bmc->spi_boot_container, 0,
+            memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
                                                 &s->bmc_boot_rom, 1);
 
             fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom,
-- 
2.41.0

From: Philippe Mathieu-Daudé <philmd@linaro.org>

The ARM array and VIC peripheral are only used by the
2400 series, remove them from the common AspeedSoCState.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h               |  5 +++--
 hw/arm/{aspeed_soc.c => aspeed_ast2400.c} | 27 +++++++++++++----------
 hw/arm/meson.build                        |  2 +-
 3 files changed, 19 insertions(+), 15 deletions(-)
 rename hw/arm/{aspeed_soc.c => aspeed_ast2400.c} (95%)